2 * MATRIX VISION GmbH mvBlueLYNX-X
4 * Derived from omap3_beagle.h:
5 * (C) Copyright 2006-2008
7 * Richard Woodruff <r-woodruff2@ti.com>
8 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Configuration settings for the TI OMAP3530 Beagle board.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 * High Level Configuration Options
37 #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
38 #define CONFIG_OMAP 1 /* in a TI OMAP core */
39 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
40 #define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
41 #define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
42 #define CONFIG_OMAP_GPIO
44 #define CONFIG_SDRC /* The chip has SDRC controller */
46 #include <asm/arch/cpu.h> /* get chip and board defs */
47 #include <asm/arch/omap3.h>
50 * Display CPU and Board information
52 #define CONFIG_DISPLAY_CPUINFO 1
53 #define CONFIG_DISPLAY_BOARDINFO 1
56 #define V_OSCK 26000000 /* Clock output from T2 */
57 #define V_SCLK (V_OSCK >> 1)
59 #undef CONFIG_USE_IRQ /* no support for IRQs */
60 #define CONFIG_MISC_INIT_R
62 #define CONFIG_OF_LIBFDT 1
64 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
65 #define CONFIG_SETUP_MEMORY_TAGS 1
66 #define CONFIG_INITRD_TAG 1
67 #define CONFIG_REVISION_TAG 1
68 #define CONFIG_SERIAL_TAG 1
71 * Size of malloc() pool
73 #define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */
75 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
82 * NS16550 Configuration
84 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
86 #define CONFIG_SYS_NS16550
87 #define CONFIG_SYS_NS16550_SERIAL
88 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
89 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
92 * select serial console configuration
94 #define CONFIG_CONS_INDEX 3
95 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
96 #define CONFIG_SERIAL3 3 /* UART3 */
98 #define CONFIG_BAUDRATE 115200
99 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
101 #define CONFIG_GENERIC_MMC 1
103 #define CONFIG_OMAP_HSMMC 1
104 #define CONFIG_DOS_PARTITION 1
107 #define CONFIG_MUSB_UDC 1
108 #define CONFIG_USB_OMAP3 1
109 #define CONFIG_TWL4030_USB 1
111 /* USB device configuration */
112 #define CONFIG_USB_DEVICE 1
113 #define CONFIG_USB_TTY 1
114 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
115 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
116 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
117 #define CONFIG_USBD_VENDORID 0x164c
118 #define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201
119 #define CONFIG_USBD_PRODUCTID_CDCACM 0x0201
120 #define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH"
121 #define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X"
123 /* no FLASH available */
124 #define CONFIG_SYS_NO_FLASH
126 /* commands to include */
127 #include <config_cmd_default.h>
129 #define CONFIG_CMD_CACHE
130 #define CONFIG_CMD_EXT2 /* EXT2 Support */
131 #define CONFIG_CMD_FAT /* FAT support */
132 #define CONFIG_CMD_I2C /* I2C serial bus support */
133 #define CONFIG_CMD_MMC /* MMC support */
134 #define CONFIG_CMD_EEPROM
135 #define CONFIG_CMD_IMI /* iminfo */
136 #undef CONFIG_CMD_IMLS /* List all found images */
137 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
138 #define CONFIG_CMD_NFS /* NFS support */
139 #define CONFIG_CMD_DHCP
140 #define CONFIG_CMD_PING
141 #define CONFIG_CMD_FPGA
143 #define CONFIG_HARD_I2C 1
144 #define CONFIG_SYS_I2C_SPEED 100000
145 #define CONFIG_SYS_I2C_SLAVE 0
146 #define CONFIG_SYS_I2C_BUS 0 /* This isn't used anywhere ?? */
147 #define CONFIG_SYS_I2C_BUS_SELECT 1 /* This isn't used anywhere ?? */
148 #define CONFIG_DRIVER_OMAP34XX_I2C 1
149 #define CONFIG_I2C_MULTI_BUS 1
154 #define CONFIG_TWL4030_POWER 1
156 /* Environment information */
157 #undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
158 #define CONFIG_BOOTDELAY 3
160 #define CONFIG_EXTRA_ENV_SETTINGS \
161 "loadaddr=0x82000000\0" \
163 "console=ttyO2,115200n8\0" \
166 "dvimode=1024x768-24@60\0" \
167 "defaultdisplay=dvi\0" \
168 "fpgafilename=mvbluelynx_x.rbf\0" \
169 "loadfpga=if fatload mmc ${mmcdev} ${loadaddr} ${fpgafilename}; then " \
170 "fpga load 0 ${loadaddr} ${filesize}; " \
173 "mmcroot=/dev/mmcblk0p2 rw\0" \
174 "mmcrootfstype=ext3 rootwait\0" \
175 "mmcargs=setenv bootargs console=${console} " \
176 "mpurate=${mpurate} " \
178 "omapfb.mode=dvi:${dvimode} " \
180 "omapdss.def_disp=${defaultdisplay} " \
182 "rootfstype=${mmcrootfstype} " \
183 "${cmdline_suffix}\0" \
184 "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
185 "importbootenv=echo Importing environment from mmc ...; " \
186 "env import -t $loadaddr $filesize\0" \
187 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
188 "mmcboot=echo Booting from mmc ...; " \
190 "bootm ${loadaddr}\0" \
192 "echo Trying mmc${mmcdev}; " \
193 "mmc dev ${mmcdev}; " \
194 "if mmc rescan; then " \
195 "setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
196 "echo SD/MMC found on device ${mmcdev};" \
197 "if run loadbootenv; then " \
198 "echo Loading boot environment from mmc${mmcdev}; " \
199 "run importbootenv; " \
202 "if test -n $uenvcmd; then " \
203 "echo Running uenvcmd ...;" \
206 "if run loaduimage; then " \
211 #define CONFIG_BOOTCOMMAND \
213 "run mmcbootcmd || " \
218 #define CONFIG_AUTO_COMPLETE 1
220 * Miscellaneous configurable options
222 #define CONFIG_SYS_LONGHELP /* undef to save memory */
223 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
224 #define CONFIG_SYS_PROMPT "mvblx # "
225 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
226 /* Print Buffer Size */
227 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
228 sizeof(CONFIG_SYS_PROMPT) + 16)
229 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
230 /* Boot Argument Buffer Size */
231 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
233 #define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */
234 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */
235 #define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */
236 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
238 /* default load address */
239 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
242 * OMAP3 has 12 GP timers, they can be driven by the system clock
243 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
244 * This rate is divided by a local divisor.
246 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
247 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
248 #define CONFIG_SYS_HZ 1000
250 /*-----------------------------------------------------------------------
253 * The stack sizes are set up in start.S using the settings below
255 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
257 /*-----------------------------------------------------------------------
258 * Physical Memory Map
260 #define CONFIG_NR_DRAM_BANKS 1
261 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
262 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
263 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
265 #define CONFIG_ENV_IS_NOWHERE 1
267 /*----------------------------------------------------------------------------
268 * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
269 *----------------------------------------------------------------------------
271 #if defined(CONFIG_CMD_NET)
272 #define CONFIG_SMC911X 1
273 #define CONFIG_SMC911X_32_BIT
274 #define CONFIG_SMC911X_BASE 0x2C000000
275 #endif /* (CONFIG_CMD_NET) */
277 #define CONFIG_FPGA_COUNT 1
278 #define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
279 #define CONFIG_FPGA_ALTERA
280 #define CONFIG_FPGA_CYCLON2
281 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
282 #define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
284 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
285 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
286 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */
287 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
288 #define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
289 #define CONFIG_ID_EEPROM
290 #define CONFIG_SYS_EEPROM_BUS_NUM 2
292 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
293 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
294 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
295 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
296 CONFIG_SYS_INIT_RAM_SIZE - \
297 GENERATED_GBL_DATA_SIZE)
299 #define CONFIG_OMAP3_SPI
301 #define CONFIG_SYS_CACHELINE_SIZE 64
303 #endif /* __CONFIG_H */