include/configs/pm9261.h

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  * Ilko Iliev <www.ronetix.at>
   6  *
   7  * Configuation settings for the RONETIX PM9261 board.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * SoC must be defined first, before hardware.h is included.
  17  * In this case SoC is defined in boards.cfg.
  18  */
  19
  20 #include <asm/hardware.h>
  21 /* ARM asynchronous clock */
  22
  23 #define CONFIG_SYS_GENERIC_BOARD
  24
  25 #define CONFIG_DISPLAY_BOARDINFO
  26
  27 #define MASTER_PLL_DIV          15
  28 #define MASTER_PLL_MUL          162
  29 #define MAIN_PLL_DIV            2
  30 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
  31 #define CONFIG_SYS_AT91_MAIN_CLOCK      18432000
  32
  33 #define CONFIG_SYS_AT91_CPU_NAME        "AT91SAM9261"
  34 #define CONFIG_PM9261           1       /* on a Ronetix PM9261 Board    */
  35 #define CONFIG_ARCH_CPU_INIT
  36 #define CONFIG_SYS_TEXT_BASE    0
  37
  38 #define MACH_TYPE_PM9261        1187
  39 #define CONFIG_MACH_TYPE        MACH_TYPE_PM9261
  40
  41 /* clocks */
  42 /* CKGR_MOR - enable main osc. */
  43 #define CONFIG_SYS_MOR_VAL                                              \
  44                 (AT91_PMC_MOR_MOSCEN |                                  \
  45                  (255 << 8))            /* Main Oscillator Start-up Time */
  46 #define CONFIG_SYS_PLLAR_VAL                                            \
  47                 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
  48                  AT91_PMC_PLLXR_OUT(3) |                                                \
  49                  ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  50
  51 /* PCK/2 = MCK Master Clock from PLLA */
  52 #define CONFIG_SYS_MCKR1_VAL            \
  53                 (AT91_PMC_MCKR_CSS_SLOW |       \
  54                  AT91_PMC_MCKR_PRES_1 | \
  55                  AT91_PMC_MCKR_MDIV_2)
  56
  57 /* PCK/2 = MCK Master Clock from PLLA */
  58 #define CONFIG_SYS_MCKR2_VAL            \
  59                 (AT91_PMC_MCKR_CSS_PLLA |       \
  60                  AT91_PMC_MCKR_PRES_1 | \
  61                  AT91_PMC_MCKR_MDIV_2)
  62
  63 /* define PDC[31:16] as DATA[31:16] */
  64 #define CONFIG_SYS_PIOC_PDR_VAL1        0xFFFF0000
  65 /* no pull-up for D[31:16] */
  66 #define CONFIG_SYS_PIOC_PPUDR_VAL       0xFFFF0000
  67
  68 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
  69 #define CONFIG_SYS_MATRIX_EBICSA_VAL            \
  70         (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
  71
  72 /* SDRAM */
  73 /* SDRAMC_MR Mode register */
  74 #define CONFIG_SYS_SDRC_MR_VAL1         AT91_SDRAMC_MODE_NORMAL
  75 /* SDRAMC_TR - Refresh Timer register */
  76 #define CONFIG_SYS_SDRC_TR_VAL1         0x13C
  77 /* SDRAMC_CR - Configuration register*/
  78 #define CONFIG_SYS_SDRC_CR_VAL                                                  \
  79                 (AT91_SDRAMC_NC_9 |                                             \
  80                  AT91_SDRAMC_NR_13 |                                            \
  81                  AT91_SDRAMC_NB_4 |                                             \
  82                  AT91_SDRAMC_CAS_3 |                                            \
  83                  AT91_SDRAMC_DBW_32 |                                           \
  84                  (1 <<  8) |            /* Write Recovery Delay */              \
  85                  (7 << 12) |            /* Row Cycle Delay */                   \
  86                  (3 << 16) |            /* Row Precharge Delay */               \
  87                  (2 << 20) |            /* Row to Column Delay */               \
  88                  (5 << 24) |            /* Active to Precharge Delay */         \
  89                  (1 << 28))             /* Exit Self Refresh to Active Delay */
  90
  91 /* Memory Device Register -> SDRAM */
  92 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
  93 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
  94 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
  95 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
  96 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
  97 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
  98 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
  99 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
 100 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
 101 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
 102 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
 103 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
 104 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
 105 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
 106 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
 107 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
 108 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
 109 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
 110
 111 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
 112 #define CONFIG_SYS_SMC0_SETUP0_VAL                                      \
 113                 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
 114                  AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
 115 #define CONFIG_SYS_SMC0_PULSE0_VAL                                      \
 116                 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
 117                  AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
 118 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
 119                 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
 120 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
 121                 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
 122                  AT91_SMC_MODE_DBW_16 |                         \
 123                  AT91_SMC_MODE_TDF |                            \
 124                  AT91_SMC_MODE_TDF_CYCLE(6))
 125
 126 /* user reset enable */
 127 #define CONFIG_SYS_RSTC_RMR_VAL                 \
 128                 (AT91_RSTC_KEY |                \
 129                 AT91_RSTC_CR_PROCRST |          \
 130                 AT91_RSTC_MR_ERSTL(1) | \
 131                 AT91_RSTC_MR_ERSTL(2))
 132
 133 /* Disable Watchdog */
 134 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
 135                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
 136                  AT91_WDT_MR_WDV(0xfff) |                                       \
 137                  AT91_WDT_MR_WDDIS |                            \
 138                  AT91_WDT_MR_WDD(0xfff))
 139
 140 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs */
 141 #define CONFIG_SETUP_MEMORY_TAGS 1
 142 #define CONFIG_INITRD_TAG       1
 143
 144 #undef CONFIG_SKIP_LOWLEVEL_INIT
 145 #define CONFIG_BOARD_EARLY_INIT_F
 146
 147 /*
 148  * Hardware drivers
 149  */
 150 #define CONFIG_AT91_GPIO        1
 151 #define CONFIG_ATMEL_USART      1
 152 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
 153 #define CONFIG_USART_ID                 ATMEL_ID_SYS
 154
 155 /* LCD */
 156 #define CONFIG_LCD                      1
 157 #define LCD_BPP                         LCD_COLOR8
 158 #define CONFIG_LCD_LOGO                 1
 159 #undef LCD_TEST_PATTERN
 160 #define CONFIG_LCD_INFO                 1
 161 #define CONFIG_LCD_INFO_BELOW_LOGO      1
 162 #define CONFIG_SYS_WHITE_ON_BLACK       1
 163 #define CONFIG_ATMEL_LCD                1
 164 #define CONFIG_ATMEL_LCD_BGR555         1
 165 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
 166
 167 /* LED */
 168 #define CONFIG_AT91_LED
 169 #define CONFIG_RED_LED          GPIO_PIN_PC(12)
 170 #define CONFIG_GREEN_LED        GPIO_PIN_PC(13)
 171 #define CONFIG_YELLOW_LED       GPIO_PIN_PC(15)
 172
 173 #define CONFIG_BOOTDELAY        3
 174
 175 /*
 176  * BOOTP options
 177  */
 178 #define CONFIG_BOOTP_BOOTFILESIZE       1
 179 #define CONFIG_BOOTP_BOOTPATH           1
 180 #define CONFIG_BOOTP_GATEWAY            1
 181 #define CONFIG_BOOTP_HOSTNAME           1
 182
 183 /*
 184  * Command line configuration.
 185  */
 186 #include <config_cmd_default.h>
 187 #undef CONFIG_CMD_BDI
 188 #undef CONFIG_CMD_IMI
 189 #undef CONFIG_CMD_FPGA
 190 #undef CONFIG_CMD_LOADS
 191 #undef CONFIG_CMD_IMLS
 192
 193 #define CONFIG_CMD_CACHE
 194 #define CONFIG_CMD_PING         1
 195 #define CONFIG_CMD_DHCP         1
 196 #define CONFIG_CMD_NAND         1
 197 #define CONFIG_CMD_USB          1
 198
 199 /* SDRAM */
 200 #define CONFIG_NR_DRAM_BANKS                    1
 201 #define PHYS_SDRAM                              0x20000000
 202 #define PHYS_SDRAM_SIZE                         0x04000000      /* 64 megs */
 203
 204 /* DataFlash */
 205 #define CONFIG_ATMEL_DATAFLASH_SPI
 206 #define CONFIG_HAS_DATAFLASH
 207 #define CONFIG_SYS_MAX_DATAFLASH_BANKS          1
 208 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000      /* CS0 */
 209 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3     0xD0000000      /* CS3 */
 210 #define AT91_SPI_CLK                            15000000
 211 #define DATAFLASH_TCSS                          (0x1a << 16)
 212 #define DATAFLASH_TCHS                          (0x1 << 24)
 213
 214 /* NAND flash */
 215 #define CONFIG_NAND_ATMEL
 216 #define CONFIG_SYS_MAX_NAND_DEVICE              1
 217 #define CONFIG_SYS_NAND_BASE                    0x40000000
 218 #define CONFIG_SYS_NAND_DBW_8                   1
 219 /* our ALE is AD22 */
 220 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 22)
 221 /* our CLE is AD21 */
 222 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 21)
 223 #define CONFIG_SYS_NAND_ENABLE_PIN              GPIO_PIN_PC(14)
 224 #define CONFIG_SYS_NAND_READY_PIN               GPIO_PIN_PA(16)
 225
 226 /* NOR flash */
 227 #define CONFIG_SYS_FLASH_CFI                    1
 228 #define CONFIG_FLASH_CFI_DRIVER                 1
 229 #define PHYS_FLASH_1                            0x10000000
 230 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
 231 #define CONFIG_SYS_MAX_FLASH_SECT               256
 232 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 233
 234 /* Ethernet */
 235 #define CONFIG_DRIVER_DM9000                    1
 236 #define CONFIG_DM9000_BASE                      0x30000000
 237 #define DM9000_IO                               CONFIG_DM9000_BASE
 238 #define DM9000_DATA                             (CONFIG_DM9000_BASE + 4)
 239 #define CONFIG_DM9000_USE_16BIT                 1
 240 #define CONFIG_NET_RETRY_COUNT                  20
 241 #define CONFIG_RESET_PHY_R                      1
 242
 243 /* USB */
 244 #define CONFIG_USB_ATMEL
 245 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 246 #define CONFIG_USB_OHCI_NEW                     1
 247 #define CONFIG_DOS_PARTITION                    1
 248 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
 249 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00500000
 250 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9261"
 251 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 252 #define CONFIG_USB_STORAGE                      1
 253
 254 #define CONFIG_SYS_LOAD_ADDR                    0x22000000
 255
 256 #define CONFIG_SYS_MEMTEST_START                PHYS_SDRAM
 257 #define CONFIG_SYS_MEMTEST_END                  0x23e00000
 258
 259 #undef CONFIG_SYS_USE_DATAFLASH_CS0
 260 #undef CONFIG_SYS_USE_NANDFLASH
 261 #define CONFIG_SYS_USE_FLASH    1
 262
 263 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0
 264
 265 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 266 #define CONFIG_ENV_IS_IN_DATAFLASH      1
 267 #define CONFIG_SYS_MONITOR_BASE         \
 268                 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
 269 #define CONFIG_ENV_OFFSET       0x4200
 270 #define CONFIG_ENV_ADDR         \
 271                 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 272 #define CONFIG_ENV_SIZE         0x4200
 273 #define CONFIG_BOOTCOMMAND      "cp.b 0xC0042000 0x22000000 0x210000; bootm"
 274 #define CONFIG_BOOTARGS         "console=ttyS0,115200 "                 \
 275                                 "root=/dev/mtdblock0 "                  \
 276                                 "mtdparts=atmel_nand:-(root) "          \
 277                                 "rw rootfstype=jffs2"
 278
 279 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
 280
 281 /* bootstrap + u-boot + env + linux in nandflash */
 282 #define CONFIG_ENV_IS_IN_NAND           1
 283 #define CONFIG_ENV_OFFSET               0x60000
 284 #define CONFIG_ENV_OFFSET_REDUND        0x80000
 285 #define CONFIG_ENV_SIZE                 0x20000         /* 1 sector = 128 kB */
 286 #define CONFIG_BOOTCOMMAND      "nand read 0x22000000 0xA0000 0x200000; bootm"
 287 #define CONFIG_BOOTARGS         "console=ttyS0,115200 "                 \
 288                                 "root=/dev/mtdblock5 "                  \
 289                                 "mtdparts=atmel_nand:128k(bootstrap)ro,"        \
 290                                 "256k(uboot)ro,128k(env1)ro,"           \
 291                                 "128k(env2)ro,2M(linux),-(root) "       \
 292                                 "rw rootfstype=jffs2"
 293
 294 #elif defined (CONFIG_SYS_USE_FLASH)
 295
 296 #define CONFIG_ENV_IS_IN_FLASH  1
 297 #define CONFIG_ENV_OFFSET       0x40000
 298 #define CONFIG_ENV_SECT_SIZE    0x10000
 299 #define CONFIG_ENV_SIZE         0x10000
 300 #define CONFIG_ENV_OVERWRITE    1
 301
 302 /* JFFS Partition offset set */
 303 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
 304 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 305
 306 /* 512k reserved for u-boot */
 307 #define CONFIG_SYS_JFFS2_FIRST_SECTOR   11
 308
 309 #define CONFIG_BOOTCOMMAND      "run flashboot"
 310
 311 #define MTDIDS_DEFAULT          "nor0=physmap-flash.0,nand0=nand"
 312 #define MTDPARTS_DEFAULT                \
 313         "mtdparts=physmap-flash.0:"     \
 314                 "256k(u-boot)ro,"       \
 315                 "64k(u-boot-env)ro,"    \
 316                 "1408k(kernel),"        \
 317                 "-(rootfs);"            \
 318         "nand:-(nand)"
 319
 320 #define CONFIG_CON_ROT "fbcon=rotate:3 "
 321 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT
 322
 323 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 324         "mtdids=" MTDIDS_DEFAULT "\0"                           \
 325         "mtdparts=" MTDPARTS_DEFAULT "\0"                       \
 326         "partition=nand0,0\0"                                   \
 327         "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
 328         "nfsargs=setenv bootargs root=/dev/nfs rw "             \
 329                 CONFIG_CON_ROT                                  \
 330                 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
 331         "addip=setenv bootargs $(bootargs) "                    \
 332                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
 333                 ":$(hostname):eth0:off\0"                       \
 334         "ramboot=tftpboot 0x22000000 vmImage;"                  \
 335                 "run ramargs;run addip;bootm 22000000\0"        \
 336         "nfsboot=tftpboot 0x22000000 vmImage;"                  \
 337                 "run nfsargs;run addip;bootm 22000000\0"        \
 338         "flashboot=run ramargs;run addip;bootm 0x10050000\0"    \
 339         ""
 340 #else
 341 #error "Undefined memory device"
 342 #endif
 343
 344 #define CONFIG_BAUDRATE                 115200
 345
 346 #define CONFIG_SYS_PROMPT               "pm9261> "
 347 #define CONFIG_SYS_CBSIZE               256
 348 #define CONFIG_SYS_MAXARGS              16
 349 #define CONFIG_SYS_PBSIZE               \
 350                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 351 #define CONFIG_SYS_LONGHELP             1
 352 #define CONFIG_CMDLINE_EDITING  1
 353
 354 /*
 355  * Size of malloc() pool
 356  */
 357 #define CONFIG_SYS_MALLOC_LEN           \
 358                 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
 359
 360 #define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM
 361 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 362                                 GENERATED_GBL_DATA_SIZE)
 363
 364 #endif