include/configs/pxa255_idp.h

   1 /*
   2  * (C) Copyright 2002
   3  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   4  *
   5  * (C) Copyright 2002
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * Copied from lubbock.h
  10  *
  11  * (C) Copyright 2004
  12  * BEC Systems <http://bec-systems.com>
  13  * Cliff Brake <cliff.brake@gmail.com>
  14  * Configuation settings for the Accelent/Vibren PXA255 IDP
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 #include <asm/arch/pxa-regs.h>
  39
  40 /*
  41  * If we are developing, we might want to start U-Boot from RAM
  42  * so we MUST NOT initialize critical regs like mem-timing ...
  43  */
  44 #undef CONFIG_SKIP_LOWLEVEL_INIT                        /* define for developing */
  45 #undef CONFIG_SKIP_RELOCATE_UBOOT                       /* define for developing */
  46 #define CONFIG_SYS_TEXT_BASE    0x0
  47
  48 /*
  49  * define the following to enable debug blinks.  A debug blink function
  50  * must be defined in memsetup.S
  51  */
  52 #undef DEBUG_BLINK_ENABLE
  53 #undef DEBUG_BLINKC_ENABLE
  54
  55 /*
  56  * High Level Configuration Options
  57  * (easy to change)
  58  */
  59 #define CONFIG_PXA250           1       /* This is an PXA250 CPU    */
  60
  61 #undef CONFIG_LCD
  62 #ifdef CONFIG_LCD
  63 #define CONFIG_SHARP_LM8V31
  64 #endif
  65
  66 #define CONFIG_MMC              1
  67 #define CONFIG_DOS_PARTITION    1
  68 #define BOARD_LATE_INIT         1
  69
  70 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  71
  72 /* we will never enable dcache, because we have to setup MMU first */
  73 #define CONFIG_SYS_NO_DCACHE
  74
  75 /*
  76  * Size of malloc() pool
  77  */
  78 #define CONFIG_SYS_MALLOC_LEN       (CONFIG_ENV_SIZE + 128*1024)
  79
  80 /*
  81  * PXA250 IDP memory map information
  82  */
  83
  84 #define IDP_CS5_ETH_OFFSET      0x03400000
  85
  86
  87 /*
  88  * Hardware drivers
  89  */
  90 #define CONFIG_NET_MULTI
  91 #define CONFIG_SMC91111
  92 #define CONFIG_SMC91111_BASE    (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
  93 #define CONFIG_SMC_USE_32_BIT   1
  94 /* #define CONFIG_SMC_USE_IOFUNCS */
  95
  96 /* the following has to be set high -- suspect something is wrong with
  97  * with the tftp timeout routines. FIXME!!!
  98  */
  99 #define CONFIG_NET_RETRY_COUNT  100
 100
 101 /*
 102  * select serial console configuration
 103  */
 104 #define CONFIG_PXA_SERIAL
 105 #define CONFIG_FFUART          1       /* we use FFUART on LUBBOCK */
 106
 107 /* allow to overwrite serial and ethaddr */
 108 #define CONFIG_ENV_OVERWRITE
 109
 110 #define CONFIG_BAUDRATE         115200
 111
 112
 113 /*
 114  * BOOTP options
 115  */
 116 #define CONFIG_BOOTP_BOOTFILESIZE
 117 #define CONFIG_BOOTP_BOOTPATH
 118 #define CONFIG_BOOTP_GATEWAY
 119 #define CONFIG_BOOTP_HOSTNAME
 120
 121
 122 /*
 123  * Command line configuration.
 124  */
 125 #include <config_cmd_default.h>
 126
 127 #define CONFIG_CMD_FAT
 128 #define CONFIG_CMD_DHCP
 129
 130 #define CONFIG_BOOTDELAY        3
 131 #define CONFIG_BOOTCOMMAND      "bootm 40000"
 132 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
 133
 134 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
 135 #define CONFIG_SETUP_MEMORY_TAGS        1
 136 /* #define CONFIG_INITRD_TAG            1 */
 137
 138 /*
 139  * Current memory map for Vibren supplied Linux images:
 140  *
 141  * Flash:
 142  * 0 - 0x3ffff (size = 0x40000): bootloader
 143  * 0x40000 - 0x13ffff (size = 0x100000): kernel
 144  * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
 145  *
 146  * RAM:
 147  * 0xa0008000 - kernel is loaded
 148  * 0xa3000000 - Uboot runs (48MB into RAM)
 149  *
 150  */
 151
 152 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 153         "prog_boot_mmc="                                                \
 154                         "mw.b 0xa0000000 0xff 0x40000; "                \
 155                         "if      mmcinit && "                           \
 156                                 "fatload mmc 0 0xa0000000 u-boot.bin; " \
 157                         "then "                                         \
 158                                 "protect off 0x0 0x3ffff; "             \
 159                                 "erase 0x0 0x3ffff; "                   \
 160                                 "cp.b 0xa0000000 0x0 0x40000; "         \
 161                                 "reset;"                                \
 162                         "fi\0"                                          \
 163         "prog_uzImage_mmc="                                             \
 164                         "mw.b 0xa0000000 0xff 0x100000; "               \
 165                         "if      mmcinit && "                           \
 166                                 "fatload mmc 0 0xa0000000 uzImage; "    \
 167                         "then "                                         \
 168                                 "protect off 0x40000 0xfffff; "         \
 169                                 "erase 0x40000 0xfffff; "               \
 170                                 "cp.b 0xa0000000 0x40000 0x100000; "    \
 171                         "fi\0"                                          \
 172         "prog_jffs_mmc="                                                \
 173                         "mw.b 0xa0000000 0xff 0x1e00000; "              \
 174                         "if      mmcinit && "                           \
 175                                 "fatload mmc 0 0xa0000000 root.jffs; "  \
 176                         "then "                                         \
 177                                 "protect off 0x140000 0x1f3ffff; "      \
 178                                 "erase 0x140000 0x1f3ffff; "            \
 179                                 "cp.b 0xa0000000 0x140000 0x1e00000; "  \
 180                         "fi\0"                                          \
 181         "boot_mmc="                                                     \
 182                         "if      mmcinit && "                           \
 183                                 "fatload mmc 0 0xa1000000 uzImage && "  \
 184                         "then "                                         \
 185                                 "bootm 0xa1000000; "                    \
 186                         "fi\0"                                          \
 187         "prog_boot_net="                                                \
 188                         "mw.b 0xa0000000 0xff 0x100000; "               \
 189                         "if      bootp 0xa0000000 u-boot.bin; "         \
 190                         "then "                                         \
 191                                 "protect off 0x0 0x3ffff; "             \
 192                                 "erase 0x0 0x3ffff; "                   \
 193                                 "cp.b 0xa0000000 0x0 0x40000; "         \
 194                                 "reset; "                               \
 195                         "fi\0"                                          \
 196         "prog_uzImage_net="                                             \
 197                         "mw.b 0xa0000000 0xff 0x100000; "               \
 198                         "if      bootp 0xa0000000 uzImage; "            \
 199                         "then "                                         \
 200                                 "protect off 0x40000 0xfffff; "         \
 201                                 "erase 0x40000 0xfffff; "               \
 202                                 "cp.b 0xa0000000 0x40000 0x100000; "    \
 203                         "fi\0"                                          \
 204         "prog_jffs_net="                                                \
 205                         "mw.b 0xa0000000 0xff 0x1e00000; "              \
 206                         "if      bootp 0xa0000000 root.jffs; "          \
 207                         "then "                                         \
 208                                 "protect off 0x140000 0x1f3ffff; "      \
 209                                 "erase 0x140000 0x1f3ffff; "            \
 210                                 "cp.b 0xa0000000 0x140000 0x1e00000; "  \
 211                         "fi\0"
 212
 213
 214 /*      "erase_env="                    */
 215 /*                      "protect off"   */
 216
 217
 218 #if defined(CONFIG_CMD_KGDB)
 219 #define CONFIG_KGDB_BAUDRATE    115200          /* speed to run kgdb serial port */
 220 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 221 #endif
 222
 223 /*
 224  * Miscellaneous configurable options
 225  */
 226 #define CONFIG_SYS_HUSH_PARSER          1
 227 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 228
 229 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
 230 #ifdef CONFIG_SYS_HUSH_PARSER
 231 #define CONFIG_SYS_PROMPT               "$ "            /* Monitor Command Prompt */
 232 #else
 233 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt */
 234 #endif
 235 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 236 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 237 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 238 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 239 #define CONFIG_SYS_DEVICE_NULLDEV       1
 240
 241 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on     */
 242 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM   */
 243
 244 #define CONFIG_SYS_LOAD_ADDR            0xa0800000      /* default load address */
 245
 246 #define CONFIG_SYS_HZ                   1000
 247 #define CONFIG_SYS_CPUSPEED             0x161           /* set core clock to 400/200/100 MHz */
 248
 249 #define RTC     1                               /* enable 32KHz osc */
 250
 251                                                 /* valid baudrates */
 252 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 253
 254 #ifdef CONFIG_MMC
 255 #define CONFIG_PXA_MMC
 256 #define CONFIG_CMD_MMC
 257 #define CONFIG_SYS_MMC_BASE             0xF0000000
 258 #endif
 259
 260 /*
 261  * Stack sizes
 262  *
 263  * The stack sizes are set up in start.S using the settings below
 264  */
 265 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 266 #ifdef CONFIG_USE_IRQ
 267 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 268 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 269 #endif
 270
 271 /*
 272  * Physical Memory Map
 273  */
 274 #define CONFIG_NR_DRAM_BANKS    1          /* we have 1 bank of DRAM */
 275 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
 276 #define PHYS_SDRAM_1_SIZE       0x04000000 /* 64 MB */
 277 #define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
 278 #define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
 279 #define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
 280 #define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
 281 #define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
 282 #define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
 283
 284 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 285 #define PHYS_FLASH_2            0x04000000 /* Flash Bank #2 */
 286 #define PHYS_FLASH_SIZE         0x02000000 /* 32 MB */
 287 #define PHYS_FLASH_BANK_SIZE    0x02000000 /* 32 MB Banks */
 288 #define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
 289
 290 #define CONFIG_SYS_DRAM_BASE            0xa0000000
 291 #define CONFIG_SYS_DRAM_SIZE            0x04000000
 292
 293 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 294
 295 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 296 #define CONFIG_SYS_INIT_SP_ADDR         (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 297
 298 /*
 299  * GPIO settings
 300  */
 301
 302 #define CONFIG_SYS_GAFR0_L_VAL  0x80001005
 303 #define CONFIG_SYS_GAFR0_U_VAL  0xa5128012
 304 #define CONFIG_SYS_GAFR1_L_VAL  0x699a9558
 305 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa5aa6a
 306 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 307 #define CONFIG_SYS_GAFR2_U_VAL  0x2
 308 #define CONFIG_SYS_GPCR0_VAL    0x1800400
 309 #define CONFIG_SYS_GPCR1_VAL    0x0
 310 #define CONFIG_SYS_GPCR2_VAL    0x0
 311 #define CONFIG_SYS_GPDR0_VAL    0xc1818440
 312 #define CONFIG_SYS_GPDR1_VAL    0xfcffab82
 313 #define CONFIG_SYS_GPDR2_VAL    0x1ffff
 314 #define CONFIG_SYS_GPSR0_VAL    0x8000
 315 #define CONFIG_SYS_GPSR1_VAL    0x3f0002
 316 #define CONFIG_SYS_GPSR2_VAL    0x1c000
 317
 318 #define CONFIG_SYS_PSSR_VAL             0x20
 319
 320 #define CONFIG_SYS_CCCR                 CCCR_L27|CCCR_M2|CCCR_N10
 321 #define CONFIG_SYS_CKEN                 0x0
 322
 323 /*
 324  * Memory settings
 325  */
 326 #define CONFIG_SYS_MSC0_VAL             0x29DCA4D2
 327 #define CONFIG_SYS_MSC1_VAL             0x43AC494C
 328 #define CONFIG_SYS_MSC2_VAL             0x39D449D4
 329 #define CONFIG_SYS_MDCNFG_VAL           0x090009C9
 330 #define CONFIG_SYS_MDREFR_VAL           0x0085C017
 331 #define CONFIG_SYS_MDMRS_VAL            0x00220022
 332 #define CONFIG_SYS_FLYCNFG_VAL          0x00000000
 333 #define CONFIG_SYS_SXCNFG_VAL           0x00000000
 334
 335 /*
 336  * PCMCIA and CF Interfaces
 337  */
 338 #define CONFIG_SYS_MECR_VAL             0x00000003
 339 #define CONFIG_SYS_MCMEM0_VAL           0x00014405
 340 #define CONFIG_SYS_MCMEM1_VAL           0x00014405
 341 #define CONFIG_SYS_MCATT0_VAL           0x00014405
 342 #define CONFIG_SYS_MCATT1_VAL           0x00014405
 343 #define CONFIG_SYS_MCIO0_VAL            0x00014405
 344 #define CONFIG_SYS_MCIO1_VAL            0x00014405
 345
 346 /*
 347  * FLASH and environment organization
 348  */
 349 #define CONFIG_SYS_FLASH_CFI
 350 #define CONFIG_FLASH_CFI_DRIVER 1
 351
 352 #define CONFIG_SYS_MONITOR_BASE 0
 353 #define CONFIG_SYS_MONITOR_LEN          PHYS_FLASH_SECT_SIZE
 354
 355 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 356 #define CONFIG_SYS_MAX_FLASH_SECT       128  /* max number of sectors on one chip    */
 357
 358 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 359
 360 /* timeout values are in ticks */
 361 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 362 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 363
 364 /* put cfg at end of flash for now */
 365 #define CONFIG_ENV_IS_IN_FLASH  1
 366  /* Addr of Environment Sector  */
 367 #define CONFIG_ENV_ADDR         (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
 368 #define CONFIG_ENV_SIZE         PHYS_FLASH_SECT_SIZE    /* Total Size of Environment Sector     */
 369 #define CONFIG_ENV_SECT_SIZE    (PHYS_FLASH_SECT_SIZE / 16)
 370
 371 #endif  /* __CONFIG_H */