2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/socfpga_base_addrs.h>
10 #include "../../board/altera/socfpga/pinmux_config.h"
11 #include "../../board/altera/socfpga/iocsr_config.h"
12 #include "../../board/altera/socfpga/pll_config.h"
15 * High level configuration
17 /* Virtual target or real hardware */
18 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
23 #define CONFIG_MISC_INIT_R
24 #define CONFIG_SINGLE_BOOTLOADER
25 #define CONFIG_SOCFPGA
28 #define CONFIG_SYS_ARM_CACHE_WRITEALLOC
29 #define CONFIG_SYS_CACHELINE_SIZE 32
30 #define CONFIG_SYS_L2_PL310
31 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
33 /* base address for .text section */
34 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
35 #define CONFIG_SYS_TEXT_BASE 0x08000040
37 #define CONFIG_SYS_TEXT_BASE 0x01000040
39 #define CONFIG_SYS_LOAD_ADDR 0x7fc0
41 /* Console I/O Buffer Size */
42 #define CONFIG_SYS_CBSIZE 256
43 /* Monitor Command Prompt */
44 #define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # "
45 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
46 sizeof(CONFIG_SYS_PROMPT) + 16)
49 * Display CPU and Board Info
51 #define CONFIG_DISPLAY_CPUINFO
52 #define CONFIG_DISPLAY_BOARDINFO
55 * Enable early stage initialization at C environment
57 #define CONFIG_BOARD_EARLY_INIT_F
59 /* flat device tree */
60 #define CONFIG_OF_LIBFDT
61 /* skip updating the FDT blob */
62 #define CONFIG_FDT_BLOB_SKIP_UPDATE
63 /* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
64 #define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024))
66 #define CONFIG_SPL_RAM_DEVICE
67 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
68 #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
69 #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
72 * Memory allocation (MALLOC)
74 /* Room required on the stack for the environment data */
75 #define CONFIG_ENV_SIZE 1024
76 /* Size of DRAM reserved for malloc() use */
77 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
79 /* SP location before relocation, must use scratch RAM */
80 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
81 /* Reserving 0x100 space at back of scratch RAM for debug info */
82 #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
83 /* Stack pointer prior relocation, must situated at on-chip RAM */
84 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
85 CONFIG_SYS_INIT_RAM_SIZE - \
86 GENERATED_GBL_DATA_SIZE)
90 * Command line configuration.
92 #define CONFIG_SYS_NO_FLASH
93 #include <config_cmd_default.h>
94 /* FAT file system support */
95 #define CONFIG_CMD_FAT
96 /* bootz command support */
97 #define CONFIG_CMD_BOOTZ
103 #define CONFIG_DOS_PARTITION 1
105 #ifdef CONFIG_SPL_BUILD
106 #undef CONFIG_PARTITIONS
113 /* Delay before automatically booting the default image */
114 #define CONFIG_BOOTDELAY 3
115 /* Enable auto completion of commands using TAB */
116 #define CONFIG_AUTO_COMPLETE
117 /* use "hush" command parser */
118 #define CONFIG_SYS_HUSH_PARSER
119 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
120 #define CONFIG_CMD_RUN
122 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
123 #define CONFIG_BOOTCOMMAND "run ramboot"
125 #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
129 * arguments passed to the bootm command. The value of
130 * CONFIG_BOOTARGS goes into the environment value "bootargs".
131 * Do note the value will overide also the chosen node in FDT blob.
133 #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
135 #define CONFIG_EXTRA_ENV_SETTINGS \
137 "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
138 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
139 "bootm ${loadaddr} - ${fdt_addr}\0" \
140 "bootimage=zImage\0" \
142 "fdtimage=socfpga.dtb\0" \
143 "fsloadcmd=ext2load\0" \
144 "bootm ${loadaddr} - ${fdt_addr}\0" \
145 "mmcroot=/dev/mmcblk0p2\0" \
146 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
147 " root=${mmcroot} rw rootwait;" \
148 "bootz ${loadaddr} - ${fdt_addr}\0" \
149 "mmcload=mmc rescan;" \
150 "fatload mmc 0:1 ${loadaddr} ${bootimage};" \
151 "fatload mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
152 "qspiroot=/dev/mtdblock0\0" \
153 "qspirootfstype=jffs2\0" \
154 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
155 " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
156 "bootm ${loadaddr} - ${fdt_addr}\0"
158 /* using environment setting for stdin, stdout, stderr */
159 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
160 /* Enable the call to overwrite_console() */
161 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
162 /* Enable overwrite of previous console environment settings */
163 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
165 /* max number of command args */
166 #define CONFIG_SYS_MAXARGS 16
176 /* We have 1 bank of DRAM */
177 #define CONFIG_NR_DRAM_BANKS 1
179 #define CONFIG_SYS_SDRAM_BASE 0x00000000
180 /* SDRAM memory size */
181 #define PHYS_SDRAM_1_SIZE 0x40000000
183 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
184 #define CONFIG_SYS_MEMTEST_START 0x00000000
185 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
188 * NS16550 Configuration
190 #define UART0_BASE SOCFPGA_UART0_ADDRESS
191 #define CONFIG_SYS_NS16550
192 #define CONFIG_SYS_NS16550_SERIAL
193 #define CONFIG_SYS_NS16550_REG_SIZE -4
194 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
195 #define CONFIG_CONS_INDEX 1
196 #define CONFIG_SYS_NS16550_COM1 UART0_BASE
197 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
198 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
199 #define V_NS16550_CLK 1000000
201 #define V_NS16550_CLK 100000000
203 #define CONFIG_BAUDRATE 115200
208 #define CONFIG_SYS_NO_FLASH
213 /* This timer use eosc1 where the clock frequency is fixed
214 * throughout any condition */
215 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
217 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
218 #define CONFIG_SYS_TIMER_RATE 2400000
220 #define CONFIG_SYS_TIMER_RATE 25000000
222 #define CONFIG_SYS_TIMER_COUNTS_DOWN
223 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
225 #define CONFIG_ENV_IS_NOWHERE
230 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
231 #define CONFIG_DESIGNWARE_ETH 1
234 #ifdef CONFIG_DESIGNWARE_ETH
235 #define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS
236 #define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS
237 /* console support for network */
238 #define CONFIG_CMD_DHCP
239 #define CONFIG_CMD_MII
240 #define CONFIG_CMD_NET
241 #define CONFIG_CMD_PING
243 #define CONFIG_NET_MULTI
244 #define CONFIG_DW_ALTDESCRIPTOR
246 #define CONFIG_PHY_GIGE
247 #define CONFIG_DW_AUTONEG
248 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
249 #define CONFIG_PHYLIB
250 #define CONFIG_PHY_MICREL
251 #define CONFIG_PHY_MICREL_KSZ9021
252 /* EMAC controller and PHY used */
253 #define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE
254 #define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR
255 #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
256 #endif /* CONFIG_DESIGNWARE_ETH */
261 #define CONFIG_HW_WATCHDOG
262 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000
263 #define CONFIG_DESIGNWARE_WATCHDOG
264 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
265 /* Clocks source frequency to watchdog timer */
266 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
273 #define CONFIG_BOUNCE_BUFFER
274 #define CONFIG_CMD_MMC
275 #define CONFIG_GENERIC_MMC
277 #define CONFIG_SOCFPGA_DWMMC
278 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
279 #define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
280 #define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
281 /* using smaller max blk cnt to avoid flooding the limited stack we have */
282 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
283 #endif /* CONFIG_MMC */
286 * SPL "Second Program Loader" aka Initial Software
289 /* Enable building of SPL globally */
290 #define CONFIG_SPL_FRAMEWORK
292 /* TEXT_BASE for linking the SPL binary */
293 #define CONFIG_SPL_TEXT_BASE 0xFFFF0000
295 /* Stack size for SPL */
296 #define CONFIG_SPL_STACK_SIZE (4 * 1024)
298 /* MALLOC size for SPL */
299 #define CONFIG_SPL_MALLOC_SIZE (5 * 1024)
301 #define CONFIG_SPL_SERIAL_SUPPORT
302 #define CONFIG_SPL_BOARD_INIT
304 #define CHUNKSZ_CRC32 (1 * 1024)
306 #define CONFIG_CRC32_VERIFY
308 /* Linker script for SPL */
309 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
311 /* Support for common/libcommon.o in SPL binary */
312 #define CONFIG_SPL_LIBCOMMON_SUPPORT
313 /* Support for lib/libgeneric.o in SPL binary */
314 #define CONFIG_SPL_LIBGENERIC_SUPPORT
316 /* Support for watchdog */
317 #define CONFIG_SPL_WATCHDOG_SUPPORT
319 #endif /* __CONFIG_H */