2 * Copyright (C) 2012 <LW@KARO-electronics.de>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/sizes.h>
26 * Ka-Ro TX51 board - SoC configuration
28 #define CONFIG_MX51 /* i.MX51 SoC */
29 #define CONFIG_SYS_MX5_IOMUX_V3
30 #define CONFIG_MXC_GPIO /* GPIO control */
31 #define CONFIG_SYS_MX5_HCLK 24000000
32 #define CONFIG_SYS_MX5_CLK32 32768
33 #define CONFIG_SYS_DDR_CLKSEL 0
34 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
35 #define CONFIG_SHOW_ACTIVITY
36 #define CONFIG_DISPLAY_BOARDINFO
37 #define CONFIG_BOARD_LATE_INIT
38 #define CONFIG_SPLASH_SCREEN
39 #define CONFIG_BOARD_EARLY_INIT_F
41 #if CONFIG_SYS_CPU_CLK == 600
42 #define TX51_MOD_PREFIX "6"
43 #elif CONFIG_SYS_CPU_CLK == 800
44 #define TX51_MOD_PREFIX "8"
45 #define CONFIG_MX51_PLL_ERRATA
47 #error Invalid CPU clock
51 * Memory configurations
53 #define PHYS_SDRAM_1 0x90000000 /* Base address of bank 1 */
54 #define PHYS_SDRAM_1_SIZE SZ_128M
55 #if CONFIG_NR_DRAM_BANKS > 1
56 #define PHYS_SDRAM_2 0x98000000 /* Base address of bank 2 */
57 #define PHYS_SDRAM_2_SIZE SZ_128M
59 #define TX51_MOD_SUFFIX "0"
61 #define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */
62 #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
63 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Reserved for initial data */
64 #define CONFIG_SYS_MEMTEST_START 0x90000000 /* Memtest start address */
65 #define CONFIG_SYS_MEMTEST_END 0x90400000 /* 4 MB RAM test */
66 #if CONFIG_SYS_SDRAM_CLK == 200
67 #define CONFIG_SYS_CLKTL_CBCDR 0x59e35180
68 #define TX51_MOD_SUFFIX "1"
69 #elif CONFIG_SYS_SDRAM_CLK == 166
70 #define CONFIG_SYS_CLKTL_CBCDR 0x01e35180
71 #ifndef TX51_MOD_SUFFIX
72 #define TX51_MOD_SUFFIX "2"
75 #error Invalid SDRAM clock
79 * U-Boot general configurations
81 #define CONFIG_SYS_LONGHELP
82 #define CONFIG_SYS_PROMPT "MX51 U-Boot > "
83 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
84 #define CONFIG_SYS_PBSIZE \
85 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
86 /* Print buffer size */
87 #define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
88 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
89 /* Boot argument buffer size */
90 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
91 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
92 #define CONFIG_CMDLINE_EDITING /* Command history etc */
94 #define CONFIG_SYS_64BIT_VSPRINTF
95 #define CONFIG_SYS_NO_FLASH
98 * Flattened Device Tree (FDT) support
100 #define CONFIG_OF_LIBFDT
101 #define CONFIG_OF_CONTROL
102 #define CONFIG_OF_EMBED
103 #define CONFIG_OF_BOARD_SETUP
104 #define CONFIG_DEFAULT_DEVICE_TREE tx51
105 #define CONFIG_ARCH_DEVICE_TREE mx51
110 #define xstr(s) str(s)
113 #define CONFIG_CMDLINE_TAG
114 #define CONFIG_SETUP_MEMORY_TAGS
115 #define CONFIG_BOOTDELAY 3
116 #define CONFIG_ZERO_BOOTDELAY_CHECK
117 #define CONFIG_BOOTFILE "uImage"
118 #define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1"
119 #define CONFIG_BOOTCOMMAND "run bootcmd_nand"
120 #define CONFIG_LOADADDR 0x90100000
121 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
122 #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
123 #define CONFIG_HW_WATCHDOG
128 #define CONFIG_EXTRA_ENV_SETTINGS \
130 "baseboard=stk5-v3\0" \
131 "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
132 " root=/dev/mmcblk0p3 rootwait\0" \
133 "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
134 " root=/dev/mtdblock3 rootfstype=jffs2\0" \
135 "nfsroot=/tftpboot/rootfs\0" \
136 "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
137 " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\
138 "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
139 "mmc read ${loadaddr} 100 3000;run bootm_cmd\0" \
140 "bootcmd_nand=set autostart no;run bootargs_nand;" \
141 "nboot linux;run bootm_cmd\0" \
142 "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
145 "bootm_cmd=fdt addr ${fdtcontroladdr};fdt board;" \
146 "bootm ${loadaddr} - ${fdtaddr}\0" \
147 "default_bootargs=set bootargs " CONFIG_BOOTARGS \
148 " ${mtdparts} video=${video_mode} ${append_bootargs}\0" \
149 "fdtcontroladdr=90004000\0" \
150 "mtdids=" MTDIDS_DEFAULT "\0" \
151 "mtdparts=" MTDPARTS_DEFAULT "\0" \
152 "touchpanel=tsc2007\0" \
153 "video_mode=640x480MR@60\0"
155 #define MTD_NAME "mxc_nand"
156 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
157 #define CONFIG_FDT_FIXUP_PARTITIONS
162 #include <config_cmd_default.h>
163 #define CONFIG_CMD_CACHE
164 #define CONFIG_CMD_MMC
165 #define CONFIG_CMD_NAND
166 #define CONFIG_CMD_MTDPARTS
171 #define CONFIG_MXC_UART
172 #define CONFIG_MXC_UART_BASE UART1_BASE
173 #define CONFIG_MXC_GPIO
174 #define CONFIG_CONS_INDEX 0
175 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
176 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
181 #define CONFIG_FEC_MXC
182 #ifdef CONFIG_FEC_MXC
183 #define IMX_FEC_BASE FEC_BASE_ADDR
184 #define CONFIG_FEC_MXC_PHYADDR 0x1f
185 #define CONFIG_PHYLIB
186 #define CONFIG_PHY_SMSC
188 #define CONFIG_FEC_XCV_TYPE MII100
189 #define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
190 #define CONFIG_ETH_PRIME
191 #define CONFIG_CMD_MII
192 #define CONFIG_CMD_DHCP
193 #define CONFIG_CMD_PING
194 /* Add for working with "strict" DHCP server */
195 #define CONFIG_BOOTP_SUBNETMASK
196 #define CONFIG_BOOTP_GATEWAY
197 #define CONFIG_BOOTP_DNS
203 #ifdef CONFIG_CMD_NAND
204 #define CONFIG_MTD_DEVICE
205 #define CONFIG_ENV_IS_IN_NAND
206 #define CONFIG_NAND_MXC
207 #define CONFIG_MXC_NAND_REGS_BASE 0xcfff0000
208 #define CONFIG_MXC_NAND_IP_BASE 0x83fdb000
209 #define CONFIG_MXC_NAND_HWECC
210 #define CONFIG_CMD_NAND_TRIMFFS
211 #define CONFIG_SYS_MAX_FLASH_SECT 1024
212 #define CONFIG_SYS_MAX_FLASH_BANKS 1
213 #define CONFIG_SYS_NAND_MAX_CHIPS 1
214 #define CONFIG_SYS_MAX_NAND_DEVICE 1
215 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
216 #define CONFIG_SYS_NAND_USE_FLASH_BBT
217 #ifdef CONFIG_ENV_IS_IN_NAND
218 #define CONFIG_ENV_OVERWRITE
219 #define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE
220 #define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */
222 #define CONFIG_ENV_OFFSET_REDUND 0x20000
223 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
226 #ifndef CONFIG_SYS_NO_FLASH
227 #define CONFIG_CMD_FLASH
228 #define CONFIG_SYS_NAND_BASE 0xa0000000
231 #define CONFIG_SYS_NAND_BASE 0x00000000
232 #define CONFIG_CMD_ROMUPDATE
234 #endif /* CONFIG_CMD_NAND */
239 #ifdef CONFIG_CMD_MMC
240 #ifndef CONFIG_ENV_IS_IN_NAND
241 #define CONFIG_ENV_IS_IN_MMC
244 #define CONFIG_GENERIC_MMC
245 #define CONFIG_FSL_ESDHC
246 #define CONFIG_SYS_FSL_ESDHC_USE_PIO
247 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
248 #define CONFIG_SYS_FSL_ESDHC_NUM 2
249 #define CONFIG_DOS_PARTITION
250 #define CONFIG_CMD_FAT
252 #define CONFIG_BOOT_PARTITION_ACCESS
253 #define CONFIG_DOS_PARTITION
254 #define CONFIG_CMD_FAT
255 #define CONFIG_CMD_EXT2
258 * Environments on MMC
260 #ifdef CONFIG_ENV_IS_IN_MMC
261 #define CONFIG_SYS_MMC_ENV_DEV 0
262 #define CONFIG_CMD_ENV
263 #define CONFIG_ENV_OVERWRITE
264 /* Associated with the MMC layout defined in mmcops.c */
265 #define CONFIG_ENV_OFFSET 0x400 /* 1 KB */
266 #define CONFIG_ENV_SIZE (0x20000 - 0x400) /* 127 KB */
267 #define CONFIG_DYNAMIC_MMC_DEVNO
268 #endif /* CONFIG_ENV_IS_IN_MMC */
269 #endif /* CONFIG_CMD_MMC */
271 #ifdef CONFIG_ENV_OFFSET_REDUND
272 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
274 xstr(CONFIG_ENV_SIZE) \
276 xstr(CONFIG_ENV_SIZE) \
277 "(env2),4m(linux),16m(rootfs),-(userfs)"
279 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
281 xstr(CONFIG_ENV_SIZE) \
282 "(env),4m(linux),16m(rootfs),-(userfs)"
285 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
286 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
287 GENERATED_GBL_DATA_SIZE)
289 #endif /* __CONFIG_H */