2 * Copyright (C) 2012 <LW@KARO-electronics.de>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
17 #include <asm/sizes.h>
20 * Ka-Ro TX51 board - SoC configuration
22 #define CONFIG_MX51 /* i.MX51 SoC */
23 #define CONFIG_SYS_MX5_IOMUX_V3
24 #define CONFIG_MXC_GPIO /* GPIO control */
25 #define CONFIG_SYS_MX5_HCLK 24000000
26 #define CONFIG_SYS_MX5_CLK32 32768
27 #define CONFIG_SYS_DDR_CLKSEL 0
28 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
29 #define CONFIG_SHOW_ACTIVITY
30 #define CONFIG_DISPLAY_BOARDINFO
31 #define CONFIG_BOARD_LATE_INIT
32 #define CONFIG_BOARD_EARLY_INIT_F
34 #if CONFIG_SYS_CPU_CLK == 600
35 #define TX51_MOD_PREFIX "6"
36 #elif CONFIG_SYS_CPU_CLK == 800
37 #define TX51_MOD_PREFIX "8"
38 #define CONFIG_MX51_PLL_ERRATA
40 #error Invalid CPU clock
43 /* LCD Logo and Splash screen support */
46 #define CONFIG_SPLASH_SCREEN
47 #define CONFIG_SPLASH_SCREEN_ALIGN
48 #define CONFIG_VIDEO_MX5
49 #define CONFIG_LCD_LOGO
50 #define LCD_BPP LCD_COLOR24
51 #define CONFIG_CMD_BMP
52 #define CONFIG_VIDEO_BMP_RLE8
53 #endif /* CONFIG_LCD */
56 * Memory configurations
58 #define PHYS_SDRAM_1 0x90000000 /* Base address of bank 1 */
59 #define PHYS_SDRAM_1_SIZE SZ_128M
60 #if CONFIG_NR_DRAM_BANKS > 1
61 #define PHYS_SDRAM_2 0x98000000 /* Base address of bank 2 */
62 #define PHYS_SDRAM_2_SIZE SZ_128M
64 #define TX51_MOD_SUFFIX "0"
66 #define CONFIG_STACKSIZE SZ_128K
67 #define CONFIG_SYS_MALLOC_LEN SZ_8M
68 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
69 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M) /* 4 MB RAM test */
70 #if CONFIG_SYS_SDRAM_CLK == 200
71 #define CONFIG_SYS_CLKTL_CBCDR 0x59e35180
72 #define TX51_MOD_SUFFIX "1"
73 #elif CONFIG_SYS_SDRAM_CLK == 166
74 #define CONFIG_SYS_CLKTL_CBCDR 0x01e35180
75 #ifndef TX51_MOD_SUFFIX
76 #define TX51_MOD_SUFFIX "2"
79 #error Invalid SDRAM clock
83 * U-Boot general configurations
85 #define CONFIG_SYS_LONGHELP
86 #define CONFIG_SYS_PROMPT "TX51 U-Boot > "
87 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
88 #define CONFIG_SYS_PBSIZE \
89 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
90 /* Print buffer size */
91 #define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
92 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
93 /* Boot argument buffer size */
94 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
95 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
96 #define CONFIG_CMDLINE_EDITING /* Command history etc */
98 #define CONFIG_SYS_64BIT_VSPRINTF
99 #define CONFIG_SYS_NO_FLASH
102 * Flattened Device Tree (FDT) support
104 #define CONFIG_OF_LIBFDT
105 #define CONFIG_OF_EMBED
106 #define CONFIG_OF_BOARD_SETUP
107 #define CONFIG_DEFAULT_DEVICE_TREE tx51
108 #define CONFIG_ARCH_DEVICE_TREE mx51
113 #define xstr(s) str(s)
115 #define __pfx(x, s) (x##s)
116 #define _pfx(x, s) __pfx(x, s)
118 #define CONFIG_CMDLINE_TAG
119 #define CONFIG_SETUP_MEMORY_TAGS
120 #define CONFIG_BOOTDELAY 3
121 #define CONFIG_ZERO_BOOTDELAY_CHECK
122 #define CONFIG_SYS_AUTOLOAD "no"
123 #define CONFIG_BOOTFILE "uImage"
124 #define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1"
125 #define CONFIG_BOOTCOMMAND "run bootcmd_nand"
126 #define CONFIG_LOADADDR 94000000
127 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
128 #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
129 #define CONFIG_HW_WATCHDOG
134 #define CONFIG_EXTRA_ENV_SETTINGS \
136 "baseboard=stk5-v3\0" \
137 "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
138 " root=/dev/mmcblk0p3 rootwait\0" \
139 "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
140 " root=/dev/mtdblock3 rootfstype=jffs2\0" \
141 "nfsroot=/tftpboot/rootfs\0" \
142 "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
143 " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\
144 "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
145 "mmc read ${loadaddr} 100 3000;run bootm_cmd\0" \
146 "bootcmd_nand=set autostart no;run bootargs_nand;" \
147 "nboot linux;run bootm_cmd\0" \
148 "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
150 "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \
151 "default_bootargs=set bootargs " CONFIG_BOOTARGS \
152 " video=${video_mode} ${append_bootargs}\0" \
153 "cpu_clk=" xstr(CONFIG_SYS_CPU_CLK) "\0" \
154 "fdtaddr=91000000\0" \
155 "mtdids=" MTDIDS_DEFAULT "\0" \
156 "mtdparts=" MTDPARTS_DEFAULT "\0" \
157 "otg_mode=device\0" \
158 "touchpanel=tsc2007\0" \
159 "video_mode=VGA-1:640x480MR-24@60\0"
161 #define MTD_NAME "mxc_nand"
162 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
163 #define CONFIG_FDT_FIXUP_PARTITIONS
168 #include <config_cmd_default.h>
169 #define CONFIG_CMD_CACHE
170 #define CONFIG_CMD_IIM
171 #define CONFIG_CMD_MMC
172 #define CONFIG_CMD_NAND
173 #define CONFIG_CMD_MTDPARTS
174 #define CONFIG_CMD_BOOTCE
175 #define CONFIG_CMD_TIME
180 #define CONFIG_MXC_UART
181 #define CONFIG_MXC_UART_BASE UART1_BASE
182 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
183 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
184 #define CONFIG_SYS_CONSOLE_INFO_QUIET
189 #define CONFIG_FEC_MXC
190 #ifdef CONFIG_FEC_MXC
191 #define IMX_FEC_BASE FEC_BASE_ADDR
192 #define CONFIG_FEC_MXC_PHYADDR 0x1f
193 #define CONFIG_PHYLIB
194 #define CONFIG_PHY_SMSC
196 #define CONFIG_FEC_XCV_TYPE MII100
197 #define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
198 #define CONFIG_CMD_MII
199 #define CONFIG_CMD_DHCP
200 #define CONFIG_CMD_PING
201 /* Add for working with "strict" DHCP server */
202 #define CONFIG_BOOTP_SUBNETMASK
203 #define CONFIG_BOOTP_GATEWAY
204 #define CONFIG_BOOTP_DNS
210 #ifdef CONFIG_CMD_NAND
211 #define CONFIG_MTD_DEVICE
212 #define CONFIG_ENV_IS_IN_NAND
213 #define CONFIG_NAND_MXC
214 #define CONFIG_MXC_NAND_REGS_BASE 0xcfff0000
215 #define CONFIG_MXC_NAND_IP_BASE 0x83fdb000
216 #define CONFIG_MXC_NAND_HWECC
217 #define CONFIG_CMD_NAND_TRIMFFS
218 #define CONFIG_SYS_MAX_FLASH_SECT 1024
219 #define CONFIG_SYS_MAX_FLASH_BANKS 1
220 #define CONFIG_SYS_NAND_MAX_CHIPS 1
221 #define CONFIG_SYS_MAX_NAND_DEVICE 1
222 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
223 #define CONFIG_SYS_NAND_USE_FLASH_BBT
224 #ifdef CONFIG_ENV_IS_IN_NAND
225 #define CONFIG_ENV_OVERWRITE
226 #define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE
227 #define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */
228 #define CONFIG_ENV_RANGE 0x60000
230 #ifndef CONFIG_SYS_NO_FLASH
231 #define CONFIG_CMD_FLASH
232 #define CONFIG_SYS_NAND_BASE 0xa0000000
235 #define CONFIG_SYS_NAND_BASE 0x00000000
236 #define CONFIG_CMD_ROMUPDATE
238 #endif /* CONFIG_CMD_NAND */
243 #ifdef CONFIG_CMD_MMC
244 #ifndef CONFIG_ENV_IS_IN_NAND
245 #define CONFIG_ENV_IS_IN_MMC
248 #define CONFIG_GENERIC_MMC
249 #define CONFIG_FSL_ESDHC
250 #define CONFIG_SYS_FSL_ESDHC_USE_PIO
251 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
252 #define CONFIG_SYS_FSL_ESDHC_NUM 2
254 #define CONFIG_BOOT_PARTITION_ACCESS
255 #define CONFIG_DOS_PARTITION
256 #define CONFIG_CMD_FAT
257 #define CONFIG_CMD_EXT2
260 * Environments on MMC
262 #ifdef CONFIG_ENV_IS_IN_MMC
263 #define CONFIG_SYS_MMC_ENV_DEV 0
264 #define CONFIG_ENV_OVERWRITE
265 /* Associated with the MMC layout defined in mmcops.c */
266 #define CONFIG_ENV_OFFSET SZ_1K
267 #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
268 #define CONFIG_DYNAMIC_MMC_DEVNO
269 #endif /* CONFIG_ENV_IS_IN_MMC */
270 #endif /* CONFIG_CMD_MMC */
272 #ifdef CONFIG_ENV_OFFSET_REDUND
273 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
275 xstr(CONFIG_ENV_RANGE) \
277 xstr(CONFIG_ENV_RANGE) \
278 "(env2),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
280 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
282 xstr(CONFIG_ENV_RANGE) \
283 "(env),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
286 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
287 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
288 GENERATED_GBL_DATA_SIZE)
290 #ifdef CONFIG_CMD_IIM
291 #define CONFIG_IMX_IIM
294 #endif /* __CONFIG_H */