include/configs/xpedite537x.h

   1 /*
   2  * Copyright 2008 Extreme Engineering Solutions, Inc.
   3  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * xpedite537x board configuration file
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * High Level Configuration Options
  32  */
  33 #define CONFIG_BOOKE            1       /* BOOKE */
  34 #define CONFIG_E500             1       /* BOOKE e500 family */
  35 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  36 #define CONFIG_MPC8572          1
  37 #define CONFIG_XPEDITE5370      1
  38 #define CONFIG_SYS_BOARD_NAME   "XPedite5370"
  39 #define CONFIG_SYS_FORM_3U_VPX  1
  40 #define CONFIG_BOARD_EARLY_INIT_R       /* Call board_pre_init */
  41
  42 #ifndef CONFIG_SYS_TEXT_BASE
  43 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  44 #endif
  45
  46 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  47 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play */
  48 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
  49 #define CONFIG_PCIE1            1       /* PCIE controler 1 */
  50 #define CONFIG_PCIE2            1       /* PCIE controler 2 */
  51 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  52 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  53 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  54 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  55 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  56 #define CONFIG_FSL_ELBC         1
  57
  58 /*
  59  * Multicore config
  60  */
  61 #define CONFIG_MP
  62 #define CONFIG_BPTR_VIRT_ADDR   0xee000000      /* virt boot page address */
  63 #define CONFIG_MPC8xxx_DISABLE_BPTR             /* Don't leave BPTR enabled */
  64
  65 /*
  66  * DDR config
  67  */
  68 #define CONFIG_FSL_DDR2
  69 #undef CONFIG_FSL_DDR_INTERACTIVE
  70 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  71 #define CONFIG_DDR_SPD
  72 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  73 #define SPD_EEPROM_ADDRESS1             0x54    /* Both channels use the */
  74 #define SPD_EEPROM_ADDRESS2             0x54    /* same SPD data         */
  75 #define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
  76 #define CONFIG_NUM_DDR_CONTROLLERS      2
  77 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  78 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  79 #define CONFIG_DDR_ECC
  80 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  81 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000 /* DDR is system memory*/
  82 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  83 #define CONFIG_VERY_BIG_RAM
  84
  85 #ifndef __ASSEMBLY__
  86 extern unsigned long get_board_sys_clk(unsigned long dummy);
  87 extern unsigned long get_board_ddr_clk(unsigned long dummy);
  88 #endif
  89
  90 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  91 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  92
  93 /*
  94  * These can be toggled for performance analysis, otherwise use default.
  95  */
  96 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  97 #define CONFIG_BTB                      /* toggle branch predition */
  98 #define CONFIG_ENABLE_36BIT_PHYS        1
  99
 100 #define CONFIG_SYS_CCSRBAR              0xef000000
 101 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 102
 103 /*
 104  * Diagnostics
 105  */
 106 #define CONFIG_SYS_ALT_MEMTEST
 107 #define CONFIG_SYS_MEMTEST_START        0x10000000
 108 #define CONFIG_SYS_MEMTEST_END          0x20000000
 109 #define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY | \
 110                                          CONFIG_SYS_POST_I2C)
 111 #define I2C_ADDR_LIST                   {CONFIG_SYS_I2C_DS1621_ADDR,    \
 112                                          CONFIG_SYS_I2C_DS4510_ADDR,    \
 113                                          CONFIG_SYS_I2C_EEPROM_ADDR,    \
 114                                          CONFIG_SYS_I2C_LM90_ADDR,      \
 115                                          CONFIG_SYS_I2C_PCA953X_ADDR0,  \
 116                                          CONFIG_SYS_I2C_PCA953X_ADDR1,  \
 117                                          CONFIG_SYS_I2C_PCA953X_ADDR2,  \
 118                                          CONFIG_SYS_I2C_PCA953X_ADDR3,  \
 119                                          CONFIG_SYS_I2C_PEX8518_ADDR,   \
 120                                          CONFIG_SYS_I2C_RTC_ADDR}
 121 /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
 122 #define I2C_ADDR_IGNORE_LIST            {0x50}
 123
 124 /*
 125  * Memory map
 126  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 127  * 0x8000_0000  0xbfff_ffff     PCIe1 Mem               1G non-cacheable
 128  * 0xc000_0000  0xcfff_ffff     PCIe2 Mem               256M non-cacheable
 129  * 0xe000_0000  0xe7ff_ffff     SRAM/SSRAM/L1 Cache     128M non-cacheable
 130  * 0xe800_0000  0xe87f_ffff     PCIe1 IO                8M non-cacheable
 131  * 0xe880_0000  0xe8ff_ffff     PCIe2 IO                8M non-cacheable
 132  * 0xee00_0000  0xee00_ffff     Boot page translation   4K non-cacheable
 133  * 0xef00_0000  0xef0f_ffff     CCSR/IMMR               1M non-cacheable
 134  * 0xef80_0000  0xef8f_ffff     NAND Flash              1M non-cacheable
 135  * 0xf000_0000  0xf7ff_ffff     NOR Flash 2             128M non-cacheable
 136  * 0xf800_0000  0xffff_ffff     NOR Flash 1             128M non-cacheable
 137  */
 138
 139 #define CONFIG_SYS_LBC_LCRR     (LCRR_CLKDIV_8 | LCRR_EADC_3)
 140
 141 /*
 142  * NAND flash configuration
 143  */
 144 #define CONFIG_SYS_NAND_BASE            0xef800000
 145 #define CONFIG_SYS_NAND_BASE2           0xef840000 /* Unused at this time */
 146 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
 147                                          CONFIG_SYS_NAND_BASE2}
 148 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 149 #define CONFIG_MTD_NAND_VERIFY_WRITE
 150 #define CONFIG_SYS_NAND_QUIET_TEST      /* 2nd NAND flash not always populated */
 151 #define CONFIG_NAND_FSL_ELBC
 152
 153 /*
 154  * NOR flash configuration
 155  */
 156 #define CONFIG_SYS_FLASH_BASE           0xf8000000
 157 #define CONFIG_SYS_FLASH_BASE2          0xf0000000
 158 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 159 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 160 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 161 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 162 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 163 #define CONFIG_FLASH_CFI_DRIVER
 164 #define CONFIG_SYS_FLASH_CFI
 165 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 166 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff40000, 0xc0000}, \
 167                                                   {0xf7f40000, 0xc0000} }
 168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 169
 170 /*
 171  * Chip select configuration
 172  */
 173 /* NOR Flash 0 on CS0 */
 174 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  | \
 175                                  BR_PS_16               | \
 176                                  BR_V)
 177 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            | \
 178                                  OR_GPCM_CSNT           | \
 179                                  OR_GPCM_XACS           | \
 180                                  OR_GPCM_ACS_DIV2       | \
 181                                  OR_GPCM_SCY_8          | \
 182                                  OR_GPCM_TRLX           | \
 183                                  OR_GPCM_EHTR           | \
 184                                  OR_GPCM_EAD)
 185
 186 /* NOR Flash 1 on CS1 */
 187 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 | \
 188                                  BR_PS_16               | \
 189                                  BR_V)
 190 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 191
 192 /* NAND flash on CS2 */
 193 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   | \
 194                                  (2<<BR_DECC_SHIFT)     | \
 195                                  BR_PS_8                | \
 196                                  BR_MS_FCM              | \
 197                                  BR_V)
 198
 199 /* NAND flash on CS2 */
 200 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB    | \
 201                                  OR_FCM_PGS     | \
 202                                  OR_FCM_CSCT    | \
 203                                  OR_FCM_CST     | \
 204                                  OR_FCM_CHT     | \
 205                                  OR_FCM_SCY_1   | \
 206                                  OR_FCM_TRLX    | \
 207                                  OR_FCM_EHTR)
 208
 209 /* NAND flash on CS3 */
 210 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  | \
 211                                  (2<<BR_DECC_SHIFT)     | \
 212                                  BR_PS_8                | \
 213                                  BR_MS_FCM              | \
 214                                  BR_V)
 215 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 216
 217 /*
 218  * Use L1 as initial stack
 219  */
 220 #define CONFIG_SYS_INIT_RAM_LOCK        1
 221 #define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
 222 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 223
 224 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 225 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 226
 227 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 228 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 229
 230 /*
 231  * Serial Port
 232  */
 233 #define CONFIG_CONS_INDEX               1
 234 #define CONFIG_SYS_NS16550
 235 #define CONFIG_SYS_NS16550_SERIAL
 236 #define CONFIG_SYS_NS16550_REG_SIZE     1
 237 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 238 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 239 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 240 #define CONFIG_SYS_BAUDRATE_TABLE       \
 241         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 242 #define CONFIG_BAUDRATE                 115200
 243 #define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
 244 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 245
 246 /*
 247  * Use the HUSH parser
 248  */
 249 #define CONFIG_SYS_HUSH_PARSER
 250
 251 /*
 252  * Pass open firmware flat tree
 253  */
 254 #define CONFIG_OF_LIBFDT                1
 255 #define CONFIG_OF_BOARD_SETUP           1
 256 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 257
 258 /*
 259  * I2C
 260  */
 261 #define CONFIG_SYS_I2C
 262 #define CONFIG_SYS_I2C_FSL
 263 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 264 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 265 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 266 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 267 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 268 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 269 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 270
 271 /* PEX8518 slave I2C interface */
 272 #define CONFIG_SYS_I2C_PEX8518_ADDR     0x70
 273
 274 /* I2C DS1631 temperature sensor */
 275 #define CONFIG_SYS_I2C_DS1621_ADDR      0x48
 276 #define CONFIG_DTT_DS1621
 277 #define CONFIG_DTT_SENSORS              { 0 }
 278 #define CONFIG_SYS_I2C_LM90_ADDR        0x4c
 279
 280 /* I2C EEPROM - AT24C128B */
 281 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 282 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 283 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
 284 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
 285
 286 /* I2C RTC */
 287 #define CONFIG_RTC_M41T11               1
 288 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 289 #define CONFIG_SYS_M41T11_BASE_YEAR     2000
 290
 291 /* GPIO/EEPROM/SRAM */
 292 #define CONFIG_DS4510
 293 #define CONFIG_SYS_I2C_DS4510_ADDR      0x51
 294
 295 /* GPIO */
 296 #define CONFIG_PCA953X
 297 #define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
 298 #define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
 299 #define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
 300 #define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
 301 #define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
 302
 303 /*
 304  * PU = pulled high, PD = pulled low
 305  * I = input, O = output, IO = input/output
 306  */
 307 /* PCA9557 @ 0x18*/
 308 #define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
 309 #define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select */
 310 #define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
 311 #define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select */
 312 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
 313 #define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Set to 0 to enable NVM writing */
 314 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2        0x40 /* VID2 of ISL6262 */
 315 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3        0x80 /* VID3 of ISL6262 */
 316
 317 /* PCA9557 @ 0x1c*/
 318 #define CONFIG_SYS_PCA953X_XMC0_ROOT0           0x01 /* PU; Low if XMC is RC */
 319 #define CONFIG_SYS_PCA953X_XMC0_MVMR0           0x02 /* XMC EEPROM write protect */
 320 #define CONFIG_SYS_PCA953X_XMC0_WAKE            0x04 /* PU; XMC wake */
 321 #define CONFIG_SYS_PCA953X_XMC0_BIST            0x08 /* PU; XMC built in self test */
 322 #define CONFIG_SYS_PCA953X_XMC_PRESENT          0x10 /* PU; Low if XMC module installed */
 323 #define CONFIG_SYS_PCA953X_PMC_PRESENT          0x20 /* PU; Low if PMC module installed */
 324 #define CONFIG_SYS_PCA953X_PMC0_MONARCH         0x40 /* PMC monarch mode enable */
 325 #define CONFIG_SYS_PCA953X_PMC0_EREADY          0x80 /* PU; PMC PCI eready */
 326
 327 /* PCA9557 @ 0x1e*/
 328 #define CONFIG_SYS_PCA953X_P0_GA0               0x01 /* PU; VPX Geographical address */
 329 #define CONFIG_SYS_PCA953X_P0_GA1               0x02 /* PU; VPX Geographical address */
 330 #define CONFIG_SYS_PCA953X_P0_GA2               0x04 /* PU; VPX Geographical address */
 331 #define CONFIG_SYS_PCA953X_P0_GA3               0x08 /* PU; VPX Geographical address */
 332 #define CONFIG_SYS_PCA953X_P0_GA4               0x10 /* PU; VPX Geographical address */
 333 #define CONFIG_SYS_PCA953X_P0_GAP               0x20 /* PU; tied to VPX P0.GAP */
 334 #define CONFIG_SYS_PCA953X_P1_SYSEN             0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
 335
 336 /* PCA9557 @ 0x1f */
 337 #define CONFIG_SYS_PCA953X_GPIO_VPX0            0x01 /* PU */
 338 #define CONFIG_SYS_PCA953X_GPIO_VPX1            0x02 /* PU */
 339 #define CONFIG_SYS_PCA953X_GPIO_VPX2            0x04 /* PU */
 340 #define CONFIG_SYS_PCA953X_GPIO_VPX3            0x08 /* PU */
 341 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL        0x10 /* PD; I2C master source for FRU SEEPROM */
 342
 343 /*
 344  * General PCI
 345  * Memory space is mapped 1-1, but I/O space must start from 0.
 346  */
 347 /* PCIE1 - VPX P1 */
 348 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 349 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 350 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
 351 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 352 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
 353 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 354
 355 /* PCIE2 - PEX8518 */
 356 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 357 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 358 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 359 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 360 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe8800000
 361 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000      /* 8M */
 362
 363 /*
 364  * Networking options
 365  */
 366 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
 367 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 368 #define CONFIG_TSEC_TBI
 369 #define CONFIG_MII              1       /* MII PHY management */
 370 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 371 #define CONFIG_ETHPRIME         "eTSEC2"
 372
 373 /*
 374  * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
 375  * 1000mbps SGMII link
 376  */
 377 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 378                 TBICR_PHY_RESET \
 379                 | TBICR_FULL_DUPLEX \
 380                 | TBICR_SPEED1_SET \
 381                 )
 382
 383 #define CONFIG_TSEC1            1
 384 #define CONFIG_TSEC1_NAME       "eTSEC1"
 385 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 386 #define TSEC1_PHY_ADDR          1
 387 #define TSEC1_PHYIDX            0
 388 #define CONFIG_HAS_ETH0
 389
 390 #define CONFIG_TSEC2            1
 391 #define CONFIG_TSEC2_NAME       "eTSEC2"
 392 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 393 #define TSEC2_PHY_ADDR          2
 394 #define TSEC2_PHYIDX            0
 395 #define CONFIG_HAS_ETH1
 396
 397 /*
 398  * Command configuration.
 399  */
 400 #include <config_cmd_default.h>
 401
 402 #define CONFIG_CMD_ASKENV
 403 #define CONFIG_CMD_DATE
 404 #define CONFIG_CMD_DHCP
 405 #define CONFIG_CMD_DS4510
 406 #define CONFIG_CMD_DS4510_INFO
 407 #define CONFIG_CMD_DTT
 408 #define CONFIG_CMD_EEPROM
 409 #define CONFIG_CMD_ELF
 410 #define CONFIG_CMD_FLASH
 411 #define CONFIG_CMD_I2C
 412 #define CONFIG_CMD_JFFS2
 413 #define CONFIG_CMD_MII
 414 #define CONFIG_CMD_NAND
 415 #define CONFIG_CMD_NET
 416 #define CONFIG_CMD_PCA953X
 417 #define CONFIG_CMD_PCA953X_INFO
 418 #define CONFIG_CMD_PCI
 419 #define CONFIG_CMD_PCI_ENUM
 420 #define CONFIG_CMD_PING
 421 #define CONFIG_CMD_SAVEENV
 422 #define CONFIG_CMD_SNTP
 423 #define CONFIG_CMD_REGINFO
 424
 425 /*
 426  * Miscellaneous configurable options
 427  */
 428 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 429 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 430 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 431 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 432 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 433 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 434 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 435 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 436 #define CONFIG_CMDLINE_EDITING  1               /* add command line history     */
 437 #define CONFIG_AUTO_COMPLETE    1               /* add autocompletion support */
 438 #define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
 439 #define CONFIG_BOOTDELAY        3               /* -1 disables auto-boot */
 440 #define CONFIG_PANIC_HANG                       /* do not reset board on panic */
 441 #define CONFIG_PREBOOT                          /* enable preboot variable */
 442 #define CONFIG_FIT              1
 443 #define CONFIG_FIT_VERBOSE      1
 444 #define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
 445
 446 /*
 447  * For booting Linux, the board info and command line data
 448  * have to be in the first 16 MB of memory, since this is
 449  * the maximum mapped by the Linux kernel during initialization.
 450  */
 451 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 452 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 453
 454 /*
 455  * Environment Configuration
 456  */
 457 #define CONFIG_ENV_IS_IN_FLASH  1
 458 #define CONFIG_ENV_SECT_SIZE    0x20000         /* 128k (one sector) for env */
 459 #define CONFIG_ENV_SIZE         0x8000
 460 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
 461
 462 /*
 463  * Flash memory map:
 464  * fff80000 - ffffffff     Pri U-Boot (512 KB)
 465  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
 466  * fff00000 - fff3ffff     Pri FDT (256KB)
 467  * fef00000 - ffefffff     Pri OS image (16MB)
 468  * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
 469  *
 470  * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
 471  * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
 472  * f7f00000 - f7f3ffff     Sec FDT (256KB)
 473  * f6f00000 - f7efffff     Sec OS image (16MB)
 474  * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
 475  */
 476 #define CONFIG_UBOOT1_ENV_ADDR  __stringify(0xfff80000)
 477 #define CONFIG_UBOOT2_ENV_ADDR  __stringify(0xf7f80000)
 478 #define CONFIG_FDT1_ENV_ADDR    __stringify(0xfff00000)
 479 #define CONFIG_FDT2_ENV_ADDR    __stringify(0xf7f00000)
 480 #define CONFIG_OS1_ENV_ADDR     __stringify(0xfef00000)
 481 #define CONFIG_OS2_ENV_ADDR     __stringify(0xf6f00000)
 482
 483 #define CONFIG_PROG_UBOOT1                                              \
 484         "$download_cmd $loadaddr $ubootfile; "                          \
 485         "if test $? -eq 0; then "                                       \
 486                 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
 487                 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
 488                 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
 489                 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
 490                 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
 491                 "if test $? -ne 0; then "                               \
 492                         "echo PROGRAM FAILED; "                         \
 493                 "else; "                                                \
 494                         "echo PROGRAM SUCCEEDED; "                      \
 495                 "fi; "                                                  \
 496         "else; "                                                        \
 497                 "echo DOWNLOAD FAILED; "                                \
 498         "fi;"
 499
 500 #define CONFIG_PROG_UBOOT2                                              \
 501         "$download_cmd $loadaddr $ubootfile; "                          \
 502         "if test $? -eq 0; then "                                       \
 503                 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
 504                 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
 505                 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
 506                 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
 507                 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
 508                 "if test $? -ne 0; then "                               \
 509                         "echo PROGRAM FAILED; "                         \
 510                 "else; "                                                \
 511                         "echo PROGRAM SUCCEEDED; "                      \
 512                 "fi; "                                                  \
 513         "else; "                                                        \
 514                 "echo DOWNLOAD FAILED; "                                \
 515         "fi;"
 516
 517 #define CONFIG_BOOT_OS_NET                                              \
 518         "$download_cmd $osaddr $osfile; "                               \
 519         "if test $? -eq 0; then "                                       \
 520                 "if test -n $fdtaddr; then "                            \
 521                         "$download_cmd $fdtaddr $fdtfile; "             \
 522                         "if test $? -eq 0; then "                       \
 523                                 "bootm $osaddr - $fdtaddr; "            \
 524                         "else; "                                        \
 525                                 "echo FDT DOWNLOAD FAILED; "            \
 526                         "fi; "                                          \
 527                 "else; "                                                \
 528                         "bootm $osaddr; "                               \
 529                 "fi; "                                                  \
 530         "else; "                                                        \
 531                 "echo OS DOWNLOAD FAILED; "                             \
 532         "fi;"
 533
 534 #define CONFIG_PROG_OS1                                                 \
 535         "$download_cmd $osaddr $osfile; "                               \
 536         "if test $? -eq 0; then "                                       \
 537                 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
 538                 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
 539                 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
 540                 "if test $? -ne 0; then "                               \
 541                         "echo OS PROGRAM FAILED; "                      \
 542                 "else; "                                                \
 543                         "echo OS PROGRAM SUCCEEDED; "                   \
 544                 "fi; "                                                  \
 545         "else; "                                                        \
 546                 "echo OS DOWNLOAD FAILED; "                             \
 547         "fi;"
 548
 549 #define CONFIG_PROG_OS2                                                 \
 550         "$download_cmd $osaddr $osfile; "                               \
 551         "if test $? -eq 0; then "                                       \
 552                 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
 553                 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
 554                 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
 555                 "if test $? -ne 0; then "                               \
 556                         "echo OS PROGRAM FAILED; "                      \
 557                 "else; "                                                \
 558                         "echo OS PROGRAM SUCCEEDED; "                   \
 559                 "fi; "                                                  \
 560         "else; "                                                        \
 561                 "echo OS DOWNLOAD FAILED; "                             \
 562         "fi;"
 563
 564 #define CONFIG_PROG_FDT1                                                \
 565         "$download_cmd $fdtaddr $fdtfile; "                             \
 566         "if test $? -eq 0; then "                                       \
 567                 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
 568                 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
 569                 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
 570                 "if test $? -ne 0; then "                               \
 571                         "echo FDT PROGRAM FAILED; "                     \
 572                 "else; "                                                \
 573                         "echo FDT PROGRAM SUCCEEDED; "                  \
 574                 "fi; "                                                  \
 575         "else; "                                                        \
 576                 "echo FDT DOWNLOAD FAILED; "                            \
 577         "fi;"
 578
 579 #define CONFIG_PROG_FDT2                                                \
 580         "$download_cmd $fdtaddr $fdtfile; "                             \
 581         "if test $? -eq 0; then "                                       \
 582                 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
 583                 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
 584                 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
 585                 "if test $? -ne 0; then "                               \
 586                         "echo FDT PROGRAM FAILED; "                     \
 587                 "else; "                                                \
 588                         "echo FDT PROGRAM SUCCEEDED; "                  \
 589                 "fi; "                                                  \
 590         "else; "                                                        \
 591                 "echo FDT DOWNLOAD FAILED; "                            \
 592         "fi;"
 593
 594 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 595         "autoload=yes\0"                                                \
 596         "download_cmd=tftp\0"                                           \
 597         "console_args=console=ttyS0,115200\0"                           \
 598         "root_args=root=/dev/nfs rw\0"                                  \
 599         "misc_args=ip=on\0"                                             \
 600         "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 601         "bootfile=/home/user/file\0"                                    \
 602         "osfile=/home/user/board.uImage\0"                              \
 603         "fdtfile=/home/user/board.dtb\0"                                \
 604         "ubootfile=/home/user/u-boot.bin\0"                             \
 605         "fdtaddr=c00000\0"                                              \
 606         "osaddr=0x1000000\0"                                            \
 607         "loadaddr=0x1000000\0"                                          \
 608         "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
 609         "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
 610         "prog_os1="CONFIG_PROG_OS1"\0"                                  \
 611         "prog_os2="CONFIG_PROG_OS2"\0"                                  \
 612         "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
 613         "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
 614         "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
 615         "bootcmd_flash1=run set_bootargs; "                             \
 616                 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
 617         "bootcmd_flash2=run set_bootargs; "                             \
 618                 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
 619         "bootcmd=run bootcmd_flash1\0"
 620 #endif  /* __CONFIG_H */