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Drop support for CONFIG_SKIP_RELOCATE_UBOOT
[karo-tx-uboot.git] / include / configs / zipitz2.h
1 /*
2  * Aeronix Zipit Z2 configuration file
3  *
4  * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of
9  * the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19  * MA 02111-1307 USA
20  */
21
22 #ifndef __CONFIG_H
23 #define __CONFIG_H
24
25 /*
26  * High Level Board Configuration Options
27  */
28 #define CONFIG_PXA27X           1       /* Marvell PXA270 CPU */
29 #define CONFIG_ZIPITZ2          1       /* Zipit Z2 board */
30 #define CONFIG_SYS_TEXT_BASE    0x0
31
32 #undef  BOARD_LATE_INIT
33 #undef  CONFIG_USE_IRQ
34 #undef  CONFIG_SKIP_LOWLEVEL_INIT
35
36 /*
37  * Environment settings
38  */
39 #define CONFIG_ENV_OVERWRITE
40 #define CONFIG_ENV_IS_IN_FLASH          1
41 #define CONFIG_ENV_ADDR                 0x40000
42 #define CONFIG_ENV_SIZE                 0x20000
43
44 #define CONFIG_SYS_MALLOC_LEN           (128*1024)
45 #define CONFIG_ARCH_CPU_INIT
46
47 #define CONFIG_BOOTCOMMAND                                              \
48         "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then "  \
49                 "source 0xa0000000; "                                   \
50         "else "                                                         \
51                 "bootm 0x60000; "                                       \
52         "fi; "
53 #define CONFIG_BOOTARGS                                                 \
54         "console=tty0 console=ttyS2,115200 fbcon=rotate:3"
55 #define CONFIG_TIMESTAMP
56 #define CONFIG_BOOTDELAY                2       /* Autoboot delay */
57 #define CONFIG_CMDLINE_TAG
58 #define CONFIG_SETUP_MEMORY_TAGS
59 #define CONFIG_SYS_TEXT_BASE            0x0
60 #define CONFIG_LZMA                     /* LZMA compression support */
61
62 /*
63  * Serial Console Configuration
64  * STUART - the lower serial port on Colibri board
65  */
66 #define CONFIG_PXA_SERIAL
67 #define CONFIG_STUART                   1
68 #define CONFIG_BAUDRATE                 115200
69 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
70
71 /*
72  * Bootloader Components Configuration
73  */
74 #include <config_cmd_default.h>
75
76 #undef  CONFIG_CMD_NET
77 #define CONFIG_CMD_ENV
78 #undef  CONFIG_CMD_IMLS
79 #define CONFIG_CMD_MMC
80 #define CONFIG_CMD_SPI
81
82 /*
83  * MMC Card Configuration
84  */
85 #ifdef  CONFIG_CMD_MMC
86 #define CONFIG_MMC
87 #define CONFIG_PXA_MMC
88 #define CONFIG_SYS_MMC_BASE             0xF0000000
89 #define CONFIG_CMD_FAT
90 #define CONFIG_CMD_EXT2
91 #define CONFIG_DOS_PARTITION
92 #endif
93
94 /*
95  * SPI and LCD
96  */
97 #ifdef  CONFIG_CMD_SPI
98 #define CONFIG_SOFT_SPI
99 #define CONFIG_LCD
100 #define CONFIG_LMS283GF05
101 #define CONFIG_VIDEO_LOGO
102 #define CONFIG_CMD_BMP
103 #define CONFIG_SPLASH_SCREEN
104 #define CONFIG_SPLASH_SCREEN_ALIGN
105 #define CONFIG_VIDEO_BMP_GZIP
106 #define CONFIG_VIDEO_BMP_RLE8
107 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)
108 #undef  SPI_INIT
109
110 #define SPI_DELAY       udelay(10)
111 #define SPI_SDA(val)    zipitz2_spi_sda(val)
112 #define SPI_SCL(val)    zipitz2_spi_scl(val)
113 #define SPI_READ        zipitz2_spi_read()
114 #ifndef __ASSEMBLY__
115 void zipitz2_spi_sda(int);
116 void zipitz2_spi_scl(int);
117 unsigned char zipitz2_spi_read(void);
118 #endif
119 #endif
120
121 /*
122  * KGDB
123  */
124 #ifdef  CONFIG_CMD_KGDB
125 #define CONFIG_KGDB_BAUDRATE            230400          /* speed to run kgdb serial port */
126 #define CONFIG_KGDB_SER_INDEX           2               /* which serial port to use */
127 #endif
128
129 /*
130  * HUSH Shell Configuration
131  */
132 #define CONFIG_SYS_HUSH_PARSER          1
133 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
134
135 #define CONFIG_SYS_LONGHELP                             /* undef to save memory */
136 #ifdef  CONFIG_SYS_HUSH_PARSER
137 #define CONFIG_SYS_PROMPT               "$ "            /* Monitor Command Prompt */
138 #else
139 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt */
140 #endif
141 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size */
142 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
143 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
144 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
145 #define CONFIG_SYS_DEVICE_NULLDEV       1
146
147 /*
148  * Clock Configuration
149  */
150 #undef  CONFIG_SYS_CLKS_IN_HZ
151 #define CONFIG_SYS_HZ                   3250000         /* Timer @ 3250000 Hz */
152 #define CONFIG_SYS_CPUSPEED             0x190           /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
153
154 /*
155  * Stack sizes
156  */
157 #define CONFIG_STACKSIZE                (128*1024)      /* regular stack */
158 #ifdef  CONFIG_USE_IRQ
159 #define CONFIG_STACKSIZE_IRQ            (4*1024)        /* IRQ stack */
160 #define CONFIG_STACKSIZE_FIQ            (4*1024)        /* FIQ stack */
161 #endif
162
163 /*
164  * DRAM Map
165  */
166 #define CONFIG_NR_DRAM_BANKS            1               /* We have 1 bank of DRAM */
167 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
168 #define PHYS_SDRAM_1_SIZE               0x02000000      /* 32 MB */
169
170 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
171 #define CONFIG_SYS_DRAM_SIZE            0x02000000      /* 32 MB DRAM */
172
173 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
174 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
175
176 #define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_DRAM_BASE
177
178 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
179 #define CONFIG_SYS_INIT_SP_ADDR         (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1 + 2048)
180
181 /*
182  * NOR FLASH
183  */
184 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
185 #define PHYS_FLASH_SIZE                 0x00800000      /* 8 MB */
186 #define PHYS_FLASH_SECT_SIZE            0x00010000      /* 64 KB sectors */
187 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
188
189 #define CONFIG_SYS_FLASH_CFI
190 #define CONFIG_FLASH_CFI_DRIVER         1
191 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
192
193 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
194 #define CONFIG_SYS_MONITOR_LEN          PHYS_FLASH_SECT_SIZE
195
196 #define CONFIG_SYS_MAX_FLASH_BANKS      1
197 #define CONFIG_SYS_MAX_FLASH_SECT       256
198
199 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
200
201 #define CONFIG_SYS_FLASH_ERASE_TOUT     (2*CONFIG_SYS_HZ)
202 #define CONFIG_SYS_FLASH_WRITE_TOUT     (2*CONFIG_SYS_HZ)
203 #define CONFIG_SYS_FLASH_LOCK_TOUT      (2*CONFIG_SYS_HZ)
204 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (2*CONFIG_SYS_HZ)
205 #define CONFIG_SYS_FLASH_PROTECTION
206
207 /*
208  * GPIO settings
209  */
210 #define CONFIG_SYS_GAFR0_L_VAL  0x02000140
211 #define CONFIG_SYS_GAFR0_U_VAL  0x59188000
212 #define CONFIG_SYS_GAFR1_L_VAL  0x63900002
213 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa03950
214 #define CONFIG_SYS_GAFR2_L_VAL  0x0aaaaaaa
215 #define CONFIG_SYS_GAFR2_U_VAL  0x29000308
216 #define CONFIG_SYS_GAFR3_L_VAL  0x54000000
217 #define CONFIG_SYS_GAFR3_U_VAL  0x000000d5
218 #define CONFIG_SYS_GPCR0_VAL    0x00000000
219 #define CONFIG_SYS_GPCR1_VAL    0x00000020
220 #define CONFIG_SYS_GPCR2_VAL    0x00000000
221 #define CONFIG_SYS_GPCR3_VAL    0x00000000
222 #define CONFIG_SYS_GPDR0_VAL    0xdafcee00
223 #define CONFIG_SYS_GPDR1_VAL    0xffa3aaab
224 #define CONFIG_SYS_GPDR2_VAL    0x8fe9ffff
225 #define CONFIG_SYS_GPDR3_VAL    0x001b1f8a
226 #define CONFIG_SYS_GPSR0_VAL    0x06080400
227 #define CONFIG_SYS_GPSR1_VAL    0x007f0000
228 #define CONFIG_SYS_GPSR2_VAL    0x032a0000
229 #define CONFIG_SYS_GPSR3_VAL    0x00000180
230
231 #define CONFIG_SYS_PSSR_VAL     0x30
232
233 /*
234  * Clock settings
235  */
236 #define CONFIG_SYS_CKEN         0x00511220
237 #define CONFIG_SYS_CCCR         0x00000190
238
239 /*
240  * Memory settings
241  */
242 #define CONFIG_SYS_MSC0_VAL     0x2ffc38f8
243 #define CONFIG_SYS_MSC1_VAL     0x0000ccd1
244 #define CONFIG_SYS_MSC2_VAL     0x0000b884
245 #define CONFIG_SYS_MDCNFG_VAL   0x08000ba9
246 #define CONFIG_SYS_MDREFR_VAL   0x2011a01e
247 #define CONFIG_SYS_MDMRS_VAL    0x00000000
248 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
249 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
250
251 /*
252  * PCMCIA and CF Interfaces
253  */
254 #define CONFIG_SYS_MECR_VAL     0x00000001
255 #define CONFIG_SYS_MCMEM0_VAL   0x00014307
256 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
257 #define CONFIG_SYS_MCATT0_VAL   0x0001c787
258 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
259 #define CONFIG_SYS_MCIO0_VAL    0x0001430f
260 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
261
262 #endif  /* __CONFIG_H */