include/configs/zipitz2.h

   1 /*
   2  * Aeronix Zipit Z2 configuration file
   3  *
   4  * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef __CONFIG_H
  23 #define __CONFIG_H
  24
  25 /*
  26  * High Level Board Configuration Options
  27  */
  28 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
  29 #define CONFIG_ZIPITZ2          1       /* Zipit Z2 board */
  30 #define CONFIG_SYS_TEXT_BASE    0x0
  31
  32 #undef  CONFIG_BOARD_LATE_INIT
  33 #undef  CONFIG_SKIP_LOWLEVEL_INIT
  34 #define CONFIG_PREBOOT
  35
  36 /*
  37  * Environment settings
  38  */
  39 #define CONFIG_ENV_OVERWRITE
  40 #define CONFIG_ENV_IS_IN_FLASH          1
  41 #define CONFIG_ENV_ADDR                 0x40000
  42 #define CONFIG_ENV_SIZE                 0x20000
  43
  44 #define CONFIG_SYS_MALLOC_LEN           (128*1024)
  45 #define CONFIG_ARCH_CPU_INIT
  46
  47 #define CONFIG_BOOTCOMMAND                                              \
  48         "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
  49         "then "                                                         \
  50                 "source 0xa0000000; "                                   \
  51         "else "                                                         \
  52                 "bootm 0x60000; "                                       \
  53         "fi; "
  54 #define CONFIG_BOOTARGS                                                 \
  55         "console=tty0 console=ttyS2,115200 fbcon=rotate:3"
  56 #define CONFIG_TIMESTAMP
  57 #define CONFIG_BOOTDELAY                2       /* Autoboot delay */
  58 #define CONFIG_CMDLINE_TAG
  59 #define CONFIG_SETUP_MEMORY_TAGS
  60 #define CONFIG_SYS_TEXT_BASE            0x0
  61 #define CONFIG_LZMA                     /* LZMA compression support */
  62
  63 /*
  64  * Serial Console Configuration
  65  * STUART - the lower serial port on Colibri board
  66  */
  67 #define CONFIG_PXA_SERIAL
  68 #define CONFIG_STUART                   1
  69 #define CONFIG_CONS_INDEX               2
  70 #define CONFIG_BAUDRATE                 115200
  71
  72 /*
  73  * Bootloader Components Configuration
  74  */
  75 #include <config_cmd_default.h>
  76
  77 #undef  CONFIG_CMD_NET
  78 #undef  CONFIG_CMD_NFS
  79 #define CONFIG_CMD_ENV
  80 #undef  CONFIG_CMD_IMLS
  81 #define CONFIG_CMD_MMC
  82 #define CONFIG_CMD_SPI
  83
  84 /*
  85  * MMC Card Configuration
  86  */
  87 #ifdef  CONFIG_CMD_MMC
  88 #define CONFIG_MMC
  89 #define CONFIG_GENERIC_MMC
  90 #define CONFIG_PXA_MMC_GENERIC
  91 #define CONFIG_SYS_MMC_BASE             0xF0000000
  92 #define CONFIG_CMD_FAT
  93 #define CONFIG_CMD_EXT2
  94 #define CONFIG_DOS_PARTITION
  95 #endif
  96
  97 /*
  98  * SPI and LCD
  99  */
 100 #ifdef  CONFIG_CMD_SPI
 101 #define CONFIG_SOFT_SPI
 102 #define CONFIG_LCD
 103 #define CONFIG_LMS283GF05
 104 #define CONFIG_VIDEO_LOGO
 105 #define CONFIG_CMD_BMP
 106 #define CONFIG_SPLASH_SCREEN
 107 #define CONFIG_SPLASH_SCREEN_ALIGN
 108 #define CONFIG_VIDEO_BMP_GZIP
 109 #define CONFIG_VIDEO_BMP_RLE8
 110 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)
 111 #undef  SPI_INIT
 112
 113 #define SPI_DELAY       udelay(10)
 114 #define SPI_SDA(val)    zipitz2_spi_sda(val)
 115 #define SPI_SCL(val)    zipitz2_spi_scl(val)
 116 #define SPI_READ        zipitz2_spi_read()
 117 #ifndef __ASSEMBLY__
 118 void zipitz2_spi_sda(int);
 119 void zipitz2_spi_scl(int);
 120 unsigned char zipitz2_spi_read(void);
 121 #endif
 122 #endif
 123
 124 /*
 125  * KGDB
 126  */
 127 #ifdef  CONFIG_CMD_KGDB
 128 #define CONFIG_KGDB_BAUDRATE            230400          /* speed to run kgdb serial port */
 129 #define CONFIG_KGDB_SER_INDEX           2               /* which serial port to use */
 130 #endif
 131
 132 /*
 133  * HUSH Shell Configuration
 134  */
 135 #define CONFIG_SYS_HUSH_PARSER          1
 136
 137 #define CONFIG_SYS_LONGHELP                             /* undef to save memory */
 138 #ifdef  CONFIG_SYS_HUSH_PARSER
 139 #define CONFIG_SYS_PROMPT               "$ "            /* Monitor Command Prompt */
 140 #else
 141 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt */
 142 #endif
 143 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size */
 144 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 145 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 146 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 147 #define CONFIG_SYS_DEVICE_NULLDEV       1
 148
 149 /*
 150  * Clock Configuration
 151  */
 152 #undef  CONFIG_SYS_CLKS_IN_HZ
 153 #define CONFIG_SYS_HZ                   3250000         /* Timer @ 3250000 Hz */
 154 #define CONFIG_SYS_CPUSPEED             0x190           /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
 155
 156 /*
 157  * SRAM Map
 158  */
 159 #define PHYS_SRAM                       0x5c000000      /* SRAM Bank #1 */
 160 #define PHYS_SRAM_SIZE                  0x00040000      /* 256k */
 161
 162 /*
 163  * DRAM Map
 164  */
 165 #define CONFIG_NR_DRAM_BANKS            1               /* We have 1 bank of DRAM */
 166 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
 167 #define PHYS_SDRAM_1_SIZE               0x02000000      /* 32 MB */
 168
 169 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
 170 #define CONFIG_SYS_DRAM_SIZE            0x02000000      /* 32 MB DRAM */
 171
 172 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
 173 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
 174
 175 #define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_DRAM_BASE
 176
 177 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 178 #define CONFIG_SYS_INIT_SP_ADDR         (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
 179
 180 /*
 181  * NOR FLASH
 182  */
 183 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
 184 #define PHYS_FLASH_SIZE                 0x00800000      /* 8 MB */
 185 #define PHYS_FLASH_SECT_SIZE            0x00010000      /* 64 KB sectors */
 186 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 187
 188 #define CONFIG_SYS_FLASH_CFI
 189 #define CONFIG_FLASH_CFI_DRIVER         1
 190 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 191
 192 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 193 #define CONFIG_SYS_MONITOR_LEN          PHYS_FLASH_SECT_SIZE
 194
 195 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 196 #define CONFIG_SYS_MAX_FLASH_SECT       256
 197
 198 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 199
 200 #define CONFIG_SYS_FLASH_ERASE_TOUT     (2*CONFIG_SYS_HZ)
 201 #define CONFIG_SYS_FLASH_WRITE_TOUT     (2*CONFIG_SYS_HZ)
 202 #define CONFIG_SYS_FLASH_LOCK_TOUT      (2*CONFIG_SYS_HZ)
 203 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (2*CONFIG_SYS_HZ)
 204 #define CONFIG_SYS_FLASH_PROTECTION
 205
 206 /*
 207  * GPIO settings
 208  */
 209 #define CONFIG_SYS_GAFR0_L_VAL  0x02000140
 210 #define CONFIG_SYS_GAFR0_U_VAL  0x59188000
 211 #define CONFIG_SYS_GAFR1_L_VAL  0x63900002
 212 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa03950
 213 #define CONFIG_SYS_GAFR2_L_VAL  0x0aaaaaaa
 214 #define CONFIG_SYS_GAFR2_U_VAL  0x29000308
 215 #define CONFIG_SYS_GAFR3_L_VAL  0x54000000
 216 #define CONFIG_SYS_GAFR3_U_VAL  0x000000d5
 217 #define CONFIG_SYS_GPCR0_VAL    0x00000000
 218 #define CONFIG_SYS_GPCR1_VAL    0x00000020
 219 #define CONFIG_SYS_GPCR2_VAL    0x00000000
 220 #define CONFIG_SYS_GPCR3_VAL    0x00000000
 221 #define CONFIG_SYS_GPDR0_VAL    0xdafcee00
 222 #define CONFIG_SYS_GPDR1_VAL    0xffa3aaab
 223 #define CONFIG_SYS_GPDR2_VAL    0x8fe9ffff
 224 #define CONFIG_SYS_GPDR3_VAL    0x001b1f8a
 225 #define CONFIG_SYS_GPSR0_VAL    0x06080400
 226 #define CONFIG_SYS_GPSR1_VAL    0x007f0000
 227 #define CONFIG_SYS_GPSR2_VAL    0x032a0000
 228 #define CONFIG_SYS_GPSR3_VAL    0x00000180
 229
 230 #define CONFIG_SYS_PSSR_VAL     0x30
 231
 232 /*
 233  * Clock settings
 234  */
 235 #define CONFIG_SYS_CKEN         0x00511220
 236 #define CONFIG_SYS_CCCR         0x00000190
 237
 238 /*
 239  * Memory settings
 240  */
 241 #define CONFIG_SYS_MSC0_VAL     0x2ffc38f8
 242 #define CONFIG_SYS_MSC1_VAL     0x0000ccd1
 243 #define CONFIG_SYS_MSC2_VAL     0x0000b884
 244 #define CONFIG_SYS_MDCNFG_VAL   0x08000ba9
 245 #define CONFIG_SYS_MDREFR_VAL   0x2011a01e
 246 #define CONFIG_SYS_MDMRS_VAL    0x00000000
 247 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
 248 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 249
 250 /*
 251  * PCMCIA and CF Interfaces
 252  */
 253 #define CONFIG_SYS_MECR_VAL     0x00000001
 254 #define CONFIG_SYS_MCMEM0_VAL   0x00014307
 255 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 256 #define CONFIG_SYS_MCATT0_VAL   0x0001c787
 257 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 258 #define CONFIG_SYS_MCIO0_VAL    0x0001430f
 259 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 260
 261 #endif  /* __CONFIG_H */