ARM: omap4: add platform specific info for GPMC and ELM controllers

[karo-tx-uboot.git] / arch / arm / include / asm / omap_common.h

diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 0dbe81b59c64c1d9c0b1b0a6077b569e68e7e28f..729723afefec8dc0460777cba60465c70458403d 100644 (file)
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -4,23 +4,7 @@
  *
  * Aneesh V <aneesh@ti.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef        _OMAP_COMMON_H_
 #define        _OMAP_COMMON_H_
@@ -89,6 +73,7 @@ struct prcm_regs {
        u32 cm_ssc_deltamstep_dpll_ddrphy;
        u32 cm_clkmode_dpll_dsp;
        u32 cm_shadow_freq_config1;
+       u32 cm_clkmode_dpll_gmac;
        u32 cm_mpu_mpu_clkctrl;
 
        /* cm1.dsp */
@@ -158,6 +143,8 @@ struct prcm_regs {
        u32 cm_div_m2_dpll_unipro;
        u32 cm_ssc_deltamstep_dpll_unipro;
        u32 cm_ssc_modfreqdiv_dpll_unipro;
+       u32 cm_coreaon_usb_phy_core_clkctrl;
+       u32 cm_coreaon_usb_phy2_core_clkctrl;
 
        /* cm2.core */
        u32 cm_coreaon_bandgap_clkctrl;
@@ -239,8 +226,11 @@ struct prcm_regs {
        u32 cm_l3init_hsusbotg_clkctrl;
        u32 cm_l3init_hsusbtll_clkctrl;
        u32 cm_l3init_p1500_clkctrl;
+       u32 cm_l3init_sata_clkctrl;
        u32 cm_l3init_fsusb_clkctrl;
        u32 cm_l3init_ocp2scp1_clkctrl;
+       u32 cm_l3init_ocp2scp3_clkctrl;
+       u32 cm_l3init_usb_otg_ss_clkctrl;
 
        u32 prm_irqstatus_mpu_2;
 
@@ -281,6 +271,7 @@ struct prcm_regs {
        u32 cm_l4per_mmcsd4_clkctrl;
        u32 cm_l4per_msprohg_clkctrl;
        u32 cm_l4per_slimbus2_clkctrl;
+       u32 cm_l4per_qspi_clkctrl;
        u32 cm_l4per_uart1_clkctrl;
        u32 cm_l4per_uart2_clkctrl;
        u32 cm_l4per_uart3_clkctrl;
@@ -325,12 +316,6 @@ struct prcm_regs {
        u32 prm_vc_val_bypass;
        u32 prm_vc_cfg_i2c_mode;
        u32 prm_vc_cfg_i2c_clk;
-       u32 prm_sldo_core_setup;
-       u32 prm_sldo_core_ctrl;
-       u32 prm_sldo_mpu_setup;
-       u32 prm_sldo_mpu_ctrl;
-       u32 prm_sldo_mm_setup;
-       u32 prm_sldo_mm_ctrl;
        u32 prm_abbldo_mpu_setup;
        u32 prm_abbldo_mpu_ctrl;
 
@@ -355,11 +340,20 @@ struct prcm_regs {
        /* SCRM stuff, used by some boards */
        u32 scrm_auxclk0;
        u32 scrm_auxclk1;
+
+       /* GMAC Clk Ctrl */
+       u32 cm_gmac_gmac_clkctrl;
+       u32 cm_gmac_clkstctrl;
 };
 
 struct omap_sys_ctrl_regs {
        u32 control_status;
+       u32 control_core_mac_id_0_lo;
+       u32 control_core_mac_id_0_hi;
+       u32 control_core_mac_id_1_lo;
+       u32 control_core_mac_id_1_hi;
        u32 control_std_fuse_opp_vdd_mpu_2;
+       u32 control_phy_power_usb;
        u32 control_core_mmr_lock1;
        u32 control_core_mmr_lock2;
        u32 control_core_mmr_lock3;
@@ -373,6 +367,7 @@ struct omap_sys_ctrl_regs {
        u32 control_ldosram_mpu_voltage_ctrl;
        u32 control_ldosram_core_voltage_ctrl;
        u32 control_usbotghs_ctrl;
+       u32 control_phy_power_sata;
        u32 control_padconf_core_base;
        u32 control_paconf_global;
        u32 control_paconf_mode;
@@ -499,6 +494,7 @@ struct dplls {
        const struct dpll_params *iva;
        const struct dpll_params *usb;
        const struct dpll_params *ddr;
+       const struct dpll_params *gmac;
 };
 
 struct pmic_data {
@@ -571,7 +567,6 @@ u32 omap_ddr_clk(void);
 u32 get_sys_clk_index(void);
 void enable_basic_clocks(void);
 void enable_basic_uboot_clocks(void);
-void enable_non_essential_clocks(void);
 void scale_vcores(struct vcores_data const *);
 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
@@ -579,6 +574,8 @@ void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
               u32 txdone, u32 txdone_mask, u32 opp);
 s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
 
+void usb_fake_mac_from_die_id(u32 *id);
+
 /* HW Init Context */
 #define OMAP_INIT_CONTEXT_SPL                  0
 #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR       1
@@ -611,6 +608,14 @@ static inline u8 is_omap54xx(void)
        extern u32 *const omap_si_rev;
        return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
 }
+
+#define DRA7XX         0x07000000
+
+static inline u8 is_dra7xx(void)
+{
+       extern u32 *const omap_si_rev;
+       return ((*omap_si_rev & 0xFF000000) == DRA7XX);
+}
 #endif
 
 /*
@@ -628,6 +633,7 @@ static inline u8 is_omap54xx(void)
 #define OMAP4430_ES2_3 0x44300230
 #define OMAP4460_ES1_0 0x44600100
 #define OMAP4460_ES1_1 0x44600110
+#define OMAP4470_ES1_0 0x44700100
 
 /* omap5 */
 #define OMAP5430_SILICON_ID_INVALID    0
@@ -638,6 +644,7 @@ static inline u8 is_omap54xx(void)
 
 /* DRA7XX */
 #define DRA752_ES1_0   0x07520100
+#define DRA752_ES1_1   0x07520110
 
 /*
  * SRAM scratch space entries