kconfig: arm: move ARCH_MX? out of choice which selects TARGETs that depend on those

[karo-tx-uboot.git] / arch / arm / lib / asm-offsets.c

diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c
index b0c26e5d689318195343152926eac50699cdd3d7..0c729c2617c609ecbac09abb3f467a74b94083a1 100644 (file)
--- a/arch/arm/lib/asm-offsets.c
+++ b/arch/arm/lib/asm-offsets.c
@@ -15,20 +15,18 @@
 #include <common.h>
 #include <linux/kbuild.h>
 
-#if defined(CONFIG_MB86R0x)
-#include <asm/arch/mb86r0x.h>
-#endif
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
-       || defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX35) \
+       || defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
 #include <asm/arch/imx-regs.h>
 #endif
+#if defined(CONFIG_ARCH_MX6)
+#include <asm/arch/crm_regs.h>
+#endif
 
 int main(void)
 {
        /*
         * TODO : Check if each entry in this file is really necessary.
-        *   - struct mb86r0x_ddr2
-        *   - struct mb86r0x_memc
         *   - struct esdramc_regs
         *   - struct max_regs
         *   - struct aips_regs
@@ -40,48 +38,7 @@ int main(void)
         * code. Is it better to define the macros directly in headers?
         */
 
-#if defined(CONFIG_MB86R0x)
-       /* ddr2 controller */
-       DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
-       DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
-       DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
-       DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
-       DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
-       DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
-       DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
-       DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
-       DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
-       DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
-       DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
-       DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
-       DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
-       DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
-       DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
-
-       /* clock reset generator */
-       DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
-       DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
-       DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
-       DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
-       DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
-       DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
-
-       /* chip control module */
-       DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
-
-       /* external bus interface */
-       DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
-       DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
-       DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
-       DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
-       DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
-       DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
-       DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
-       DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
-       DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
-#endif
-
-#if defined(CONFIG_MX25)
+#if defined(CONFIG_SOC_MX25)
        /* Clock Control Module */
        DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
        DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
@@ -117,7 +74,7 @@ int main(void)
        DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
 #endif
 
-#if defined(CONFIG_MX27)
+#if defined(CONFIG_SOC_MX27)
        DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
        DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
        DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
@@ -143,7 +100,7 @@ int main(void)
                offsetof(struct system_control_regs, fmcr));
 #endif
 
-#if defined(CONFIG_MX35)
+#if defined(CONFIG_SOC_MX35)
        /* Round up to make sure size gives nice stack alignment */
        DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
        DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
@@ -193,7 +150,7 @@ int main(void)
        DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
 #endif
 
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#if defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53)
        /* Round up to make sure size gives nice stack alignment */
        DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
        DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
@@ -229,7 +186,7 @@ int main(void)
        DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
        DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
        DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
-#if defined(CONFIG_MX53)
+#if defined(CONFIG_SOC_MX53)
        DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
 #endif
 
@@ -243,6 +200,43 @@ int main(void)
        DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
        DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
 #endif
-
+#if defined(CONFIG_ARCH_MX6)
+       DEFINE(CCM_CCR, offsetof(struct mxc_ccm_reg, ccr));
+       DEFINE(CCM_CCDR, offsetof(struct mxc_ccm_reg, ccdr));
+       DEFINE(CCM_CSR, offsetof(struct mxc_ccm_reg, csr));
+       DEFINE(CCM_CCSR, offsetof(struct mxc_ccm_reg, ccsr));
+       DEFINE(CCM_CACRR, offsetof(struct mxc_ccm_reg, cacrr));
+       DEFINE(CCM_CBCDR, offsetof(struct mxc_ccm_reg, cbcdr));
+       DEFINE(CCM_CBCMR, offsetof(struct mxc_ccm_reg, cbcmr));
+       DEFINE(CCM_CSCMR1, offsetof(struct mxc_ccm_reg, cscmr1));
+       DEFINE(CCM_CSCMR2, offsetof(struct mxc_ccm_reg, cscmr2));
+       DEFINE(CCM_CSCDR1, offsetof(struct mxc_ccm_reg, cscdr1));
+       DEFINE(CCM_CS1CDR, offsetof(struct mxc_ccm_reg, cs1cdr));
+       DEFINE(CCM_CS2CDR, offsetof(struct mxc_ccm_reg, cs2cdr));
+       DEFINE(CCM_CDCDR, offsetof(struct mxc_ccm_reg, cdcdr));
+       DEFINE(CCM_CHSCCDR, offsetof(struct mxc_ccm_reg, chsccdr));
+       DEFINE(CCM_CSCDR2, offsetof(struct mxc_ccm_reg, cscdr2));
+       DEFINE(CCM_CSCDR3, offsetof(struct mxc_ccm_reg, cscdr3));
+       DEFINE(CCM_CSCDR4, offsetof(struct mxc_ccm_reg, cscdr4));
+       DEFINE(CCM_CDHIPR, offsetof(struct mxc_ccm_reg, cdhipr));
+       DEFINE(CCM_CDCR, offsetof(struct mxc_ccm_reg, cdcr));
+       DEFINE(CCM_CTOR, offsetof(struct mxc_ccm_reg, ctor));
+       DEFINE(CCM_CLPCR, offsetof(struct mxc_ccm_reg, clpcr));
+       DEFINE(CCM_CISR, offsetof(struct mxc_ccm_reg, cisr));
+       DEFINE(CCM_CIMR, offsetof(struct mxc_ccm_reg, cimr));
+       DEFINE(CCM_CCOSR, offsetof(struct mxc_ccm_reg, ccosr));
+       DEFINE(CCM_CGPR, offsetof(struct mxc_ccm_reg, cgpr));
+       DEFINE(CCM_CCGR0, offsetof(struct mxc_ccm_reg, CCGR0));
+       DEFINE(CCM_CCGR1, offsetof(struct mxc_ccm_reg, CCGR1));
+       DEFINE(CCM_CCGR2, offsetof(struct mxc_ccm_reg, CCGR2));
+       DEFINE(CCM_CCGR3, offsetof(struct mxc_ccm_reg, CCGR3));
+       DEFINE(CCM_CCGR4, offsetof(struct mxc_ccm_reg, CCGR4));
+       DEFINE(CCM_CCGR5, offsetof(struct mxc_ccm_reg, CCGR5));
+       DEFINE(CCM_CCGR6, offsetof(struct mxc_ccm_reg, CCGR6));
+       DEFINE(CCM_CCGR7, offsetof(struct mxc_ccm_reg, CCGR7));
+       DEFINE(CCM_CMEOR, offsetof(struct mxc_ccm_reg, cmeor));
+
+       DEFINE(ANATOP_PLL_ENET, offsetof(struct anatop_regs, pll_enet));
+#endif
        return 0;
 }