ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin
ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
+ifeq ($(CONFIG_SPL_FSL_PBL),y)
+ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
+else
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
+endif
ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE
$(call if_changed,cat)
+#Add a target to create boot binary having SPL binary in PBI format
+#concatenated with u-boot binary. It is need by PowerPC SoC having
+#internal SRAM <= 512KB.
+MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
+ -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
+
+spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage)
+
+OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
+ --gap-fill=0xff
+
+u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl u-boot.bin FORCE
+ $(call if_changed,pad_cat)
+
# PPC4xx needs the SPL at the end of the image, since the reset vector
# is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target
# and need to introduce a new build target with the full blown U-Boot
In this mode, a single differential clock is used to supply
clocks to the sysclock, ddrclock and usbclock.
+ CONFIG_SYS_CPC_REINIT_F
+ This CONFIG is defined when the CPC is configured as SRAM at the
+ time of U-boot entry and is required to be re-initialized.
+
+ CONFIG_DEEP_SLEEP
+ Inidcates this SoC supports deep sleep feature. If deep sleep is
+ supported, core will start to execute uboot when wakes up.
+
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
CONFIG_SYS_FSL_DDRC_GEN3
Freescale DDR3 controller.
+ CONFIG_SYS_FSL_DDRC_GEN4
+ Freescale DDR4 controller.
+
CONFIG_SYS_FSL_DDRC_ARM_GEN3
Freescale DDR3 controller for ARM-based SoCs.
CONFIG_SYS_FSL_DDR3
Board config to use DDR3. It can be enabled for SoCs with
- Freescale DDR3 controllers.
+ Freescale DDR3 or DDR3L controllers.
+
+ CONFIG_SYS_FSL_DDR3L
+ Board config to use DDR3L. It can be enabled for SoCs with
+ DDR3L controllers.
+
+ CONFIG_SYS_FSL_DDR4
+ Board config to use DDR4. It can be enabled for SoCs with
+ DDR4 controllers.
CONFIG_SYS_FSL_IFC_BE
Defines the IFC controller register space as Big Endian
PBI commands can be used to configure SoC before it starts the execution.
Please refer doc/README.pblimage for more details
+ CONFIG_SPL_FSL_PBL
+ It adds a target to create boot binary having SPL binary in PBI format
+ concatenated with u-boot binary.
+
CONFIG_SYS_FSL_DDR_BE
Defines the DDR controller register space as Big Endian
continuing (the hardware starts execution after just
loading the first page rather than the full 4K).
+ CONFIG_SPL_SKIP_RELOCATE
+ Avoid SPL relocation
+
CONFIG_SPL_NAND_BASE
Include nand_base.c in the SPL. Requires
CONFIG_SPL_NAND_DRIVERS.
are used to identify the storage device (NOR flash, SPI, etc) and the address
within that device.
-- CONFIG_SYS_QE_FMAN_FW_ADDR
- The address in the storage device where the firmware is located. The
+- CONFIG_SYS_FMAN_FW_ADDR
+ The address in the storage device where the FMAN microcode is located. The
+ meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+ is also specified.
+
+- CONFIG_SYS_QE_FW_ADDR
+ The address in the storage device where the QE microcode is located. The
meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
is also specified.
obj-y += cpu_init.o
obj-y += cpu_init_early.o
obj-y += interrupts.o
+ifneq ($(CONFIG_QEMU_E500),y)
obj-y += speed.o
+endif
obj-y += tlb.o
obj-y += traps.o
}
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
+/*
+ * This workaround can be implemented in PBI, or by u-boot.
+ */
+static void check_erratum_a007212(void)
+{
+ u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
+
+ if (in_be32(plldgdcr) & 0x1fe) {
+ /* check if PLL ratio is set by workaround */
+ puts("Work-around for Erratum A007212 enabled\n");
+ }
+}
+#endif
+
static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
puts("Work-around for Erratum A005125 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007075
+ if (has_erratum_a007075())
+ puts("Work-around for Erratum A007075 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
if (has_erratum_a006261())
puts("Work-around for Erratum A006261 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
+ check_erratum_a007212();
+#endif
+
return 0;
}
get_sys_info(&sysinfo);
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+ if (sysinfo.diff_sysclk == 1)
+ puts("Single Source Clock Configuration\n");
+#endif
+
puts("Clock Configuration:");
for_each_cpu(i, core, nr_cores, mask) {
if (!(i & 3))
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
#define CONFIG_SYS_FSL_TBCLK_DIV 8
#endif
-unsigned long get_tbclk (void)
+__weak unsigned long get_tbclk (void)
{
unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
!defined(CONFIG_SYS_INIT_L2_ADDR)
phys_size_t initdram(int board_type)
{
-#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
+#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
+ defined(CONFIG_QEMU_E500)
return fsl_ddr_sdram_size();
#else
return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif
#include "../../../../drivers/block/fsl_sata.h"
+#ifdef CONFIG_U_QE
+#include "../../../../drivers/qe/qe.h"
+#endif
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+/*
+ * For deriving usb clock from 100MHz sysclk, reference divisor is set
+ * to a value of 5, which gives an intermediate value 20(100/5). The
+ * multiplication factor integer is set to 24, which when multiplied to
+ * above intermediate value provides clock for usb ip.
+ */
+void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
+{
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+ if (sysinfo.diff_sysclk == 1) {
+ clrbits_be32(&usb_phy->pllprg[1],
+ CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
+ setbits_be32(&usb_phy->pllprg[1],
+ CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
+ CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
+ CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
+ }
+}
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
{
#endif
-#ifdef CONFIG_QE
+#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
int open_drain, int assign);
#endif
#ifdef CONFIG_SYS_FSL_CPC
-static void enable_cpc(void)
+#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
+static void disable_cpc_sram(void)
{
int i;
- u32 size = 0;
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
- u32 cpccfg0 = in_be32(&cpc->cpccfg0);
- size += CPC_CFG0_SZ_K(cpccfg0);
-#ifdef CONFIG_RAMBOOT_PBL
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
/* find and disable LAW of SRAM */
struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
out_be32(&cpc->cpccsr0, 0);
out_be32(&cpc->cpcsrcr0, 0);
}
+ }
+}
#endif
+static void enable_cpc(void)
+{
+ int i;
+ u32 size = 0;
+
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+
+ for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+ u32 cpccfg0 = in_be32(&cpc->cpccfg0);
+ size += CPC_CFG0_SZ_K(cpccfg0);
+
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
#endif
}
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
+void fsl_erratum_a007212_workaround(void)
+{
+ ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 ddr_pll_ratio;
+ u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
+ u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
+ u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+ u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
+ u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+ u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
+ u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
+#endif
+#endif
+ /*
+ * Even this workaround applies to selected version of SoCs, it is
+ * safe to apply to all versions, with the limitation of odd ratios.
+ * If RCW has disabled DDR PLL, we have to apply this workaround,
+ * otherwise DDR will not work.
+ */
+ ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
+ FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
+ FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
+ /* check if RCW sets ratio to 0, required by this workaround */
+ if (ddr_pll_ratio != 0)
+ return;
+ ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
+ FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
+ FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
+ /* check if reserved bits have the desired ratio */
+ if (ddr_pll_ratio == 0) {
+ printf("Error: Unknown DDR PLL ratio!\n");
+ return;
+ }
+ ddr_pll_ratio >>= 1;
+
+ setbits_be32(plldadcr1, 0x02000001);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+ setbits_be32(plldadcr2, 0x02000001);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+ setbits_be32(plldadcr3, 0x02000001);
+#endif
+#endif
+ setbits_be32(dpdovrcr4, 0xe0000000);
+ out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+ out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+ out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
+#endif
+#endif
+ udelay(100);
+ clrbits_be32(plldadcr1, 0x02000001);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+ clrbits_be32(plldadcr2, 0x02000001);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+ clrbits_be32(plldadcr3, 0x02000001);
+#endif
+#endif
+ clrbits_be32(dpdovrcr4, 0xe0000000);
+}
+#endif
+
void cpu_init_f (void)
{
extern void m8560_cpm_reset (void);
#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
#endif
#if defined(CONFIG_SECURE_BOOT)
struct law_entry law;
law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
if (law.index != -1)
disable_law(law.index);
+
+#if defined(CONFIG_SYS_CPC_REINIT_F)
+ disable_cpc_sram();
+#endif
#endif
#ifdef CONFIG_CPM2
#if defined(CONFIG_CPM2)
m8560_cpm_reset();
#endif
-#ifdef CONFIG_QE
+
+#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
/* Config QE ioports */
config_qe_ioports();
#endif
+
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif
in_be32(&gur->dcsrcr);
#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CONFIG_DEEP_SLEEP
+ /* disable the console if boot from deep sleep */
+ if (in_be32(&gur->scrtsr[0]) & (1 << 3))
+ gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+#endif
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
+ fsl_erratum_a007212_workaround();
+#endif
+
}
/* Implement a dummy function for those platforms w/o SERDES */
puts("disabled\n");
#endif
+#if defined(CONFIG_RAMBOOT_PBL)
+ disable_cpc_sram();
+#endif
enable_cpc();
#ifndef CONFIG_SYS_FSL_NO_SERDES
CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+ usb_single_source_clk_configure(usb_phy);
+#endif
setbits_be32(&usb_phy->port1.ctrl,
CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
setbits_be32(&usb_phy->port1.drvvbuscfg,
return 0;
}
-extern void setup_ivors(void);
-
void arch_preboot_os(void)
{
u32 msr;
msr = mfmsr();
msr &= ~(MSR_ME|MSR_CE);
mtmsr(msr);
-
- setup_ivors();
}
#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
void cpu_secondary_init_r(void)
{
-#ifdef CONFIG_QE
+#ifdef CONFIG_U_QE
+ uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
+#elif defined CONFIG_QE
uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
-#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
- int ret;
- size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
-
- /* load QE firmware from NAND flash to DDR first */
- ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
- &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
-
- if (ret && ret == -EUCLEAN) {
- printf ("NAND read for QE firmware at offset %x failed %d\n",
- CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
- }
#endif
+
+#ifdef CONFIG_QE
qe_init(qe_base);
qe_reset();
#endif
#endif
/* We run cpu_init_early_f in AS = 1 */
-void cpu_init_early_f(void)
+void cpu_init_early_f(void *fdt)
{
u32 mas0, mas1, mas2, mas3, mas7;
int i;
for (i = 0; i < sizeof(gd_t); i++)
((char *)gd)[i] = 0;
+ /*
+ * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
+ * so we need to populate it before it accesses it.
+ */
+ gd->fdt_blob = fdt;
+
mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
/* Only initialize every eighth thread */
- if (reg && !((*reg) % 8))
+ if (reg && !((*reg) % 8)) {
+ fdt_setprop_cell(blob, l2_off, "cache-stash-id",
+ (*reg / 4) + 32 + 1);
+ }
#else
- if (reg)
-#endif
+ if (reg) {
fdt_setprop_cell(blob, l2_off, "cache-stash-id",
- (*reg * 2) + 32 + 1);
+ (*reg * 2) + 32 + 1);
+ }
+#endif
#endif
fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
#define fdt_fixup_usb(x)
#endif
+#if defined(CONFIG_PPC_T1040)
+static void fdt_fixup_l2_switch(void *blob)
+{
+ uchar l2swaddr[6];
+ int node;
+
+ /* The l2switch node from device-tree has
+ * compatible string "vitesse-9953" */
+ node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
+ if (node == -FDT_ERR_NOTFOUND)
+ /* no l2switch node has been found */
+ return;
+
+ /* Get MAC address for the l2switch from "l2switchaddr"*/
+ if (!eth_getenv_enetaddr("l2switchaddr", l2swaddr)) {
+ printf("Warning: MAC address for l2switch not found\n");
+ memset(l2swaddr, 0, sizeof(l2swaddr));
+ }
+
+ /* Add MAC address to l2switch node */
+ fdt_setprop(blob, node, "local-mac-address", l2swaddr,
+ sizeof(l2swaddr));
+}
+#else
+#define fdt_fixup_l2_switch(x)
+#endif
+
void ft_cpu_setup(void *blob, bd_t *bd)
{
int off;
"clock-frequency", gd->bus_clk/2, 1);
fdt_fixup_usb(blob);
+
+ fdt_fixup_l2_switch(blob);
}
/*
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * Kumar Gala <kumar.gala@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* This file is intended to be included by other asm code since
- * we will want to execute this on both the primary core when
- * it does a bootm and the secondary core's that get released
- * out of the spin table */
-
-#define SET_IVOR(vector_number, vector_offset) \
- li r3,vector_offset@l; \
- mtspr SPRN_IVOR##vector_number,r3;
-
-#define SET_GIVOR(vector_number, vector_offset) \
- li r3,vector_offset@l; \
- mtspr SPRN_GIVOR##vector_number,r3;
-
- SET_IVOR(0, 0x020) /* Critical Input */
- SET_IVOR(1, 0x000) /* Machine Check */
- SET_IVOR(2, 0x060) /* Data Storage */
- SET_IVOR(3, 0x080) /* Instruction Storage */
- SET_IVOR(4, 0x0a0) /* External Input */
- SET_IVOR(5, 0x0c0) /* Alignment */
- SET_IVOR(6, 0x0e0) /* Program */
- SET_IVOR(7, 0x100) /* FP Unavailable */
- SET_IVOR(8, 0x120) /* System Call */
- SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
- SET_IVOR(10, 0x160) /* Decrementer */
- SET_IVOR(11, 0x180) /* Fixed Interval Timer */
- SET_IVOR(12, 0x1a0) /* Watchdog Timer */
- SET_IVOR(13, 0x1c0) /* Data TLB Error */
- SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
- SET_IVOR(15, 0x040) /* Debug */
-
-/* e500v1 & e500v2 only */
-#ifndef CONFIG_E500MC
- SET_IVOR(32, 0x200) /* SPE Unavailable */
- SET_IVOR(33, 0x220) /* Embedded FP Data */
- SET_IVOR(34, 0x240) /* Embedded FP Round */
-#endif
-
- SET_IVOR(35, 0x260) /* Performance monitor */
-
-/* e500mc only */
-#ifdef CONFIG_E500MC
- SET_IVOR(36, 0x280) /* Processor doorbell */
- SET_IVOR(37, 0x2a0) /* Processor doorbell critical */
- SET_IVOR(38, 0x2c0) /* Guest Processor doorbell */
- SET_IVOR(39, 0x2e0) /* Guest Processor critical & machine check */
- SET_IVOR(40, 0x300) /* Hypervisor system call */
- SET_IVOR(41, 0x320) /* Hypervisor Priviledge */
-
- SET_GIVOR(2, 0x060) /* Guest Data Storage */
- SET_GIVOR(3, 0x080) /* Guest Instruction Storage */
- SET_GIVOR(4, 0x0a0) /* Guest External Input */
- SET_GIVOR(8, 0x120) /* Guest System Call */
- SET_GIVOR(13, 0x1c0) /* Guest Data TLB Error */
- SET_GIVOR(14, 0x1e0) /* Guest Instruction TLB Error */
-#endif
#include "asm/io.h"
#include "asm/immap_85xx.h"
-#if defined(CONFIG_QE)
+#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
#define NUM_OF_PINS 32
void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
{
bne 3b
isync
- /* setup IVORs to match fixed offsets */
-#include "fixed_ivor.S"
-
/* get the upper bits of the addr */
lwz r11,ENTRY_ADDR_UPPER(r10)
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
uint mem_pll_rat;
-#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
- uint single_src;
-#endif
sys_info->freq_systembus = sysclk;
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+ uint ddr_refclk_sel;
+ unsigned int porsr1_sys_clk;
+ porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
+ & FSL_DCFG_PORSR1_SYSCLK_MASK;
+ if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
+ sys_info->diff_sysclk = 1;
+ else
+ sys_info->diff_sysclk = 0;
+
/*
* DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
* are driven by separate DDR Refclock or single source
* differential clock.
*/
- single_src = (in_be32(&gur->rcwsr[5]) >>
+ ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
/*
- * For single source clocking, both ddrclock and syclock
+ * For single source clocking, both ddrclock and sysclock
* are driven by differential sysclock.
*/
- if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
- printf("Single Source Clock Configuration\n");
+ if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
- } else
+ else
#endif
#ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
+ if (mem_pll_rat == 0) {
+ mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
+ FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
+ FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
+ }
+#endif
/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
* it uses 6.
sys_info->freq_processor[cpu] =
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
-#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \
- defined(CONFIG_PPC_T2081)
+#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
+ defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
#else
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#ifdef CONFIG_U_QE
+ sys_info->freq_qe = sys_info->freq_systembus / 2;
+#endif
+
#else /* CONFIG_FSL_CORENET */
uint plat_ratio, e500_ratio, half_freq_systembus;
int i;
#undef MSR_KERNEL
#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
+#define LAW_EN 0x80000000
+
#if defined(CONFIG_NAND_SPL) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
#define MINIMAL_SPL
li r1,MSR_DE
mtmsr r1
+ /*
+ * If we got an ePAPR device tree pointer passed in as r3, we need that
+ * later in cpu_init_early_f(). Save it to a safe register before we
+ * clobber it so that we can fetch it from there later.
+ */
+ mr r24, r3
+
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
mfspr r3,SPRN_SVR
rlwinm r3,r3,0,0xff
#endif
-#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
+ !defined(CONFIG_E6500)
/* ISBC uses L2 as stack.
* Disable L2 cache here so that u-boot can enable it later
* as part of it's normal flow
2: cmpw r3, r4
blt 1b
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \
+ !defined(CONFIG_SECURE_BOOT)
/*
* TLB entry for debuggging in AS1
* Create temporary TLB entry in AS0 to handle debug exception
0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
-#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
- create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
- 0, BOOKE_PAGESZ_1M, \
- CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
- CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
- 0, r6
#else
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
#ifdef CONFIG_FSL_CORENET
#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
-#define LAW_EN 0x80000000
#define LAW_SIZE_4K 0xb
#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
#define CCSRAR_C 0x80000000 /* Commit */
mr r1,r3 /* Transfer to SP(r1) */
GET_GOT
+
+ /* Pass our potential ePAPR device tree pointer to cpu_init_early_f */
+ mr r3, r24
+
bl cpu_init_early_f
/* switch back to AS = 0 */
mr r10,r5 /* Save copy of Destination Address */
GET_GOT
+#ifndef CONFIG_SPL_SKIP_RELOCATE
mr r3,r5 /* Destination Address */
lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
mtlr r0
blr /* NEVER RETURNS! */
+#endif
.globl in_ram
in_ram:
isync
blr
-
-.globl setup_ivors
-setup_ivors:
-
-#include "fixed_ivor.S"
- blr
#endif /* !MINIMAL_SPL */
SET_DMA_LIODN(2, 227),
/* SET_NEXUS_LIODN(557), -- not yet implemented */
+ SET_QE_LIODN(559),
};
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
mtspr(MMUCSR0, 0x2);
}
-void init_tlbs(void)
+__weak void init_tlbs(void)
{
int i;
}
#endif
-unsigned int
-setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
+uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
+ enum tlb_map_type map_type)
{
int i;
unsigned int tlb_size;
- unsigned int wimge = MAS2_M;
- unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
+ unsigned int wimge;
+ unsigned int perm;
unsigned int max_cam, tsize_mask;
- u64 size, memsize = (u64)memsize_in_meg << 20;
+ if (map_type == TLB_MAP_RAM) {
+ perm = MAS3_SX|MAS3_SW|MAS3_SR;
+ wimge = MAS2_M;
#ifdef CONFIG_SYS_PPC_DDR_WIMGE
- wimge = CONFIG_SYS_PPC_DDR_WIMGE;
+ wimge = CONFIG_SYS_PPC_DDR_WIMGE;
#endif
- size = min(memsize, CONFIG_MAX_MEM_MAPPED);
+ } else {
+ perm = MAS3_SW|MAS3_SR;
+ wimge = MAS2_I|MAS2_G;
+ }
+
if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
/* Convert (4^max) kB to (2^max) bytes */
max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
}
for (i = 0; size && i < 8; i++) {
- int ram_tlb_index = find_free_tlbcam();
+ int tlb_index = find_free_tlbcam();
u32 camsize = __ilog2_u64(size) & tsize_mask;
- u32 align = __ilog2(ram_tlb_address) & tsize_mask;
+ u32 align = __ilog2(v_addr) & tsize_mask;
- if (ram_tlb_index == -1)
+ if (tlb_index == -1)
break;
if (align == -2) align = max_cam;
tlb_size = camsize - 10;
- set_tlb(1, ram_tlb_address, p_addr,
- MAS3_SX|MAS3_SW|MAS3_SR, wimge,
- 0, ram_tlb_index, tlb_size, 1);
+ set_tlb(1, v_addr, p_addr, perm, wimge,
+ 0, tlb_index, tlb_size, 1);
size -= 1ULL << camsize;
- memsize -= 1ULL << camsize;
- ram_tlb_address += 1UL << camsize;
+ v_addr += 1UL << camsize;
p_addr += 1UL << camsize;
}
+ return size;
+}
+
+unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
+ unsigned int memsize_in_meg)
+{
+ unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
+ u64 memsize = (u64)memsize_in_meg << 20;
+
+ memsize = min(memsize, CONFIG_MAX_MEM_MAPPED);
+ memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM);
+
if (memsize)
print_size(memsize, " left unmapped\n");
+
return memsize_in_meg;
}
* SPDX-License-Identifier: GPL-2.0+
*/
+#include "config.h" /* CONFIG_BOARDDIR */
+
+#ifndef CONFIG_SYS_MONITOR_LEN
+#define CONFIG_SYS_MONITOR_LEN 0x80000
+#endif
+
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
} :text = 0xffff
- . = ADDR(.text) + 0x80000;
+ . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN;
__bss_start = .;
.bss (NOLOAD) :
. = ALIGN(8);
__init_begin = .;
__init_end = .;
+#ifdef CONFIG_SPL_SKIP_RELOCATE
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : {
+ *(.sbss*)
+ *(.bss*)
+ }
+ . = ALIGN(4);
+ __bss_end = .;
+#endif
/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
} :text = 0xffff
#else
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
- .bootpg ADDR(.text) + 0x1000 :
+#ifndef BOOT_PAGE_OFFSET
+#define BOOT_PAGE_OFFSET 0x1000
+#endif
+ .bootpg ADDR(.text) + BOOT_PAGE_OFFSET :
{
arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
}
+#ifndef RESET_VECTOR_OFFSET
#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
+#endif
#elif defined(CONFIG_FSL_ELBC)
#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
#else
} = 0xffff
#endif
+#ifndef CONFIG_SPL_SKIP_RELOCATE
/*
* Make sure that the bss segment isn't linked at 0x0, otherwise its
* address won't be updated during relocation fixups.
}
. = ALIGN(4);
__bss_end = .;
+#endif
}
#define RESET_VECTOR_ADDRESS 0xfffffffc
#endif
+#ifndef CONFIG_SYS_MONITOR_LEN
+#define CONFIG_SYS_MONITOR_LEN 0x80000
+#endif
+
OUTPUT_ARCH(powerpc)
+ENTRY(_start_e500)
PHDRS
{
{
KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
} :text = 0xffff
- . = ADDR(.text) + 0x80000;
+ . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN;
#else
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
{
}
#endif /* not SPL */
+void disable_non_ddr_laws(void)
+{
+ int i;
+ int id;
+ for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
+ u32 lawar = in_be32(LAWAR_ADDR(i));
+
+ if (lawar & LAW_EN) {
+ id = (lawar & ~LAW_EN) >> 20;
+ switch (id) {
+ case LAW_TRGT_IF_DDR_1:
+ case LAW_TRGT_IF_DDR_2:
+ case LAW_TRGT_IF_DDR_3:
+ case LAW_TRGT_IF_DDR_4:
+ case LAW_TRGT_IF_DDR_INTRLV:
+ case LAW_TRGT_IF_DDR_INTLV_34:
+ case LAW_TRGT_IF_DDR_INTLV_123:
+ case LAW_TRGT_IF_DDR_INTLV_1234:
+ continue;
+ default:
+ disable_law(i);
+ }
+ }
+ }
+}
+
void init_laws(void)
{
int i;
#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
#endif
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500) && \
+ !defined(CONFIG_E500MC)
+ /* ISBC (Boot ROM) creates a LAW 0 entry for non PBL platforms,
+ * which is not disabled before transferring the control to uboot.
+ * Disable the LAW 0 entry here.
+ */
+ disable_law(0);
+#endif
+
+#if !defined(CONFIG_SECURE_BOOT)
+ /*
+ * if any non DDR LAWs has been created earlier, remove them before
+ * LAW table is parsed.
+ */
+ disable_non_ddr_laws();
+#endif
+
/*
* Any LAWs that were set up before we booted assume they are meant to
* be around and mark them used.
gd->arch.used_laws |= (1 << i);
}
-#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
- /*
- * in SPL boot we've already parsed the law_table and setup those LAWs
- * so don't do it again.
- */
- return;
-#endif
-
for (i = 0; i < num_law_entries; i++) {
if (law_table[i].index == -1)
set_next_law(law_table[i].addr, law_table[i].size,
*/
#define CONFIG_PPC_SPINTABLE_COMPATIBLE
-#define FSL_DDR_VER_4_7 47
-#define FSL_DDR_VER_5_0 50
+#include <fsl_ddrc_version.h>
+#define CONFIG_SYS_FSL_DDR_BE
/* IP endianness */
#define CONFIG_SYS_FSL_IFC_BE
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
#define CONFIG_ESDHC_HC_BLK_ADDR
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
#define CONFIG_SYS_FSL_ERRATUM_A005812
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_NUM_FM2_DTSEC 5
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_FSL_ERRATUM_A006379
#define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_ERRATUM_A006475
#define CONFIG_SYS_FSL_ERRATUM_A006384
+#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#ifdef CONFIG_PPC_B4860
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
+#ifdef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDRC_GEN4
+#endif
#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
#define CONFIG_MAX_CPUS 4
#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define QE_MURAM_SIZE 0x6000UL
+#define MAX_QE_RISC 1
+#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define CONFIG_E6500
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ISBC_VER 2
#define CONFIG_SYS_FSL_SEC_COMPAT 6
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#elif defined(CONFIG_QEMU_E500)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
+
#else
#error Processor type not defined for this platform
#endif
#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
!defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
- !defined(CONFIG_SYS_FSL_DDRC_GEN3)
+ !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
+ !defined(CONFIG_SYS_FSL_DDRC_GEN4)
#define CONFIG_SYS_FSL_DDRC_GEN3
#endif
}
#endif
+static inline bool has_erratum_a007075(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ switch (soc) {
+ case SVR_B4860:
+ case SVR_B4420:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_P1010:
+ return IS_SVR_REV(svr, 1, 0);
+ case SVR_P4080:
+ return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
+ }
+ return false;
+}
#endif
SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
+#define SET_QE_LIODN(liodn) \
+ SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
+ CONFIG_SYS_MPC85xx_QE_OFFSET)
+
#define SET_QMAN_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
CONFIG_SYS_FSL_QMAN_OFFSET, \
#ifdef CONFIG_SECURE_BOOT
#if defined(CONFIG_FSL_CORENET)
#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
+#elif defined(CONFIG_BSC9132QDS)
+#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
#else
#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
#endif
#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
+#if defined(CONFIG_B4860QDS) || \
+ defined(CONFIG_T4240QDS) || \
+ defined(CONFIG_T2080QDS) || \
+ defined(CONFIG_T1040QDS) || \
+ defined(CONFIG_T1040RDB)
+#define CONFIG_SYS_CPC_REINIT_F
+#undef CONFIG_SYS_INIT_L3_ADDR
+#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
+#endif
+
#endif
#endif
typedef struct ccsr_gur {
u32 porsr1; /* POR status 1 */
u32 porsr2; /* POR status 2 */
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15
+#define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1
+#define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1
+#define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0
+#endif
u8 res_008[0x20-0x8];
u32 gpporcr1; /* General-purpose POR configuration */
u32 gpporcr2; /* General-purpose POR configuration 2 */
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
+/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
u32 sata2liodnr; /* SATA 2 LIODN */
u32 sata3liodnr; /* SATA 3 LIODN */
u32 sata4liodnr; /* SATA 4 LIODN */
- u8 res22[32];
+ u8 res22[24];
+ u32 qeliodnr; /* QE LIODN */
+ u8 res_57c[4];
u32 dma1liodnr; /* DMA 1 LIODN */
u32 dma2liodnr; /* DMA 2 LIODN */
u32 dma3liodnr; /* DMA 3 LIODN */
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
+#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
&& !defined(CONFIG_PPC_B4420)
#define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
};
+
+#define CONFIG_SYS_MPC85xx_SCFG \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
+#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
+/* The supplement configuration unit register */
+struct ccsr_scfg {
+ u32 dpslpcr; /* 0x000 Deep Sleep Control register */
+ u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
+ u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
+ u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
+ u32 res1[4];
+ u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
+ u32 res2;
+ u32 pixclkcr; /* 0x028 Pixel Clock Control register */
+ u32 res3[245];
+ u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */
+ u32 emiiocr; /* 0x404 EMI MDIO Control Register */
+ u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */
+ u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */
+ u32 res4[60];
+ u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */
+};
#endif /*__IMMAP_85xx__*/
extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
extern void clear_ddr_tlbs(unsigned int memsize_in_meg);
+enum tlb_map_type {
+ TLB_MAP_RAM,
+ TLB_MAP_IO,
+};
+
+extern uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
+ enum tlb_map_type map_type);
+
extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);
#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
#ifdef CONFIG_PRAM
ulong reg;
#endif
+#ifdef CONFIG_DEEP_SLEEP
+ const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+ u32 start_addr;
+ typedef void (*func_t)(void);
+ func_t kernel_resume;
+#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
if ((*init_fnc_ptr) () != 0)
hang();
+#ifdef CONFIG_DEEP_SLEEP
+ /* Jump to kernel in deep sleep case */
+ if (in_be32(&gur->scrtsr[0]) & (1 << 3)) {
+ start_addr = in_be32(&scfg->sparecr[1]);
+ kernel_resume = (func_t)start_addr;
+ kernel_resume();
+ }
+#endif
+
#ifdef CONFIG_POST
post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(NULL));
# SPDX-License-Identifier: GPL-2.0+
#
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
obj-y += b4860qds.o
-obj-y += ddr.o
obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o
-obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_PCI) += pci.o
+endif
+
+obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
09110024 00100008
09110028 00100008
0911002c 00100008
+#slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
#Flush PBL data
09138000 00000000
091380c0 00000000
{
phys_size_t dram_size;
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
- puts(" DDR: ");
+#else
+ dram_size = fsl_ddr_sdram_size();
+#endif
return dram_size;
}
--- /dev/null
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/spl.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include "../common/qixis.h"
+#include "b4860qds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((sysclk_conf & 0x0C) >> 2) {
+ case QIXIS_CLK_100:
+ return 100000000;
+ case QIXIS_CLK_125:
+ return 125000000;
+ case QIXIS_CLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (ddrclk_conf & 0x03) {
+ case QIXIS_CLK_100:
+ return 100000000;
+ case QIXIS_CLK_125:
+ return 125000000;
+ case QIXIS_CLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, uart_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ /* compiler optimization barrier needed for GCC >= 3.4 */
+ __asm__ __volatile__("" : : : "memory");
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ uart_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ uart_clk / 16 / CONFIG_BAUDRATE);
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+ env_init();
+ env_relocate();
+#else
+ /* relocate environment function pointers etc. */
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+#endif
+
+ i2c_init_all();
+
+ puts("\n\n");
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_boot();
+#endif
+}
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
+#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_16M, 1),
#endif
+#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for SRIO2.
*/
+#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
/* *I*G* - SRIO1 */
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 17, BOOKE_PAGESZ_1M, 1),
#endif
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 17, BOOKE_PAGESZ_2G, 1)
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
--- /dev/null
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += qemu-ppce500.o
--- /dev/null
+/*
+ * Copyright 2007,2009-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void *get_fdt_virt(void)
+{
+ return (void *)CONFIG_SYS_TMPVIRT;
+}
+
+static uint64_t get_fdt_phys(void)
+{
+ return (uint64_t)(uintptr_t)gd->fdt_blob;
+}
+
+static void map_fdt_as(int esel)
+{
+ u32 mas0, mas1, mas2, mas3, mas7;
+ uint64_t fdt_phys = get_fdt_phys();
+ unsigned long fdt_phys_tlb = fdt_phys & ~0xffffful;
+ unsigned long fdt_virt_tlb = (ulong)get_fdt_virt() & ~0xffffful;
+
+ mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(esel);
+ mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
+ mas2 = FSL_BOOKE_MAS2(fdt_virt_tlb, 0);
+ mas3 = FSL_BOOKE_MAS3(fdt_phys_tlb, 0, MAS3_SW|MAS3_SR);
+ mas7 = FSL_BOOKE_MAS7(fdt_phys_tlb);
+
+ write_tlb(mas0, mas1, mas2, mas3, mas7);
+}
+
+uint64_t get_phys_ccsrbar_addr_early(void)
+{
+ void *fdt = get_fdt_virt();
+ uint64_t r;
+
+ /*
+ * To be able to read the FDT we need to create a temporary TLB
+ * map for it.
+ */
+ map_fdt_as(10);
+ r = fdt_get_base_address(fdt, fdt_path_offset(fdt, "/soc"));
+ disable_tlb(10);
+
+ return r;
+}
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ return 0;
+}
+
+static int pci_map_region(void *fdt, int pci_node, int range_id,
+ phys_size_t *ppaddr, pci_addr_t *pvaddr,
+ pci_size_t *psize, ulong *pmap_addr)
+{
+ uint64_t addr;
+ uint64_t size;
+ ulong map_addr;
+ int r;
+
+ r = fdt_read_range(fdt, pci_node, 0, NULL, &addr, &size);
+ if (r)
+ return r;
+
+ if (ppaddr)
+ *ppaddr = addr;
+ if (psize)
+ *psize = size;
+
+ if (!pmap_addr)
+ return 0;
+
+ map_addr = *pmap_addr;
+
+ /* Align map_addr */
+ map_addr += size - 1;
+ map_addr &= ~(size - 1);
+
+ if (map_addr + size >= CONFIG_SYS_PCI_MAP_END)
+ return -1;
+
+ /* Map virtual memory for range */
+ assert(!tlb_map_range(map_addr, addr, size, TLB_MAP_IO));
+ *pmap_addr = map_addr + size;
+
+ if (pvaddr)
+ *pvaddr = map_addr;
+
+ return 0;
+}
+
+void pci_init_board(void)
+{
+ struct pci_controller *pci_hoses;
+ void *fdt = get_fdt_virt();
+ int pci_node = -1;
+ int pci_num = 0;
+ int pci_count = 0;
+ ulong map_addr;
+
+ puts("\n");
+
+ /* Start MMIO and PIO range maps above RAM */
+ map_addr = CONFIG_SYS_PCI_MAP_START;
+
+ /* Count and allocate PCI buses */
+ pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
+ "device_type", "pci", 4);
+ while (pci_node != -FDT_ERR_NOTFOUND) {
+ pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
+ "device_type", "pci", 4);
+ pci_count++;
+ }
+
+ if (pci_count) {
+ pci_hoses = malloc(sizeof(struct pci_controller) * pci_count);
+ } else {
+ printf("PCI: disabled\n\n");
+ return;
+ }
+
+ /* Spawn PCI buses based on device tree */
+ pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
+ "device_type", "pci", 4);
+ while (pci_node != -FDT_ERR_NOTFOUND) {
+ struct fsl_pci_info pci_info = { };
+ const fdt32_t *reg;
+ int r;
+
+ reg = fdt_getprop(fdt, pci_node, "reg", NULL);
+ pci_info.regs = fdt_translate_address(fdt, pci_node, reg);
+
+ /* Map MMIO range */
+ r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL,
+ &pci_info.mem_size, &map_addr);
+ if (r)
+ break;
+
+ /* Map PIO range */
+ r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL,
+ &pci_info.io_size, &map_addr);
+ if (r)
+ break;
+
+ /*
+ * The PCI framework finds virtual addresses for the buses
+ * through our address map, so tell it the physical addresses.
+ */
+ pci_info.mem_bus = pci_info.mem_phys;
+ pci_info.io_bus = pci_info.io_phys;
+
+ /* Instantiate */
+ pci_info.pci_num = pci_num + 1;
+
+ fsl_setup_hose(&pci_hoses[pci_num], pci_info.regs);
+ printf("PCI: base address %lx\n", pci_info.regs);
+
+ fsl_pci_init_port(&pci_info, &pci_hoses[pci_num], pci_num);
+
+ /* Jump to next PCI node */
+ pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
+ "device_type", "pci", 4);
+ pci_num++;
+ }
+
+ puts("\n");
+}
+
+int last_stage_init(void)
+{
+ void *fdt = get_fdt_virt();
+ int len = 0;
+ const uint64_t *prop;
+ int chosen;
+
+ chosen = fdt_path_offset(fdt, "/chosen");
+ if (chosen < 0) {
+ printf("Couldn't find /chosen node in fdt\n");
+ return -EIO;
+ }
+
+ /* -kernel boot */
+ prop = fdt_getprop(fdt, chosen, "qemu,boot-kernel", &len);
+ if (prop && (len >= 8))
+ setenv_hex("qemu_kernel_addr", *prop);
+
+ /* Give the user a variable for the host fdt */
+ setenv_hex("fdt_addr_r", (ulong)fdt);
+
+ return 0;
+}
+
+static uint64_t get_linear_ram_size(void)
+{
+ void *fdt = get_fdt_virt();
+ const void *prop;
+ int memory;
+ int len;
+
+ memory = fdt_path_offset(fdt, "/memory");
+ prop = fdt_getprop(fdt, memory, "reg", &len);
+
+ if (prop && len >= 16)
+ return *(uint64_t *)(prop+8);
+
+ panic("Couldn't determine RAM size");
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
+#endif
+
+void print_laws(void)
+{
+ /* We don't emulate LAWs yet */
+}
+
+phys_size_t fixed_sdram(void)
+{
+ return get_linear_ram_size();
+}
+
+phys_size_t fsl_ddr_sdram_size(void)
+{
+ return get_linear_ram_size();
+}
+
+void init_tlbs(void)
+{
+ phys_size_t ram_size;
+
+ /*
+ * Create a temporary AS=1 map for the fdt
+ *
+ * We use ESEL=0 here to overwrite the previous AS=0 map for ourselves
+ * which was only 4k big. This way we don't have to clear any other maps.
+ */
+ map_fdt_as(0);
+
+ /* Fetch RAM size from the fdt */
+ ram_size = get_linear_ram_size();
+
+ /* And remove our fdt map again */
+ disable_tlb(0);
+
+ /* Create an internal map of manually created TLB maps */
+ init_used_tlb_cams();
+
+ /* Create a dynamic AS=0 CCSRBAR mapping */
+ assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ 1024 * 1024, TLB_MAP_IO));
+
+ /* Create a RAM map that spans all accessible RAM */
+ setup_ddr_tlbs(ram_size >> 20);
+
+ /* Create a map for the TLB */
+ assert(!tlb_map_range((ulong)get_fdt_virt(), get_fdt_phys(),
+ 1024 * 1024, TLB_MAP_RAM));
+}
+
+void init_laws(void)
+{
+ /* We don't emulate LAWs yet */
+}
+
+static uint32_t get_cpu_freq(void)
+{
+ void *fdt = get_fdt_virt();
+ int cpus_node = fdt_path_offset(fdt, "/cpus");
+ int cpu_node = fdt_first_subnode(fdt, cpus_node);
+ const char *prop = "clock-frequency";
+ return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
+}
+
+void get_sys_info(sys_info_t *sys_info)
+{
+ int freq = get_cpu_freq();
+
+ memset(sys_info, 0, sizeof(sys_info_t));
+ sys_info->freq_systembus = freq;
+ sys_info->freq_ddrbus = freq;
+ sys_info->freq_processor[0] = freq;
+}
+
+int get_clocks (void)
+{
+ sys_info_t sys_info;
+
+ get_sys_info(&sys_info);
+
+ gd->cpu_clk = sys_info.freq_processor[0];
+ gd->bus_clk = sys_info.freq_systembus;
+ gd->mem_clk = sys_info.freq_ddrbus;
+ gd->arch.lbc_clk = sys_info.freq_ddrbus;
+
+ return 0;
+}
+
+unsigned long get_tbclk (void)
+{
+ void *fdt = get_fdt_virt();
+ int cpus_node = fdt_path_offset(fdt, "/cpus");
+ int cpu_node = fdt_first_subnode(fdt, cpus_node);
+ const char *prop = "timebase-frequency";
+ return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
+}
+
+/********************************************
+ * get_bus_freq
+ * return system bus freq in Hz
+ *********************************************/
+ulong get_bus_freq (ulong dummy)
+{
+ sys_info_t sys_info;
+ get_sys_info(&sys_info);
+ return sys_info.freq_systembus;
+}
/*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
if (pbsp->n_ranks == pdimm->n_ranks &&
(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp->force_2t;
goto found;
}
pbsp_highest = pbsp;
printf("for data rate %lu MT/s\n", ddr_freq);
printf("Trying to use the highest speed (%u) parameters\n",
pbsp_highest->datarate_mhz_high);
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp_highest->force_2t;
} else {
panic("DIMM is not supported by this board");
}
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
- popts->half_strength_driver_enable = 0;
+ popts->half_strength_driver_enable = 1;
/*
* Write leveling override
*/
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
+#ifdef CONFIG_SYS_FSL_DDR4
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+ DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+#else
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
}
phys_size_t initdram(int board_type)
/*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
};
/*
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
- {2, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0},
- {2, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0},
- {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0},
- {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0},
- {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0},
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0},
- {1, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0},
- {1, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0},
- {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0},
- {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0},
- {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0},
- {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0},
+#ifdef CONFIG_SYS_FSL_DDR4
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
+ {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,},
+#elif defined(CONFIG_SYS_FSL_DDR3)
+ {2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
+ {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
+ {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
+ {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+#else
+#error DDR type not defined
+#endif
{}
};
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
+#include <hwconfig.h>
+#include <asm/mpc85xx_gpio.h>
#include "../common/qixis.h"
#include "t1040qds.h"
return 0;
}
+static void qe_board_setup(void)
+{
+ u8 brdcfg15, brdcfg9;
+
+ if (hwconfig("qe") && hwconfig("tdm")) {
+ brdcfg15 = QIXIS_READ(brdcfg[15]);
+ /*
+ * TDMRiser uses QE-TDM
+ * Route QE_TDM signals to TDM Riser slot
+ */
+ QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
+ } else if (hwconfig("qe") && hwconfig("uart")) {
+ brdcfg15 = QIXIS_READ(brdcfg[15]);
+ brdcfg9 = QIXIS_READ(brdcfg[9]);
+ /*
+ * Route QE_TDM signals to UCC
+ * ProfiBus controlled by UCC3
+ */
+ brdcfg15 &= 0xfc;
+ QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
+ QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
+ }
+}
+
int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
}
}
+ qe_board_setup();
+
return 0;
}
{
return 1;
}
+
+#ifdef CONFIG_DEEP_SLEEP
+void board_mem_sleep_setup(void)
+{
+ /* does not provide HW signals for power management */
+ QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
# SPDX-License-Identifier: GPL-2.0+
#
-
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
obj-y += t104xrdb.o
-obj-y += ddr.o
+obj-y += cpld.o
obj-y += eth.o
obj-$(CONFIG_PCI) += pci.o
+endif
+obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
2.To change from vbank4 to vbank0
=> qixis reset (it will boot using vbank0)
+
+NAND boot with 2 Stage boot loader
+----------------------------------
+PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
+SPL further initialise DDR using SPD and environment variables and copy
+u-boot(768 KB) from flash to DDR.
+Finally SPL transer control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+ Run time view of SPL framework during boot :-
+ -----------------------------------------------
+ Area | Address |
+-----------------------------------------------
+ Secure boot | 0xFFFC0000 (32KB) |
+ headers | |
+ -----------------------------------------------
+ GD, BD | 0xFFFC8000 (4KB) |
+ -----------------------------------------------
+ ENV | 0xFFFC9000 (8KB) |
+ -----------------------------------------------
+ HEAP | 0xFFFCB000 (30KB) |
+ -----------------------------------------------
+ STACK | 0xFFFD8000 (22KB) |
+ -----------------------------------------------
+ U-boot SPL | 0xFFFD8000 (160KB) |
+ -----------------------------------------------
+
+NAND Flash memory Map on T104xRDB
+------------------------------------------
+ Start End Definition Size
+0x000000 0x0FFFFF u-boot 1MB
+0x180000 0x19FFFF u-boot env 128KB
+0x280000 0x29FFFF FMAN Ucode 128KB
+0x380000 0x39FFFF QE Firmware 128KB
+
+SD Card memory Map on T104xRDB
+------------------------------------------
+ Block #blocks Definition Size
+0x008 2048 u-boot 1MB
+0x800 0024 u-boot env 8KB
+0x820 0256 FMAN Ucode 128KB
+0x920 0256 QE Firmware 128KB
+
+SPI Flash memory Map on T104xRDB
+------------------------------------------
+ Start End Definition Size
+0x000000 0x0FFFFF u-boot 1MB
+0x100000 0x101FFF u-boot env 8KB
+0x110000 0x12FFFF FMAN Ucode 128KB
+0x130000 0x14FFFF QE Firmware 128KB
+
+Please note QE Firmware is only valid for T1040RDB
+
+
+Switch Settings: (ON is 0, OFF is 1)
+===============
+NAND boot SW setting:
+SW1: 10001000
+SW2: 00111001
+SW3: 11110001
+
+SPI boot SW setting:
+SW1: 00100010
+SW2: 10111001
+SW3: 11100001
+
+SD boot SW setting:
+SW1: 00100000
+SW2: 00111001
+SW3: 11100001
--- /dev/null
+/**
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file provides support for the board-specific CPLD used on some Freescale
+ * reference boards.
+ *
+ * The following macros need to be defined:
+ *
+ * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ out_8(p + reg, value);
+}
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void cpld_set_altbank(void)
+{
+ u8 reg = CPLD_READ(flash_ctl_status);
+
+ reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
+
+ CPLD_WRITE(flash_ctl_status, reg);
+ CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
+}
+
+/**
+ * Set the boot bank to the default bank
+ */
+void cpld_set_defbank(void)
+{
+ u8 reg = CPLD_READ(flash_ctl_status);
+
+ reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
+
+ CPLD_WRITE(flash_ctl_status, reg);
+ CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
+}
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+ printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
+ printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
+ printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
+ printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
+ printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
+ printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
+ printf("int_status = 0x%02x\n", CPLD_READ(int_status));
+ printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
+ printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
+ printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
+ printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
+ printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
+ printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
+ printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
+ printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
+ putc('\n');
+}
+#endif
+
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rc = 0;
+
+ if (argc <= 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], "reset") == 0) {
+ if (strcmp(argv[2], "altbank") == 0)
+ cpld_set_altbank();
+ else
+ cpld_set_defbank();
+#ifdef DEBUG
+ } else if (strcmp(argv[1], "dump") == 0) {
+ cpld_dump_regs();
+#endif
+ } else
+ rc = cmd_usage(cmdtp);
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+ "Reset the board or alternate bank",
+ "reset - hard reset to default bank\n"
+ "cpld reset altbank - reset to alternate bank\n"
+#ifdef DEBUG
+ "cpld dump - display the CPLD registers\n"
+#endif
+ );
--- /dev/null
+/**
+ * Copyright 2013 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/*
+ * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
+ */
+struct cpld_data {
+ u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */
+ u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */
+ u8 hw_ver; /* 0x02 - Hardware Revision Register */
+ u8 sw_ver; /* 0x03 - Software Revision register */
+ u8 res0[12]; /* 0x04 - 0x0F - not used */
+ u8 reset_ctl1; /* 0x10 - Reset control Register1 */
+ u8 reset_ctl2; /* 0x11 - Reset control Register2 */
+ u8 int_status; /* 0x12 - Interrupt status Register */
+ u8 flash_ctl_status; /* 0x13 - Flash control and status register */
+ u8 fan_ctl_status; /* 0x14 - Fan control and status register */
+ u8 led_ctl_status; /* 0x15 - LED control and status register */
+ u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
+ u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
+ u8 boot_override; /* 0x18 - Boot override register */
+ u8 boot_config1; /* 0x19 - Boot config override register*/
+ u8 boot_config2; /* 0x1A - Boot config override register*/
+} cpld_data_t;
+
+
+/* Pointer to the CPLD register set */
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value)\
+ cpld_write(offsetof(struct cpld_data, reg), value)
{
phys_size_t dram_size;
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
- puts(" DDR: ");
+#else
+ dram_size = fsl_ddr_sdram_size();
+#endif
return dram_size;
}
/* T1040RDB only supports SGMII on DTSEC3 */
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_SGMII1_PHY_ADDR);
+ break;
#endif
case PHY_INTERFACE_MODE_RGMII:
if (FM1_DTSEC4 == i)
--- /dev/null
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return CONFIG_DDR_CLK_FREQ;
+}
+
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, uart_clk;
+#ifdef CONFIG_SPL_NAND_BOOT
+ u32 porsr1, pinctl;
+#endif
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ /*
+ * There is T1040 SoC issue where NOR, FPGA are inaccessible during
+ * NAND boot because IFC signals > IFC_AD7 are not enabled.
+ * This workaround changes RCW source to make all signals enabled.
+ */
+ porsr1 = in_be32(&gur->porsr1);
+ pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
+ out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
+#endif
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ /* compiler optimization barrier needed for GCC >= 3.4 */
+ __asm__ __volatile__("" : : : "memory");
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ uart_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ uart_clk / 16 / CONFIG_BAUDRATE);
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+#endif
+
+ /* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ puts("\n\n");
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 80000002 e8106000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+06000002 00400002 e8106000 01000000
+00000000 00000000 00000000 00030810
+00000000 01fe0a06 00000000 00000000
--- /dev/null
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+091380c0 000FFFFF
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
+#include <asm/mpc85xx_gpio.h>
#include "t104xrdb.h"
+#include "cpld.h"
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
+ u8 sw;
printf("Board: %sRDB\n", cpu->name);
+ printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
+ CPLD_READ(hw_ver), CPLD_READ(sw_ver));
+
+ sw = CPLD_READ(flash_ctl_status);
+ sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
+
+ if (sw <= 7)
+ printf("vBank: %d\n", sw);
+ else
+ printf("Unsupported Bank=%x\n", sw);
+
return 0;
}
fdt_fixup_fman_ethernet(blob);
#endif
}
+
+#ifdef CONFIG_DEEP_SLEEP
+void board_mem_sleep_setup(void)
+{
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
+#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_16M, 1),
#endif
+#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 11, BOOKE_PAGESZ_256K, 1),
#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 12, BOOKE_PAGESZ_1G, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 13, BOOKE_PAGESZ_1G, 1)
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
# SPDX-License-Identifier: GPL-2.0+
#
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
obj-$(CONFIG_T2080QDS) += t208xqds.o
obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
obj-$(CONFIG_T2081QDS) += t208xqds.o
obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
obj-$(CONFIG_PCI) += pci.o
+endif
+
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
{
phys_size_t dram_size;
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
-
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
+#else
+ /* DDR has been initialised by first stage boot loader */
+ dram_size = fsl_ddr_sdram_size();
+#endif
- puts(" DDR: ");
return dram_size;
}
--- /dev/null
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+#include "../common/qixis.h"
+#include "t208xqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0F) {
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, ccb_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ ccb_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ puts("\nNAND boot...\n");
+#endif
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
+#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCIe 1, 0x80000000 */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_16M, 1),
#endif
+#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 18, BOOKE_PAGESZ_1M, 1),
#endif
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 19, BOOKE_PAGESZ_2G, 1)
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
# SPDX-License-Identifier: GPL-2.0+
#
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
obj-$(CONFIG_T2080RDB) += t208xrdb.o
obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
obj-$(CONFIG_T2080RDB) += cpld.o
obj-$(CONFIG_PCI) += pci.o
+endif
+
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
- One PCIe x2 end-point device (C293 Crypto co-processor)
- IFC/Local Bus
- NOR: 128MB 16-bit NOR Flash
- - NAND: 512MB 8-bit NAND flash
+ - NAND: 1GB 8-bit NAND flash
- CPLD: for system controlling with programable header on-board
- SATA
- Two SATA 2.0 onnectors on-board
0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB
0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
-0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
+0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
0xE8000000 0xE801FFFF RCW (current bank) 128KB
------------------------------------------
1. NOR boot:
a. build NOR boot image
- $ make T2080RDB
+ $ make T2080RDB_config
+ $ make
b. program u-boot.bin image to NOR flash
=> tftp 1000000 u-boot.bin
=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
Switching between default bank and alternate bank on NOR flash
To change boot source to vbank4:
via software: run command 'cpld reset altbank' in u-boot.
- via DIP-switch: set SW3[5:7] = '011'
+ via DIP-switch: set SW3[5:7] = '100'
To change boot source to vbank0:
via software: run command 'cpld reset' in u-boot.
- via DIP-Switch: set SW3[5:7] = '111'
+ via DIP-Switch: set SW3[5:7] = '000'
2. NAND Boot:
a. build PBL image for NAND boot
$ make T2080RDB_NAND_config
- $ make u-boot.pbl
- b. program u-boot.pbl to NAND flash
- => tftp 1000000 u-boot.pbl
+ $ make
+ b. program u-boot-with-spl-pbl.bin to NAND flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
=> nand erase 0 d0000
=> nand write 1000000 0 $filesize
set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
3. SPI Boot:
a. build PBL image for SPI boot
$ make T2080RDB_SPIFLASH_config
- $ make u-boot.pbl
- b. program u-boot.pbl to SPI flash
- => tftp 1000000 u-boot.pbl
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SPI flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
=> sf probe 0
=> sf erase 0 d0000
=> sf write 1000000 0 $filesize
4. SD Boot:
a. build PBL image for SD boot
$ make T2080RDB_SDCARD_config
- $ make u-boot.pbl
- b. program u-boot.pbl to TF card
- => tftp 1000000 u-boot.pbl
- => mmc write 1000000 8 1650
+ $ make
+ b. program u-boot-with-spl-pbl.bin to micro-SD/TF card
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => mmc write 1000000 8 0x800
set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+2-stage NAND/SPI/SD boot loader
+-------------------------------
+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
+SPL further initializes DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area | Address |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB) |
+-------------------------------------------------
+|GD, BD | 0xFFFC8000 (4KB) |
+-------------------------------------------------
+|ENV | 0xFFFC9000 (8KB) |
+-------------------------------------------------
+|HEAP | 0xFFFCB000 (50KB) |
+-------------------------------------------------
+|STACK | 0xFFFD8000 (22KB) |
+-------------------------------------------------
+|U-boot SPL | 0xFFFD8000 (160KB) |
+-------------------------------------------------
+
+NAND Flash memory Map on T2080RDB
+--------------------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB (2 blocks)
+0x100000 0x17FFFF u-boot env 512KB (1 block)
+0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
+0x200000 0x27FFFF CS4315 ucode 512KB (1 block)
+
+
+Micro SD Card memory Map on T2080RDB
+----------------------------------------------------
+Block #blocks Definition Size
+0x008 2048 u-boot img 1MB
+0x800 0016 u-boot env 8KB
+0x820 0128 FMAN ucode 64KB
+0x8a0 0512 CS4315 ucode 256KB
+
+
+SPI Flash memory Map on T2080RDB
+----------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB
+0x100000 0x101FFF u-boot env 8KB
+0x110000 0x11FFFF FMAN ucode 64KB
+0x120000 0x15FFFF CS4315 ucode 256KB
+
+
How to update the ucode of Cortina CS4315/CS4340 10G PHY
--------------------------------------------------------
=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt
#define CPLD_LBMAP_MASK 0x3F
#define CPLD_BANK_SEL_MASK 0x07
#define CPLD_BANK_OVERRIDE 0x40
-#define CPLD_LBMAP_ALTBANK 0x43 /* BANK OR | BANK 4 */
-#define CPLD_LBMAP_DFLTBANK 0x47 /* BANK OR | BANK 0 */
+#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
+#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
#define CPLD_BOOT_SEL 0x80
{
phys_size_t dram_size;
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
-
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
-
- puts(" DDR: ");
+#else
+ /* DDR has been initialised by first stage boot loader */
+ dram_size = fsl_ddr_sdram_size();
+#endif
return dram_size;
}
--- /dev/null
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return CONFIG_DDR_CLK_FREQ;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, ccb_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ ccb_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ puts("\nNAND boot...\n");
+#endif
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
puts("NAND\n");
} else {
reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
- printf("NOR vBank%d\n", ~reg & 0x7);
+ printf("NOR vBank%d\n", reg);
}
#endif
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
+#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCIe 1, 0x80000000 */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_16M, 1),
#endif
+#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 18, BOOKE_PAGESZ_1M, 1),
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 19, BOOKE_PAGESZ_2G, 1)
# SPDX-License-Identifier: GPL-2.0+
#
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
obj-$(CONFIG_T4240QDS) += t4240qds.o
obj-$(CONFIG_T4240EMU) += t4240emu.o
-obj-y += ddr.o
obj-$(CONFIG_T4240QDS)+= eth.o
obj-$(CONFIG_PCI) += pci.o
+endif
+obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
puts("Initializing....using SPD\n");
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
- puts(" DDR: ");
+#else
+ /* DDR has been initialised by first stage boot loader */
+ dram_size = fsl_ddr_sdram_size();
+#endif
return dram_size;
}
--- /dev/null
+/* Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/spl.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include "../common/qixis.h"
+#include "t4240qds_qixis.h"
+
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0F) {
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, ccb_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#ifdef CONFIG_SPL_NAND_BOOT
+ u32 porsr1, pinctl;
+#endif
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ porsr1 = in_be32(&gur->porsr1);
+ pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
+ out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
+#endif
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ /* compiler optimization barrier needed for GCC >= 3.4 */
+ __asm__ __volatile__("" : : : "memory");
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ ccb_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ puts("\nNAND boot...\n");
+#endif
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
09000d00 00000000
09000d04 fff80000
09000d08 81000012
-#workaround for IFC bus speed
-091241c0 f03f3f3f
-091241c4 ff003f3f
-09124010 00000101
-09124130 0000000c
-#workaround for SERDES A-006031
-090ea000 064740e6
-090ea020 064740e6
-090eb000 064740e6
-090eb020 064740e6
-090ec000 064740e6
-090ec020 064740e6
-090ed000 064740e6
-090ed020 064740e6
#Configure alternate space
09000010 00000000
09000014 ff000000
#PBL preamble and RCW header
aa55aa55 010e0100
#serdes protocol 1_28_6_12
-120c0019 0c101915 00000000 00000000
-04383063 30548c00 6c020000 1d000000
+16070019 18101916 00000000 00000000
+04383060 30548c00 ec020000 f5000000
00000000 ee0000ee 00000000 000307fc
-00000000 00000000 00000000 00000020
+00000000 00000000 00000000 00000028
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
-
+#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_16M, 1),
#endif
+#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 18, BOOKE_PAGESZ_1M, 1),
#endif
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 19, BOOKE_PAGESZ_2G, 1)
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
Active powerpc mpc85xx - - socrates socrates - -
Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com>
Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 -
-Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 -
-Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale b4860qds B4860QDS_SECURE_BOOT B4860QDS:PPC_B4860,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND
Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal <poonam.aggrwal@freescale.com>
Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
-Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
-Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale t1040qds T1040QDS_D4 T1040QDS:PPC_T1040,SYS_FSL_DDR4 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale t1040qds T1040QDS_SECURE_BOOT T1040QDS:PPC_T1040,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1040RDB T104xRDB:PPC_T1040,T1040RDB Priyanka Jain <Priyanka.Jain@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1040RDB_NAND T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND Priyanka Jain <Priyanka.Jain@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SDCARD T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
+Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SECURE_BOOT T104xRDB:PPC_T1040,SECURE_BOOT,T1040RDB Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SPIFLASH T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Priyanka Jain <Priyanka.Jain@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T104xRDB:PPC_T1042,T1042RDB_PI Priyanka Jain <Priyanka.Jain@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_NAND T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND Priyanka Jain <Priyanka.Jain@freescale.com>
+Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SDCARD T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
+Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SPIFLASH T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Priyanka Jain <Priyanka.Jain@freescale.com>
Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 -
-Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SECURE_BOOT T208xQDS:PPC_T2080,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
+Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH
Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081 -
-Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
+Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH -
Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080 -
-Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND
+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH
Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
-Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t4qds T4160QDS_SECURE_BOOT T4240QDS:PPC_T4160,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale t4qds T4160QDS_NAND T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
+Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun@freescale.com>
Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 -
-Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
-Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale t4qds T4240QDS_SECURE_BOOT T4240QDS:PPC_T4240,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
+Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+Active powerpc mpc85xx - freescale qemu-ppce500 qemu-ppce500 - Alexander Graf <agraf@suse.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de>
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
return 1;
}
}
+
+unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd)
+{
+ char *p = (char *)spd;
+ int csum16;
+ int len;
+ char crc_lsb; /* byte 126 */
+ char crc_msb; /* byte 127 */
+
+ len = 126;
+ csum16 = crc16(p, len);
+
+ crc_lsb = (char) (csum16 & 0xff);
+ crc_msb = (char) (csum16 >> 8);
+
+ if (spd->crc[0] != crc_lsb || spd->crc[1] != crc_msb) {
+ printf("SPD checksum unexpected.\n"
+ "Checksum lsb in SPD = %02X, computed SPD = %02X\n"
+ "Checksum msb in SPD = %02X, computed SPD = %02X\n",
+ spd->crc[0], crc_lsb, spd->crc[1], crc_msb);
+ return 1;
+ }
+
+ p = (char *)((ulong)spd + 128);
+ len = 126;
+ csum16 = crc16(p, len);
+
+ crc_lsb = (char) (csum16 & 0xff);
+ crc_msb = (char) (csum16 >> 8);
+
+ if (spd->mod_section.uc[126] != crc_lsb ||
+ spd->mod_section.uc[127] != crc_msb) {
+ printf("SPD checksum unexpected.\n"
+ "Checksum lsb in SPD = %02X, computed SPD = %02X\n"
+ "Checksum msb in SPD = %02X, computed SPD = %02X\n",
+ spd->mod_section.uc[126],
+ crc_lsb, spd->mod_section.uc[127],
+ crc_msb);
+ return 1;
+ }
+
+ return 0;
+}
}
}
+/**
+ * fdt_getprop_u32_default_node - Return a node's property or a default
+ *
+ * @fdt: ptr to device tree
+ * @off: offset of node
+ * @cell: cell offset in property
+ * @prop: property name
+ * @dflt: default value if the property isn't found
+ *
+ * Convenience function to return a node's property or a default value if
+ * the property doesn't exist.
+ */
+u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell,
+ const char *prop, const u32 dflt)
+{
+ const fdt32_t *val;
+ int len;
+
+ val = fdt_getprop(fdt, off, prop, &len);
+
+ /* Check if property exists */
+ if (!val)
+ return dflt;
+
+ /* Check if property is long enough */
+ if (len < ((cell + 1) * sizeof(uint32_t)))
+ return dflt;
+
+ return fdt32_to_cpu(*val);
+}
+
/**
* fdt_getprop_u32_default - Find a node and return it's property or a default
*
u32 fdt_getprop_u32_default(const void *fdt, const char *path,
const char *prop, const u32 dflt)
{
- const fdt32_t *val;
int off;
off = fdt_path_offset(fdt, path);
if (off < 0)
return dflt;
- val = fdt_getprop(fdt, off, prop, NULL);
- if (val)
- return fdt32_to_cpu(*val);
- else
- return dflt;
+ return fdt_getprop_u32_default_node(fdt, off, 0, prop, dflt);
}
/**
return prop ? fdt_translate_address(fdt, node, prop + naddr) : 0;
}
+
+/*
+ * Read a property of size <prop_len>. Currently only supports 1 or 2 cells.
+ */
+static int fdt_read_prop(const fdt32_t *prop, int prop_len, int cell_off,
+ uint64_t *val, int cells)
+{
+ const fdt32_t *prop32 = &prop[cell_off];
+ const fdt64_t *prop64 = (const fdt64_t *)&prop[cell_off];
+
+ if ((cell_off + cells) > prop_len)
+ return -FDT_ERR_NOSPACE;
+
+ switch (cells) {
+ case 1:
+ *val = fdt32_to_cpu(*prop32);
+ break;
+ case 2:
+ *val = fdt64_to_cpu(*prop64);
+ break;
+ default:
+ return -FDT_ERR_NOSPACE;
+ }
+
+ return 0;
+}
+
+/**
+ * fdt_read_range - Read a node's n'th range property
+ *
+ * @fdt: ptr to device tree
+ * @node: offset of node
+ * @n: range index
+ * @child_addr: pointer to storage for the "child address" field
+ * @addr: pointer to storage for the CPU view translated physical start
+ * @len: pointer to storage for the range length
+ *
+ * Convenience function that reads and interprets a specific range out of
+ * a number of the "ranges" property array.
+ */
+int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr,
+ uint64_t *addr, uint64_t *len)
+{
+ int pnode = fdt_parent_offset(fdt, node);
+ const fdt32_t *ranges;
+ int pacells;
+ int acells;
+ int scells;
+ int ranges_len;
+ int cell = 0;
+ int r = 0;
+
+ /*
+ * The "ranges" property is an array of
+ * { <child address> <parent address> <size in child address space> }
+ *
+ * All 3 elements can span a diffent number of cells. Fetch their size.
+ */
+ pacells = fdt_getprop_u32_default_node(fdt, pnode, 0, "#address-cells", 1);
+ acells = fdt_getprop_u32_default_node(fdt, node, 0, "#address-cells", 1);
+ scells = fdt_getprop_u32_default_node(fdt, node, 0, "#size-cells", 1);
+
+ /* Now try to get the ranges property */
+ ranges = fdt_getprop(fdt, node, "ranges", &ranges_len);
+ if (!ranges)
+ return -FDT_ERR_NOTFOUND;
+ ranges_len /= sizeof(uint32_t);
+
+ /* Jump to the n'th entry */
+ cell = n * (pacells + acells + scells);
+
+ /* Read <child address> */
+ if (child_addr) {
+ r = fdt_read_prop(ranges, ranges_len, cell, child_addr,
+ acells);
+ if (r)
+ return r;
+ }
+ cell += acells;
+
+ /* Read <parent address> */
+ if (addr)
+ *addr = fdt_translate_address(fdt, node, ranges + cell);
+ cell += pacells;
+
+ /* Read <size in child address space> */
+ if (len) {
+ r = fdt_read_prop(ranges, ranges_len, cell, len, scells);
+ if (r)
+ return r;
+ }
+
+ return 0;
+}
On Linux the interfaces are renamed as:
. eth2 -> fm1-gb2
. eth3 -> fm1-gb3
+
+NAND boot with 2 Stage boot loader
+----------------------------------
+PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
+SPL further initialise DDR using SPD and environment variables and copy
+u-boot(768 KB) from flash to DDR.
+Finally SPL transer control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+ Run time view of SPL framework during boot :-
+ -----------------------------------------------
+ Area | Address |
+-----------------------------------------------
+ Secure boot | 0xFFFC0000 (32KB) |
+ headers | |
+ -----------------------------------------------
+ GD, BD | 0xFFFC8000 (4KB) |
+ -----------------------------------------------
+ ENV | 0xFFFC9000 (8KB) |
+ -----------------------------------------------
+ HEAP | 0xFFFCB000 (30KB) |
+ -----------------------------------------------
+ STACK | 0xFFFD8000 (22KB) |
+ -----------------------------------------------
+ U-boot SPL | 0xFFFD8000 (160KB) |
+ -----------------------------------------------
+
+NAND Flash memory Map on B4860 and B4420QDS
+------------------------------------------
+ Start End Definition Size
+0x000000 0x0FFFFF u-boot 1MB
+0x140000 0x15FFFF u-boot env 128KB
+0x1A0000 0x1BFFFF FMAN Ucode 128KB
Note: voltage adjustment needs to be done step by step. Changing voltage too
rapidly may cause current surge. The voltage stepping is done by software.
Users can set the final voltage directly.
+
+2-stage NAND/SD boot loader
+-------------------------------
+PBL initializes the internal SRAM and copy SPL(160K) in SRAM.
+SPL further initialise DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area | Address |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB) |
+-------------------------------------------------
+|GD, BD | 0xFFFC8000 (4KB) |
+-------------------------------------------------
+|ENV | 0xFFFC9000 (8KB) |
+-------------------------------------------------
+|HEAP | 0xFFFCB000 (50KB) |
+-------------------------------------------------
+|STACK | 0xFFFD8000 (22KB) |
+-------------------------------------------------
+|U-boot SPL | 0xFFFD8000 (160KB) |
+-------------------------------------------------
+
+NAND Flash memory Map on T4QDS
+--------------------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB
+0x140000 0x15FFFF u-boot env 128KB
+0x160000 0x17FFFF FMAN Ucode 128KB
+
+Micro SD Card memory Map on T4QDS
+----------------------------------------------------
+Block #blocks Definition Size
+0x008 2048 u-boot img 1MB
+0x800 0016 u-boot env 8KB
+0x820 0128 FMAN ucode 64KB
+
+Switch Settings: (ON is 1, OFF is 0)
+===============
+NAND boot SW setting:
+SW1[1:8] = 10000010
+SW2[1.1] = 0
+SW6[1:4] = 1001
+
+SD boot SW setting:
+SW1[1:8] = 00100000
+SW2[1.1] = 0
#
-# Copyright 2008-2011 Freescale Semiconductor, Inc.
+# Copyright 2008-2014 Freescale Semiconductor, Inc.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License
# Version 2 as published by the Free Software Foundation.
#
-obj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
- lc_common_dimm_params.o
+obj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
+ lc_common_dimm_params.o
+obj-$(CONFIG_SYS_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
+ lc_common_dimm_params.o
+obj-$(CONFIG_SYS_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
+ lc_common_dimm_params.o
+obj-$(CONFIG_SYS_FSL_DDR4) += main.o util.o ctrl_regs.o options.o \
+ lc_common_dimm_params.o
-obj-$(CONFIG_SYS_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
- lc_common_dimm_params.o
-
-obj-$(CONFIG_SYS_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
- lc_common_dimm_params.o
ifdef CONFIG_DDR_SPD
SPD := y
endif
obj-$(CONFIG_SYS_FSL_DDR1) += ddr1_dimm_params.o
obj-$(CONFIG_SYS_FSL_DDR2) += ddr2_dimm_params.o
obj-$(CONFIG_SYS_FSL_DDR3) += ddr3_dimm_params.o
+obj-$(CONFIG_SYS_FSL_DDR4) += ddr4_dimm_params.o
endif
obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
+obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <fsl_immap.h>
#include <asm/io.h>
-#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
-
-static u32 fsl_ddr_get_version(void)
-{
- struct ccsr_ddr __iomem *ddr;
- u32 ver_major_minor_errata;
-
- ddr = (void *)_DDR_ADDR;
- ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
- ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
-
- return ver_major_minor_errata;
-}
-
unsigned int picos_to_mclk(unsigned int picos);
/*
return rtt;
}
+#ifdef CONFIG_SYS_FSL_DDR4
+/*
+ * compute CAS write latency according to DDR4 spec
+ * CWL = 9 for <= 1600MT/s
+ * 10 for <= 1866MT/s
+ * 11 for <= 2133MT/s
+ * 12 for <= 2400MT/s
+ * 14 for <= 2667MT/s
+ * 16 for <= 2933MT/s
+ * 18 for higher
+ */
+static inline unsigned int compute_cas_write_latency(void)
+{
+ unsigned int cwl;
+ const unsigned int mclk_ps = get_memory_clk_period_ps();
+ if (mclk_ps >= 1250)
+ cwl = 9;
+ else if (mclk_ps >= 1070)
+ cwl = 10;
+ else if (mclk_ps >= 935)
+ cwl = 11;
+ else if (mclk_ps >= 833)
+ cwl = 12;
+ else if (mclk_ps >= 750)
+ cwl = 14;
+ else if (mclk_ps >= 681)
+ cwl = 16;
+ else
+ cwl = 18;
+
+ return cwl;
+}
+#else
/*
* compute the CAS write latency according to DDR3 spec
* CWL = 5 if tCK >= 2.5ns
}
return cwl;
}
+#endif
/* Chip Select Configuration (CSn_CONFIG) */
static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
int go_config = 0;
+#ifdef CONFIG_SYS_FSL_DDR4
+ unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
+#else
+ unsigned int n_banks_per_sdram_device;
+#endif
/* Compute CS_CONFIG only for existing ranks of each DIMM. */
switch (i) {
break;
}
if (go_config) {
- unsigned int n_banks_per_sdram_device;
cs_n_en = 1;
ap_n_en = popts->cs_local_opts[i].auto_precharge;
odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
+#ifdef CONFIG_SYS_FSL_DDR4
+ ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
+ bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
+#else
n_banks_per_sdram_device
= dimm_params[dimm_number].n_banks_per_sdram_device;
ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
+#endif
row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
}
| ((ba_bits_cs_n & 0x3) << 14)
| ((row_bits_cs_n & 0x7) << 8)
+#ifdef CONFIG_SYS_FSL_DDR4
+ | ((bg_bits_cs_n & 0x3) << 4)
+#endif
| ((col_bits_cs_n & 0x7) << 0)
);
debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
/* Precharge powerdown exit timing (tXP). */
unsigned char pre_pd_exit_mclk;
/* ODT powerdown exit timing (tAXPD). */
- unsigned char taxpd_mclk;
+ unsigned char taxpd_mclk = 0;
/* Mode register set cycle time (tMRD). */
unsigned char tmrd_mclk;
-#ifdef CONFIG_SYS_FSL_DDR3
+#ifdef CONFIG_SYS_FSL_DDR4
+ /* tXP=max(4nCK, 6ns) */
+ int txp = max((get_memory_clk_period_ps() * 4), 6000); /* unit=ps */
+ trwt_mclk = 2;
+ twrt_mclk = 1;
+ act_pd_exit_mclk = picos_to_mclk(txp);
+ pre_pd_exit_mclk = act_pd_exit_mclk;
+ /*
+ * MRS_CYC = max(tMRD, tMOD)
+ * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
+ */
+ tmrd_mclk = max(24, picos_to_mclk(15000));
+#elif defined(CONFIG_SYS_FSL_DDR3)
/*
* (tXARD and tXARDS). Empirical?
* The DDR3 spec has not tXARD,
* spec has not the tAXPD, we use
* tAXPD=1, need design to confirm.
*/
- int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
+ int txp = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
unsigned int data_rate = get_ddr_freq(0);
tmrd_mclk = 4;
/* set the turnaround time */
taxpd_mclk = 1;
} else {
/* act_pd_exit_mclk = tXARD, see above */
- act_pd_exit_mclk = picos_to_mclk(tXP);
+ act_pd_exit_mclk = picos_to_mclk(txp);
/* Mode register MR0[A12] is '1' - fast exit */
pre_pd_exit_mclk = act_pd_exit_mclk;
taxpd_mclk = 1;
ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
ext_caslat = (2 * cas_latency - 1) >> 4;
ext_add_lat = additive_latency >> 4;
+#ifdef CONFIG_SYS_FSL_DDR4
+ ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4;
+#else
ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
+#endif
ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
(popts->otf_burst_chop_en ? 2 : 0)) >> 4;
unsigned char acttoact_mclk;
/* Last write data pair to read command issue interval (tWTR) */
unsigned char wrtord_mclk;
+#ifdef CONFIG_SYS_FSL_DDR4
+ /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
+ static const u8 wrrec_table[] = {
+ 10, 10, 10, 10, 10,
+ 10, 10, 10, 10, 10,
+ 12, 12, 14, 14, 16,
+ 16, 18, 18, 20, 20,
+ 24, 24, 24, 24};
+#else
/* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
static const u8 wrrec_table[] = {
1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
+#endif
pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
* we need set extend bit for it at
* TIMING_CFG_3[EXT_CASLAT]
*/
- caslat_ctrl = 2 * cas_latency - 1;
+ if (fsl_ddr_get_version() <= 0x40400)
+ caslat_ctrl = 2 * cas_latency - 1;
+ else
+ caslat_ctrl = (cas_latency - 1) << 1;
#endif
+#ifdef CONFIG_SYS_FSL_DDR4
+ refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
+ wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
+ acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4);
+ wrtord_mclk = max(2, picos_to_mclk(2500));
+ if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
+ printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
+ else
+ wrrec_mclk = wrrec_table[wrrec_mclk - 1];
+#else
refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
-
- if (wrrec_mclk > 16)
- printf("Error: WRREC doesn't support more than 16 clocks\n");
+ acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
+ wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
+ if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
+ printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
else
wrrec_mclk = wrrec_table[wrrec_mclk - 1];
+#endif
if (popts->otf_burst_chop_en)
wrrec_mclk += 2;
- acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
/*
* JEDEC has min requirement for tRRD
*/
if (acttoact_mclk < 4)
acttoact_mclk = 4;
#endif
- wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
/*
* JEDEC has some min requirements for tWTR
*/
wr_lat = compute_cas_write_latency();
#endif
+#ifdef CONFIG_SYS_FSL_DDR4
+ rd_to_pre = picos_to_mclk(7500);
+#else
rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
+#endif
/*
* JEDEC has some min requirements for tRTP
*/
#if defined(CONFIG_SYS_FSL_DDR2)
if (rd_to_pre < 2)
rd_to_pre = 2;
-#elif defined(CONFIG_SYS_FSL_DDR3)
+#elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
if (rd_to_pre < 4)
rd_to_pre = 4;
#endif
rd_to_pre += 2; /* according to UM */
wr_data_delay = popts->write_data_delay;
+#ifdef CONFIG_SYS_FSL_DDR4
+ cpo = 0;
+ cke_pls = max(3, picos_to_mclk(5000));
+#else
cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
+#endif
+
four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
ddr->timing_cfg_2 = (0
| ((add_lat_mclk & 0xf) << 28)
| ((cpo & 0x1f) << 23)
| ((wr_lat & 0xf) << 19)
+ | ((wr_lat & 0x10) << 14)
| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
| ((cke_pls & 0x7) << 6)
* we must clear it when use the on-the-fly mode,
* must set it when use the 32-bits bus mode.
*/
- if (sdram_type == SDRAM_TYPE_DDR3) {
+ if ((sdram_type == SDRAM_TYPE_DDR3) ||
+ (sdram_type == SDRAM_TYPE_DDR4)) {
if (popts->burst_length == DDR_BL8)
eight_be = 1;
if (popts->burst_length == DDR_OTF)
{
unsigned int frc_sr = 0; /* Force self refresh */
unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
- unsigned int dll_rst_dis; /* DLL reset disable */
- unsigned int dqs_cfg; /* DQS configuration */
unsigned int odt_cfg = 0; /* ODT configuration */
unsigned int num_pr; /* Number of posted refreshes */
unsigned int slow = 0; /* DDR will be run less than 1250 */
unsigned int md_en = 0; /* Mirrored DIMM Enable */
unsigned int qd_en = 0; /* quad-rank DIMM Enable */
int i;
+#ifndef CONFIG_SYS_FSL_DDR4
+ unsigned int dll_rst_dis = 1; /* DLL reset disable */
+ unsigned int dqs_cfg; /* DQS configuration */
- dll_rst_dis = 1; /* Make this configurable */
dqs_cfg = popts->dqs_config;
+#endif
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (popts->cs_local_opts[i].odt_rd_cfg
|| popts->cs_local_opts[i].odt_wr_cfg) {
* * ({EXT_REFREC || REFREC} + 8 + 2)]}
* << DDR_SDRAM_INTERVAL[REFINT]
*/
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
obc_cfg = popts->otf_burst_chop_en;
#else
obc_cfg = 0;
d_init = 0;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
md_en = popts->mirrored_dimm;
#endif
qd_en = popts->quad_rank_present ? 1 : 0;
ddr->ddr_sdram_cfg_2 = (0
| ((frc_sr & 0x1) << 31)
| ((sr_ie & 0x1) << 30)
+#ifndef CONFIG_SYS_FSL_DDR4
| ((dll_rst_dis & 0x1) << 29)
| ((dqs_cfg & 0x3) << 26)
+#endif
| ((odt_cfg & 0x3) << 21)
| ((num_pr & 0xf) << 12)
| ((slow & 1) << 11)
debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
}
+#ifdef CONFIG_SYS_FSL_DDR4
/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
{
unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
+ int i;
+ unsigned int wr_crc = 0; /* Disable */
+ unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
+ unsigned int srt = 0; /* self-refresh temerature, normal range */
+ unsigned int cwl = compute_cas_write_latency() - 9;
+ unsigned int mpr = 0; /* serial */
+ unsigned int wc_lat;
+ const unsigned int mclk_ps = get_memory_clk_period_ps();
-#if defined(CONFIG_SYS_FSL_DDR3)
+ if (popts->rtt_override)
+ rtt_wr = popts->rtt_wr_override_value;
+ else
+ rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
+
+ if (common_dimm->extended_op_srt)
+ srt = common_dimm->extended_op_srt;
+
+ esdmode2 = (0
+ | ((wr_crc & 0x1) << 12)
+ | ((rtt_wr & 0x3) << 9)
+ | ((srt & 0x3) << 6)
+ | ((cwl & 0x7) << 3));
+
+ if (mclk_ps >= 1250)
+ wc_lat = 0;
+ else if (mclk_ps >= 833)
+ wc_lat = 1;
+ else
+ wc_lat = 2;
+
+ esdmode3 = (0
+ | ((mpr & 0x3) << 11)
+ | ((wc_lat & 0x3) << 9));
+
+ ddr->ddr_sdram_mode_2 = (0
+ | ((esdmode2 & 0xFFFF) << 16)
+ | ((esdmode3 & 0xFFFF) << 0)
+ );
+ debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
+
+ if (unq_mrs_en) { /* unique mode registers are supported */
+ for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (popts->rtt_override)
+ rtt_wr = popts->rtt_wr_override_value;
+ else
+ rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
+
+ esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
+ esdmode2 |= (rtt_wr & 0x3) << 9;
+ switch (i) {
+ case 1:
+ ddr->ddr_sdram_mode_4 = (0
+ | ((esdmode2 & 0xFFFF) << 16)
+ | ((esdmode3 & 0xFFFF) << 0)
+ );
+ break;
+ case 2:
+ ddr->ddr_sdram_mode_6 = (0
+ | ((esdmode2 & 0xFFFF) << 16)
+ | ((esdmode3 & 0xFFFF) << 0)
+ );
+ break;
+ case 3:
+ ddr->ddr_sdram_mode_8 = (0
+ | ((esdmode2 & 0xFFFF) << 16)
+ | ((esdmode3 & 0xFFFF) << 0)
+ );
+ break;
+ }
+ }
+ debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
+ ddr->ddr_sdram_mode_4);
+ debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
+ ddr->ddr_sdram_mode_6);
+ debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
+ ddr->ddr_sdram_mode_8);
+ }
+}
+#elif defined(CONFIG_SYS_FSL_DDR3)
+/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
+static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ const unsigned int unq_mrs_en)
+{
+ unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
+ unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
int i;
unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
unsigned int srt = 0; /* self-refresh temerature, normal range */
| ((asr & 0x1) << 6)
| ((cwl & 0x7) << 3)
| ((pasr & 0x7) << 0));
-#endif
ddr->ddr_sdram_mode_2 = (0
| ((esdmode2 & 0xFFFF) << 16)
| ((esdmode3 & 0xFFFF) << 0)
);
debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
-#ifdef CONFIG_SYS_FSL_DDR3
if (unq_mrs_en) { /* unique mode registers are supported */
for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (popts->rtt_override)
debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
ddr->ddr_sdram_mode_8);
}
+}
+
+#else /* for DDR2 and DDR1 */
+/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
+static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ const unsigned int unq_mrs_en)
+{
+ unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
+ unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
+
+ ddr->ddr_sdram_mode_2 = (0
+ | ((esdmode2 & 0xFFFF) << 16)
+ | ((esdmode3 & 0xFFFF) << 0)
+ );
+ debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
+}
#endif
+
+#ifdef CONFIG_SYS_FSL_DDR4
+/* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
+static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ const unsigned int unq_mrs_en)
+{
+ int i;
+ unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */
+ unsigned short esdmode5; /* Extended SDRAM mode 5 */
+
+ esdmode5 = 0x00000400; /* Data mask enabled */
+
+ ddr->ddr_sdram_mode_9 = (0
+ | ((esdmode4 & 0xffff) << 16)
+ | ((esdmode5 & 0xffff) << 0)
+ );
+ debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
+ if (unq_mrs_en) { /* unique mode registers are supported */
+ for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ switch (i) {
+ case 1:
+ ddr->ddr_sdram_mode_11 = (0
+ | ((esdmode4 & 0xFFFF) << 16)
+ | ((esdmode5 & 0xFFFF) << 0)
+ );
+ break;
+ case 2:
+ ddr->ddr_sdram_mode_13 = (0
+ | ((esdmode4 & 0xFFFF) << 16)
+ | ((esdmode5 & 0xFFFF) << 0)
+ );
+ break;
+ case 3:
+ ddr->ddr_sdram_mode_15 = (0
+ | ((esdmode4 & 0xFFFF) << 16)
+ | ((esdmode5 & 0xFFFF) << 0)
+ );
+ break;
+ }
+ }
+ debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
+ ddr->ddr_sdram_mode_11);
+ debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
+ ddr->ddr_sdram_mode_13);
+ debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
+ ddr->ddr_sdram_mode_15);
+ }
+}
+
+/* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
+static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ const unsigned int unq_mrs_en)
+{
+ int i;
+ unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
+ unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
+ unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps);
+
+ esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
+
+ ddr->ddr_sdram_mode_10 = (0
+ | ((esdmode6 & 0xffff) << 16)
+ | ((esdmode7 & 0xffff) << 0)
+ );
+ debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
+ if (unq_mrs_en) { /* unique mode registers are supported */
+ for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ switch (i) {
+ case 1:
+ ddr->ddr_sdram_mode_12 = (0
+ | ((esdmode6 & 0xFFFF) << 16)
+ | ((esdmode7 & 0xFFFF) << 0)
+ );
+ break;
+ case 2:
+ ddr->ddr_sdram_mode_14 = (0
+ | ((esdmode6 & 0xFFFF) << 16)
+ | ((esdmode7 & 0xFFFF) << 0)
+ );
+ break;
+ case 3:
+ ddr->ddr_sdram_mode_16 = (0
+ | ((esdmode6 & 0xFFFF) << 16)
+ | ((esdmode7 & 0xFFFF) << 0)
+ );
+ break;
+ }
+ }
+ debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
+ ddr->ddr_sdram_mode_12);
+ debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
+ ddr->ddr_sdram_mode_14);
+ debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
+ ddr->ddr_sdram_mode_16);
+ }
}
+#endif
+
/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
}
-#if defined(CONFIG_SYS_FSL_DDR3)
+#ifdef CONFIG_SYS_FSL_DDR4
/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
unsigned int additive_latency,
const unsigned int unq_mrs_en)
{
+ int i;
+ unsigned short esdmode; /* Extended SDRAM mode */
+ unsigned short sdmode; /* SDRAM mode */
+
+ /* Mode Register - MR1 */
+ unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
+ unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
+ unsigned int rtt;
+ unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
+ unsigned int al = 0; /* Posted CAS# additive latency (AL) */
+ unsigned int dic = 0; /* Output driver impedance, 40ohm */
+ unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal),
+ 0=Disable (Test/Debug) */
+
+ /* Mode Register - MR0 */
+ unsigned int wr = 0; /* Write Recovery */
+ unsigned int dll_rst; /* DLL Reset */
+ unsigned int mode; /* Normal=0 or Test=1 */
+ unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
+ /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
+ unsigned int bt;
+ unsigned int bl; /* BL: Burst Length */
+
+ unsigned int wr_mclk;
+ /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
+ static const u8 wr_table[] = {
+ 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
+ /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
+ static const u8 cas_latency_table[] = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
+ 9, 9, 10, 10, 11, 11};
+
+ if (popts->rtt_override)
+ rtt = popts->rtt_override_value;
+ else
+ rtt = popts->cs_local_opts[0].odt_rtt_norm;
+
+ if (additive_latency == (cas_latency - 1))
+ al = 1;
+ if (additive_latency == (cas_latency - 2))
+ al = 2;
+
+ if (popts->quad_rank_present)
+ dic = 1; /* output driver impedance 240/7 ohm */
+
+ /*
+ * The esdmode value will also be used for writing
+ * MR1 during write leveling for DDR3, although the
+ * bits specifically related to the write leveling
+ * scheme will be handled automatically by the DDR
+ * controller. so we set the wrlvl_en = 0 here.
+ */
+ esdmode = (0
+ | ((qoff & 0x1) << 12)
+ | ((tdqs_en & 0x1) << 11)
+ | ((rtt & 0x7) << 8)
+ | ((wrlvl_en & 0x1) << 7)
+ | ((al & 0x3) << 3)
+ | ((dic & 0x3) << 1) /* DIC field is split */
+ | ((dll_en & 0x1) << 0)
+ );
+
+ /*
+ * DLL control for precharge PD
+ * 0=slow exit DLL off (tXPDLL)
+ * 1=fast exit DLL on (tXP)
+ */
+
+ wr_mclk = picos_to_mclk(common_dimm->twr_ps);
+ if (wr_mclk <= 24) {
+ wr = wr_table[wr_mclk - 10];
+ } else {
+ printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
+ wr_mclk);
+ }
+
+ dll_rst = 0; /* dll no reset */
+ mode = 0; /* normal mode */
+
+ /* look up table to get the cas latency bits */
+ if (cas_latency >= 9 && cas_latency <= 24)
+ caslat = cas_latency_table[cas_latency - 9];
+ else
+ printf("Error: unsupported cas latency for mode register\n");
+
+ bt = 0; /* Nibble sequential */
+
+ switch (popts->burst_length) {
+ case DDR_BL8:
+ bl = 0;
+ break;
+ case DDR_OTF:
+ bl = 1;
+ break;
+ case DDR_BC4:
+ bl = 2;
+ break;
+ default:
+ printf("Error: invalid burst length of %u specified. ",
+ popts->burst_length);
+ puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
+ bl = 1;
+ break;
+ }
+
+ sdmode = (0
+ | ((wr & 0x7) << 9)
+ | ((dll_rst & 0x1) << 8)
+ | ((mode & 0x1) << 7)
+ | (((caslat >> 1) & 0x7) << 4)
+ | ((bt & 0x1) << 3)
+ | ((caslat & 1) << 2)
+ | ((bl & 0x3) << 0)
+ );
+
+ ddr->ddr_sdram_mode = (0
+ | ((esdmode & 0xFFFF) << 16)
+ | ((sdmode & 0xFFFF) << 0)
+ );
+
+ debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
+
+ if (unq_mrs_en) { /* unique mode registers are supported */
+ for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (popts->rtt_override)
+ rtt = popts->rtt_override_value;
+ else
+ rtt = popts->cs_local_opts[i].odt_rtt_norm;
+
+ esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
+ esdmode |= (rtt & 0x7) << 8;
+ switch (i) {
+ case 1:
+ ddr->ddr_sdram_mode_3 = (0
+ | ((esdmode & 0xFFFF) << 16)
+ | ((sdmode & 0xFFFF) << 0)
+ );
+ break;
+ case 2:
+ ddr->ddr_sdram_mode_5 = (0
+ | ((esdmode & 0xFFFF) << 16)
+ | ((sdmode & 0xFFFF) << 0)
+ );
+ break;
+ case 3:
+ ddr->ddr_sdram_mode_7 = (0
+ | ((esdmode & 0xFFFF) << 16)
+ | ((sdmode & 0xFFFF) << 0)
+ );
+ break;
+ }
+ }
+ debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
+ ddr->ddr_sdram_mode_3);
+ debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
+ ddr->ddr_sdram_mode_5);
+ debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
+ ddr->ddr_sdram_mode_5);
+ }
+}
+
+#elif defined(CONFIG_SYS_FSL_DDR3)
+/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
+static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ unsigned int cas_latency,
+ unsigned int additive_latency,
+ const unsigned int unq_mrs_en)
+{
+ int i;
unsigned short esdmode; /* Extended SDRAM mode */
unsigned short sdmode; /* SDRAM mode */
*/
static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
- const unsigned int mclk_ps = get_memory_clk_period_ps();
- int i;
-
if (popts->rtt_override)
rtt = popts->rtt_override_value;
else
*/
dll_on = 1;
- wr_mclk = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps;
+ wr_mclk = picos_to_mclk(common_dimm->twr_ps);
if (wr_mclk <= 16) {
wr = wr_table[wr_mclk - 5];
} else {
unsigned int bt;
unsigned int bl; /* BL: Burst Length */
-#if defined(CONFIG_SYS_FSL_DDR2)
- const unsigned int mclk_ps = get_memory_clk_period_ps();
-#endif
dqs_en = !popts->dqs_config;
rtt = fsl_ddr_get_rtt();
#if defined(CONFIG_SYS_FSL_DDR1)
wr = 0; /* Historical */
#elif defined(CONFIG_SYS_FSL_DDR2)
- wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1;
+ wr = picos_to_mclk(common_dimm->twr_ps);
#endif
dll_res = 0;
mode = 0;
unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
if (popts->burst_length == DDR_BL8) {
/* We set BL/2 for fixed BL8 */
rrt = 0; /* BL/2 clocks */
rrt = 2; /* BL/2 + 2 clocks */
wwt = 2; /* BL/2 + 2 clocks */
}
+#endif
+
+#ifdef CONFIG_SYS_FSL_DDR4
+ dll_lock = 2; /* tDLLK = 1024 clocks */
+#elif defined(CONFIG_SYS_FSL_DDR3)
dll_lock = 1; /* tDLLK = 512 clocks from spec */
#endif
ddr->timing_cfg_4 = (0
unsigned int wodt_on = 0; /* Write to ODT on */
unsigned int wodt_off = 0; /* Write to ODT off */
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
+ unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
+ ((ddr->timing_cfg_2 & 0x00040000) >> 14);
/* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
- rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
+ if (cas_latency >= wr_lat)
+ rodt_on = cas_latency - wr_lat + 1;
rodt_off = 4; /* 4 clocks */
wodt_on = 1; /* 1 clocks */
wodt_off = 4; /* 4 clocks */
debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
}
+#ifdef CONFIG_SYS_FSL_DDR4
+static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
+{
+ unsigned int hs_caslat = 0;
+ unsigned int hs_wrlat = 0;
+ unsigned int hs_wrrec = 0;
+ unsigned int hs_clkadj = 0;
+ unsigned int hs_wrlvl_start = 0;
+
+ ddr->timing_cfg_6 = (0
+ | ((hs_caslat & 0x1f) << 24)
+ | ((hs_wrlat & 0x1f) << 19)
+ | ((hs_wrrec & 0x1f) << 12)
+ | ((hs_clkadj & 0x1f) << 6)
+ | ((hs_wrlvl_start & 0x1f) << 0)
+ );
+ debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
+}
+
+static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr,
+ const common_timing_params_t *common_dimm)
+{
+ unsigned int txpr, tcksre, tcksrx;
+ unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
+
+ txpr = max(5, picos_to_mclk(common_dimm->trfc1_ps + 10000));
+ tcksre = max(5, picos_to_mclk(10000));
+ tcksrx = max(5, picos_to_mclk(10000));
+ par_lat = 0;
+ cs_to_cmd = 0;
+
+ if (txpr <= 200)
+ cke_rst = 0;
+ else if (txpr <= 256)
+ cke_rst = 1;
+ else if (txpr <= 512)
+ cke_rst = 2;
+ else
+ cke_rst = 3;
+
+ if (tcksre <= 19)
+ cksre = tcksre - 5;
+ else
+ cksre = 15;
+
+ if (tcksrx <= 19)
+ cksrx = tcksrx - 5;
+ else
+ cksrx = 15;
+
+ ddr->timing_cfg_7 = (0
+ | ((cke_rst & 0x3) << 28)
+ | ((cksre & 0xf) << 24)
+ | ((cksrx & 0xf) << 20)
+ | ((par_lat & 0xf) << 16)
+ | ((cs_to_cmd & 0xf) << 4)
+ );
+ debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
+}
+
+static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ unsigned int cas_latency)
+{
+ unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
+ unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
+ unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps);
+ unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
+ ((ddr->timing_cfg_2 & 0x00040000) >> 14);
+
+ rwt_bg = cas_latency + 2 + 4 - wr_lat;
+ if (rwt_bg < tccdl)
+ rwt_bg = tccdl - rwt_bg;
+ else
+ rwt_bg = 0;
+
+ wrt_bg = wr_lat + 4 + 1 - cas_latency;
+ if (wrt_bg < tccdl)
+ wrt_bg = tccdl - wrt_bg;
+ else
+ wrt_bg = 0;
+
+ if (popts->burst_length == DDR_BL8) {
+ rrt_bg = tccdl - 4;
+ wwt_bg = tccdl - 4;
+ } else {
+ rrt_bg = tccdl - 2;
+ wwt_bg = tccdl - 4;
+ }
+
+ acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
+ wrtord_bg = max(4, picos_to_mclk(7500));
+ pre_all_rec = 0;
+
+ ddr->timing_cfg_8 = (0
+ | ((rwt_bg & 0xf) << 28)
+ | ((wrt_bg & 0xf) << 24)
+ | ((rrt_bg & 0xf) << 20)
+ | ((wwt_bg & 0xf) << 16)
+ | ((acttoact_bg & 0xf) << 12)
+ | ((wrtord_bg & 0xf) << 8)
+ | ((pre_all_rec & 0x1f) << 0)
+ );
+
+ debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
+}
+
+static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
+{
+ ddr->timing_cfg_9 = 0;
+ debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
+}
+
+static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
+ const dimm_params_t *dimm_params)
+{
+ ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) |
+ ((dimm_params->dq_mapping[1] & 0x3F) << 20) |
+ ((dimm_params->dq_mapping[2] & 0x3F) << 14) |
+ ((dimm_params->dq_mapping[3] & 0x3F) << 8) |
+ ((dimm_params->dq_mapping[4] & 0x3F) << 2);
+
+ ddr->dq_map_1 = ((dimm_params->dq_mapping[5] & 0x3F) << 26) |
+ ((dimm_params->dq_mapping[6] & 0x3F) << 20) |
+ ((dimm_params->dq_mapping[7] & 0x3F) << 14) |
+ ((dimm_params->dq_mapping[10] & 0x3F) << 8) |
+ ((dimm_params->dq_mapping[11] & 0x3F) << 2);
+
+ ddr->dq_map_2 = ((dimm_params->dq_mapping[12] & 0x3F) << 26) |
+ ((dimm_params->dq_mapping[13] & 0x3F) << 20) |
+ ((dimm_params->dq_mapping[14] & 0x3F) << 14) |
+ ((dimm_params->dq_mapping[15] & 0x3F) << 8) |
+ ((dimm_params->dq_mapping[16] & 0x3F) << 2);
+
+ ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) |
+ ((dimm_params->dq_mapping[8] & 0x3F) << 20) |
+ ((dimm_params->dq_mapping[9] & 0x3F) << 14) |
+ dimm_params->dq_mapping_ors;
+
+ debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
+ debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
+ debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
+ debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
+}
+static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts)
+{
+ int rd_pre;
+
+ rd_pre = popts->quad_rank_present ? 1 : 0;
+
+ ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
+
+ debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
+}
+#endif /* CONFIG_SYS_FSL_DDR4 */
+
/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
{
unsigned int zqoper = 0;
/* Normal Operation Short Calibration Time (tZQCS) */
unsigned int zqcs = 0;
+#ifdef CONFIG_SYS_FSL_DDR4
+ unsigned int zqcs_init;
+#endif
if (zq_en) {
+#ifdef CONFIG_SYS_FSL_DDR4
+ zqinit = 10; /* 1024 clocks */
+ zqoper = 9; /* 512 clocks */
+ zqcs = 7; /* 128 clocks */
+ zqcs_init = 5; /* 1024 refresh sequences */
+#else
zqinit = 9; /* 512 clocks */
zqoper = 8; /* 256 clocks */
zqcs = 6; /* 64 clocks */
+#endif
}
ddr->ddr_zq_cntl = (0
| ((zqinit & 0xF) << 24)
| ((zqoper & 0xF) << 16)
| ((zqcs & 0xF) << 8)
+#ifdef CONFIG_SYS_FSL_DDR4
+ | ((zqcs_init & 0xF) << 0)
+#endif
);
debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
}
*/
cas_latency = (popts->cas_latency_override)
? popts->cas_latency_override_value
- : common_dimm->lowest_common_SPD_caslat;
+ : common_dimm->lowest_common_spd_caslat;
additive_latency = (popts->additive_latency_override)
? popts->additive_latency_override_value
set_ddr_sdram_mode(ddr, popts, common_dimm,
cas_latency, additive_latency, unq_mrs_en);
set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
+#ifdef CONFIG_SYS_FSL_DDR4
+ set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
+ set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en);
+#endif
set_ddr_sdram_interval(ddr, popts, common_dimm);
set_ddr_data_init(ddr);
set_ddr_sdram_clk_cntl(ddr, popts);
set_ddr_init_ext_addr(ddr);
set_timing_cfg_4(ddr, popts);
set_timing_cfg_5(ddr, cas_latency);
+#ifdef CONFIG_SYS_FSL_DDR4
+ set_ddr_sdram_cfg_3(ddr, popts);
+ set_timing_cfg_6(ddr);
+ set_timing_cfg_7(ddr, common_dimm);
+ set_timing_cfg_8(ddr, popts, common_dimm, cas_latency);
+ set_timing_cfg_9(ddr);
+ set_ddr_dq_mapping(ddr, dimm_params);
+#endif
set_ddr_zq_cntl(ddr, zq_en);
set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * calculate the organization and timing parameter
+ * from ddr3 spd, please refer to the spec
+ * JEDEC standard No.21-C 4_01_02_12R23A.pdf
+ *
+ *
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+
+#include <fsl_ddr.h>
+
+/*
+ * Calculate the Density of each Physical Rank.
+ * Returned size is in bytes.
+ *
+ * Total DIMM size =
+ * sdram capacity(bit) / 8 * primary bus width / sdram width
+ * * Logical Ranks per DIMM
+ *
+ * where: sdram capacity = spd byte4[3:0]
+ * primary bus width = spd byte13[2:0]
+ * sdram width = spd byte12[2:0]
+ * Logical Ranks per DIMM = spd byte12[5:3] for SDP, DDP, QDP
+ * spd byte12{5:3] * spd byte6[6:4] for 3DS
+ *
+ * To simplify each rank size = total DIMM size / Number of Package Ranks
+ * where Number of Package Ranks = spd byte12[5:3]
+ *
+ * SPD byte4 - sdram density and banks
+ * bit[3:0] size(bit) size(byte)
+ * 0000 256Mb 32MB
+ * 0001 512Mb 64MB
+ * 0010 1Gb 128MB
+ * 0011 2Gb 256MB
+ * 0100 4Gb 512MB
+ * 0101 8Gb 1GB
+ * 0110 16Gb 2GB
+ * 0111 32Gb 4GB
+ *
+ * SPD byte13 - module memory bus width
+ * bit[2:0] primary bus width
+ * 000 8bits
+ * 001 16bits
+ * 010 32bits
+ * 011 64bits
+ *
+ * SPD byte12 - module organization
+ * bit[2:0] sdram device width
+ * 000 4bits
+ * 001 8bits
+ * 010 16bits
+ * 011 32bits
+ *
+ * SPD byte12 - module organization
+ * bit[5:3] number of package ranks per DIMM
+ * 000 1
+ * 001 2
+ * 010 3
+ * 011 4
+ *
+ * SPD byte6 - SDRAM package type
+ * bit[6:4] Die count
+ * 000 1
+ * 001 2
+ * 010 3
+ * 011 4
+ * 100 5
+ * 101 6
+ * 110 7
+ * 111 8
+ *
+ * SPD byte6 - SRAM package type
+ * bit[1:0] Signal loading
+ * 00 Not specified
+ * 01 Multi load stack
+ * 10 Sigle load stack (3DS)
+ * 11 Reserved
+ */
+static unsigned long long
+compute_ranksize(const struct ddr4_spd_eeprom_s *spd)
+{
+ unsigned long long bsize;
+
+ int nbit_sdram_cap_bsize = 0;
+ int nbit_primary_bus_width = 0;
+ int nbit_sdram_width = 0;
+ int die_count = 0;
+ bool package_3ds;
+
+ if ((spd->density_banks & 0xf) <= 7)
+ nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
+ if ((spd->bus_width & 0x7) < 4)
+ nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
+ if ((spd->organization & 0x7) < 4)
+ nbit_sdram_width = (spd->organization & 0x7) + 2;
+ package_3ds = (spd->package_type & 0x3) == 0x2;
+ if (package_3ds)
+ die_count = (spd->package_type >> 4) & 0x7;
+
+ bsize = 1ULL << (nbit_sdram_cap_bsize - 3 +
+ nbit_primary_bus_width - nbit_sdram_width +
+ die_count);
+
+ debug("DDR: DDR III rank density = 0x%16llx\n", bsize);
+
+ return bsize;
+}
+
+#define spd_to_ps(mtb, ftb) \
+ (mtb * pdimm->mtb_ps + (ftb * pdimm->ftb_10th_ps) / 10)
+/*
+ * ddr_compute_dimm_parameters for DDR3 SPD
+ *
+ * Compute DIMM parameters based upon the SPD information in spd.
+ * Writes the results to the dimm_params_t structure pointed by pdimm.
+ *
+ */
+unsigned int
+ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd,
+ dimm_params_t *pdimm,
+ unsigned int dimm_number)
+{
+ unsigned int retval;
+ int i;
+
+ if (spd->mem_type) {
+ if (spd->mem_type != SPD_MEMTYPE_DDR4) {
+ printf("DIMM %u: is not a DDR4 SPD.\n", dimm_number);
+ return 1;
+ }
+ } else {
+ memset(pdimm, 0, sizeof(dimm_params_t));
+ return 1;
+ }
+
+ retval = ddr4_spd_check(spd);
+ if (retval) {
+ printf("DIMM %u: failed checksum\n", dimm_number);
+ return 2;
+ }
+
+ /*
+ * The part name in ASCII in the SPD EEPROM is not null terminated.
+ * Guarantee null termination here by presetting all bytes to 0
+ * and copying the part name in ASCII from the SPD onto it
+ */
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ if ((spd->info_size_crc & 0xF) > 2)
+ memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
+
+ /* DIMM organization parameters */
+ pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
+ pdimm->rank_density = compute_ranksize(spd);
+ pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
+ pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
+ if ((spd->bus_width >> 3) & 0x3)
+ pdimm->ec_sdram_width = 8;
+ else
+ pdimm->ec_sdram_width = 0;
+ pdimm->data_width = pdimm->primary_sdram_width
+ + pdimm->ec_sdram_width;
+ pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
+
+ /* These are the types defined by the JEDEC DDR3 SPD spec */
+ pdimm->mirrored_dimm = 0;
+ pdimm->registered_dimm = 0;
+ switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
+ case DDR3_SPD_MODULETYPE_RDIMM:
+ /* Registered/buffered DIMMs */
+ pdimm->registered_dimm = 1;
+ break;
+
+ case DDR3_SPD_MODULETYPE_UDIMM:
+ case DDR3_SPD_MODULETYPE_SO_DIMM:
+ /* Unbuffered DIMMs */
+ if (spd->mod_section.unbuffered.addr_mapping & 0x1)
+ pdimm->mirrored_dimm = 1;
+ break;
+
+ default:
+ printf("unknown module_type 0x%02X\n", spd->module_type);
+ return 1;
+ }
+
+ /* SDRAM device parameters */
+ pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
+ pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
+ pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3;
+ pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3;
+
+ /*
+ * The SPD spec has not the ECC bit,
+ * We consider the DIMM as ECC capability
+ * when the extension bus exist
+ */
+ if (pdimm->ec_sdram_width)
+ pdimm->edc_config = 0x02;
+ else
+ pdimm->edc_config = 0x00;
+
+ /*
+ * The SPD spec has not the burst length byte
+ * but DDR4 spec has nature BL8 and BC4,
+ * BL8 -bit3, BC4 -bit2
+ */
+ pdimm->burst_lengths_bitmask = 0x0c;
+ pdimm->row_density = __ilog2(pdimm->rank_density);
+
+ /* MTB - medium timebase
+ * The MTB in the SPD spec is 125ps,
+ *
+ * FTB - fine timebase
+ * use 1/10th of ps as our unit to avoid floating point
+ * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
+ */
+ if ((spd->timebases & 0xf) == 0x0) {
+ pdimm->mtb_ps = 125;
+ pdimm->ftb_10th_ps = 10;
+
+ } else {
+ printf("Unknown Timebases\n");
+ }
+
+ /* sdram minimum cycle time */
+ pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min);
+
+ /* sdram max cycle time */
+ pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max);
+
+ /*
+ * CAS latency supported
+ * bit0 - CL7
+ * bit4 - CL11
+ * bit8 - CL15
+ * bit12- CL19
+ * bit16- CL23
+ */
+ pdimm->caslat_x = (spd->caslat_b1 << 7) |
+ (spd->caslat_b2 << 15) |
+ (spd->caslat_b3 << 23);
+
+ BUG_ON(spd->caslat_b4 != 0);
+
+ /*
+ * min CAS latency time
+ */
+ pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min);
+
+ /*
+ * min RAS to CAS delay time
+ */
+ pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min);
+
+ /*
+ * Min Row Precharge Delay Time
+ */
+ pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min);
+
+ /* min active to precharge delay time */
+ pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) +
+ spd->tras_min_lsb) * pdimm->mtb_ps;
+
+ /* min active to actice/refresh delay time */
+ pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) +
+ spd->trc_min_lsb), spd->fine_trc_min);
+ /* Min Refresh Recovery Delay Time */
+ pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) *
+ pdimm->mtb_ps;
+ pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) *
+ pdimm->mtb_ps;
+ pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) *
+ pdimm->mtb_ps;
+ /* min four active window delay time */
+ pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) *
+ pdimm->mtb_ps;
+
+ /* min row active to row active delay time, different bank group */
+ pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min);
+ /* min row active to row active delay time, same bank group */
+ pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min);
+ /* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */
+ pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min);
+
+ /*
+ * Average periodic refresh interval
+ * tREFI = 7.8 us at normal temperature range
+ */
+ pdimm->refresh_rate_ps = 7800000;
+
+ for (i = 0; i < 18; i++)
+ pdimm->dq_mapping[i] = spd->mapping[i];
+
+ pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0;
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/processor.h>
+#include <fsl_ddr.h>
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+/*
+ * regs has the to-be-set values for DDR controller registers
+ * ctrl_num is the DDR controller number
+ * step: 0 goes through the initialization in one pass
+ * 1 sets registers and returns before enabling controller
+ * 2 resumes from step 1 and continues to initialize
+ * Dividing the initialization to two steps to deassert DDR reset signal
+ * to comply with JEDEC specs for RDIMMs.
+ */
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+ unsigned int ctrl_num, int step)
+{
+ unsigned int i, bus_width;
+ struct ccsr_ddr __iomem *ddr;
+ u32 temp_sdram_cfg;
+ u32 total_gb_size_per_controller;
+ int timeout;
+
+ switch (ctrl_num) {
+ case 0:
+ ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ break;
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+ case 1:
+ ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+ case 2:
+ ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+ case 3:
+ ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+ break;
+#endif
+ default:
+ printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
+ return;
+ }
+
+ if (step == 2)
+ goto step2;
+
+ if (regs->ddr_eor)
+ ddr_out32(&ddr->eor, regs->ddr_eor);
+
+ ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (i == 0) {
+ ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
+ ddr_out32(&ddr->cs0_config, regs->cs[i].config);
+ ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
+
+ } else if (i == 1) {
+ ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
+ ddr_out32(&ddr->cs1_config, regs->cs[i].config);
+ ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
+
+ } else if (i == 2) {
+ ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
+ ddr_out32(&ddr->cs2_config, regs->cs[i].config);
+ ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
+
+ } else if (i == 3) {
+ ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
+ ddr_out32(&ddr->cs3_config, regs->cs[i].config);
+ ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
+ }
+ }
+
+ ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
+ ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
+ ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+ ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+ ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
+ ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
+ ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
+ ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
+ ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
+ ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
+ ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
+ ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
+ ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
+ ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
+ ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
+ ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+ ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
+ ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+ ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
+ ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
+ ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
+ ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
+ ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
+ ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
+ ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
+ ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
+ ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
+ ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
+ ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
+ ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
+ ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
+ ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
+ ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
+ ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
+ ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+ ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
+ ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
+ ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+ ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+#ifndef CONFIG_SYS_FSL_DDR_EMU
+ /*
+ * Skip these two registers if running on emulator
+ * because emulator doesn't have skew between bytes.
+ */
+
+ if (regs->ddr_wrlvl_cntl_2)
+ ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
+ if (regs->ddr_wrlvl_cntl_3)
+ ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
+#endif
+
+ ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
+ ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
+ ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
+ ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
+ ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
+ ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
+ ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
+ ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
+ ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+ ddr_out32(&ddr->err_disable, regs->err_disable);
+ ddr_out32(&ddr->err_int_en, regs->err_int_en);
+ for (i = 0; i < 32; i++) {
+ if (regs->debug[i]) {
+ debug("Write to debug_%d as %08x\n",
+ i+1, regs->debug[i]);
+ ddr_out32(&ddr->debug[i], regs->debug[i]);
+ }
+ }
+
+ /*
+ * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
+ * deasserted. Clocks start when any chip select is enabled and clock
+ * control register is set. Because all DDR components are connected to
+ * one reset signal, this needs to be done in two steps. Step 1 is to
+ * get the clocks started. Step 2 resumes after reset signal is
+ * deasserted.
+ */
+ if (step == 1) {
+ udelay(200);
+ return;
+ }
+
+step2:
+ /* Set, but do not enable the memory */
+ temp_sdram_cfg = regs->ddr_sdram_cfg;
+ temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
+ ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
+
+ /*
+ * 500 painful micro-seconds must elapse between
+ * the DDR clock setup and the DDR config enable.
+ * DDR2 need 200 us, and DDR3 need 500 us from spec,
+ * we choose the max, that is 500 us for all of case.
+ */
+ udelay(500);
+ asm volatile("sync;isync");
+
+ /* Let the controller go */
+ temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
+ ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
+ asm volatile("sync;isync");
+
+ total_gb_size_per_controller = 0;
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (!(regs->cs[i].config & 0x80000000))
+ continue;
+ total_gb_size_per_controller += 1 << (
+ ((regs->cs[i].config >> 14) & 0x3) + 2 +
+ ((regs->cs[i].config >> 8) & 0x7) + 12 +
+ ((regs->cs[i].config >> 4) & 0x3) + 0 +
+ ((regs->cs[i].config >> 0) & 0x7) + 8 +
+ 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
+ 26); /* minus 26 (count of 64M) */
+ }
+ if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */
+ total_gb_size_per_controller *= 3;
+ else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
+ total_gb_size_per_controller <<= 1;
+ /*
+ * total memory / bus width = transactions needed
+ * transactions needed / data rate = seconds
+ * to add plenty of buffer, double the time
+ * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
+ * Let's wait for 800ms
+ */
+ bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+ >> SDRAM_CFG_DBW_SHIFT);
+ timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
+ (get_ddr_freq(0) >> 20)) << 2;
+ total_gb_size_per_controller >>= 4; /* shift down to gb size */
+ debug("total %d GB\n", total_gb_size_per_controller);
+ debug("Need to wait up to %d * 10ms\n", timeout);
+
+ /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
+ while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+ (timeout >= 0)) {
+ udelay(10000); /* throttle polling rate */
+ timeout--;
+ }
+
+ if (timeout <= 0)
+ printf("Waiting for D_INIT timeout. Memory may not work.\n");
+
+}
/*
- * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * Copyright 2010-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
static const struct options_string options[] = {
COMMON_TIMING(tckmin_x_ps),
COMMON_TIMING(tckmax_ps),
- COMMON_TIMING(tckmax_max_ps),
+ COMMON_TIMING(taamin_ps),
COMMON_TIMING(trcd_ps),
COMMON_TIMING(trp_ps),
COMMON_TIMING(tras_ps),
- COMMON_TIMING(twr_ps),
+
+#ifdef CONFIG_SYS_FSL_DDR4
+ COMMON_TIMING(trfc1_ps),
+ COMMON_TIMING(trfc2_ps),
+ COMMON_TIMING(trfc4_ps),
+ COMMON_TIMING(trrds_ps),
+ COMMON_TIMING(trrdl_ps),
+ COMMON_TIMING(tccdl_ps),
+#else
COMMON_TIMING(twtr_ps),
COMMON_TIMING(trfc_ps),
COMMON_TIMING(trrd_ps),
+ COMMON_TIMING(trtp_ps),
+#endif
+ COMMON_TIMING(twr_ps),
COMMON_TIMING(trc_ps),
COMMON_TIMING(refresh_rate_ps),
+ COMMON_TIMING(extended_op_srt),
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
COMMON_TIMING(tis_ps),
COMMON_TIMING(tih_ps),
COMMON_TIMING(tds_ps),
COMMON_TIMING(tdh_ps),
- COMMON_TIMING(trtp_ps),
COMMON_TIMING(tdqsq_max_ps),
COMMON_TIMING(tqhs_ps),
+#endif
COMMON_TIMING(ndimms_present),
- COMMON_TIMING(lowest_common_SPD_caslat),
+ COMMON_TIMING(lowest_common_spd_caslat),
COMMON_TIMING(highest_common_derated_caslat),
COMMON_TIMING(additive_latency),
COMMON_TIMING(all_dimms_burst_lengths_bitmask),
DIMM_PARM(n_row_addr),
DIMM_PARM(n_col_addr),
DIMM_PARM(edc_config),
+#ifdef CONFIG_SYS_FSL_DDR4
+ DIMM_PARM(bank_addr_bits),
+ DIMM_PARM(bank_group_bits),
+#else
DIMM_PARM(n_banks_per_sdram_device),
+#endif
DIMM_PARM(burst_lengths_bitmask),
DIMM_PARM(row_density),
DIMM_PARM(trcd_ps),
DIMM_PARM(trp_ps),
DIMM_PARM(tras_ps),
+#ifdef CONFIG_SYS_FSL_DDR4
+ DIMM_PARM(trfc1_ps),
+ DIMM_PARM(trfc2_ps),
+ DIMM_PARM(trfc4_ps),
+ DIMM_PARM(trrds_ps),
+ DIMM_PARM(trrdl_ps),
+ DIMM_PARM(tccdl_ps),
+#else
DIMM_PARM(twr_ps),
DIMM_PARM(twtr_ps),
DIMM_PARM(trfc_ps),
DIMM_PARM(trrd_ps),
+ DIMM_PARM(trtp_ps),
+#endif
DIMM_PARM(trc_ps),
DIMM_PARM(refresh_rate_ps),
+ DIMM_PARM(extended_op_srt),
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
DIMM_PARM(tis_ps),
DIMM_PARM(tih_ps),
DIMM_PARM(tds_ps),
DIMM_PARM(tdh_ps),
- DIMM_PARM(trtp_ps),
DIMM_PARM(tdqsq_max_ps),
DIMM_PARM(tqhs_ps),
+#endif
DIMM_PARM(rank_density),
DIMM_PARM(capacity),
DIMM_PARM(n_row_addr),
DIMM_PARM(n_col_addr),
DIMM_PARM(edc_config),
+#ifdef CONFIG_SYS_FSL_DDR4
+ DIMM_PARM(bank_addr_bits),
+ DIMM_PARM(bank_group_bits),
+#else
DIMM_PARM(n_banks_per_sdram_device),
+#endif
DIMM_PARM(tckmin_x_ps),
DIMM_PARM(tckmin_x_minus_1_ps),
DIMM_PARM(trcd_ps),
DIMM_PARM(trp_ps),
DIMM_PARM(tras_ps),
+#ifdef CONFIG_SYS_FSL_DDR4
+ DIMM_PARM(trfc1_ps),
+ DIMM_PARM(trfc2_ps),
+ DIMM_PARM(trfc4_ps),
+ DIMM_PARM(trrds_ps),
+ DIMM_PARM(trrdl_ps),
+ DIMM_PARM(tccdl_ps),
+#else
DIMM_PARM(twr_ps),
DIMM_PARM(twtr_ps),
DIMM_PARM(trfc_ps),
DIMM_PARM(trrd_ps),
+ DIMM_PARM(trtp_ps),
+#endif
DIMM_PARM(trc_ps),
DIMM_PARM(refresh_rate_ps),
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
DIMM_PARM(tis_ps),
DIMM_PARM(tih_ps),
DIMM_PARM(tds_ps),
DIMM_PARM(tdh_ps),
- DIMM_PARM(trtp_ps),
DIMM_PARM(tdqsq_max_ps),
DIMM_PARM(tqhs_ps),
+#endif
};
static const unsigned int n_opts = ARRAY_SIZE(options);
const common_timing_params_t *plcd_dimm_params)
{
static const struct options_string options[] = {
- COMMON_TIMING(tckmax_max_ps),
+ COMMON_TIMING(taamin_ps),
COMMON_TIMING(trcd_ps),
COMMON_TIMING(trp_ps),
COMMON_TIMING(tras_ps),
- COMMON_TIMING(twr_ps),
+#ifdef CONFIG_SYS_FSL_DDR4
+ COMMON_TIMING(trfc1_ps),
+ COMMON_TIMING(trfc2_ps),
+ COMMON_TIMING(trfc4_ps),
+ COMMON_TIMING(trrds_ps),
+ COMMON_TIMING(trrdl_ps),
+ COMMON_TIMING(tccdl_ps),
+#else
COMMON_TIMING(twtr_ps),
COMMON_TIMING(trfc_ps),
COMMON_TIMING(trrd_ps),
+ COMMON_TIMING(trtp_ps),
+#endif
+ COMMON_TIMING(twr_ps),
COMMON_TIMING(trc_ps),
COMMON_TIMING(refresh_rate_ps),
+ COMMON_TIMING(extended_op_srt),
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
COMMON_TIMING(tis_ps),
+ COMMON_TIMING(tih_ps),
COMMON_TIMING(tds_ps),
COMMON_TIMING(tdh_ps),
- COMMON_TIMING(trtp_ps),
COMMON_TIMING(tdqsq_max_ps),
COMMON_TIMING(tqhs_ps),
- COMMON_TIMING(lowest_common_SPD_caslat),
+#endif
+ COMMON_TIMING(lowest_common_spd_caslat),
COMMON_TIMING(highest_common_derated_caslat),
COMMON_TIMING(additive_latency),
COMMON_TIMING(ndimms_present),
CTRL_OPTIONS(tfaw_window_four_activates_ps),
CTRL_OPTIONS(trwt_override),
CTRL_OPTIONS(trwt),
+ CTRL_OPTIONS(rtt_override),
+ CTRL_OPTIONS(rtt_override_value),
+ CTRL_OPTIONS(rtt_wr_override_value),
};
static const unsigned int n_opts = ARRAY_SIZE(options);
CFG_REGS(timing_cfg_2),
CFG_REGS(ddr_sdram_cfg),
CFG_REGS(ddr_sdram_cfg_2),
+ CFG_REGS(ddr_sdram_cfg_3),
CFG_REGS(ddr_sdram_mode),
CFG_REGS(ddr_sdram_mode_2),
CFG_REGS(ddr_sdram_mode_3),
CFG_REGS(ddr_sdram_mode_6),
CFG_REGS(ddr_sdram_mode_7),
CFG_REGS(ddr_sdram_mode_8),
+#ifdef CONFIG_SYS_FSL_DDR4
+ CFG_REGS(ddr_sdram_mode_9),
+ CFG_REGS(ddr_sdram_mode_10),
+ CFG_REGS(ddr_sdram_mode_11),
+ CFG_REGS(ddr_sdram_mode_12),
+ CFG_REGS(ddr_sdram_mode_13),
+ CFG_REGS(ddr_sdram_mode_14),
+ CFG_REGS(ddr_sdram_mode_15),
+ CFG_REGS(ddr_sdram_mode_16),
+#endif
CFG_REGS(ddr_sdram_interval),
CFG_REGS(ddr_data_init),
CFG_REGS(ddr_sdram_clk_cntl),
CFG_REGS(ddr_init_ext_addr),
CFG_REGS(timing_cfg_4),
CFG_REGS(timing_cfg_5),
+#ifdef CONFIG_SYS_FSL_DDR4
+ CFG_REGS(timing_cfg_6),
+ CFG_REGS(timing_cfg_7),
+ CFG_REGS(timing_cfg_8),
+ CFG_REGS(timing_cfg_9),
+#endif
CFG_REGS(ddr_zq_cntl),
CFG_REGS(ddr_wrlvl_cntl),
CFG_REGS(ddr_wrlvl_cntl_2),
CFG_REGS(ddr_sdram_rcw_2),
CFG_REGS(ddr_cdr1),
CFG_REGS(ddr_cdr2),
+ CFG_REGS(dq_map_0),
+ CFG_REGS(dq_map_1),
+ CFG_REGS(dq_map_2),
+ CFG_REGS(dq_map_3),
CFG_REGS(err_disable),
CFG_REGS(err_int_en),
CFG_REGS(ddr_eor),
CFG_REGS(timing_cfg_2),
CFG_REGS(ddr_sdram_cfg),
CFG_REGS(ddr_sdram_cfg_2),
+ CFG_REGS(ddr_sdram_cfg_3),
CFG_REGS(ddr_sdram_mode),
CFG_REGS(ddr_sdram_mode_2),
CFG_REGS(ddr_sdram_mode_3),
CFG_REGS(ddr_sdram_mode_6),
CFG_REGS(ddr_sdram_mode_7),
CFG_REGS(ddr_sdram_mode_8),
+#ifdef CONFIG_SYS_FSL_DDR4
+ CFG_REGS(ddr_sdram_mode_9),
+ CFG_REGS(ddr_sdram_mode_10),
+ CFG_REGS(ddr_sdram_mode_11),
+ CFG_REGS(ddr_sdram_mode_12),
+ CFG_REGS(ddr_sdram_mode_13),
+ CFG_REGS(ddr_sdram_mode_14),
+ CFG_REGS(ddr_sdram_mode_15),
+ CFG_REGS(ddr_sdram_mode_16),
+#endif
CFG_REGS(ddr_sdram_interval),
CFG_REGS(ddr_data_init),
CFG_REGS(ddr_sdram_clk_cntl),
CFG_REGS(ddr_init_ext_addr),
CFG_REGS(timing_cfg_4),
CFG_REGS(timing_cfg_5),
+#ifdef CONFIG_SYS_FSL_DDR4
+ CFG_REGS(timing_cfg_6),
+ CFG_REGS(timing_cfg_7),
+ CFG_REGS(timing_cfg_8),
+ CFG_REGS(timing_cfg_9),
+#endif
CFG_REGS(ddr_zq_cntl),
CFG_REGS(ddr_wrlvl_cntl),
CFG_REGS(ddr_wrlvl_cntl_2),
CFG_REGS(ddr_sdram_rcw_2),
CFG_REGS(ddr_cdr1),
CFG_REGS(ddr_cdr2),
+ CFG_REGS(dq_map_0),
+ CFG_REGS(dq_map_1),
+ CFG_REGS(dq_map_2),
+ CFG_REGS(dq_map_3),
CFG_REGS(err_disable),
CFG_REGS(err_int_en),
CFG_REGS(ddr_sdram_rcw_2),
CTRL_OPTIONS(tfaw_window_four_activates_ps),
CTRL_OPTIONS(trwt_override),
CTRL_OPTIONS(trwt),
+ CTRL_OPTIONS(rtt_override),
+ CTRL_OPTIONS(rtt_override_value),
+ CTRL_OPTIONS(rtt_wr_override_value),
};
static const unsigned int n_opts = ARRAY_SIZE(options);
}
#endif
+#ifdef CONFIG_SYS_FSL_DDR4
+void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd)
+{
+ unsigned int i;
+
+ /* General Section: Bytes 0-127 */
+
+#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y);
+#define PRINT_NNXXS(n0, n1, x0, x1, s) \
+ printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
+
+ PRINT_NXS(0, spd->info_size_crc,
+ "info_size_crc bytes written into serial memory, CRC coverage");
+ PRINT_NXS(1, spd->spd_rev,
+ "spd_rev SPD Revision");
+ PRINT_NXS(2, spd->mem_type,
+ "mem_type Key Byte / DRAM Device Type");
+ PRINT_NXS(3, spd->module_type,
+ "module_type Key Byte / Module Type");
+ PRINT_NXS(4, spd->density_banks,
+ "density_banks SDRAM Density and Banks");
+ PRINT_NXS(5, spd->addressing,
+ "addressing SDRAM Addressing");
+ PRINT_NXS(6, spd->package_type,
+ "package_type Package type");
+ PRINT_NXS(7, spd->opt_feature,
+ "opt_feature Optional features");
+ PRINT_NXS(8, spd->thermal_ref,
+ "thermal_ref Thermal and Refresh options");
+ PRINT_NXS(9, spd->oth_opt_features,
+ "oth_opt_features Other SDRAM optional features");
+ PRINT_NXS(10, spd->res_10,
+ "res_10 Reserved");
+ PRINT_NXS(11, spd->module_vdd,
+ "module_vdd Module Nominal Voltage, VDD");
+ PRINT_NXS(12, spd->organization,
+ "organization Module Organization");
+ PRINT_NXS(13, spd->bus_width,
+ "bus_width Module Memory Bus Width");
+ PRINT_NXS(14, spd->therm_sensor,
+ "therm_sensor Module Thermal Sensor");
+ PRINT_NXS(15, spd->ext_type,
+ "ext_type Extended module type");
+ PRINT_NXS(16, spd->res_16,
+ "res_16 Reserved");
+ PRINT_NXS(17, spd->timebases,
+ "timebases MTb and FTB");
+ PRINT_NXS(18, spd->tck_min,
+ "tck_min tCKAVGmin");
+ PRINT_NXS(19, spd->tck_max,
+ "tck_max TCKAVGmax");
+ PRINT_NXS(20, spd->caslat_b1,
+ "caslat_b1 CAS latencies, 1st byte");
+ PRINT_NXS(21, spd->caslat_b2,
+ "caslat_b2 CAS latencies, 2nd byte");
+ PRINT_NXS(22, spd->caslat_b3,
+ "caslat_b3 CAS latencies, 3rd byte ");
+ PRINT_NXS(23, spd->caslat_b4,
+ "caslat_b4 CAS latencies, 4th byte");
+ PRINT_NXS(24, spd->taa_min,
+ "taa_min Min CAS Latency Time");
+ PRINT_NXS(25, spd->trcd_min,
+ "trcd_min Min RAS# to CAS# Delay Time");
+ PRINT_NXS(26, spd->trp_min,
+ "trp_min Min Row Precharge Delay Time");
+ PRINT_NXS(27, spd->tras_trc_ext,
+ "tras_trc_ext Upper Nibbles for tRAS and tRC");
+ PRINT_NXS(28, spd->tras_min_lsb,
+ "tras_min_lsb tRASmin, lsb");
+ PRINT_NXS(29, spd->trc_min_lsb,
+ "trc_min_lsb tRCmin, lsb");
+ PRINT_NXS(30, spd->trfc1_min_lsb,
+ "trfc1_min_lsb Min Refresh Recovery Delay Time, LSB");
+ PRINT_NXS(31, spd->trfc1_min_msb,
+ "trfc1_min_msb Min Refresh Recovery Delay Time, MSB ");
+ PRINT_NXS(32, spd->trfc2_min_lsb,
+ "trfc2_min_lsb Min Refresh Recovery Delay Time, LSB");
+ PRINT_NXS(33, spd->trfc2_min_msb,
+ "trfc2_min_msb Min Refresh Recovery Delay Time, MSB");
+ PRINT_NXS(34, spd->trfc4_min_lsb,
+ "trfc4_min_lsb Min Refresh Recovery Delay Time, LSB");
+ PRINT_NXS(35, spd->trfc4_min_msb,
+ "trfc4_min_msb Min Refresh Recovery Delay Time, MSB");
+ PRINT_NXS(36, spd->tfaw_msb,
+ "tfaw_msb Upper Nibble for tFAW");
+ PRINT_NXS(37, spd->tfaw_min,
+ "tfaw_min tFAW, lsb");
+ PRINT_NXS(38, spd->trrds_min,
+ "trrds_min tRRD_Smin, MTB");
+ PRINT_NXS(39, spd->trrdl_min,
+ "trrdl_min tRRD_Lmin, MTB");
+ PRINT_NXS(40, spd->tccdl_min,
+ "tccdl_min tCCS_Lmin, MTB");
+
+ printf("%-3d-%3d: ", 41, 59); /* Reserved, General Section */
+ for (i = 41; i <= 59; i++)
+ printf("%02x ", spd->res_41[i - 41]);
+
+ puts("\n");
+ printf("%-3d-%3d: ", 60, 77);
+ for (i = 60; i <= 77; i++)
+ printf("%02x ", spd->mapping[i - 60]);
+ puts(" mapping[] Connector to SDRAM bit map\n");
+
+ PRINT_NXS(117, spd->fine_tccdl_min,
+ "fine_tccdl_min Fine offset for tCCD_Lmin");
+ PRINT_NXS(118, spd->fine_trrdl_min,
+ "fine_trrdl_min Fine offset for tRRD_Lmin");
+ PRINT_NXS(119, spd->fine_trrds_min,
+ "fine_trrds_min Fine offset for tRRD_Smin");
+ PRINT_NXS(120, spd->fine_trc_min,
+ "fine_trc_min Fine offset for tRCmin");
+ PRINT_NXS(121, spd->fine_trp_min,
+ "fine_trp_min Fine offset for tRPmin");
+ PRINT_NXS(122, spd->fine_trcd_min,
+ "fine_trcd_min Fine offset for tRCDmin");
+ PRINT_NXS(123, spd->fine_taa_min,
+ "fine_taa_min Fine offset for tAAmin");
+ PRINT_NXS(124, spd->fine_tck_max,
+ "fine_tck_max Fine offset for tCKAVGmax");
+ PRINT_NXS(125, spd->fine_tck_min,
+ "fine_tck_min Fine offset for tCKAVGmin");
+
+ /* CRC: Bytes 126-127 */
+ PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC");
+
+ switch (spd->module_type) {
+ case 0x02: /* UDIMM */
+ case 0x03: /* SO-DIMM */
+ PRINT_NXS(128, spd->mod_section.unbuffered.mod_height,
+ "mod_height (Unbuffered) Module Nominal Height");
+ PRINT_NXS(129, spd->mod_section.unbuffered.mod_thickness,
+ "mod_thickness (Unbuffered) Module Maximum Thickness");
+ PRINT_NXS(130, spd->mod_section.unbuffered.ref_raw_card,
+ "ref_raw_card (Unbuffered) Reference Raw Card Used");
+ PRINT_NXS(131, spd->mod_section.unbuffered.addr_mapping,
+ "addr_mapping (Unbuffered) Address mapping from Edge Connector to DRAM");
+ PRINT_NNXXS(254, 255, spd->mod_section.unbuffered.crc[0],
+ spd->mod_section.unbuffered.crc[1], " Module CRC");
+ break;
+ case 0x01: /* RDIMM */
+ PRINT_NXS(128, spd->mod_section.registered.mod_height,
+ "mod_height (Registered) Module Nominal Height");
+ PRINT_NXS(129, spd->mod_section.registered.mod_thickness,
+ "mod_thickness (Registered) Module Maximum Thickness");
+ PRINT_NXS(130, spd->mod_section.registered.ref_raw_card,
+ "ref_raw_card (Registered) Reference Raw Card Used");
+ PRINT_NXS(131, spd->mod_section.registered.modu_attr,
+ "modu_attr (Registered) DIMM Module Attributes");
+ PRINT_NXS(132, spd->mod_section.registered.thermal,
+ "thermal (Registered) Thermal Heat Spreader Solution");
+ PRINT_NXS(133, spd->mod_section.registered.reg_id_lo,
+ "reg_id_lo (Registered) Register Manufacturer ID Code, LSB");
+ PRINT_NXS(134, spd->mod_section.registered.reg_id_hi,
+ "reg_id_hi (Registered) Register Manufacturer ID Code, MSB");
+ PRINT_NXS(135, spd->mod_section.registered.reg_rev,
+ "reg_rev (Registered) Register Revision Number");
+ PRINT_NXS(136, spd->mod_section.registered.reg_map,
+ "reg_map (Registered) Address mapping");
+ PRINT_NNXXS(254, 255, spd->mod_section.registered.crc[0],
+ spd->mod_section.registered.crc[1], " Module CRC");
+ break;
+ case 0x04: /* LRDIMM */
+ PRINT_NXS(128, spd->mod_section.loadreduced.mod_height,
+ "mod_height (Loadreduced) Module Nominal Height");
+ PRINT_NXS(129, spd->mod_section.loadreduced.mod_thickness,
+ "mod_thickness (Loadreduced) Module Maximum Thickness");
+ PRINT_NXS(130, spd->mod_section.loadreduced.ref_raw_card,
+ "ref_raw_card (Loadreduced) Reference Raw Card Used");
+ PRINT_NXS(131, spd->mod_section.loadreduced.modu_attr,
+ "modu_attr (Loadreduced) DIMM Module Attributes");
+ PRINT_NXS(132, spd->mod_section.loadreduced.thermal,
+ "thermal (Loadreduced) Thermal Heat Spreader Solution");
+ PRINT_NXS(133, spd->mod_section.loadreduced.reg_id_lo,
+ "reg_id_lo (Loadreduced) Register Manufacturer ID Code, LSB");
+ PRINT_NXS(134, spd->mod_section.loadreduced.reg_id_hi,
+ "reg_id_hi (Loadreduced) Register Manufacturer ID Code, MSB");
+ PRINT_NXS(135, spd->mod_section.loadreduced.reg_rev,
+ "reg_rev (Loadreduced) Register Revision Number");
+ PRINT_NXS(136, spd->mod_section.loadreduced.reg_map,
+ "reg_map (Loadreduced) Address mapping");
+ PRINT_NXS(137, spd->mod_section.loadreduced.reg_drv,
+ "reg_drv (Loadreduced) Reg output drive strength");
+ PRINT_NXS(138, spd->mod_section.loadreduced.reg_drv_ck,
+ "reg_drv_ck (Loadreduced) Reg output drive strength for CK");
+ PRINT_NXS(139, spd->mod_section.loadreduced.data_buf_rev,
+ "data_buf_rev (Loadreduced) Data Buffer Revision Numbe");
+ PRINT_NXS(140, spd->mod_section.loadreduced.vrefqe_r0,
+ "vrefqe_r0 (Loadreduced) DRAM VrefDQ for Package Rank 0");
+ PRINT_NXS(141, spd->mod_section.loadreduced.vrefqe_r1,
+ "vrefqe_r1 (Loadreduced) DRAM VrefDQ for Package Rank 1");
+ PRINT_NXS(142, spd->mod_section.loadreduced.vrefqe_r2,
+ "vrefqe_r2 (Loadreduced) DRAM VrefDQ for Package Rank 2");
+ PRINT_NXS(143, spd->mod_section.loadreduced.vrefqe_r3,
+ "vrefqe_r3 (Loadreduced) DRAM VrefDQ for Package Rank 3");
+ PRINT_NXS(144, spd->mod_section.loadreduced.data_intf,
+ "data_intf (Loadreduced) Data Buffer VrefDQ for DRAM Interface");
+ PRINT_NXS(145, spd->mod_section.loadreduced.data_drv_1866,
+ "data_drv_1866 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
+ PRINT_NXS(146, spd->mod_section.loadreduced.data_drv_2400,
+ "data_drv_2400 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
+ PRINT_NXS(147, spd->mod_section.loadreduced.data_drv_3200,
+ "data_drv_3200 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
+ PRINT_NXS(148, spd->mod_section.loadreduced.dram_drv,
+ "dram_drv (Loadreduced) DRAM Drive Strength");
+ PRINT_NXS(149, spd->mod_section.loadreduced.dram_odt_1866,
+ "dram_odt_1866 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
+ PRINT_NXS(150, spd->mod_section.loadreduced.dram_odt_2400,
+ "dram_odt_2400 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
+ PRINT_NXS(151, spd->mod_section.loadreduced.dram_odt_3200,
+ "dram_odt_3200 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
+ PRINT_NXS(152, spd->mod_section.loadreduced.dram_odt_park_1866,
+ "dram_odt_park_1866 (Loadreduced) DRAM ODT (RTT_PARK)");
+ PRINT_NXS(153, spd->mod_section.loadreduced.dram_odt_park_2400,
+ "dram_odt_park_2400 (Loadreduced) DRAM ODT (RTT_PARK)");
+ PRINT_NXS(154, spd->mod_section.loadreduced.dram_odt_park_3200,
+ "dram_odt_park_3200 (Loadreduced) DRAM ODT (RTT_PARK)");
+ PRINT_NNXXS(254, 255, spd->mod_section.loadreduced.crc[0],
+ spd->mod_section.loadreduced.crc[1],
+ " Module CRC");
+ break;
+ default:
+ /* Module-specific Section, Unsupported Module Type */
+ printf("%-3d-%3d: ", 128, 255);
+
+ for (i = 128; i <= 255; i++)
+ printf("%02x", spd->mod_section.uc[i - 60]);
+
+ break;
+ }
+
+ /* Unique Module ID: Bytes 320-383 */
+ PRINT_NXS(320, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
+ PRINT_NXS(321, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
+ PRINT_NXS(322, spd->mloc, "Mfg Location");
+ PRINT_NNXXS(323, 324, spd->mdate[0], spd->mdate[1], "Mfg Date");
+
+ printf("%-3d-%3d: ", 325, 328);
+
+ for (i = 325; i <= 328; i++)
+ printf("%02x ", spd->sernum[i - 325]);
+ printf(" Module Serial Number\n");
+
+ printf("%-3d-%3d: ", 329, 348);
+ for (i = 329; i <= 348; i++)
+ printf("%02x ", spd->mpart[i - 329]);
+ printf(" Mfg's Module Part Number\n");
+
+ PRINT_NXS(349, spd->mrev, "Module Revision code");
+ PRINT_NXS(350, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
+ PRINT_NXS(351, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
+ PRINT_NXS(352, spd->stepping, "DRAM stepping");
+
+ printf("%-3d-%3d: ", 353, 381);
+ for (i = 353; i <= 381; i++)
+ printf("%02x ", spd->msd[i - 353]);
+ printf(" Mfg's Specific Data\n");
+}
+#endif
+
static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
{
#if defined(CONFIG_SYS_FSL_DDR1)
ddr2_spd_dump(spd);
#elif defined(CONFIG_SYS_FSL_DDR3)
ddr3_spd_dump(spd);
+#elif defined(CONFIG_SYS_FSL_DDR4)
+ ddr4_spd_dump(spd);
#endif
}
/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
#include <fsl_ddr.h>
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
static unsigned int
-compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
- common_timing_params_t *outpdimm,
- unsigned int number_of_dimms)
+compute_cas_latency(const dimm_params_t *dimm_params,
+ common_timing_params_t *outpdimm,
+ unsigned int number_of_dimms)
{
unsigned int i;
- unsigned int taamin_ps = 0;
- unsigned int tckmin_x_ps = 0;
unsigned int common_caslat;
unsigned int caslat_actual;
unsigned int retry = 16;
unsigned int tmp;
const unsigned int mclk_ps = get_memory_clk_period_ps();
+#ifdef CONFIG_SYS_FSL_DDR3
+ const unsigned int taamax = 20000;
+#else
+ const unsigned int taamax = 18000;
+#endif
/* compute the common CAS latency supported between slots */
tmp = dimm_params[0].caslat_x;
}
common_caslat = tmp;
- /* compute the max tAAmin tCKmin between slots */
- for (i = 0; i < number_of_dimms; i++) {
- taamin_ps = max(taamin_ps, dimm_params[i].taa_ps);
- tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
- }
/* validate if the memory clk is in the range of dimms */
- if (mclk_ps < tckmin_x_ps) {
+ if (mclk_ps < outpdimm->tckmin_x_ps) {
printf("DDR clock (MCLK cycle %u ps) is faster than "
"the slowest DIMM(s) (tCKmin %u ps) can support.\n",
- mclk_ps, tckmin_x_ps);
+ mclk_ps, outpdimm->tckmin_x_ps);
+ }
+#ifdef CONFIG_SYS_FSL_DDR4
+ if (mclk_ps > outpdimm->tckmax_ps) {
+ printf("DDR clock (MCLK cycle %u ps) is slower than DIMM(s) (tCKmax %u ps) can support.\n",
+ mclk_ps, outpdimm->tckmax_ps);
}
+#endif
/* determine the acutal cas latency */
- caslat_actual = (taamin_ps + mclk_ps - 1) / mclk_ps;
+ caslat_actual = (outpdimm->taamin_ps + mclk_ps - 1) / mclk_ps;
/* check if the dimms support the CAS latency */
while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
caslat_actual++;
}
/* once the caculation of caslat_actual is completed
* we must verify that this CAS latency value does not
- * exceed tAAmax, which is 20 ns for all DDR3 speed grades
+ * exceed tAAmax, which is 20 ns for all DDR3 speed grades,
+ * 18ns for all DDR4 speed grades.
*/
- if (caslat_actual * mclk_ps > 20000) {
+ if (caslat_actual * mclk_ps > taamax) {
printf("The choosen cas latency %d is too large\n",
caslat_actual);
}
- outpdimm->lowest_common_SPD_caslat = caslat_actual;
+ outpdimm->lowest_common_spd_caslat = caslat_actual;
+ debug("lowest_common_spd_caslat is 0x%x\n", caslat_actual);
+
+ return 0;
+}
+#else /* for DDR1 and DDR2 */
+static unsigned int
+compute_cas_latency(const dimm_params_t *dimm_params,
+ common_timing_params_t *outpdimm,
+ unsigned int number_of_dimms)
+{
+ int i;
+ const unsigned int mclk_ps = get_memory_clk_period_ps();
+ unsigned int lowest_good_caslat;
+ unsigned int not_ok;
+ unsigned int temp1, temp2;
+
+ debug("using mclk_ps = %u\n", mclk_ps);
+ if (mclk_ps > outpdimm->tckmax_ps) {
+ printf("Warning: DDR clock (%u ps) is slower than DIMM(s) (tCKmax %u ps)\n",
+ mclk_ps, outpdimm->tckmax_ps);
+ }
+
+ /*
+ * Compute a CAS latency suitable for all DIMMs
+ *
+ * Strategy for SPD-defined latencies: compute only
+ * CAS latency defined by all DIMMs.
+ */
+
+ /*
+ * Step 1: find CAS latency common to all DIMMs using bitwise
+ * operation.
+ */
+ temp1 = 0xFF;
+ for (i = 0; i < number_of_dimms; i++) {
+ if (dimm_params[i].n_ranks) {
+ temp2 = 0;
+ temp2 |= 1 << dimm_params[i].caslat_x;
+ temp2 |= 1 << dimm_params[i].caslat_x_minus_1;
+ temp2 |= 1 << dimm_params[i].caslat_x_minus_2;
+ /*
+ * If there was no entry for X-2 (X-1) in
+ * the SPD, then caslat_x_minus_2
+ * (caslat_x_minus_1) contains either 255 or
+ * 0xFFFFFFFF because that's what the glorious
+ * __ilog2 function returns for an input of 0.
+ * On 32-bit PowerPC, left shift counts with bit
+ * 26 set (that the value of 255 or 0xFFFFFFFF
+ * will have), cause the destination register to
+ * be 0. That is why this works.
+ */
+ temp1 &= temp2;
+ }
+ }
+
+ /*
+ * Step 2: check each common CAS latency against tCK of each
+ * DIMM's SPD.
+ */
+ lowest_good_caslat = 0;
+ temp2 = 0;
+ while (temp1) {
+ not_ok = 0;
+ temp2 = __ilog2(temp1);
+ debug("checking common caslat = %u\n", temp2);
+
+ /* Check if this CAS latency will work on all DIMMs at tCK. */
+ for (i = 0; i < number_of_dimms; i++) {
+ if (!dimm_params[i].n_ranks)
+ continue;
+
+ if (dimm_params[i].caslat_x == temp2) {
+ if (mclk_ps >= dimm_params[i].tckmin_x_ps) {
+ debug("CL = %u ok on DIMM %u at tCK=%u ps with tCKmin_X_ps of %u\n",
+ temp2, i, mclk_ps,
+ dimm_params[i].tckmin_x_ps);
+ continue;
+ } else {
+ not_ok++;
+ }
+ }
+
+ if (dimm_params[i].caslat_x_minus_1 == temp2) {
+ unsigned int tckmin_x_minus_1_ps
+ = dimm_params[i].tckmin_x_minus_1_ps;
+ if (mclk_ps >= tckmin_x_minus_1_ps) {
+ debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_1_ps of %u\n",
+ temp2, i, mclk_ps,
+ tckmin_x_minus_1_ps);
+ continue;
+ } else {
+ not_ok++;
+ }
+ }
+
+ if (dimm_params[i].caslat_x_minus_2 == temp2) {
+ unsigned int tckmin_x_minus_2_ps
+ = dimm_params[i].tckmin_x_minus_2_ps;
+ if (mclk_ps >= tckmin_x_minus_2_ps) {
+ debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_2_ps of %u\n",
+ temp2, i, mclk_ps,
+ tckmin_x_minus_2_ps);
+ continue;
+ } else {
+ not_ok++;
+ }
+ }
+ }
+
+ if (!not_ok)
+ lowest_good_caslat = temp2;
+
+ temp1 &= ~(1 << temp2);
+ }
+
+ debug("lowest common SPD-defined CAS latency = %u\n",
+ lowest_good_caslat);
+ outpdimm->lowest_common_spd_caslat = lowest_good_caslat;
+
+
+ /*
+ * Compute a common 'de-rated' CAS latency.
+ *
+ * The strategy here is to find the *highest* dereated cas latency
+ * with the assumption that all of the DIMMs will support a dereated
+ * CAS latency higher than or equal to their lowest dereated value.
+ */
+ temp1 = 0;
+ for (i = 0; i < number_of_dimms; i++)
+ temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
+
+ outpdimm->highest_common_derated_caslat = temp1;
+ debug("highest common dereated CAS latency = %u\n", temp1);
return 0;
}
unsigned int tckmin_x_ps = 0;
unsigned int tckmax_ps = 0xFFFFFFFF;
- unsigned int tckmax_max_ps = 0;
unsigned int trcd_ps = 0;
unsigned int trp_ps = 0;
unsigned int tras_ps = 0;
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
+ unsigned int taamin_ps = 0;
+#endif
+#ifdef CONFIG_SYS_FSL_DDR4
+ unsigned int twr_ps = 15000;
+ unsigned int trfc1_ps = 0;
+ unsigned int trfc2_ps = 0;
+ unsigned int trfc4_ps = 0;
+ unsigned int trrds_ps = 0;
+ unsigned int trrdl_ps = 0;
+ unsigned int tccdl_ps = 0;
+#else
unsigned int twr_ps = 0;
unsigned int twtr_ps = 0;
unsigned int trfc_ps = 0;
unsigned int trrd_ps = 0;
+ unsigned int trtp_ps = 0;
+#endif
unsigned int trc_ps = 0;
unsigned int refresh_rate_ps = 0;
unsigned int extended_op_srt = 1;
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
unsigned int tis_ps = 0;
unsigned int tih_ps = 0;
unsigned int tds_ps = 0;
unsigned int tdh_ps = 0;
- unsigned int trtp_ps = 0;
unsigned int tdqsq_max_ps = 0;
unsigned int tqhs_ps = 0;
-
+#endif
unsigned int temp1, temp2;
unsigned int additive_latency = 0;
-#if !defined(CONFIG_SYS_FSL_DDR3)
- const unsigned int mclk_ps = get_memory_clk_period_ps();
- unsigned int lowest_good_caslat;
- unsigned int not_ok;
-
- debug("using mclk_ps = %u\n", mclk_ps);
-#endif
temp1 = 0;
for (i = 0; i < number_of_dimms; i++) {
* i.e., this is the slowest the whole system can go.
*/
tckmax_ps = min(tckmax_ps, dimm_params[i].tckmax_ps);
-
- /* Either find maximum value to determine slowest
- * speed, delay, time, period, etc */
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
+ taamin_ps = max(taamin_ps, dimm_params[i].taa_ps);
+#endif
tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
- tckmax_max_ps = max(tckmax_max_ps, dimm_params[i].tckmax_ps);
trcd_ps = max(trcd_ps, dimm_params[i].trcd_ps);
trp_ps = max(trp_ps, dimm_params[i].trp_ps);
tras_ps = max(tras_ps, dimm_params[i].tras_ps);
+#ifdef CONFIG_SYS_FSL_DDR4
+ trfc1_ps = max(trfc1_ps, dimm_params[i].trfc1_ps);
+ trfc2_ps = max(trfc2_ps, dimm_params[i].trfc2_ps);
+ trfc4_ps = max(trfc4_ps, dimm_params[i].trfc4_ps);
+ trrds_ps = max(trrds_ps, dimm_params[i].trrds_ps);
+ trrdl_ps = max(trrdl_ps, dimm_params[i].trrdl_ps);
+ tccdl_ps = max(tccdl_ps, dimm_params[i].tccdl_ps);
+#else
twr_ps = max(twr_ps, dimm_params[i].twr_ps);
twtr_ps = max(twtr_ps, dimm_params[i].twtr_ps);
trfc_ps = max(trfc_ps, dimm_params[i].trfc_ps);
trrd_ps = max(trrd_ps, dimm_params[i].trrd_ps);
+ trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps);
+#endif
trc_ps = max(trc_ps, dimm_params[i].trc_ps);
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
tis_ps = max(tis_ps, dimm_params[i].tis_ps);
tih_ps = max(tih_ps, dimm_params[i].tih_ps);
tds_ps = max(tds_ps, dimm_params[i].tds_ps);
tdh_ps = max(tdh_ps, dimm_params[i].tdh_ps);
- trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps);
tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps);
- refresh_rate_ps = max(refresh_rate_ps,
- dimm_params[i].refresh_rate_ps);
- /* extended_op_srt is either 0 or 1, 0 having priority */
- extended_op_srt = min(extended_op_srt,
- dimm_params[i].extended_op_srt);
-
/*
* Find maximum tdqsq_max_ps to find slowest.
*
* strategy for this parameter?
*/
tdqsq_max_ps = max(tdqsq_max_ps, dimm_params[i].tdqsq_max_ps);
+#endif
+ refresh_rate_ps = max(refresh_rate_ps,
+ dimm_params[i].refresh_rate_ps);
+ /* extended_op_srt is either 0 or 1, 0 having priority */
+ extended_op_srt = min(extended_op_srt,
+ dimm_params[i].extended_op_srt);
}
outpdimm->ndimms_present = number_of_dimms - temp1;
outpdimm->tckmin_x_ps = tckmin_x_ps;
outpdimm->tckmax_ps = tckmax_ps;
- outpdimm->tckmax_max_ps = tckmax_max_ps;
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
+ outpdimm->taamin_ps = taamin_ps;
+#endif
outpdimm->trcd_ps = trcd_ps;
outpdimm->trp_ps = trp_ps;
outpdimm->tras_ps = tras_ps;
- outpdimm->twr_ps = twr_ps;
+#ifdef CONFIG_SYS_FSL_DDR4
+ outpdimm->trfc1_ps = trfc1_ps;
+ outpdimm->trfc2_ps = trfc2_ps;
+ outpdimm->trfc4_ps = trfc4_ps;
+ outpdimm->trrds_ps = trrds_ps;
+ outpdimm->trrdl_ps = trrdl_ps;
+ outpdimm->tccdl_ps = tccdl_ps;
+#else
outpdimm->twtr_ps = twtr_ps;
outpdimm->trfc_ps = trfc_ps;
outpdimm->trrd_ps = trrd_ps;
+ outpdimm->trtp_ps = trtp_ps;
+#endif
+ outpdimm->twr_ps = twr_ps;
outpdimm->trc_ps = trc_ps;
outpdimm->refresh_rate_ps = refresh_rate_ps;
outpdimm->extended_op_srt = extended_op_srt;
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
outpdimm->tis_ps = tis_ps;
outpdimm->tih_ps = tih_ps;
outpdimm->tds_ps = tds_ps;
outpdimm->tdh_ps = tdh_ps;
- outpdimm->trtp_ps = trtp_ps;
outpdimm->tdqsq_max_ps = tdqsq_max_ps;
outpdimm->tqhs_ps = tqhs_ps;
+#endif
/* Determine common burst length for all DIMMs. */
temp1 = 0xff;
if (temp1 != 0)
printf("ERROR: Mix different RDIMM detected!\n");
-#if defined(CONFIG_SYS_FSL_DDR3)
- if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
+ /* calculate cas latency for all DDR types */
+ if (compute_cas_latency(dimm_params, outpdimm, number_of_dimms))
return 1;
-#else
- /*
- * Compute a CAS latency suitable for all DIMMs
- *
- * Strategy for SPD-defined latencies: compute only
- * CAS latency defined by all DIMMs.
- */
-
- /*
- * Step 1: find CAS latency common to all DIMMs using bitwise
- * operation.
- */
- temp1 = 0xFF;
- for (i = 0; i < number_of_dimms; i++) {
- if (dimm_params[i].n_ranks) {
- temp2 = 0;
- temp2 |= 1 << dimm_params[i].caslat_x;
- temp2 |= 1 << dimm_params[i].caslat_x_minus_1;
- temp2 |= 1 << dimm_params[i].caslat_x_minus_2;
- /*
- * FIXME: If there was no entry for X-2 (X-1) in
- * the SPD, then caslat_x_minus_2
- * (caslat_x_minus_1) contains either 255 or
- * 0xFFFFFFFF because that's what the glorious
- * __ilog2 function returns for an input of 0.
- * On 32-bit PowerPC, left shift counts with bit
- * 26 set (that the value of 255 or 0xFFFFFFFF
- * will have), cause the destination register to
- * be 0. That is why this works.
- */
- temp1 &= temp2;
- }
- }
-
- /*
- * Step 2: check each common CAS latency against tCK of each
- * DIMM's SPD.
- */
- lowest_good_caslat = 0;
- temp2 = 0;
- while (temp1) {
- not_ok = 0;
- temp2 = __ilog2(temp1);
- debug("checking common caslat = %u\n", temp2);
-
- /* Check if this CAS latency will work on all DIMMs at tCK. */
- for (i = 0; i < number_of_dimms; i++) {
- if (!dimm_params[i].n_ranks) {
- continue;
- }
- if (dimm_params[i].caslat_x == temp2) {
- if (mclk_ps >= dimm_params[i].tckmin_x_ps) {
- debug("CL = %u ok on DIMM %u at tCK=%u"
- " ps with its tCKmin_X_ps of %u\n",
- temp2, i, mclk_ps,
- dimm_params[i].tckmin_x_ps);
- continue;
- } else {
- not_ok++;
- }
- }
-
- if (dimm_params[i].caslat_x_minus_1 == temp2) {
- unsigned int tckmin_x_minus_1_ps
- = dimm_params[i].tckmin_x_minus_1_ps;
- if (mclk_ps >= tckmin_x_minus_1_ps) {
- debug("CL = %u ok on DIMM %u at "
- "tCK=%u ps with its "
- "tckmin_x_minus_1_ps of %u\n",
- temp2, i, mclk_ps,
- tckmin_x_minus_1_ps);
- continue;
- } else {
- not_ok++;
- }
- }
-
- if (dimm_params[i].caslat_x_minus_2 == temp2) {
- unsigned int tckmin_x_minus_2_ps
- = dimm_params[i].tckmin_x_minus_2_ps;
- if (mclk_ps >= tckmin_x_minus_2_ps) {
- debug("CL = %u ok on DIMM %u at "
- "tCK=%u ps with its "
- "tckmin_x_minus_2_ps of %u\n",
- temp2, i, mclk_ps,
- tckmin_x_minus_2_ps);
- continue;
- } else {
- not_ok++;
- }
- }
- }
-
- if (!not_ok) {
- lowest_good_caslat = temp2;
- }
-
- temp1 &= ~(1 << temp2);
- }
-
- debug("lowest common SPD-defined CAS latency = %u\n",
- lowest_good_caslat);
- outpdimm->lowest_common_SPD_caslat = lowest_good_caslat;
-
-
- /*
- * Compute a common 'de-rated' CAS latency.
- *
- * The strategy here is to find the *highest* dereated cas latency
- * with the assumption that all of the DIMMs will support a dereated
- * CAS latency higher than or equal to their lowest dereated value.
- */
- temp1 = 0;
- for (i = 0; i < number_of_dimms; i++) {
- temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
- }
- outpdimm->highest_common_derated_caslat = temp1;
- debug("highest common dereated CAS latency = %u\n", temp1);
-#endif /* #if defined(CONFIG_SYS_FSL_DDR3) */
/* Determine if all DIMMs ECC capable. */
temp1 = 1;
}
outpdimm->all_dimms_ecc_capable = temp1;
-#ifndef CONFIG_SYS_FSL_DDR3
- /* FIXME: move to somewhere else to validate. */
- if (mclk_ps > tckmax_max_ps) {
- printf("Warning: some of the installed DIMMs "
- "can not operate this slowly.\n");
- return 1;
- }
-#endif
/*
* Compute additive latency.
*
additive_latency = 0;
#if defined(CONFIG_SYS_FSL_DDR2)
- if (lowest_good_caslat < 4) {
- additive_latency = (picos_to_mclk(trcd_ps) > lowest_good_caslat)
- ? picos_to_mclk(trcd_ps) - lowest_good_caslat : 0;
+ if ((outpdimm->lowest_common_spd_caslat < 4) &&
+ (picos_to_mclk(trcd_ps) > outpdimm->lowest_common_spd_caslat)) {
+ additive_latency = picos_to_mclk(trcd_ps) -
+ outpdimm->lowest_common_spd_caslat;
if (mclk_to_picos(additive_latency) > trcd_ps) {
additive_latency = picos_to_mclk(trcd_ps);
debug("setting additive_latency to %u because it was "
" greater than tRCD_ps\n", additive_latency);
}
}
-
-#elif defined(CONFIG_SYS_FSL_DDR3)
- /*
- * The system will not use the global auto-precharge mode.
- * However, it uses the page mode, so we set AL=0
- */
- additive_latency = 0;
#endif
/*
* Validate additive latency
- * FIXME: move to somewhere else to validate
*
* AL <= tRCD(min)
*/
debug("trcd_ps = %u\n", outpdimm->trcd_ps);
debug("trp_ps = %u\n", outpdimm->trp_ps);
debug("tras_ps = %u\n", outpdimm->tras_ps);
- debug("twr_ps = %u\n", outpdimm->twr_ps);
+#ifdef CONFIG_SYS_FSL_DDR4
+ debug("trfc1_ps = %u\n", trfc1_ps);
+ debug("trfc2_ps = %u\n", trfc2_ps);
+ debug("trfc4_ps = %u\n", trfc4_ps);
+ debug("trrds_ps = %u\n", trrds_ps);
+ debug("trrdl_ps = %u\n", trrdl_ps);
+ debug("tccdl_ps = %u\n", tccdl_ps);
+#else
debug("twtr_ps = %u\n", outpdimm->twtr_ps);
debug("trfc_ps = %u\n", outpdimm->trfc_ps);
debug("trrd_ps = %u\n", outpdimm->trrd_ps);
+#endif
+ debug("twr_ps = %u\n", outpdimm->twr_ps);
debug("trc_ps = %u\n", outpdimm->trc_ps);
return 0;
/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
#endif
+#define SPD_SPA0_ADDRESS 0x36
+#define SPD_SPA1_ADDRESS 0x37
+
static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
{
int ret;
+#ifdef CONFIG_SYS_FSL_DDR4
+ uint8_t dummy = 0;
+#endif
i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
+#ifdef CONFIG_SYS_FSL_DDR4
+ /*
+ * DDR4 SPD has 384 to 512 bytes
+ * To access the lower 256 bytes, we need to set EE page address to 0
+ * To access the upper 256 bytes, we need to set EE page address to 1
+ * See Jedec standar No. 21-C for detail
+ */
+ i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
+ ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);
+ if (!ret) {
+ i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
+ ret = i2c_read(i2c_address, 0, 1,
+ (uchar *)((ulong)spd + 256),
+ min(256, sizeof(generic_spd_eeprom_t) - 256));
+ }
+#else
ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
sizeof(generic_spd_eeprom_t));
+#endif
if (ret) {
if (i2c_address ==
if ((1 << s) != step)
return step_string_tbl[7];
+ if (s >= ARRAY_SIZE(step_string_tbl)) {
+ printf("Error for the step in %s\n", __func__);
+ s = 0;
+ }
+
return step_string_tbl[s];
}
/* STEP 5: Assign addresses to chip selects */
check_interleaving_options(pinfo);
total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
+ debug("Total mem %llu assigned\n", total_mem);
case STEP_COMPUTE_REGS:
/* STEP 6: compute controller register values */
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
#endif
+DECLARE_GLOBAL_DATA_PTR;
/*
* regs has the to-be-set values for DDR controller registers
u32 save1, save2;
#endif
+#ifdef CONFIG_DEEP_SLEEP
+ const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ bool sleep_flag = 0;
+#endif
+
+#ifdef CONFIG_DEEP_SLEEP
+ if (in_be32(&gur->scrtsr[0]) & (1 << 3))
+ sleep_flag = 1;
+#endif
+
switch (ctrl_num) {
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
- out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+#ifdef CONFIG_DEEP_SLEEP
+ if (sleep_flag)
+ out_be32(&ddr->sdram_cfg_2,
+ regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
+ else
+#endif
+ out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
- out_be32(&ddr->init_addr, regs->ddr_init_addr);
- out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+#ifdef CONFIG_DEEP_SLEEP
+ if (sleep_flag) {
+ out_be32(&ddr->init_addr, 0);
+ out_be32(&ddr->init_ext_addr, (1 << 31));
+ } else
+#endif
+ {
+ out_be32(&ddr->init_addr, regs->ddr_init_addr);
+ out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+ }
out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
udelay(500);
asm volatile("sync;isync");
+#ifdef CONFIG_DEEP_SLEEP
+ if (sleep_flag) {
+ /* enter self-refresh */
+ setbits_be32(&ddr->sdram_cfg_2, (1 << 31));
+ /* do board specific memory setup */
+ board_mem_sleep_setup();
+ }
+#endif
+
/* Let the controller go */
- temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
+#ifdef CONFIG_DEEP_SLEEP
+ if (sleep_flag)
+ temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
+ else
+#endif
+ temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);
out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
asm volatile("sync;isync");
clrbits_be32(&ddr->sdram_cfg, 0x2);
}
#endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
+#ifdef CONFIG_DEEP_SLEEP
+ if (sleep_flag)
+ /* exit self-refresh */
+ clrbits_be32(&ddr->sdram_cfg_2, (1 << 31));
+#endif
}
/*
- * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2010-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
unsigned int odt_rtt_wr;
};
-#ifdef CONFIG_SYS_FSL_DDR3
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
static const struct dynamic_odt single_Q[4] = {
{ /* cs0 */
FSL_DDR_ODT_NEVER,
DDR3_RTT_OFF
}
};
-#else /* CONFIG_SYS_FSL_DDR3 */
+#else /* CONFIG_SYS_FSL_DDR3 || CONFIG_SYS_FSL_DDR4 */
static const struct dynamic_odt single_Q[4] = {
{0, 0, 0, 0},
{0, 0, 0, 0},
unsigned int i;
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
-#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
+#if defined(CONFIG_SYS_FSL_DDR3) || \
+ defined(CONFIG_SYS_FSL_DDR2) || \
+ defined(CONFIG_SYS_FSL_DDR4)
const struct dynamic_odt *pdodt = odt_unknown;
#endif
ulong ddr_freq;
if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
-#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
+#if defined(CONFIG_SYS_FSL_DDR3) || \
+ defined(CONFIG_SYS_FSL_DDR2) || \
+ defined(CONFIG_SYS_FSL_DDR4)
/* Chip select options. */
- if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
- switch (pdimm[0].n_ranks) {
- case 1:
- pdodt = single_S;
- break;
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+ switch (pdimm[0].n_ranks) {
+ case 1:
+ pdodt = single_S;
+ break;
+ case 2:
+ pdodt = single_D;
+ break;
+ case 4:
+ pdodt = single_Q;
+ break;
+ }
+#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ switch (pdimm[0].n_ranks) {
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+ case 4:
+ pdodt = single_Q;
+ if (pdimm[1].n_ranks)
+ printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n");
+ break;
+#endif
+ case 2:
+ switch (pdimm[1].n_ranks) {
case 2:
- pdodt = single_D;
+ pdodt = dual_DD;
break;
- case 4:
- pdodt = single_Q;
+ case 1:
+ pdodt = dual_DS;
break;
- }
- } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
- switch (pdimm[0].n_ranks) {
-#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
- case 4:
- pdodt = single_Q;
- if (pdimm[1].n_ranks)
- printf("Error: Quad- and Dual-rank DIMMs "
- "cannot be used together\n");
+ case 0:
+ pdodt = dual_D0;
break;
-#endif
+ }
+ break;
+ case 1:
+ switch (pdimm[1].n_ranks) {
case 2:
- switch (pdimm[1].n_ranks) {
- case 2:
- pdodt = dual_DD;
- break;
- case 1:
- pdodt = dual_DS;
- break;
- case 0:
- pdodt = dual_D0;
- break;
- }
+ pdodt = dual_SD;
break;
case 1:
- switch (pdimm[1].n_ranks) {
- case 2:
- pdodt = dual_SD;
- break;
- case 1:
- pdodt = dual_SS;
- break;
- case 0:
- pdodt = dual_S0;
- break;
- }
+ pdodt = dual_SS;
break;
case 0:
- switch (pdimm[1].n_ranks) {
- case 2:
- pdodt = dual_0D;
- break;
- case 1:
- pdodt = dual_0S;
- break;
- }
+ pdodt = dual_S0;
+ break;
+ }
+ break;
+ case 0:
+ switch (pdimm[1].n_ranks) {
+ case 2:
+ pdodt = dual_0D;
+ break;
+ case 1:
+ pdodt = dual_0S;
break;
}
+ break;
}
-#endif
+#endif /* CONFIG_DIMM_SLOTS_PER_CTLR */
+#endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */
/* Pick chip-select local options. */
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
+#if defined(CONFIG_SYS_FSL_DDR3) || \
+ defined(CONFIG_SYS_FSL_DDR2) || \
+ defined(CONFIG_SYS_FSL_DDR4)
popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
/* Choose burst length. */
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
#if defined(CONFIG_E500MC)
popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */
popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
#endif
/* Choose ddr controller address mirror mode */
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
popts->mirrored_dimm = pdimm[0].mirrored_dimm;
#endif
* BSTTOPRE precharge interval
*
* Set this to 0 for global auto precharge
- *
- * FIXME: Should this be configured in picoseconds?
- * Why it should be in ps: better understanding of this
- * relative to actual DRAM timing parameters such as tRAS.
- * e.g. tRAS(min) = 40 ns
+ * The value of 0x100 has been used for DDR1, DDR2, DDR3.
+ * It is not wrong. Any value should be OK. The performance depends on
+ * applications. There is no one good value for all.
*/
popts->bstopre = 0x100;
*/
popts->tfaw_window_four_activates_ps = 37500;
-#elif defined(CONFIG_SYS_FSL_DDR3)
+#else
popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
#endif
popts->zq_en = 0;
popts->wrlvl_en = 0;
-#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
/*
* due to ddr3 dimm is fly-by topology
* we suggest to enable write leveling to
popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
popts->memctl_interleaving = 1;
debug("256 Byte interleaving\n");
- goto done;
-#endif
+#else
/*
* test null first. if CONFIG_HWCONFIG is not defined
* hwconfig_arg_cmp returns non-zero
popts->memctl_interleaving = 0;
printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
}
+#endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
done:
-#endif
+#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
/* test null first. if CONFIG_HWCONFIG is not defined,
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
case FSL_DDR_SUPERBANK_INTERLEAVING:
- if (3 == CONFIG_NUM_DDR_CONTROLLERS)
+#if (3 == CONFIG_NUM_DDR_CONTROLLERS)
k = 2;
- else
+#else
k = CONFIG_NUM_DDR_CONTROLLERS;
+#endif
break;
case FSL_DDR_3WAY_1KB_INTERLEAVING:
case FSL_DDR_3WAY_4KB_INTERLEAVING:
/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
#define ULL_8FS 0xFFFFFFFFULL
+u32 fsl_ddr_get_version(void)
+{
+ struct ccsr_ddr __iomem *ddr;
+ u32 ver_major_minor_errata;
+
+ ddr = (void *)_DDR_ADDR;
+ ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
+ ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
+
+ return ver_major_minor_errata;
+}
+
/*
* Round up mclk_ps to nearest 1 ps in memory controller code
* if the error is 0.5ps or more.
case SDRAM_TYPE_DDR3:
puts("3");
break;
+ case SDRAM_TYPE_DDR4:
+ puts("4");
+ break;
default:
puts("?");
break;
puts(", 64-bit");
/* Calculate CAS latency based on timing cfg values */
- cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
- if ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 1)
- cas_lat += (8 << 1);
+ cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf);
+ if (fsl_ddr_get_version() <= 0x40400)
+ cas_lat += 1;
+ else
+ cas_lat += 2;
+ cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4;
printf(", CL=%d", cas_lat >> 1);
if (cas_lat & 0x1)
puts(".5");
set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
#endif
}
+
+void init_final_memctl_regs(void)
+{
+#ifdef CONFIG_SYS_CSPR0_FINAL
+ set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL);
+#endif
+}
#define MBRDBR_BOOT_SIG_AA 0x1ff
#define CONFIG_CFG_DATA_SECTOR 0
+
+void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst)
+{
+ uint blk_start, blk_cnt, err;
+
+ struct mmc *mmc = find_mmc_device(0);
+ if (!mmc) {
+ puts("spl: mmc device not found!!\n");
+ hang();
+ }
+
+ if (mmc_init(mmc)) {
+ puts("MMC init failed\n");
+ return;
+ }
+
+ blk_start = ALIGN(offs, mmc->read_bl_len) / mmc->read_bl_len;
+ blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
+
+ err = mmc->block_dev.block_read(0, blk_start, blk_cnt, vdst);
+ if (err != blk_cnt) {
+ puts("spl: mmc read failed!!\n");
+ hang();
+ }
+}
+
/*
* The main entry for mmc booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
{
__attribute__((noreturn)) void (*uboot)(void);
uint blk_start, blk_cnt, err;
- u32 blklen;
+#ifndef CONFIG_FSL_CORENET
uchar *tmp_buf;
+ u32 blklen;
uchar val;
uint i, byte_num;
+#endif
u32 offset, code_len;
struct mmc *mmc;
(uchar *)CONFIG_SYS_MMC_U_BOOT_DST);
if (err != blk_cnt) {
puts("spl: mmc read failed!!\n");
+#ifndef CONFIG_FSL_CORENET
free(tmp_buf);
+#endif
hang();
}
return __raw_readw((u16 *)marker) != 0xffff;
}
-#ifdef CONFIG_TPL_BUILD
int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
-#else
-static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst)
-#endif
{
struct fsl_ifc *ifc = IFC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
return 0;
}
-/*
- * Defines a static function nand_load_image() here, because non-static makes
- * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
- */
-#ifndef CONFIG_TPL_BUILD
-#define nand_spl_load_image(offs, uboot_size, vdst) \
- nand_load(offs, uboot_size, vdst)
-#endif
-
/*
* Main entrypoint for NAND Boot. It's necessary that SDRAM is already
* configured and available since this code loads the main U-boot image
#define ESPI_BOOT_IMAGE_ADDR 0x50
#define CONFIG_CFG_DATA_SECTOR 0
+void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst)
+{
+ struct spi_flash *flash;
+
+ flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+ if (flash == NULL) {
+ puts("\nspi_flash_probe failed");
+ hang();
+ }
+
+ spi_flash_read(flash, offs, size, vdst);
+}
+
/*
* The main entry for SPI booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
void spi_boot(void)
{
void (*uboot)(void) __noreturn;
- u32 offset, code_len;
+ u32 offset, code_len, copy_len = 0;
+#ifndef CONFIG_FSL_CORENET
unsigned char *buf = NULL;
+#endif
struct spi_flash *flash;
flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
code_len = code_len - CONFIG_SPL_MAX_SIZE;
#endif
/* copy code to DDR */
- spi_flash_read(flash, offset, code_len,
- (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST);
+ printf("Loading second stage boot loader ");
+ while (copy_len <= code_len) {
+ spi_flash_read(flash, offset + copy_len, 0x2000,
+ (void *)(CONFIG_SYS_SPI_FLASH_U_BOOT_DST
+ + copy_len));
+ copy_len = copy_len + 0x2000;
+ putc('.');
+ }
+
/*
* Jump to U-Boot image
*/
{
int rc;
#if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
- void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR;
+ void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
- rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_ADDR,
+ rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
&fw_length, (u_char *)addr);
if (rc == -EUCLEAN) {
printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
- CONFIG_SYS_QE_FMAN_FW_ADDR, rc);
+ CONFIG_SYS_FMAN_FW_ADDR, rc);
}
#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
struct spi_flash *ucode_flash;
if (!ucode_flash)
printf("SF: probe for ucode failed\n");
else {
- ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FMAN_FW_ADDR,
+ ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR,
CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
if (ret)
printf("SF: read for ucode failed\n");
int dev = CONFIG_SYS_MMC_ENV_DEV;
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
- u32 blk = CONFIG_SYS_QE_FMAN_FW_ADDR / 512;
+ u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
if (!mmc)
flush_cache((ulong)addr, cnt * 512);
}
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
- void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR;
+ void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
#else
void *addr = NULL;
#endif
bus->priv = info->regs;
+ /*
+ * On some platforms like B4860, default value of MDIO_CLK_DIV bits
+ * in mdio_stat(mdio_cfg) register generates MDIO clock too high
+ * (much higher than 2.5MHz), violating the IEEE specs.
+ * On other platforms like T1040, default value of MDIO_CLK_DIV bits
+ * is zero, so MDIO clock is disabled.
+ * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
+ * be properly initialized.
+ */
+ setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat,
+ MDIO_STAT_CLKDIV(258));
+
return mdio_register(bus);
}
.uid = 0x4dd074,
.mask = 0xffffffef,
.features = PHY_GBIT_FEATURES,
- .config = genphy_config,
+ .config = ar8021_config,
.startup = genphy_startup,
.shutdown = genphy_shutdown,
};
static struct phy_driver VSC8514_driver = {
.name = "Vitesse VSC8514",
- .uid = 0x70570,
+ .uid = 0x70670,
.mask = 0xffff0,
.features = PHY_GBIT_FEATURES,
.config = &vsc8514_config,
/*
* Upload microcode to IRAM for those SOCs which do not have ROM in QE.
*/
- qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR);
+ qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
/* enable the microcode in IRAM */
out_be32(&qe_immr->iram.iready,QE_IRAM_READY);
int qe_upload_firmware(const struct qe_firmware *firmware);
struct qe_firmware_info *qe_get_firmware_info(void);
void ft_qe_setup(void *blob);
+void qe_init(uint qe_base);
+void qe_reset(void);
#endif /* __QE_H__ */
#include <asm/io.h>
#include <usb/ehci-fsl.h>
#include <hwconfig.h>
+#include <asm/fsl_errata.h>
#include "ehci.h"
+static void set_txfifothresh(struct usb_ehci *, u32);
+
/* Check USB PHY clock valid */
static int usb_phy_clk_valid(struct usb_ehci *ehci)
{
struct usb_ehci *ehci = NULL;
const char *phy_type = NULL;
size_t len;
+ char current_usb_controller[5];
#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
char usb_phy[5];
usb_phy[0] = '\0';
#endif
+ if (has_erratum_a007075()) {
+ /*
+ * A 5ms delay is needed after applying soft-reset to the
+ * controller to let external ULPI phy come out of reset.
+ * This delay needs to be added before re-initializing
+ * the controller after soft-resetting completes
+ */
+ mdelay(5);
+ }
+ memset(current_usb_controller, '\0', 5);
+ snprintf(current_usb_controller, 4, "usb%d", index+1);
switch (index) {
case 0:
out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
/* Init phy */
- if (hwconfig_sub("usb1", "phy_type"))
- phy_type = hwconfig_subarg("usb1", "phy_type", &len);
+ if (hwconfig_sub(current_usb_controller, "phy_type"))
+ phy_type = hwconfig_subarg(current_usb_controller,
+ "phy_type", &len);
else
phy_type = getenv("usb_phy_type");
in_le32(&ehci->usbmode);
+ if (SVR_SOC_VER(get_svr()) == SVR_T4240 &&
+ IS_SVR_REV(get_svr(), 2, 0))
+ set_txfifothresh(ehci, TXFIFOTHRESH);
+
return 0;
}
{
return 0;
}
+
+/*
+ * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
+ * to counter DDR latencies in writing data into Tx buffer.
+ * This prevents Tx buffer from getting underrun
+ */
+static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
+{
+ u32 cmd;
+ cmd = ehci_readl(&ehci->txfilltuning);
+ cmd &= ~TXFIFO_THRESH_MASK;
+ cmd |= TXFIFO_THRESH(txfifo_thresh);
+ ehci_writel(&ehci->txfilltuning, cmd);
+}
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
unsigned int tckmin_x_ps;
unsigned int tckmax_ps;
- unsigned int tckmax_max_ps;
unsigned int trcd_ps;
unsigned int trp_ps;
unsigned int tras_ps;
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
+ unsigned int taamin_ps;
+#endif
- unsigned int twr_ps; /* maximum = 63750 ps */
+#ifdef CONFIG_SYS_FSL_DDR4
+ unsigned int trfc1_ps;
+ unsigned int trfc2_ps;
+ unsigned int trfc4_ps;
+ unsigned int trrds_ps;
+ unsigned int trrdl_ps;
+ unsigned int tccdl_ps;
+#else
unsigned int twtr_ps; /* maximum = 63750 ps */
unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns
= 511750 ps */
unsigned int trrd_ps; /* maximum = 63750 ps */
+ unsigned int trtp_ps; /* byte 38, spd->trtp */
+#endif
+ unsigned int twr_ps; /* maximum = 63750 ps */
unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
unsigned int refresh_rate_ps;
unsigned int extended_op_srt;
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
unsigned int tis_ps; /* byte 32, spd->ca_setup */
unsigned int tih_ps; /* byte 33, spd->ca_hold */
unsigned int tds_ps; /* byte 34, spd->data_setup */
unsigned int tdh_ps; /* byte 35, spd->data_hold */
- unsigned int trtp_ps; /* byte 38, spd->trtp */
unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */
unsigned int tqhs_ps; /* byte 45, spd->tqhs */
+#endif
unsigned int ndimms_present;
- unsigned int lowest_common_SPD_caslat;
+ unsigned int lowest_common_spd_caslat;
unsigned int highest_common_derated_caslat;
unsigned int additive_latency;
unsigned int all_dimms_burst_lengths_bitmask;
#define CONFIG_PHYS_64BIT
#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
+#ifndef CONFIG_NAND
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/b4860qds/b4_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/b4860qds/b4_rcw.cfg
+#else
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
+#define CONFIG_SPL_PAD_TO 0x40000
+#define CONFIG_SPL_MAX_SIZE 0x28000
+#define RESET_VECTOR_OFFSET 0x27FFC
+#define BOOT_PAGE_OFFSET 0x27000
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+#endif
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CONFIG_SYS_L3_SIZE 256 << 10
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_NAND
+#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_DDR_SPD
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_FSL_DDR3
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_FSL_DDR_INTERACTIVE
+#endif
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS1 0x51
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
#if defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_SYS_RAMBOOT
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* Serial Port - controlled on board with jumper J8
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
+#endif
/* Use the HUSH parser */
* env, so we got 0x110000.
*/
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
* 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
* master LAW->the ucode address in master's memory space.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
+#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
/* Serial Port */
#define CONFIG_SYS_TEXT_BASE 0x11000000
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#endif
+#ifdef CONFIG_NAND_SECBOOT
+#define CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE 0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
+#endif
#ifdef CONFIG_NAND
#define CONFIG_SPL
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
/* Serial Port */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
-#elif defined(CONFIG_NAND)
+#elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+#include <asm/fsl_secure_boot.h>
+
#endif /* __CONFIG_H */
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
/*
#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD 1
-#define CONFIG_SYS_TEXT_BASE 0xf8f80000
+#define CONFIG_SYS_TEXT_BASE 0xf8f40000
#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH 1
-#define CONFIG_SYS_TEXT_BASE 0xf8f80000
+#define CONFIG_SYS_TEXT_BASE 0xf8f40000
#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
#endif
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xfff00000
+#define CONFIG_SYS_QE_FW_ADDR 0xfff00000
/*
* BOOTP options
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0
-#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
+#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
+ defined(CONFIG_RAMBOOT_NAND)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#else
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
-#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\
- && !defined(CONFIG_SECURE_BOOT)
+#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_A003399_NOR_WORKAROUND
#endif
#endif
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
/*
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/*
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
#define CONFIG_SYS_NAND_BASE 0xffa00000
/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
#ifndef CONFIG_NAND_SPL
/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f00000
+#define CONFIG_SYS_FMAN_FW_ADDR 0x1f00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
#ifndef CONFIG_NAND_SPL
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
#define CONFIG_SYS_NAND_BASE 0xffa00000
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
/* Serial Port - controlled on board with jumper J8
* env, so we got 0x110000.
*/
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
* 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
* master LAW->the ucode address in master's memory space.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
+#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
/*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
+/* support deep sleep */
+#define CONFIG_DEEP_SLEEP
+#define CONFIG_SILENT_CONSOLE
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
+#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDR3
#define CONFIG_FSL_DDR_INTERACTIVE
+#endif
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/* Serial Port - controlled on board with jumper J8
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
+#define CONFIG_QE
+#define CONFIG_U_QE
/* Default address of microcode for the Linux Fman driver */
#if defined(CONFIG_SPIFLASH)
/*
* env, so we got 0x110000.
*/
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
* 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
+#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
+ "spi0=spife110000.0"
+#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
+ "128k(dtb),96m(fs),-(user);"\
+ "fff800000.flash:2m(uboot),9m(kernel),"\
+ "128k(dtb),96m(fs),-(user);spife110000.0:" \
+ "2m(uboot),9m(kernel),128k(dtb),-(user)"
+#endif
+
/*
* Environment
*/
+++ /dev/null
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * T1040 RDB board configuration file
- */
-#define CONFIG_T104xRDB
-#define CONFIG_T1040RDB
-#define CONFIG_PHYS_64BIT
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_MP /* support multiple processors */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff40000
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
-#define CONFIG_FSL_IFC /* Enable IFC Support */
-#define CONFIG_PCI /* Enable PCI/PCIE */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCIE1 /* PCIE controler 1 */
-#define CONFIG_PCIE2 /* PCIE controler 2 */
-#define CONFIG_PCIE3 /* PCIE controler 3 */
-#define CONFIG_PCIE4 /* PCIE controler 4 */
-
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#define CONFIG_FSL_LAW /* Use common FSL init code */
-
-#define CONFIG_ENV_OVERWRITE
-
-#ifdef CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_NOWHERE
-#else
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#endif
-
-#ifndef CONFIG_SYS_NO_FLASH
-#if defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
-#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (512 * 1658)
-#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
-#endif
-#else /* CONFIG_SYS_NO_FLASH */
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
-#endif
-
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 66666666
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_DDR_ECC
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-
-#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_FSL_DDR3
-
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x51
-
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe8000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-
-#define CONFIG_SYS_NOR_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-
-/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR2_EXT (0xf)
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2 0x0
-/* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
- FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x0) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3 0x0
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
- | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
- | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
-
-#if defined(CONFIG_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
-#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
-
-/* I2C bus multiplexer */
-#define I2C_MUX_PCA_ADDR 0x70
-#define I2C_MUX_CH_DEFAULT 0x8
-
-
-/*
- * eSPI - Enhanced SPI
- */
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_CMD_SF
-#define CONFIG_SF_DEFAULT_SPEED 10000000
-#define CONFIG_SF_DEFAULT_MODE 0
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 10000000
-#define CONFIG_ENV_SPI_MODE 0
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-#ifdef CONFIG_PCI
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#ifdef CONFIG_PCIE2
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#ifdef CONFIG_PCIE3
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-/* controller 4, Base address 203000 */
-#ifdef CONFIG_PCIE4
-#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-#endif
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_E1000
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
-#endif /* CONFIG_PCI */
-
-/* SATA */
-#define CONFIG_FSL_SATA_V2
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#endif
-
-/*
-* USB
-*/
-#define CONFIG_HAS_FSL_DR_USB
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_EXT2
-#endif
-#endif
-
-#define CONFIG_MMC
-
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS 25
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_NUM_PORTALS 25
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
- */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
-#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_REALTEK
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
-#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
-#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_ETHPRIME "FM1@DTSEC4"
-#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SETEXPR
-
-#ifdef CONFIG_PCI
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NET
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/
-
-#define CONFIG_BAUDRATE 115200
-
-#define __USB_PHY_TYPE utmi
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
- "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=t1040rdb/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=t1040rdb/t1040rdb.dtb\0" \
- "bdev=sda3\0" \
- "c=ffe\0"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#ifdef CONFIG_SECURE_BOOT
-#include <asm/fsl_secure_boot.h>
-#endif
-
-#endif /* __CONFIG_H */
/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
++ * Copyright 2014 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
#ifndef __CONFIG_H
#define __CONFIG_H
/*
- * T1042RDB_PI board configuration file
+ * T104x RDB board configuration file
*/
#define CONFIG_T104xRDB
-#define CONFIG_T1042RDB_PI
#define CONFIG_PHYS_64BIT
#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
+#ifdef CONFIG_T1040RDB
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
+#endif
+#ifdef CONFIG_T1042RDB_PI
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
+#endif
+
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
+#define CONFIG_SPL_PAD_TO 0x40000
+#define CONFIG_SPL_MAX_SIZE 0x28000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+#define RESET_VECTOR_OFFSET 0x27FFC
+#define BOOT_PAGE_OFFSET 0x27000
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_SPI_BOOT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
#endif
/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
+/* support deep sleep */
+#define CONFIG_DEEP_SLEEP
+#define CONFIG_SILENT_CONSOLE
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#define CONFIG_ENV_OVERWRITE
-#ifdef CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_NOWHERE
-#else
+#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#endif
-#ifndef CONFIG_SYS_NO_FLASH
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (512 * 1658)
+#define CONFIG_ENV_OFFSET (512 * 0x800)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
-#else /* CONFIG_SYS_NO_FLASH */
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
-#endif
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 66666666
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CONFIG_SYS_L3_SIZE 256 << 10
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
/* CPLD on IFC */
+#define CPLD_LBMAP_MASK 0x3F
+#define CPLD_BANK_SEL_MASK 0x07
+#define CPLD_BANK_OVERRIDE 0x40
+#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
+#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
+#define CPLD_LBMAP_RESET 0xFF
+#define CPLD_LBMAP_SHIFT 0x03
+
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
#define CONFIG_SYS_CSPR2_EXT (0xf)
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
#if defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_SYS_RAMBOOT
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* Serial Port - controlled on board with jumper J8
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
+#endif
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x70
+#ifdef CONFIG_T1040RDB
+#define I2C_MUX_CH_DEFAULT 0x8
+#endif
+#ifdef CONFIG_T1042RDB_PI
/*
* RTC configuration
*/
/*DVI encoder*/
#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
+#endif
/*
* eSPI - Enhanced SPI
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
+#ifdef CONFIG_T1040RDB
+#define CONFIG_QE
+#define CONFIG_U_QE
+#endif
+
/* Default address of microcode for the Linux Fman driver */
#if defined(CONFIG_SPIFLASH)
/*
* env, so we got 0x110000.
*/
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
+#endif
+
+#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_QE_FW_ADDR 0x130000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
+#endif
#endif
+
+
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#endif
#ifdef CONFIG_FMAN_ENET
+#ifdef CONFIG_T1040RDB
+#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
+#endif
#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
*/
#include <config_cmd_default.h>
+#ifdef CONFIG_T1042RDB_PI
#define CONFIG_CMD_DATE
+#endif
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_ERRATA
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
+ "spi0=spife110000.0"
+#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
+ "128k(dtb),96m(fs),-(user);"\
+ "fff800000.flash:2m(uboot),9m(kernel),"\
+ "128k(dtb),96m(fs),-(user);spife110000.0:" \
+ "2m(uboot),9m(kernel),128k(dtb),-(user)"
+#endif
+
/*
* Environment Configuration
*/
#define __USB_PHY_TYPE utmi
+#ifdef CONFIG_T1040RDB
+#define FDTFILE "t1040rdb/t1040rdb.dtb"
+#define RAMDISKFILE "t1040rdb/ramdisk.uboot"
+#elif CONFIG_T1042RDB_PI
+#define FDTFILE "t1040rdb_pi/t1040rdb_pi.dtb"
+#define RAMDISKFILE "t1040rdb_pi/ramdisk.uboot"
+#endif
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
"cmp.b $loadaddr $ubootaddr $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
- "ramdiskfile=t1040rdb_pi/ramdisk.uboot\0" \
+ "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
"fdtaddr=c00000\0" \
- "fdtfile=t1040rdb_pi/t1040rdb_pi.dtb\0" \
+ "fdtfile=" __stringify(FDTFILE) "\0" \
"bdev=sda3\0" \
"c=ffe\0"
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
#if defined(CONFIG_PPC_T2080)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
#elif defined(CONFIG_PPC_T2081)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
#endif
+
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
+#define CONFIG_SPL_PAD_TO 0x40000
+#define CONFIG_SPL_MAX_SIZE 0x28000
+#define RESET_VECTOR_OFFSET 0x27FFC
+#define BOOT_PAGE_OFFSET 0x27000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
+#define CONFIG_SPL_SPI_BOOT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
+#endif /* CONFIG_RAMBOOT_PBL */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#ifdef CONFIG_SYS_NO_FLASH
-#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-#else
+#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (512 * 1658)
+#define CONFIG_ENV_OFFSET (512 * 0x800)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CONFIG_SYS_L3_SIZE (512 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
#endif
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
#if defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/*
*/
#ifdef CONFIG_SPI_FLASH
#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_SPI_FLASH_STMICRO
-#if defined(CONFIG_T2080QDS)
-#define CONFIG_SPI_FLASH_SPANSION
-#elif defined(CONFIG_T2081QDS)
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SPI_FLASH_SST
#define CONFIG_SPI_FLASH_EON
#endif
#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
#endif
* env, so we got 0x110000.
*/
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
* master LAW->the ucode address in master's memory space.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
+#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#define CONFIG_DOS_PARTITION
#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
+ "spi0=spife110000.0"
+#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
+ "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
+ "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
+ "1m(uboot),5m(kernel),128k(dtb),-(user)"
+#endif
+
/*
* Environment
*/
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
+
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
+#define CONFIG_SPL_PAD_TO 0x40000
+#define CONFIG_SPL_MAX_SIZE 0x28000
+#define RESET_VECTOR_OFFSET 0x27FFC
+#define BOOT_PAGE_OFFSET 0x27000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
+#define CONFIG_SPL_SPI_BOOT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
+#endif /* CONFIG_RAMBOOT_PBL */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#ifdef CONFIG_SYS_NO_FLASH
-#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-#else
+#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (512 * 1658)
+#define CONFIG_ENV_OFFSET (512 * 0x800)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CONFIG_SYS_L3_SIZE (512 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/*
* DDR Setup
#define CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/*
* env, so we got 0x110000.
*/
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#define CONFIG_CORTINA_FW_ADDR 0x120000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
-#define CONFIG_CORTINA_FW_ADDR (512 * 1808)
+#define CONFIG_SYS_CORTINA_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
+#define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#define CONFIG_CORTINA_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_CORTINA_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
* master LAW->the ucode address in master's memory space.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
+#define CONFIG_SYS_CORTINA_FW_IN_REMOTE
+#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#define CONFIG_CORTINA_FW_ADDR 0xFFE10000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
+#define CONFIG_SYS_CORTINA_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#define CONFIG_CORTINA_FW_ADDR 0xEFE00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_DOS_PARTITION
#endif
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
+ "spi0=spife110000.1"
+#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
+ "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
+ "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \
+ "1m(uboot),5m(kernel),128k(dtb),-(user)"
+#endif
+
/*
* Environment
*/
#define CONFIG_SYS_INTERLAKEN
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg
+#if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#else
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
+#define CONFIG_SPL_PAD_TO 0x40000
+#define CONFIG_SPL_MAX_SIZE 0x28000
+#define RESET_VECTOR_OFFSET 0x27FFC
+#define BOOT_PAGE_OFFSET 0x27000
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
+#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+
#endif
+#endif /* CONFIG_RAMBOOT_PBL */
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (512 * 1658)
+#define CONFIG_ENV_OFFSET (512 * 0x800)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
#endif
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
#if defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_SYS_RAMBOOT
* env, so we got 0x110000.
*/
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
* master LAW->the ucode address in master's memory space.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
+#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port - controlled on board with jumper J8
* env, so we got 0x110000.
*/
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
* 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
* master LAW->the ucode address in master's memory space.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
+#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
+#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
/* at end of uboot partition, before env */
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xF00B0000
+#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000
/*
* System IO Config
* ucode is stored after env, so we got 0x120000.
*/
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x120000
+#define CONFIG_SYS_FMAN_FW_ADDR 0x120000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
#define CONFIG_SYS_CPLD_BASE 0xffa00000
#ifdef CONFIG_QE
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000
+#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#endif /* CONFIG_QE */
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)/* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#ifdef CONFIG_QE
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000
+#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#endif /* CONFIG_QE */
--- /dev/null
+/*
+ * Copyright 2011-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Corenet DS style board configuration file
+ */
+#ifndef __QEMU_PPCE500_H
+#define __QEMU_PPCE500_H
+
+#define CONFIG_CMD_REGINFO
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_QEMU_E500
+
+#undef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */
+
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+
+#define CONFIG_SYS_RAMBOOT
+
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCI1 1 /* PCI controller 1 */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/* Needed to fill the ccsrbar pointer */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Virtual address to CCSRBAR */
+#define CONFIG_SYS_CCSRBAR 0xe0000000
+/* Physical address should be a function call */
+#ifndef __ASSEMBLY__
+extern unsigned long long get_phys_ccsrbar_addr_early(void);
+#endif
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+
+/* Virtual address range for PCI region maps */
+#define CONFIG_SYS_PCI_MAP_START 0x80000000
+#define CONFIG_SYS_PCI_MAP_END 0xe8000000
+
+/* Virtual address to a temporary map if we need it (max 128MB) */
+#define CONFIG_SYS_TMPVIRT 0xe8000000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_CHIP_SELECTS_PER_CTRL 0
+
+#define CONFIG_SYS_CLK_FREQ 33000000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_BOOT_BLOCK 0x00000000 /* boot TLB */
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x00100000
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+#define CONFIG_LBA48
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_SIZE 0x2000
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_BOOTCOMMAND \
+ "test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0"
+
+#endif /* __QEMU_PPCE500_H */
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CONFIG_SYS_L3_SIZE (512 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_R
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* Serial Port - controlled on board with jumper J8
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
} ddr3_spd_eeprom_t;
+/* From JEEC Standard No. 21-C release 23A */
+struct ddr4_spd_eeprom_s {
+ /* General Section: Bytes 0-127 */
+ uint8_t info_size_crc; /* 0 # bytes */
+ uint8_t spd_rev; /* 1 Total # bytes of SPD */
+ uint8_t mem_type; /* 2 Key Byte / mem type */
+ uint8_t module_type; /* 3 Key Byte / Module Type */
+ uint8_t density_banks; /* 4 Density and Banks */
+ uint8_t addressing; /* 5 Addressing */
+ uint8_t package_type; /* 6 Package type */
+ uint8_t opt_feature; /* 7 Optional features */
+ uint8_t thermal_ref; /* 8 Thermal and refresh */
+ uint8_t oth_opt_features; /* 9 Other optional features */
+ uint8_t res_10; /* 10 Reserved */
+ uint8_t module_vdd; /* 11 Module nominal voltage */
+ uint8_t organization; /* 12 Module Organization */
+ uint8_t bus_width; /* 13 Module Memory Bus Width */
+ uint8_t therm_sensor; /* 14 Module Thermal Sensor */
+ uint8_t ext_type; /* 15 Extended module type */
+ uint8_t res_16;
+ uint8_t timebases; /* 17 MTb and FTB */
+ uint8_t tck_min; /* 18 tCKAVGmin */
+ uint8_t tck_max; /* 19 TCKAVGmax */
+ uint8_t caslat_b1; /* 20 CAS latencies, 1st byte */
+ uint8_t caslat_b2; /* 21 CAS latencies, 2nd byte */
+ uint8_t caslat_b3; /* 22 CAS latencies, 3rd byte */
+ uint8_t caslat_b4; /* 23 CAS latencies, 4th byte */
+ uint8_t taa_min; /* 24 Min CAS Latency Time */
+ uint8_t trcd_min; /* 25 Min RAS# to CAS# Delay Time */
+ uint8_t trp_min; /* 26 Min Row Precharge Delay Time */
+ uint8_t tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */
+ uint8_t tras_min_lsb; /* 28 tRASmin, lsb */
+ uint8_t trc_min_lsb; /* 29 tRCmin, lsb */
+ uint8_t trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */
+ uint8_t trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */
+ uint8_t trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */
+ uint8_t trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */
+ uint8_t trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */
+ uint8_t trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */
+ uint8_t tfaw_msb; /* 36 Upper Nibble for tFAW */
+ uint8_t tfaw_min; /* 37 tFAW, lsb */
+ uint8_t trrds_min; /* 38 tRRD_Smin, MTB */
+ uint8_t trrdl_min; /* 39 tRRD_Lmin, MTB */
+ uint8_t tccdl_min; /* 40 tCCS_Lmin, MTB */
+ uint8_t res_41[60-41]; /* 41 Rserved */
+ uint8_t mapping[78-60]; /* 60~77 Connector to SDRAM bit map */
+ uint8_t res_78[117-78]; /* 78~116, Reserved */
+ int8_t fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */
+ int8_t fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */
+ int8_t fine_trrds_min; /* 119 Fine offset for tRRD_Smin */
+ int8_t fine_trc_min; /* 120 Fine offset for tRCmin */
+ int8_t fine_trp_min; /* 121 Fine offset for tRPmin */
+ int8_t fine_trcd_min; /* 122 Fine offset for tRCDmin */
+ int8_t fine_taa_min; /* 123 Fine offset for tAAmin */
+ int8_t fine_tck_max; /* 124 Fine offset for tCKAVGmax */
+ int8_t fine_tck_min; /* 125 Fine offset for tCKAVGmin */
+ /* CRC: Bytes 126-127 */
+ uint8_t crc[2]; /* 126-127 SPD CRC */
+
+ /* Module-Specific Section: Bytes 128-255 */
+ union {
+ struct {
+ /* 128 (Unbuffered) Module Nominal Height */
+ uint8_t mod_height;
+ /* 129 (Unbuffered) Module Maximum Thickness */
+ uint8_t mod_thickness;
+ /* 130 (Unbuffered) Reference Raw Card Used */
+ uint8_t ref_raw_card;
+ /* 131 (Unbuffered) Address Mapping from
+ Edge Connector to DRAM */
+ uint8_t addr_mapping;
+ /* 132~253 (Unbuffered) Reserved */
+ uint8_t res_132[254-132];
+ /* 254~255 CRC */
+ uint8_t crc[2];
+ } unbuffered;
+ struct {
+ /* 128 (Registered) Module Nominal Height */
+ uint8_t mod_height;
+ /* 129 (Registered) Module Maximum Thickness */
+ uint8_t mod_thickness;
+ /* 130 (Registered) Reference Raw Card Used */
+ uint8_t ref_raw_card;
+ /* 131 DIMM Module Attributes */
+ uint8_t modu_attr;
+ /* 132 RDIMM Thermal Heat Spreader Solution */
+ uint8_t thermal;
+ /* 133 Register Manufacturer ID Code, LSB */
+ uint8_t reg_id_lo;
+ /* 134 Register Manufacturer ID Code, MSB */
+ uint8_t reg_id_hi;
+ /* 135 Register Revision Number */
+ uint8_t reg_rev;
+ /* 136 Address mapping from register to DRAM */
+ uint8_t reg_map;
+ /* 137~253 Reserved */
+ uint8_t res_137[254-137];
+ /* 254~255 CRC */
+ uint8_t crc[2];
+ } registered;
+ struct {
+ /* 128 (Loadreduced) Module Nominal Height */
+ uint8_t mod_height;
+ /* 129 (Loadreduced) Module Maximum Thickness */
+ uint8_t mod_thickness;
+ /* 130 (Loadreduced) Reference Raw Card Used */
+ uint8_t ref_raw_card;
+ /* 131 DIMM Module Attributes */
+ uint8_t modu_attr;
+ /* 132 RDIMM Thermal Heat Spreader Solution */
+ uint8_t thermal;
+ /* 133 Register Manufacturer ID Code, LSB */
+ uint8_t reg_id_lo;
+ /* 134 Register Manufacturer ID Code, MSB */
+ uint8_t reg_id_hi;
+ /* 135 Register Revision Number */
+ uint8_t reg_rev;
+ /* 136 Address mapping from register to DRAM */
+ uint8_t reg_map;
+ /* 137 Register Output Drive Strength for CMD/Add*/
+ uint8_t reg_drv;
+ /* 138 Register Output Drive Strength for CK */
+ uint8_t reg_drv_ck;
+ /* 139 Data Buffer Revision Number */
+ uint8_t data_buf_rev;
+ /* 140 DRAM VrefDQ for Package Rank 0 */
+ uint8_t vrefqe_r0;
+ /* 141 DRAM VrefDQ for Package Rank 1 */
+ uint8_t vrefqe_r1;
+ /* 142 DRAM VrefDQ for Package Rank 2 */
+ uint8_t vrefqe_r2;
+ /* 143 DRAM VrefDQ for Package Rank 3 */
+ uint8_t vrefqe_r3;
+ /* 144 Data Buffer VrefDQ for DRAM Interface */
+ uint8_t data_intf;
+ /*
+ * 145 Data Buffer MDQ Drive Strength and RTT
+ * for data rate <= 1866
+ */
+ uint8_t data_drv_1866;
+ /*
+ * 146 Data Buffer MDQ Drive Strength and RTT
+ * for 1866 < data rate <= 2400
+ */
+ uint8_t data_drv_2400;
+ /*
+ * 147 Data Buffer MDQ Drive Strength and RTT
+ * for 2400 < data rate <= 3200
+ */
+ uint8_t data_drv_3200;
+ /* 148 DRAM Drive Strength */
+ uint8_t dram_drv;
+ /*
+ * 149 DRAM ODT (RTT_WR, RTT_NOM)
+ * for data rate <= 1866
+ */
+ uint8_t dram_odt_1866;
+ /*
+ * 150 DRAM ODT (RTT_WR, RTT_NOM)
+ * for 1866 < data rate <= 2400
+ */
+ uint8_t dram_odt_2400;
+ /*
+ * 151 DRAM ODT (RTT_WR, RTT_NOM)
+ * for 2400 < data rate <= 3200
+ */
+ uint8_t dram_odt_3200;
+ /*
+ * 152 DRAM ODT (RTT_PARK)
+ * for data rate <= 1866
+ */
+ uint8_t dram_odt_park_1866;
+ /*
+ * 153 DRAM ODT (RTT_PARK)
+ * for 1866 < data rate <= 2400
+ */
+ uint8_t dram_odt_park_2400;
+ /*
+ * 154 DRAM ODT (RTT_PARK)
+ * for 2400 < data rate <= 3200
+ */
+ uint8_t dram_odt_park_3200;
+ uint8_t res_155[254-155]; /* Reserved */
+ /* 254~255 CRC */
+ uint8_t crc[2];
+ } loadreduced;
+ uint8_t uc[128]; /* 128-255 Module-Specific Section */
+ } mod_section;
+
+ uint8_t res_256[320-256]; /* 256~319 Reserved */
+
+ /* Module supplier's data: Byte 320~383 */
+ uint8_t mmid_lsb; /* 320 Module MfgID Code LSB */
+ uint8_t mmid_msb; /* 321 Module MfgID Code MSB */
+ uint8_t mloc; /* 322 Mfg Location */
+ uint8_t mdate[2]; /* 323~324 Mfg Date */
+ uint8_t sernum[4]; /* 325~328 Module Serial Number */
+ uint8_t mpart[20]; /* 329~348 Mfg's Module Part Number */
+ uint8_t mrev; /* 349 Module Revision Code */
+ uint8_t dmid_lsb; /* 350 DRAM MfgID Code LSB */
+ uint8_t dmid_msb; /* 351 DRAM MfgID Code MSB */
+ uint8_t stepping; /* 352 DRAM stepping */
+ uint8_t msd[29]; /* 353~381 Mfg's Specific Data */
+ uint8_t res_382[2]; /* 382~383 Reserved */
+
+ uint8_t user[512-384]; /* 384~511 End User Programmable */
+};
+
extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd);
extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd);
extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd);
extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd);
extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
+unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd);
/*
* Byte 2 Fundamental Memory Types.
#define SPD_MEMTYPE_DDR2_FBDIMM (0x09)
#define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A)
#define SPD_MEMTYPE_DDR3 (0x0B)
+#define SPD_MEMTYPE_DDR4 (0x0C)
/* DIMM Type for DDR2 SPD (according to v1.3) */
#define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00)
#define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C)
#define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D)
+/* DIMM Type for DDR4 SPD */
+#define DDR4_SPD_MODULETYPE_MASK (0x0f)
+#define DDR4_SPD_MODULETYPE_EXT (0x00)
+#define DDR4_SPD_MODULETYPE_RDIMM (0x01)
+#define DDR4_SPD_MODULETYPE_UDIMM (0x02)
+#define DDR4_SPD_MODULETYPE_SO_DIMM (0x03)
+#define DDR4_SPD_MODULETYPE_LRDIMM (0x04)
+#define DDR4_SPD_MODULETYPE_MINI_RDIMM (0x05)
+#define DDR4_SPD_MODULETYPE_MINI_UDIMM (0x06)
+#define DDR4_SPD_MODULETYPE_72B_SO_UDIMM (0x08)
+#define DDR4_SPD_MODULETYPE_72B_SO_RDIMM (0x09)
+#define DDR4_SPD_MODULETYPE_16B_SO_DIMM (0x0C)
+#define DDR4_SPD_MODULETYPE_32B_SO_DIMM (0x0D)
+
#endif /* _DDR_SPD_H_ */
#ifdef CONFIG_SYS_DPAA_PME
unsigned long freq_pme;
#endif
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+ unsigned char diff_sysclk;
+#endif
} MPC85xx_SYS_INFO;
#endif /* _ASMLANGUAGE */
#include <libfdt.h>
+u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell,
+ const char *prop, const u32 dflt);
u32 fdt_getprop_u32_default(const void *fdt, const char *path,
const char *prop, const u32 dflt);
int fdt_chosen(void *fdt, int force);
int fdt_verify_alias_address(void *fdt, int anode, const char *alias,
u64 addr);
u64 fdt_get_base_address(void *fdt, int node);
+int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr,
+ uint64_t *addr, uint64_t *len);
enum fdt_status {
FDT_STATUS_OKAY,
/*
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
#ifndef FSL_DDR_MAIN_H
#define FSL_DDR_MAIN_H
+#include <fsl_ddrc_version.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#define ddr_out32(a, v) out_be32(a, v)
#endif
+#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
+
+u32 fsl_ddr_get_version(void);
+
#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
/*
* Bind the main DDR setup driver's generic names
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
#define EDC_ECC 2
#define EDC_AC_PARITY 4
-/* Parameters for a DDR2 dimm computed from the SPD */
+/* Parameters for a DDR dimm computed from the SPD */
typedef struct dimm_params_s {
/* DIMM organization parameters */
unsigned int n_row_addr;
unsigned int n_col_addr;
unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
+#ifdef CONFIG_SYS_FSL_DDR4
+ unsigned int bank_addr_bits;
+ unsigned int bank_group_bits;
+#else
unsigned int n_banks_per_sdram_device;
+#endif
unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
unsigned int row_density;
/* DIMM timing parameters */
- unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */
- unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */
- unsigned int taa_ps; /* minimum CAS latency time, only for ddr3 */
- unsigned int tfaw_ps; /* four active window delay, only for ddr3 */
+ int mtb_ps; /* medium timebase ps */
+ int ftb_10th_ps; /* fine timebase, in 1/10 ps */
+ int taa_ps; /* minimum CAS latency time */
+ int tfaw_ps; /* four active window delay */
/*
* SDRAM clock periods
* The range for these are 1000-10000 so a short should be sufficient
*/
- unsigned int tckmin_x_ps;
- unsigned int tckmin_x_minus_1_ps;
- unsigned int tckmin_x_minus_2_ps;
- unsigned int tckmax_ps;
+ int tckmin_x_ps;
+ int tckmin_x_minus_1_ps;
+ int tckmin_x_minus_2_ps;
+ int tckmax_ps;
/* SPD-defined CAS latencies */
unsigned int caslat_x;
unsigned int caslat_lowest_derated; /* Derated CAS latency */
/* basic timing parameters */
- unsigned int trcd_ps;
- unsigned int trp_ps;
- unsigned int tras_ps;
-
- unsigned int twr_ps; /* maximum = 63750 ps */
- unsigned int twtr_ps; /* maximum = 63750 ps */
- unsigned int trfc_ps; /* max = 255 ns + 256 ns + .75 ns
+ int trcd_ps;
+ int trp_ps;
+ int tras_ps;
+
+#ifdef CONFIG_SYS_FSL_DDR4
+ int trfc1_ps;
+ int trfc2_ps;
+ int trfc4_ps;
+ int trrds_ps;
+ int trrdl_ps;
+ int tccdl_ps;
+#else
+ int twr_ps; /* maximum = 63750 ps */
+ int trfc_ps; /* max = 255 ns + 256 ns + .75 ns
= 511750 ps */
+ int trrd_ps; /* maximum = 63750 ps */
+ int twtr_ps; /* maximum = 63750 ps */
+ int trtp_ps; /* byte 38, spd->trtp */
+#endif
- unsigned int trrd_ps; /* maximum = 63750 ps */
- unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
+ int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
- unsigned int refresh_rate_ps;
- unsigned int extended_op_srt;
+ int refresh_rate_ps;
+ int extended_op_srt;
- /* DDR3 doesn't need these as below */
- unsigned int tis_ps; /* byte 32, spd->ca_setup */
- unsigned int tih_ps; /* byte 33, spd->ca_hold */
- unsigned int tds_ps; /* byte 34, spd->data_setup */
- unsigned int tdh_ps; /* byte 35, spd->data_hold */
- unsigned int trtp_ps; /* byte 38, spd->trtp */
- unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */
- unsigned int tqhs_ps; /* byte 45, spd->tqhs */
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
+ int tis_ps; /* byte 32, spd->ca_setup */
+ int tih_ps; /* byte 33, spd->ca_hold */
+ int tds_ps; /* byte 34, spd->data_setup */
+ int tdh_ps; /* byte 35, spd->data_hold */
+ int tdqsq_max_ps; /* byte 44, spd->tdqsq */
+ int tqhs_ps; /* byte 45, spd->tqhs */
+#endif
/* DDR3 RDIMM */
unsigned char rcw[16]; /* Register Control Word 0-15 */
+#ifdef CONFIG_SYS_FSL_DDR4
+ unsigned int dq_mapping[18];
+ unsigned int dq_mapping_ors;
+#endif
} dimm_params_t;
extern unsigned int ddr_compute_dimm_parameters(
/*
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Pick a basic DDR Technology.
*/
#include <ddr_spd.h>
+#include <fsl_ddrc_version.h>
-#define SDRAM_TYPE_DDR1 2
-#define SDRAM_TYPE_DDR2 3
-#define SDRAM_TYPE_LPDDR1 6
-#define SDRAM_TYPE_DDR3 7
+#define SDRAM_TYPE_DDR1 2
+#define SDRAM_TYPE_DDR2 3
+#define SDRAM_TYPE_LPDDR1 6
+#define SDRAM_TYPE_DDR3 7
+#define SDRAM_TYPE_DDR4 5
#define DDR_BL4 4 /* burst length 4 */
#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
#endif
+#elif defined(CONFIG_SYS_FSL_DDR4)
+#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
+typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4
+#endif
#endif /* #if defined(CONFIG_SYS_FSL_DDR1) */
#define FSL_DDR_ODT_NEVER 0x0
#define TIMING_CFG_2_CPO_MASK 0x0F800000
-#if defined(CONFIG_P4080)
+#if defined(CONFIG_SYS_FSL_DDR_VER) && \
+ (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4)
#define RD_TO_PRE_MASK 0xf
#define RD_TO_PRE_SHIFT 13
#define WR_DATA_DELAY_MASK 0xf
#define DDR_CDR2_ODT_MASK 0x1
#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
+#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
+#ifdef CONFIG_SYS_FSL_DDR3L
+#define DDR_CDR_ODT_OFF 0x0
+#define DDR_CDR_ODT_120ohm 0x1
+#define DDR_CDR_ODT_200ohm 0x2
+#define DDR_CDR_ODT_75ohm 0x3
+#define DDR_CDR_ODT_60ohm 0x5
+#define DDR_CDR_ODT_46ohm 0x7
+#elif defined(CONFIG_SYS_FSL_DDR4)
+#define DDR_CDR_ODT_OFF 0x0
+#define DDR_CDR_ODT_100ohm 0x1
+#define DDR_CDR_ODT_120OHM 0x2
+#define DDR_CDR_ODT_80ohm 0x3
+#define DDR_CDR_ODT_60ohm 0x4
+#define DDR_CDR_ODT_40ohm 0x5
+#define DDR_CDR_ODT_50ohm 0x6
+#define DDR_CDR_ODT_30ohm 0x7
+#else
#define DDR_CDR_ODT_OFF 0x0
#define DDR_CDR_ODT_120ohm 0x1
#define DDR_CDR_ODT_180ohm 0x2
#define DDR_CDR_ODT_60hm 0x5
#define DDR_CDR_ODT_70ohm 0x6
#define DDR_CDR_ODT_47ohm 0x7
+#endif /* DDR3L */
#else
#define DDR_CDR_ODT_75ohm 0x0
#define DDR_CDR_ODT_55ohm 0x1
unsigned int timing_cfg_2;
unsigned int ddr_sdram_cfg;
unsigned int ddr_sdram_cfg_2;
+ unsigned int ddr_sdram_cfg_3;
unsigned int ddr_sdram_mode;
unsigned int ddr_sdram_mode_2;
unsigned int ddr_sdram_mode_3;
unsigned int ddr_sdram_mode_6;
unsigned int ddr_sdram_mode_7;
unsigned int ddr_sdram_mode_8;
+ unsigned int ddr_sdram_mode_9;
+ unsigned int ddr_sdram_mode_10;
+ unsigned int ddr_sdram_mode_11;
+ unsigned int ddr_sdram_mode_12;
+ unsigned int ddr_sdram_mode_13;
+ unsigned int ddr_sdram_mode_14;
+ unsigned int ddr_sdram_mode_15;
+ unsigned int ddr_sdram_mode_16;
unsigned int ddr_sdram_md_cntl;
unsigned int ddr_sdram_interval;
unsigned int ddr_data_init;
unsigned int ddr_init_ext_addr;
unsigned int timing_cfg_4;
unsigned int timing_cfg_5;
+ unsigned int timing_cfg_6;
+ unsigned int timing_cfg_7;
+ unsigned int timing_cfg_8;
+ unsigned int timing_cfg_9;
unsigned int ddr_zq_cntl;
unsigned int ddr_wrlvl_cntl;
unsigned int ddr_wrlvl_cntl_2;
unsigned int ddr_sr_cntr;
unsigned int ddr_sdram_rcw_1;
unsigned int ddr_sdram_rcw_2;
+ unsigned int ddr_sdram_rcw_3;
+ unsigned int ddr_sdram_rcw_4;
+ unsigned int ddr_sdram_rcw_5;
+ unsigned int ddr_sdram_rcw_6;
+ unsigned int dq_map_0;
+ unsigned int dq_map_1;
+ unsigned int dq_map_2;
+ unsigned int dq_map_3;
unsigned int ddr_eor;
unsigned int ddr_cdr1;
unsigned int ddr_cdr2;
unsigned int all_dimms_burst_lengths_bitmask;
unsigned int all_dimms_registered;
unsigned int all_dimms_unbuffered;
- /* unsigned int lowest_common_SPD_caslat; */
+ /* unsigned int lowest_common_spd_caslat; */
unsigned int all_dimms_minimum_trcd_ps;
} memctl_options_partial_t;
int board_need_mem_reset(void)
__attribute__((weak, alias("__board_need_mem_reset")));
+void __weak board_mem_sleep_setup(void)
+{
+}
+
/*
* The 85xx boards have a common prototype for fixed_sdram so put the
* declaration here.
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_DDRC_VER_H
+#define __FSL_DDRC_VER_H
+
+/*
+ * Only the versions with distinct features or registers are listed here.
+ */
+#define FSL_DDR_VER_4_4 44
+#define FSL_DDR_VER_4_6 46
+#define FSL_DDR_VER_4_7 47
+#define FSL_DDR_VER_5_0 50
+
+#endif /* __FSL_DDRC_VER_H */
static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
#endif /* CONFIG_FSL_ESDHC */
void __noreturn mmc_boot(void);
+void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
#endif /* __FSL_ESDHC_H__ */
extern void print_ifc_regs(void);
extern void init_early_memctl_regs(void);
+void init_final_memctl_regs(void);
#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
/*
* Common internal memory map for some Freescale SoCs
*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
u8 res_150[16];
u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
- u8 reg_168[8];
+ u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */
+ u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */
u32 ddr_zq_cntl; /* ZQ calibration control*/
u32 ddr_wrlvl_cntl; /* write leveling control*/
u8 reg_178[4];
u8 reg_188[8];
u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
- u8 res_198[104];
+ u8 res_198[0x1a0-0x198];
+ u32 ddr_sdram_rcw_3;
+ u32 ddr_sdram_rcw_4;
+ u32 ddr_sdram_rcw_5;
+ u32 ddr_sdram_rcw_6;
+ u8 res_1b0[0x200-0x1b0];
u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
- u8 res_218[0x908];
+ u8 res_218[0x220-0x218];
+ u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */
+ u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */
+ u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */
+ u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */
+ u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */
+ u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */
+ u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */
+ u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */
+ u8 res_240[0x250-0x240];
+ u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */
+ u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */
+ u8 res_258[0x260-0x258];
+ u32 sdram_cfg_3;
+ u8 res_264[0x2a0-0x264];
+ u32 deskew_cntl;
+ u8 res_2a4[0x400-0x2a4];
+ u32 dq_map_0;
+ u32 dq_map_1;
+ u32 dq_map_2;
+ u32 dq_map_3;
+ u8 res_410[0xb20-0x410];
u32 ddr_dsr1; /* Debug Status 1 */
u32 ddr_dsr2; /* Debug Status 2 */
u32 ddr_cdr1; /* Control Driver 1 */
#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16)
+#define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20)
+#endif
#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
}
void spi_boot(void) __noreturn;
+void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
#endif /* _SPI_FLASH_H_ */
#define CONFIG_SYS_FSL_USB2_ADDR 0
#endif
+/*
+ * Increasing TX FIFO threshold value from 2 to 4 decreases
+ * data burst rate with which data packets are posted from the TX
+ * latency FIFO to compensate for latencies in DDR pipeline during DMA
+ */
+#define TXFIFOTHRESH 4
+
/*
* USB Registers
*/
@rm -f $@
ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-$(obj)/fixed_ivor.S:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
-
-$(obj)/start.S: $(obj)/fixed_ivor.S
+$(obj)/start.S:
@rm -f $@
ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
@rm -f $@
ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-$(obj)/fixed_ivor.S:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
-
-$(obj)/start.S: $(obj)/fixed_ivor.S
+$(obj)/start.S:
@rm -f $@
ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
@rm -f $@
ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-$(obj)/fixed_ivor.S:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
-
-$(obj)/start.S: $(obj)/fixed_ivor.S
+$(obj)/start.S:
@rm -f $@
ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
@rm -f $@
ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-$(obj)/fixed_ivor.S:
- @rm -f $@
- ln -sf $(srctree)/$(CPUDIR)/fixed_ivor.S $@
-
-$(obj)/start.S: $(obj)/fixed_ivor.S
+$(obj)/start.S:
@rm -f $@
ln -sf $(srctree)/$(CPUDIR)/start.S $@
@rm -f $@
ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-$(obj)/fixed_ivor.S:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
-
-$(obj)/start.S: $(obj)/fixed_ivor.S
+$(obj)/start.S:
@rm -f $@
ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
projects / karo-tx-uboot.git / commitdiff