ColdFire: Add Freescale MCF54418TWR ColdFire development board support

Add Freescale MCF54418TWR ColdFire development board support.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>

diff --git a/board/freescale/m54418twr/Makefile b/board/freescale/m54418twr/Makefile
new file mode 100644 (file)
index 0000000..1e53f48
--- /dev/null
+++ b/board/freescale/m54418twr/Makefile
@@ -0,0 +1,43 @@
+# Copyright 2010-2012 Freescale Semiconductor, Inc.
+# TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  = $(BOARD).o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

diff --git a/board/freescale/m54418twr/config.mk b/board/freescale/m54418twr/config.mk
new file mode 100644 (file)
index 0000000..a592335
--- /dev/null
+++ b/board/freescale/m54418twr/config.mk
@@ -0,0 +1,25 @@
+# Copyright 2010-2012 Freescale Semiconductor, Inc.
+# TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(CONFIG_SYS_TEXT_BASE)

diff --git a/board/freescale/m54418twr/m54418twr.c b/board/freescale/m54418twr/m54418twr.c
new file mode 100644 (file)
index 0000000..6e57bef
--- /dev/null
+++ b/board/freescale/m54418twr/m54418twr.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+       /*
+        * need to to:
+        * Check serial flash size. if 2mb evb, else 8mb demo
+        */
+       puts("Board: ");
+       puts("Freescale MCF54418 Tower System\n");
+       return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+       u32 dramsize;
+
+#if defined(CONFIG_SERIAL_BOOT)
+       /*
+        * Serial Boot: The dram is already initialized in start.S
+        * only require to return DRAM size
+        */
+       dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+#else
+       sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+       ccm_t *ccm = (ccm_t *)MMAP_CCM;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       pm_t *pm = (pm_t *) MMAP_PM;
+       u32 i;
+
+       dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+       for (i = 0x13; i < 0x20; i++) {
+               if (dramsize == (1 << i))
+                       break;
+       }
+
+       out_8(&pm->pmcr0, 0x2E);
+       out_8(&gpio->mscr_sdram, 1);
+
+       clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF);
+       setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK);
+
+       out_be32(&sdram->rcrcr, 0x40000000);
+       out_be32(&sdram->padcr, 0x01030203);
+
+       out_be32(&sdram->cr00, 0x01010101);
+       out_be32(&sdram->cr01, 0x00000101);
+       out_be32(&sdram->cr02, 0x01010100);
+       out_be32(&sdram->cr03, 0x01010000);
+       out_be32(&sdram->cr04, 0x00010101);
+       out_be32(&sdram->cr06, 0x00010100);
+       out_be32(&sdram->cr07, 0x00000001);
+       out_be32(&sdram->cr08, 0x01000001);
+       out_be32(&sdram->cr09, 0x00000100);
+       out_be32(&sdram->cr10, 0x00010001);
+       out_be32(&sdram->cr11, 0x00000200);
+       out_be32(&sdram->cr12, 0x01000002);
+       out_be32(&sdram->cr13, 0x00000000);
+       out_be32(&sdram->cr14, 0x00000100);
+       out_be32(&sdram->cr15, 0x02000100);
+       out_be32(&sdram->cr16, 0x02000407);
+       out_be32(&sdram->cr17, 0x02030007);
+       out_be32(&sdram->cr18, 0x02000100);
+       out_be32(&sdram->cr19, 0x0A030203);
+       out_be32(&sdram->cr20, 0x00020708);
+       out_be32(&sdram->cr21, 0x00050008);
+       out_be32(&sdram->cr22, 0x04030002);
+       out_be32(&sdram->cr23, 0x00000004);
+       out_be32(&sdram->cr24, 0x020A0000);
+       out_be32(&sdram->cr25, 0x0C00000E);
+       out_be32(&sdram->cr26, 0x00002004);
+       out_be32(&sdram->cr28, 0x00100010);
+       out_be32(&sdram->cr29, 0x00100010);
+       out_be32(&sdram->cr31, 0x07990000);
+       out_be32(&sdram->cr40, 0x00000000);
+       out_be32(&sdram->cr41, 0x00C80064);
+       out_be32(&sdram->cr42, 0x44520002);
+       out_be32(&sdram->cr43, 0x00C80023);
+       out_be32(&sdram->cr45, 0x0000C350);
+       out_be32(&sdram->cr56, 0x04000000);
+       out_be32(&sdram->cr57, 0x03000304);
+       out_be32(&sdram->cr58, 0x40040000);
+       out_be32(&sdram->cr59, 0xC0004004);
+       out_be32(&sdram->cr60, 0x0642C000);
+       out_be32(&sdram->cr61, 0x00000642);
+       asm("tpf");
+
+       out_be32(&sdram->cr09, 0x01000100);
+
+       udelay(100);
+#endif
+       return dramsize;
+};
+
+int testdram(void)
+{
+       return 0;
+}

diff --git a/board/freescale/m54418twr/u-boot.lds b/board/freescale/m54418twr/u-boot.lds
new file mode 100644 (file)
index 0000000..f341449
--- /dev/null
+++ b/board/freescale/m54418twr/u-boot.lds
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .text      :
+  {
+    arch/m68k/cpu/mcf5445x/start.o             (.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    KEEP(*(.got))
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss  (NOLOAD)     :
+  {
+   _sbss = .;
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  __bss_end__ = . ;
+  PROVIDE (end = .);
+}

diff --git a/boards.cfg b/boards.cfg
index b14a08ff15c9258f18c6fe16c86674089e036c87..4c637890417ff51b7ffb205291b373f8a0cd83ae 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -380,6 +380,12 @@ M53017EVB                    m68k        mcf532x     m53017evb           freesca
 M5329AFEE                    m68k        mcf532x     m5329evb            freescale      -           M5329EVB:NANDFLASH_SIZE=0
 M5329BFEE                    m68k        mcf532x     m5329evb            freescale      -           M5329EVB:NANDFLASH_SIZE=16
 M5373EVB                     m68k        mcf532x     m5373evb            freescale      -           M5373EVB:NANDFLASH_SIZE=16
 M5329AFEE                    m68k        mcf532x     m5329evb            freescale      -           M5329EVB:NANDFLASH_SIZE=0
 M5329BFEE                    m68k        mcf532x     m5329evb            freescale      -           M5329EVB:NANDFLASH_SIZE=16
 M5373EVB                     m68k        mcf532x     m5373evb            freescale      -           M5373EVB:NANDFLASH_SIZE=16

+M54418TWR                    m68k        mcf5445x    m54418twr           freescale      -           M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000
+M54418TWR_nand_mii           m68k        mcf5445x    m54418twr           freescale      -           M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000
+M54418TWR_nand_rmii          m68k        mcf5445x    m54418twr           freescale      -           M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000
+M54418TWR_nand_rmii_lowfreq  m68k        mcf5445x    m54418twr           freescale      -           M54418TWR:SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000
+M54418TWR_serial_mii         m68k        mcf5445x    m54418twr           freescale      -           M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000
+M54418TWR_serial_rmii        m68k        mcf5445x    m54418twr           freescale      -           M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000

 M54451EVB                    m68k        mcf5445x    m54451evb           freescale      -           M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000
 M54451EVB_stmicro            m68k        mcf5445x    m54451evb           freescale      -           M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000
 M54455EVB                    m68k        mcf5445x    m54455evb           freescale      -           M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333
 M54451EVB                    m68k        mcf5445x    m54451evb           freescale      -           M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000
 M54451EVB_stmicro            m68k        mcf5445x    m54451evb           freescale      -           M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000
 M54455EVB                    m68k        mcf5445x    m54455evb           freescale      -           M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333

diff --git a/doc/README.m54418twr b/doc/README.m54418twr
new file mode 100644 (file)
index 0000000..f69ae01
--- /dev/null
+++ b/doc/README.m54418twr
@@ -0,0 +1,244 @@
+Freescale MCF54418TWR ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created Mar 22, 2012
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m54418twr/m54418twr.c        Dram setup
+- board/freescale/m54418twr/Makefile   Makefile
+- board/freescale/m54418twr/config.mk  config make
+- board/freescale/m54418twr/u-boot.lds Linker description
+
+- arch/m68k/cpu/mcf5445x/cpu.c         cpu specific code
+- arch/m68k/cpu/mcf5445x/cpu_init.c    Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
+- arch/m68k/cpu/mcf5445x/interrupts.c  cpu specific interrupt support
+- arch/m68k/cpu/mcf5445x/speed.c       system, pci, flexbus, and cpu clock
+- arch/m68k/cpu/mcf5445x/Makefile      Makefile
+- arch/m68k/cpu/mcf5445x/config.mk     config make
+- arch/m68k/cpu/mcf5445x/start.S       start up assembly code
+
+- doc/README.m54418twr                 This readme file
+
+- drivers/net/mcffec.c                 ColdFire common FEC driver
+- drivers/net/mcfmii.c                 ColdFire common MII driver
+- drivers/serial/mcfuart.c             ColdFire common UART driver
+
+- arch/m68k/include/asm/bitops.h       Bit operation function export
+- arch/m68k/include/asm/byteorder.h    Byte order functions
+- arch/m68k/include/asm/fec.h          FEC structure and definition
+- arch/m68k/include/asm/global_data.h  Global data structure
+- arch/m68k/include/asm/immap.h                ColdFire specific header file and driver macros
+- arch/m68k/include/asm/immap_5441x.h  mcf5441x specific header file
+- arch/m68k/include/asm/io.h           io functions
+- arch/m68k/include/asm/m5441x.h       mcf5441x specific header file
+- arch/m68k/include/asm/posix_types.h  Posix
+- arch/m68k/include/asm/processor.h    header file
+- arch/m68k/include/asm/ptrace.h       Exception structure
+- arch/m68k/include/asm/rtc.h          Realtime clock header file
+- arch/m68k/include/asm/string.h       String function export
+- arch/m68k/include/asm/timer.h                Timer structure and definition
+- arch/m68k/include/asm/types.h                Data types definition
+- arch/m68k/include/asm/uart.h         Uart structure and definition
+- arch/m68k/include/asm/u-boot.h       u-boot structure
+
+- include/configs/M54418TWR.h          Board specific configuration file
+
+- arch/m68k/lib/board.c                        board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts.c           Coldfire common interrupt functions
+- arch/m68k/lib/time.c                 Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c                        Exception init code
+
+1 MCF5441x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M54418TWR Development Board
+CONFIG_MCF5441x                        -- define for all MCF5441x CPUs
+CONFIG_M54418                  -- define for all Freescale MCF54418 CPUs
+CONFIG_M54418TWR               -- define for M54418TWR board
+
+CONFIG_MCFUART                 -- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT           -- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE                        -- define UART baudrate
+
+CONFIG_MCFFEC                  -- define to use common CF FEC driver
+CONFIG_MII                     -- enable to use MII driver
+CONFIG_SYS_DISCOVER_PHY                -- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER       -- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN        --
+CONFIG_SYS_FEC0_PINMUX         -- Set FEC0 Pin configuration
+CONFIG_SYS_FEC1_PINMUX         -- Set FEC1 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE                -- Set FEC0 MII base register
+CONFIG_SYS_FEC1_MIIBASE                -- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP               -- set FEC timeout loop
+CONFIG_HAS_ETH1                        -- define to enable second FEC in u-boot
+
+CONFIG_MCFTMR                  -- define to use DMA timer
+
+CONFIG_SYS_IMMR                        -- define for MBAR offset
+
+CONFIG_EXTRA_CLOCK             -- Enable extra clock such as vco, flexbus, pci, etc
+
+CONFIG_SYS_MBAR                        -- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM       -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR       -- defines the base address of the MCF54455 internal SRAM
+
+CONFIG_SYS_CSn_BASE            -- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK            -- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL            -- defines the Chip Select Control register
+
+CONFIG_SYS_SDRAM_BASE          -- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+       MRAM:           0x00000000-0x0003FFFF (256KB)
+       DDR:            0x40000000-0x47FFFFFF (128MB)
+       SRAM:           0x80000000-0x8000FFFF (64KB)
+       IP:             0xE0000000-0xFFFFFFFF (512MB)
+
+3. COMPILATION
+==============
+3.1    To create U-Boot the gcc-4.x compiler set (ColdFire ELF version)
+from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+   export CROSS_COMPILE=cross-compile-prefix
+   cd u-boot
+   make distclean
+   make M54418TWR_config, or                   - default to spi serial flash boot, 50Mhz input clock
+   make M54418TWR_nand_mii_config, or          - default to nand flash boot, mii mode, 25Mhz input clock
+   make M54418TWR_nand_rmii_config, or         - default to nand flash boot, rmii mode, 50Mhz input clock
+   make M54418TWR_nand_rmii_lowfreq_config, or - default to nand flash boot, rmii mode, 50Mhz input clock
+   make M54418TWR_serial_mii_config, or                - default to spi serial flash boot, 25Mhz input clock
+   make M54418TWR_serial_rmii_config, or       - default to spi serial flash boot, 50Mhz input clock
+   make
+
+4. SCREEN DUMP
+==============
+4.1 M54418TWR Development board
+    Boot from NAND flash (NOTE: May not show exactly the same)
+
+U-Boot 2012.10-00209-g12ae1d8-dirty (Oct 18 2012 - 15:54:54)
+
+CPU:   Freescale MCF54418 (Mask:a3 Version:1)
+       CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 125 MHz
+       INP CLK 50 MHz VCO CLK 500 MHz
+Board: Freescale MCF54418 Tower System
+SPI:   ready
+DRAM:  128 MiB
+NAND:  256 MiB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   FEC0, FEC1
+-> pri
+baudrate=115200
+bootargs=root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(k
+ernel)ro,-(jffs2) console=ttyS0,115200
+bootdelay=2
+eth1addr=00:e0:0c:bc:e5:61
+ethact=FEC0
+ethaddr=00:e0:0c:bc:e5:60
+fileaddr=40010000
+filesize=27354
+gatewayip=192.168.1.1
+hostname=M54418TWR
+inpclk=50000000
+ipaddr=192.168.1.2
+load=tftp ${loadaddr} ${u-boot};
+loadaddr=0x40010000
+mem=129024k
+netdev=eth0
+netmask=255.255.255.0
+prog=nand device 0;nand erase 0 40000;nb_update ${loadaddr} ${filesize};save
+serverip=192.168.1.1
+stderr=serial
+stdin=serial
+stdout=serial
+u-boot=u-boot.bin
+upd=run load; run prog
+
+Environment size: 653/131068 bytes
+-> bdinfo
+memstart    = 0x40000000
+memsize     = 0x08000000
+flashstart  = 0x00000000
+flashsize   = 0x00000000
+flashoffset = 0x00000000
+sramstart   = 0x80000000
+sramsize    = 0x00010000
+mbar        = 0xFC000000
+cpufreq     =    250 MHz
+busfreq     =    125 MHz
+flbfreq     =    125 MHz
+inpfreq     =     50 MHz
+vcofreq     =    500 MHz
+ethaddr     = 00:e0:0c:bc:e5:60
+eth1addr    = 00:e0:0c:bc:e5:61
+ip_addr     = 192.168.1.2
+baudrate    = 115200 bps
+-> help
+?       - alias for 'help'
+base    - print or set address offset
+bdinfo  - print Board Info structure
+boot    - boot default, i.e., run 'bootcmd'
+bootd   - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm   - boot application image from memory
+bootp   - boot image via network using BOOTP/TFTP protocol
+bootvx  - Boot vxWorks from an ELF image
+cmp     - memory compare
+coninfo - print console devices and information
+cp      - memory copy
+crc32   - checksum calculation
+dcache  - enable or disable data cache
+dhcp    - boot image via network using DHCP/TFTP protocol
+echo    - echo args to console
+editenv - edit environment variable
+env     - environment handling commands
+exit    - exit script
+false   - do nothing, unsuccessfully
+go      - start application at address 'addr'
+help    - print command description/usage
+icache  - enable or disable instruction cache
+iminfo  - print header information for application image
+imxtract- extract a part of a multi-image
+itest   - return true/false on integer compare
+loop    - infinite loop on address range
+md      - memory display
+mdio    - MDIO utility commands
+mii     - MII utility commands
+mm      - memory modify (auto-incrementing address)
+mtest   - simple RAM read/write test
+mw      - memory write (fill)
+nand    - NAND sub-system
+nb_update- Nand boot update  program
+nboot   - boot from NAND device
+nfs     - boot image via network using NFS protocol
+nm      - memory modify (constant address)
+ping    - send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+reginfo - print register information
+reset   - Perform RESET of the CPU
+run     - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv  - set environment variables
+sf      - SPI flash sub-system
+showvar - print local hushshell variables
+sleep   - delay execution for some time
+source  - run script from memory
+sspi    - SPI utility command
+test    - minimal test like /bin/sh
+tftpboot- boot image via network using TFTP protocol
+true    - do nothing, successfully
+version - print monitor, compiler and linker version

diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
new file mode 100644 (file)
index 0000000..6c96111
--- /dev/null
+++ b/include/configs/M54418TWR.h
@@ -0,0 +1,448 @@
+/*
+ * Configuation settings for the Freescale MCF54418 TWR board.
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M54418TWR_H
+#define _M54418TWR_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF5441x        /* define processor family */
+#define CONFIG_M54418          /* define processor type */
+#define CONFIG_M54418TWR       /* M54418TWR board */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT           (0)
+#define CONFIG_BAUDRATE                115200
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_TIMESTAMP       /* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_UBI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_NAND_YAFFS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+/*
+ * NAND FLASH
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_JFFS2_NAND
+#define CONFIG_NAND_FSL_NFC
+#define CONFIG_SYS_NAND_BASE           0xFC0FC000
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define NAND_MAX_CHIPS                 CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_NAND_SELECT_DEVICE
+#define        CONFIG_SYS_64BIT_VSPRINTF       /* needed for nand_util.c */
+#endif
+
+/* Network configuration */
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#define CONFIG_NET_MULTI               1
+#define CONFIG_MII                     1
+#define CONFIG_MII_INIT                1
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_RX_ETH_BUFFER       2
+#define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
+#define CONFIG_SYS_TX_ETH_BUFFER       2
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_SYS_FEC0_PINMUX         0
+#define CONFIG_SYS_FEC0_MIIBASE        CONFIG_SYS_FEC0_IOBASE
+#define CONFIG_SYS_FEC1_PINMUX         0
+#define CONFIG_SYS_FEC1_MIIBASE        CONFIG_SYS_FEC0_MIIBASE
+#define MCFFEC_TOUT_LOOP               50000
+#define CONFIG_SYS_FEC0_PHYADDR        0
+#define CONFIG_SYS_FEC1_PHYADDR        1
+
+#define CONFIG_BOOTDELAY               2       /* autoboot after 5 seconds */
+
+#ifdef CONFIG_SYS_NAND_BOOT
+#define CONFIG_BOOTARGS        "root=/dev/mtdblock2 rw rootfstype=jffs2 " \
+                               "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \
+                               "-(jffs2) console=ttyS0,115200"
+#else
+#define CONFIG_BOOTARGS        "root=/dev/nfs rw nfsroot="     \
+                               __stringify(CONFIG_SERVERIP) ":/tftpboot/" \
+                               __stringify(CONFIG_IPADDR) "  ip="      \
+                               __stringify(CONFIG_IPADDR) ":"  \
+                               __stringify(CONFIG_SERVERIP)":" \
+                               __stringify(CONFIG_GATEWAYIP)": "       \
+                               __stringify(CONFIG_NETMASK)             \
+                               "::eth0:off:rw console=ttyS0,115200"
+#endif
+
+#define CONFIG_ETHADDR         00:e0:0c:bc:e5:60
+#define CONFIG_ETH1ADDR        00:e0:0c:bc:e5:61
+#define CONFIG_ETHPRIME        "FEC0"
+#define CONFIG_IPADDR          192.168.1.2
+#define CONFIG_NETMASK         255.255.255.0
+#define CONFIG_SERVERIP        192.168.1.1
+#define CONFIG_GATEWAYIP       192.168.1.1
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_SYS_FEC_BUF_USE_SRAM
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#ifndef CONFIG_SYS_DISCOVER_PHY
+#define FECDUPLEX      FULL
+#define FECSPEED       _100BASET
+#define LINKSTATUS     1
+#else
+#define LINKSTATUS     0
+#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#endif
+#endif                 /* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_HOSTNAME                M54418TWR
+
+#if defined(CONFIG_CF_SBF)
+/* ST Micro serial flash */
+#define        CONFIG_SYS_LOAD_ADDR2           0x40010007
+#define CONFIG_EXTRA_ENV_SETTINGS              \
+       "netdev=eth0\0"                         \
+       "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
+       "loadaddr=0x40010000\0"                 \
+       "sbfhdr=sbfhdr.bin\0"                   \
+       "uboot=u-boot.bin\0"                    \
+       "load=tftp ${loadaddr} ${sbfhdr};"      \
+       "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
+       "upd=run load; run prog\0"              \
+       "prog=sf probe 0:1 1000000 3;"          \
+       "sf erase 0 40000;"                     \
+       "sf write ${loadaddr} 0 40000;"         \
+       "save\0"                                \
+       ""
+#elif defined(CONFIG_SYS_NAND_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS              \
+       "netdev=eth0\0"                         \
+       "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
+       "loadaddr=0x40010000\0"                 \
+       "u-boot=u-boot.bin\0"                   \
+       "load=tftp ${loadaddr} ${u-boot};\0"    \
+       "upd=run load; run prog\0"              \
+       "prog=nand device 0;"                   \
+       "nand erase 0 40000;"                   \
+       "nb_update ${loadaddr} ${filesize};"    \
+       "save\0"                                \
+       ""
+#else
+#define CONFIG_SYS_UBOOT_END   0x3FFFF
+#define CONFIG_EXTRA_ENV_SETTINGS              \
+       "netdev=eth0\0"                         \
+       "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
+       "loadaddr=40010000\0"                   \
+       "u-boot=u-boot.bin\0"                   \
+       "load=tftp ${loadaddr) ${u-boot}\0"     \
+       "upd=run load; run prog\0"              \
+       "prog=prot off mram" " ;"       \
+       "cp.b ${loadaddr} 0 ${filesize};"       \
+       "save\0"                                \
+       ""
+#endif
+
+/* Realtime clock */
+#undef CONFIG_MCFRTC
+#define CONFIG_RTC_MCFRRTC
+#define CONFIG_SYS_MCFRRTC_BASE                0xFC0A8000
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2c */
+#undef CONFIG_FSL_I2C
+#undef CONFIG_HARD_I2C         /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C         /* I2C bit-banged */
+/* I2C speed and slave address  */
+#define CONFIG_SYS_I2C_SPEED           80000
+#define CONFIG_SYS_I2C_SLAVE           0x7F
+#define CONFIG_SYS_I2C_OFFSET          0x58000
+#define CONFIG_SYS_IMMR                CONFIG_SYS_MBAR
+
+/* DSPI and Serial Flash */
+#define CONFIG_CF_SPI
+#define CONFIG_CF_DSPI
+#define CONFIG_SERIAL_FLASH
+#define CONFIG_HARD_SPI
+#define CONFIG_SYS_SBFHDR_SIZE         0x7
+#ifdef CONFIG_CMD_SPI
+#      define CONFIG_SPI_FLASH
+#      define CONFIG_SPI_FLASH_ATMEL
+
+#      define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
+                                        DSPI_CTAR_PCSSCK_1CLK | \
+                                        DSPI_CTAR_PASC(0) | \
+                                        DSPI_CTAR_PDT(0) | \
+                                        DSPI_CTAR_CSSCK(0) | \
+                                        DSPI_CTAR_ASC(0) | \
+                                        DSPI_CTAR_DT(1))
+#      define CONFIG_SYS_DSPI_CTAR1    (CONFIG_SYS_DSPI_CTAR0)
+#      define CONFIG_SYS_DSPI_CTAR2    (CONFIG_SYS_DSPI_CTAR0)
+#endif
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_PRAM                    2048    /* 2048 KB */
+
+/* HUSH */
+#define CONFIG_SYS_HUSH_PARSER         1
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+
+#define CONFIG_SYS_PROMPT              "-> "
+#define CONFIG_SYS_LONGHELP            /* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE              1024    /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE              256     /* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS             16      /* max number of command args */
+/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR           (CONFIG_SYS_SDRAM_BASE + 0x10000)
+
+#define CONFIG_SYS_HZ                  1000
+
+#define CONFIG_SYS_MBAR                0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR       0x80000000
+/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE       0x10000
+#define CONFIG_SYS_INIT_RAM_CTRL       0x221
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE       256
+#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_SIZE - \
+                                       CONFIG_SYS_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - 32)
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE          0x40000000
+#define CONFIG_SYS_SDRAM_SIZE          128     /* SDRAM size in MB */
+
+#define CONFIG_SYS_MEMTEST_START       (CONFIG_SYS_SDRAM_BASE + 0x400)
+#define CONFIG_SYS_MEMTEST_END         ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+#define CONFIG_SYS_DRAM_TEST
+
+#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
+#define CONFIG_SERIAL_BOOT
+#endif
+
+#if defined(CONFIG_SERIAL_BOOT)
+#define CONFIG_SYS_MONITOR_BASE        (TEXT_BASE + 0x400)
+#else
+#define CONFIG_SYS_MONITOR_BASE        (CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_BOOTPARAMS_LEN      (64 * 1024)
+/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN         (256 << 10)
+/* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN          (256 << 10)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
+                               (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#if !defined(CONFIG_SERIAL_BOOT)  /*MRAM boot*/
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_MRAM  1
+#define CONFIG_ENV_ADDR                (0x40000 - 0x1000) /*MRAM size 40000*/
+#define CONFIG_ENV_SIZE                0x1000
+#endif
+
+#if defined(CONFIG_CF_SBF)
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH     1
+#define CONFIG_ENV_SPI_CS              1
+#define CONFIG_ENV_OFFSET              0x40000
+#define CONFIG_ENV_SIZE                0x2000
+#define CONFIG_ENV_SECT_SIZE           0x10000
+#endif
+#if defined(CONFIG_SYS_NAND_BOOT)
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND  1
+#define CONFIG_ENV_OFFSET      0x80000
+#define CONFIG_ENV_SIZE        0x20000
+#define CONFIG_ENV_SECT_SIZE   0x20000
+#endif
+#undef CONFIG_ENV_OVERWRITE
+
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_BASE          CONFIG_SYS_CS0_BASE
+
+#undef CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+
+#define CONFIG_FLASH_CFI_DRIVER        1
+/* Max size that the board might have */
+#define CONFIG_SYS_FLASH_SIZE          0x1000000
+#define CONFIG_SYS_FLASH_CFI_WIDTH     FLASH_CFI_16BIT
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT      270
+/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_CS0_BASE }
+#else
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT      270
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS     0
+#endif
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#ifdef CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_DEV               "nand0"
+#define CONFIG_JFFS2_PART_OFFSET       (0x800000)
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define MTDIDS_DEFAULT         "nand0=m54418twr.nand"
+
+#define MTDPARTS_DEFAULT       "mtdparts=m54418twr.nand:1m(data),"     \
+                                               "7m(kernel),"           \
+                                               "-(rootfs)"
+
+#endif
+
+#ifdef CONFIG_CMD_UBI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE      /* needed for mtdparts command */
+#define CONFIG_MTD_PARTITIONS  /* mtdparts and UBI support */
+#define CONFIG_RBTREE
+#define MTDIDS_DEFAULT         "nand0=NAND"
+#define MTDPARTS_DEFAULT       "mtdparts=NAND:1m(u-boot),"     \
+                                       "-(ubi)"
+#endif
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE      16
+#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV          (CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV          (CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2          (CONFIG_SYS_SDRAM_BASE | \
+                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_BEC | CF_CACR_IEC | \
+                                        CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR         ((CONFIG_SYS_CACHE_ICACR | \
+                                        CF_CACR_DEC | CF_CACR_DDCM_P | \
+                                        CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
+#define CACR_STATUS    (CONFIG_SYS_INIT_RAM_ADDR + \
+                       CONFIG_SYS_INIT_RAM_SIZE - 12)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/*
+ * CS0 - NOR Flash 16MB
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+
+ /* Flash */
+#define CONFIG_SYS_CS0_BASE            0x00000000
+#define CONFIG_SYS_CS0_MASK            0x000F0101
+#define CONFIG_SYS_CS0_CTRL            0x00001D60
+
+#endif                         /* _M54418TWR_H */