Rename common ns16550 constants with UART_ prefix to prevent conflicts

Fix problems introduced in commit
7b5611cdd12ca0cc33f994f0d4a4454788fc3124 [inka4x0: Add hardware
diagnosis functions for inka4x0] which redefined MSR_RI which is
already used on PowerPC systems.

Also eliminate redundant definitions in ps2mult.h.  More cleanup will
be needed for other redundant occurrences though.

Signed-off-by: Detlev Zundel <dzu@denx.de>

diff --git a/board/inka4x0/inkadiag.c b/board/inka4x0/inkadiag.c
index 06c980713bd78d4e19b02e85f2a2d940078f16d7..12c0a85d6ec41da1898933c4dd37a138fecb15bd 100644 (file)
--- a/board/inka4x0/inkadiag.c
+++ b/board/inka4x0/inkadiag.c
@@ -280,48 +280,48 @@ static int do_inkadiag_serial(cmd_tbl_t *cmdtp, int flag, int argc,
        if ((num >= 0) && (num <= 7)) {
                if (mode & 1) {
                        /* turn on 'loopback' mode */
        if ((num >= 0) && (num <= 7)) {
                if (mode & 1) {
                        /* turn on 'loopback' mode */

-                       out_8(&uart->mcr, MCR_LOOP);
+                       out_8(&uart->mcr, UART_MCR_LOOP);

                } else {
                        /*
                         * establish the UART's operational parameters
                         * set DLAB=1, so rbr accesses DLL
                         */
                } else {
                        /*
                         * establish the UART's operational parameters
                         * set DLAB=1, so rbr accesses DLL
                         */

-                       out_8(&uart->lcr, LCR_DLAB);
+                       out_8(&uart->lcr, UART_LCR_DLAB);

                        /* set baudrate */
                        out_8(&uart->rbr, combrd);
                        /* set data-format: 8-N-1 */
                        /* set baudrate */
                        out_8(&uart->rbr, combrd);
                        /* set data-format: 8-N-1 */

-                       out_8(&uart->lcr, LCR_WLS_8);
+                       out_8(&uart->lcr, UART_LCR_WLS_8);

                }
 
                if (mode & 2) {
                        /* set request to send */
                }
 
                if (mode & 2) {
                        /* set request to send */

-                       out_8(&uart->mcr, MCR_RTS);
+                       out_8(&uart->mcr, UART_MCR_RTS);

                        udelay(10);
                        /* check clear to send */
                        udelay(10);
                        /* check clear to send */

-                       if ((in_8(&uart->msr) & MSR_CTS) == 0x00)
+                       if ((in_8(&uart->msr) & UART_MSR_CTS) == 0x00)

                                return -1;
                }
                if (mode & 4) {
                        /* set data terminal ready */
                                return -1;
                }
                if (mode & 4) {
                        /* set data terminal ready */

-                       out_8(&uart->mcr, MCR_DTR);
+                       out_8(&uart->mcr, UART_MCR_DTR);

                        udelay(10);
                        /* check data set ready and carrier detect */
                        udelay(10);
                        /* check data set ready and carrier detect */

-                       if ((in_8(&uart->msr) & (MSR_DSR | MSR_DCD))
-                           != (MSR_DSR | MSR_DCD))
+                       if ((in_8(&uart->msr) & (UART_MSR_DSR | UART_MSR_DCD))
+                           != (UART_MSR_DSR | UART_MSR_DCD))

                                return -1;
                }
 
                /* write each message-character, read it back, and display it */
                for (i = 0, len = strlen(argv[3]); i < len; ++i) {
                        j = 0;
                                return -1;
                }
 
                /* write each message-character, read it back, and display it */
                for (i = 0, len = strlen(argv[3]); i < len; ++i) {
                        j = 0;

-                       while ((in_8(&uart->lsr) & LSR_THRE) == 0x00) {
+                       while ((in_8(&uart->lsr) & UART_LSR_THRE) ==    0x00) {

                                if (j++ > CONFIG_SYS_HZ)
                                        break;
                                udelay(10);
                        }
                        out_8(&uart->rbr, argv[3][i]);
                        j = 0;
                                if (j++ > CONFIG_SYS_HZ)
                                        break;
                                udelay(10);
                        }
                        out_8(&uart->rbr, argv[3][i]);
                        j = 0;

-                       while ((in_8(&uart->lsr) & LSR_DR) == 0x00) {
+                       while ((in_8(&uart->lsr) & UART_LSR_DR) == 0x00) {

                                if (j++ > CONFIG_SYS_HZ)
                                        break;
                                udelay(10);
                                if (j++ > CONFIG_SYS_HZ)
                                        break;
                                udelay(10);

diff --git a/board/linkstation/avr.c b/board/linkstation/avr.c
index fda1b913eb6750213f7ce1b8d716eb4e8641f604..782b24a71aaaef17c79ec7d2fde157bd67dcae71 100644 (file)
--- a/board/linkstation/avr.c
+++ b/board/linkstation/avr.c
@@ -90,12 +90,12 @@ void init_AVR_DUART (void)
         */
        AVR_port->lcr = 0x00;
        AVR_port->ier = 0x00;
         */
        AVR_port->lcr = 0x00;
        AVR_port->ier = 0x00;

-       AVR_port->lcr = LCR_BKSE;
+       AVR_port->lcr = UART_LCR_BKSE;

        AVR_port->dll = clock_divisor & 0xff;
        AVR_port->dlm = (clock_divisor >> 8) & 0xff;
        AVR_port->dll = clock_divisor & 0xff;
        AVR_port->dlm = (clock_divisor >> 8) & 0xff;

-       AVR_port->lcr = LCR_WLS_8 | LCR_PEN | LCR_EPS;
+       AVR_port->lcr = UART_LCR_WLS_8 | UART_LCR_PEN | UART_LCR_EPS;

        AVR_port->mcr = 0x00;
        AVR_port->mcr = 0x00;

-       AVR_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
+       AVR_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR;

 
        miconCntl_DisWDT();
 
 
        miconCntl_DisWDT();
 

diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c
index 1af3fde6477868151d4ed87f08b347a24536fe91..1a5e2d43dba29537d92670685ca9283e9841e167 100644 (file)
--- a/drivers/input/ps2ser.c
+++ b/drivers/input/ps2ser.c
@@ -1,6 +1,6 @@
 /***********************************************************************
  *
 /***********************************************************************
  *

- * (C) Copyright 2004
+ * (C) Copyright 2004-2009

  * DENX Software Engineering
  * Wolfgang Denk, wd@denx.de
  * All rights reserved.
  * DENX Software Engineering
  * Wolfgang Denk, wd@denx.de
  * All rights reserved.


@@ -18,9 +18,11 @@
 #include <asm/io.h>
 #include <asm/atomic.h>
 #include <ps2mult.h>
 #include <asm/io.h>
 #include <asm/atomic.h>
 #include <ps2mult.h>

-#if defined(CONFIG_SYS_NS16550) || defined(CONFIG_MPC85xx)
-#include <ns16550.h>
+/* This is needed for ns16550.h */
+#ifndef CONFIG_SYS_NS16550_REG_SIZE
+#define CONFIG_SYS_NS16550_REG_SIZE 1

 #endif
 #endif

+#include <ns16550.h>

 
 DECLARE_GLOBAL_DATA_PTR;
 
 
 DECLARE_GLOBAL_DATA_PTR;
 


@@ -128,12 +130,12 @@ int ps2ser_init(void)
        NS16550_t com_port = (NS16550_t)COM_BASE;
 
        com_port->ier = 0x00;
        NS16550_t com_port = (NS16550_t)COM_BASE;
 
        com_port->ier = 0x00;

-       com_port->lcr = LCR_BKSE | LCR_8N1;
+       com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;

        com_port->dll = (CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
        com_port->dlm = ((CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
        com_port->dll = (CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
        com_port->dlm = ((CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;

-       com_port->lcr = LCR_8N1;
-       com_port->mcr = (MCR_DTR | MCR_RTS);
-       com_port->fcr = (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR);
+       com_port->lcr = UART_LCR_8N1;
+       com_port->mcr = (UART_MCR_DTR | UART_MCR_RTS);
+       com_port->fcr = (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR);

 
        return (0);
 }
 
        return (0);
 }


@@ -202,7 +204,7 @@ void ps2ser_putc(int chr)
        psc->psc_buffer_8 = chr;
 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
        psc->psc_buffer_8 = chr;
 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)

-       while ((com_port->lsr & LSR_THRE) == 0);
+       while ((com_port->lsr & UART_LSR_THRE) == 0);

        com_port->thr = chr;
 #else
        while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));
        com_port->thr = chr;
 #else
        while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));


@@ -227,7 +229,7 @@ static int ps2ser_getc_hw(void)
        }
 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
        }
 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)

-       if (com_port->lsr & LSR_DR) {
+       if (com_port->lsr & UART_LSR_DR) {

                res = com_port->rbr;
        }
 #else
                res = com_port->rbr;
        }
 #else


@@ -315,7 +317,7 @@ static void ps2ser_interrupt(void *dev_id)
        } while (status & PSC_SR_RXRDY);
 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
        } while (status & PSC_SR_RXRDY);
 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)

-       } while (status & LSR_DR);
+       } while (status & UART_LSR_DR);

 #else
        } while (status & UART_IIR_RDI);
 #endif
 #else
        } while (status & UART_IIR_RDI);
 #endif

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 397f5df5d60b81139852037c35c9464ba6bece27..657c9dadf9cd5f3e56f5e0c7858b26fbecc6e921 100644 (file)
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -7,9 +7,12 @@
 #include <config.h>
 #include <ns16550.h>
 
 #include <config.h>
 #include <ns16550.h>
 

-#define LCRVAL LCR_8N1                                 /* 8 data, 1 stop, no parity */
-#define MCRVAL (MCR_DTR | MCR_RTS)                     /* RTS/DTR */
-#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR)     /* Clear & enable FIFOs */
+#define UART_LCRVAL UART_LCR_8N1               /* 8 data, 1 stop, no parity */
+#define UART_MCRVAL (UART_MCR_DTR | \
+                    UART_MCR_RTS)              /* RTS/DTR */
+#define UART_FCRVAL (UART_FCR_FIFO_EN |        \
+                    UART_FCR_RXSR |    \
+                    UART_FCR_TXSR)             /* Clear & enable FIFOs */

 
 void NS16550_init (NS16550_t com_port, int baud_divisor)
 {
 
 void NS16550_init (NS16550_t com_port, int baud_divisor)
 {


@@ -17,16 +20,16 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
 #ifdef CONFIG_OMAP
        com_port->mdr1 = 0x7;   /* mode select reset TL16C750*/
 #endif
 #ifdef CONFIG_OMAP
        com_port->mdr1 = 0x7;   /* mode select reset TL16C750*/
 #endif

-       com_port->lcr = LCR_BKSE | LCRVAL;
+       com_port->lcr = UART_LCR_BKSE | UART_LCRVAL;

        com_port->dll = 0;
        com_port->dlm = 0;
        com_port->dll = 0;
        com_port->dlm = 0;

-       com_port->lcr = LCRVAL;
-       com_port->mcr = MCRVAL;
-       com_port->fcr = FCRVAL;
-       com_port->lcr = LCR_BKSE | LCRVAL;
+       com_port->lcr = UART_LCRVAL;
+       com_port->mcr = UART_MCRVAL;
+       com_port->fcr = UART_FCRVAL;
+       com_port->lcr = UART_LCR_BKSE | UART_LCRVAL;

        com_port->dll = baud_divisor & 0xff;
        com_port->dlm = (baud_divisor >> 8) & 0xff;
        com_port->dll = baud_divisor & 0xff;
        com_port->dlm = (baud_divisor >> 8) & 0xff;

-       com_port->lcr = LCRVAL;
+       com_port->lcr = UART_LCRVAL;

 #if defined(CONFIG_OMAP)
 #if defined(CONFIG_APTIX)
        com_port->mdr1 = 3;     /* /13 mode so Aptix 6MHz can hit 115200 */
 #if defined(CONFIG_OMAP)
 #if defined(CONFIG_APTIX)
        com_port->mdr1 = 3;     /* /13 mode so Aptix 6MHz can hit 115200 */


@@ -40,29 +43,29 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
 void NS16550_reinit (NS16550_t com_port, int baud_divisor)
 {
        com_port->ier = 0x00;
 void NS16550_reinit (NS16550_t com_port, int baud_divisor)
 {
        com_port->ier = 0x00;

-       com_port->lcr = LCR_BKSE | LCRVAL;
+       com_port->lcr = UART_LCR_BKSE | UART_LCRVAL;

        com_port->dll = 0;
        com_port->dlm = 0;
        com_port->dll = 0;
        com_port->dlm = 0;

-       com_port->lcr = LCRVAL;
-       com_port->mcr = MCRVAL;
-       com_port->fcr = FCRVAL;
-       com_port->lcr = LCR_BKSE;
+       com_port->lcr = UART_LCRVAL;
+       com_port->mcr = UART_MCRVAL;
+       com_port->fcr = UART_FCRVAL;
+       com_port->lcr = UART_LCR_BKSE;

        com_port->dll = baud_divisor & 0xff;
        com_port->dlm = (baud_divisor >> 8) & 0xff;
        com_port->dll = baud_divisor & 0xff;
        com_port->dlm = (baud_divisor >> 8) & 0xff;

-       com_port->lcr = LCRVAL;
+       com_port->lcr = UART_LCRVAL;

 }
 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
 
 void NS16550_putc (NS16550_t com_port, char c)
 {
 }
 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
 
 void NS16550_putc (NS16550_t com_port, char c)
 {

-       while ((com_port->lsr & LSR_THRE) == 0);
+       while ((com_port->lsr & UART_LSR_THRE) == 0);

        com_port->thr = c;
 }
 
 #ifndef CONFIG_NS16550_MIN_FUNCTIONS
 char NS16550_getc (NS16550_t com_port)
 {
        com_port->thr = c;
 }
 
 #ifndef CONFIG_NS16550_MIN_FUNCTIONS
 char NS16550_getc (NS16550_t com_port)
 {

-       while ((com_port->lsr & LSR_DR) == 0) {
+       while ((com_port->lsr & UART_LSR_DR) == 0) {

 #ifdef CONFIG_USB_TTY
                extern void usbtty_poll(void);
                usbtty_poll();
 #ifdef CONFIG_USB_TTY
                extern void usbtty_poll(void);
                usbtty_poll();


@@ -73,7 +76,7 @@ char NS16550_getc (NS16550_t com_port)
 
 int NS16550_tstc (NS16550_t com_port)
 {
 
 int NS16550_tstc (NS16550_t com_port)
 {

-       return ((com_port->lsr & LSR_DR) != 0);
+       return ((com_port->lsr & UART_LSR_DR) != 0);

 }
 
 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
 }
 
 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */

diff --git a/include/ns16550.h b/include/ns16550.h
index edfbc53a521e402e8baf678a3f8d0985c9f8bd2e..87624bf4220f90d6f5c35f681f7ac8dded7db8bb 100644 (file)
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -1,6 +1,10 @@
 /*
  * NS16550 Serial Port
  * originally from linux source (arch/ppc/boot/ns16550.h)
 /*
  * NS16550 Serial Port
  * originally from linux source (arch/ppc/boot/ns16550.h)

+ *
+ * Cleanup and unification
+ * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
+ *

  * modified slightly to
  * have addresses as offsets from CONFIG_SYS_ISA_BASE
  * added a few more definitions
  * modified slightly to
  * have addresses as offsets from CONFIG_SYS_ISA_BASE
  * added a few more definitions


@@ -115,53 +119,100 @@ struct NS16550 {
 
 typedef volatile struct NS16550 *NS16550_t;
 
 
 typedef volatile struct NS16550 *NS16550_t;
 

-#define FCR_FIFO_EN     0x01           /* Fifo enable */
-#define FCR_RXSR        0x02           /* Receiver soft reset */
-#define FCR_TXSR        0x04           /* Transmitter soft reset */
-
-#define MCR_DTR         0x01
-#define MCR_RTS         0x02
-#define MCR_DMA_EN      0x04
-#define MCR_TX_DFR      0x08
-#define MCR_LOOP       0x10            /* Enable loopback test mode */
-
-#define LCR_WLS_MSK    0x03            /* character length select mask */
-#define LCR_WLS_5      0x00            /* 5 bit character length */
-#define LCR_WLS_6      0x01            /* 6 bit character length */
-#define LCR_WLS_7      0x02            /* 7 bit character length */
-#define LCR_WLS_8      0x03            /* 8 bit character length */
-#define LCR_STB                0x04            /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define LCR_PEN                0x08            /* Parity eneble */
-#define LCR_EPS                0x10            /* Even Parity Select */
-#define LCR_STKP       0x20            /* Stick Parity */
-#define LCR_SBRK       0x40            /* Set Break */
-#define LCR_BKSE       0x80            /* Bank select enable */
-#define LCR_DLAB       0x80            /* Divisor latch access bit */
-
-#define LSR_DR         0x01            /* Data ready */
-#define LSR_OE         0x02            /* Overrun */
-#define LSR_PE         0x04            /* Parity error */
-#define LSR_FE         0x08            /* Framing error */
-#define LSR_BI         0x10            /* Break */
-#define LSR_THRE       0x20            /* Xmit holding register empty */
-#define LSR_TEMT       0x40            /* Xmitter empty */
-#define LSR_ERR                0x80            /* Error */
-
-#define MSR_DCD                0x80            /* Data Carrier Detect */
-#define MSR_RI         0x40            /* Ring Indicator */
-#define MSR_DSR                0x20            /* Data Set Ready */
-#define MSR_CTS                0x10            /* Clear to Send */
-#define MSR_DDCD       0x08            /* Delta DCD */
-#define MSR_TERI       0x04            /* Trailing edge ring indicator */
-#define MSR_DDSR       0x02            /* Delta DSR */
-#define MSR_DCTS       0x01            /* Delta CTS */
+/*
+ * These are the definitions for the FIFO Control Register
+ */
+#define UART_FCR_FIFO_EN       0x01 /* Fifo enable */
+#define UART_FCR_CLEAR_RCVR    0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT    0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT    0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK  0xC0 /* Mask for the FIFO trigger range */
+#define UART_FCR_TRIGGER_1     0x00 /* Mask for trigger set at 1 */
+#define UART_FCR_TRIGGER_4     0x40 /* Mask for trigger set at 4 */
+#define UART_FCR_TRIGGER_8     0x80 /* Mask for trigger set at 8 */
+#define UART_FCR_TRIGGER_14    0xC0 /* Mask for trigger set at 14 */
+
+#define UART_FCR_RXSR          0x02 /* Receiver soft reset */
+#define UART_FCR_TXSR          0x04 /* Transmitter soft reset */
+
+/*
+ * These are the definitions for the Modem Control Register
+ */
+#define UART_MCR_DTR   0x01            /* DTR   */
+#define UART_MCR_RTS   0x02            /* RTS   */
+#define UART_MCR_OUT1  0x04            /* Out 1 */
+#define UART_MCR_OUT2  0x08            /* Out 2 */
+#define UART_MCR_LOOP  0x10            /* Enable loopback test mode */
+
+#define UART_MCR_DMA_EN        0x04
+#define UART_MCR_TX_DFR        0x08
+
+/*
+ * These are the definitions for the Line Control Register
+ *
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
+ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+ */
+#define UART_LCR_WLS_MSK 0x03          /* character length select mask */
+#define UART_LCR_WLS_5 0x00            /* 5 bit character length */
+#define UART_LCR_WLS_6 0x01            /* 6 bit character length */
+#define UART_LCR_WLS_7 0x02            /* 7 bit character length */
+#define UART_LCR_WLS_8 0x03            /* 8 bit character length */
+#define UART_LCR_STB   0x04            /* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define UART_LCR_PEN   0x08            /* Parity eneble */
+#define UART_LCR_EPS   0x10            /* Even Parity Select */
+#define UART_LCR_STKP  0x20            /* Stick Parity */
+#define UART_LCR_SBRK  0x40            /* Set Break */
+#define UART_LCR_BKSE  0x80            /* Bank select enable */
+#define UART_LCR_DLAB  0x80            /* Divisor latch access bit */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_DR    0x01            /* Data ready */
+#define UART_LSR_OE    0x02            /* Overrun */
+#define UART_LSR_PE    0x04            /* Parity error */
+#define UART_LSR_FE    0x08            /* Framing error */
+#define UART_LSR_BI    0x10            /* Break */
+#define UART_LSR_THRE  0x20            /* Xmit holding register empty */
+#define UART_LSR_TEMT  0x40            /* Xmitter empty */
+#define UART_LSR_ERR   0x80            /* Error */
+
+#define UART_MSR_DCD   0x80            /* Data Carrier Detect */
+#define UART_MSR_RI    0x40            /* Ring Indicator */
+#define UART_MSR_DSR   0x20            /* Data Set Ready */
+#define UART_MSR_CTS   0x10            /* Clear to Send */
+#define UART_MSR_DDCD  0x08            /* Delta DCD */
+#define UART_MSR_TERI  0x04            /* Trailing edge ring indicator */
+#define UART_MSR_DDSR  0x02            /* Delta DSR */
+#define UART_MSR_DCTS  0x01            /* Delta CTS */
+
+/*
+ * These are the definitions for the Interrupt Identification Register
+ */
+#define UART_IIR_NO_INT        0x01    /* No interrupts pending */
+#define UART_IIR_ID    0x06    /* Mask for the interrupt ID */
+
+#define UART_IIR_MSI   0x00    /* Modem status interrupt */
+#define UART_IIR_THRI  0x02    /* Transmitter holding register empty */
+#define UART_IIR_RDI   0x04    /* Receiver data interrupt */
+#define UART_IIR_RLSI  0x06    /* Receiver line status interrupt */
+
+/*
+ * These are the definitions for the Interrupt Enable Register
+ */
+#define UART_IER_MSI   0x08    /* Enable Modem status interrupt */
+#define UART_IER_RLSI  0x04    /* Enable receiver line status interrupt */
+#define UART_IER_THRI  0x02    /* Enable Transmitter holding register int. */
+#define UART_IER_RDI   0x01    /* Enable receiver data interrupt */
+

 
 #ifdef CONFIG_OMAP1510
 
 #ifdef CONFIG_OMAP1510

-#define OSC_12M_SEL    0x01            /* selects 6.5 * current clk div */
+#define OSC_12M_SEL    0x01    /* selects 6.5 * current clk div */

 #endif
 
 /* useful defaults for LCR */
 #endif
 
 /* useful defaults for LCR */

-#define LCR_8N1                0x03
+#define UART_LCR_8N1   0x03

 
 void   NS16550_init   (NS16550_t com_port, int baud_divisor);
 void   NS16550_putc   (NS16550_t com_port, char c);
 
 void   NS16550_init   (NS16550_t com_port, int baud_divisor);
 void   NS16550_putc   (NS16550_t com_port, char c);

diff --git a/include/ps2mult.h b/include/ps2mult.h
index 599cb6dc42ddbf82ac524d10d4dedaf145baf331..1a38733b7649af5a240e26d832dae51587cf89a2 100644 (file)
--- a/include/ps2mult.h
+++ b/include/ps2mult.h
@@ -53,103 +53,4 @@ struct serial_state {
        u8      *iomem_base;
 };
 
        u8      *iomem_base;
 };
 

-#define UART_RX                0       /* In:  Receive buffer (DLAB=0) */
-#define UART_TX                0       /* Out: Transmit buffer (DLAB=0) */
-#define UART_DLL       0       /* Out: Divisor Latch Low (DLAB=1) */
-
-#define UART_DLM       1       /* Out: Divisor Latch High (DLAB=1) */
-#define UART_IER       1       /* Out: Interrupt Enable Register */
-
-#define UART_IIR       2       /* In:  Interrupt ID Register */
-#define UART_FCR       2       /* Out: FIFO Control Register */
-
-#define UART_LCR       3       /* Out: Line Control Register */
-#define UART_MCR       4       /* Out: Modem Control Register */
-#define UART_LSR       5       /* In:  Line Status Register */
-#define UART_MSR       6       /* In:  Modem Status Register */
-#define UART_SCR       7       /* I/O: Scratch Register */
-
-/*
- * These are the definitions for the FIFO Control Register
- * (16650 only)
- */
-#define UART_FCR_ENABLE_FIFO   0x01 /* Enable the FIFO */
-#define UART_FCR_CLEAR_RCVR    0x02 /* Clear the RCVR FIFO */
-#define UART_FCR_CLEAR_XMIT    0x04 /* Clear the XMIT FIFO */
-#define UART_FCR_DMA_SELECT    0x08 /* For DMA applications */
-#define UART_FCR_TRIGGER_MASK  0xC0 /* Mask for the FIFO trigger range */
-#define UART_FCR_TRIGGER_1     0x00 /* Mask for trigger set at 1 */
-#define UART_FCR_TRIGGER_4     0x40 /* Mask for trigger set at 4 */
-#define UART_FCR_TRIGGER_8     0x80 /* Mask for trigger set at 8 */
-#define UART_FCR_TRIGGER_14    0xC0 /* Mask for trigger set at 14 */
-
-/*
- * These are the definitions for the Line Control Register
- *
- * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
- * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
- */
-#define UART_LCR_DLAB  0x80    /* Divisor latch access bit */
-#define UART_LCR_SBC   0x40    /* Set break control */
-#define UART_LCR_SPAR  0x20    /* Stick parity (?) */
-#define UART_LCR_EPAR  0x10    /* Even parity select */
-#define UART_LCR_PARITY        0x08    /* Parity Enable */
-#define UART_LCR_STOP  0x04    /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
-#define UART_LCR_WLEN5  0x00   /* Wordlength: 5 bits */
-#define UART_LCR_WLEN6  0x01   /* Wordlength: 6 bits */
-#define UART_LCR_WLEN7  0x02   /* Wordlength: 7 bits */
-#define UART_LCR_WLEN8  0x03   /* Wordlength: 8 bits */
-
-/*
- * These are the definitions for the Line Status Register
- */
-#define UART_LSR_TEMT  0x40    /* Transmitter empty */
-#define UART_LSR_THRE  0x20    /* Transmit-hold-register empty */
-#define UART_LSR_BI    0x10    /* Break interrupt indicator */
-#define UART_LSR_FE    0x08    /* Frame error indicator */
-#define UART_LSR_PE    0x04    /* Parity error indicator */
-#define UART_LSR_OE    0x02    /* Overrun error indicator */
-#define UART_LSR_DR    0x01    /* Receiver data ready */
-
-/*
- * These are the definitions for the Interrupt Identification Register
- */
-#define UART_IIR_NO_INT        0x01    /* No interrupts pending */
-#define UART_IIR_ID    0x06    /* Mask for the interrupt ID */
-
-#define UART_IIR_MSI   0x00    /* Modem status interrupt */
-#define UART_IIR_THRI  0x02    /* Transmitter holding register empty */
-#define UART_IIR_RDI   0x04    /* Receiver data interrupt */
-#define UART_IIR_RLSI  0x06    /* Receiver line status interrupt */
-
-/*
- * These are the definitions for the Interrupt Enable Register
- */
-#define UART_IER_MSI   0x08    /* Enable Modem status interrupt */
-#define UART_IER_RLSI  0x04    /* Enable receiver line status interrupt */
-#define UART_IER_THRI  0x02    /* Enable Transmitter holding register int. */
-#define UART_IER_RDI   0x01    /* Enable receiver data interrupt */
-
-/*
- * These are the definitions for the Modem Control Register
- */
-#define UART_MCR_LOOP  0x10    /* Enable loopback test mode */
-#define UART_MCR_OUT2  0x08    /* Out2 complement */
-#define UART_MCR_OUT1  0x04    /* Out1 complement */
-#define UART_MCR_RTS   0x02    /* RTS complement */
-#define UART_MCR_DTR   0x01    /* DTR complement */
-
-/*
- * These are the definitions for the Modem Status Register
- */
-#define UART_MSR_DCD   0x80    /* Data Carrier Detect */
-#define UART_MSR_RI    0x40    /* Ring Indicator */
-#define UART_MSR_DSR   0x20    /* Data Set Ready */
-#define UART_MSR_CTS   0x10    /* Clear to Send */
-#define UART_MSR_DDCD  0x08    /* Delta DCD */
-#define UART_MSR_TERI  0x04    /* Trailing edge ring indicator */
-#define UART_MSR_DDSR  0x02    /* Delta DSR */
-#define UART_MSR_DCTS  0x01    /* Delta CTS */
-#define UART_MSR_ANY_DELTA 0x0F        /* Any of the delta bits! */
-

 #endif /* __LINUX_PS2MULT_H */
 #endif /* __LINUX_PS2MULT_H */