depends on !SPL_BUILD
help
The old configuration infrastructure (= mkconfig + boards.cfg)
- provided the extra options field. It you have something like
+ provided the extra options field. If you have something like
"HAS_BAR,BAZ=64", the optional options
#define CONFIG_HAS
#define CONFIG_BAZ 64
endmenu # Boot images
source "arch/Kconfig"
+
+source "common/Kconfig"
+
+source "dts/Kconfig"
+
+source "net/Kconfig"
+
+source "drivers/Kconfig"
+
+source "fs/Kconfig"
+
+source "lib/Kconfig"
libs-y += net/
libs-y += disk/
libs-y += drivers/
-libs-$(CONFIG_DM) += drivers/core/
libs-y += drivers/dma/
libs-y += drivers/gpio/
libs-y += drivers/i2c/
-libs-y += drivers/input/
libs-y += drivers/mmc/
libs-y += drivers/mtd/
libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/
libs-$(CONFIG_HAS_POST) += post/
libs-y += test/
libs-y += test/dm/
-libs-$(CONFIG_DM_DEMO) += drivers/demo/
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
libs-y += arch/$(ARCH)/imx-common/
downloads. This buffer should be as large as possible for a
platform. Define this to the size available RAM for fastboot.
+ CONFIG_FASTBOOT_FLASH
+ The fastboot protocol includes a "flash" command for writing
+ the downloaded image to a non-volatile storage device. Define
+ this to enable the "fastboot flash" command.
+
+ CONFIG_FASTBOOT_FLASH_MMC_DEV
+ The fastboot "flash" command requires additional information
+ regarding the non-volatile storage device. Define this to
+ the eMMC device that fastboot should use to store the image.
+
- Journaling Flash filesystem support:
CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
CONFIG_JFFS2_NAND_DEV
config ARM
bool "ARM architecture"
+ select SUPPORT_OF_CONTROL
config AVR32
bool "AVR32 architecture"
config MICROBLAZE
bool "MicroBlaze architecture"
+ select SUPPORT_OF_CONTROL
config MIPS
bool "MIPS architecture"
config SANDBOX
bool "Sandbox"
+ select SUPPORT_OF_CONTROL
config SH
bool "SuperH architecture"
config X86
bool "x86 architecture"
+ select SUPPORT_OF_CONTROL
endchoice
config TEGRA
bool "NVIDIA Tegra"
select SPL
+ select OF_CONTROL if !SPL_BUILD
config TARGET_VEXPRESS_AEMV8A
bool "Support vexpress_aemv8a"
pllctl_reg_write(data->pll, ctl, tmp);
mult = data->pll_freq / fpll;
- for (mult = MAX(mult, 1); mult <= MAX_MULT; mult++) {
+ for (mult = max(mult, 1); mult <= MAX_MULT; mult++) {
div = (fpll * mult) / data->pll_freq;
if (div < 1 || div > MAX_DIV)
continue;
config TARGET_ARNDALE
bool "Exynos5250 Arndale board"
+ select OF_CONTROL if !SPL_BUILD
config TARGET_SMDK5250
bool "SMDK5250 board"
+ select OF_CONTROL if !SPL_BUILD
config TARGET_SNOW
bool "Snow board"
+ select OF_CONTROL if !SPL_BUILD
config TARGET_SMDK5420
bool "SMDK5420 board"
+ select OF_CONTROL if !SPL_BUILD
config TARGET_PEACH_PIT
bool "Peach Pi board"
+ select OF_CONTROL if !SPL_BUILD
endchoice
switch (ddr3_cfg->mem_speed) {
case 800:
- txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
- tcke = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
+ txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
+ tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(40000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
+ trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
} else {
tfaw = DIV_ROUND_UP(50000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
+ trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
}
break;
case 1066:
- txp = DIV_ROUND_UP(MAX(3 * clkper, 7500), clkper) - 1;
- tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
+ txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
+ tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(37500, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
+ trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
} else {
tfaw = DIV_ROUND_UP(50000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4 * clkper, 10000), clkper) - 1;
+ trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
}
break;
case 1333:
- txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
- tcke = DIV_ROUND_UP(MAX(3 * clkper, 5625), clkper) - 1;
+ txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1;
+ tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(30000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1;
+ trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1;
} else {
tfaw = DIV_ROUND_UP(45000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
+ trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
}
break;
case 1600:
- txp = DIV_ROUND_UP(MAX(3 * clkper, 6000), clkper) - 1;
- tcke = DIV_ROUND_UP(MAX(3 * clkper, 5000), clkper) - 1;
+ txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1;
+ tcke = DIV_ROUND_UP(max(3 * clkper, 5000), clkper) - 1;
if (ddr3_cfg->pagesz == 1) {
tfaw = DIV_ROUND_UP(30000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4 * clkper, 6000), clkper) - 1;
+ trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1;
} else {
tfaw = DIV_ROUND_UP(40000, clkper) - 1;
- trrd = DIV_ROUND_UP(MAX(4 * clkper, 7500), clkper) - 1;
+ trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
}
break;
default:
hang();
break;
}
- txpdll = DIV_ROUND_UP(MAX(10 * clkper, 24000), clkper) - 1;
- tcksre = DIV_ROUND_UP(MAX(5 * clkper, 10000), clkper);
+ txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
+ tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
taonpd = DIV_ROUND_UP(2000, clkper) - 1;
tcksrx = tcksre;
taofpd = taonpd;
twr = DIV_ROUND_UP(15000, clkper) - 1;
- tmrd = DIV_ROUND_UP(MAX(12 * clkper, 15000), clkper) - 1;
+ tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
- twtr = ROUND(MAX(4 * clkper, 7500) / clkper, 1) - 1;
+ twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
trcd = trp;
trtp = twtr;
cs0_end = 4 * sysinfo->cs_density - 1;
#define KWSPI_XFERLEN_2BYTE (1 << 5)
#define KWSPI_XFERLEN_MASK (1 << 5)
#define KWSPI_ADRLEN_1BYTE 0
-#define KWSPI_ADRLEN_2BYTE 1 << 8
-#define KWSPI_ADRLEN_3BYTE 2 << 8
-#define KWSPI_ADRLEN_4BYTE 3 << 8
-#define KWSPI_ADRLEN_MASK 3 << 8
+#define KWSPI_ADRLEN_2BYTE (1 << 8)
+#define KWSPI_ADRLEN_3BYTE (2 << 8)
+#define KWSPI_ADRLEN_4BYTE (3 << 8)
+#define KWSPI_ADRLEN_MASK (3 << 8)
#define KWSPI_TIMEOUT 10000
#endif /* __KW_SPI_H__ */
CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
LDFLAGS_FINAL += --gc-sections
+LDFLAGS_FINAL += --bss-plt
PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections \
-meabi
PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2
#endif
cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
- /* Is serdes enabled at all? */
- if (!cfg) {
- printf("SERDES%d is not enabled\n", sd + 1);
- return 0;
- }
/* Erratum A-007186
* Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
/*
- * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ * Copyright 2009-2014 Freescale Semiconductor, Inc.
*
* This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
* arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
{
const char *modes[] = { "host", "peripheral", "otg" };
const char *phys[] = { "ulpi", "utmi" };
- const char *dr_mode_type = NULL;
- const char *dr_phy_type = NULL;
int usb_mode_off = -1;
int usb_phy_off = -1;
char str[5];
int i, j;
for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
+ const char *dr_mode_type = NULL;
+ const char *dr_phy_type = NULL;
int mode_idx = -1, phy_idx = -1;
snprintf(str, 5, "%s%d", "usb", i);
if (hwconfig(str)) {
}
}
- if (mode_idx < 0 || phy_idx < 0) {
- puts("ERROR: wrong usb mode/phy defined!!\n");
- return;
- }
-
- dr_mode_type = modes[mode_idx];
- dr_phy_type = phys[phy_idx];
-
if (mode_idx < 0 && phy_idx < 0) {
printf("WARNING: invalid phy or mode\n");
return;
}
+
+ if (mode_idx > -1)
+ dr_mode_type = modes[mode_idx];
+
+ if (phy_idx > -1)
+ dr_phy_type = phys[phy_idx];
}
usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
/* Handle memory below 4GB. */
if (start <= max_addr) {
- phys_size_t low_size = MIN(max_addr + 1 - start, size);
+ phys_size_t low_size = min(max_addr + 1 - start, size);
void *start_ptr = (void *)(uintptr_t)start;
assert(((phys_addr_t)(uintptr_t)start) == start);
/* Handle the first partial page. */
if (offset) {
phys_addr_t end =
- MIN(map_addr + LARGE_PAGE_SIZE, start + size);
+ min(map_addr + LARGE_PAGE_SIZE, start + size);
phys_size_t cur_size = end - start;
x86_phys_memset_page(map_addr, offset, c, cur_size);
size -= cur_size;
NET2BIG_V2 BOARD
-M: -
+#M: -
S: Maintained
F: board/LaCie/net2big_v2/
F: include/configs/lacie_kw.h
F: configs/netspace_v2_defconfig
NETSPACE_LITE_V2 BOARD
-M: -
+#M: -
S: Maintained
F: configs/netspace_lite_v2_defconfig
F: configs/netspace_mini_v2_defconfig
WIRELESS_SPACE BOARD
-M: -
+#M: -
S: Maintained
F: board/LaCie/wireless_space/
F: include/configs/wireless_space.h
DB64360 BOARD
-M: -
+#M: -
S: Maintained
F: board/Marvell/db64360/
F: include/configs/DB64360.h
DB64460 BOARD
-M: -
+#M: -
S: Maintained
F: board/Marvell/db64460/
F: include/configs/DB64460.h
F: configs/openrd_base_defconfig
OPENRD_CLIENT BOARD
-M: -
+#M: -
S: Maintained
F: configs/openrd_client_defconfig
F: configs/openrd_ultimate_defconfig
A3000 BOARD
-M: -
+#M: -
S: Maintained
F: board/a3000/
F: include/configs/A3000.h
BLUESTONE BOARD
-M: Tirumala Marri <tmarri@apm.com>
+#M: Tirumala Marri <tmarri@apm.com>
S: Orphan (since 2014-03)
F: board/amcc/bluestone/
F: include/configs/bluestone.h
BUBINGA BOARD
-M: -
+#M: -
S: Maintained
F: board/amcc/bubinga/
F: include/configs/bubinga.h
YUCCA BOARD
-M: -
+#M: -
S: Maintained
F: board/amcc/yucca/
F: include/configs/yucca.h
VERSATILE BOARD
-M: -
+#M: -
S: Maintained
F: board/armltd/versatile/
F: include/configs/versatile.h
VEXPRESS BOARD
-M: -
+#M: -
S: Maintained
F: board/armltd/vexpress/
F: include/configs/vexpress_ca15_tc2.h
F: configs/vexpress_ca15_tc2_defconfig
VEXPRESS_CA5X2 BOARD
-M: Matt Waddel <matt.waddel@linaro.org>
+#M: Matt Waddel <matt.waddel@linaro.org>
S: Orphan (since 2014-08)
F: include/configs/vexpress_ca5x2.h
F: configs/vexpress_ca5x2_defconfig
ATNGW100 BOARD
-M: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+#M: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
S: Orphan (since 2014-06)
F: board/atmel/atngw100/
F: include/configs/atngw100.h
ATSTK1000 BOARD
-M: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+#M: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
S: Orphan (since 2014-06)
F: board/atmel/atstk1000/
F: include/configs/atstk1002.h
BC3450 BOARD
-M: -
+#M: -
S: Maintained
F: board/bc3450/
F: include/configs/BC3450.h
#endif
#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
+}
+
iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
SBC35_A9G20 BOARD
-
M: Albin Tonnerre <albin.tonnerre@free-electrons.com>
+
#M: Albin Tonnerre <albin.tonnerre@free-electrons.com>
S: Orphan (since 2014-06)
F: board/calao/sbc35_a9g20/
F: include/configs/sbc35_a9g20.h
TNY_A9260 BOARD
-
M: Albin Tonnerre <albin.tonnerre@free-electrons.com>
+
#M: Albin Tonnerre <albin.tonnerre@free-electrons.com>
S: Orphan (since 2014-06)
F: board/calao/tny_a9260/
F: include/configs/tny_a9260.h
CANMB BOARD
-M: -
+#M: -
S: Maintained
F: board/canmb/
F: include/configs/canmb.h
CM-BF527 BOARD
-M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
S: Orphan (since 2014-03)
F: board/cm-bf527/
F: include/configs/cm-bf527.h
CM-BF533 BOARD
-M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
S: Orphan (since 2014-03)
F: board/cm-bf533/
F: include/configs/cm-bf533.h
CM-BF537E BOARD
-M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
S: Orphan (since 2014-03)
F: board/cm-bf537e/
F: include/configs/cm-bf537e.h
CM-BF537U BOARD
-M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
S: Orphan (since 2014-03)
F: board/cm-bf537u/
F: include/configs/cm-bf537u.h
CM-BF548 BOARD
-M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
S: Orphan (since 2014-03)
F: board/cm-bf548/
F: include/configs/cm-bf548.h
CM-BF561 BOARD
-M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
S: Orphan (since 2014-03)
F: board/cm-bf561/
F: include/configs/cm-bf561.h
CM41XX BOARD
-M: -
+#M: -
S: Maintained
F: board/cm41xx/
F: include/configs/cm41xx.h
CM5200 BOARD
-M: -
+#M: -
S: Maintained
F: board/cm5200/
F: include/configs/cm5200.h
CMI BOARD
-M: -
+#M: -
S: Maintained
F: board/cmi/
F: include/configs/cmi_mpc5xx.h
COBRA5272 BOARD
-M: -
+#M: -
S: Maintained
F: board/cobra5272/
F: include/configs/cobra5272.h
CGTQMX6EVAL BOARD
-M: Leo Sartre <lsartre@adeneo-embedded.com>
+#M: Leo Sartre <lsartre@adeneo-embedded.com>
S: Orphan (since 2014-06)
F: board/congatec/cgtqmx6eval/
F: include/configs/cgtqmx6eval.h
CPU87 BOARD
-M: -
+#M: -
S: Maintained
F: board/cpu87/
F: include/configs/CPU87.h
L1 BOARD
-M: David Updegraff <dave@cray.com>
+#M: David Updegraff <dave@cray.com>
S: Orphan (since 2014-03)
F: board/cray/L1/
F: include/configs/CRAYL1.h
PPCHAMELEONEVB BOARD
-M: -
+#M: -
S: Maintained
F: board/dave/PPChameleonEVB/
F: include/configs/CATcenter.h
DM355EVM BOARD
-M: Sandeep Paulraj <s-paulraj@ti.com>
+#M: Sandeep Paulraj <s-paulraj@ti.com>
S: Orphan (since 2014-08)
F: board/davinci/dm355evm/
F: include/configs/davinci_dm355evm.h
DM355LEOPARD BOARD
-M: Sandeep Paulraj <s-paulraj@ti.com>
+#M: Sandeep Paulraj <s-paulraj@ti.com>
S: Orphan (since 2014-08)
F: board/davinci/dm355leopard/
F: include/configs/davinci_dm355leopard.h
DM365EVM BOARD
-M: Sandeep Paulraj <s-paulraj@ti.com>
+#M: Sandeep Paulraj <s-paulraj@ti.com>
S: Orphan (since 2014-08)
F: board/davinci/dm365evm/
F: include/configs/davinci_dm365evm.h
DM6467EVM BOARD
-M: Sandeep Paulraj <s-paulraj@ti.com>
+#M: Sandeep Paulraj <s-paulraj@ti.com>
S: Orphan (since 2014-08)
F: board/davinci/dm6467evm/
F: include/configs/davinci_dm6467evm.h
DVEVM BOARD
-M: -
+#M: -
S: Maintained
F: board/davinci/dvevm/
F: include/configs/davinci_dvevm.h
SCHMOOGIE BOARD
-M: -
+#M: -
S: Maintained
F: board/davinci/schmoogie/
F: include/configs/davinci_schmoogie.h
SFFSDR BOARD
-M: -
+#M: -
S: Maintained
F: board/davinci/sffsdr/
F: include/configs/davinci_sffsdr.h
SONATA BOARD
-M: -
+#M: -
S: Maintained
F: board/davinci/sonata/
F: include/configs/davinci_sonata.h
FAVR-32-EZKIT BOARD
-M: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
+#M: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
S: Orphan (since 2014-06)
F: board/earthlcd/favr-32-ezkit/
F: include/configs/favr-32-ezkit.h
ELPPC BOARD
-M: -
+#M: -
S: Maintained
F: board/eltec/elppc/
F: include/configs/ELPPC.h
+++ /dev/null
-/*
- * (C) Copyright 2001-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
+}
+
static void setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
EP8260 BOARD
-M: Frank Panno <fpanno@delphintech.com>
+#M: Frank Panno <fpanno@delphintech.com>
S: Orphan (since 2014-06)
F: board/ep8260/
F: include/configs/ep8260.h
EP82XXM BOARD
-M: -
+#M: -
S: Maintained
F: board/ep82xxm/
F: include/configs/ep82xxm.h
IMA3-MX53 BOARD
-M: -
+#M: -
S: Maintained
F: board/esg/ima3-mx53/
F: include/configs/ima3-mx53.h
ESPT BOARD
-M: -
+#M: -
S: Maintained
F: board/espt/
F: include/configs/espt.h
F: configs/P3G4_defconfig
ZUMA BOARD
-M: Nye Liu <nyet@zumanetworks.com>
+#M: Nye Liu <nyet@zumanetworks.com>
S: Orphan (since 2014-04)
F: include/configs/ZUMA.h
F: configs/ZUMA_defconfig
HWW1U1A BOARD
-M: Kyle Moffett <Kyle.D.Moffett@boeing.com>
+#M: Kyle Moffett <Kyle.D.Moffett@boeing.com>
S: Orphan (since 2014-06)
F: board/exmeritus/hww1u1a/
F: include/configs/HWW1U1A.h
B4860QDS BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/b4860qds/
F: include/configs/B4860QDS.h
continue;
/* Calculate the temp out frequency */
tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
- diff = MAX(out_freq, tmp_out) - MIN(out_freq, tmp_out);
+ diff = max(out_freq, tmp_out) - min(out_freq, tmp_out);
/*
* calculate the percent, the precision is 1/1000
* If greater than 1/1000, continue
CORENET_DS BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/corenet_ds/
F: include/configs/P3041DS.h
M5208EVBE BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/m5208evbe/
F: include/configs/M5208EVBE.h
M5249EVB BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/m5249evb/
F: include/configs/M5249EVB.h
M5253EVBE BOARD
-M: Hayden Fraser <Hayden.Fraser@freescale.com>
+#M: Hayden Fraser <Hayden.Fraser@freescale.com>
S: Orphan (since 2014-06)
F: board/freescale/m5253evbe/
F: include/configs/M5253EVBE.h
M5272C3 BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/m5272c3/
F: include/configs/M5272C3.h
M5275EVB BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/m5275evb/
F: include/configs/M5275EVB.h
M5282EVB BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/m5282evb/
F: include/configs/M5282EVB.h
M54418TWR BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/m54418twr/
F: include/configs/M54418TWR.h
M54451EVB BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/m54451evb/
F: include/configs/M54451EVB.h
MPC5121ADS BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/mpc5121ads/
F: include/configs/mpc5121ads.h
MPC8313ERDB BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/mpc8313erdb/
F: include/configs/MPC8313ERDB.h
MPC8349ITX BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/mpc8349itx/
F: include/configs/MPC8349ITX.h
MPC8360ERDK BOARD
-
M: Anton Vorontsov <avorontsov@ru.mvista.com>
+
#M: Anton Vorontsov <avorontsov@ru.mvista.com>
S: Orphan (since 2014-03)
F: board/freescale/mpc8360erdk/
F: include/configs/MPC8360ERDK.h
MPC837XERDB BOARD
-M: Joe D'Abbraccio <ljd015@freescale.com>
+#M: Joe D'Abbraccio <ljd015@freescale.com>
S: Orphan (since 2014-06)
F: board/freescale/mpc837xerdb/
F: include/configs/MPC837XERDB.h
MPC8536DS BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/mpc8536ds/
F: include/configs/MPC8536DS.h
MPC8540ADS BOARD
-M: Kumar Gala <kumar.gala@freescale.com>
+#M: Kumar Gala <kumar.gala@freescale.com>
S: Orphan (since 2014-06)
F: board/freescale/mpc8540ads/
F: include/configs/MPC8540ADS.h
MPC8541CDS BOARD
-M: Kumar Gala <kumar.gala@freescale.com>
+#M: Kumar Gala <kumar.gala@freescale.com>
S: Orphan (since 2014-06)
F: board/freescale/mpc8541cds/
F: include/configs/MPC8541CDS.h
MPC8544DS BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/mpc8544ds/
F: include/configs/MPC8544DS.h
MPC8548CDS BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/mpc8548cds/
F: include/configs/MPC8548CDS.h
MPC8555CDS BOARD
-M: Kumar Gala <kumar.gala@freescale.com>
+#M: Kumar Gala <kumar.gala@freescale.com>
S: Orphan (since 2014-06)
F: board/freescale/mpc8555cds/
F: include/configs/MPC8555CDS.h
MPC8560ADS BOARD
-M: Kumar Gala <kumar.gala@freescale.com>
+#M: Kumar Gala <kumar.gala@freescale.com>
S: Orphan (since 2014-06)
F: board/freescale/mpc8560ads/
F: include/configs/MPC8560ADS.h
MPC8568MDS BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/mpc8568mds/
F: include/configs/MPC8568MDS.h
MPC8569MDS BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/mpc8569mds/
F: include/configs/MPC8569MDS.h
MPC8610HPCD BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/mpc8610hpcd/
F: include/configs/MPC8610HPCD.h
MPC8641HPCN BOARD
-M: Kumar Gala <kumar.gala@freescale.com>
+#M: Kumar Gala <kumar.gala@freescale.com>
S: Orphan (since 2014-06)
F: board/freescale/mpc8641hpcn/
F: include/configs/MPC8641HPCN.h
MX31ADS BOARD
-M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+#M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
S: Orphan (since 2013-09)
F: board/freescale/mx31ads/
F: include/configs/mx31ads.h
return 0;
}
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
+}
+#endif
+
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
return 0;
}
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
+}
+#endif
+
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
+}
+
static void setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
P1010RDB BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/p1010rdb/
F: include/configs/P1010RDB.h
P1023RDB BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/p1023rdb/
F: include/configs/P1023RDB.h
P1_P2_RDB BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/p1_p2_rdb/
F: include/configs/P1_P2_RDB.h
P1_P2_RDB_PC BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/p1_p2_rdb_pc/
F: include/configs/p1_p2_rdb_pc.h
P1_TWR BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/p1_twr/
F: include/configs/p1_twr.h
P2020DS BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/p2020ds/
F: include/configs/P2020DS.h
P2041RDB BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/p2041rdb/
F: include/configs/P2041RDB.h
break;
case 0xA7:
lane_to_slot[1] = 7;
+ lane_to_slot[2] = 6;
+ lane_to_slot[3] = 5;
lane_to_slot[7] = 7;
break;
case 0xAA:
fm_info_set_phy_address(i, riser_phy_addr[1]);
if (FM1_DTSEC3 == i)
fm_info_set_phy_address(i, riser_phy_addr[2]);
+ if (FM1_DTSEC5 == i)
+ fm_info_set_phy_address(i, riser_phy_addr[3]);
mdio_mux[i] = EMI1_SLOT7;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
F: configs/T1040RDB_defconfig
F: configs/T1040RDB_NAND_defconfig
F: configs/T1040RDB_SPIFLASH_defconfig
+F: configs/T1042RDB_defconfig
F: configs/T1042RDB_PI_defconfig
F: configs/T1042RDB_PI_NAND_defconfig
F: configs/T1042RDB_PI_SPIFLASH_defconfig
T1040RDB_SDCARD BOARD
-M: -
+#M: -
S: Maintained
F: configs/T1040RDB_SDCARD_defconfig
F: configs/T1042RDB_PI_SDCARD_defconfig
(and variants). Variants inclued T1042 presonality of T1040, in which
case T1040RDB can also be called T1042RDB.
+The T1042RDB is a Freescale reference board that hosts the T1042 SoC
+(and variants). The board is similar to T1040RDB, T1040 is a reduced
+personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
+
The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
(a personality of T1040 SoC). The board is similar to T1040RDB but is
designed specially with low power features targeted for Printing Image Market.
+Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB
+-------------------------------------------------------------------------
+Board Si Protocol Targeted Market
+-------------------------------------------------------------------------
+T1040RDB T1040 0x66 Networking
+T1040RDB T1042 0x86 Networking
+T1042RDB_PI T1042 0x06 Printing & Imaging
+
+
T1040 SoC Overview
------------------
The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
Commands for switching to alternate bank.
1. To change from vbank0 to vbank4
- => qixis_reset altbank (it will boot using vbank4)
+ => cpld reset altbank (it will boot using vbank4)
2.To change from vbank4 to vbank0
- => qixis reset (it will boot using vbank0)
+ => cpld reset (it will boot using vbank0)
NAND boot with 2 Stage boot loader
----------------------------------
===============
NAND boot SW setting:
SW1: 10001000
-SW2: 00111001
+SW2: 00111011
SW3: 11110001
SPI boot SW setting:
SW1: 00100010
-SW2: 10111001
+SW2: 10111011
SW3: 11100001
SD boot SW setting:
SW1: 00100000
-SW2: 00111001
+SW2: 00111011
SW3: 11100001
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
}
phys_size_t initdram(int board_type)
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_SGMII1_PHY_ADDR);
break;
+#endif
+#ifdef CONFIG_T1042RDB
+ case PHY_INTERFACE_MODE_SGMII:
+ /* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
+ if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
+ fm_info_set_phy_address(i, 0);
+ /* T1042RDB only supports SGMII on DTSEC3 */
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_SGMII1_PHY_ADDR);
+ break;
#endif
case PHY_INTERFACE_MODE_RGMII:
if (FM1_DTSEC4 == i)
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x06
+0c18000e 0e000000 00000000 00000000
+06000002 00400002 e8106000 01000000
+00000000 00000000 00000000 00030810
+00000000 01fe0a06 00000000 00000000
#PBL preamble and RCW header
aa55aa55 010e0100
-# serdes protocol 0x66
+# serdes protocol 0x86
0c18000e 0e000000 00000000 00000000
-06000002 00400002 e8106000 01000000
-00000000 00000000 00000000 00030810
-00000000 01fe0a06 00000000 00000000
+86000002 80000002 ec027000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
T208XQDS BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/t208xqds/
F: include/configs/T208xQDS.h
T208XRDB BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/t208xrdb/
F: include/configs/T208xRDB.h
T4QDS BOARD
-M: -
+#M: -
S: Maintained
F: board/freescale/t4qds/
F: include/configs/T4240QDS.h
VOVPN-GW BOARD
-M: -
+#M: -
S: Maintained
F: board/funkwerk/vovpn-gw/
F: include/configs/VoVPN-GW.h
GR_CPCI_AX2000 BOARD
-M: -
+#M: -
S: Maintained
F: board/gaisler/gr_cpci_ax2000/
F: include/configs/gr_cpci_ax2000.h
GR_EP2S60 BOARD
-M: -
+#M: -
S: Maintained
F: board/gaisler/gr_ep2s60/
F: include/configs/gr_ep2s60.h
GR_XC3S_1500 BOARD
-M: -
+#M: -
S: Maintained
F: board/gaisler/gr_xc3s_1500/
F: include/configs/gr_xc3s_1500.h
GRSIM BOARD
-M: -
+#M: -
S: Maintained
F: board/gaisler/grsim/
F: include/configs/grsim.h
GRSIM_LEON2 BOARD
-M: -
+#M: -
S: Maintained
F: board/gaisler/grsim_leon2/
F: include/configs/grsim_leon2.h
GALAXY5200 BOARD
-M: Eric Millbrandt <emillbrandt@dekaresearch.com>
+#M: Eric Millbrandt <emillbrandt@dekaresearch.com>
S: Orphan (since 2014-06)
F: board/galaxy5200/
F: include/configs/galaxy5200.h
IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
};
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
+}
+
static void setup_spi(void)
{
- gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
+ gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
SETUP_IOMUX_PADS(ecspi1_pads);
}
#endif
MX51_EFIKAMX BOARD
-M: -
+#M: -
S: Maintained
F: board/genesi/mx51_efikamx/
F: include/configs/mx51_efikamx.h
* PMIC configuration
*/
#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 1) ? 121 : -1;
+}
+
static void power_init(void)
{
unsigned int val;
F: configs/icecube_5200_defconfig
ICECUBE_5200_DDR BOARD
-M: -
+#M: -
S: Maintained
F: configs/icecube_5200_DDR_defconfig
F: configs/icecube_5200_DDR_LOWBOOT_defconfig
IMX31_PHYCORE BOARD
-M: -
+#M: -
S: Maintained
F: board/imx31_phycore/
F: include/configs/imx31_phycore.h
F: configs/imx31_phycore_defconfig
IMX31_PHYCORE_EET BOARD
-M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+#M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
S: Orphan (since 2013-09)
F: configs/imx31_phycore_eet_defconfig
IP04 BOARD
-M: Brent Kandetzki <brentk@teleco.com>
+#M: Brent Kandetzki <brentk@teleco.com>
S: Orphan (since 2014-06)
F: board/ip04/
F: include/configs/ip04.h
F: configs/igep0032_defconfig
IGEP0020_NAND BOARD
-M: -
+#M: -
S: Maintained
F: configs/igep0020_nand_defconfig
F: configs/igep0030_nand_defconfig
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
TK71 BOARD
-M: -
+#M: -
S: Maintained
F: board/karo/tk71/
F: include/configs/tk71.h
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
IMX31_LITEKIT BOARD
-M: -
+#M: -
S: Maintained
F: board/logicpd/imx31_litekit/
F: include/configs/imx31_litekit.h
+++ /dev/null
-/*
- * (C) Copyright 2001-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
HMI1001 BOARD
-M: -
+#M: -
S: Maintained
F: board/manroland/hmi1001/
F: include/configs/hmi1001.h
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
MERGERBOX BOARD
-
M: Andre Schwarz <andre.schwarz@matrix-vision.de>
+
#M: Andre Schwarz <andre.schwarz@matrix-vision.de>
S: Orphan (since 2014-03)
F: board/matrix_vision/mergerbox/
F: include/configs/MERGERBOX.h
MVBC_P BOARD
-
M: Andre Schwarz <andre.schwarz@matrix-vision.de>
+
#M: Andre Schwarz <andre.schwarz@matrix-vision.de>
S: Orphan (since 2014-03)
F: board/matrix_vision/mvbc_p/
F: include/configs/MVBC_P.h
MVBLM7 BOARD
-
M: Andre Schwarz <andre.schwarz@matrix-vision.de>
+
#M: Andre Schwarz <andre.schwarz@matrix-vision.de>
S: Orphan (since 2014-03)
F: board/matrix_vision/mvblm7/
F: include/configs/MVBLM7.h
MVSMR BOARD
-
M: Andre Schwarz <andre.schwarz@matrix-vision.de>
+
#M: Andre Schwarz <andre.schwarz@matrix-vision.de>
S: Orphan (since 2014-03)
F: board/matrix_vision/mvsmr/
F: include/configs/MVSMR.h
MCC200 BOARD
-M: -
+#M: -
S: Maintained
F: board/mcc200/
F: include/configs/mcc200.h
VCT BOARD
-M: -
+#M: -
S: Maintained
F: board/micronas/vct/
F: include/configs/vct.h
MOTIONPRO BOARD
-M: -
+#M: -
S: Maintained
F: board/motionpro/
F: include/configs/motionpro.h
PATI BOARD
-M: -
+#M: -
S: Maintained
F: board/mpl/pati/
F: include/configs/PATI.h
MUNICES BOARD
-M: -
+#M: -
S: Maintained
F: board/munices/
F: include/configs/munices.h
MUSENKI BOARD
-M: Jim Thompson <jim@musenki.com>
+#M: Jim Thompson <jim@musenki.com>
S: Orphan (since 2014-04)
F: board/musenki/
F: include/configs/MUSENKI.h
MVBLUE BOARD
-M: -
+#M: -
S: Maintained
F: board/mvblue/
F: include/configs/MVBLUE.h
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
PALMTREO680 BOARD
-M: Mike Dunn <mikedunn@newsguy.com>
+#M: Mike Dunn <mikedunn@newsguy.com>
S: Orphan (since 2014-06)
F: board/palmtreo680/
F: include/configs/palmtreo680.h
PB1X00 BOARD
-M: -
+#M: -
S: Maintained
F: board/pb1x00/
F: include/configs/pb1x00.h
PM828 BOARD
-M: -
+#M: -
S: Maintained
F: board/pm828/
F: include/configs/PM828.h
PPMC7XX BOARD
-M: -
+#M: -
S: Maintained
F: board/ppmc7xx/
F: include/configs/ppmc7xx.h
PPMC8260 BOARD
-M: Brad Kemp <Brad.Kemp@seranoa.com>
+#M: Brad Kemp <Brad.Kemp@seranoa.com>
S: Orphan (since 2014-04)
F: board/ppmc8260/
F: include/configs/ppmc8260.h
F: configs/qemu_mips_defconfig
QEMU_MIPSEL BOARD
-M: -
+#M: -
S: Maintained
F: configs/qemu_mipsel_defconfig
F: include/configs/qemu-mips64.h
MIGOR BOARD
-M: -
+#M: -
S: Maintained
F: board/renesas/MigoR/
F: include/configs/MigoR.h
RSK7269 BOARD
-M: -
+#M: -
S: Maintained
F: board/renesas/rsk7269/
F: include/configs/rsk7269.h
SH7752EVB BOARD
-M: -
+#M: -
S: Maintained
F: board/renesas/sh7752evb/
F: include/configs/sh7752evb.h
SH7753EVB BOARD
-M: -
+#M: -
S: Maintained
F: board/renesas/sh7753evb/
F: include/configs/sh7753evb.h
SH7757LCR BOARD
-M: -
+#M: -
S: Maintained
F: board/renesas/sh7757lcr/
F: include/configs/sh7757lcr.h
SH7785LCR BOARD
-M: -
+#M: -
S: Maintained
F: board/renesas/sh7785lcr/
F: include/configs/sh7785lcr.h
SACSNG BOARD
-M: Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
+#M: Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
S: Orphan (since 2014-06)
F: board/sacsng/
F: include/configs/sacsng.h
KAREF BOARD
-M: Travis Sawyer <travis.sawyer@sandburst.com>
+#M: Travis Sawyer <travis.sawyer@sandburst.com>
S: Orphan (since 2014-03)
F: board/sandburst/karef/
F: include/configs/KAREF.h
METROBOX BOARD
-M: Travis Sawyer <travis.sawyer@sandburst.com>
+#M: Travis Sawyer <travis.sawyer@sandburst.com>
S: Orphan (since 2014-03)
F: board/sandburst/metrobox/
F: include/configs/METROBOX.h
F: configs/Sandpoint8240_defconfig
SANDPOINT8245 BOARD
-M: Jim Thompson <jim@musenki.com>
+#M: Jim Thompson <jim@musenki.com>
S: Orphan (since 2014-04)
F: include/configs/Sandpoint8245.h
F: configs/Sandpoint8245_defconfig
SBC405 BOARD
-M: -
+#M: -
S: Maintained
F: board/sbc405/
F: include/configs/sbc405.h
SOCRATES BOARD
-M: -
+#M: -
S: Maintained
F: board/socrates/
F: include/configs/socrates.h
F: configs/spear300_defconfig
SPEAR300_NAND BOARD
-M: -
+#M: -
S: Maintained
F: configs/spear300_nand_defconfig
F: configs/spear300_usbtty_defconfig
F: configs/spear310_defconfig
SPEAR310_NAND BOARD
-M: -
+#M: -
S: Maintained
F: configs/spear310_nand_defconfig
F: configs/spear310_pnor_defconfig
F: configs/spear320_defconfig
SPEAR320_NAND BOARD
-M: -
+#M: -
S: Maintained
F: configs/spear320_nand_defconfig
F: configs/spear320_pnor_defconfig
F: configs/spear600_defconfig
SPEAR600_NAND BOARD
-M: -
+#M: -
S: Maintained
F: configs/spear600_nand_defconfig
F: configs/spear600_usbtty_defconfig
U8500 BOARD
-M: -
+#M: -
S: Maintained
F: board/st-ericsson/u8500/
F: include/configs/u8500_href.h
STXGP3 BOARD
-M: Dan Malek <dan@embeddedalley.com>
+#M: Dan Malek <dan@embeddedalley.com>
S: Orphan (since 2014-06)
F: board/stx/stxgp3/
F: include/configs/stxgp3.h
STXSSA BOARD
-M: Dan Malek <dan@embeddedalley.com>
+#M: Dan Malek <dan@embeddedalley.com>
S: Orphan (since 2014-06)
F: board/stx/stxssa/
F: include/configs/stxssa.h
TCM-BF518 BOARD
-M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
S: Orphan (since 2014-03)
F: board/tcm-bf518/
F: include/configs/tcm-bf518.h
TCM-BF537 BOARD
-M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
S: Orphan (since 2014-03)
F: board/tcm-bf537/
F: include/configs/tcm-bf537.h
F: configs/omap3_evm_defconfig
OMAP3_EVM_QUICK_MMC BOARD
-M: -
+#M: -
S: Maintained
F: include/configs/omap3_evm_quick_mmc.h
F: configs/omap3_evm_quick_mmc_defconfig
TI816X BOARD
-M: -
+#M: -
S: Maintained
F: board/ti/ti816x/
F: include/configs/ti816x_evm.h
TNETV107XEVM BOARD
-M: Chan-Taek Park <c-park@ti.com>
+#M: Chan-Taek Park <c-park@ti.com>
S: Orphan (since 2014-06)
F: board/ti/tnetv107xevm/
F: include/configs/tnetv107x_evm.h
TOTAL5200 BOARD
-M: -
+#M: -
S: Maintained
F: board/total5200/
F: include/configs/Total5200.h
TQM5200 BOARD
-M: -
+#M: -
S: Maintained
F: board/tqc/tqm5200/
F: include/configs/aev.h
TQM8272 BOARD
-M: -
+#M: -
S: Maintained
F: board/tqc/tqm8272/
F: include/configs/TQM8272.h
TQM834X BOARD
-M: -
+#M: -
S: Maintained
F: board/tqc/tqm834x/
F: include/configs/TQM834x.h
F: configs/wtk_defconfig
NSCU BOARD
-M: -
+#M: -
S: Maintained
F: include/configs/NSCU.h
F: configs/NSCU_defconfig
}
#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 1) ? 121 : -1;
+}
+
void spi_io_init(void)
{
static const iomux_v3_cfg_t spi_pads[] = {
V38B BOARD
-M: -
+#M: -
S: Maintained
F: board/v38b/
F: include/configs/v38b.h
F: configs/woodburn_defconfig
WOODBURN_SD BOARD
-M: -
+#M: -
S: Maintained
F: include/configs/woodburn_sd.h
F: configs/woodburn_sd_defconfig
XAENIAX BOARD
-M: -
+#M: -
S: Maintained
F: board/xaeniax/
F: include/configs/xaeniax.h
XPEDITE517X BOARD
-M: -
+#M: -
S: Maintained
F: board/xes/xpedite517x/
F: include/configs/xpedite517x.h
XPEDITE520X BOARD
-M: -
+#M: -
S: Maintained
F: board/xes/xpedite520x/
F: include/configs/xpedite520x.h
XPEDITE537X BOARD
-M: -
+#M: -
S: Maintained
F: board/xes/xpedite537x/
F: include/configs/xpedite537x.h
XPEDITE550X BOARD
-M: -
+#M: -
S: Maintained
F: board/xes/xpedite550x/
F: include/configs/xpedite550x.h
--- /dev/null
+menu "Command line interface"
+ depends on !SPL_BUILD
+
+config CMD_BOOTM
+ bool "Enable bootm command"
+ default y
+ help
+ Boot an application image from the memory.
+
+config CMD_CRC32
+ bool "Enable crc32 command"
+ default y
+ help
+ Compute CRC32.
+
+config CMD_EXPORTENV
+ bool "Enable env export command"
+ default y
+ help
+ Export environments.
+
+config CMD_IMPORTENV
+ bool "Enable env import command"
+ default y
+ help
+ Import environments.
+
+config CMD_GO
+ bool "Enable go command"
+ default y
+ help
+ Start an application at a given address.
+
+endmenu
#environment
obj-y += env_common.o
#others
-ifdef CONFIG_DDR_SPD
-SPD := y
-endif
-ifdef CONFIG_SPD_EEPROM
-SPD := y
-endif
-obj-$(SPD) += ddr_spd.o
+obj-$(CONFIG_DDR_SPD) += ddr_spd.o
+obj-$(CONFIG_SPD_EEPROM) += ddr_spd.o
obj-$(CONFIG_HWCONFIG) += hwconfig.o
obj-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o
obj-y += console.o
obj-y += memsize.o
obj-y += stdio.o
+# This option is not just y/n - it can have a numeric value
+ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+obj-y += aboot.o
+obj-y += fb_mmc.o
+endif
+
CFLAGS_env_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null)
}
U_BOOT_CMD(
- fastboot, 1, 1, do_fastboot,
- "fastboot - enter USB Fastboot protocol",
- ""
+ fastboot, 1, 0, do_fastboot,
+ "use USB Fastboot protocol",
+ "\n"
+ " - run as a fastboot usb device"
);
read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
printf("\nNAND %s: ", read ? "read" : "write");
- nand = &nand_info[dev];
-
s = strchr(cmd, '.');
if (s && !strcmp(s, ".raw")) {
if (arg_off(argv[3], &dev, &off, &size, &maxsize))
return 1;
+ nand = &nand_info[dev];
+
if (argc > 4 && !str2long(argv[4], &pagecount)) {
printf("'%s' is not a number\n", argv[4]);
return 1;
rwsize = size;
}
+ nand = &nand_info[dev];
+
if (!s || !strcmp(s, ".jffs2") ||
!strcmp(s, ".e") || !strcmp(s, ".i")) {
if (read)
#include <asm/io.h>
-#ifndef CONFIG_SF_DEFAULT_SPEED
-# define CONFIG_SF_DEFAULT_SPEED 1000000
-#endif
-#ifndef CONFIG_SF_DEFAULT_MODE
-# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
-#endif
-#ifndef CONFIG_SF_DEFAULT_CS
-# define CONFIG_SF_DEFAULT_CS 0
-#endif
-#ifndef CONFIG_SF_DEFAULT_BUS
-# define CONFIG_SF_DEFAULT_BUS 0
-#endif
-
static struct spi_flash *flash;
static int ctrlc_was_pressed = 0;
int ctrlc(void)
{
+#ifndef CONFIG_SANDBOX
if (!ctrlc_disabled && gd->have_console) {
if (tstc()) {
switch (getc()) {
}
}
}
+#endif
+
return 0;
}
/* Reads user's confirmation.
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fb_mmc.h>
+#include <part.h>
+#include <aboot.h>
+#include <sparse_format.h>
+
+/* The 64 defined bytes plus the '\0' */
+#define RESPONSE_LEN (64 + 1)
+
+static char *response_str;
+
+void fastboot_fail(const char *s)
+{
+ strncpy(response_str, "FAIL", 4);
+ strncat(response_str, s, RESPONSE_LEN - 4 - 1);
+}
+
+void fastboot_okay(const char *s)
+{
+ strncpy(response_str, "OKAY", 4);
+ strncat(response_str, s, RESPONSE_LEN - 4 - 1);
+}
+
+static void write_raw_image(block_dev_desc_t *dev_desc, disk_partition_t *info,
+ const char *part_name, void *buffer,
+ unsigned int download_bytes)
+{
+ lbaint_t blkcnt;
+ lbaint_t blks;
+
+ /* determine number of blocks to write */
+ blkcnt = ((download_bytes + (info->blksz - 1)) & ~(info->blksz - 1));
+ blkcnt = blkcnt / info->blksz;
+
+ if (blkcnt > info->size) {
+ error("too large for partition: '%s'\n", part_name);
+ fastboot_fail("too large for partition");
+ return;
+ }
+
+ puts("Flashing Raw Image\n");
+
+ blks = dev_desc->block_write(dev_desc->dev, info->start, blkcnt,
+ buffer);
+ if (blks != blkcnt) {
+ error("failed writing to device %d\n", dev_desc->dev);
+ fastboot_fail("failed writing to device");
+ return;
+ }
+
+ printf("........ wrote " LBAFU " bytes to '%s'\n", blkcnt * info->blksz,
+ part_name);
+ fastboot_okay("");
+}
+
+void fb_mmc_flash_write(const char *cmd, void *download_buffer,
+ unsigned int download_bytes, char *response)
+{
+ int ret;
+ block_dev_desc_t *dev_desc;
+ disk_partition_t info;
+
+ /* initialize the response buffer */
+ response_str = response;
+
+ dev_desc = get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+ if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+ error("invalid mmc device\n");
+ fastboot_fail("invalid mmc device");
+ return;
+ }
+
+ ret = get_partition_info_efi_by_name(dev_desc, cmd, &info);
+ if (ret) {
+ error("cannot find partition: '%s'\n", cmd);
+ fastboot_fail("cannot find partition");
+ return;
+ }
+
+ if (is_sparse_image(download_buffer))
+ write_sparse_image(dev_desc, &info, cmd, download_buffer,
+ download_bytes);
+ else
+ write_raw_image(dev_desc, &info, cmd, download_buffer,
+ download_bytes);
+}
sinclude $(srctree)/board/$(BOARDDIR)/config.mk # include board specific rules
endif
+ifdef FTRACE
+PLATFORM_CPPFLAGS += -finstrument-functions -DFTRACE
+endif
+
#########################################################################
RELFLAGS := $(PLATFORM_RELFLAGS)
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT,ENABLE_VBOOT"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_ARNDALE=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
CONFIG_BLACKFIN=y
CONFIG_TARGET_BCT_BRETTL2=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA30=y
+S:CONFIG_TARGET_BEAVER=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver"
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF506F_EZKIT=y
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF518F_EZBRD=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF526_EZBRD=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF527_AD7160_EVAL=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_SYS_EXTRA_OPTIONS="BF527_EZKIT_REV_2_1"
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF527_EZKIT=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF527_EZKIT=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF527_SDP=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF533_EZKIT=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF533_STAMP=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF537_STAMP=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF538F_EZKIT=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF548_EZKIT=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF561_ACVILON=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF561_EZKIT=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_BR4=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA30=y
+S:CONFIG_TARGET_CARDHU=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-cardhu"
CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF527=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF533=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF537E=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF537U=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF548=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF561=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_COLIBRI_T20_IRIS=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri_t20_iris"
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA30=y
+S:CONFIG_TARGET_COLIBRI_T30=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_CONTROLCENTERD=y
+# CONFIG_CMD_BOOTM is not set
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_CONTROLCENTERD=y
+# CONFIG_CMD_BOOTM is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x01110000"
CONFIG_X86=y
CONFIG_TARGET_COREBOOT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="link"
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA114=y
+S:CONFIG_TARGET_DALMORE=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore"
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_HARMONY=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony"
CONFIG_BLACKFIN=y
CONFIG_TARGET_IP04=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA124=y
+S:CONFIG_TARGET_JETSON_TK1=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1"
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_KWB=y
+# CONFIG_CMD_CRC32 is not set
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_MEDCOM_WIDE=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-medcom-wide"
CONFIG_SPL=y
+S:CONFIG_MICROBLAZE=y
+S:CONFIG_TARGET_MICROBLAZE_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_ODROID=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid"
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_ORIGEN=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_PAZ00=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-paz00"
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_PEACH_PIT=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit"
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_PLUTUX=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-plutux"
CONFIG_BLACKFIN=y
CONFIG_TARGET_PR1=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_S5PC210_UNIVERSAL=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210"
+CONFIG_OF_CONTROL=y
+CONFIG_OF_HOSTFILE=y
+CONFIG_DEFAULT_DEVICE_TREE="sandbox"
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_SEABOARD=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard"
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_SMDK5250=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250"
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_SMDK5420=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420"
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_EXYNOS=y
+S:CONFIG_TARGET_SNOW=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
CONFIG_BLACKFIN=y
CONFIG_TARGET_TCM_BF518=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_TCM_BF537=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA30=y
+S:CONFIG_TARGET_TEC_NG=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-tec-ng"
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_TEC=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-tec"
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_TRATS2=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2"
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_TRATS=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats"
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_TRIMSLICE=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-trimslice"
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_TSERIES=y
+# CONFIG_CMD_CRC32 is not set
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_TSERIES=y
+# CONFIG_CMD_CRC32 is not set
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_TSERIES=y
+# CONFIG_CMD_CRC32 is not set
CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+# CONFIG_CMD_CRC32 is not set
CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+# CONFIG_CMD_CRC32 is not set
CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+# CONFIG_CMD_CRC32 is not set
CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+# CONFIG_CMD_CRC32 is not set
CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+# CONFIG_CMD_CRC32 is not set
CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+# CONFIG_CMD_CRC32 is not set
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA124=y
+S:CONFIG_TARGET_VENICE2=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2"
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_VENTANA=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-ventana"
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_AEMV8A=y
+CONFIG_DEFAULT_DEVICE_TREE="vexpress64"
CONFIG_SYS_EXTRA_OPTIONS="SEMIHOSTING,BASE_FVP"
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_AEMV8A=y
+CONFIG_DEFAULT_DEVICE_TREE="vexpress64"
+S:CONFIG_TEGRA=y
+S:CONFIG_TEGRA20=y
+S:CONFIG_TARGET_WHISTLER=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-whistler"
+S:CONFIG_ARM=y
+S:CONFIG_ZYNQ=y
+S:CONFIG_TARGET_ZYNQ_MICROZED=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
+S:CONFIG_ARM=y
+S:CONFIG_ZYNQ=y
+S:CONFIG_TARGET_ZYNQ_ZC70X=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
+S:CONFIG_ARM=y
+S:CONFIG_ZYNQ=y
+S:CONFIG_TARGET_ZYNQ_ZC770=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
+S:CONFIG_ARM=y
+S:CONFIG_ZYNQ=y
+S:CONFIG_TARGET_ZYNQ_ZC770=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
+S:CONFIG_ARM=y
+S:CONFIG_ZYNQ=y
+S:CONFIG_TARGET_ZYNQ_ZC770=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
+S:CONFIG_ARM=y
+S:CONFIG_ZYNQ=y
+S:CONFIG_TARGET_ZYNQ_ZED=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
* Overflowless variant of (block_count * mul_by / div_by)
* when div_by > mul_by
*/
-static lba512_t lba512_muldiv (lba512_t block_count, lba512_t mul_by, lba512_t div_by)
+static lba512_t lba512_muldiv(lba512_t block_count, lba512_t mul_by, lba512_t div_by)
{
lba512_t bc_quot, bc_rem;
lba512 = (lba * (dev_desc->blksz/512));
/* round to 1 digit */
- mb = lba512_muldiv(lba512, 10, 2048); /* 2048 = (1024 * 1024) / 512 MB */
+ /* 2048 = (1024 * 1024) / 512 MB */
+ mb = lba512_muldiv(lba512, 10, 2048);
mb_quot = mb / 10;
mb_rem = mb - (10 * mb_quot);
#ifdef HAVE_BLOCK_DEVICE
-void init_part (block_dev_desc_t * dev_desc)
+void init_part(block_dev_desc_t *dev_desc)
{
#ifdef CONFIG_ISO_PARTITION
if (test_part_iso(dev_desc) == 0) {
defined(CONFIG_AMIGA_PARTITION) || \
defined(CONFIG_EFI_PARTITION)
-static void print_part_header (const char *type, block_dev_desc_t * dev_desc)
+static void print_part_header(const char *type, block_dev_desc_t *dev_desc)
{
puts ("\nPartition Map for ");
switch (dev_desc->if_type) {
The protocol that is used over USB is described in
README.android-fastboot-protocol in same directory.
-The current implementation does not yet support the flash and erase
-commands.
+The current implementation does not yet support the erase command or the
+"oem format" command, and there is minimal support for the flash command;
+it only supports eMMC devices.
Client installation
===================
FreeBSD 11 (Current):
--------------------
Since llvm 3.4 is currently in the base system, the integrated as is
-incapable of building U-Boot. Therefore gas from devel/arm-eabi-binutils
+incapable of building U-Boot. Therefore gas from devel/arm-gnueabi-binutils
is used instead. It needs a symlinks to be picked up correctly though:
-ln -s /usr/local/bin/arm-eabi-as /usr/bin/arm-freebsd-eabi-as
+ln -s /usr/local/bin/arm-gnueabi-freebsd-as /usr/bin/arm-freebsd-eabi-as
# The following commands compile U-Boot using the clang xdev toolchain.
# NOTE: CROSS_COMPILE and target differ on purpose!
-export CROSS_COMPILE=arm-eabi-
+export CROSS_COMPILE=arm-gnueabi-freebsd-
gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" rpi_b_defconfig
gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" -j8
Given that u-boot will default to gcc, above commands can be
simplified with a simple wrapper script, listed below.
-/usr/local/bin/arm-eabi-gcc
+/usr/local/bin/arm-gnueabi-freebsd-gcc
---
#!/bin/sh
Platform specific options
=========================
+ CONFIG_NAND_DENALI
+ Enables the denali.c driver.
+
+ CONFIG_SYS_NAND_DENALI_64BIT
+ Indicates that the Denali NAND controller is the 64-bit variant.
+
CONFIG_NAND_OMAP_GPMC
Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
GPMC controller is used for parallel NAND flash devices, and can
--- /dev/null
+menu "Device Drivers"
+
+source "drivers/core/Kconfig"
+
+source "drivers/pci/Kconfig"
+
+source "drivers/pcmcia/Kconfig"
+
+source "drivers/mtd/Kconfig"
+
+source "drivers/block/Kconfig"
+
+source "drivers/misc/Kconfig"
+
+source "drivers/net/Kconfig"
+
+source "drivers/input/Kconfig"
+
+source "drivers/serial/Kconfig"
+
+source "drivers/tpm/Kconfig"
+
+source "drivers/i2c/Kconfig"
+
+source "drivers/spi/Kconfig"
+
+source "drivers/gpio/Kconfig"
+
+source "drivers/power/Kconfig"
+
+source "drivers/hwmon/Kconfig"
+
+source "drivers/watchdog/Kconfig"
+
+source "drivers/video/Kconfig"
+
+source "drivers/sound/Kconfig"
+
+source "drivers/usb/Kconfig"
+
+source "drivers/dfu/Kconfig"
+
+source "drivers/mmc/Kconfig"
+
+source "drivers/rtc/Kconfig"
+
+source "drivers/dma/Kconfig"
+
+source "drivers/crypto/Kconfig"
+
+endmenu
+obj-$(CONFIG_DM) += core/
+obj-$(CONFIG_DM_DEMO) += demo/
obj-$(CONFIG_BIOSEMU) += bios_emulator/
obj-y += block/
obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
obj-$(CONFIG_QE) += qe/
obj-y += memory/
obj-y += pwm/
+obj-y += input/
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_DM) := device.o lists.o root.o uclass.o util.o
+obj-y := device.o lists.o root.o uclass.o util.o
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_DM_DEMO) += demo-uclass.o demo-pdata.o
+obj-y += demo-uclass.o demo-pdata.o
obj-$(CONFIG_DM_DEMO_SIMPLE) += demo-simple.o
obj-$(CONFIG_DM_DEMO_SHAPE) += demo-shape.o
uint xfer_size;
while (count) {
- xfer_size = MIN(FSL_DMA_MAX_SIZE, count);
+ xfer_size = min(FSL_DMA_MAX_SIZE, count);
out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF));
out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF));
int shift = (alen-1) * 8;
while (alen) {
- int transfer = MIN(alen, 2);
+ int transfer = min(alen, 2);
uchar buf[2];
bool is_last = alen <= transfer;
return 1;
while (len) {
- int transfer = MIN(len, 2);
+ int transfer = min(len, 2);
if (ihs_i2c_transfer(chip, buffer, transfer, read,
len <= transfer))
#endif
cfg->cfg.f_min = 400000;
- cfg->cfg.f_max = MIN(gd->arch.sdhc_clk, 52000000);
+ cfg->cfg.f_max = min(gd->arch.sdhc_clk, 52000000);
cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
+obj-$(CONFIG_NAND_DENALI) += denali.o
obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
/* Row address */
- hwctrl(&nand_info[0], (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
- hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
+ if (cmd != NAND_CMD_RNDOUT) {
+ hwctrl(&nand_info[0], (page_addr & 0xff),
+ NAND_CTRL_ALE); /* A[19:12] */
+ hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
NAND_CTRL_ALE); /* A[27:20] */
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
- /* One more address cycle for devices > 128MiB */
- hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
+ /* One more address cycle for devices > 128MiB */
+ hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
NAND_CTRL_ALE); /* A[31:28] */
#endif
+ }
+
hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
if (cmd == NAND_CMD_READ0) {
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
+ * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <nand.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+
+#include "denali.h"
+
+#define NAND_DEFAULT_TIMINGS -1
+
+static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
+
+/* We define a macro here that combines all interrupts this driver uses into
+ * a single constant value, for convenience. */
+#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
+ INTR_STATUS__ECC_TRANSACTION_DONE | \
+ INTR_STATUS__ECC_ERR | \
+ INTR_STATUS__PROGRAM_FAIL | \
+ INTR_STATUS__LOAD_COMP | \
+ INTR_STATUS__PROGRAM_COMP | \
+ INTR_STATUS__TIME_OUT | \
+ INTR_STATUS__ERASE_FAIL | \
+ INTR_STATUS__RST_COMP | \
+ INTR_STATUS__ERASE_COMP | \
+ INTR_STATUS__ECC_UNCOR_ERR | \
+ INTR_STATUS__INT_ACT | \
+ INTR_STATUS__LOCKED_BLK)
+
+/* indicates whether or not the internal value for the flash bank is
+ * valid or not */
+#define CHIP_SELECT_INVALID -1
+
+#define SUPPORT_8BITECC 1
+
+/*
+ * this macro allows us to convert from an MTD structure to our own
+ * device context (denali) structure.
+ */
+#define mtd_to_denali(m) (((struct nand_chip *)mtd->priv)->priv)
+
+/* These constants are defined by the driver to enable common driver
+ * configuration options. */
+#define SPARE_ACCESS 0x41
+#define MAIN_ACCESS 0x42
+#define MAIN_SPARE_ACCESS 0x43
+
+#define DENALI_UNLOCK_START 0x10
+#define DENALI_UNLOCK_END 0x11
+#define DENALI_LOCK 0x21
+#define DENALI_LOCK_TIGHT 0x31
+#define DENALI_BUFFER_LOAD 0x60
+#define DENALI_BUFFER_WRITE 0x62
+
+#define DENALI_READ 0
+#define DENALI_WRITE 0x100
+
+/* types of device accesses. We can issue commands and get status */
+#define COMMAND_CYCLE 0
+#define ADDR_CYCLE 1
+#define STATUS_CYCLE 2
+
+/* this is a helper macro that allows us to
+ * format the bank into the proper bits for the controller */
+#define BANK(x) ((x) << 24)
+
+/* Interrupts are cleared by writing a 1 to the appropriate status bit */
+static inline void clear_interrupt(struct denali_nand_info *denali,
+ uint32_t irq_mask)
+{
+ uint32_t intr_status_reg;
+
+ intr_status_reg = INTR_STATUS(denali->flash_bank);
+
+ writel(irq_mask, denali->flash_reg + intr_status_reg);
+}
+
+static uint32_t read_interrupt_status(struct denali_nand_info *denali)
+{
+ uint32_t intr_status_reg;
+
+ intr_status_reg = INTR_STATUS(denali->flash_bank);
+
+ return readl(denali->flash_reg + intr_status_reg);
+}
+
+static void clear_interrupts(struct denali_nand_info *denali)
+{
+ uint32_t status;
+
+ status = read_interrupt_status(denali);
+ clear_interrupt(denali, status);
+
+ denali->irq_status = 0;
+}
+
+static void denali_irq_enable(struct denali_nand_info *denali,
+ uint32_t int_mask)
+{
+ int i;
+
+ for (i = 0; i < denali->max_banks; ++i)
+ writel(int_mask, denali->flash_reg + INTR_EN(i));
+}
+
+static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
+{
+ unsigned long timeout = 1000000;
+ uint32_t intr_status;
+
+ do {
+ intr_status = read_interrupt_status(denali) & DENALI_IRQ_ALL;
+ if (intr_status & irq_mask) {
+ denali->irq_status &= ~irq_mask;
+ /* our interrupt was detected */
+ break;
+ }
+ udelay(1);
+ timeout--;
+ } while (timeout != 0);
+
+ if (timeout == 0) {
+ /* timeout */
+ printf("Denali timeout with interrupt status %08x\n",
+ read_interrupt_status(denali));
+ intr_status = 0;
+ }
+ return intr_status;
+}
+
+/*
+ * Certain operations for the denali NAND controller use an indexed mode to
+ * read/write data. The operation is performed by writing the address value
+ * of the command to the device memory followed by the data. This function
+ * abstracts this common operation.
+*/
+static void index_addr(struct denali_nand_info *denali,
+ uint32_t address, uint32_t data)
+{
+ writel(address, denali->flash_mem + INDEX_CTRL_REG);
+ writel(data, denali->flash_mem + INDEX_DATA_REG);
+}
+
+/* Perform an indexed read of the device */
+static void index_addr_read_data(struct denali_nand_info *denali,
+ uint32_t address, uint32_t *pdata)
+{
+ writel(address, denali->flash_mem + INDEX_CTRL_REG);
+ *pdata = readl(denali->flash_mem + INDEX_DATA_REG);
+}
+
+/* We need to buffer some data for some of the NAND core routines.
+ * The operations manage buffering that data. */
+static void reset_buf(struct denali_nand_info *denali)
+{
+ denali->buf.head = 0;
+ denali->buf.tail = 0;
+}
+
+static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
+{
+ denali->buf.buf[denali->buf.tail++] = byte;
+}
+
+/* resets a specific device connected to the core */
+static void reset_bank(struct denali_nand_info *denali)
+{
+ uint32_t irq_status;
+ uint32_t irq_mask = INTR_STATUS__RST_COMP |
+ INTR_STATUS__TIME_OUT;
+
+ clear_interrupts(denali);
+
+ writel(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
+
+ irq_status = wait_for_irq(denali, irq_mask);
+ if (irq_status & INTR_STATUS__TIME_OUT)
+ debug("reset bank failed.\n");
+}
+
+/* Reset the flash controller */
+static uint32_t denali_nand_reset(struct denali_nand_info *denali)
+{
+ uint32_t i;
+
+ for (i = 0; i < denali->max_banks; i++)
+ writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
+ denali->flash_reg + INTR_STATUS(i));
+
+ for (i = 0; i < denali->max_banks; i++) {
+ writel(1 << i, denali->flash_reg + DEVICE_RESET);
+ while (!(readl(denali->flash_reg + INTR_STATUS(i)) &
+ (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
+ if (readl(denali->flash_reg + INTR_STATUS(i)) &
+ INTR_STATUS__TIME_OUT)
+ debug("NAND Reset operation timed out on bank"
+ " %d\n", i);
+ }
+
+ for (i = 0; i < denali->max_banks; i++)
+ writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
+ denali->flash_reg + INTR_STATUS(i));
+
+ return 0;
+}
+
+/*
+ * this routine calculates the ONFI timing values for a given mode and
+ * programs the clocking register accordingly. The mode is determined by
+ * the get_onfi_nand_para routine.
+ */
+static void nand_onfi_timing_set(struct denali_nand_info *denali,
+ uint16_t mode)
+{
+ uint32_t trea[6] = {40, 30, 25, 20, 20, 16};
+ uint32_t trp[6] = {50, 25, 17, 15, 12, 10};
+ uint32_t treh[6] = {30, 15, 15, 10, 10, 7};
+ uint32_t trc[6] = {100, 50, 35, 30, 25, 20};
+ uint32_t trhoh[6] = {0, 15, 15, 15, 15, 15};
+ uint32_t trloh[6] = {0, 0, 0, 0, 5, 5};
+ uint32_t tcea[6] = {100, 45, 30, 25, 25, 25};
+ uint32_t tadl[6] = {200, 100, 100, 100, 70, 70};
+ uint32_t trhw[6] = {200, 100, 100, 100, 100, 100};
+ uint32_t trhz[6] = {200, 100, 100, 100, 100, 100};
+ uint32_t twhr[6] = {120, 80, 80, 60, 60, 60};
+ uint32_t tcs[6] = {70, 35, 25, 25, 20, 15};
+
+ uint32_t tclsrising = 1;
+ uint32_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
+ uint32_t dv_window = 0;
+ uint32_t en_lo, en_hi;
+ uint32_t acc_clks;
+ uint32_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
+
+ en_lo = DIV_ROUND_UP(trp[mode], CLK_X);
+ en_hi = DIV_ROUND_UP(treh[mode], CLK_X);
+ if ((en_hi * CLK_X) < (treh[mode] + 2))
+ en_hi++;
+
+ if ((en_lo + en_hi) * CLK_X < trc[mode])
+ en_lo += DIV_ROUND_UP((trc[mode] - (en_lo + en_hi) * CLK_X),
+ CLK_X);
+
+ if ((en_lo + en_hi) < CLK_MULTI)
+ en_lo += CLK_MULTI - en_lo - en_hi;
+
+ while (dv_window < 8) {
+ data_invalid_rhoh = en_lo * CLK_X + trhoh[mode];
+
+ data_invalid_rloh = (en_lo + en_hi) * CLK_X + trloh[mode];
+
+ data_invalid =
+ data_invalid_rhoh <
+ data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh;
+
+ dv_window = data_invalid - trea[mode];
+
+ if (dv_window < 8)
+ en_lo++;
+ }
+
+ acc_clks = DIV_ROUND_UP(trea[mode], CLK_X);
+
+ while (((acc_clks * CLK_X) - trea[mode]) < 3)
+ acc_clks++;
+
+ if ((data_invalid - acc_clks * CLK_X) < 2)
+ debug("%s, Line %d: Warning!\n", __FILE__, __LINE__);
+
+ addr_2_data = DIV_ROUND_UP(tadl[mode], CLK_X);
+ re_2_we = DIV_ROUND_UP(trhw[mode], CLK_X);
+ re_2_re = DIV_ROUND_UP(trhz[mode], CLK_X);
+ we_2_re = DIV_ROUND_UP(twhr[mode], CLK_X);
+ cs_cnt = DIV_ROUND_UP((tcs[mode] - trp[mode]), CLK_X);
+ if (!tclsrising)
+ cs_cnt = DIV_ROUND_UP(tcs[mode], CLK_X);
+ if (cs_cnt == 0)
+ cs_cnt = 1;
+
+ if (tcea[mode]) {
+ while (((cs_cnt * CLK_X) + trea[mode]) < tcea[mode])
+ cs_cnt++;
+ }
+
+ /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
+ if ((readl(denali->flash_reg + MANUFACTURER_ID) == 0) &&
+ (readl(denali->flash_reg + DEVICE_ID) == 0x88))
+ acc_clks = 6;
+
+ writel(acc_clks, denali->flash_reg + ACC_CLKS);
+ writel(re_2_we, denali->flash_reg + RE_2_WE);
+ writel(re_2_re, denali->flash_reg + RE_2_RE);
+ writel(we_2_re, denali->flash_reg + WE_2_RE);
+ writel(addr_2_data, denali->flash_reg + ADDR_2_DATA);
+ writel(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
+ writel(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
+ writel(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
+}
+
+/* queries the NAND device to see what ONFI modes it supports. */
+static uint32_t get_onfi_nand_para(struct denali_nand_info *denali)
+{
+ int i;
+ /*
+ * we needn't to do a reset here because driver has already
+ * reset all the banks before
+ */
+ if (!(readl(denali->flash_reg + ONFI_TIMING_MODE) &
+ ONFI_TIMING_MODE__VALUE))
+ return -EIO;
+
+ for (i = 5; i > 0; i--) {
+ if (readl(denali->flash_reg + ONFI_TIMING_MODE) &
+ (0x01 << i))
+ break;
+ }
+
+ nand_onfi_timing_set(denali, i);
+
+ /* By now, all the ONFI devices we know support the page cache */
+ /* rw feature. So here we enable the pipeline_rw_ahead feature */
+ return 0;
+}
+
+static void get_samsung_nand_para(struct denali_nand_info *denali,
+ uint8_t device_id)
+{
+ if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
+ /* Set timing register values according to datasheet */
+ writel(5, denali->flash_reg + ACC_CLKS);
+ writel(20, denali->flash_reg + RE_2_WE);
+ writel(12, denali->flash_reg + WE_2_RE);
+ writel(14, denali->flash_reg + ADDR_2_DATA);
+ writel(3, denali->flash_reg + RDWR_EN_LO_CNT);
+ writel(2, denali->flash_reg + RDWR_EN_HI_CNT);
+ writel(2, denali->flash_reg + CS_SETUP_CNT);
+ }
+}
+
+static void get_toshiba_nand_para(struct denali_nand_info *denali)
+{
+ uint32_t tmp;
+
+ /* Workaround to fix a controller bug which reports a wrong */
+ /* spare area size for some kind of Toshiba NAND device */
+ if ((readl(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
+ (readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
+ writel(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
+ tmp = readl(denali->flash_reg + DEVICES_CONNECTED) *
+ readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
+ writel(tmp, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
+ }
+}
+
+static void get_hynix_nand_para(struct denali_nand_info *denali,
+ uint8_t device_id)
+{
+ uint32_t main_size, spare_size;
+
+ switch (device_id) {
+ case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
+ case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
+ writel(128, denali->flash_reg + PAGES_PER_BLOCK);
+ writel(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
+ writel(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
+ main_size = 4096 *
+ readl(denali->flash_reg + DEVICES_CONNECTED);
+ spare_size = 224 *
+ readl(denali->flash_reg + DEVICES_CONNECTED);
+ writel(main_size, denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
+ writel(spare_size, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
+ writel(0, denali->flash_reg + DEVICE_WIDTH);
+ break;
+ default:
+ debug("Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
+ "Will use default parameter values instead.\n",
+ device_id);
+ }
+}
+
+/*
+ * determines how many NAND chips are connected to the controller. Note for
+ * Intel CE4100 devices we don't support more than one device.
+ */
+static void find_valid_banks(struct denali_nand_info *denali)
+{
+ uint32_t id[denali->max_banks];
+ int i;
+
+ denali->total_used_banks = 1;
+ for (i = 0; i < denali->max_banks; i++) {
+ index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90);
+ index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0);
+ index_addr_read_data(denali,
+ (uint32_t)(MODE_11 | (i << 24) | 2),
+ &id[i]);
+
+ if (i == 0) {
+ if (!(id[i] & 0x0ff))
+ break;
+ } else {
+ if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
+ denali->total_used_banks++;
+ else
+ break;
+ }
+ }
+}
+
+/*
+ * Use the configuration feature register to determine the maximum number of
+ * banks that the hardware supports.
+ */
+static void detect_max_banks(struct denali_nand_info *denali)
+{
+ uint32_t features = readl(denali->flash_reg + FEATURES);
+ denali->max_banks = 2 << (features & FEATURES__N_BANKS);
+}
+
+static void detect_partition_feature(struct denali_nand_info *denali)
+{
+ /*
+ * For MRST platform, denali->fwblks represent the
+ * number of blocks firmware is taken,
+ * FW is in protect partition and MTD driver has no
+ * permission to access it. So let driver know how many
+ * blocks it can't touch.
+ */
+ if (readl(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
+ if ((readl(denali->flash_reg + PERM_SRC_ID(1)) &
+ PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
+ denali->fwblks =
+ ((readl(denali->flash_reg + MIN_MAX_BANK(1)) &
+ MIN_MAX_BANK__MIN_VALUE) *
+ denali->blksperchip)
+ +
+ (readl(denali->flash_reg + MIN_BLK_ADDR(1)) &
+ MIN_BLK_ADDR__VALUE);
+ } else {
+ denali->fwblks = SPECTRA_START_BLOCK;
+ }
+ } else {
+ denali->fwblks = SPECTRA_START_BLOCK;
+ }
+}
+
+static uint32_t denali_nand_timing_set(struct denali_nand_info *denali)
+{
+ uint32_t id_bytes[5], addr;
+ uint8_t i, maf_id, device_id;
+
+ /* Use read id method to get device ID and other
+ * params. For some NAND chips, controller can't
+ * report the correct device ID by reading from
+ * DEVICE_ID register
+ * */
+ addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
+ index_addr(denali, (uint32_t)addr | 0, 0x90);
+ index_addr(denali, (uint32_t)addr | 1, 0);
+ for (i = 0; i < 5; i++)
+ index_addr_read_data(denali, addr | 2, &id_bytes[i]);
+ maf_id = id_bytes[0];
+ device_id = id_bytes[1];
+
+ if (readl(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
+ ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
+ if (get_onfi_nand_para(denali))
+ return -EIO;
+ } else if (maf_id == 0xEC) { /* Samsung NAND */
+ get_samsung_nand_para(denali, device_id);
+ } else if (maf_id == 0x98) { /* Toshiba NAND */
+ get_toshiba_nand_para(denali);
+ } else if (maf_id == 0xAD) { /* Hynix NAND */
+ get_hynix_nand_para(denali, device_id);
+ }
+
+ find_valid_banks(denali);
+
+ detect_partition_feature(denali);
+
+ /* If the user specified to override the default timings
+ * with a specific ONFI mode, we apply those changes here.
+ */
+ if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
+ nand_onfi_timing_set(denali, onfi_timing_mode);
+
+ return 0;
+}
+
+/* validation function to verify that the controlling software is making
+ * a valid request
+ */
+static inline bool is_flash_bank_valid(int flash_bank)
+{
+ return flash_bank >= 0 && flash_bank < 4;
+}
+
+static void denali_irq_init(struct denali_nand_info *denali)
+{
+ uint32_t int_mask = 0;
+ int i;
+
+ /* Disable global interrupts */
+ writel(0, denali->flash_reg + GLOBAL_INT_ENABLE);
+
+ int_mask = DENALI_IRQ_ALL;
+
+ /* Clear all status bits */
+ for (i = 0; i < denali->max_banks; ++i)
+ writel(0xFFFF, denali->flash_reg + INTR_STATUS(i));
+
+ denali_irq_enable(denali, int_mask);
+}
+
+/* This helper function setups the registers for ECC and whether or not
+ * the spare area will be transferred. */
+static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
+ bool transfer_spare)
+{
+ int ecc_en_flag = 0, transfer_spare_flag = 0;
+
+ /* set ECC, transfer spare bits if needed */
+ ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
+ transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
+
+ /* Enable spare area/ECC per user's request. */
+ writel(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
+ /* applicable for MAP01 only */
+ writel(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
+}
+
+/* sends a pipeline command operation to the controller. See the Denali NAND
+ * controller's user guide for more information (section 4.2.3.6).
+ */
+static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
+ bool ecc_en, bool transfer_spare,
+ int access_type, int op)
+{
+ uint32_t addr, cmd, irq_status;
+ static uint32_t page_count = 1;
+
+ setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
+
+ /* clear interrupts */
+ clear_interrupts(denali);
+
+ addr = BANK(denali->flash_bank) | denali->page;
+
+ /* setup the acccess type */
+ cmd = MODE_10 | addr;
+ index_addr(denali, cmd, access_type);
+
+ /* setup the pipeline command */
+ index_addr(denali, cmd, 0x2000 | op | page_count);
+
+ cmd = MODE_01 | addr;
+ writel(cmd, denali->flash_mem + INDEX_CTRL_REG);
+
+ if (op == DENALI_READ) {
+ /* wait for command to be accepted */
+ irq_status = wait_for_irq(denali, INTR_STATUS__LOAD_COMP);
+
+ if (irq_status == 0)
+ return -EIO;
+ }
+
+ return 0;
+}
+
+/* helper function that simply writes a buffer to the flash */
+static int write_data_to_flash_mem(struct denali_nand_info *denali,
+ const uint8_t *buf, int len)
+{
+ uint32_t i = 0, *buf32;
+
+ /* verify that the len is a multiple of 4. see comment in
+ * read_data_from_flash_mem() */
+ BUG_ON((len % 4) != 0);
+
+ /* write the data to the flash memory */
+ buf32 = (uint32_t *)buf;
+ for (i = 0; i < len / 4; i++)
+ writel(*buf32++, denali->flash_mem + INDEX_DATA_REG);
+ return i * 4; /* intent is to return the number of bytes read */
+}
+
+/* helper function that simply reads a buffer from the flash */
+static int read_data_from_flash_mem(struct denali_nand_info *denali,
+ uint8_t *buf, int len)
+{
+ uint32_t i, *buf32;
+
+ /*
+ * we assume that len will be a multiple of 4, if not
+ * it would be nice to know about it ASAP rather than
+ * have random failures...
+ * This assumption is based on the fact that this
+ * function is designed to be used to read flash pages,
+ * which are typically multiples of 4...
+ */
+
+ BUG_ON((len % 4) != 0);
+
+ /* transfer the data from the flash */
+ buf32 = (uint32_t *)buf;
+ for (i = 0; i < len / 4; i++)
+ *buf32++ = readl(denali->flash_mem + INDEX_DATA_REG);
+
+ return i * 4; /* intent is to return the number of bytes read */
+}
+
+static void denali_mode_main_access(struct denali_nand_info *denali)
+{
+ uint32_t addr, cmd;
+
+ addr = BANK(denali->flash_bank) | denali->page;
+ cmd = MODE_10 | addr;
+ index_addr(denali, cmd, MAIN_ACCESS);
+}
+
+static void denali_mode_main_spare_access(struct denali_nand_info *denali)
+{
+ uint32_t addr, cmd;
+
+ addr = BANK(denali->flash_bank) | denali->page;
+ cmd = MODE_10 | addr;
+ index_addr(denali, cmd, MAIN_SPARE_ACCESS);
+}
+
+/* writes OOB data to the device */
+static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ uint32_t irq_status;
+ uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
+ INTR_STATUS__PROGRAM_FAIL;
+ int status = 0;
+
+ denali->page = page;
+
+ if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
+ DENALI_WRITE) == 0) {
+ write_data_to_flash_mem(denali, buf, mtd->oobsize);
+
+ /* wait for operation to complete */
+ irq_status = wait_for_irq(denali, irq_mask);
+
+ if (irq_status == 0) {
+ dev_err(denali->dev, "OOB write failed\n");
+ status = -EIO;
+ }
+ } else {
+ printf("unable to send pipeline command\n");
+ status = -EIO;
+ }
+ return status;
+}
+
+/* reads OOB data from the device */
+static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ uint32_t irq_mask = INTR_STATUS__LOAD_COMP,
+ irq_status = 0, addr = 0x0, cmd = 0x0;
+
+ denali->page = page;
+
+ if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
+ DENALI_READ) == 0) {
+ read_data_from_flash_mem(denali, buf, mtd->oobsize);
+
+ /* wait for command to be accepted
+ * can always use status0 bit as the mask is identical for each
+ * bank. */
+ irq_status = wait_for_irq(denali, irq_mask);
+
+ if (irq_status == 0)
+ printf("page on OOB timeout %d\n", denali->page);
+
+ /* We set the device back to MAIN_ACCESS here as I observed
+ * instability with the controller if you do a block erase
+ * and the last transaction was a SPARE_ACCESS. Block erase
+ * is reliable (according to the MTD test infrastructure)
+ * if you are in MAIN_ACCESS.
+ */
+ addr = BANK(denali->flash_bank) | denali->page;
+ cmd = MODE_10 | addr;
+ index_addr(denali, cmd, MAIN_ACCESS);
+ }
+}
+
+/* this function examines buffers to see if they contain data that
+ * indicate that the buffer is part of an erased region of flash.
+ */
+static bool is_erased(uint8_t *buf, int len)
+{
+ int i = 0;
+ for (i = 0; i < len; i++)
+ if (buf[i] != 0xFF)
+ return false;
+ return true;
+}
+
+/* programs the controller to either enable/disable DMA transfers */
+static void denali_enable_dma(struct denali_nand_info *denali, bool en)
+{
+ uint32_t reg_val = 0x0;
+
+ if (en)
+ reg_val = DMA_ENABLE__FLAG;
+
+ writel(reg_val, denali->flash_reg + DMA_ENABLE);
+ readl(denali->flash_reg + DMA_ENABLE);
+}
+
+/* setups the HW to perform the data DMA */
+static void denali_setup_dma(struct denali_nand_info *denali, int op)
+{
+ uint32_t mode;
+ const int page_count = 1;
+ uint32_t addr = (uint32_t)denali->buf.dma_buf;
+
+ flush_dcache_range(addr, addr + sizeof(denali->buf.dma_buf));
+
+/* For Denali controller that is 64 bit bus IP core */
+#ifdef CONFIG_SYS_NAND_DENALI_64BIT
+ mode = MODE_10 | BANK(denali->flash_bank) | denali->page;
+
+ /* DMA is a three step process */
+
+ /* 1. setup transfer type, interrupt when complete,
+ burst len = 64 bytes, the number of pages */
+ index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count);
+
+ /* 2. set memory low address bits 31:0 */
+ index_addr(denali, mode, addr);
+
+ /* 3. set memory high address bits 64:32 */
+ index_addr(denali, mode, 0);
+#else
+ mode = MODE_10 | BANK(denali->flash_bank);
+
+ /* DMA is a four step process */
+
+ /* 1. setup transfer type and # of pages */
+ index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
+
+ /* 2. set memory high address bits 23:8 */
+ index_addr(denali, mode | ((uint32_t)(addr >> 16) << 8), 0x2200);
+
+ /* 3. set memory low address bits 23:8 */
+ index_addr(denali, mode | ((uint32_t)addr << 8), 0x2300);
+
+ /* 4. interrupt when complete, burst len = 64 bytes*/
+ index_addr(denali, mode | 0x14000, 0x2400);
+#endif
+}
+
+/* Common DMA function */
+static uint32_t denali_dma_configuration(struct denali_nand_info *denali,
+ uint32_t ops, bool raw_xfer,
+ uint32_t irq_mask, int oob_required)
+{
+ uint32_t irq_status = 0;
+ /* setup_ecc_for_xfer(bool ecc_en, bool transfer_spare) */
+ setup_ecc_for_xfer(denali, !raw_xfer, oob_required);
+
+ /* clear any previous interrupt flags */
+ clear_interrupts(denali);
+
+ /* enable the DMA */
+ denali_enable_dma(denali, true);
+
+ /* setup the DMA */
+ denali_setup_dma(denali, ops);
+
+ /* wait for operation to complete */
+ irq_status = wait_for_irq(denali, irq_mask);
+
+ /* if ECC fault happen, seems we need delay before turning off DMA.
+ * If not, the controller will go into non responsive condition */
+ if (irq_status & INTR_STATUS__ECC_UNCOR_ERR)
+ udelay(100);
+
+ /* disable the DMA */
+ denali_enable_dma(denali, false);
+
+ return irq_status;
+}
+
+static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, bool raw_xfer, int oob_required)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+
+ uint32_t irq_status = 0;
+ uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
+
+ denali->status = 0;
+
+ /* copy buffer into DMA buffer */
+ memcpy(denali->buf.dma_buf, buf, mtd->writesize);
+
+ /* need extra memcpy for raw transfer */
+ if (raw_xfer)
+ memcpy(denali->buf.dma_buf + mtd->writesize,
+ chip->oob_poi, mtd->oobsize);
+
+ /* setting up DMA */
+ irq_status = denali_dma_configuration(denali, DENALI_WRITE, raw_xfer,
+ irq_mask, oob_required);
+
+ /* if timeout happen, error out */
+ if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {
+ debug("DMA timeout for denali write_page\n");
+ denali->status = NAND_STATUS_FAIL;
+ return -EIO;
+ }
+
+ if (irq_status & INTR_STATUS__LOCKED_BLK) {
+ debug("Failed as write to locked block\n");
+ denali->status = NAND_STATUS_FAIL;
+ return -EIO;
+ }
+ return 0;
+}
+
+/* NAND core entry points */
+
+/*
+ * this is the callback that the NAND core calls to write a page. Since
+ * writing a page with ECC or without is similar, all the work is done
+ * by write_page above.
+ */
+static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int oob_required)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+
+ /*
+ * for regular page writes, we let HW handle all the ECC
+ * data written to the device.
+ */
+ if (oob_required)
+ /* switch to main + spare access */
+ denali_mode_main_spare_access(denali);
+ else
+ /* switch to main access only */
+ denali_mode_main_access(denali);
+
+ return write_page(mtd, chip, buf, false, oob_required);
+}
+
+/*
+ * This is the callback that the NAND core calls to write a page without ECC.
+ * raw access is similar to ECC page writes, so all the work is done in the
+ * write_page() function above.
+ */
+static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int oob_required)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+
+ /*
+ * for raw page writes, we want to disable ECC and simply write
+ * whatever data is in the buffer.
+ */
+
+ if (oob_required)
+ /* switch to main + spare access */
+ denali_mode_main_spare_access(denali);
+ else
+ /* switch to main access only */
+ denali_mode_main_access(denali);
+
+ return write_page(mtd, chip, buf, true, oob_required);
+}
+
+static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ return write_oob_data(mtd, chip->oob_poi, page);
+}
+
+/* raw include ECC value and all the spare area */
+static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+
+ uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;
+
+ if (denali->page != page) {
+ debug("Missing NAND_CMD_READ0 command\n");
+ return -EIO;
+ }
+
+ if (oob_required)
+ /* switch to main + spare access */
+ denali_mode_main_spare_access(denali);
+ else
+ /* switch to main access only */
+ denali_mode_main_access(denali);
+
+ /* setting up the DMA where ecc_enable is false */
+ irq_status = denali_dma_configuration(denali, DENALI_READ, true,
+ irq_mask, oob_required);
+
+ /* if timeout happen, error out */
+ if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {
+ debug("DMA timeout for denali_read_page_raw\n");
+ return -EIO;
+ }
+
+ /* splitting the content to destination buffer holder */
+ memcpy(chip->oob_poi, (denali->buf.dma_buf + mtd->writesize),
+ mtd->oobsize);
+ memcpy(buf, denali->buf.dma_buf, mtd->writesize);
+
+ return 0;
+}
+
+static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;
+
+ if (denali->page != page) {
+ debug("Missing NAND_CMD_READ0 command\n");
+ return -EIO;
+ }
+
+ if (oob_required)
+ /* switch to main + spare access */
+ denali_mode_main_spare_access(denali);
+ else
+ /* switch to main access only */
+ denali_mode_main_access(denali);
+
+ /* setting up the DMA where ecc_enable is true */
+ irq_status = denali_dma_configuration(denali, DENALI_READ, false,
+ irq_mask, oob_required);
+
+ memcpy(buf, denali->buf.dma_buf, mtd->writesize);
+
+ /* check whether any ECC error */
+ if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) {
+ /* is the ECC cause by erase page, check using read_page_raw */
+ debug(" Uncorrected ECC detected\n");
+ denali_read_page_raw(mtd, chip, buf, oob_required,
+ denali->page);
+
+ if (is_erased(buf, mtd->writesize) == true &&
+ is_erased(chip->oob_poi, mtd->oobsize) == true) {
+ debug(" ECC error cause by erased block\n");
+ /* false alarm, return the 0xFF */
+ } else {
+ return -EIO;
+ }
+ }
+ memcpy(buf, denali->buf.dma_buf, mtd->writesize);
+ return 0;
+}
+
+static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ read_oob_data(mtd, chip->oob_poi, page);
+
+ return 0;
+}
+
+static uint8_t denali_read_byte(struct mtd_info *mtd)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ uint32_t addr, result;
+
+ addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
+ index_addr_read_data(denali, addr | 2, &result);
+ return (uint8_t)result & 0xFF;
+}
+
+static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ uint32_t i, addr, result;
+
+ /* delay for tR (data transfer from Flash array to data register) */
+ udelay(25);
+
+ /* ensure device completed else additional delay and polling */
+ wait_for_irq(denali, INTR_STATUS__INT_ACT);
+
+ addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
+ for (i = 0; i < len; i++) {
+ index_addr_read_data(denali, (uint32_t)addr | 2, &result);
+ write_byte_to_buf(denali, result);
+ }
+ memcpy(buf, denali->buf.buf, len);
+}
+
+static void denali_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+
+ denali->flash_bank = chip;
+}
+
+static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ int status = denali->status;
+ denali->status = 0;
+
+ return status;
+}
+
+static void denali_erase(struct mtd_info *mtd, int page)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ uint32_t cmd, irq_status;
+
+ /* clear interrupts */
+ clear_interrupts(denali);
+
+ /* setup page read request for access type */
+ cmd = MODE_10 | BANK(denali->flash_bank) | page;
+ index_addr(denali, cmd, 0x1);
+
+ /* wait for erase to complete or failure to occur */
+ irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
+ INTR_STATUS__ERASE_FAIL);
+
+ if (irq_status & INTR_STATUS__ERASE_FAIL ||
+ irq_status & INTR_STATUS__LOCKED_BLK)
+ denali->status = NAND_STATUS_FAIL;
+ else
+ denali->status = 0;
+}
+
+static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
+ int page)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ uint32_t addr;
+
+ switch (cmd) {
+ case NAND_CMD_PAGEPROG:
+ break;
+ case NAND_CMD_STATUS:
+ addr = MODE_11 | BANK(denali->flash_bank);
+ index_addr(denali, addr | 0, cmd);
+ break;
+ case NAND_CMD_PARAM:
+ clear_interrupts(denali);
+ case NAND_CMD_READID:
+ reset_buf(denali);
+ /* sometimes ManufactureId read from register is not right
+ * e.g. some of Micron MT29F32G08QAA MLC NAND chips
+ * So here we send READID cmd to NAND insteand
+ * */
+ addr = MODE_11 | BANK(denali->flash_bank);
+ index_addr(denali, addr | 0, cmd);
+ index_addr(denali, addr | 1, col & 0xFF);
+ break;
+ case NAND_CMD_READ0:
+ case NAND_CMD_SEQIN:
+ denali->page = page;
+ break;
+ case NAND_CMD_RESET:
+ reset_bank(denali);
+ break;
+ case NAND_CMD_READOOB:
+ /* TODO: Read OOB data */
+ break;
+ case NAND_CMD_ERASE1:
+ /*
+ * supporting block erase only, not multiblock erase as
+ * it will cross plane and software need complex calculation
+ * to identify the block count for the cross plane
+ */
+ denali_erase(mtd, page);
+ break;
+ case NAND_CMD_ERASE2:
+ /* nothing to do here as it was done during NAND_CMD_ERASE1 */
+ break;
+ case NAND_CMD_UNLOCK1:
+ addr = MODE_10 | BANK(denali->flash_bank) | page;
+ index_addr(denali, addr | 0, DENALI_UNLOCK_START);
+ break;
+ case NAND_CMD_UNLOCK2:
+ addr = MODE_10 | BANK(denali->flash_bank) | page;
+ index_addr(denali, addr | 0, DENALI_UNLOCK_END);
+ break;
+ case NAND_CMD_LOCK:
+ addr = MODE_10 | BANK(denali->flash_bank);
+ index_addr(denali, addr | 0, DENALI_LOCK);
+ break;
+ default:
+ printf(": unsupported command received 0x%x\n", cmd);
+ break;
+ }
+}
+/* end NAND core entry points */
+
+/* Initialization code to bring the device up to a known good state */
+static void denali_hw_init(struct denali_nand_info *denali)
+{
+ /*
+ * tell driver how many bit controller will skip before writing
+ * ECC code in OOB. This is normally used for bad block marker
+ */
+ writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES,
+ denali->flash_reg + SPARE_AREA_SKIP_BYTES);
+ detect_max_banks(denali);
+ denali_nand_reset(denali);
+ writel(0x0F, denali->flash_reg + RB_PIN_ENABLED);
+ writel(CHIP_EN_DONT_CARE__FLAG,
+ denali->flash_reg + CHIP_ENABLE_DONT_CARE);
+ writel(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
+
+ /* Should set value for these registers when init */
+ writel(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
+ writel(1, denali->flash_reg + ECC_ENABLE);
+ denali_nand_timing_set(denali);
+ denali_irq_init(denali);
+}
+
+static struct nand_ecclayout nand_oob;
+
+static int denali_nand_init(struct nand_chip *nand)
+{
+ struct denali_nand_info *denali;
+
+ denali = malloc(sizeof(*denali));
+ if (!denali)
+ return -ENOMEM;
+
+ nand->priv = denali;
+
+ denali->flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
+ denali->flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
+
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+ /* check whether flash got BBT table (located at end of flash). As we
+ * use NAND_BBT_NO_OOB, the BBT page will start with
+ * bbt_pattern. We will have mirror pattern too */
+ nand->bbt_options |= NAND_BBT_USE_FLASH;
+ /*
+ * We are using main + spare with ECC support. As BBT need ECC support,
+ * we need to ensure BBT code don't write to OOB for the BBT pattern.
+ * All BBT info will be stored into data area with ECC support.
+ */
+ nand->bbt_options |= NAND_BBT_NO_OOB;
+#endif
+
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.size = CONFIG_NAND_DENALI_ECC_SIZE;
+ nand->ecc.read_oob = denali_read_oob;
+ nand->ecc.write_oob = denali_write_oob;
+ nand->ecc.read_page = denali_read_page;
+ nand->ecc.read_page_raw = denali_read_page_raw;
+ nand->ecc.write_page = denali_write_page;
+ nand->ecc.write_page_raw = denali_write_page_raw;
+ /*
+ * Tell driver the ecc strength. This register may be already set
+ * correctly. So we read this value out.
+ */
+ nand->ecc.strength = readl(denali->flash_reg + ECC_CORRECTION);
+ switch (nand->ecc.size) {
+ case 512:
+ nand->ecc.bytes = (nand->ecc.strength * 13 + 15) / 16 * 2;
+ break;
+ case 1024:
+ nand->ecc.bytes = (nand->ecc.strength * 14 + 15) / 16 * 2;
+ break;
+ default:
+ pr_err("Unsupported ECC size\n");
+ return -EINVAL;
+ }
+ nand_oob.eccbytes = nand->ecc.bytes;
+ nand->ecc.layout = &nand_oob;
+
+ /* Set address of hardware control function */
+ nand->cmdfunc = denali_cmdfunc;
+ nand->read_byte = denali_read_byte;
+ nand->read_buf = denali_read_buf;
+ nand->select_chip = denali_select_chip;
+ nand->waitfunc = denali_waitfunc;
+ denali_hw_init(denali);
+ return 0;
+}
+
+int board_nand_init(struct nand_chip *chip)
+{
+ return denali_nand_init(chip);
+}
--- /dev/null
+/*
+ * Copyright (C) 2013-2014 Altera Corporation <www.altera.com>
+ * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/mtd/nand.h>
+
+#define DEVICE_RESET 0x0
+#define DEVICE_RESET__BANK0 0x0001
+#define DEVICE_RESET__BANK1 0x0002
+#define DEVICE_RESET__BANK2 0x0004
+#define DEVICE_RESET__BANK3 0x0008
+
+#define TRANSFER_SPARE_REG 0x10
+#define TRANSFER_SPARE_REG__FLAG 0x0001
+
+#define LOAD_WAIT_CNT 0x20
+#define LOAD_WAIT_CNT__VALUE 0xffff
+
+#define PROGRAM_WAIT_CNT 0x30
+#define PROGRAM_WAIT_CNT__VALUE 0xffff
+
+#define ERASE_WAIT_CNT 0x40
+#define ERASE_WAIT_CNT__VALUE 0xffff
+
+#define INT_MON_CYCCNT 0x50
+#define INT_MON_CYCCNT__VALUE 0xffff
+
+#define RB_PIN_ENABLED 0x60
+#define RB_PIN_ENABLED__BANK0 0x0001
+#define RB_PIN_ENABLED__BANK1 0x0002
+#define RB_PIN_ENABLED__BANK2 0x0004
+#define RB_PIN_ENABLED__BANK3 0x0008
+
+#define MULTIPLANE_OPERATION 0x70
+#define MULTIPLANE_OPERATION__FLAG 0x0001
+
+#define MULTIPLANE_READ_ENABLE 0x80
+#define MULTIPLANE_READ_ENABLE__FLAG 0x0001
+
+#define COPYBACK_DISABLE 0x90
+#define COPYBACK_DISABLE__FLAG 0x0001
+
+#define CACHE_WRITE_ENABLE 0xa0
+#define CACHE_WRITE_ENABLE__FLAG 0x0001
+
+#define CACHE_READ_ENABLE 0xb0
+#define CACHE_READ_ENABLE__FLAG 0x0001
+
+#define PREFETCH_MODE 0xc0
+#define PREFETCH_MODE__PREFETCH_EN 0x0001
+#define PREFETCH_MODE__PREFETCH_BURST_LENGTH 0xfff0
+
+#define CHIP_ENABLE_DONT_CARE 0xd0
+#define CHIP_EN_DONT_CARE__FLAG 0x01
+
+#define ECC_ENABLE 0xe0
+#define ECC_ENABLE__FLAG 0x0001
+
+#define GLOBAL_INT_ENABLE 0xf0
+#define GLOBAL_INT_EN_FLAG 0x01
+
+#define WE_2_RE 0x100
+#define WE_2_RE__VALUE 0x003f
+
+#define ADDR_2_DATA 0x110
+#define ADDR_2_DATA__VALUE 0x003f
+
+#define RE_2_WE 0x120
+#define RE_2_WE__VALUE 0x003f
+
+#define ACC_CLKS 0x130
+#define ACC_CLKS__VALUE 0x000f
+
+#define NUMBER_OF_PLANES 0x140
+#define NUMBER_OF_PLANES__VALUE 0x0007
+
+#define PAGES_PER_BLOCK 0x150
+#define PAGES_PER_BLOCK__VALUE 0xffff
+
+#define DEVICE_WIDTH 0x160
+#define DEVICE_WIDTH__VALUE 0x0003
+
+#define DEVICE_MAIN_AREA_SIZE 0x170
+#define DEVICE_MAIN_AREA_SIZE__VALUE 0xffff
+
+#define DEVICE_SPARE_AREA_SIZE 0x180
+#define DEVICE_SPARE_AREA_SIZE__VALUE 0xffff
+
+#define TWO_ROW_ADDR_CYCLES 0x190
+#define TWO_ROW_ADDR_CYCLES__FLAG 0x0001
+
+#define MULTIPLANE_ADDR_RESTRICT 0x1a0
+#define MULTIPLANE_ADDR_RESTRICT__FLAG 0x0001
+
+#define ECC_CORRECTION 0x1b0
+#define ECC_CORRECTION__VALUE 0x001f
+
+#define READ_MODE 0x1c0
+#define READ_MODE__VALUE 0x000f
+
+#define WRITE_MODE 0x1d0
+#define WRITE_MODE__VALUE 0x000f
+
+#define COPYBACK_MODE 0x1e0
+#define COPYBACK_MODE__VALUE 0x000f
+
+#define RDWR_EN_LO_CNT 0x1f0
+#define RDWR_EN_LO_CNT__VALUE 0x001f
+
+#define RDWR_EN_HI_CNT 0x200
+#define RDWR_EN_HI_CNT__VALUE 0x001f
+
+#define MAX_RD_DELAY 0x210
+#define MAX_RD_DELAY__VALUE 0x000f
+
+#define CS_SETUP_CNT 0x220
+#define CS_SETUP_CNT__VALUE 0x001f
+
+#define SPARE_AREA_SKIP_BYTES 0x230
+#define SPARE_AREA_SKIP_BYTES__VALUE 0x003f
+
+#define SPARE_AREA_MARKER 0x240
+#define SPARE_AREA_MARKER__VALUE 0xffff
+
+#define DEVICES_CONNECTED 0x250
+#define DEVICES_CONNECTED__VALUE 0x0007
+
+#define DIE_MASK 0x260
+#define DIE_MASK__VALUE 0x00ff
+
+#define FIRST_BLOCK_OF_NEXT_PLANE 0x270
+#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE 0xffff
+
+#define WRITE_PROTECT 0x280
+#define WRITE_PROTECT__FLAG 0x0001
+
+#define RE_2_RE 0x290
+#define RE_2_RE__VALUE 0x003f
+
+#define MANUFACTURER_ID 0x300
+#define MANUFACTURER_ID__VALUE 0x00ff
+
+#define DEVICE_ID 0x310
+#define DEVICE_ID__VALUE 0x00ff
+
+#define DEVICE_PARAM_0 0x320
+#define DEVICE_PARAM_0__VALUE 0x00ff
+
+#define DEVICE_PARAM_1 0x330
+#define DEVICE_PARAM_1__VALUE 0x00ff
+
+#define DEVICE_PARAM_2 0x340
+#define DEVICE_PARAM_2__VALUE 0x00ff
+
+#define LOGICAL_PAGE_DATA_SIZE 0x350
+#define LOGICAL_PAGE_DATA_SIZE__VALUE 0xffff
+
+#define LOGICAL_PAGE_SPARE_SIZE 0x360
+#define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff
+
+#define REVISION 0x370
+#define REVISION__VALUE 0xffff
+
+#define ONFI_DEVICE_FEATURES 0x380
+#define ONFI_DEVICE_FEATURES__VALUE 0x003f
+
+#define ONFI_OPTIONAL_COMMANDS 0x390
+#define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f
+
+#define ONFI_TIMING_MODE 0x3a0
+#define ONFI_TIMING_MODE__VALUE 0x003f
+
+#define ONFI_PGM_CACHE_TIMING_MODE 0x3b0
+#define ONFI_PGM_CACHE_TIMING_MODE__VALUE 0x003f
+
+#define ONFI_DEVICE_NO_OF_LUNS 0x3c0
+#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS 0x00ff
+#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE 0x0100
+
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE 0xffff
+
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE 0xffff
+
+#define FEATURES 0x3f0
+#define FEATURES__N_BANKS 0x0003
+#define FEATURES__ECC_MAX_ERR 0x003c
+#define FEATURES__DMA 0x0040
+#define FEATURES__CMD_DMA 0x0080
+#define FEATURES__PARTITION 0x0100
+#define FEATURES__XDMA_SIDEBAND 0x0200
+#define FEATURES__GPREG 0x0400
+#define FEATURES__INDEX_ADDR 0x0800
+
+#define TRANSFER_MODE 0x400
+#define TRANSFER_MODE__VALUE 0x0003
+
+#define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50))
+#define INTR_EN(__bank) (0x420 + ((__bank) * 0x50))
+
+/*
+ * Some versions of the IP have the ECC fixup handled in hardware. In this
+ * configuration we only get interrupted when the error is uncorrectable.
+ * Unfortunately this bit replaces INTR_STATUS__ECC_TRANSACTION_DONE from the
+ * old IP.
+ */
+#define INTR_STATUS__ECC_UNCOR_ERR 0x0001
+#define INTR_STATUS__ECC_TRANSACTION_DONE 0x0001
+#define INTR_STATUS__ECC_ERR 0x0002
+#define INTR_STATUS__DMA_CMD_COMP 0x0004
+#define INTR_STATUS__TIME_OUT 0x0008
+#define INTR_STATUS__PROGRAM_FAIL 0x0010
+#define INTR_STATUS__ERASE_FAIL 0x0020
+#define INTR_STATUS__LOAD_COMP 0x0040
+#define INTR_STATUS__PROGRAM_COMP 0x0080
+#define INTR_STATUS__ERASE_COMP 0x0100
+#define INTR_STATUS__PIPE_CPYBCK_CMD_COMP 0x0200
+#define INTR_STATUS__LOCKED_BLK 0x0400
+#define INTR_STATUS__UNSUP_CMD 0x0800
+#define INTR_STATUS__INT_ACT 0x1000
+#define INTR_STATUS__RST_COMP 0x2000
+#define INTR_STATUS__PIPE_CMD_ERR 0x4000
+#define INTR_STATUS__PAGE_XFER_INC 0x8000
+
+#define INTR_EN__ECC_TRANSACTION_DONE 0x0001
+#define INTR_EN__ECC_ERR 0x0002
+#define INTR_EN__DMA_CMD_COMP 0x0004
+#define INTR_EN__TIME_OUT 0x0008
+#define INTR_EN__PROGRAM_FAIL 0x0010
+#define INTR_EN__ERASE_FAIL 0x0020
+#define INTR_EN__LOAD_COMP 0x0040
+#define INTR_EN__PROGRAM_COMP 0x0080
+#define INTR_EN__ERASE_COMP 0x0100
+#define INTR_EN__PIPE_CPYBCK_CMD_COMP 0x0200
+#define INTR_EN__LOCKED_BLK 0x0400
+#define INTR_EN__UNSUP_CMD 0x0800
+#define INTR_EN__INT_ACT 0x1000
+#define INTR_EN__RST_COMP 0x2000
+#define INTR_EN__PIPE_CMD_ERR 0x4000
+#define INTR_EN__PAGE_XFER_INC 0x8000
+
+#define PAGE_CNT(__bank) (0x430 + ((__bank) * 0x50))
+#define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50))
+#define ERR_BLOCK_ADDR(__bank) (0x450 + ((__bank) * 0x50))
+
+#define DATA_INTR 0x550
+#define DATA_INTR__WRITE_SPACE_AV 0x0001
+#define DATA_INTR__READ_DATA_AV 0x0002
+
+#define DATA_INTR_EN 0x560
+#define DATA_INTR_EN__WRITE_SPACE_AV 0x0001
+#define DATA_INTR_EN__READ_DATA_AV 0x0002
+
+#define GPREG_0 0x570
+#define GPREG_0__VALUE 0xffff
+
+#define GPREG_1 0x580
+#define GPREG_1__VALUE 0xffff
+
+#define GPREG_2 0x590
+#define GPREG_2__VALUE 0xffff
+
+#define GPREG_3 0x5a0
+#define GPREG_3__VALUE 0xffff
+
+#define ECC_THRESHOLD 0x600
+#define ECC_THRESHOLD__VALUE 0x03ff
+
+#define ECC_ERROR_BLOCK_ADDRESS 0x610
+#define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff
+
+#define ECC_ERROR_PAGE_ADDRESS 0x620
+#define ECC_ERROR_PAGE_ADDRESS__VALUE 0x0fff
+#define ECC_ERROR_PAGE_ADDRESS__BANK 0xf000
+
+#define ECC_ERROR_ADDRESS 0x630
+#define ECC_ERROR_ADDRESS__OFFSET 0x0fff
+#define ECC_ERROR_ADDRESS__SECTOR_NR 0xf000
+
+#define ERR_CORRECTION_INFO 0x640
+#define ERR_CORRECTION_INFO__BYTEMASK 0x00ff
+#define ERR_CORRECTION_INFO__DEVICE_NR 0x0f00
+#define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000
+#define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000
+
+#define DMA_ENABLE 0x700
+#define DMA_ENABLE__FLAG 0x0001
+
+#define IGNORE_ECC_DONE 0x710
+#define IGNORE_ECC_DONE__FLAG 0x0001
+
+#define DMA_INTR 0x720
+#define DMA_INTR__TARGET_ERROR 0x0001
+#define DMA_INTR__DESC_COMP_CHANNEL0 0x0002
+#define DMA_INTR__DESC_COMP_CHANNEL1 0x0004
+#define DMA_INTR__DESC_COMP_CHANNEL2 0x0008
+#define DMA_INTR__DESC_COMP_CHANNEL3 0x0010
+#define DMA_INTR__MEMCOPY_DESC_COMP 0x0020
+
+#define DMA_INTR_EN 0x730
+#define DMA_INTR_EN__TARGET_ERROR 0x0001
+#define DMA_INTR_EN__DESC_COMP_CHANNEL0 0x0002
+#define DMA_INTR_EN__DESC_COMP_CHANNEL1 0x0004
+#define DMA_INTR_EN__DESC_COMP_CHANNEL2 0x0008
+#define DMA_INTR_EN__DESC_COMP_CHANNEL3 0x0010
+#define DMA_INTR_EN__MEMCOPY_DESC_COMP 0x0020
+
+#define TARGET_ERR_ADDR_LO 0x740
+#define TARGET_ERR_ADDR_LO__VALUE 0xffff
+
+#define TARGET_ERR_ADDR_HI 0x750
+#define TARGET_ERR_ADDR_HI__VALUE 0xffff
+
+#define CHNL_ACTIVE 0x760
+#define CHNL_ACTIVE__CHANNEL0 0x0001
+#define CHNL_ACTIVE__CHANNEL1 0x0002
+#define CHNL_ACTIVE__CHANNEL2 0x0004
+#define CHNL_ACTIVE__CHANNEL3 0x0008
+
+#define ACTIVE_SRC_ID 0x800
+#define ACTIVE_SRC_ID__VALUE 0x00ff
+
+#define PTN_INTR 0x810
+#define PTN_INTR__CONFIG_ERROR 0x0001
+#define PTN_INTR__ACCESS_ERROR_BANK0 0x0002
+#define PTN_INTR__ACCESS_ERROR_BANK1 0x0004
+#define PTN_INTR__ACCESS_ERROR_BANK2 0x0008
+#define PTN_INTR__ACCESS_ERROR_BANK3 0x0010
+#define PTN_INTR__REG_ACCESS_ERROR 0x0020
+
+#define PTN_INTR_EN 0x820
+#define PTN_INTR_EN__CONFIG_ERROR 0x0001
+#define PTN_INTR_EN__ACCESS_ERROR_BANK0 0x0002
+#define PTN_INTR_EN__ACCESS_ERROR_BANK1 0x0004
+#define PTN_INTR_EN__ACCESS_ERROR_BANK2 0x0008
+#define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010
+#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020
+
+#define PERM_SRC_ID(__bank) (0x830 + ((__bank) * 0x40))
+#define PERM_SRC_ID__SRCID 0x00ff
+#define PERM_SRC_ID__DIRECT_ACCESS_ACTIVE 0x0800
+#define PERM_SRC_ID__WRITE_ACTIVE 0x2000
+#define PERM_SRC_ID__READ_ACTIVE 0x4000
+#define PERM_SRC_ID__PARTITION_VALID 0x8000
+
+#define MIN_BLK_ADDR(__bank) (0x840 + ((__bank) * 0x40))
+#define MIN_BLK_ADDR__VALUE 0xffff
+
+#define MAX_BLK_ADDR(__bank) (0x850 + ((__bank) * 0x40))
+#define MAX_BLK_ADDR__VALUE 0xffff
+
+#define MIN_MAX_BANK(__bank) (0x860 + ((__bank) * 0x40))
+#define MIN_MAX_BANK__MIN_VALUE 0x0003
+#define MIN_MAX_BANK__MAX_VALUE 0x000c
+
+/* lld.h */
+#define GOOD_BLOCK 0
+#define DEFECTIVE_BLOCK 1
+#define READ_ERROR 2
+
+#define CLK_X 5
+#define CLK_MULTI 4
+
+/* spectraswconfig.h */
+#define CMD_DMA 0
+
+#define SPECTRA_PARTITION_ID 0
+/**** Block Table and Reserved Block Parameters *****/
+#define SPECTRA_START_BLOCK 3
+#define NUM_FREE_BLOCKS_GATE 30
+
+/* KBV - Updated to LNW scratch register address */
+#define SCRATCH_REG_ADDR CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR
+#define SCRATCH_REG_SIZE 64
+
+#define GLOB_HWCTL_DEFAULT_BLKS 2048
+
+#define CUSTOM_CONF_PARAMS 0
+
+#ifndef _LLD_NAND_
+#define _LLD_NAND_
+
+#define INDEX_CTRL_REG 0x0
+#define INDEX_DATA_REG 0x10
+
+#define MODE_00 0x00000000
+#define MODE_01 0x04000000
+#define MODE_10 0x08000000
+#define MODE_11 0x0C000000
+
+
+#define DATA_TRANSFER_MODE 0
+#define PROTECTION_PER_BLOCK 1
+#define LOAD_WAIT_COUNT 2
+#define PROGRAM_WAIT_COUNT 3
+#define ERASE_WAIT_COUNT 4
+#define INT_MONITOR_CYCLE_COUNT 5
+#define READ_BUSY_PIN_ENABLED 6
+#define MULTIPLANE_OPERATION_SUPPORT 7
+#define PRE_FETCH_MODE 8
+#define CE_DONT_CARE_SUPPORT 9
+#define COPYBACK_SUPPORT 10
+#define CACHE_WRITE_SUPPORT 11
+#define CACHE_READ_SUPPORT 12
+#define NUM_PAGES_IN_BLOCK 13
+#define ECC_ENABLE_SELECT 14
+#define WRITE_ENABLE_2_READ_ENABLE 15
+#define ADDRESS_2_DATA 16
+#define READ_ENABLE_2_WRITE_ENABLE 17
+#define TWO_ROW_ADDRESS_CYCLES 18
+#define MULTIPLANE_ADDRESS_RESTRICT 19
+#define ACC_CLOCKS 20
+#define READ_WRITE_ENABLE_LOW_COUNT 21
+#define READ_WRITE_ENABLE_HIGH_COUNT 22
+
+#define ECC_SECTOR_SIZE 512
+
+#define DENALI_BUF_SIZE (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE)
+
+struct nand_buf {
+ int head;
+ int tail;
+ /* seprating dma_buf as buf can be used for status read purpose */
+ uint8_t dma_buf[DENALI_BUF_SIZE] __aligned(64);
+ uint8_t buf[DENALI_BUF_SIZE];
+};
+
+#define INTEL_CE4100 1
+#define INTEL_MRST 2
+#define DT 3
+
+struct denali_nand_info {
+ struct mtd_info mtd;
+ struct nand_chip *nand;
+
+ int flash_bank; /* currently selected chip */
+ int status;
+ int platform;
+ struct nand_buf buf;
+ struct device *dev;
+ int total_used_banks;
+ uint32_t block; /* stored for future use */
+ uint32_t page;
+ void __iomem *flash_reg; /* Mapped io reg base address */
+ void __iomem *flash_mem; /* Mapped io reg base address */
+
+ /* elements used by ISR */
+ /*struct completion complete;*/
+
+ uint32_t irq_status;
+ int irq_debug_array[32];
+ int idx;
+ int irq;
+
+ uint32_t devnum; /* represent how many nands connected */
+ uint32_t fwblks; /* represent how many blocks FW used */
+ uint32_t totalblks;
+ uint32_t blksperchip;
+ uint32_t bbtskipbytes;
+ uint32_t max_banks;
+};
+
+#endif /*_LLD_NAND_*/
{
int i;
u16 *p = (u16 *) buf;
- len >>= 1;
-
+
for (i = 0; i < len; i++)
p[i] = readw(addr);
}
{
int i;
u16 *p = (u16 *) buf;
- len >>= 1;
for (i = 0; i < len; i++)
writew(p[i], addr);
{"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0},
{"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0},
{"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0},
+ {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, 0, 0},
+ {"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_EXTN, 0},
{"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0},
{"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0},
{"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0},
+ {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, 0, SECT_4K},
{"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
{"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
{"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
* Load U-Boot image from SPI flash into RAM
*/
- flash = spi_flash_probe(CONFIG_SPL_SPI_BUS, CONFIG_SPL_SPI_CS,
- CONFIG_SF_DEFAULT_SPEED, SPI_MODE_3);
+ flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
+ CONFIG_SF_DEFAULT_CS,
+ CONFIG_SF_DEFAULT_SPEED,
+ CONFIG_SF_DEFAULT_MODE);
if (!flash) {
puts("SPI probe failed.\n");
hang();
hw->autoneg_failed = 0;
hw->autoneg = 1;
hw->get_link_status = true;
+#ifndef CONFIG_E1000_NO_NVM
hw->eeprom_semaphore_present = true;
+#endif
hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
PCI_REGION_MEM);
hw->mac_type = e1000_undefined;
else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII)
return PHY_INTERFACE_MODE_MII;
- else
- return PHY_INTERFACE_MODE_NONE;
}
switch (port) {
if (space) {
write_buffer (&usbtty_output);
- n = MIN (space, MIN (len, maxlen));
+ n = min(space, min(len, maxlen));
buf_push (&usbtty_output, str, n);
str += n;
space_avail =
current_urb->buffer_length -
current_urb->actual_length;
- popnum = MIN (space_avail, buf->size);
+ popnum = min(space_avail, buf->size);
if (popnum == 0)
break;
static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE;
-u32 cs_spi_mpp_back[2];
+static u32 cs_spi_mpp_back[2];
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
if (!slave)
return NULL;
- writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl);
+ writel(KWSPI_SMEMRDY, &spireg->ctrl);
/* calculate spi clock prescaller using max_hz */
data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
/* program spi clock prescaller using max_hz */
writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
- debug("data = 0x%08x \n", data);
+ debug("data = 0x%08x\n", data);
writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
writel(KWSPI_IRQMASK, &spireg->irq_mask);
/* set new spi mpp and save current mpp config */
kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
-
#endif
return board_spi_claim_bus(slave);
*/
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
- return (bus == 0 && (cs == 0 || cs == 1));
+ return bus == 0 && (cs == 0 || cs == 1);
}
#endif
void spi_cs_activate(struct spi_slave *slave)
{
- writel(readl(&spireg->ctrl) | KWSPI_IRQUNMASK, &spireg->ctrl);
+ setbits_le32(&spireg->ctrl, KWSPI_CSN_ACT);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
- writel(readl(&spireg->ctrl) & KWSPI_IRQMASK, &spireg->ctrl);
+ clrbits_le32(&spireg->ctrl, KWSPI_CSN_ACT);
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
* handle data in 8-bit chunks
* TBD: 2byte xfer mode to be enabled
*/
- writel(((readl(&spireg->cfg) & ~KWSPI_XFERLEN_MASK) |
- KWSPI_XFERLEN_1BYTE), &spireg->cfg);
+ clrsetbits_le32(&spireg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
while (bitlen > 4) {
debug("loopstart bitlen %d\n", bitlen);
/* Shift data so it's msb-justified */
if (dout)
- tmpdout = *(u32 *) dout & 0x0ff;
+ tmpdout = *(u32 *)dout & 0xff;
- writel(~KWSPI_SMEMRDIRQ, &spireg->irq_cause);
+ clrbits_le32(&spireg->irq_cause, KWSPI_SMEMRDIRQ);
writel(tmpdout, &spireg->dout); /* Write the data out */
debug("*** spi_xfer: ... %08x written, bitlen %d\n",
tmpdout, bitlen);
if (readl(&spireg->irq_cause) & KWSPI_SMEMRDIRQ) {
isread = 1;
tmpdin = readl(&spireg->din);
- debug
- ("spi_xfer: din %p..%08x read\n",
- din, tmpdin);
+ debug("spi_xfer: din %p..%08x read\n",
+ din, tmpdin);
if (din) {
- *((u8 *) din) = (u8) tmpdin;
+ *((u8 *)din) = (u8)tmpdin;
din += 1;
}
if (dout)
MXC_SPI_BASE_ADDRESSES
};
+__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return -1;
+}
+
#define OUT MXC_GPIO_DIRECTION_OUT
#define reg_read readl
{
}
-static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
+/*
+ * Some SPI devices require active chip-select over multiple
+ * transactions, we achieve this using a GPIO. Still, the SPI
+ * controller has to be configured to use one of its own chipselects.
+ * To use this feature you have to implement board_spi_cs_gpio() to assign
+ * a gpio value for each cs (-1 if cs doesn't need to use gpio).
+ * You must use some unused on this SPI controller cs between 0 and 3.
+ */
+static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
+ unsigned int bus, unsigned int cs)
{
int ret;
- /*
- * Some SPI devices require active chip-select over multiple
- * transactions, we achieve this using a GPIO. Still, the SPI
- * controller has to be configured to use one of its own chipselects.
- * To use this feature you have to call spi_setup_slave() with
- * cs = internal_cs | (gpio << 8), and you have to use some unused
- * on this SPI controller cs between 0 and 3.
- */
- if (cs > 3) {
- mxcs->gpio = cs >> 8;
- cs &= 3;
- ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
- if (ret) {
- printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
- return -EINVAL;
- }
- } else {
- mxcs->gpio = -1;
+ mxcs->gpio = board_spi_cs_gpio(bus, cs);
+ if (mxcs->gpio == -1)
+ return 0;
+
+ ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
+ if (ret) {
+ printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
+ return -EINVAL;
}
- return cs;
+ return 0;
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
- ret = decode_cs(mxcs, cs);
+ ret = setup_cs_gpio(mxcs, bus, cs);
if (ret < 0) {
free(mxcs);
return NULL;
}
- cs = ret;
-
mxcs->base = spi_bases[bus];
ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d",
urb->buffer, urb->buffer_length, urb->actual_length);
- last = MIN(urb->actual_length - endpoint->sent,
+ last = min(urb->actual_length - endpoint->sent,
endpoint->tx_packetSize);
if (last) {
align = ((ulong)cp % sizeof(int));
if (align)
- last = MIN(last, sizeof(int) - align);
+ last = min(last, sizeof(int) - align);
UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d",
endpoint->sent, endpoint->tx_packetSize, last);
/*copy_config(urb, &report_descriptor->bData[0], report_descriptor->wLength, max); */
if (max - urb->actual_length > 0) {
int length =
- MIN (report_descriptor->wLength,
+ min(report_descriptor->wLength,
max - urb->actual_length);
memcpy (urb->buffer + urb->actual_length,
&report_descriptor->bData[0], length);
*
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <config.h>
#include <common.h>
#include <errno.h>
#include <malloc.h>
#include <linux/compiler.h>
#include <version.h>
#include <g_dnl.h>
+#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+#include <fb_mmc.h>
+#endif
#define FASTBOOT_VERSION "0.4"
struct f_fastboot {
struct usb_function usb_function;
- /* IN/OUT EP's and correspoinding requests */
+ /* IN/OUT EP's and corresponding requests */
struct usb_ep *in_ep, *out_ep;
struct usb_request *in_req, *out_req;
};
}
DECLARE_GADGET_BIND_CALLBACK(usb_dnl_fastboot, fastboot_add);
-int fastboot_tx_write(const char *buffer, unsigned int buffer_size)
+static int fastboot_tx_write(const char *buffer, unsigned int buffer_size)
{
struct usb_request *in_req = fastboot_func->in_req;
int ret;
strsep(&cmd, ":");
if (!cmd) {
+ error("missing variable\n");
fastboot_tx_write_str("FAILmissing var");
return;
}
else
strcpy(response, "FAILValue not set");
} else {
+ error("unknown variable: %s\n", cmd);
strcpy(response, "FAILVariable not implemented");
}
fastboot_tx_write_str(response);
fastboot_tx_write_str("OKAY");
}
+#ifdef CONFIG_FASTBOOT_FLASH
+static void cb_flash(struct usb_ep *ep, struct usb_request *req)
+{
+ char *cmd = req->buf;
+ char response[RESPONSE_LEN];
+
+ strsep(&cmd, ":");
+ if (!cmd) {
+ error("missing partition name\n");
+ fastboot_tx_write_str("FAILmissing partition name");
+ return;
+ }
+
+ strcpy(response, "FAILno flash device defined");
+#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+ fb_mmc_flash_write(cmd, (void *)CONFIG_USB_FASTBOOT_BUF_ADDR,
+ download_bytes, response);
+#endif
+ fastboot_tx_write_str(response);
+}
+#endif
+
struct cmd_dispatch_info {
char *cmd;
void (*cb)(struct usb_ep *ep, struct usb_request *req);
.cmd = "boot",
.cb = cb_boot,
},
+#ifdef CONFIG_FASTBOOT_FLASH
+ {
+ .cmd = "flash",
+ .cb = cb_flash,
+ },
+#endif
};
static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
}
}
- if (!func_cb)
+ if (!func_cb) {
+ error("unknown command: %s\n", cmdbuf);
fastboot_tx_write_str("FAILunknown command");
- else
+ } else {
func_cb(ep, req);
+ }
if (req->status == 0) {
*cmdbuf = '\0';
pkt_len = urb->actual_length - epi->sent;
if (pkt_len > epi->tx_packetSize || pkt_len > EP_MAX_PKT) {
- pkt_len = MIN (epi->tx_packetSize, EP_MAX_PKT);
+ pkt_len = min(epi->tx_packetSize, EP_MAX_PKT);
}
for (x = 0; x < pkt_len; x++) {
/* TX ACK : USB 2.0 8.7.2, Toggle PID, Advance TX */
epi->sent += pkt_len;
- epi->last = MIN (urb->actual_length - epi->sent, epi->tx_packetSize);
+ epi->last = min(urb->actual_length - epi->sent, epi->tx_packetSize);
TOGGLE_TX_PID (ep_ref[ep].pid);
if (epi->sent >= epi->tx_urb->actual_length) {
if (!urb || !urb->actual_length)
return -1;
- n = MIN(urb->actual_length - endpoint->sent, endpoint->tx_packetSize);
+ n = min(urb->actual_length - endpoint->sent, endpoint->tx_packetSize);
if (n <= 0)
return -1;
--- /dev/null
+#
+# Device Tree Control
+#
+# TODO:
+# This feature is not currently supported for SPL,
+# but this restriction should be removed in the future.
+
+config SUPPORT_OF_CONTROL
+ bool
+
+menu "Device Tree Control"
+ depends on !SPL_BUILD
+ depends on SUPPORT_OF_CONTROL
+
+config OF_CONTROL
+ bool "Run-time configuration via Device Tree"
+ help
+ This feature provides for run-time configuration of U-Boot
+ via a flattened device tree.
+
+choice
+ prompt "Provider of DTB for DT control"
+ depends on OF_CONTROL
+
+config OF_SEPARATE
+ bool "Separate DTB for DT control"
+ depends on !SANDBOX
+ help
+ If this option is enabled, the device tree will be built and
+ placed as a separate u-boot.dtb file alongside the U-Boot image.
+
+config OF_EMBED
+ bool "Embedded DTB for DT control"
+ help
+ If this option is enabled, the device tree will be picked up and
+ built into the U-Boot image.
+
+config OF_HOSTFILE
+ bool "Host filed DTB for DT control"
+ depends on SANDBOX
+ help
+ If this option is enabled, DTB will be read from a file on startup.
+ This is only useful for Sandbox. Use the -d flag to U-Boot to
+ specify the file to read.
+
+endchoice
+
+config DEFAULT_DEVICE_TREE
+ string "Default Device Tree for DT control"
+ help
+ This option specifies the default Device Tree used for DT control.
+ It can be overrided from the command line:
+ $ make DEVICE_TREE=<device-tree-name>
+
+endmenu
--- /dev/null
+#
+# File system configuration
+#
+
+menu "File systems"
+
+source "fs/ext4/Kconfig"
+
+source "fs/reiserfs/Kconfig"
+
+source "fs/fat/Kconfig"
+
+source "fs/jffs2/Kconfig"
+
+source "fs/ubifs/Kconfig"
+
+source "fs/cramfs/Kconfig"
+
+endmenu
while (bseen < array_len) {
struct zap_leaf_array *la = &ZAP_LEAF_CHUNK(l, blksft, chunk).l_array;
- int toread = MIN(array_len - bseen, ZAP_LEAF_ARRAY_BYTES);
+ int toread = min(array_len - bseen, ZAP_LEAF_ARRAY_BYTES);
if (chunk >= ZAP_LEAF_NUMCHUNKS(blksft))
return 0;
while (bseen < array_len) {
struct zap_leaf_array *la = &ZAP_LEAF_CHUNK(l, blksft, chunk).l_array;
- int toread = MIN(array_len - bseen, ZAP_LEAF_ARRAY_BYTES);
+ int toread = min(array_len - bseen, ZAP_LEAF_ARRAY_BYTES);
if (chunk >= ZAP_LEAF_NUMCHUNKS(blksft))
/* Don't use errno because this error is to be ignored. */
data->file_start = blkid * blksz;
data->file_end = data->file_start + blksz;
- movesize = MIN(length, data->file_end - (int) file->offset - red);
+ movesize = min(length, data->file_end - (int)file->offset - red);
memmove(buf, data->file_buf + file->offset + red
- data->file_start, movesize);
typeof(Y) __y = (Y); \
(__x > __y) ? __x : __y; })
-#define MIN(x, y) min(x, y)
-#define MAX(x, y) max(x, y)
-
#define min3(X, Y, Z) \
({ typeof(X) __x = (X); \
typeof(Y) __y = (Y); \
__x > __y ? (__x > __z ? __x : __z) : \
(__y > __z ? __y : __z); })
-#define MIN3(x, y, z) min3(x, y, z)
-#define MAX3(x, y, z) max3(x, y, z)
-
/*
* Return the absolute value of a number.
*
#endif /* USE_HOSTCC */
-/* compiler options */
-#define uninitialized_var(x) x = x
-
#define likely(x) __builtin_expect(!!(x), 1)
#define unlikely(x) __builtin_expect(!!(x), 0)
+++ /dev/null
-/*
- * config_cmd_defaults.h - sane defaults for everyone
- *
- * Copyright (c) 2010-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CONFIG_CMD_DEFAULTS_H_
-#define _CONFIG_CMD_DEFAULTS_H_
-
-#define CONFIG_CMD_BOOTM 1
-#define CONFIG_CMD_CRC32 1
-#define CONFIG_CMD_EXPORTENV 1
-#define CONFIG_CMD_GO 1
-#define CONFIG_CMD_IMPORTENV 1
-
-#endif
#endif
#ifdef CONFIG_CMD_SCSI
-#define BOOTENV_SHARED_SCSI BOOTENV_SHARED_BLKDEV(scsi)
+#define BOOTENV_RUN_SCSI_INIT "run scsi_init; "
+#define BOOTENV_SET_SCSI_NEED_INIT "setenv scsi_need_init; "
+#define BOOTENV_SHARED_SCSI \
+ "scsi_init=" \
+ "if ${scsi_need_init}; then " \
+ "setenv scsi_need_init false; " \
+ "scsi scan; " \
+ "fi\0" \
+ \
+ "scsi_boot=" \
+ BOOTENV_RUN_SCSI_INIT \
+ BOOTENV_SHARED_BLKDEV_BODY(scsi)
#define BOOTENV_DEV_SCSI BOOTENV_DEV_BLKDEV
#define BOOTENV_DEV_NAME_SCSI BOOTENV_DEV_NAME_BLKDEV
#else
+#define BOOTENV_RUN_SCSI_INIT
+#define BOOTENV_SET_SCSI_NEED_INIT
#define BOOTENV_SHARED_SCSI
#define BOOTENV_DEV_SCSI \
BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_CMD_SCSI
\
BOOT_TARGET_DEVICES(BOOTENV_DEV) \
\
- "bootcmd=" BOOTENV_SET_USB_NEED_INIT \
+ "bootcmd=" BOOTENV_SET_USB_NEED_INIT BOOTENV_SET_SCSI_NEED_INIT \
"for target in ${boot_targets}; do " \
"run bootcmd_${target}; " \
"done\0"
#endif
/* EEPROM */
+#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define __USB_PHY_TYPE ulpi
+#ifdef CONFIG_PPC_B4860
+#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
+ "bank_intlv=cs0_cs1;" \
+ "en_cpc:cpc2;"
+#else
+#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
+#endif
+
#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=null," \
- "bank_intlv=cs0_cs1;" \
+ HWCONFIG \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
#endif
#ifdef CONFIG_T1042RDB_PI
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg
+#endif
+#ifdef CONFIG_T1042RDB
#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
#endif
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x70
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
#define I2C_MUX_CH_DEFAULT 0x8
#endif
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
#define CONFIG_QE
#define CONFIG_U_QE
#endif
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_QE_FW_ADDR 0x130000
#elif defined(CONFIG_SDCARD)
#endif
#ifdef CONFIG_FMAN_ENET
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
#endif
#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
#define CONFIG_BAUDRATE 115200
#define __USB_PHY_TYPE utmi
+#define RAMDISKFILE "t104xrdb/ramdisk.uboot"
#ifdef CONFIG_T1040RDB
#define FDTFILE "t1040rdb/t1040rdb.dtb"
-#define RAMDISKFILE "t1040rdb/ramdisk.uboot"
-#elif CONFIG_T1042RDB_PI
-#define FDTFILE "t1040rdb_pi/t1040rdb_pi.dtb"
-#define RAMDISKFILE "t1040rdb_pi/ramdisk.uboot"
+#elif defined(CONFIG_T1042RDB_PI)
+#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
+#elif defined(CONFIG_T1042RDB)
+#define FDTFILE "t1042rdb/t1042rdb.dtb"
#endif
#ifdef CONFIG_FSL_DIU_FB
# define CONFIG_TIMESTAMP
# define CONFIG_LZO
# ifdef CONFIG_ENABLE_VBOOT
-# define CONFIG_OF_CONTROL
-# define CONFIG_OF_SEPARATE
-# define CONFIG_DEFAULT_DEVICE_TREE am335x-boneblack
# define CONFIG_FIT_SIGNATURE
# define CONFIG_RSA
# endif
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
/* Allow tracing to be enabled */
#define CONFIG_TRACE
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX77686
-#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-arndale
#define CONFIG_PREBOOT
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
/* VDD core PMIC */
#define CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
-/* Enable fdt support for Beaver. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra30-beaver
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* High-level configuration options */
#define V_PROMPT "Tegra30 (Beaver) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Beaver"
*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x400
-#undef CONFIG_CMD_EXPORTENV
-#undef CONFIG_CMD_IMPORTENV
/*
#define CONFIG_CMD_MEMORY
#undef CONFIG_GZIP
#undef CONFIG_ZLIB
-#undef CONFIG_CMD_BOOTM
#undef CONFIG_BOOTM_RTEMS
#undef CONFIG_BOOTM_LINUX
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 1
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/* define to enable run status via led */
/* #define CONFIG_STATUS_LED */
*/
#define CONFIG_MISC_INIT_R
#define CONFIG_UART_CONSOLE 0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 1
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
*/
#define CONFIG_MISC_INIT_R
#define CONFIG_UART_CONSOLE 0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
*/
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/* FLASH/ETHERNET uses the same async bank */
#define SHARED_RESOURCES 1
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/* Define if want to do post memory test */
#undef CONFIG_POST
*/
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 1
#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
#define CONFIG_ADI_GPIO2
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BAUDRATE 57600
#define CONFIG_SYS_PROMPT "Acvilon> "
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
* Misc Settings
*/
#define CONFIG_UART_CONSOLE 0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Run core 1 from L1 SRAM start address when init uboot on core 0
#define CONFIG_BOOTCOMMAND "run nandboot"
#define CONFIG_BOOTDELAY 2
#define CONFIG_LOADADDR 0x2000000
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG
-#undef CONFIG_CMD_CRC32
/* define command we need always */
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_SOURCE
/* VDD core PMIC */
#define CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
-/* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra30-cardhu
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* High-level configuration options */
#define V_PROMPT "Tegra30 (Cardhu) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu"
#define FLASHBOOT_ENV_SETTINGS \
"flashboot=flread 20040000 1000000 300000;" \
"bootm 0x1000000\0"
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
"flashboot=flread 20040000 1000000 3c0000;" \
"bootm 0x1000000\0"
#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
"flashboot=flread 20040000 1000000 300000;" \
"bootm 0x1000000\0"
#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_UART_CONSOLE 1
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
#define CONFIG_ADI_GPIO2
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#include "tegra20-common.h"
-/* Enable FDT support */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra20-colibri_t20_iris
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Colibri) # "
#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20 on Iris"
#include "tegra30-common.h"
-#define CONFIG_DEFAULT_DEVICE_TREE tegra30-colibri
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
#define V_PROMPT "Colibri T30 # "
#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T30"
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_LAST_STAGE_INIT
-#undef CONFIG_CMD_BOOTM
#endif /* CONFIG_TRAILBLAZER */
#define CONFIG_LMB
#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-#define CONFIG_DEFAULT_DEVICE_TREE link
#define CONFIG_BOOTSTAGE
#define CONFIG_BOOTSTAGE_REPORT
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
#endif
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#include "tegra114-common.h"
-/* Enable fdt support for Dalmore. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra114-dalmore
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* High-level configuration options */
#define V_PROMPT "Tegra114 (Dalmore) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Dalmore"
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(2, 30) << 8))
+#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#endif
#define CONFIG_BOARD_COMMON
#define CONFIG_SYS_GENERIC_BOARD
-/* Enable fdt support */
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
#define CONFIG_SYS_CACHELINE_SIZE 32
/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_EXYNOS_SPL
-/* Enable fdt support for Exynos5250 */
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* Allow tracing to be enabled */
#define CONFIG_TRACE
#define CONFIG_CMD_TRACE
#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_BUS 0
- #define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8))
+ #define CONFIG_SF_DEFAULT_CS 0
/* GPIO 3-19 (21248) */
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 }
-#define CONFIG_CMD_IMPORTENV 1
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_RUN
#include <linux/sizes.h>
#include "tegra20-common.h"
-/* Enable fdt support for Harmony. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra20-harmony
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Harmony) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony"
#define CONFIG_BAUDRATE 115200
#define CONFIG_MISC_INIT_R /* needed for MAC address */
#define CONFIG_UART_CONSOLE 0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
#undef CONFIG_SHOW_BOOT_PROGRESS
/* Enable this if bootretry required; currently it's disabled */
#include "tegra124-common.h"
-/* Enable fdt support for Jetson TK1. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra124-jetson-tk1
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* High-level configuration options */
#define V_PROMPT "Tegra124 (Jetson TK1) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1"
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SPL_FRAMEWORK
#undef CONFIG_BOOTM_RTEMS
#undef CONFIG_GZIP
#undef CONFIG_ZLIB
-#undef CONFIG_CMD_CRC32
/* USB configuration */
#define CONFIG_USB_MUSB_DSPS
#include "tegra20-common.h"
-/* Enable fdt support for Medcom-Wide. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra20-medcom-wide
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Medcom-Wide) # "
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide"
/* MicroBlaze CPU */
#define MICROBLAZE_V5 1
-/* Open Firmware DTS */
-#define CONFIG_OF_CONTROL 1
-#define CONFIG_OF_EMBED 1
-#define CONFIG_DEFAULT_DEVICE_TREE microblaze-generic
-
/* linear and spi flash memory */
#ifdef XILINX_FLASH_START
#define FLASH
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SF_DEFAULT_CS (1 | 121 << 8)
+#define CONFIG_SF_DEFAULT_CS 1
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
#define CONFIG_SF_DEFAULT_SPEED 25000000
-#define CONFIG_ENV_SPI_CS (1 | 121 << 8)
+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_MAX_HZ 25000000
#define CONFIG_ENV_SPI_MODE (SPI_MODE_0)
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(4, 9) << 8))
+#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#endif
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(4, 11) << 8))
+#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#endif
#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8))
+#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 25000000
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
#endif
#define CONFIG_SYS_PROMPT "Odroid # " /* Monitor Command Prompt */
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE exynos4412-odroid
#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_PROMPT "ORIGEN # "
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-origen
/* High Level Configuration Options */
#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
#include <linux/sizes.h>
#include "tegra20-common.h"
-/* Enable fdt support for Paz00. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra20-paz00
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Paz00) MOD # "
#define CONFIG_TEGRA_BOARD_STRING "Compal Paz00"
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
#endif
#include <configs/exynos5420.h>
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE exynos5420-peach-pit
/* select serial console configuration */
#define CONFIG_SERIAL3 /* use SERIAL 3 */
#include "tegra20-common.h"
-/* Enable fdt support for Plutux. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra20-plutux
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Plutux) # "
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Plutux"
#define CONFIG_BOOTCOMMAND "run nandboot"
#define CONFIG_BOOTDELAY 2
#define CONFIG_LOADADDR 0x2000000
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#define CONFIG_SYS_PROMPT "Universal # " /* Monitor Command Prompt */
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-universal_c210
#define CONFIG_TIZEN /* TIZEN lib */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
#endif
/* Number of bits in a C 'long' on this architecture */
#define CONFIG_SANDBOX_BITS_PER_LONG 64
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_HOSTFILE
#define CONFIG_OF_LIBFDT
#define CONFIG_LMB
#define CONFIG_FIT
#define CONFIG_FIT_SIGNATURE
#define CONFIG_RSA
#define CONFIG_CMD_FDT
-#define CONFIG_DEFAULT_DEVICE_TREE sandbox
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_FS_FAT
#include "tegra20-common.h"
-/* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra20-seaboard
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* High-level configuration options */
#define V_PROMPT "Tegra20 (SeaBoard) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard"
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#include <configs/exynos5250-dt.h>
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-smdk5250
/* Enable FIT support and comparison */
#define CONFIG_FIT
#define CONFIG_SMDK5420 /* which is in a SMDK5420 */
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE exynos5420-smdk5420
/* select serial console configuration */
#define CONFIG_SERIAL3 /* use SERIAL 3 */
#include <configs/exynos5250-dt.h>
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-snow
/* Enable FIT support and comparison */
#define CONFIG_FIT
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
"flashboot=flread 20040000 1000000 300000;" \
"bootm 0x1000000\0"
#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
/*
* Pull in common ADI header for remaining command/environment setup
#include "tegra30-common.h"
-/* Enable fdt support for tec-ng. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra30-tec-ng
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* High-level configuration options */
#define V_PROMPT "Tegra30 (TEC-NG) # "
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier"
#include "tegra20-common.h"
-/* Enable fdt support for TEC. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra20-tec
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* High-level configuration options */
#define V_PROMPT "Tegra20 (TEC) # "
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier"
/* remove devicetree support */
#ifdef CONFIG_OF_CONTROL
-#undef CONFIG_OF_CONTROL
#endif
/* remove I2C support */
#define CONFIG_TRATS
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-trats
#define CONFIG_TIZEN /* TIZEN lib */
#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE exynos4412-trats2
#define CONFIG_TIZEN /* TIZEN lib */
#include <linux/sizes.h>
#include "tegra20-common.h"
-/* Enable fdt support for TrimSlice. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra20-trimslice
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* High-level configuration options */
#define V_PROMPT "Tegra20 (TrimSlice) # "
#define CONFIG_TEGRA_BOARD_STRING "Compulab Trimslice"
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#undef CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_IN_SPI_FLASH
#undef CONFIG_CMD_BEDBUG
#undef CONFIG_CMD_CACHE
#undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_CRC32
#undef CONFIG_CMD_DHCP
#undef CONFIG_CMD_EEPROM
#undef CONFIG_CMD_EEPROM
#include "tegra124-common.h"
-/* Enable fdt support for Venice2. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra124-venice2
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* High-level configuration options */
#define V_PROMPT "Tegra124 (Venice2) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2"
#include <linux/sizes.h>
#include "tegra20-common.h"
-/* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra20-ventana
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Ventana) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Ventana"
/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
-#define CONFIG_DEFAULT_DEVICE_TREE vexpress64
/* SMP Spin Table Definitions */
#ifdef CONFIG_BASE_FVP
* Use gpio 4 pin 25 as chip select for SPI flash
* This corresponds to gpio 121
*/
-#define CONFIG_SF_DEFAULT_CS (1 | (121 << 8))
+#define CONFIG_SF_DEFAULT_CS 1
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 25000000
-#define CONFIG_ENV_SPI_CS (1 | (121 << 8))
+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_MAX_HZ 25000000
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
#include <linux/sizes.h>
#include "tegra20-common.h"
-/* Enable fdt support for Whistler. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra20-whistler
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Whistler) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Whistler"
#define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */
/* FDT support */
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
#define CONFIG_DISPLAY_BOARDINFO_LATE
/* RSA support */
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
-#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_OF_SEPARATE)
-# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
-#else
-# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
-#endif
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
#endif
/* Disable dcache for SPL just for sure */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_DCACHE_OFF
#undef CONFIG_FPGA
-#undef CONFIG_OF_CONTROL
#endif
/* Address in RAM where the parameters must be copied by SPL. */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_BUS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000
-#define CONFIG_SPL_SPI_CS 0
#endif
/* for booting directly linux */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_SDHCI0
-#define CONFIG_DEFAULT_DEVICE_TREE zynq-microzed
#include <configs/zynq-common.h>
#define CONFIG_ZYNQ_I2C0
#define CONFIG_ZYNQ_EEPROM
#define CONFIG_ZYNQ_BOOT_FREEBSD
-#define CONFIG_DEFAULT_DEVICE_TREE zynq-zc702
#include <configs/zynq-common.h>
# define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
# define CONFIG_ZYNQ_SDHCI0
# define CONFIG_ZYNQ_SPI
-# define CONFIG_DEFAULT_DEVICE_TREE zynq-zc770-xm010
#elif defined(CONFIG_ZC770_XM012)
# define CONFIG_ZYNQ_SERIAL_UART1
# undef CONFIG_SYS_NO_FLASH
-# define CONFIG_DEFAULT_DEVICE_TREE zynq-zc770-xm012
#elif defined(CONFIG_ZC770_XM013)
# define CONFIG_ZYNQ_SERIAL_UART0
# define CONFIG_ZYNQ_GEM1
# define CONFIG_ZYNQ_GEM_PHY_ADDR1 7
-# define CONFIG_DEFAULT_DEVICE_TREE zynq-zc770-xm013
#else
# define CONFIG_ZYNQ_SERIAL_UART0
#define CONFIG_ZYNQ_USB
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_BOOT_FREEBSD
-#define CONFIG_DEFAULT_DEVICE_TREE zynq-zed
#include <configs/zynq-common.h>
--- /dev/null
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+void fb_mmc_flash_write(const char *cmd, void *download_buffer,
+ unsigned int download_bytes, char *response);
* together. Assuming _list and _entry are the list and entry names,
* then the corresponding input section name is
*
- * _u_boot_list + _2_ + @_list + _2_ + @_entry
+ * .u_boot_list_ + 2_ + @_list + _2_ + @_entry
*
* and the C variable name is
*
- * .u_boot_list_ + 2_ + @_list + _2_ + @_entry
+ * _u_boot_list + _2_ + @_list + _2_ + @_entry
*
* This ensures uniqueness for both input section and C variable name.
*
#endif
#define __deprecated __attribute__((deprecated))
+#ifndef __packed
#define __packed __attribute__((packed))
+#endif
+#ifndef __weak
#define __weak __attribute__((weak))
+#endif
/*
* it doesn't make sense on ARM (currently the only user of __naked) to trace
* would be.
* [...]
*/
+#ifndef __pure
#define __pure __attribute__((pure))
+#endif
+#ifndef __aligned
#define __aligned(x) __attribute__((aligned(x)))
+#endif
#define __printf(a, b) __attribute__((format(printf, a, b)))
#define __scanf(a, b) __attribute__((format(scanf, a, b)))
#define noinline __attribute__((noinline))
*/
#define uninitialized_var(x) x = x
+#ifndef __always_inline
#define __always_inline inline __attribute__((always_inline))
+#endif
#include <linux/types.h>
#include <linux/compiler.h>
+#ifndef CONFIG_SF_DEFAULT_SPEED
+# define CONFIG_SF_DEFAULT_SPEED 1000000
+#endif
+#ifndef CONFIG_SF_DEFAULT_MODE
+# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+#endif
+#ifndef CONFIG_SF_DEFAULT_CS
+# define CONFIG_SF_DEFAULT_CS 0
+#endif
+#ifndef CONFIG_SF_DEFAULT_BUS
+# define CONFIG_SF_DEFAULT_BUS 0
+#endif
+
/* sf param flags */
#define SECT_4K 1 << 1
#define SECT_32K 1 << 2
--- /dev/null
+menu "Library routines"
+
+config CC_OPTIMIZE_LIBS_FOR_SPEED
+ bool "Optimize libraries for speed"
+ help
+ Enabling this option will pass "-O2" to gcc when compiling
+ under "lib" directory.
+
+ If unsure, say N.
+
+endmenu
--- /dev/null
+#
+# Network configuration
+#
+
+menuconfig NET
+ bool "Networking support"
+
+if NET
+
+endif # if NET
| sed '/=/ {s/=/ /;q; } ; { s/$$/ 1/; }'; \
done; \
echo \#define CONFIG_BOARDDIR board/$(if $(VENDOR),$(VENDOR)/)$(BOARD);\
- echo \#include \<config_cmd_defaults.h\>; \
echo \#include \<config_defaults.h\>; \
echo \#include \<configs/$(CONFIG_SYS_CONFIG_NAME).h\>; \
echo \#include \<asm/config.h\>; \
"please, no space before tabs\n" . $herevet) &&
$fix) {
while ($fixed[$linenr - 1] =~
- s/(^\+.*) {8,8}+\t/$1\t\t/) {}
+ s/(^\+.*) {8,8}\t/$1\t\t/) {}
while ($fixed[$linenr - 1] =~
s/(^\+.*) +\t/$1\t/) {}
}
--- /dev/null
+#!/bin/sh
+
+# Test for U-Boot cli including command repeat
+
+BASE="$(dirname $0)"
+. $BASE/common.sh
+
+run_test() {
+ ./${OUTPUT_DIR}/u-boot <<END
+setenv ctrlc_ignore y
+md 0
+
+reset
+END
+}
+check_results() {
+ echo "Check results"
+
+ grep -q 00000100 ${tmp} || fail "Command did not repeat"
+}
+
+echo "Test CLI repeat"
+echo
+tmp="$(tempfile)"
+build_uboot
+run_test >${tmp}
+check_results ${tmp}
+rm ${tmp}
+echo "Test passed"
--- /dev/null
+#!/bin/sh
+
+OUTPUT_DIR=sandbox
+
+fail() {
+ echo "Test failed: $1"
+ if [ -n ${tmp} ]; then
+ rm ${tmp}
+ fi
+ exit 1
+}
+
+build_uboot() {
+ echo "Build sandbox"
+ OPTS="O=${OUTPUT_DIR} $1"
+ NUM_CPUS=$(grep -c processor /proc/cpuinfo)
+ echo ${OPTS}
+ make ${OPTS} sandbox_config
+ make ${OPTS} -s -j${NUM_CPUS}
+}
# Simple test script for tracing with sandbox
-OUTPUT_DIR=sandbox
TRACE_OPT="FTRACE=1"
-fail() {
- echo "Test failed: $1"
- if [ -n ${tmp} ]; then
- rm ${tmp}
- fi
- exit 1
-}
-
-build_uboot() {
- echo "Build sandbox"
- OPTS="O=${OUTPUT_DIR} ${TRACE_OPT}"
- NUM_CPUS=$(grep -c processor /proc/cpuinfo)
- make ${OPTS} sandbox_config
- make ${OPTS} -s -j${NUM_CPUS}
-}
+BASE="$(dirname $0)/.."
+. $BASE/common.sh
run_trace() {
echo "Run trace"
./${OUTPUT_DIR}/u-boot <<END
- trace stats
- hash sha256 0 10000
- trace pause
- trace stats
- hash sha256 0 10000
- trace stats
- trace resume
- hash sha256 0 10000
- trace pause
- trace stats
- reset
+trace stats
+hash sha256 0 10000
+trace pause
+trace stats
+hash sha256 0 10000
+trace stats
+trace resume
+hash sha256 0 10000
+trace pause
+trace stats
+reset
END
}
echo "Simple trace test / sanity check using sandbox"
echo
tmp="$(tempfile)"
-build_uboot
+build_uboot "${TRACE_OPT}"
run_trace >${tmp}
check_results ${tmp}
rm ${tmp}
endif
always := fw_printenv
-hostprogs-y := fw_printenv_unstripped
+hostprogs-y := fw_printenv
-fw_printenv_unstripped-objs := fw_env.o fw_env_main.o \
+fw_printenv-objs := fw_env.o fw_env_main.o \
crc32.o ctype.o linux_string.o \
env_attr.o env_flags.o aes.o
-quiet_cmd_strip = STRIP $@
- cmd_strip = $(STRIP) -o $@ $<
+quiet_cmd_crosstools_strip = STRIP $^
+ cmd_crosstools_strip = $(STRIP) $^; touch $@
-$(obj)/fw_printenv: $(obj)/fw_printenv_unstripped FORCE
- $(call if_changed,strip)
+$(obj)/.strip: $(obj)/fw_printenv
+ $(call cmd,crosstools_strip)
+
+always += .strip
maintainers = []
status = '-'
for line in open(file):
+ # Check also commented maintainers
+ if line[:3] == '#M:':
+ line = line[1:]
tag, rest = line[:2], line[2:].strip()
if tag == 'M:':
maintainers.append(rest)
+++ /dev/null
-#! /usr/bin/python
-########################################################################
-#
-# reorder and reformat a file in columns
-#
-# this utility takes lines from its standard input and reproduces them,
-# partially reordered and reformatted, on its standard output.
-#
-# It has the same effect as a 'sort | column -t', with the exception
-# that empty lines, as well as lines which start with a '#' sign, are
-# not affected, i.e. they keep their position and formatting, and act
-# as separators, i.e. the parts before and after them are each sorted
-# separately (but overall field widths are computed across the whole
-# input).
-#
-# Options:
-# -i:
-# --ignore-case:
-# Do not consider case when sorting.
-# -d:
-# --default:
-# What to chage empty fields to.
-# -s <N>:
-# --split=<N>:
-# Treat only the first N whitespace sequences as separators.
-# line content after the Nth separator will count as only one
-# field even if it contains whitespace.
-# Example : '-s 2' causes input 'a b c d e' to be split into
-# three fields, 'a', 'b', and 'c d e'.
-#
-# boards.cfg requires -ids 6.
-#
-########################################################################
-
-import sys, getopt, locale
-
-# ensure we sort using the C locale.
-
-locale.setlocale(locale.LC_ALL, 'C')
-
-# check options
-
-maxsplit = 0
-ignore_case = 0
-default_field =''
-
-try:
- opts, args = getopt.getopt(sys.argv[1:], "id:s:",
- ["ignore-case","default","split="])
-except getopt.GetoptError as err:
- print str(err) # will print something like "option -a not recognized"
- sys.exit(2)
-
-for o, a in opts:
- if o in ("-s", "--split"):
- maxsplit = eval(a)
- elif o in ("-i", "--ignore-case"):
- ignore_case = 1
- elif o in ("-d", "--default"):
- default_field = a
- else:
- assert False, "unhandled option"
-
-# collect all lines from standard input and, for the ones which must be
-# reformatted and sorted, count their fields and compute each field's
-# maximum size
-
-input_lines = []
-field_width = []
-
-for line in sys.stdin:
- # remove final end of line
- input_line = line.strip('\n')
- if (len(input_line)>0) and (input_line[0] != '#'):
- # sortable line: split into fields
- fields = input_line.split(None,maxsplit)
- # if there are new fields, top up field_widths
- for f in range(len(field_width), len(fields)):
- field_width.append(0)
- # compute the maximum witdh of each field
- for f in range(len(fields)):
- field_width[f] = max(field_width[f],len(fields[f]))
- # collect the line for next stage
- input_lines.append(input_line)
-
-# run through collected input lines, collect the ones which must be
-# reformatted and sorted, and whenever a non-reformattable, non-sortable
-# line is met, sort the collected lines before it and append them to the
-# output lines, then add the non-sortable line too.
-
-output_lines = []
-sortable_lines = []
-for input_line in input_lines:
- if (len(input_line)>0) and (input_line[0] != '#'):
- # this line should be reformatted and sorted
- input_fields = input_line.split(None,maxsplit)
- output_fields = [];
- # reformat each field to this field's column width
- for f in range(len(input_fields)):
- output_field = input_fields[f];
- output_fields.append(output_field.ljust(field_width[f]))
- # any missing field is set to default if it exists
- if default_field != '':
- for f in range(len(input_fields),len(field_width)):
- output_fields.append(default_field.ljust(field_width[f]))
- # join fields using two spaces, like column -t would
- output_line = ' '.join(output_fields);
- # collect line for later
- sortable_lines.append(output_line)
- else:
- # this line is non-sortable
- # sort collected sortable lines
- if ignore_case!=0:
- sortable_lines.sort(key=lambda x: str.lower(locale.strxfrm(x)))
- else:
- sortable_lines.sort(key=lambda x: locale.strxfrm(x))
- # append sortable lines to the final output
- output_lines.extend(sortable_lines)
- sortable_lines = []
- # append non-sortable line to the final output
- output_lines.append(input_line)
-# maybe we had sortable lines pending, so append them to the final output
-if ignore_case!=0:
- sortable_lines.sort(key=lambda x: str.lower(locale.strxfrm(x)))
-else:
- sortable_lines.sort(key=lambda x: locale.strxfrm(x))
-output_lines.extend(sortable_lines)
-
-# run through output lines and print them, except rightmost whitespace
-
-for output_line in output_lines:
- print output_line.rstrip()
projects / karo-tx-uboot.git / commitdiff