am335x: pepper: Add Gumstix Pepper AM335x-based machine

This adds the Gumstix Pepper[1] single-board computer based on the
TI AM335x processor. Schematics are available [2].

[1] https://store.gumstix.com/index.php/products/344/
[2] https://pubs.gumstix.com/boards/PEPPER/

Signed-off-by: Ash Charles <ash@gumstix.com>
[trini: Move 'cdev' in board.c down to under #ifdef's where it's used]
Signed-off-by: Tom Rini <trini@ti.com>

diff --git a/board/gumstix/pepper/Makefile b/board/gumstix/pepper/Makefile
new file mode 100644 (file)
index 0000000..ecb1d61
--- /dev/null
+++ b/board/gumstix/pepper/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y  += mux.o
+endif
+
+obj-y  += board.o

diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c
new file mode 100644 (file)
index 0000000..75aac49
--- /dev/null
+++ b/board/gumstix/pepper/board.c
@@ -0,0 +1,226 @@
+/*
+ * Board functions for Gumstix Pepper and AM335x-based boards
+ *
+ * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
+ * Based on board/ti/am335x/board.c from Texas Instruments, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <environment.h>
+#include <watchdog.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+static const struct ddr_data ddr2_data = {
+       .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
+                         (MT47H128M16RT25E_RD_DQS<<20) |
+                         (MT47H128M16RT25E_RD_DQS<<10) |
+                         (MT47H128M16RT25E_RD_DQS<<0)),
+       .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
+                         (MT47H128M16RT25E_WR_DQS<<20) |
+                         (MT47H128M16RT25E_WR_DQS<<10) |
+                         (MT47H128M16RT25E_WR_DQS<<0)),
+       .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
+                        (MT47H128M16RT25E_PHY_WRLVL<<20) |
+                        (MT47H128M16RT25E_PHY_WRLVL<<10) |
+                        (MT47H128M16RT25E_PHY_WRLVL<<0)),
+       .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
+                        (MT47H128M16RT25E_PHY_GATELVL<<20) |
+                        (MT47H128M16RT25E_PHY_GATELVL<<10) |
+                        (MT47H128M16RT25E_PHY_GATELVL<<0)),
+       .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
+                         (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
+                         (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
+                         (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
+       .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
+                         (MT47H128M16RT25E_PHY_WR_DATA<<20) |
+                         (MT47H128M16RT25E_PHY_WR_DATA<<10) |
+                         (MT47H128M16RT25E_PHY_WR_DATA<<0)),
+};
+
+static const struct cmd_control ddr2_cmd_ctrl_data = {
+       .cmd0csratio = MT47H128M16RT25E_RATIO,
+       .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
+
+       .cmd1csratio = MT47H128M16RT25E_RATIO,
+       .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
+
+       .cmd2csratio = MT47H128M16RT25E_RATIO,
+       .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
+};
+
+static const struct emif_regs ddr2_emif_reg_data = {
+       .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+       .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+       .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+       .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+       .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+       .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+       /* break into full u-boot on 'c' */
+       return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+#define OSC    (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+       return &dpll_ddr;
+}
+
+void set_uart_mux_conf(void)
+{
+       enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+       enable_board_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs = {
+       .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
+       .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
+       .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
+       .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
+       .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+       config_ddr(266, &ioregs, &ddr2_data,
+                  &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
+}
+#endif
+
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+       hw_watchdog_init();
+#endif
+
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+       gpmc_init();
+
+       return 0;
+}
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+       (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+static void cpsw_control(int enabled)
+{
+       /* VTP can be added here */
+
+       return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+       {
+               .slave_reg_ofs  = 0x208,
+               .sliver_reg_ofs = 0xd80,
+               .phy_addr       = 0,
+               .phy_if         = PHY_INTERFACE_MODE_RGMII,
+       },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+       .mdio_base              = CPSW_MDIO_BASE,
+       .cpsw_base              = CPSW_BASE,
+       .mdio_div               = 0xff,
+       .channels               = 8,
+       .cpdma_reg_ofs          = 0x800,
+       .slaves                 = 1,
+       .slave_data             = cpsw_slaves,
+       .ale_reg_ofs            = 0xd00,
+       .ale_entries            = 1024,
+       .host_port_reg_ofs      = 0x108,
+       .hw_stats_reg_ofs       = 0x900,
+       .bd_ram_ofs             = 0x2000,
+       .mac_control            = (1 << 5),
+       .control                = cpsw_control,
+       .host_port_num          = 0,
+       .version                = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+       int rv, n = 0;
+       uint8_t mac_addr[6];
+       uint32_t mac_hi, mac_lo;
+       const char *devname;
+
+       if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+               /* try reading mac address from efuse */
+               mac_lo = readl(&cdev->macid0l);
+               mac_hi = readl(&cdev->macid0h);
+               mac_addr[0] = mac_hi & 0xFF;
+               mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+               mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+               mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+               mac_addr[4] = mac_lo & 0xFF;
+               mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+               if (is_valid_ether_addr(mac_addr))
+                       eth_setenv_enetaddr("ethaddr", mac_addr);
+       }
+
+       writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
+
+       rv = cpsw_register(&cpsw_data);
+       if (rv < 0)
+               printf("Error %d registering CPSW switch\n", rv);
+       else
+               n += rv;
+
+       /*
+        *
+        * CPSW RGMII Internal Delay Mode is not supported in all PVT
+        * operating points.  So we must set the TX clock delay feature
+        * in the KSZ9021 PHY.  Since we only support a single ethernet
+        * device in U-Boot, we only do this for the current instance.
+        */
+       devname = miiphy_get_current_dev();
+       /* max rx/tx clock delay, min rx/tx control delay */
+       miiphy_write(devname, 0x0, 0x0b, 0x8104);
+       miiphy_write(devname, 0x0, 0xc, 0xa0a0);
+
+       /* min rx data delay */
+       miiphy_write(devname, 0x0, 0x0b, 0x8105);
+       miiphy_write(devname, 0x0, 0x0c, 0x0000);
+
+       /* min tx data delay */
+       miiphy_write(devname, 0x0, 0x0b, 0x8106);
+       miiphy_write(devname, 0x0, 0x0c, 0x0000);
+
+       return n;
+}
+#endif

diff --git a/board/gumstix/pepper/board.h b/board/gumstix/pepper/board.h
new file mode 100644 (file)
index 0000000..0512735
--- /dev/null
+++ b/board/gumstix/pepper/board.h
@@ -0,0 +1,19 @@
+/*
+ * Gumstix Pepper and AM335x-based boards information header
+ *
+ * Copyright (C) 2014, Gumstix, Inc. - http://www.gumstix.com/
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We must be able to enable uart0, for initial output. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif

diff --git a/board/gumstix/pepper/mux.c b/board/gumstix/pepper/mux.c
new file mode 100644 (file)
index 0000000..50b1266
--- /dev/null
+++ b/board/gumstix/pepper/mux.c
@@ -0,0 +1,78 @@
+/*
+ * Muxing for Gumstix Pepper and AM335x-based boards
+ *
+ * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+       {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},  /* UART0_RXD */
+       {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},              /* UART0_TXD */
+       {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+       {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT3 */
+       {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT2 */
+       {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT1 */
+       {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT0 */
+       {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},   /* MMC0_CLK */
+       {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},   /* MMC0_CMD */
+       {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},   /* MMC0_CD */
+       {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+       /* I2C_DATA */
+       {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+       /* I2C_SCLK */
+       {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+       {-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+       {OFFSET(mii1_txen), MODE(2)},                   /* RGMII1_TCTL */
+       {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},        /* RGMII1_RCTL */
+       {OFFSET(mii1_txd3), MODE(2)},                   /* RGMII1_TD3 */
+       {OFFSET(mii1_txd2), MODE(2)},                   /* RGMII1_TD2 */
+       {OFFSET(mii1_txd1), MODE(2)},                   /* RGMII1_TD1 */
+       {OFFSET(mii1_txd0), MODE(2)},                   /* RGMII1_TD0 */
+       {OFFSET(mii1_txclk), MODE(2)},                  /* RGMII1_TCLK */
+       {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},       /* RGMII1_RCLK */
+       {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},        /* RGMII1_RD3 */
+       {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},        /* RGMII1_RD2 */
+       {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},        /* RGMII1_RD1 */
+       {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},        /* RGMII1_RD0 */
+       {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+       {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},        /* MDIO_CLK */
+       {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE},     /* ETH_INT */
+       {OFFSET(mii1_col), MODE(7) | PULLUP_EN},        /* PHY_NRESET */
+       {OFFSET(xdma_event_intr1), MODE(3)},
+       {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+       configure_module_pin_mux(uart0_pin_mux);
+}
+
+/*
+ * Do board-specific muxes.
+ */
+void enable_board_pin_mux(void)
+{
+       /* I2C0 */
+       configure_module_pin_mux(i2c0_pin_mux);
+       /* SD Card */
+       configure_module_pin_mux(mmc0_pin_mux);
+       /* Ethernet pinmux. */
+       configure_module_pin_mux(rgmii1_pin_mux);
+}

diff --git a/boards.cfg b/boards.cfg
index 3681339e544dea1720cf40995219bcf6583ef2ec..8aaf74939f8abe7237af3e9a47668d352c3c4f36 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -257,6 +257,7 @@ Active  arm         armv7          am33xx      BuR             tseries
 Active  arm         armv7          am33xx      BuR             tseries             tseries_nand                         tseries:SERIAL1,CONS_INDEX=1,NAND                                                                                                 Hannes Petermaier <hannes.petermaier@br-automation.com>
 Active  arm         armv7          am33xx      BuR             tseries             tseries_spi                          tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT                                                                                   Hannes Petermaier <hannes.petermaier@br-automation.com>
 Active  arm         armv7          am33xx      compulab        cm_t335             cm_t335                              -                                                                                                                                 Igor Grinberg <grinberg@compulab.co.il>
+Active  arm         armv7          am33xx      gumstix         pepper              pepper                               -                                                                                                                                 Ash Charles <ash@gumstix.com>
 Active  arm         armv7          am33xx      isee            igep0033            am335x_igep0033                      -                                                                                                                                 Enric Balletbo i Serra <eballetbo@iseebcn.com>
 Active  arm         armv7          am33xx      phytec          pcm051              pcm051_rev1                          pcm051:REV1                                                                                                                       Lars Poeschel <poeschel@lemonage.de>
 Active  arm         armv7          am33xx      phytec          pcm051              pcm051_rev3                          pcm051:REV3                                                                                                                       Lars Poeschel <poeschel@lemonage.de>

diff --git a/include/configs/pepper.h b/include/configs/pepper.h
new file mode 100644 (file)
index 0000000..cc153ab
--- /dev/null
+++ b/include/configs/pepper.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2013 Gumstix, Inc. - http://www.gumstix.com/
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_PEPPER_H
+#define __CONFIG_PEPPER_H
+
+#define CONFIG_MMC
+#include <configs/ti_am335x_common.h>
+
+#undef CONFIG_BOARD_LATE_INIT
+#undef CONFIG_SPL_OS_BOOT
+
+/* Clock defines */
+#define V_OSCK                         24000000  /* Clock output from T2 */
+#define V_SCLK                         (V_OSCK)
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT              "pepper# "
+
+/* Mach type */
+#define MACH_TYPE_PEPPER               4207    /* Until the next sync */
+#define CONFIG_MACH_TYPE               MACH_TYPE_PEPPER
+
+#define CONFIG_ENV_SIZE                        (128 << 10)     /* 128 KiB */
+#define CONFIG_ENV_IS_NOWHERE
+/* Display cpuinfo */
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       DEFAULT_LINUX_BOOT_ENV \
+       "bootdir=/boot\0" \
+       "bootfile=zImage\0" \
+       "fdtfile=am335x-pepper.dtb\0" \
+       "console=ttyO0,115200n8\0" \
+       "optargs=\0" \
+       "mmcdev=0\0" \
+       "mmcroot=/dev/mmcblk0p2 rw\0" \
+       "mmcrootfstype=ext3 rootwait\0" \
+       "mmcargs=setenv bootargs console=${console} " \
+               "${optargs} " \
+               "root=${mmcroot} " \
+               "rootfstype=${mmcrootfstype}\0" \
+       "bootenv=uEnv.txt\0" \
+       "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+       "importbootenv=echo Importing environment from mmc ...; " \
+               "env import -t ${loadaddr} ${filesize}\0" \
+       "mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
+               "load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+       "loaduimage=fatload mmc ${mmcdev}:1 ${loadaddr} uImage\0" \
+       "uimageboot=echo Booting from mmc${mmcdev} ...; " \
+               "run mmcargs; " \
+               "bootm ${loadaddr}\0" \
+       "mmcboot=echo Booting from mmc ...; " \
+               "run mmcargs; " \
+               "bootz ${loadaddr} - ${fdtaddr}\0" \
+       "ubiboot=echo Booting from nand (ubifs) ...; " \
+               "run ubiargs; run ubiload; " \
+               "bootz ${loadaddr} - ${fdtaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+       "mmc dev ${mmcdev}; if mmc rescan; then " \
+               "echo SD/MMC found on device ${mmcdev};" \
+               "if run loadbootenv; then " \
+                       "echo Loaded environment from ${bootenv};" \
+                       "run importbootenv;" \
+               "fi;" \
+               "if test -n $uenvcmd; then " \
+                       "echo Running uenvcmd ...;" \
+                       "run uenvcmd;" \
+               "fi;" \
+               "if run mmcload; then " \
+                       "run mmcboot;" \
+               "fi;" \
+               "if run loaduimage; then " \
+                       "run uimageboot;" \
+               "fi;" \
+       "fi;" \
+
+/* Serial console configuration */
+#define CONFIG_CONS_INDEX              1 /* UART0 */
+#define CONFIG_SERIAL1                 1
+#define CONFIG_SYS_NS16550_COM1                0x44e09000
+
+/* Ethernet support */
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR                        0
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_PHY_RESET_DELAY 1000
+
+/* SPL */
+#define CONFIG_SPL_LDSCRIPT            "$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#endif /* __CONFIG_PEPPER_H */