LIB = $(obj)lib$(SOC).o
COBJS = soc.o clock.o
-ifneq ($(CONFIG_SYS_MX5_IOMUX_V3),)
- COBJS += iomux-v3.o
-else
+ifeq ($(CONFIG_SYS_MX5_IOMUX_V3),)
COBJS += iomux.o
endif
SOBJS = lowlevel_init.o
+++ /dev/null
-/*
- * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- * <armlinux@phytec.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux-v3.h>
-#include <asm/arch/sys_proto.h>
-
-static void __iomem *base = (void __iomem *)IOMUXC_BASE_ADDR;
-
-/*
- * configures a single pad in the iomuxer
- */
-int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
-{
- u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
- u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
- u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
- u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
- u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
- u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
-
- if (mux_ctrl_ofs)
- __raw_writel(mux_mode, base + mux_ctrl_ofs);
-
- if (sel_input_ofs)
- __raw_writel(sel_input, base + sel_input_ofs);
-
- if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
- __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
-
- return 0;
-}
-
-int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list, unsigned count)
-{
- const iomux_v3_cfg_t *p = pad_list;
- int i;
- int ret;
-
- for (i = 0; i < count; i++) {
- ret = mxc_iomux_v3_setup_pad(*p);
- if (ret)
- return ret;
- p++;
- }
- return 0;
-}
--- /dev/null
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+ DEFINE(CCM_CCR, offsetof(struct mxc_ccm_reg, ccr));
+ DEFINE(CCM_CCDR, offsetof(struct mxc_ccm_reg, ccdr));
+ DEFINE(CCM_CSR, offsetof(struct mxc_ccm_reg, csr));
+ DEFINE(CCM_CCSR, offsetof(struct mxc_ccm_reg, ccsr));
+ DEFINE(CCM_CACRR, offsetof(struct mxc_ccm_reg, cacrr));
+ DEFINE(CCM_CBCDR, offsetof(struct mxc_ccm_reg, cbcdr));
+ DEFINE(CCM_CBCMR, offsetof(struct mxc_ccm_reg, cbcmr));
+ DEFINE(CCM_CSCMR1, offsetof(struct mxc_ccm_reg, cscmr1));
+ DEFINE(CCM_CSCMR2, offsetof(struct mxc_ccm_reg, cscmr2));
+ DEFINE(CCM_CSCDR1, offsetof(struct mxc_ccm_reg, cscdr1));
+ DEFINE(CCM_CS1CDR, offsetof(struct mxc_ccm_reg, cs1cdr));
+ DEFINE(CCM_CS2CDR, offsetof(struct mxc_ccm_reg, cs2cdr));
+ DEFINE(CCM_CDCDR, offsetof(struct mxc_ccm_reg, cdcdr));
+ DEFINE(CCM_CHSCCDR, offsetof(struct mxc_ccm_reg, chsccdr));
+ DEFINE(CCM_CSCDR2, offsetof(struct mxc_ccm_reg, cscdr2));
+ DEFINE(CCM_CSCDR3, offsetof(struct mxc_ccm_reg, cscdr3));
+ DEFINE(CCM_CSCDR4, offsetof(struct mxc_ccm_reg, cscdr4));
+ DEFINE(CCM_CDHIPR, offsetof(struct mxc_ccm_reg, cdhipr));
+ DEFINE(CCM_CDCR, offsetof(struct mxc_ccm_reg, cdcr));
+ DEFINE(CCM_CTOR, offsetof(struct mxc_ccm_reg, ctor));
+ DEFINE(CCM_CLPCR, offsetof(struct mxc_ccm_reg, clpcr));
+ DEFINE(CCM_CISR, offsetof(struct mxc_ccm_reg, cisr));
+ DEFINE(CCM_CIMR, offsetof(struct mxc_ccm_reg, cimr));
+ DEFINE(CCM_CCOSR, offsetof(struct mxc_ccm_reg, ccosr));
+ DEFINE(CCM_CGPR, offsetof(struct mxc_ccm_reg, cgpr));
+ DEFINE(CCM_CCGR0, offsetof(struct mxc_ccm_reg, CCGR0));
+ DEFINE(CCM_CCGR1, offsetof(struct mxc_ccm_reg, CCGR1));
+ DEFINE(CCM_CCGR2, offsetof(struct mxc_ccm_reg, CCGR2));
+ DEFINE(CCM_CCGR3, offsetof(struct mxc_ccm_reg, CCGR3));
+ DEFINE(CCM_CCGR4, offsetof(struct mxc_ccm_reg, CCGR4));
+ DEFINE(CCM_CCGR5, offsetof(struct mxc_ccm_reg, CCGR5));
+ DEFINE(CCM_CCGR6, offsetof(struct mxc_ccm_reg, CCGR6));
+ DEFINE(CCM_CCGR7, offsetof(struct mxc_ccm_reg, CCGR7));
+ DEFINE(CCM_CMEOR, offsetof(struct mxc_ccm_reg, cmeor));
+
+ DEFINE(ANATOP_PLL_ENET, offsetof(struct anatop_regs, pll_enet));
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/include/ "imx6qdl.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ operating-points = <
+ /* kHz uV */
+ 792000 1150000
+ 396000 950000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clks 104>, <&clks 6>, <&clks 16>,
+ <&clks 17>, <&clks 170>;
+ clock-names = "arm", "pll2_pfd2_396m", "step",
+ "pll1_sw", "pll1_sys";
+ arm-supply = <®_arm>;
+ pu-supply = <®_pu>;
+ soc-supply = <®_soc>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ soc {
+ aips-bus@02000000 { /* AIPS1 */
+ spba-bus@02000000 {
+ ecspi5: ecspi@02018000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,iMX6DL-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02018000 0x4000>;
+ interrupts = <0 35 0x04>;
+ clocks = <&clks 116>, <&clks 116>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+ };
+
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,iMX6DL-iomuxc";
+ reg = <0x020e0000 0x4000>;
+
+ /* shared pinctrl settings */
+ audmux {
+ pinctrl_audmux_1: audmux-1 {
+ fsl,pins = <
+ 18 0x80000000 /* MX6DL_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
+ 1586 0x80000000 /* MX6DL_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
+ 11 0x80000000 /* MX6DL_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
+ 3 0x80000000 /* MX6DL_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+ >;
+ };
+ };
+
+ ecspi1 {
+ pinctrl_ecspi1_1: ecspi1grp-1 {
+ fsl,pins = <
+ 101 0x100b1 /* MX6DL_PAD_EIM_D17__ECSPI1_MISO */
+ 109 0x100b1 /* MX6DL_PAD_EIM_D18__ECSPI1_MOSI */
+ 94 0x100b1 /* MX6DL_PAD_EIM_D16__ECSPI1_SCLK */
+ >;
+ };
+ };
+
+ enet {
+ pinctrl_enet_1: enetgrp-1 {
+ fsl,pins = <
+ 695 0x1b0b0 /* MX6DL_PAD_ENET_MDIO__ENET_MDIO */
+ 756 0x1b0b0 /* MX6DL_PAD_ENET_MDC__ENET_MDC */
+ 24 0x1b0b0 /* MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC */
+ 30 0x1b0b0 /* MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+ 34 0x1b0b0 /* MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+ 39 0x1b0b0 /* MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+ 44 0x1b0b0 /* MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+ 56 0x1b0b0 /* MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+ 702 0x1b0b0 /* MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK */
+ 74 0x1b0b0 /* MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC */
+ 52 0x1b0b0 /* MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+ 61 0x1b0b0 /* MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+ 66 0x1b0b0 /* MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+ 70 0x1b0b0 /* MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+ 48 0x1b0b0 /* MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+ 1033 0x4001b0a8 /* MX6DL_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
+ >;
+ };
+
+ pinctrl_enet_2: enetgrp-2 {
+ fsl,pins = <
+ 890 0x1b0b0 /* MX6DL_PAD_KEY_COL1__ENET_MDIO */
+ 909 0x1b0b0 /* MX6DL_PAD_KEY_COL2__ENET_MDC */
+ 24 0x1b0b0 /* MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC */
+ 30 0x1b0b0 /* MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+ 34 0x1b0b0 /* MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+ 39 0x1b0b0 /* MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+ 44 0x1b0b0 /* MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+ 56 0x1b0b0 /* MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+ 702 0x1b0b0 /* MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK */
+ 74 0x1b0b0 /* MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC */
+ 52 0x1b0b0 /* MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+ 61 0x1b0b0 /* MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+ 66 0x1b0b0 /* MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+ 70 0x1b0b0 /* MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+ 48 0x1b0b0 /* MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+ >;
+ };
+ };
+
+ gpmi-nand {
+ pinctrl_gpmi_nand_1: gpmi-nand-1 {
+ fsl,pins = <
+ 1328 0xb0b1 /* MX6DL_PAD_NANDF_CLE__RAWNAND_CLE */
+ 1336 0xb0b1 /* MX6DL_PAD_NANDF_ALE__RAWNAND_ALE */
+ 1344 0xb0b1 /* MX6DL_PAD_NANDF_WP_B__RAWNAND_RESETN */
+ 1352 0xb000 /* MX6DL_PAD_NANDF_RB0__RAWNAND_READY0 */
+ 1360 0xb0b1 /* MX6DL_PAD_NANDF_CS0__RAWNAND_CE0N */
+ 1365 0xb0b1 /* MX6DL_PAD_NANDF_CS1__RAWNAND_CE1N */
+ 1371 0xb0b1 /* MX6DL_PAD_NANDF_CS2__RAWNAND_CE2N */
+ 1378 0xb0b1 /* MX6DL_PAD_NANDF_CS3__RAWNAND_CE3N */
+ 1387 0xb0b1 /* MX6DL_PAD_SD4_CMD__RAWNAND_RDN */
+ 1393 0xb0b1 /* MX6DL_PAD_SD4_CLK__RAWNAND_WRN */
+ 1397 0xb0b1 /* MX6DL_PAD_NANDF_D0__RAWNAND_D0 */
+ 1405 0xb0b1 /* MX6DL_PAD_NANDF_D1__RAWNAND_D1 */
+ 1413 0xb0b1 /* MX6DL_PAD_NANDF_D2__RAWNAND_D2 */
+ 1421 0xb0b1 /* MX6DL_PAD_NANDF_D3__RAWNAND_D3 */
+ 1429 0xb0b1 /* MX6DL_PAD_NANDF_D4__RAWNAND_D4 */
+ 1437 0xb0b1 /* MX6DL_PAD_NANDF_D5__RAWNAND_D5 */
+ 1445 0xb0b1 /* MX6DL_PAD_NANDF_D6__RAWNAND_D6 */
+ 1453 0xb0b1 /* MX6DL_PAD_NANDF_D7__RAWNAND_D7 */
+ 1463 0x00b1 /* MX6DL_PAD_SD4_DAT0__RAWNAND_DQS */
+ >;
+ };
+ };
+
+ i2c1 {
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ 137 0x4001b8b1 /* MX6DL_PAD_EIM_D21__I2C1_SCL */
+ 196 0x4001b8b1 /* MX6DL_PAD_EIM_D28__I2C1_SDA */
+ >;
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1_1: uart1grp-1 {
+ fsl,pins = <
+ 1140 0x1b0b1 /* MX6DL_PAD_CSI0_DAT10__UART1_TXD */
+ 1148 0x1b0b1 /* MX6DL_PAD_CSI0_DAT11__UART1_RXD */
+ >;
+ };
+ pinctrl_uart1_2: uart1-grp-2 {
+ fsl,pins = <
+ 120 0x1b0b1 /* MX6DL_PAD_EIM_D19__UART1_CTS */
+ 128 0x1b0b1 /* MX6DL_PAD_EIM_D20__UART1_RTS */
+ >;
+ };
+
+ pinctrl_uart1_3: uart1grp-3 {
+ fsl,pins = <
+ 1242 0x1b0b1 /* MX6DL_PAD_SD3_DAT7__UART1_TXD */
+ 1250 0x1b0b1 /* MX6DL_PAD_SD3_DAT6__UART1_RXD */
+ >;
+ };
+ pinctrl_uart1_4: uart1-grp-4 {
+ fsl,pins = <
+ 1290 0x1b0b1 /* MX6DL_PAD_SD3_DAT0__UART1_CTS */
+ 1298 0x1b0b1 /* MX6DL_PAD_SD3_DAT1__UART1_RTS */
+ >;
+ };
+ };
+
+ uart2 {
+ pinctrl_uart2_1: uart2grp-1 {
+ fsl,pins = <
+ 183 0x1b0b1 /* MX6DL_PAD_EIM_D26__UART2_TXD */
+ 191 0x1b0b1 /* MX6DL_PAD_EIM_D27__UART2_RXD */
+ >;
+ };
+ pinctrl_uart2_2: uart2grp-2 {
+ fsl,pins = <
+ 199 0x1b0b1 /* MX6DL_PAD_EIM_D28__UART2_CTS */
+ 206 0x1b0b1 /* MX6DL_PAD_EIM_D29__UART2_RTS */
+ >;
+ };
+
+ pinctrl_uart2_3: uart2grp-3 {
+ fsl,pins = <
+ 1258 0x1b0b1 /* MX6DL_PAD_SD3_DAT5__UART2_TXD */
+ 1266 0x1b0b1 /* MX6DL_PAD_SD3_DAT6__UART2_RXD */
+ >;
+ };
+ pinctrl_uart2_4: uart2grp-4 {
+ fsl,pins = <
+ 1274 0x1b0b1 /* MX6DL_PAD_SD3_CMD__UART2_CTS */
+ 1282 0x1b0b1 /* MX6DL_PAD_SD3_CLK__UART2_RTS */
+ >;
+ };
+
+ pinctrl_uart2_5: uart2grp-5 {
+ fsl,pins = <
+ 1518 0x1b0b1 /* MX6DL_PAD_SD4_DAT7__UART2_TXD */
+ 1494 0x1b0b1 /* MX6DL_PAD_SD4_DAT4__UART2_RXD */
+ >;
+ };
+ pinctrl_uart2_6: uart2grp-6 {
+ fsl,pins = <
+ 1510 0x1b0b1 /* MX6DL_PAD_SD4_DAT6__UART2_CTS */
+ 1502 0x1b0b1 /* MX6DL_PAD_SD4_DAT5__UART2_RTS */
+ >;
+ };
+
+ pinctrl_uart2_7: uart2grp-7 {
+ fsl,pins = <
+ 1019 0x1b0b1 /* MX6DL_PAD_GPIO_7__UART2_TXD */
+ 1027 0x1b0b1 /* MX6DL_PAD_GPIO_8__UART2_RXD */
+ >;
+ };
+ };
+
+ uart3 {
+ pinctrl_uart3_1: uart3grp-1 {
+ fsl,pins = <
+ 165 0x1b0b1 /* MX6DL_PAD_EIM_D24__UART3_TXD */
+ 173 0x1b0b1 /* MX6DL_PAD_EIM_D25__UART3_RXD */
+ >;
+ };
+ pinctrl_uart3_2: uart3grp-2 {
+ fsl,pins = <
+ 149 0x1b0b1 /* MX6DL_PAD_EIM_D23__UART3_CTS */
+ 157 0x1b0b1 /* MX6DL_PAD_EIM_EB3__UART3_RTS */
+ >;
+ };
+
+ pinctrl_uart3_3: uart3grp-3 {
+ fsl,pins = <
+ 1388 0x1b0b1 /* MX6DL_PAD_SD4_CMD__UART3_TXD */
+ 1394 0x1b0b1 /* MX6DL_PAD_SD4_CLK__UART3_RXD */
+ >;
+ };
+ pinctrl_uart3_4: uart3grp-4 {
+ fsl,pins = <
+ 1313 0x1b0b1 /* MX6DL_PAD_SD3_DAT3__UART3_CTS */
+ 1321 0x1b0b1 /* MX6DL_PAD_SD3_RST__UART3_RTS */
+ >;
+ };
+
+ pinctrl_uart3_5: uart3grp-5 {
+ fsl,pins = <
+ 214 0x1b0b1 /* MX6DL_PAD_EIM_D30__UART3_CTS */
+ 222 0x1b0b1 /* MX6DL_PAD_EIM_D31__UART3_RTS */
+ >;
+ };
+ };
+
+ uart4 {
+ pinctrl_uart4_1: uart4grp-1 {
+ fsl,pins = <
+ 877 0x1b0b1 /* MX6DL_PAD_KEY_COL0__UART4_TXD */
+ 885 0x1b0b1 /* MX6DL_PAD_KEY_ROW0__UART4_RXD */
+ >;
+ };
+ };
+
+ usbotg {
+ pinctrl_usbotg_1: usbotggrp-1 {
+ fsl,pins = <
+ 1592 0x17059 /* MX6DL_PAD_GPIO_1__ANATOP_USBOTG_ID */
+ >;
+ };
+ };
+
+ usdhc1 {
+ pinctrl_usdhc1_1: usdhc1grp-1 {
+ fsl,pins = <
+ 1548 0x17059 /* MX6DL_PAD_SD1_CMD__USDHC1_CMD */
+ 1562 0x10059 /* MX6DL_PAD_SD1_CLK__USDHC1_CLK */
+ 1532 0x17059 /* MX6DL_PAD_SD1_DAT0__USDHC1_DAT0 */
+ 1524 0x17059 /* MX6DL_PAD_SD1_DAT1__USDHC1_DAT1 */
+ 1554 0x17059 /* MX6DL_PAD_SD1_DAT2__USDHC1_DAT2 */
+ 1540 0x17059 /* MX6DL_PAD_SD1_DAT3__USDHC1_DAT3 */
+ 1398 0x17059 /* MX6DL_PAD_NANDF_D0__USDHC1_DAT4 */
+ 1406 0x17059 /* MX6DL_PAD_NANDF_D1__USDHC1_DAT5 */
+ 1414 0x17059 /* MX6DL_PAD_NANDF_D2__USDHC1_DAT6 */
+ 1422 0x17059 /* MX6DL_PAD_NANDF_D3__USDHC1_DAT7 */
+ >;
+ };
+
+ pinctrl_usdhc1_2: usdhc1grp-2 {
+ fsl,pins = <
+ 1548 0x17059 /* MX6DL_PAD_SD1_CMD__USDHC1_CMD */
+ 1562 0x10059 /* MX6DL_PAD_SD1_CLK__USDHC1_CLK */
+ 1532 0x17059 /* MX6DL_PAD_SD1_DAT0__USDHC1_DAT0 */
+ 1524 0x17059 /* MX6DL_PAD_SD1_DAT1__USDHC1_DAT1 */
+ 1554 0x17059 /* MX6DL_PAD_SD1_DAT2__USDHC1_DAT2 */
+ 1540 0x17059 /* MX6DL_PAD_SD1_DAT3__USDHC1_DAT3 */
+ >;
+ };
+ };
+
+ usdhc2 {
+ pinctrl_usdhc2_1: usdhc2grp-1 {
+ fsl,pins = <
+ 1577 0x17059 /* MX6DL_PAD_SD2_CMD__USDHC2_CMD */
+ 1569 0x10059 /* MX6DL_PAD_SD2_CLK__USDHC2_CLK */
+ 16 0x17059 /* MX6DL_PAD_SD2_DAT0__USDHC2_DAT0 */
+ 0 0x17059 /* MX6DL_PAD_SD2_DAT1__USDHC2_DAT1 */
+ 8 0x17059 /* MX6DL_PAD_SD2_DAT2__USDHC2_DAT2 */
+ 1583 0x17059 /* MX6DL_PAD_SD2_DAT3__USDHC2_DAT3 */
+ 1430 0x17059 /* MX6DL_PAD_NANDF_D4__USDHC2_DAT4 */
+ 1438 0x17059 /* MX6DL_PAD_NANDF_D5__USDHC2_DAT5 */
+ 1446 0x17059 /* MX6DL_PAD_NANDF_D6__USDHC2_DAT6 */
+ 1454 0x17059 /* MX6DL_PAD_NANDF_D7__USDHC2_DAT7 */
+ >;
+ };
+
+ pinctrl_usdhc2_2: usdhc2grp-2 {
+ fsl,pins = <
+ 1577 0x17059 /* MX6DL_PAD_SD2_CMD__USDHC2_CMD */
+ 1569 0x10059 /* MX6DL_PAD_SD2_CLK__USDHC2_CLK */
+ 16 0x17059 /* MX6DL_PAD_SD2_DAT0__USDHC2_DAT0 */
+ 0 0x17059 /* MX6DL_PAD_SD2_DAT1__USDHC2_DAT1 */
+ 8 0x17059 /* MX6DL_PAD_SD2_DAT2__USDHC2_DAT2 */
+ 1583 0x17059 /* MX6DL_PAD_SD2_DAT3__USDHC2_DAT3 */
+ >;
+ };
+ };
+
+ usdhc3 {
+ pinctrl_usdhc3_1: usdhc3grp-1 {
+ fsl,pins = <
+ 1273 0x17059 /* MX6DL_PAD_SD3_CMD__USDHC3_CMD */
+ 1281 0x10059 /* MX6DL_PAD_SD3_CLK__USDHC3_CLK */
+ 1289 0x17059 /* MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 */
+ 1297 0x17059 /* MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 */
+ 1305 0x17059 /* MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 */
+ 1312 0x17059 /* MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 */
+ 1265 0x17059 /* MX6DL_PAD_SD3_DAT4__USDHC3_DAT4 */
+ 1257 0x17059 /* MX6DL_PAD_SD3_DAT5__USDHC3_DAT5 */
+ 1249 0x17059 /* MX6DL_PAD_SD3_DAT6__USDHC3_DAT6 */
+ 1241 0x17059 /* MX6DL_PAD_SD3_DAT7__USDHC3_DAT7 */
+ >;
+ };
+
+ pinctrl_usdhc3_2: usdhc3grp-2 {
+ fsl,pins = <
+ 1273 0x17059 /* MX6DL_PAD_SD3_CMD__USDHC3_CMD */
+ 1281 0x10059 /* MX6DL_PAD_SD3_CLK__USDHC3_CLK */
+ 1289 0x17059 /* MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 */
+ 1297 0x17059 /* MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 */
+ 1305 0x17059 /* MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 */
+ 1312 0x17059 /* MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 */
+ >;
+ };
+ };
+
+ usdhc4 {
+ pinctrl_usdhc4_1: usdhc4grp-1 {
+ fsl,pins = <
+ 1386 0x17059 /* MX6DL_PAD_SD4_CMD__USDHC4_CMD */
+ 1392 0x10059 /* MX6DL_PAD_SD4_CLK__USDHC4_CLK */
+ 1462 0x17059 /* MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 */
+ 1470 0x17059 /* MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 */
+ 1478 0x17059 /* MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 */
+ 1486 0x17059 /* MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 */
+ 1493 0x17059 /* MX6DL_PAD_SD4_DAT4__USDHC4_DAT4 */
+ 1501 0x17059 /* MX6DL_PAD_SD4_DAT5__USDHC4_DAT5 */
+ 1509 0x17059 /* MX6DL_PAD_SD4_DAT6__USDHC4_DAT6 */
+ 1517 0x17059 /* MX6DL_PAD_SD4_DAT7__USDHC4_DAT7 */
+ >;
+ };
+
+ pinctrl_usdhc4_2: usdhc4grp-2 {
+ fsl,pins = <
+ 1386 0x17059 /* MX6DL_PAD_SD4_CMD__USDHC4_CMD */
+ 1392 0x10059 /* MX6DL_PAD_SD4_CLK__USDHC4_CLK */
+ 1462 0x17059 /* MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 */
+ 1470 0x17059 /* MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 */
+ 1478 0x17059 /* MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 */
+ 1486 0x17059 /* MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 */
+ >;
+ };
+ };
+ };
+ };
+
+ ipu2: ipu@02800000 {
+ #crtc-cells = <1>;
+ compatible = "fsl,iMX6DL-ipu";
+ reg = <0x02800000 0x400000>;
+ interrupts = <0 8 0x4 0 7 0x4>;
+ clocks = <&clks 133>, <&clks 134>, <&clks 137>;
+ clock-names = "bus", "di0", "di1";
+ };
+ };
+};
/ {
cpus {
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
#define GPTCR_CLKSOURCE_IPG (1 << 6) /* Clock source */
#define GPTCR_CLKSOURCE_CKIH (2 << 6)
#define GPTCR_CLKSOURCE_32kHz (4 << 6)
-#ifdef CONFIG_MX6
-#define GPTCR_CLKSOURCE_OSC_DIV_8 (5 << 6)
+#if defined(CONFIG_MX6Q)
+#define GPTCR_CLKSOURCE_OSCDIV8 (5 << 6)
#define GPTCR_CLKSOURCE_OSC (7 << 6)
+#elif defined(CONFIG_MX6DL)
+#define GPTCR_M24EN (1 << 10)
+#define GPTCR_CLKSOURCE_OSC ((5 << 6) | GPTCR_M24EN)
#else
#define GPTCR_CLKSOURCE_OSC (5 << 6)
#endif
int timer_init(void)
{
int i;
- ulong val;
/* setup GP Timer 1 */
__raw_writel(GPTCR_SWR, &cur_gpt->control);
i &= ~GPTCR_CLKSOURCE_MASK;
__raw_writel(i | GPT_CLKSOURCE | GPTCR_TEN, &cur_gpt->control);
- val = __raw_readl(&cur_gpt->counter);
- gd->arch.lastinc = val;
+ gd->arch.lastinc = __raw_readl(&cur_gpt->counter);
gd->arch.tbu = 0;
gd->arch.tbl = TIMER_START;
gd->arch.timer_rate_hz = GPT_CLK;
u32 cs1cdr;
u32 cs2cdr;
u32 cdcdr; /* 0x0030 */
- u32 chscdr;
+ u32 chsccdr;
u32 cscdr2;
u32 cscdr3;
u32 cscdr4; /* 0x0040 */
+++ /dev/null
-/*
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- * <armlinux@phytec.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_IOMUX_V3_H__
-#define __MACH_IOMUX_V3_H__
-
-#include <linux/compiler.h>
-
-/*
- * build IOMUX_PAD structure
- *
- * This iomux scheme is based around pads, which are the physical balls
- * on the processor.
- *
- * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
- * things like driving strength and pullup/pulldown.
- * - Each pad can have but not necessarily does have an output routing register
- * (IOMUXC_SW_MUX_CTL_PAD_x).
- * - Each pad can have but not necessarily does have an input routing register
- * (IOMUXC_x_SELECT_INPUT)
- *
- * The three register sets do not have a fixed offset to each other,
- * hence we order this table by pad control registers (which all pads
- * have) and put the optional i/o routing registers into additional
- * fields.
- *
- * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named
- * GPIO_<unit>_<num>
- *
- * IOMUX/PAD Bit field definitions
- *
- * MUX_CTRL_OFS: 0..11 (12)
- * PAD_CTRL_OFS: 12..23 (12)
- * SEL_INPUT_OFS: 24..35 (12)
- * MUX_MODE + SION: 36..40 (5)
- * PAD_CTRL + NO_PAD_CTRL: 41..57 (17)
- * SEL_INP: 58..61 (4)
- * reserved: 63 (1)
-*/
-
-typedef u64 iomux_v3_cfg_t;
-
-#define MUX_CTRL_OFS_SHIFT 0
-#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
-#define MUX_PAD_CTRL_OFS_SHIFT 12
-#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT)
-#define MUX_SEL_INPUT_OFS_SHIFT 24
-#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT)
-
-#define MUX_MODE_SHIFT 36
-#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
-#define MUX_PAD_CTRL_SHIFT 41
-#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT)
-#define MUX_SEL_INPUT_SHIFT 58
-#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
-
-#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
-
-#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \
- _sel_input, _pad_ctrl) \
- (((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
- ((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) | \
- ((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
- ((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
- ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
- ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT))
-
-#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad))
-/*
- * Use to set PAD control
- */
-
-#define NO_PAD_CTRL (1 << 16)
-#define PAD_CTL_DVS (1 << 13)
-#define PAD_CTL_HYS (1 << 8)
-
-#define PAD_CTL_PKE (1 << 7)
-#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
-#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
-
-#define PAD_CTL_ODE (1 << 3)
-
-#define PAD_CTL_DSE_LOW (0 << 1)
-#define PAD_CTL_DSE_MED (1 << 1)
-#define PAD_CTL_DSE_HIGH (2 << 1)
-#define PAD_CTL_DSE_MAX (3 << 1)
-
-#define PAD_CTL_SRE_FAST (1 << 0)
-#define PAD_CTL_SRE_SLOW (0 << 0)
-
-#define IOMUX_CONFIG_SION (0x1 << 4)
-
-/*
- * sets up a single pad in the iomuxer
- */
-int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
-
-/*
- * sets up mutliple pads
- * convenient way to call the above function with tables
- */
-int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list, unsigned count);
-
-#endif /* __MACH_IOMUX_V3_H__*/
-
u32 cs1cdr;
u32 cs2cdr;
u32 cdcdr; /* 0x0030 */
- u32 chscdr;
+ u32 chsccdr;
u32 cscdr2;
u32 cscdr3;
u32 cscdr4; /* 0x0040 */
*
*/
-#ifndef __MACH_IOMUX_MX6Q_H__
-#define __MACH_IOMUX_MX6Q_H__
-
-#include <asm/arch/iomux-v3.h>
+#ifndef __ASM_ARCH_IOMUX_MX6_H__
+#define __ASM_ARCH_IOMUX_MX6_H__
+
+#include <asm/imx-common/iomux-v3.h>
+#ifdef CONFIG_MX6Q
+#include "iomux-mx6q.h"
+#elif defined(CONFIG_MX6DL)
+#include "iomux-mx6dl.h"
+#elif defined(CONFIG_MX6SL)
+#include "iomux-mx6sl.h"
+#else
+#error Unsupported i.MX6 variant
+#endif
/*
* Use to set PAD control
*/
-#define MX6_PAD_CTL_HYS (1 << 16)
-
-#define MX6_PAD_CTL_PUS_100K_DOWN (MX6_PAD_CTL_PULL | (0 << 14))
-#define MX6_PAD_CTL_PUS_47K_UP (MX6_PAD_CTL_PULL | (1 << 14))
-#define MX6_PAD_CTL_PUS_100K_UP (MX6_PAD_CTL_PULL | (2 << 14))
-#define MX6_PAD_CTL_PUS_22K_UP (MX6_PAD_CTL_PULL | (3 << 14))
-
-#define MX6_PAD_CTL_PULL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE)
-#define MX6_PAD_CTL_PUE (1 << 13)
-#define MX6_PAD_CTL_PKE (1 << 12)
-#define MX6_PAD_CTL_ODE (1 << 11)
-
-#define MX6_PAD_CTL_SPEED_LOW (1 << 6)
-#define MX6_PAD_CTL_SPEED_MED (2 << 6)
-#define MX6_PAD_CTL_SPEED_HIGH (3 << 6)
-
-#define MX6_PAD_CTL_DSE_DISABLE (0 << 3)
-#define MX6_PAD_CTL_DSE_240ohm (1 << 3)
-#define MX6_PAD_CTL_DSE_120ohm (2 << 3)
-#define MX6_PAD_CTL_DSE_80ohm (3 << 3)
-#define MX6_PAD_CTL_DSE_60ohm (4 << 3)
-#define MX6_PAD_CTL_DSE_48ohm (5 << 3)
-#define MX6_PAD_CTL_DSE_40ohm (6 << 3)
-#define MX6_PAD_CTL_DSE_34ohm (7 << 3)
-
-#define MX6_PAD_CTL_SRE_FAST (1 << 0)
-#define MX6_PAD_CTL_SRE_SLOW (0 << 0)
-
-#define MX6Q_UART_PAD_CTRL (MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
- MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS)
-
-#define MX6Q_ECSPI_PAD_CTRL (MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_SPEED_MED | \
- MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS)
-
-#define MX6Q_USDHC_PAD_CTRL (MX6_PAD_CTL_PUS_47K_UP | MX6_PAD_CTL_SPEED_MED | \
- MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS)
-
-#define MX6Q_ENET_PAD_CTRL (MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
- MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS)
-
-#define MX6Q_I2C_PAD_CTRL (MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
- MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS | \
- MX6_PAD_CTL_ODE | MX6_PAD_CTL_SRE_FAST)
-
-#define MX6Q_PWM_PAD_CTRL (MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
- MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS | \
- MX6_PAD_CTL_SRE_FAST)
-
-#define MX6Q_HIGH_DRV MX6_PAD_CTL_DSE_120ohm
-
-#define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \
- IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \
- IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0)
-#define _MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \
- IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \
- IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0)
-#define _MX6Q_PAD_SD2_DAT1__KPP_COL_7 \
- IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0)
-#define _MX6Q_PAD_SD2_DAT1__GPIO_1_14 \
- IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT1__CCM_WAIT \
- IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \
- IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \
- IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \
- IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0)
-#define _MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \
- IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \
- IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0)
-#define _MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \
- IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0)
-#define _MX6Q_PAD_SD2_DAT2__GPIO_1_13 \
- IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT2__CCM_STOP \
- IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \
- IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \
- IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \
- IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0)
-#define _MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \
- IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0)
-#define _MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \
- IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0)
-#define _MX6Q_PAD_SD2_DAT0__GPIO_1_15 \
- IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \
- IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \
- IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \
- IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \
- IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \
- IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0)
-#define _MX6Q_PAD_RGMII_TXC__GPIO_6_19 \
- IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \
- IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \
- IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \
- IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \
- IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD0__GPIO_6_20 \
- IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \
- IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \
- IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \
- IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD1__GPIO_6_21 \
- IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \
- IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \
- IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \
- IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \
- IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD2__GPIO_6_22 \
- IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \
- IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \
- IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \
- IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \
- IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD3__GPIO_6_23 \
- IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \
- IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \
- IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \
- IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0)
-#define _MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \
- IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \
- IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \
- IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \
- IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0)
-#define _MX6Q_PAD_RGMII_RD0__GPIO_6_25 \
- IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \
- IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \
- IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \
- IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \
- IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \
- IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \
- IOMUX_PAD(0x0388, 0x0074, 0x17, 0x083C, 0, 0)
-
-#define _MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \
- IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \
- IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0)
-#define _MX6Q_PAD_RGMII_RD1__GPIO_6_27 \
- IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \
- IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD1__SJC_FAIL \
- IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \
- IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \
- IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0)
-#define _MX6Q_PAD_RGMII_RD2__GPIO_6_28 \
- IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \
- IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \
- IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \
- IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0)
-#define _MX6Q_PAD_RGMII_RD3__GPIO_6_29 \
- IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \
- IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \
- IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \
- IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0)
-#define _MX6Q_PAD_RGMII_RXC__GPIO_6_30 \
- IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \
- IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \
- IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A25__ECSPI4_SS1 \
- IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A25__ECSPI2_RDY \
- IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \
- IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \
- IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A25__GPIO_5_2 \
- IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \
- IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0)
-#define _MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \
- IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \
- IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \
- IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0)
-#define _MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \
- IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0)
-#define _MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \
- IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0)
-#define _MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \
- IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0)
-#define _MX6Q_PAD_EIM_EB2__GPIO_2_30 \
- IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB2__I2C2_SCL \
- IOMUX_PAD(0x03A0, 0x008C, 6 | IOMUX_CONFIG_SION, 0x08A0, 0, 0)
-#define _MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \
- IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \
- IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D16__ECSPI1_SCLK \
- IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0)
-#define _MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \
- IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \
- IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0)
-#define _MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \
- IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0)
-#define _MX6Q_PAD_EIM_D16__GPIO_3_16 \
- IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D16__I2C2_SDA \
- IOMUX_PAD(0x03A4, 0x0090, 6 | IOMUX_CONFIG_SION, 0x08A4, 0, 0)
-
-#define _MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \
- IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D17__ECSPI1_MISO \
- IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0)
-#define _MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \
- IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \
- IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0)
-#define _MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \
- IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D17__GPIO_3_17 \
- IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D17__I2C3_SCL \
- IOMUX_PAD(0x03A8, 0x0094, 6 | IOMUX_CONFIG_SION, 0x08A8, 0, 0)
-#define _MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \
- IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \
- IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D18__ECSPI1_MOSI \
- IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0)
-#define _MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \
- IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \
- IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0)
-#define _MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \
- IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D18__GPIO_3_18 \
- IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D18__I2C3_SDA \
- IOMUX_PAD(0x03AC, 0x0098, 6 | IOMUX_CONFIG_SION, 0x08AC, 0, 0)
-#define _MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \
- IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \
- IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D19__ECSPI1_SS1 \
- IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0)
-#define _MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \
- IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \
- IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0)
-#define _MX6Q_PAD_EIM_D19__UART1_CTS \
- IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D19__UART1_RTS \
- IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0)
-#define _MX6Q_PAD_EIM_D19__GPIO_3_19 \
- IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D19__EPIT1_EPITO \
- IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \
- IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \
- IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D20__ECSPI4_SS0 \
- IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0)
-#define _MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \
- IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \
- IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0)
-#define _MX6Q_PAD_EIM_D20__UART1_CTS \
- IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D20__UART1_RTS \
- IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0)
-#define _MX6Q_PAD_EIM_D20__GPIO_3_20 \
- IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D20__EPIT2_EPITO \
- IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \
- IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D21__ECSPI4_SCLK \
- IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \
- IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \
- IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0)
-#define _MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \
- IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0)
-#define _MX6Q_PAD_EIM_D21__GPIO_3_21 \
- IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D21__I2C1_SCL \
- IOMUX_PAD(0x03B8, 0x00A4, 6 | IOMUX_CONFIG_SION, 0x0898, 0, 0)
-#define _MX6Q_PAD_EIM_D21__SPDIF_IN1 \
- IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0)
-
-#define _MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \
- IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D22__ECSPI4_MISO \
- IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \
- IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \
- IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0)
-#define _MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \
- IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D22__GPIO_3_22 \
- IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D22__SPDIF_OUT1 \
- IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \
- IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \
- IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \
- IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D23__UART3_CTS \
- IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D23__UART3_RTS \
- IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0)
-#define _MX6Q_PAD_EIM_D23__UART1_DCD \
- IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \
- IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0)
-#define _MX6Q_PAD_EIM_D23__GPIO_3_23 \
- IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \
- IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \
- IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \
- IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB3__ECSPI4_RDY \
- IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB3__UART3_CTS \
- IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB3__UART3_RTS \
- IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0)
-#define _MX6Q_PAD_EIM_EB3__UART1_RI \
- IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \
- IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0)
-#define _MX6Q_PAD_EIM_EB3__GPIO_2_31 \
- IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \
- IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \
- IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \
- IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D24__ECSPI4_SS2 \
- IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D24__UART3_TXD \
- IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D24__UART3_RXD \
- IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0)
-#define _MX6Q_PAD_EIM_D24__ECSPI1_SS2 \
- IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0)
-#define _MX6Q_PAD_EIM_D24__ECSPI2_SS2 \
- IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D24__GPIO_3_24 \
- IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \
- IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0)
-#define _MX6Q_PAD_EIM_D24__UART1_DTR \
- IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \
- IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D25__ECSPI4_SS3 \
- IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D25__UART3_TXD \
- IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D25__UART3_RXD \
- IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0)
-#define _MX6Q_PAD_EIM_D25__ECSPI1_SS3 \
- IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0)
-#define _MX6Q_PAD_EIM_D25__ECSPI2_SS3 \
- IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D25__GPIO_3_25 \
- IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \
- IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0)
-#define _MX6Q_PAD_EIM_D25__UART1_DSR \
- IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \
- IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \
- IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \
- IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \
- IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0)
-#define _MX6Q_PAD_EIM_D26__UART2_TXD \
- IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D26__UART2_RXD \
- IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0)
-#define _MX6Q_PAD_EIM_D26__GPIO_3_26 \
- IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D26__IPU1_SISG_2 \
- IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \
- IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \
- IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \
- IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \
- IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \
- IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0)
-#define _MX6Q_PAD_EIM_D27__UART2_TXD \
- IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D27__UART2_RXD \
- IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0)
-#define _MX6Q_PAD_EIM_D27__GPIO_3_27 \
- IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D27__IPU1_SISG_3 \
- IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \
- IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \
- IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D28__I2C1_SDA \
- IOMUX_PAD(0x03D8, 0x00C4, 1 | IOMUX_CONFIG_SION, 0x089C, 0, 0)
-#define _MX6Q_PAD_EIM_D28__ECSPI4_MOSI \
- IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \
- IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0)
-#define _MX6Q_PAD_EIM_D28__UART2_CTS \
- IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D28__UART2_RTS \
- IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0)
-#define _MX6Q_PAD_EIM_D28__GPIO_3_28 \
- IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \
- IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \
- IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \
- IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \
- IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D29__ECSPI4_SS0 \
- IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0)
-#define _MX6Q_PAD_EIM_D29__UART2_CTS \
- IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D29__UART2_RTS \
- IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0)
-#define _MX6Q_PAD_EIM_D29__GPIO_3_29 \
- IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \
- IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0)
-#define _MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \
- IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \
- IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \
- IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \
- IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \
- IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D30__UART3_CTS \
- IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 2, 0)
-#define _MX6Q_PAD_EIM_D30__UART3_RTS \
- IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0)
-#define _MX6Q_PAD_EIM_D30__GPIO_3_30 \
- IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \
- IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0)
-#define _MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \
- IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \
- IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \
- IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \
- IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \
- IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D31__UART3_CTS \
- IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D31__UART3_RTS \
- IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0)
-#define _MX6Q_PAD_EIM_D31__GPIO_3_31 \
- IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \
- IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \
- IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \
- IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \
- IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \
- IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0)
-#define _MX6Q_PAD_EIM_A24__IPU2_SISG_2 \
- IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A24__IPU1_SISG_2 \
- IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A24__GPIO_5_4 \
- IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \
- IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \
- IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \
- IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \
- IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \
- IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0)
-#define _MX6Q_PAD_EIM_A23__IPU2_SISG_3 \
- IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A23__IPU1_SISG_3 \
- IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A23__GPIO_6_6 \
- IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \
- IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \
- IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \
- IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \
- IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \
- IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0)
-#define _MX6Q_PAD_EIM_A22__GPIO_2_16 \
- IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \
- IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \
- IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \
- IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \
- IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \
- IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0)
-#define _MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \
- IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A21__GPIO_2_17 \
- IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \
- IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \
- IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \
- IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \
- IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \
- IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0)
-#define _MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \
- IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A20__GPIO_2_18 \
- IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \
- IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \
- IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \
- IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \
- IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \
- IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0)
-#define _MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \
- IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A19__GPIO_2_19 \
- IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \
- IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \
- IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \
- IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \
- IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \
- IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0)
-#define _MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \
- IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A18__GPIO_2_20 \
- IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \
- IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \
- IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \
- IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \
- IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \
- IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0)
-#define _MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \
- IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A17__GPIO_2_21 \
- IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \
- IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \
- IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \
- IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \
- IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \
- IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0)
-#define _MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \
- IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A16__GPIO_2_22 \
- IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \
- IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \
- IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \
- IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \
- IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \
- IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0)
-#define _MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \
- IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_CS0__GPIO_2_23 \
- IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \
- IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \
- IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \
- IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \
- IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0)
-#define _MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \
- IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_CS1__GPIO_2_24 \
- IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \
- IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \
- IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \
- IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_OE__ECSPI2_MISO \
- IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0)
-#define _MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \
- IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_OE__GPIO_2_25 \
- IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \
- IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \
- IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \
- IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_RW__ECSPI2_SS0 \
- IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0)
-#define _MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \
- IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_RW__GPIO_2_26 \
- IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \
- IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \
- IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \
- IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \
- IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \
- IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0)
-#define _MX6Q_PAD_EIM_LBA__GPIO_2_27 \
- IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \
- IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \
- IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \
- IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \
- IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \
- IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0)
-#define _MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \
- IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \
- IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0)
-#define _MX6Q_PAD_EIM_EB0__GPIO_2_28 \
- IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \
- IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \
- IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \
- IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \
- IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \
- IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0)
-#define _MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \
- IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB1__GPIO_2_29 \
- IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \
- IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \
- IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \
- IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \
- IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \
- IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \
- IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA0__GPIO_3_0 \
- IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \
- IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \
- IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \
- IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \
- IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \
- IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \
- IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \
- IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA1__GPIO_3_1 \
- IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \
- IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \
- IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \
- IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \
- IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \
- IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \
- IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \
- IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA2__GPIO_3_2 \
- IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \
- IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \
- IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \
- IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \
- IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \
- IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \
- IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \
- IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA3__GPIO_3_3 \
- IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \
- IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \
- IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \
- IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \
- IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \
- IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \
- IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \
- IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA4__GPIO_3_4 \
- IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \
- IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \
- IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \
- IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \
- IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \
- IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \
- IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \
- IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA5__GPIO_3_5 \
- IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \
- IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \
- IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \
- IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \
- IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \
- IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \
- IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \
- IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA6__GPIO_3_6 \
- IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \
- IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \
- IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \
- IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \
- IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \
- IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \
- IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA7__GPIO_3_7 \
- IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \
- IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \
- IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \
- IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \
- IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \
- IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \
- IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA8__GPIO_3_8 \
- IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \
- IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \
- IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \
- IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \
- IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \
- IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \
- IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA9__GPIO_3_9 \
- IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \
- IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \
- IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \
- IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \
- IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \
- IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0)
-#define _MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \
- IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA10__GPIO_3_10 \
- IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \
- IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \
- IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \
- IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \
- IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \
- IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0)
-#define _MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \
- IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \
- IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA11__GPIO_3_11 \
- IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \
- IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \
- IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \
- IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \
- IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \
- IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0)
-#define _MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \
- IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \
- IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA12__GPIO_3_12 \
- IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \
- IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \
- IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \
- IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \
- IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \
- IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0)
-#define _MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \
- IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \
- IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA13__GPIO_3_13 \
- IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \
- IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \
- IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \
- IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \
- IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \
- IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \
- IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \
- IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA14__GPIO_3_14 \
- IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \
- IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \
- IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \
- IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \
- IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \
- IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \
- IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA15__GPIO_3_15 \
- IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \
- IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \
- IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \
- IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \
- IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_WAIT__GPIO_5_0 \
- IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \
- IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \
- IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \
- IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \
- IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_BCLK__GPIO_6_31 \
- IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \
- IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \
- IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \
- IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \
- IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \
- IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \
- IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \
- IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \
- IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \
- IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \
- IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \
- IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \
- IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN15__GPIO_4_17 \
- IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \
- IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \
- IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \
- IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \
- IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \
- IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \
- IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN2__GPIO_4_18 \
- IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \
- IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \
- IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \
- IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \
- IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \
- IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \
- IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \
- IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN3__GPIO_4_19 \
- IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \
- IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \
- IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \
- IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \
- IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \
- IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN4__USDHC1_WP \
- IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0)
-#define _MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \
- IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN4__GPIO_4_20 \
- IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \
- IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \
- IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \
- IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \
- IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \
- IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \
- IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \
- IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \
- IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \
- IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \
- IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \
- IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \
- IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \
- IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \
- IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \
- IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \
- IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \
- IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \
- IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \
- IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \
- IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \
- IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \
- IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \
- IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \
- IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \
- IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \
- IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \
- IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \
- IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \
- IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \
- IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \
- IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \
- IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \
- IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \
- IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \
- IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \
- IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \
- IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \
- IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \
- IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \
- IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \
- IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \
- IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \
- IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \
- IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \
- IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \
- IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \
- IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \
- IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \
- IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \
- IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \
- IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \
- IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \
- IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \
- IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \
- IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \
- IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \
- IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \
- IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \
- IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \
- IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \
- IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \
- IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \
- IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \
- IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \
- IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \
- IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \
- IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \
- IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \
- IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \
- IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \
- IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \
- IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \
- IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \
- IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \
- IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \
- IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \
- IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \
- IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \
- IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \
- IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \
- IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \
- IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \
- IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \
- IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
- IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \
- IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \
- IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \
- IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \
- IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \
- IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \
- IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
- IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \
- IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \
- IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \
- IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \
- IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \
- IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
- IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \
- IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \
- IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \
- IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \
- IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \
- IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \
- IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
- IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \
- IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \
- IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \
- IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \
- IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \
- IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \
- IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
- IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \
- IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \
- IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \
- IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \
- IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \
- IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \
- IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \
- IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \
- IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \
- IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \
- IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \
- IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \
- IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \
- IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \
- IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \
- IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \
- IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \
- IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \
- IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \
- IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \
- IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \
- IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \
- IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \
- IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \
- IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \
- IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \
- IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \
- IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \
- IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \
- IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \
- IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \
- IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \
- IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \
- IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \
- IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \
- IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \
- IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \
- IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \
- IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \
- IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \
- IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \
- IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \
- IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \
- IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \
- IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \
- IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \
- IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \
- IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \
- IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \
- IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \
- IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \
- IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \
- IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \
- IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \
- IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \
- IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \
- IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \
- IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \
- IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \
- IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \
- IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \
- IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \
- IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \
- IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \
- IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \
- IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \
- IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \
- IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \
- IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \
- IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \
- IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0)
-#define _MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \
- IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \
- IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \
- IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \
- IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_MDIO__ENET_MDIO \
- IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0)
-#define _MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \
- IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0)
-#define _MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \
- IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \
- IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_MDIO__GPIO_1_22 \
- IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \
- IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \
- IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \
- IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0)
-#define _MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \
- IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \
- IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \
- IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \
- IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \
- IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \
- IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0)
-#define _MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \
- IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0)
-#define _MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \
- IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \
- IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RX_ER__PHY_TDI \
- IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \
- IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \
- IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0)
-#define _MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \
- IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0)
-#define _MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \
- IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0)
-#define _MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \
- IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_CRS_DV__PHY_TDO \
- IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \
- IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \
- IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0)
-#define _MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \
- IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0)
-#define _MX6Q_PAD_ENET_RXD1__ESAI1_FST \
- IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0)
-#define _MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \
- IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RXD1__GPIO_1_26 \
- IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RXD1__PHY_TCK \
- IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \
- IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \
- IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \
- IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0)
-#define _MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \
- IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0)
-#define _MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \
- IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RXD0__GPIO_1_27 \
- IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RXD0__PHY_TMS \
- IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \
- IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \
- IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \
- IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0)
-#define _MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \
- IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \
- IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \
- IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \
- IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0)
-#define _MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \
- IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \
- IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0)
-#define _MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \
- IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TXD1__GPIO_1_29 \
- IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \
- IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \
- IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \
- IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \
- IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0)
-#define _MX6Q_PAD_ENET_TXD0__GPIO_1_30 \
- IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \
- IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \
- IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_ENET_MDC__MLB_MLBDAT \
- IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0)
-#define _MX6Q_PAD_ENET_MDC__ENET_MDC \
- IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \
- IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0)
-#define _MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \
- IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_MDC__GPIO_1_31 \
- IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \
- IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \
- IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \
- IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \
- IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \
- IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \
- IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \
- IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \
- IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \
- IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \
- IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \
- IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \
- IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \
- IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \
- IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \
- IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \
- IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \
- IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \
- IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \
- IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \
- IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \
- IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \
- IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \
- IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \
- IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \
- IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \
- IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \
- IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \
- IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \
- IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \
- IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \
- IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \
- IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \
- IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \
- IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \
- IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \
- IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \
- IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \
- IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \
- IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \
- IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \
- IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \
- IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \
- IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \
- IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \
- IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \
- IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \
- IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \
- IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \
- IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \
- IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0)
-#define _MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \
- IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0)
-#define _MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \
- IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0)
-#define _MX6Q_PAD_KEY_COL0__KPP_COL_0 \
- IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL0__UART4_TXD \
- IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL0__UART4_RXD \
- IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0)
-#define _MX6Q_PAD_KEY_COL0__GPIO_4_6 \
- IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \
- IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \
- IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \
- IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0)
-#define _MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \
- IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \
- IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0)
-#define _MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \
- IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW0__UART4_TXD \
- IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW0__UART4_RXD \
- IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0)
-#define _MX6Q_PAD_KEY_ROW0__GPIO_4_7 \
- IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \
- IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \
- IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_COL1__ECSPI1_MISO \
- IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0)
-#define _MX6Q_PAD_KEY_COL1__ENET_MDIO \
- IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0)
-#define _MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \
- IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0)
-#define _MX6Q_PAD_KEY_COL1__KPP_COL_1 \
- IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL1__UART5_TXD \
- IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL1__UART5_RXD \
- IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0)
-#define _MX6Q_PAD_KEY_COL1__GPIO_4_8 \
- IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \
- IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \
- IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \
- IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0)
-#define _MX6Q_PAD_KEY_ROW1__ENET_COL \
- IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \
- IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0)
-#define _MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \
- IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW1__UART5_TXD \
- IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW1__UART5_RXD \
- IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0)
-#define _MX6Q_PAD_KEY_ROW1__GPIO_4_9 \
- IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \
- IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \
- IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \
- IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0)
-#define _MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \
- IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0)
-#define _MX6Q_PAD_KEY_COL2__CAN1_TXCAN \
- IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL2__KPP_COL_2 \
- IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL2__ENET_MDC \
- IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL2__GPIO_4_10 \
- IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \
- IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \
- IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \
- IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0)
-#define _MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \
- IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \
- IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0)
-#define _MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \
- IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \
- IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW2__GPIO_4_11 \
- IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \
- IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0)
-#define _MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \
- IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \
- IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0)
-#define _MX6Q_PAD_KEY_COL3__ENET_CRS \
- IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \
- IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0)
-#define _MX6Q_PAD_KEY_COL3__KPP_COL_3 \
- IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL3__I2C2_SCL \
- IOMUX_PAD(0x05E0, 0x0210, 4 | IOMUX_CONFIG_SION, 0x08A0, 1, 0)
-#define _MX6Q_PAD_KEY_COL3__GPIO_4_12 \
- IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL3__SPDIF_IN1 \
- IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0)
-#define _MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \
- IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \
- IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \
- IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0)
-#define _MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \
- IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0)
-#define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \
- IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW3__I2C2_SDA \
- IOMUX_PAD(0x05E4, 0x0214, 4 | IOMUX_CONFIG_SION, 0x08A4, 1, 0)
-#define _MX6Q_PAD_KEY_ROW3__GPIO_4_13 \
- IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \
- IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \
- IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_COL4__CAN2_TXCAN \
- IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \
- IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \
- IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0)
-#define _MX6Q_PAD_KEY_COL4__KPP_COL_4 \
- IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL4__UART5_CTS \
- IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL4__UART5_RTS \
- IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0)
-#define _MX6Q_PAD_KEY_COL4__GPIO_4_14 \
- IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \
- IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \
- IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \
- IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0)
-#define _MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \
- IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \
- IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \
- IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW4__UART5_CTS \
- IOMUX_PAD(0x05EC, 0x021C, 4, 0x0000, 1, 0)
-#define _MX6Q_PAD_KEY_ROW4__UART5_RTS \
- IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0)
-#define _MX6Q_PAD_KEY_ROW4__GPIO_4_15 \
- IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \
- IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \
- IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_0__CCM_CLKO \
- IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_0__KPP_COL_5 \
- IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0)
-#define _MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \
- IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0)
-#define _MX6Q_PAD_GPIO_0__EPIT1_EPITO \
- IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_0__GPIO_1_0 \
- IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \
- IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \
- IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_1__ESAI1_SCKR \
- IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0)
-#define _MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \
- IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_1__KPP_ROW_5 \
- IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0)
-#define _MX6Q_PAD_GPIO_1__PWM2_PWMO \
- IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_1__GPIO_1_1 \
- IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_1__USDHC1_CD \
- IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \
- IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_9__ESAI1_FSR \
- IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0)
-#define _MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \
- IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_9__KPP_COL_6 \
- IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0)
-#define _MX6Q_PAD_GPIO_9__CCM_REF_EN_B \
- IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_9__PWM1_PWMO \
- IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_9__GPIO_1_9 \
- IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_9__USDHC1_WP \
- IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0)
-#define _MX6Q_PAD_GPIO_9__SRC_EARLY_RST \
- IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_3__ESAI1_HCKR \
- IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0)
-#define _MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \
- IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_3__I2C3_SCL \
- IOMUX_PAD(0x05FC, 0x022C, 2 | IOMUX_CONFIG_SION, 0x08A8, 1, 0)
-#define _MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \
- IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_3__CCM_CLKO2 \
- IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_3__GPIO_1_3 \
- IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \
- IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0)
-#define _MX6Q_PAD_GPIO_3__MLB_MLBCLK \
- IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0)
-
-#define _MX6Q_PAD_GPIO_6__ESAI1_SCKT \
- IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0)
-#define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
- IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_6__I2C3_SDA \
- IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0)
-#define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \
- IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \
- IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_6__GPIO_1_6 \
- IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_6__USDHC2_LCTL \
- IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_6__MLB_MLBSIG \
- IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0)
-
-#define _MX6Q_PAD_GPIO_2__ESAI1_FST \
- IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0)
-#define _MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \
- IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_2__KPP_ROW_6 \
- IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0)
-#define _MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \
- IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \
- IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_2__GPIO_1_2 \
- IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_2__USDHC2_WP \
- IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_2__MLB_MLBDAT \
- IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0)
-
-#define _MX6Q_PAD_GPIO_4__ESAI1_HCKT \
- IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0)
-#define _MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \
- IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_4__KPP_COL_7 \
- IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0)
-#define _MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \
- IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \
- IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_4__GPIO_1_4 \
- IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_4__USDHC2_CD \
- IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \
- IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \
- IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0)
-#define _MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \
- IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_5__KPP_ROW_7 \
- IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0)
-#define _MX6Q_PAD_GPIO_5__CCM_CLKO \
- IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \
- IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_5__GPIO_1_5 \
- IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_5__I2C3_SCL \
- IOMUX_PAD(0x060C, 0x023C, 6 | IOMUX_CONFIG_SION, 0x08A8, 2, 0)
-#define _MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \
- IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \
- IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0)
-#define _MX6Q_PAD_GPIO_7__ECSPI5_RDY \
- IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_7__EPIT1_EPITO \
- IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_7__CAN1_TXCAN \
- IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_7__UART2_TXD \
- IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_7__UART2_RXD \
- IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0)
-#define _MX6Q_PAD_GPIO_7__GPIO_1_7 \
- IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_7__SPDIF_PLOCK \
- IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \
- IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \
- IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0)
-#define _MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \
- IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_8__EPIT2_EPITO \
- IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_8__CAN1_RXCAN \
- IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0)
-#define _MX6Q_PAD_GPIO_8__UART2_TXD \
- IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_8__UART2_RXD \
- IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0)
-#define _MX6Q_PAD_GPIO_8__GPIO_1_8 \
- IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_8__SPDIF_SRCLK \
- IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \
- IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \
- IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0)
-#define _MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \
- IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \
- IOMUX_PAD(0x0618, 0x0248, 0x12, 0x083C, 1, 0)
-#define _MX6Q_PAD_GPIO_16__USDHC1_LCTL \
- IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_16__SPDIF_IN1 \
- IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0)
-#define _MX6Q_PAD_GPIO_16__GPIO_7_11 \
- IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_16__I2C3_SDA \
- IOMUX_PAD(0x0618, 0x0248, 6 | IOMUX_CONFIG_SION, 0x08AC, 2, 0)
-#define _MX6Q_PAD_GPIO_16__SJC_DE_B \
- IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_17__ESAI1_TX0 \
- IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0)
-#define _MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \
- IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \
- IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0)
-#define _MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \
- IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0)
-#define _MX6Q_PAD_GPIO_17__SPDIF_OUT1 \
- IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_17__GPIO_7_12 \
- IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \
- IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_18__ESAI1_TX1 \
- IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0)
-#define _MX6Q_PAD_GPIO_18__ENET_RX_CLK \
- IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0)
-#define _MX6Q_PAD_GPIO_18__USDHC3_VSELECT \
- IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \
- IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0)
-#define _MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \
- IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0)
-#define _MX6Q_PAD_GPIO_18__GPIO_7_13 \
- IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \
- IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \
- IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_GPIO_19__KPP_COL_5 \
- IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0)
-#define _MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \
- IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_19__SPDIF_OUT1 \
- IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_19__CCM_CLKO \
- IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_19__ECSPI1_RDY \
- IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_19__GPIO_4_5 \
- IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_19__ENET_TX_ER \
- IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_GPIO_19__SRC_INT_BOOT \
- IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0)
+#define PAD_CTL_HYS __MUX_PAD_CTRL((1 << 16))
-#define _MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \
- IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \
- IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \
- IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \
- IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \
- IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \
- IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0)
+#define PAD_CTL_PUS_100K_DOWN __MUX_PAD_CTRL(PAD_CTL_PULL | (0 << 14))
+#define PAD_CTL_PUS_47K_UP __MUX_PAD_CTRL(PAD_CTL_PULL | (1 << 14))
+#define PAD_CTL_PUS_100K_UP __MUX_PAD_CTRL(PAD_CTL_PULL | (2 << 14))
+#define PAD_CTL_PUS_22K_UP __MUX_PAD_CTRL(PAD_CTL_PULL | (3 << 14))
-#define _MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \
- IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \
- IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_MCLK__CCM_CLKO \
- IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \
- IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \
- IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \
- IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \
- IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0)
+#define PAD_CTL_PULL __MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE)
+#define PAD_CTL_PUE __MUX_PAD_CTRL(1 << 13)
+#define PAD_CTL_PKE __MUX_PAD_CTRL(1 << 12)
+#define PAD_CTL_ODE __MUX_PAD_CTRL(1 << 11)
-#define _MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \
- IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \
- IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \
- IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \
- IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \
- IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \
- IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \
- IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0)
+#define PAD_CTL_SPEED_LOW __MUX_PAD_CTRL(1 << 6)
+#define PAD_CTL_SPEED_MED __MUX_PAD_CTRL(2 << 6)
+#define PAD_CTL_SPEED_HIGH __MUX_PAD_CTRL(3 << 6)
-#define _MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \
- IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \
- IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \
- IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \
- IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \
- IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \
- IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \
- IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0)
+#define PAD_CTL_DSE_DISABLE __MUX_PAD_CTRL(0 << 3)
+#define PAD_CTL_DSE_240ohm __MUX_PAD_CTRL(1 << 3)
+#define PAD_CTL_DSE_120ohm __MUX_PAD_CTRL(2 << 3)
+#define PAD_CTL_DSE_80ohm __MUX_PAD_CTRL(3 << 3)
+#define PAD_CTL_DSE_60ohm __MUX_PAD_CTRL(4 << 3)
+#define PAD_CTL_DSE_48ohm __MUX_PAD_CTRL(5 << 3)
+#define PAD_CTL_DSE_40ohm __MUX_PAD_CTRL(6 << 3)
+#define PAD_CTL_DSE_34ohm __MUX_PAD_CTRL(7 << 3)
-#define _MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \
- IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \
- IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \
- IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0)
-#define _MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \
- IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \
- IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \
- IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \
- IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \
- IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0)
+#define PAD_CTL_SRE_FAST __MUX_PAD_CTRL(1 << 0)
+#define PAD_CTL_SRE_SLOW __MUX_PAD_CTRL(0 << 0)
-#define _MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \
- IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \
- IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \
- IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0)
-#define _MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \
- IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0)
-#define _MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \
- IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \
- IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \
- IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \
- IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0)
+#define MX6_UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define _MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \
- IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \
- IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \
- IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0)
-#define _MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \
- IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0)
-#define _MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \
- IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \
- IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \
- IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \
- IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0)
+#define MX6_ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-#define _MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \
- IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \
- IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \
- IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0)
-#define _MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \
- IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \
- IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \
- IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \
- IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \
- IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0)
+#define MX6_USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define _MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \
- IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \
- IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \
- IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \
- IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT8__I2C1_SDA \
- IOMUX_PAD(0x0648, 0x0278, 4 | IOMUX_CONFIG_SION, 0x089C, 1, 0)
-#define _MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \
- IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \
- IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \
- IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0)
+#define MX6_ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-#define _MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \
- IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \
- IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \
- IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \
- IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT9__I2C1_SCL \
- IOMUX_PAD(0x064C, 0x027C, 4 | IOMUX_CONFIG_SION, 0x0898, 1, 0)
-#define _MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \
- IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \
- IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \
- IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0)
+#define MX6_I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-#define _MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \
- IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \
- IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \
- IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT10__UART1_TXD \
- IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT10__UART1_RXD \
- IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \
- IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \
- IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \
- IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \
- IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0)
+#define MX6_PWM_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_SRE_FAST)
-#define _MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \
- IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \
- IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \
- IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT11__UART1_TXD \
- IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT11__UART1_RXD \
- IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0)
-#define _MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \
- IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \
- IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \
- IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \
- IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0)
+#define MX6_HIGH_DRV PAD_CTL_DSE_120ohm
-#define _MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \
- IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \
- IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \
- IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT12__UART4_TXD \
- IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT12__UART4_RXD \
- IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \
- IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \
- IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \
- IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \
- IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0)
+#define MX6_DISP_PAD_CTRL MX6_HIGH_DRV
-#define _MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \
- IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \
- IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \
- IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT13__UART4_TXD \
- IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT13__UART4_RXD \
- IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0)
-#define _MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \
- IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \
- IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \
- IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \
- IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0)
+#define MX6_GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define MX6_GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
+#define MX6_GPMI_PAD_CTRL2 (MX6_GPMI_PAD_CTRL0 | MX6_GPMI_PAD_CTRL1)
-#define _MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \
- IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \
- IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \
- IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT14__UART5_TXD \
- IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT14__UART5_RXD \
- IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \
- IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \
- IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \
- IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \
- IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \
- IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \
- IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \
- IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT15__UART5_TXD \
- IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT15__UART5_RXD \
- IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0)
-#define _MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \
- IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \
- IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \
- IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \
- IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \
- IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \
- IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \
- IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT16__UART4_CTS \
- IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT16__UART4_RTS \
- IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \
- IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \
- IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \
- IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \
- IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \
- IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \
- IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \
- IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT17__UART4_CTS \
- IOMUX_PAD(0x066C, 0x029C, 3, 0x0000, 1, 0)
-#define _MX6Q_PAD_CSI0_DAT17__UART4_RTS \
- IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0)
-#define _MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \
- IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \
- IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \
- IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \
- IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \
- IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \
- IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \
- IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT18__UART5_CTS \
- IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT18__UART5_RTS \
- IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0)
-#define _MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \
- IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \
- IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \
- IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \
- IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \
- IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \
- IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \
- IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT19__UART5_CTS \
- IOMUX_PAD(0x0674, 0x02A4, 3, 0x0000, 3, 0)
-#define _MX6Q_PAD_CSI0_DAT19__UART5_RTS \
- IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0)
-#define _MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \
- IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \
- IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \
- IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \
- IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_JTAG_TMS__SJC_TMS \
- IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_JTAG_MOD__SJC_MOD \
- IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \
- IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_JTAG_TDI__SJC_TDI \
- IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_JTAG_TCK__SJC_TCK \
- IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_JTAG_TDO__SJC_TDO \
- IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_POR_B__SRC_POR_B \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_RESET_IN_B__SRC_RESET_B \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \
- IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 \
- IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT7__UART1_TXD \
- IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT7__UART1_RXD \
- IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0)
-#define _MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \
- IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \
- IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \
- IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT7__GPIO_6_17 \
- IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \
- IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \
- IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 \
- IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT6__UART1_TXD \
- IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT6__UART1_RXD \
- IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0)
-#define _MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \
- IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \
- IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \
- IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT6__GPIO_6_18 \
- IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \
- IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \
- IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 \
- IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT5__UART2_TXD \
- IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT5__UART2_RXD \
- IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0)
-#define _MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \
- IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \
- IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \
- IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT5__GPIO_7_0 \
- IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \
- IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \
- IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 \
- IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT4__UART2_TXD \
- IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT4__UART2_RXD \
- IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0)
-#define _MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \
- IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \
- IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \
- IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT4__GPIO_7_1 \
- IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \
- IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \
- IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_CMD__USDHC3_CMD \
- IOMUX_PAD(0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CMD__UART2_CTS \
- IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0000, 2, 0)
-#define _MX6Q_PAD_SD3_CMD__UART2_RTS \
- IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0)
-#define _MX6Q_PAD_SD3_CMD__CAN1_TXCAN \
- IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \
- IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \
- IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CMD__GPIO_7_2 \
- IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \
- IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \
- IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_CLK__USDHC3_CLK \
- IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CLK__UART2_CTS \
- IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CLK__UART2_RTS \
- IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0)
-#define _MX6Q_PAD_SD3_CLK__CAN1_RXCAN \
- IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0)
-#define _MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \
- IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \
- IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CLK__GPIO_7_3 \
- IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \
- IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \
- IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 \
- IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT0__UART1_CTS \
- IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT0__UART1_RTS \
- IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0)
-#define _MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \
- IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \
- IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \
- IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT0__GPIO_7_4 \
- IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \
- IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \
- IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 \
- IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT1__UART1_CTS \
- IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT1__UART1_RTS \
- IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0)
-#define _MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \
- IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0)
-#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \
- IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \
- IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT1__GPIO_7_5 \
- IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \
- IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \
- IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 \
- IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \
- IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \
- IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \
- IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT2__GPIO_7_6 \
- IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \
- IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \
- IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 \
- IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT3__UART3_CTS \
- IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 4, 0)
-#define _MX6Q_PAD_SD3_DAT3__UART3_RTS \
- IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0)
-#define _MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \
- IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \
- IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \
- IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT3__GPIO_7_7 \
- IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \
- IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \
- IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD3_RST__USDHC3_RST \
- IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_RST__UART3_CTS \
- IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_RST__UART3_RTS \
- IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0)
-#define _MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \
- IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \
- IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \
- IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_RST__GPIO_7_8 \
- IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \
- IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \
- IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \
- IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \
- IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \
- IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \
- IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \
- IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CLE__GPIO_6_7 \
- IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \
- IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \
- IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \
- IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_ALE__USDHC4_RST \
- IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \
- IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \
- IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \
- IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_ALE__GPIO_6_8 \
- IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \
- IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \
- IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \
- IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \
- IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \
- IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \
- IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \
- IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \
- IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \
- IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \
- IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \
- IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \
- IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \
- IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \
- IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \
- IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_RB0__GPIO_6_10 \
- IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \
- IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \
- IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \
- IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \
- IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \
- IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS0__GPIO_6_11 \
- IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \
- IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \
- IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \
- IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \
- IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \
- IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS1__GPIO_6_14 \
- IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \
- IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \
- IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \
- IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \
- IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0)
-#define _MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \
- IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \
- IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS2__GPIO_6_15 \
- IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \
- IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \
- IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \
- IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \
- IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0)
-#define _MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \
- IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \
- IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS3__GPIO_6_16 \
- IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \
- IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_CS3__TPSMP_CLK \
- IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_CMD__USDHC4_CMD \
- IOMUX_PAD(0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CMD__RAWNAND_RDN \
- IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CMD__UART3_TXD \
- IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CMD__UART3_RXD \
- IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0)
-#define _MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \
- IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CMD__GPIO_7_9 \
- IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \
- IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_CLK__USDHC4_CLK \
- IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CLK__RAWNAND_WRN \
- IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CLK__UART3_TXD \
- IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CLK__UART3_RXD \
- IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0)
-#define _MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \
- IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_CLK__GPIO_7_10 \
- IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_D0__RAWNAND_D0 \
- IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \
- IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \
- IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \
- IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \
- IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D0__GPIO_2_0 \
- IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \
- IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \
- IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_D1__RAWNAND_D1 \
- IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \
- IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \
- IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \
- IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \
- IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D1__GPIO_2_1 \
- IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \
- IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \
- IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_D2__RAWNAND_D2 \
- IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \
- IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \
- IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \
- IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \
- IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D2__GPIO_2_2 \
- IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \
- IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \
- IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_D3__RAWNAND_D3 \
- IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \
- IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \
- IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \
- IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \
- IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D3__GPIO_2_3 \
- IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \
- IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \
- IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_D4__RAWNAND_D4 \
- IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \
- IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \
- IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \
- IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \
- IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D4__GPIO_2_4 \
- IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \
- IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \
- IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_D5__RAWNAND_D5 \
- IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \
- IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \
- IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \
- IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \
- IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D5__GPIO_2_5 \
- IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \
- IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \
- IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_D6__RAWNAND_D6 \
- IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \
- IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \
- IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \
- IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \
- IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D6__GPIO_2_6 \
- IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \
- IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \
- IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_NANDF_D7__RAWNAND_D7 \
- IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \
- IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \
- IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \
- IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \
- IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D7__GPIO_2_7 \
- IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \
- IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \
- IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \
- IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 \
- IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \
- IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \
- IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \
- IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT0__GPIO_2_8 \
- IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \
- IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \
- IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \
- IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 \
- IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT1__PWM3_PWMO \
- IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \
- IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \
- IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT1__GPIO_2_9 \
- IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \
- IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \
- IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \
- IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 \
- IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT2__PWM4_PWMO \
- IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \
- IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \
- IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT2__GPIO_2_10 \
- IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \
- IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \
- IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \
- IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 \
- IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \
- IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \
- IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT3__GPIO_2_11 \
- IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \
- IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \
- IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \
- IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 \
- IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT4__UART2_TXD \
- IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT4__UART2_RXD \
- IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0)
-#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \
- IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \
- IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT4__GPIO_2_12 \
- IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \
- IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \
- IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \
- IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 \
- IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT5__UART2_CTS \
- IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT5__UART2_RTS \
- IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0)
-#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \
- IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \
- IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT5__GPIO_2_13 \
- IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \
- IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \
- IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \
- IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 \
- IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT6__UART2_CTS \
- IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 5, 0)
-#define _MX6Q_PAD_SD4_DAT6__UART2_RTS \
- IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0)
-#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \
- IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \
- IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT6__GPIO_2_14 \
- IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \
- IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \
- IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \
- IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 \
- IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT7__UART2_TXD \
- IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT7__UART2_RXD \
- IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0)
-#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \
- IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \
- IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT7__GPIO_2_15 \
- IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \
- IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \
- IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \
- IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \
- IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0)
-#define _MX6Q_PAD_SD1_DAT1__PWM3_PWMO \
- IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \
- IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \
- IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT1__GPIO_1_17 \
- IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \
- IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \
- IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \
- IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \
- IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0)
-#define _MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \
- IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \
- IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \
- IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT0__GPIO_1_16 \
- IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \
- IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \
- IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \
- IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \
- IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \
- IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT3__PWM1_PWMO \
- IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \
- IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT3__GPIO_1_21 \
- IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \
- IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \
- IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD1_CMD__USDHC1_CMD \
- IOMUX_PAD(0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \
- IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0)
-#define _MX6Q_PAD_SD1_CMD__PWM4_PWMO \
- IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \
- IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CMD__GPIO_1_18 \
- IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \
- IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \
- IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \
- IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0)
-#define _MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \
- IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT2__PWM2_PWMO \
- IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \
- IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT2__GPIO_1_19 \
- IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \
- IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \
- IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD1_CLK__USDHC1_CLK \
- IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \
- IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0)
-#define _MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \
- IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CLK__GPT_CLKIN \
- IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CLK__GPIO_1_20 \
- IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CLK__PHY_DTB_0 \
- IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \
- IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD2_CLK__USDHC2_CLK \
- IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \
- IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0)
-#define _MX6Q_PAD_SD2_CLK__KPP_COL_5 \
- IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0)
-#define _MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \
- IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0)
-#define _MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \
- IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_CLK__GPIO_1_10 \
- IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_CLK__PHY_DTB_1 \
- IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \
- IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD2_CMD__USDHC2_CMD \
- IOMUX_PAD(0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \
- IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0)
-#define _MX6Q_PAD_SD2_CMD__KPP_ROW_5 \
- IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0)
-#define _MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \
- IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0)
-#define _MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \
- IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_CMD__GPIO_1_11 \
- IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0)
-
-#define _MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \
- IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \
- IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT3__KPP_COL_6 \
- IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0)
-#define _MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \
- IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0)
-#define _MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \
- IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT3__GPIO_1_12 \
- IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT3__SJC_DONE \
- IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0)
-#define _MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \
- IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0)
-
-#define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 (_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0)
-#define MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 (_MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2)
-#define MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS (_MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS)
-#define MX6Q_PAD_SD2_DAT1__KPP_COL_7 (_MX6Q_PAD_SD2_DAT1__KPP_COL_7)
-#define MX6Q_PAD_SD2_DAT1__GPIO_1_14 (_MX6Q_PAD_SD2_DAT1__GPIO_1_14)
-#define MX6Q_PAD_SD2_DAT1__CCM_WAIT (_MX6Q_PAD_SD2_DAT1__CCM_WAIT)
-#define MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 (_MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0)
-
-#define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 (_MX6Q_PAD_SD2_DAT2__ECSPI5_SS1)
-#define MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 (_MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3)
-#define MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD (_MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD)
-#define MX6Q_PAD_SD2_DAT2__KPP_ROW_6 (_MX6Q_PAD_SD2_DAT2__KPP_ROW_6)
-#define MX6Q_PAD_SD2_DAT2__GPIO_1_13 (_MX6Q_PAD_SD2_DAT2__GPIO_1_13)
-#define MX6Q_PAD_SD2_DAT2__CCM_STOP (_MX6Q_PAD_SD2_DAT2__CCM_STOP)
-#define MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 (_MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1)
-
-#define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO (_MX6Q_PAD_SD2_DAT0__ECSPI5_MISO)
-#define MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD (_MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD)
-#define MX6Q_PAD_SD2_DAT0__KPP_ROW_7 (_MX6Q_PAD_SD2_DAT0__KPP_ROW_7)
-#define MX6Q_PAD_SD2_DAT0__GPIO_1_15 (_MX6Q_PAD_SD2_DAT0__GPIO_1_15)
-#define MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT (_MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT)
-#define MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 (_MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2)
-
-#define MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA (_MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA)
-#define MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC (_MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK (_MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK)
-#define MX6Q_PAD_RGMII_TXC__GPIO_6_19 (_MX6Q_PAD_RGMII_TXC__GPIO_6_19)
-#define MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 (_MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0)
-#define MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT (_MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT)
-
-#define MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY (_MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY)
-#define MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 (_MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_RGMII_TD0__GPIO_6_20 (_MX6Q_PAD_RGMII_TD0__GPIO_6_20)
-#define MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 (_MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1)
-
-#define MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG (_MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG)
-#define MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 (_MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_RGMII_TD1__GPIO_6_21 (_MX6Q_PAD_RGMII_TD1__GPIO_6_21)
-#define MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 (_MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2)
-#define MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP (_MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP)
-
-#define MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA (_MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA)
-#define MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 (_MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_RGMII_TD2__GPIO_6_22 (_MX6Q_PAD_RGMII_TD2__GPIO_6_22)
-#define MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 (_MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3)
-#define MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP (_MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP)
-
-#define MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE (_MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE)
-#define MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 (_MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_RGMII_TD3__GPIO_6_23 (_MX6Q_PAD_RGMII_TD3__GPIO_6_23)
-#define MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 (_MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4)
-
-#define MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA (_MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA)
-#define MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL (_MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 (_MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24)
-#define MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 (_MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5)
-
-#define MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY (_MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY)
-#define MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 (_MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_RGMII_RD0__GPIO_6_25 (_MX6Q_PAD_RGMII_RD0__GPIO_6_25)
-#define MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 (_MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6)
-
-#define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE)
-#define MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL (_MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 (_MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26)
-#define MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 (_MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7)
-#define MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT (_MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT)
-
-#define MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG (_MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG)
-#define MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 (_MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_RGMII_RD1__GPIO_6_27 (_MX6Q_PAD_RGMII_RD1__GPIO_6_27)
-#define MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 (_MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8)
-#define MX6Q_PAD_RGMII_RD1__SJC_FAIL (_MX6Q_PAD_RGMII_RD1__SJC_FAIL)
-
-#define MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA (_MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA)
-#define MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 (_MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_RGMII_RD2__GPIO_6_28 (_MX6Q_PAD_RGMII_RD2__GPIO_6_28)
-#define MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 (_MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9)
-
-#define MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE (_MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE)
-#define MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 (_MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_RGMII_RD3__GPIO_6_29 (_MX6Q_PAD_RGMII_RD3__GPIO_6_29)
-#define MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 (_MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10)
-
-#define MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE)
-#define MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC (_MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_RGMII_RXC__GPIO_6_30 (_MX6Q_PAD_RGMII_RXC__GPIO_6_30)
-#define MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 (_MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11)
-
-#define MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 (_MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25)
-#define MX6Q_PAD_EIM_A25__ECSPI4_SS1 (_MX6Q_PAD_EIM_A25__ECSPI4_SS1)
-#define MX6Q_PAD_EIM_A25__ECSPI2_RDY (_MX6Q_PAD_EIM_A25__ECSPI2_RDY)
-#define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 (_MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12)
-#define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS (_MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS)
-#define MX6Q_PAD_EIM_A25__GPIO_5_2 (_MX6Q_PAD_EIM_A25__GPIO_5_2)
-#define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE (_MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE)
-#define MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 (_MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0)
-
-#define MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 (_MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2)
-#define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 (_MX6Q_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
-#define MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK (_MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK)
-#define MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 (_MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19)
-#define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL (_MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL)
-#define MX6Q_PAD_EIM_EB2__GPIO_2_30 (_MX6Q_PAD_EIM_EB2__GPIO_2_30)
-#define MX6Q_PAD_EIM_EB2__I2C2_SCL (_MX6Q_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 (_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30)
-
-#define MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16)
-#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
-#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 (_MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5)
-#define MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 (_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18)
-#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA (_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA)
-#define MX6Q_PAD_EIM_D16__GPIO_3_16 (_MX6Q_PAD_EIM_D16__GPIO_3_16)
-#define MX6Q_PAD_EIM_D16__I2C2_SDA (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-
-#define MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17)
-#define MX6Q_PAD_EIM_D17__ECSPI1_MISO (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
-#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 (_MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6)
-#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK (_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK)
-#define MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT (_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT)
-#define MX6Q_PAD_EIM_D17__GPIO_3_17 (_MX6Q_PAD_EIM_D17__GPIO_3_17)
-#define MX6Q_PAD_EIM_D17__I2C3_SCL (_MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 (_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1)
-
-#define MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18)
-#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
-#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 (_MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7)
-#define MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 (_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17)
-#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS (_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS)
-#define MX6Q_PAD_EIM_D18__GPIO_3_18 (_MX6Q_PAD_EIM_D18__GPIO_3_18)
-#define MX6Q_PAD_EIM_D18__I2C3_SDA (_MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 (_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2)
-
-#define MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19)
-#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
-#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 (_MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8)
-#define MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 (_MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16)
-#define MX6Q_PAD_EIM_D19__UART1_CTS (_MX6Q_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D19__GPIO_3_19 (_MX6Q_PAD_EIM_D19__GPIO_3_19)
-#define MX6Q_PAD_EIM_D19__EPIT1_EPITO (_MX6Q_PAD_EIM_D19__EPIT1_EPITO)
-#define MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP (_MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP)
-
-#define MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 (_MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20)
-#define MX6Q_PAD_EIM_D20__ECSPI4_SS0 (_MX6Q_PAD_EIM_D20__ECSPI4_SS0)
-#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 (_MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16)
-#define MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 (_MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15)
-#define MX6Q_PAD_EIM_D20__UART1_CTS (_MX6Q_PAD_EIM_D20__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D20__UART1_RTS (_MX6Q_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D20__GPIO_3_20 (_MX6Q_PAD_EIM_D20__GPIO_3_20)
-#define MX6Q_PAD_EIM_D20__EPIT2_EPITO (_MX6Q_PAD_EIM_D20__EPIT2_EPITO)
-
-#define MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 (_MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21)
-#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK (_MX6Q_PAD_EIM_D21__ECSPI4_SCLK)
-#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 (_MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17)
-#define MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 (_MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11)
-#define MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC (_MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC)
-#define MX6Q_PAD_EIM_D21__GPIO_3_21 (_MX6Q_PAD_EIM_D21__GPIO_3_21)
-#define MX6Q_PAD_EIM_D21__I2C1_SCL (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define MX6Q_PAD_EIM_D21__SPDIF_IN1 (_MX6Q_PAD_EIM_D21__SPDIF_IN1)
-
-#define MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 (_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22)
-#define MX6Q_PAD_EIM_D22__ECSPI4_MISO (_MX6Q_PAD_EIM_D22__ECSPI4_MISO)
-#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 (_MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1)
-#define MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 (_MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10)
-#define MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR (_MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR)
-#define MX6Q_PAD_EIM_D22__GPIO_3_22 (_MX6Q_PAD_EIM_D22__GPIO_3_22)
-#define MX6Q_PAD_EIM_D22__SPDIF_OUT1 (_MX6Q_PAD_EIM_D22__SPDIF_OUT1)
-#define MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE (_MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE)
-
-#define MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 (_MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23)
-#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS (_MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS)
-#define MX6Q_PAD_EIM_D23__UART3_CTS (_MX6Q_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D23__UART1_DCD (_MX6Q_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN (_MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN)
-#define MX6Q_PAD_EIM_D23__GPIO_3_23 (_MX6Q_PAD_EIM_D23__GPIO_3_23)
-#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2)
-#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14)
-
-#define MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 (_MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3)
-#define MX6Q_PAD_EIM_EB3__ECSPI4_RDY (_MX6Q_PAD_EIM_EB3__ECSPI4_RDY)
-#define MX6Q_PAD_EIM_EB3__UART3_CTS (_MX6Q_PAD_EIM_EB3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_EB3__UART3_RTS (_MX6Q_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_EB3__UART1_RI (_MX6Q_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC (_MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC)
-#define MX6Q_PAD_EIM_EB3__GPIO_2_31 (_MX6Q_PAD_EIM_EB3__GPIO_2_31)
-#define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 (_MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3)
-#define MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 (_MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31)
-
-#define MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 (_MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24)
-#define MX6Q_PAD_EIM_D24__ECSPI4_SS2 (_MX6Q_PAD_EIM_D24__ECSPI4_SS2)
-#define MX6Q_PAD_EIM_D24__UART3_TXD (_MX6Q_PAD_EIM_D24__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D24__UART3_RXD (_MX6Q_PAD_EIM_D24__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D24__ECSPI1_SS2 (_MX6Q_PAD_EIM_D24__ECSPI1_SS2)
-#define MX6Q_PAD_EIM_D24__ECSPI2_SS2 (_MX6Q_PAD_EIM_D24__ECSPI2_SS2)
-#define MX6Q_PAD_EIM_D24__GPIO_3_24 (_MX6Q_PAD_EIM_D24__GPIO_3_24)
-#define MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS (_MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS)
-#define MX6Q_PAD_EIM_D24__UART1_DTR (_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-
-#define MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 (_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25)
-#define MX6Q_PAD_EIM_D25__ECSPI4_SS3 (_MX6Q_PAD_EIM_D25__ECSPI4_SS3)
-#define MX6Q_PAD_EIM_D25__UART3_TXD (_MX6Q_PAD_EIM_D25__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D25__UART3_RXD (_MX6Q_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D25__ECSPI1_SS3 (_MX6Q_PAD_EIM_D25__ECSPI1_SS3)
-#define MX6Q_PAD_EIM_D25__ECSPI2_SS3 (_MX6Q_PAD_EIM_D25__ECSPI2_SS3)
-#define MX6Q_PAD_EIM_D25__GPIO_3_25 (_MX6Q_PAD_EIM_D25__GPIO_3_25)
-#define MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC (_MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC)
-#define MX6Q_PAD_EIM_D25__UART1_DSR (_MX6Q_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-
-#define MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 (_MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26)
-#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 (_MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11)
-#define MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 (_MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1)
-#define MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 (_MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14)
-#define MX6Q_PAD_EIM_D26__UART2_TXD (_MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D26__UART2_RXD (_MX6Q_PAD_EIM_D26__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D26__GPIO_3_26 (_MX6Q_PAD_EIM_D26__GPIO_3_26)
-#define MX6Q_PAD_EIM_D26__IPU1_SISG_2 (_MX6Q_PAD_EIM_D26__IPU1_SISG_2)
-#define MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 (_MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22)
-
-#define MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 (_MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27)
-#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 (_MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13)
-#define MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 (_MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0)
-#define MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 (_MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13)
-#define MX6Q_PAD_EIM_D27__UART2_TXD (_MX6Q_PAD_EIM_D27__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D27__UART2_RXD (_MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D27__GPIO_3_27 (_MX6Q_PAD_EIM_D27__GPIO_3_27)
-#define MX6Q_PAD_EIM_D27__IPU1_SISG_3 (_MX6Q_PAD_EIM_D27__IPU1_SISG_3)
-#define MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 (_MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23)
-
-#define MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28)
-#define MX6Q_PAD_EIM_D28__I2C1_SDA (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI (_MX6Q_PAD_EIM_D28__ECSPI4_MOSI)
-#define MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 (_MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12)
-#define MX6Q_PAD_EIM_D28__UART2_CTS (_MX6Q_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D28__GPIO_3_28 (_MX6Q_PAD_EIM_D28__GPIO_3_28)
-#define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG (_MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG)
-#define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 (_MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13)
-
-#define MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 (_MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29)
-#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 (_MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15)
-#define MX6Q_PAD_EIM_D29__ECSPI4_SS0 (_MX6Q_PAD_EIM_D29__ECSPI4_SS0)
-#define MX6Q_PAD_EIM_D29__UART2_CTS (_MX6Q_PAD_EIM_D29__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D29__UART2_RTS (_MX6Q_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D29__GPIO_3_29 (_MX6Q_PAD_EIM_D29__GPIO_3_29)
-#define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC (_MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC)
-#define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 (_MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14)
-
-#define MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 (_MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30)
-#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 (_MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21)
-#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 (_MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11)
-#define MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 (_MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3)
-#define MX6Q_PAD_EIM_D30__UART3_CTS (_MX6Q_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D30__GPIO_3_30 (_MX6Q_PAD_EIM_D30__GPIO_3_30)
-#define MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC (_MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC)
-#define MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 (_MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0)
-
-#define MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 (_MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31)
-#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 (_MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20)
-#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 (_MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12)
-#define MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 (_MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2)
-#define MX6Q_PAD_EIM_D31__UART3_CTS (_MX6Q_PAD_EIM_D31__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D31__UART3_RTS (_MX6Q_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_EIM_D31__GPIO_3_31 (_MX6Q_PAD_EIM_D31__GPIO_3_31)
-#define MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR (_MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR)
-#define MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 (_MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1)
-
-#define MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 (_MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24)
-#define MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 (_MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19)
-#define MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 (_MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19)
-#define MX6Q_PAD_EIM_A24__IPU2_SISG_2 (_MX6Q_PAD_EIM_A24__IPU2_SISG_2)
-#define MX6Q_PAD_EIM_A24__IPU1_SISG_2 (_MX6Q_PAD_EIM_A24__IPU1_SISG_2)
-#define MX6Q_PAD_EIM_A24__GPIO_5_4 (_MX6Q_PAD_EIM_A24__GPIO_5_4)
-#define MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 (_MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2)
-#define MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 (_MX6Q_PAD_EIM_A24__SRC_BT_CFG_24)
-
-#define MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 (_MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23)
-#define MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 (_MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18)
-#define MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 (_MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18)
-#define MX6Q_PAD_EIM_A23__IPU2_SISG_3 (_MX6Q_PAD_EIM_A23__IPU2_SISG_3)
-#define MX6Q_PAD_EIM_A23__IPU1_SISG_3 (_MX6Q_PAD_EIM_A23__IPU1_SISG_3)
-#define MX6Q_PAD_EIM_A23__GPIO_6_6 (_MX6Q_PAD_EIM_A23__GPIO_6_6)
-#define MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 (_MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3)
-#define MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 (_MX6Q_PAD_EIM_A23__SRC_BT_CFG_23)
-
-#define MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 (_MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22)
-#define MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 (_MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17)
-#define MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 (_MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17)
-#define MX6Q_PAD_EIM_A22__GPIO_2_16 (_MX6Q_PAD_EIM_A22__GPIO_2_16)
-#define MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 (_MX6Q_PAD_EIM_A22__TPSMP_HDATA_0)
-#define MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 (_MX6Q_PAD_EIM_A22__SRC_BT_CFG_22)
-
-#define MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 (_MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21)
-#define MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 (_MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16)
-#define MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 (_MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16)
-#define MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 (_MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18)
-#define MX6Q_PAD_EIM_A21__GPIO_2_17 (_MX6Q_PAD_EIM_A21__GPIO_2_17)
-#define MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 (_MX6Q_PAD_EIM_A21__TPSMP_HDATA_1)
-#define MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 (_MX6Q_PAD_EIM_A21__SRC_BT_CFG_21)
-
-#define MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 (_MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20)
-#define MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 (_MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15)
-#define MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 (_MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15)
-#define MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 (_MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19)
-#define MX6Q_PAD_EIM_A20__GPIO_2_18 (_MX6Q_PAD_EIM_A20__GPIO_2_18)
-#define MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 (_MX6Q_PAD_EIM_A20__TPSMP_HDATA_2)
-#define MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 (_MX6Q_PAD_EIM_A20__SRC_BT_CFG_20)
-
-#define MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 (_MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19)
-#define MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 (_MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14)
-#define MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 (_MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14)
-#define MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 (_MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20)
-#define MX6Q_PAD_EIM_A19__GPIO_2_19 (_MX6Q_PAD_EIM_A19__GPIO_2_19)
-#define MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 (_MX6Q_PAD_EIM_A19__TPSMP_HDATA_3)
-#define MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 (_MX6Q_PAD_EIM_A19__SRC_BT_CFG_19)
-
-#define MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 (_MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18)
-#define MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 (_MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13)
-#define MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 (_MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13)
-#define MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 (_MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21)
-#define MX6Q_PAD_EIM_A18__GPIO_2_20 (_MX6Q_PAD_EIM_A18__GPIO_2_20)
-#define MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 (_MX6Q_PAD_EIM_A18__TPSMP_HDATA_4)
-#define MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 (_MX6Q_PAD_EIM_A18__SRC_BT_CFG_18)
-
-#define MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 (_MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17)
-#define MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 (_MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12)
-#define MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 (_MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12)
-#define MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 (_MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22)
-#define MX6Q_PAD_EIM_A17__GPIO_2_21 (_MX6Q_PAD_EIM_A17__GPIO_2_21)
-#define MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 (_MX6Q_PAD_EIM_A17__TPSMP_HDATA_5)
-#define MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 (_MX6Q_PAD_EIM_A17__SRC_BT_CFG_17)
-
-#define MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 (_MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16)
-#define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK (_MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK)
-#define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK (_MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK)
-#define MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 (_MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23)
-#define MX6Q_PAD_EIM_A16__GPIO_2_22 (_MX6Q_PAD_EIM_A16__GPIO_2_22)
-#define MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 (_MX6Q_PAD_EIM_A16__TPSMP_HDATA_6)
-#define MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 (_MX6Q_PAD_EIM_A16__SRC_BT_CFG_16)
-
-#define MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 (_MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0)
-#define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 (_MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5)
-#define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK (_MX6Q_PAD_EIM_CS0__ECSPI2_SCLK)
-#define MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 (_MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24)
-#define MX6Q_PAD_EIM_CS0__GPIO_2_23 (_MX6Q_PAD_EIM_CS0__GPIO_2_23)
-#define MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 (_MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7)
-
-#define MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 (_MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1)
-#define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 (_MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6)
-#define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI (_MX6Q_PAD_EIM_CS1__ECSPI2_MOSI)
-#define MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 (_MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25)
-#define MX6Q_PAD_EIM_CS1__GPIO_2_24 (_MX6Q_PAD_EIM_CS1__GPIO_2_24)
-#define MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 (_MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8)
-
-#define MX6Q_PAD_EIM_OE__WEIM_WEIM_OE (_MX6Q_PAD_EIM_OE__WEIM_WEIM_OE)
-#define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 (_MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7)
-#define MX6Q_PAD_EIM_OE__ECSPI2_MISO (_MX6Q_PAD_EIM_OE__ECSPI2_MISO)
-#define MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 (_MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26)
-#define MX6Q_PAD_EIM_OE__GPIO_2_25 (_MX6Q_PAD_EIM_OE__GPIO_2_25)
-#define MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 (_MX6Q_PAD_EIM_OE__TPSMP_HDATA_9)
-
-#define MX6Q_PAD_EIM_RW__WEIM_WEIM_RW (_MX6Q_PAD_EIM_RW__WEIM_WEIM_RW)
-#define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 (_MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8)
-#define MX6Q_PAD_EIM_RW__ECSPI2_SS0 (_MX6Q_PAD_EIM_RW__ECSPI2_SS0)
-#define MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 (_MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27)
-#define MX6Q_PAD_EIM_RW__GPIO_2_26 (_MX6Q_PAD_EIM_RW__GPIO_2_26)
-#define MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 (_MX6Q_PAD_EIM_RW__TPSMP_HDATA_10)
-#define MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 (_MX6Q_PAD_EIM_RW__SRC_BT_CFG_29)
-
-#define MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA (_MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA)
-#define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 (_MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17)
-#define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 (_MX6Q_PAD_EIM_LBA__ECSPI2_SS1)
-#define MX6Q_PAD_EIM_LBA__GPIO_2_27 (_MX6Q_PAD_EIM_LBA__GPIO_2_27)
-#define MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 (_MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11)
-#define MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 (_MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26)
-
-#define MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 (_MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0)
-#define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 (_MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11)
-#define MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 (_MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11)
-#define MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 (_MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0)
-#define MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY (_MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY)
-#define MX6Q_PAD_EIM_EB0__GPIO_2_28 (_MX6Q_PAD_EIM_EB0__GPIO_2_28)
-#define MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 (_MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12)
-#define MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 (_MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27)
-
-#define MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 (_MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1)
-#define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 (_MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10)
-#define MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 (_MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10)
-#define MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 (_MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1)
-#define MX6Q_PAD_EIM_EB1__GPIO_2_29 (_MX6Q_PAD_EIM_EB1__GPIO_2_29)
-#define MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 (_MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13)
-#define MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 (_MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28)
-
-#define MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 (_MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0)
-#define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 (_MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9)
-#define MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 (_MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9)
-#define MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 (_MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2)
-#define MX6Q_PAD_EIM_DA0__GPIO_3_0 (_MX6Q_PAD_EIM_DA0__GPIO_3_0)
-#define MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 (_MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14)
-#define MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 (_MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0)
-
-#define MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 (_MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1)
-#define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 (_MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8)
-#define MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 (_MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8)
-#define MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 (_MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3)
-#define MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE (_MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE)
-#define MX6Q_PAD_EIM_DA1__GPIO_3_1 (_MX6Q_PAD_EIM_DA1__GPIO_3_1)
-#define MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 (_MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15)
-#define MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 (_MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1)
-
-#define MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 (_MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2)
-#define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 (_MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7)
-#define MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 (_MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7)
-#define MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 (_MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4)
-#define MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE (_MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE)
-#define MX6Q_PAD_EIM_DA2__GPIO_3_2 (_MX6Q_PAD_EIM_DA2__GPIO_3_2)
-#define MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 (_MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16)
-#define MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 (_MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2)
-
-#define MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 (_MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3)
-#define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 (_MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6)
-#define MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 (_MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6)
-#define MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 (_MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5)
-#define MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ (_MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ)
-#define MX6Q_PAD_EIM_DA3__GPIO_3_3 (_MX6Q_PAD_EIM_DA3__GPIO_3_3)
-#define MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 (_MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17)
-#define MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 (_MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3)
-
-#define MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 (_MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4)
-#define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 (_MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5)
-#define MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 (_MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5)
-#define MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 (_MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6)
-#define MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN (_MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN)
-#define MX6Q_PAD_EIM_DA4__GPIO_3_4 (_MX6Q_PAD_EIM_DA4__GPIO_3_4)
-#define MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 (_MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18)
-#define MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 (_MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4)
-
-#define MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 (_MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5)
-#define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 (_MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4)
-#define MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 (_MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4)
-#define MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 (_MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7)
-#define MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP (_MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP)
-#define MX6Q_PAD_EIM_DA5__GPIO_3_5 (_MX6Q_PAD_EIM_DA5__GPIO_3_5)
-#define MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 (_MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19)
-#define MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 (_MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5)
-
-#define MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 (_MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6)
-#define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 (_MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3)
-#define MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 (_MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3)
-#define MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 (_MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8)
-#define MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN (_MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN)
-#define MX6Q_PAD_EIM_DA6__GPIO_3_6 (_MX6Q_PAD_EIM_DA6__GPIO_3_6)
-#define MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 (_MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20)
-#define MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 (_MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6)
-
-#define MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 (_MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7)
-#define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 (_MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2)
-#define MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 (_MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2)
-#define MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 (_MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9)
-#define MX6Q_PAD_EIM_DA7__GPIO_3_7 (_MX6Q_PAD_EIM_DA7__GPIO_3_7)
-#define MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 (_MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21)
-#define MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 (_MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7)
-
-#define MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 (_MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8)
-#define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 (_MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1)
-#define MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 (_MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1)
-#define MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 (_MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10)
-#define MX6Q_PAD_EIM_DA8__GPIO_3_8 (_MX6Q_PAD_EIM_DA8__GPIO_3_8)
-#define MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 (_MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22)
-#define MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 (_MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8)
-
-#define MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 (_MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9)
-#define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 (_MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0)
-#define MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 (_MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0)
-#define MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 (_MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11)
-#define MX6Q_PAD_EIM_DA9__GPIO_3_9 (_MX6Q_PAD_EIM_DA9__GPIO_3_9)
-#define MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 (_MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23)
-#define MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 (_MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9)
-
-#define MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 (_MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10)
-#define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 (_MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15)
-#define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN (_MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN)
-#define MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 (_MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12)
-#define MX6Q_PAD_EIM_DA10__GPIO_3_10 (_MX6Q_PAD_EIM_DA10__GPIO_3_10)
-#define MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 (_MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24)
-#define MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 (_MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10)
-
-#define MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 (_MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11)
-#define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 (_MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2)
-#define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC (_MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC)
-#define MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 (_MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13)
-#define MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 (_MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6)
-#define MX6Q_PAD_EIM_DA11__GPIO_3_11 (_MX6Q_PAD_EIM_DA11__GPIO_3_11)
-#define MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 (_MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25)
-#define MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 (_MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11)
-
-#define MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 (_MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12)
-#define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 (_MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3)
-#define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC (_MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC)
-#define MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 (_MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14)
-#define MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 (_MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3)
-#define MX6Q_PAD_EIM_DA12__GPIO_3_12 (_MX6Q_PAD_EIM_DA12__GPIO_3_12)
-#define MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 (_MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26)
-#define MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 (_MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12)
-
-#define MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 (_MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13)
-#define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS (_MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS)
-#define MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK (_MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK)
-#define MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 (_MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15)
-#define MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 (_MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4)
-#define MX6Q_PAD_EIM_DA13__GPIO_3_13 (_MX6Q_PAD_EIM_DA13__GPIO_3_13)
-#define MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 (_MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27)
-#define MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 (_MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13)
-
-#define MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 (_MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14)
-#define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS (_MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS)
-#define MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK (_MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK)
-#define MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 (_MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16)
-#define MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 (_MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5)
-#define MX6Q_PAD_EIM_DA14__GPIO_3_14 (_MX6Q_PAD_EIM_DA14__GPIO_3_14)
-#define MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 (_MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28)
-#define MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 (_MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14)
-
-#define MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 (_MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15)
-#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1)
-#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4)
-#define MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 (_MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17)
-#define MX6Q_PAD_EIM_DA15__GPIO_3_15 (_MX6Q_PAD_EIM_DA15__GPIO_3_15)
-#define MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 (_MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29)
-#define MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 (_MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15)
-
-#define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT)
-#define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B)
-#define MX6Q_PAD_EIM_WAIT__GPIO_5_0 (_MX6Q_PAD_EIM_WAIT__GPIO_5_0)
-#define MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 (_MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30)
-#define MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 (_MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25)
-
-#define MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK (_MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK)
-#define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 (_MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16)
-#define MX6Q_PAD_EIM_BCLK__GPIO_6_31 (_MX6Q_PAD_EIM_BCLK__GPIO_6_31)
-#define MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 (_MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31)
-
-#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK)
-#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK (_MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK)
-#define MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 (_MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28)
-#define MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 (_MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0)
-#define MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 (_MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16)
-#define MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 (_MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0)
-
-#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 (_MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15)
-#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 (_MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15)
-#define MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC (_MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC)
-#define MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 (_MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29)
-#define MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 (_MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1)
-#define MX6Q_PAD_DI0_PIN15__GPIO_4_17 (_MX6Q_PAD_DI0_PIN15__GPIO_4_17)
-#define MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 (_MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1)
-
-#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 (_MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2)
-#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 (_MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2)
-#define MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD (_MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD)
-#define MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 (_MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30)
-#define MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 (_MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2)
-#define MX6Q_PAD_DI0_PIN2__GPIO_4_18 (_MX6Q_PAD_DI0_PIN2__GPIO_4_18)
-#define MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 (_MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2)
-#define MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 (_MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9)
-
-#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 (_MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3)
-#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 (_MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3)
-#define MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS (_MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS)
-#define MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 (_MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31)
-#define MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 (_MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3)
-#define MX6Q_PAD_DI0_PIN3__GPIO_4_19 (_MX6Q_PAD_DI0_PIN3__GPIO_4_19)
-#define MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 (_MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3)
-#define MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 (_MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10)
-
-#define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 (_MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4)
-#define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 (_MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4)
-#define MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD (_MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD)
-#define MX6Q_PAD_DI0_PIN4__USDHC1_WP (_MX6Q_PAD_DI0_PIN4__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD (_MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD)
-#define MX6Q_PAD_DI0_PIN4__GPIO_4_20 (_MX6Q_PAD_DI0_PIN4__GPIO_4_20)
-#define MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 (_MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4)
-#define MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 (_MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11)
-
-#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 (_MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0)
-#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 (_MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0)
-#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK (_MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK)
-#define MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 (_MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN (_MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN)
-#define MX6Q_PAD_DISP0_DAT0__GPIO_4_21 (_MX6Q_PAD_DISP0_DAT0__GPIO_4_21)
-#define MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 (_MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5)
-
-#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 (_MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1)
-#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 (_MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1)
-#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI (_MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI)
-#define MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 (_MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL (_MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL)
-#define MX6Q_PAD_DISP0_DAT1__GPIO_4_22 (_MX6Q_PAD_DISP0_DAT1__GPIO_4_22)
-#define MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 (_MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6)
-#define MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 (_MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12)
-
-#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 (_MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2)
-#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 (_MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2)
-#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO (_MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO)
-#define MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 (_MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE (_MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE)
-#define MX6Q_PAD_DISP0_DAT2__GPIO_4_23 (_MX6Q_PAD_DISP0_DAT2__GPIO_4_23)
-#define MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 (_MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7)
-#define MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 (_MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13)
-
-#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 (_MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3)
-#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 (_MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3)
-#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 (_MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0)
-#define MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 (_MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR (_MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR)
-#define MX6Q_PAD_DISP0_DAT3__GPIO_4_24 (_MX6Q_PAD_DISP0_DAT3__GPIO_4_24)
-#define MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 (_MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8)
-#define MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 (_MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14)
-
-#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 (_MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4)
-#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 (_MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4)
-#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 (_MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1)
-#define MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 (_MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB (_MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB)
-#define MX6Q_PAD_DISP0_DAT4__GPIO_4_25 (_MX6Q_PAD_DISP0_DAT4__GPIO_4_25)
-#define MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 (_MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9)
-#define MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 (_MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15)
-
-#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 (_MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5)
-#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 (_MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5)
-#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 (_MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2)
-#define MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS (_MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS)
-#define MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS (_MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS)
-#define MX6Q_PAD_DISP0_DAT5__GPIO_4_26 (_MX6Q_PAD_DISP0_DAT5__GPIO_4_26)
-#define MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 (_MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10)
-#define MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 (_MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16)
-
-#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 (_MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6)
-#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 (_MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6)
-#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 (_MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3)
-#define MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC (_MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC)
-#define MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE (_MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE)
-#define MX6Q_PAD_DISP0_DAT6__GPIO_4_27 (_MX6Q_PAD_DISP0_DAT6__GPIO_4_27)
-#define MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 (_MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11)
-#define MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 (_MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17)
-
-#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 (_MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7)
-#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 (_MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7)
-#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY (_MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY)
-#define MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 (_MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 (_MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0)
-#define MX6Q_PAD_DISP0_DAT7__GPIO_4_28 (_MX6Q_PAD_DISP0_DAT7__GPIO_4_28)
-#define MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 (_MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12)
-#define MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 (_MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18)
-
-#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 (_MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8)
-#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 (_MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8)
-#define MX6Q_PAD_DISP0_DAT8__PWM1_PWMO (_MX6Q_PAD_DISP0_DAT8__PWM1_PWMO)
-#define MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B (_MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B)
-#define MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 (_MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1)
-#define MX6Q_PAD_DISP0_DAT8__GPIO_4_29 (_MX6Q_PAD_DISP0_DAT8__GPIO_4_29)
-#define MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 (_MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13)
-#define MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 (_MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19)
-
-#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 (_MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9)
-#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 (_MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9)
-#define MX6Q_PAD_DISP0_DAT9__PWM2_PWMO (_MX6Q_PAD_DISP0_DAT9__PWM2_PWMO)
-#define MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B (_MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B)
-#define MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 (_MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2)
-#define MX6Q_PAD_DISP0_DAT9__GPIO_4_30 (_MX6Q_PAD_DISP0_DAT9__GPIO_4_30)
-#define MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 (_MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14)
-#define MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 (_MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20)
-
-#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 (_MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10)
-#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 (_MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10)
-#define MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 (_MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 (_MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3)
-#define MX6Q_PAD_DISP0_DAT10__GPIO_4_31 (_MX6Q_PAD_DISP0_DAT10__GPIO_4_31)
-#define MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 (_MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15)
-#define MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 (_MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21)
-
-#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 (_MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11)
-#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 (_MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11)
-#define MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 (_MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 (_MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4)
-#define MX6Q_PAD_DISP0_DAT11__GPIO_5_5 (_MX6Q_PAD_DISP0_DAT11__GPIO_5_5)
-#define MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 (_MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16)
-#define MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 (_MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22)
-
-#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 (_MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12)
-#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 (_MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12)
-#define MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 (_MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5)
-#define MX6Q_PAD_DISP0_DAT12__GPIO_5_6 (_MX6Q_PAD_DISP0_DAT12__GPIO_5_6)
-#define MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 (_MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17)
-#define MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 (_MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23)
-
-#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 (_MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13)
-#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 (_MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13)
-#define MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS (_MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS)
-#define MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 (_MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0)
-#define MX6Q_PAD_DISP0_DAT13__GPIO_5_7 (_MX6Q_PAD_DISP0_DAT13__GPIO_5_7)
-#define MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 (_MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18)
-#define MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 (_MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24)
-
-#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 (_MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14)
-#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 (_MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14)
-#define MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC (_MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC)
-#define MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 (_MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1)
-#define MX6Q_PAD_DISP0_DAT14__GPIO_5_8 (_MX6Q_PAD_DISP0_DAT14__GPIO_5_8)
-#define MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 (_MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19)
-
-#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 (_MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15)
-#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 (_MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15)
-#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 (_MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1)
-#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 (_MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1)
-#define MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 (_MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2)
-#define MX6Q_PAD_DISP0_DAT15__GPIO_5_9 (_MX6Q_PAD_DISP0_DAT15__GPIO_5_9)
-#define MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 (_MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20)
-#define MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 (_MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25)
-
-#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 (_MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16)
-#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 (_MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16)
-#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI (_MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI)
-#define MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC (_MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC)
-#define MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 (_MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0)
-#define MX6Q_PAD_DISP0_DAT16__GPIO_5_10 (_MX6Q_PAD_DISP0_DAT16__GPIO_5_10)
-#define MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 (_MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21)
-#define MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 (_MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26)
-
-#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 (_MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17)
-#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 (_MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17)
-#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO (_MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO)
-#define MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD (_MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD)
-#define MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 (_MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1)
-#define MX6Q_PAD_DISP0_DAT17__GPIO_5_11 (_MX6Q_PAD_DISP0_DAT17__GPIO_5_11)
-#define MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 (_MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22)
-#define MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 (_MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27)
-
-#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 (_MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18)
-#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 (_MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18)
-#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 (_MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0)
-#define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS)
-#define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS)
-#define MX6Q_PAD_DISP0_DAT18__GPIO_5_12 (_MX6Q_PAD_DISP0_DAT18__GPIO_5_12)
-#define MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 (_MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23)
-#define MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 (_MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2)
-
-#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 (_MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19)
-#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 (_MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19)
-#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK (_MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK)
-#define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD)
-#define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC)
-#define MX6Q_PAD_DISP0_DAT19__GPIO_5_13 (_MX6Q_PAD_DISP0_DAT19__GPIO_5_13)
-#define MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 (_MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24)
-#define MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 (_MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3)
-
-#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 (_MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20)
-#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 (_MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20)
-#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK (_MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK)
-#define MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC (_MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC)
-#define MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 (_MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7)
-#define MX6Q_PAD_DISP0_DAT20__GPIO_5_14 (_MX6Q_PAD_DISP0_DAT20__GPIO_5_14)
-#define MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 (_MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25)
-#define MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 (_MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28)
-
-#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 (_MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21)
-#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 (_MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21)
-#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI (_MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI)
-#define MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD (_MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD)
-#define MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 (_MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0)
-#define MX6Q_PAD_DISP0_DAT21__GPIO_5_15 (_MX6Q_PAD_DISP0_DAT21__GPIO_5_15)
-#define MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 (_MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26)
-#define MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 (_MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29)
-
-#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 (_MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22)
-#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 (_MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22)
-#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO (_MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO)
-#define MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS (_MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS)
-#define MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 (_MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1)
-#define MX6Q_PAD_DISP0_DAT22__GPIO_5_16 (_MX6Q_PAD_DISP0_DAT22__GPIO_5_16)
-#define MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 (_MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27)
-#define MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 (_MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30)
-
-#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 (_MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23)
-#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 (_MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23)
-#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 (_MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0)
-#define MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD (_MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD)
-#define MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 (_MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2)
-#define MX6Q_PAD_DISP0_DAT23__GPIO_5_17 (_MX6Q_PAD_DISP0_DAT23__GPIO_5_17)
-#define MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 (_MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28)
-#define MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 (_MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31)
-
-#define MX6Q_PAD_ENET_MDIO__ENET_MDIO (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_ENET_MDIO__ESAI1_SCKR (_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR)
-#define MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 (_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3)
-#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT (_MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT)
-#define MX6Q_PAD_ENET_MDIO__GPIO_1_22 (_MX6Q_PAD_ENET_MDIO__GPIO_1_22)
-#define MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK (_MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK)
-
-#define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK (_MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR (_MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR)
-#define MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 (_MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4)
-#define MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 (_MX6Q_PAD_ENET_REF_CLK__GPIO_1_23)
-#define MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK (_MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK)
-#define MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH (_MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH)
-
-#define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER (_MX6Q_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR (_MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR)
-#define MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 (_MX6Q_PAD_ENET_RX_ER__SPDIF_IN1)
-#define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT (_MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT)
-#define MX6Q_PAD_ENET_RX_ER__GPIO_1_24 (_MX6Q_PAD_ENET_RX_ER__GPIO_1_24)
-#define MX6Q_PAD_ENET_RX_ER__PHY_TDI (_MX6Q_PAD_ENET_RX_ER__PHY_TDI)
-#define MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD (_MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD)
-
-#define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN (_MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT (_MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT)
-#define MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK (_MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK)
-#define MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 (_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25)
-#define MX6Q_PAD_ENET_CRS_DV__PHY_TDO (_MX6Q_PAD_ENET_CRS_DV__PHY_TDO)
-#define MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD (_MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD)
-
-#define MX6Q_PAD_ENET_RXD1__MLB_MLBSIG (_MX6Q_PAD_ENET_RXD1__MLB_MLBSIG)
-#define MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 (_MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_ENET_RXD1__ESAI1_FST (_MX6Q_PAD_ENET_RXD1__ESAI1_FST)
-#define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT (_MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT)
-#define MX6Q_PAD_ENET_RXD1__GPIO_1_26 (_MX6Q_PAD_ENET_RXD1__GPIO_1_26)
-#define MX6Q_PAD_ENET_RXD1__PHY_TCK (_MX6Q_PAD_ENET_RXD1__PHY_TCK)
-#define MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET (_MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET)
-
-#define MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT (_MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT)
-#define MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 (_MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_ENET_RXD0__ESAI1_HCKT (_MX6Q_PAD_ENET_RXD0__ESAI1_HCKT)
-#define MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 (_MX6Q_PAD_ENET_RXD0__SPDIF_OUT1)
-#define MX6Q_PAD_ENET_RXD0__GPIO_1_27 (_MX6Q_PAD_ENET_RXD0__GPIO_1_27)
-#define MX6Q_PAD_ENET_RXD0__PHY_TMS (_MX6Q_PAD_ENET_RXD0__PHY_TMS)
-#define MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV (_MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV)
-
-#define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN (_MX6Q_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 (_MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2)
-#define MX6Q_PAD_ENET_TX_EN__GPIO_1_28 (_MX6Q_PAD_ENET_TX_EN__GPIO_1_28)
-#define MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI (_MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI)
-#define MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH (_MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH)
-
-#define MX6Q_PAD_ENET_TXD1__MLB_MLBCLK (_MX6Q_PAD_ENET_TXD1__MLB_MLBCLK)
-#define MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 (_MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 (_MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3)
-#define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN (_MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN)
-#define MX6Q_PAD_ENET_TXD1__GPIO_1_29 (_MX6Q_PAD_ENET_TXD1__GPIO_1_29)
-#define MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO (_MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO)
-#define MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD (_MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD)
-
-#define MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 (_MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 (_MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1)
-#define MX6Q_PAD_ENET_TXD0__GPIO_1_30 (_MX6Q_PAD_ENET_TXD0__GPIO_1_30)
-#define MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK (_MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK)
-#define MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD (_MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD)
-
-#define MX6Q_PAD_ENET_MDC__MLB_MLBDAT (_MX6Q_PAD_ENET_MDC__MLB_MLBDAT)
-#define MX6Q_PAD_ENET_MDC__ENET_MDC (_MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 (_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0)
-#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN (_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN)
-#define MX6Q_PAD_ENET_MDC__GPIO_1_31 (_MX6Q_PAD_ENET_MDC__GPIO_1_31)
-#define MX6Q_PAD_ENET_MDC__SATA_PHY_TMS (_MX6Q_PAD_ENET_MDC__SATA_PHY_TMS)
-#define MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET (_MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET)
-
-#define MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 (_MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40)
-#define MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 (_MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41)
-#define MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 (_MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42)
-#define MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 (_MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43)
-#define MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 (_MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44)
-#define MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 (_MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45)
-#define MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 (_MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46)
-#define MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 (_MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47)
-
-#define MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 (_MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5)
-#define MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 (_MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5)
-
-#define MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 (_MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32)
-#define MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 (_MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33)
-#define MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 (_MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34)
-#define MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 (_MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35)
-#define MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 (_MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36)
-#define MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 (_MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37)
-#define MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 (_MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38)
-#define MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 (_MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39)
-#define MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 (_MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4)
-#define MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 (_MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4)
-#define MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 (_MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24)
-#define MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 (_MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25)
-#define MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 (_MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26)
-#define MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 (_MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27)
-#define MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 (_MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28)
-#define MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 (_MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29)
-#define MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 (_MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3)
-#define MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 (_MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30)
-#define MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 (_MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31)
-#define MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 (_MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3)
-#define MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 (_MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16)
-#define MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 (_MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17)
-#define MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 (_MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18)
-#define MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 (_MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19)
-#define MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 (_MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20)
-#define MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 (_MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21)
-#define MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 (_MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22)
-#define MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 (_MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2)
-#define MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 (_MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23)
-#define MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 (_MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2)
-#define MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 (_MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0)
-#define MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 (_MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1)
-#define MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 (_MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2)
-#define MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 (_MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3)
-#define MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 (_MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4)
-#define MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 (_MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5)
-#define MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 (_MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6)
-#define MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 (_MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7)
-#define MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 (_MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8)
-#define MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 (_MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9)
-#define MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 (_MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10)
-#define MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 (_MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11)
-#define MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 (_MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12)
-#define MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 (_MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13)
-#define MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 (_MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14)
-#define MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 (_MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15)
-#define MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS (_MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS)
-#define MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 (_MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0)
-#define MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 (_MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1)
-#define MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS (_MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS)
-#define MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET (_MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET)
-#define MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 (_MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0)
-#define MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 (_MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1)
-#define MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 (_MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0)
-#define MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 (_MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2)
-#define MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 (_MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0)
-#define MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 (_MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1)
-#define MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 (_MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1)
-#define MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 (_MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0)
-#define MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 (_MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1)
-#define MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE (_MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE)
-#define MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 (_MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0)
-#define MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 (_MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1)
-#define MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 (_MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2)
-#define MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 (_MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3)
-#define MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 (_MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4)
-#define MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 (_MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5)
-#define MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 (_MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0)
-#define MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 (_MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6)
-#define MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 (_MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7)
-#define MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 (_MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0)
-#define MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 (_MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8)
-#define MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 (_MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9)
-#define MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 (_MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10)
-#define MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 (_MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11)
-#define MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 (_MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12)
-#define MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 (_MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13)
-#define MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 (_MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14)
-#define MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 (_MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1)
-#define MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 (_MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15)
-#define MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 (_MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1)
-#define MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 (_MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48)
-#define MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 (_MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49)
-#define MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 (_MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50)
-#define MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 (_MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51)
-#define MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 (_MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52)
-#define MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 (_MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53)
-#define MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 (_MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54)
-#define MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 (_MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55)
-#define MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 (_MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6)
-#define MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 (_MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6)
-#define MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 (_MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56)
-#define MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 (_MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7)
-#define MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 (_MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57)
-#define MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 (_MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58)
-#define MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 (_MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59)
-#define MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 (_MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60)
-#define MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 (_MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7)
-#define MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 (_MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61)
-#define MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 (_MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62)
-#define MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 (_MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63)
-
-#define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK (_MX6Q_PAD_KEY_COL0__ECSPI1_SCLK)
-#define MX6Q_PAD_KEY_COL0__ENET_RDATA_3 (_MX6Q_PAD_KEY_COL0__ENET_RDATA_3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC (_MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC)
-#define MX6Q_PAD_KEY_COL0__KPP_COL_0 (_MX6Q_PAD_KEY_COL0__KPP_COL_0)
-#define MX6Q_PAD_KEY_COL0__UART4_TXD (_MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_KEY_COL0__UART4_RXD (_MX6Q_PAD_KEY_COL0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_KEY_COL0__GPIO_4_6 (_MX6Q_PAD_KEY_COL0__GPIO_4_6)
-#define MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT (_MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT)
-#define MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST (_MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST)
-
-#define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI (_MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI)
-#define MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 (_MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD (_MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD)
-#define MX6Q_PAD_KEY_ROW0__KPP_ROW_0 (_MX6Q_PAD_KEY_ROW0__KPP_ROW_0)
-#define MX6Q_PAD_KEY_ROW0__UART4_TXD (_MX6Q_PAD_KEY_ROW0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_KEY_ROW0__UART4_RXD (_MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_KEY_ROW0__GPIO_4_7 (_MX6Q_PAD_KEY_ROW0__GPIO_4_7)
-#define MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT (_MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT)
-#define MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 (_MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0)
-
-#define MX6Q_PAD_KEY_COL1__ECSPI1_MISO (_MX6Q_PAD_KEY_COL1__ECSPI1_MISO)
-#define MX6Q_PAD_KEY_COL1__ENET_MDIO (_MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS (_MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS)
-#define MX6Q_PAD_KEY_COL1__KPP_COL_1 (_MX6Q_PAD_KEY_COL1__KPP_COL_1)
-#define MX6Q_PAD_KEY_COL1__UART5_TXD (_MX6Q_PAD_KEY_COL1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_KEY_COL1__UART5_RXD (_MX6Q_PAD_KEY_COL1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_KEY_COL1__GPIO_4_8 (_MX6Q_PAD_KEY_COL1__GPIO_4_8)
-#define MX6Q_PAD_KEY_COL1__USDHC1_VSELECT (_MX6Q_PAD_KEY_COL1__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 (_MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1)
-
-#define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 (_MX6Q_PAD_KEY_ROW1__ECSPI1_SS0)
-#define MX6Q_PAD_KEY_ROW1__ENET_COL (_MX6Q_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD (_MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD)
-#define MX6Q_PAD_KEY_ROW1__KPP_ROW_1 (_MX6Q_PAD_KEY_ROW1__KPP_ROW_1)
-#define MX6Q_PAD_KEY_ROW1__UART5_TXD (_MX6Q_PAD_KEY_ROW1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_KEY_ROW1__UART5_RXD (_MX6Q_PAD_KEY_ROW1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_KEY_ROW1__GPIO_4_9 (_MX6Q_PAD_KEY_ROW1__GPIO_4_9)
-#define MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT (_MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 (_MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2)
-
-#define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 (_MX6Q_PAD_KEY_COL2__ECSPI1_SS1)
-#define MX6Q_PAD_KEY_COL2__ENET_RDATA_2 (_MX6Q_PAD_KEY_COL2__ENET_RDATA_2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_KEY_COL2__CAN1_TXCAN (_MX6Q_PAD_KEY_COL2__CAN1_TXCAN)
-#define MX6Q_PAD_KEY_COL2__KPP_COL_2 (_MX6Q_PAD_KEY_COL2__KPP_COL_2)
-#define MX6Q_PAD_KEY_COL2__ENET_MDC (_MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_KEY_COL2__GPIO_4_10 (_MX6Q_PAD_KEY_COL2__GPIO_4_10)
-#define MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP (_MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP)
-#define MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 (_MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3)
-
-#define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 (_MX6Q_PAD_KEY_ROW2__ECSPI1_SS2)
-#define MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 (_MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_KEY_ROW2__CAN1_RXCAN (_MX6Q_PAD_KEY_ROW2__CAN1_RXCAN)
-#define MX6Q_PAD_KEY_ROW2__KPP_ROW_2 (_MX6Q_PAD_KEY_ROW2__KPP_ROW_2)
-#define MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT (_MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_KEY_ROW2__GPIO_4_11 (_MX6Q_PAD_KEY_ROW2__GPIO_4_11)
-#define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE (_MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE)
-#define MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 (_MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4)
-
-#define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 (_MX6Q_PAD_KEY_COL3__ECSPI1_SS3)
-#define MX6Q_PAD_KEY_COL3__ENET_CRS (_MX6Q_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL (_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL)
-#define MX6Q_PAD_KEY_COL3__KPP_COL_3 (_MX6Q_PAD_KEY_COL3__KPP_COL_3)
-#define MX6Q_PAD_KEY_COL3__I2C2_SCL (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define MX6Q_PAD_KEY_COL3__GPIO_4_12 (_MX6Q_PAD_KEY_COL3__GPIO_4_12)
-#define MX6Q_PAD_KEY_COL3__SPDIF_IN1 (_MX6Q_PAD_KEY_COL3__SPDIF_IN1)
-#define MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 (_MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5)
-
-#define MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT (_MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT)
-#define MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK (_MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK)
-#define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA (_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA)
-#define MX6Q_PAD_KEY_ROW3__KPP_ROW_3 (_MX6Q_PAD_KEY_ROW3__KPP_ROW_3)
-#define MX6Q_PAD_KEY_ROW3__I2C2_SDA (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define MX6Q_PAD_KEY_ROW3__GPIO_4_13 (_MX6Q_PAD_KEY_ROW3__GPIO_4_13)
-#define MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT (_MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 (_MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6)
-
-#define MX6Q_PAD_KEY_COL4__CAN2_TXCAN (_MX6Q_PAD_KEY_COL4__CAN2_TXCAN)
-#define MX6Q_PAD_KEY_COL4__IPU1_SISG_4 (_MX6Q_PAD_KEY_COL4__IPU1_SISG_4)
-#define MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC (_MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC)
-#define MX6Q_PAD_KEY_COL4__KPP_COL_4 (_MX6Q_PAD_KEY_COL4__KPP_COL_4)
-#define MX6Q_PAD_KEY_COL4__UART5_CTS (_MX6Q_PAD_KEY_COL4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_KEY_COL4__UART5_RTS (_MX6Q_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_KEY_COL4__GPIO_4_14 (_MX6Q_PAD_KEY_COL4__GPIO_4_14)
-#define MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 (_MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49)
-#define MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 (_MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7)
-
-#define MX6Q_PAD_KEY_ROW4__CAN2_RXCAN (_MX6Q_PAD_KEY_ROW4__CAN2_RXCAN)
-#define MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 (_MX6Q_PAD_KEY_ROW4__IPU1_SISG_5)
-#define MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR (_MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR)
-#define MX6Q_PAD_KEY_ROW4__KPP_ROW_4 (_MX6Q_PAD_KEY_ROW4__KPP_ROW_4)
-#define MX6Q_PAD_KEY_ROW4__UART5_CTS (_MX6Q_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_KEY_ROW4__GPIO_4_15 (_MX6Q_PAD_KEY_ROW4__GPIO_4_15)
-#define MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 (_MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50)
-#define MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 (_MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8)
-
-#define MX6Q_PAD_GPIO_0__CCM_CLKO (_MX6Q_PAD_GPIO_0__CCM_CLKO)
-#define MX6Q_PAD_GPIO_0__KPP_COL_5 (_MX6Q_PAD_GPIO_0__KPP_COL_5)
-#define MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK (_MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK)
-#define MX6Q_PAD_GPIO_0__EPIT1_EPITO (_MX6Q_PAD_GPIO_0__EPIT1_EPITO)
-#define MX6Q_PAD_GPIO_0__GPIO_1_0 (_MX6Q_PAD_GPIO_0__GPIO_1_0)
-#define MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR (_MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR)
-#define MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 (_MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5)
-
-#define MX6Q_PAD_GPIO_1__ESAI1_SCKR (_MX6Q_PAD_GPIO_1__ESAI1_SCKR)
-#define MX6Q_PAD_GPIO_1__WDOG2_WDOG_B (_MX6Q_PAD_GPIO_1__WDOG2_WDOG_B)
-#define MX6Q_PAD_GPIO_1__KPP_ROW_5 (_MX6Q_PAD_GPIO_1__KPP_ROW_5)
-#define MX6Q_PAD_GPIO_1__PWM2_PWMO (_MX6Q_PAD_GPIO_1__PWM2_PWMO)
-#define MX6Q_PAD_GPIO_1__GPIO_1_1 (_MX6Q_PAD_GPIO_1__GPIO_1_1)
-#define MX6Q_PAD_GPIO_1__USDHC1_CD (_MX6Q_PAD_GPIO_1__USDHC1_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_GPIO_1__SRC_TESTER_ACK (_MX6Q_PAD_GPIO_1__SRC_TESTER_ACK)
-
-#define MX6Q_PAD_GPIO_9__ESAI1_FSR (_MX6Q_PAD_GPIO_9__ESAI1_FSR)
-#define MX6Q_PAD_GPIO_9__WDOG1_WDOG_B (_MX6Q_PAD_GPIO_9__WDOG1_WDOG_B)
-#define MX6Q_PAD_GPIO_9__KPP_COL_6 (_MX6Q_PAD_GPIO_9__KPP_COL_6)
-#define MX6Q_PAD_GPIO_9__CCM_REF_EN_B (_MX6Q_PAD_GPIO_9__CCM_REF_EN_B)
-#define MX6Q_PAD_GPIO_9__PWM1_PWMO (_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(MX6Q_PWM_PAD_CTRL))
-#define MX6Q_PAD_GPIO_9__GPIO_1_9 (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
-#define MX6Q_PAD_GPIO_9__USDHC1_WP (_MX6Q_PAD_GPIO_9__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_GPIO_9__SRC_EARLY_RST (_MX6Q_PAD_GPIO_9__SRC_EARLY_RST)
-
-#define MX6Q_PAD_GPIO_3__ESAI1_HCKR (_MX6Q_PAD_GPIO_3__ESAI1_HCKR)
-#define MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 (_MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0)
-#define MX6Q_PAD_GPIO_3__I2C3_SCL (_MX6Q_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT (_MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT)
-#define MX6Q_PAD_GPIO_3__CCM_CLKO2 (_MX6Q_PAD_GPIO_3__CCM_CLKO2)
-#define MX6Q_PAD_GPIO_3__GPIO_1_3 (_MX6Q_PAD_GPIO_3__GPIO_1_3)
-#define MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC (_MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC)
-#define MX6Q_PAD_GPIO_3__MLB_MLBCLK (_MX6Q_PAD_GPIO_3__MLB_MLBCLK)
-
-#define MX6Q_PAD_GPIO_6__ESAI1_SCKT (_MX6Q_PAD_GPIO_6__ESAI1_SCKT)
-#define MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1)
-#define MX6Q_PAD_GPIO_6__I2C3_SDA (_MX6Q_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 (_MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0)
-#define MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB (_MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB)
-#define MX6Q_PAD_GPIO_6__GPIO_1_6 (_MX6Q_PAD_GPIO_6__GPIO_1_6)
-#define MX6Q_PAD_GPIO_6__USDHC2_LCTL (_MX6Q_PAD_GPIO_6__USDHC2_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_GPIO_6__MLB_MLBSIG (_MX6Q_PAD_GPIO_6__MLB_MLBSIG)
-
-#define MX6Q_PAD_GPIO_2__ESAI1_FST (_MX6Q_PAD_GPIO_2__ESAI1_FST)
-#define MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 (_MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2)
-#define MX6Q_PAD_GPIO_2__KPP_ROW_6 (_MX6Q_PAD_GPIO_2__KPP_ROW_6)
-#define MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 (_MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1)
-#define MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 (_MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0)
-#define MX6Q_PAD_GPIO_2__GPIO_1_2 (_MX6Q_PAD_GPIO_2__GPIO_1_2)
-#define MX6Q_PAD_GPIO_2__USDHC2_WP (_MX6Q_PAD_GPIO_2__USDHC2_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_GPIO_2__MLB_MLBDAT (_MX6Q_PAD_GPIO_2__MLB_MLBDAT)
-
-#define MX6Q_PAD_GPIO_4__ESAI1_HCKT (_MX6Q_PAD_GPIO_4__ESAI1_HCKT)
-#define MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 (_MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3)
-#define MX6Q_PAD_GPIO_4__KPP_COL_7 (_MX6Q_PAD_GPIO_4__KPP_COL_7)
-#define MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 (_MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2)
-#define MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 (_MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1)
-#define MX6Q_PAD_GPIO_4__GPIO_1_4 (_MX6Q_PAD_GPIO_4__GPIO_1_4)
-#define MX6Q_PAD_GPIO_4__USDHC2_CD (_MX6Q_PAD_GPIO_4__USDHC2_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED (_MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED)
-
-#define MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 (_MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3)
-#define MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 (_MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4)
-#define MX6Q_PAD_GPIO_5__KPP_ROW_7 (_MX6Q_PAD_GPIO_5__KPP_ROW_7)
-#define MX6Q_PAD_GPIO_5__CCM_CLKO (_MX6Q_PAD_GPIO_5__CCM_CLKO)
-#define MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 (_MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2)
-#define MX6Q_PAD_GPIO_5__GPIO_1_5 (_MX6Q_PAD_GPIO_5__GPIO_1_5)
-#define MX6Q_PAD_GPIO_5__I2C3_SCL (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define MX6Q_PAD_GPIO_5__CHEETAH_EVENTI (_MX6Q_PAD_GPIO_5__CHEETAH_EVENTI)
-
-#define MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 (_MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1)
-#define MX6Q_PAD_GPIO_7__ECSPI5_RDY (_MX6Q_PAD_GPIO_7__ECSPI5_RDY)
-#define MX6Q_PAD_GPIO_7__EPIT1_EPITO (_MX6Q_PAD_GPIO_7__EPIT1_EPITO)
-#define MX6Q_PAD_GPIO_7__CAN1_TXCAN (_MX6Q_PAD_GPIO_7__CAN1_TXCAN)
-#define MX6Q_PAD_GPIO_7__UART2_TXD (_MX6Q_PAD_GPIO_7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_GPIO_7__UART2_RXD (_MX6Q_PAD_GPIO_7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_GPIO_7__GPIO_1_7 (_MX6Q_PAD_GPIO_7__GPIO_1_7)
-#define MX6Q_PAD_GPIO_7__SPDIF_PLOCK (_MX6Q_PAD_GPIO_7__SPDIF_PLOCK)
-#define MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE (_MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE)
-
-#define MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 (_MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0)
-#define MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT (_MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT)
-#define MX6Q_PAD_GPIO_8__EPIT2_EPITO (_MX6Q_PAD_GPIO_8__EPIT2_EPITO)
-#define MX6Q_PAD_GPIO_8__CAN1_RXCAN (_MX6Q_PAD_GPIO_8__CAN1_RXCAN)
-#define MX6Q_PAD_GPIO_8__UART2_TXD (_MX6Q_PAD_GPIO_8__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_GPIO_8__UART2_RXD (_MX6Q_PAD_GPIO_8__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_GPIO_8__GPIO_1_8 (_MX6Q_PAD_GPIO_8__GPIO_1_8)
-#define MX6Q_PAD_GPIO_8__SPDIF_SRCLK (_MX6Q_PAD_GPIO_8__SPDIF_SRCLK)
-#define MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP (_MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP)
-
-#define MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 (_MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2)
-#define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN (_MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN)
-#define MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT (_MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT)
-#define MX6Q_PAD_GPIO_16__USDHC1_LCTL (_MX6Q_PAD_GPIO_16__USDHC1_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_GPIO_16__SPDIF_IN1 (_MX6Q_PAD_GPIO_16__SPDIF_IN1)
-#define MX6Q_PAD_GPIO_16__GPIO_7_11 (_MX6Q_PAD_GPIO_16__GPIO_7_11)
-#define MX6Q_PAD_GPIO_16__I2C3_SDA (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define MX6Q_PAD_GPIO_16__SJC_DE_B (_MX6Q_PAD_GPIO_16__SJC_DE_B)
-
-#define MX6Q_PAD_GPIO_17__ESAI1_TX0 (_MX6Q_PAD_GPIO_17__ESAI1_TX0)
-#define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN (_MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN)
-#define MX6Q_PAD_GPIO_17__CCM_PMIC_RDY (_MX6Q_PAD_GPIO_17__CCM_PMIC_RDY)
-#define MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 (_MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0)
-#define MX6Q_PAD_GPIO_17__SPDIF_OUT1 (_MX6Q_PAD_GPIO_17__SPDIF_OUT1)
-#define MX6Q_PAD_GPIO_17__GPIO_7_12 (_MX6Q_PAD_GPIO_17__GPIO_7_12)
-#define MX6Q_PAD_GPIO_17__SJC_JTAG_ACT (_MX6Q_PAD_GPIO_17__SJC_JTAG_ACT)
-
-#define MX6Q_PAD_GPIO_18__ESAI1_TX1 (_MX6Q_PAD_GPIO_18__ESAI1_TX1)
-#define MX6Q_PAD_GPIO_18__ENET_RX_CLK (_MX6Q_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_GPIO_18__USDHC3_VSELECT (_MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 (_MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1)
-#define MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK (_MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK)
-#define MX6Q_PAD_GPIO_18__GPIO_7_13 (_MX6Q_PAD_GPIO_18__GPIO_7_13)
-#define MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL (_MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL)
-#define MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST (_MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST)
-
-#define MX6Q_PAD_GPIO_19__KPP_COL_5 (_MX6Q_PAD_GPIO_19__KPP_COL_5)
-#define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT (_MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT)
-#define MX6Q_PAD_GPIO_19__SPDIF_OUT1 (_MX6Q_PAD_GPIO_19__SPDIF_OUT1)
-#define MX6Q_PAD_GPIO_19__CCM_CLKO (_MX6Q_PAD_GPIO_19__CCM_CLKO)
-#define MX6Q_PAD_GPIO_19__ECSPI1_RDY (_MX6Q_PAD_GPIO_19__ECSPI1_RDY)
-#define MX6Q_PAD_GPIO_19__GPIO_4_5 (_MX6Q_PAD_GPIO_19__GPIO_4_5)
-#define MX6Q_PAD_GPIO_19__ENET_TX_ER (_MX6Q_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
-#define MX6Q_PAD_GPIO_19__SRC_INT_BOOT (_MX6Q_PAD_GPIO_19__SRC_INT_BOOT)
-
-#define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK (_MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK)
-#define MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 (_MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12)
-#define MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 (_MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0)
-#define MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 (_MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18)
-#define MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 (_MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29)
-#define MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO (_MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO)
-
-#define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC (_MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC)
-#define MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 (_MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13)
-#define MX6Q_PAD_CSI0_MCLK__CCM_CLKO (_MX6Q_PAD_CSI0_MCLK__CCM_CLKO)
-#define MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 (_MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1)
-#define MX6Q_PAD_CSI0_MCLK__GPIO_5_19 (_MX6Q_PAD_CSI0_MCLK__GPIO_5_19)
-#define MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 (_MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30)
-#define MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL (_MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL)
-
-#define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN (_MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN)
-#define MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 (_MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0)
-#define MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 (_MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14)
-#define MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 (_MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2)
-#define MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 (_MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20)
-#define MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 (_MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31)
-#define MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK (_MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK)
-
-#define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC (_MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC)
-#define MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 (_MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1)
-#define MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 (_MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15)
-#define MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 (_MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3)
-#define MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 (_MX6Q_PAD_CSI0_VSYNC__GPIO_5_21)
-#define MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 (_MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32)
-#define MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 (_MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0)
-
-#define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 (_MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4)
-#define MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 (_MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2)
-#define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK (_MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK)
-#define MX6Q_PAD_CSI0_DAT4__KPP_COL_5 (_MX6Q_PAD_CSI0_DAT4__KPP_COL_5)
-#define MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC (_MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC)
-#define MX6Q_PAD_CSI0_DAT4__GPIO_5_22 (_MX6Q_PAD_CSI0_DAT4__GPIO_5_22)
-#define MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 (_MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43)
-#define MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 (_MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1)
-
-#define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 (_MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5)
-#define MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 (_MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3)
-#define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI (_MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI)
-#define MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 (_MX6Q_PAD_CSI0_DAT5__KPP_ROW_5)
-#define MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD (_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD)
-#define MX6Q_PAD_CSI0_DAT5__GPIO_5_23 (_MX6Q_PAD_CSI0_DAT5__GPIO_5_23)
-#define MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 (_MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44)
-#define MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 (_MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2)
-
-#define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 (_MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6)
-#define MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 (_MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4)
-#define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO (_MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO)
-#define MX6Q_PAD_CSI0_DAT6__KPP_COL_6 (_MX6Q_PAD_CSI0_DAT6__KPP_COL_6)
-#define MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS (_MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS)
-#define MX6Q_PAD_CSI0_DAT6__GPIO_5_24 (_MX6Q_PAD_CSI0_DAT6__GPIO_5_24)
-#define MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 (_MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45)
-#define MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 (_MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3)
-
-#define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 (_MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7)
-#define MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 (_MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5)
-#define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 (_MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0)
-#define MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 (_MX6Q_PAD_CSI0_DAT7__KPP_ROW_6)
-#define MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD (_MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD)
-#define MX6Q_PAD_CSI0_DAT7__GPIO_5_25 (_MX6Q_PAD_CSI0_DAT7__GPIO_5_25)
-#define MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 (_MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46)
-#define MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 (_MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4)
-
-#define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 (_MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8)
-#define MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 (_MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6)
-#define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK (_MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK)
-#define MX6Q_PAD_CSI0_DAT8__KPP_COL_7 (_MX6Q_PAD_CSI0_DAT8__KPP_COL_7)
-#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA (_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT8__GPIO_5_26 (_MX6Q_PAD_CSI0_DAT8__GPIO_5_26)
-#define MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 (_MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47)
-#define MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 (_MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5)
-
-#define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 (_MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9)
-#define MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 (_MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7)
-#define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI (_MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI)
-#define MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 (_MX6Q_PAD_CSI0_DAT9__KPP_ROW_7)
-#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL (_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT9__GPIO_5_27 (_MX6Q_PAD_CSI0_DAT9__GPIO_5_27)
-#define MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 (_MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48)
-#define MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 (_MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6)
-
-#define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 (_MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10)
-#define MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC (_MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC)
-#define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO (_MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO)
-#define MX6Q_PAD_CSI0_DAT10__UART1_TXD (_MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT10__UART1_RXD (_MX6Q_PAD_CSI0_DAT10__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 (_MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4)
-#define MX6Q_PAD_CSI0_DAT10__GPIO_5_28 (_MX6Q_PAD_CSI0_DAT10__GPIO_5_28)
-#define MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 (_MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33)
-#define MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 (_MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7)
-
-#define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 (_MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11)
-#define MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS (_MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS)
-#define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 (_MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0)
-#define MX6Q_PAD_CSI0_DAT11__UART1_TXD (_MX6Q_PAD_CSI0_DAT11__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT11__UART1_RXD (_MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 (_MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5)
-#define MX6Q_PAD_CSI0_DAT11__GPIO_5_29 (_MX6Q_PAD_CSI0_DAT11__GPIO_5_29)
-#define MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 (_MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34)
-#define MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 (_MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8)
-
-#define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 (_MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12)
-#define MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 (_MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8)
-#define MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 (_MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16)
-#define MX6Q_PAD_CSI0_DAT12__UART4_TXD (_MX6Q_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT12__UART4_RXD (_MX6Q_PAD_CSI0_DAT12__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 (_MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6)
-#define MX6Q_PAD_CSI0_DAT12__GPIO_5_30 (_MX6Q_PAD_CSI0_DAT12__GPIO_5_30)
-#define MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 (_MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35)
-#define MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 (_MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9)
-
-#define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 (_MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13)
-#define MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 (_MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9)
-#define MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 (_MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17)
-#define MX6Q_PAD_CSI0_DAT13__UART4_TXD (_MX6Q_PAD_CSI0_DAT13__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT13__UART4_RXD (_MX6Q_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 (_MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7)
-#define MX6Q_PAD_CSI0_DAT13__GPIO_5_31 (_MX6Q_PAD_CSI0_DAT13__GPIO_5_31)
-#define MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 (_MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36)
-#define MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 (_MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10)
-
-#define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 (_MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14)
-#define MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 (_MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10)
-#define MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 (_MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18)
-#define MX6Q_PAD_CSI0_DAT14__UART5_TXD (_MX6Q_PAD_CSI0_DAT14__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT14__UART5_RXD (_MX6Q_PAD_CSI0_DAT14__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 (_MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8)
-#define MX6Q_PAD_CSI0_DAT14__GPIO_6_0 (_MX6Q_PAD_CSI0_DAT14__GPIO_6_0)
-#define MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 (_MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37)
-#define MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 (_MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11)
-
-#define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 (_MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15)
-#define MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 (_MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11)
-#define MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 (_MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19)
-#define MX6Q_PAD_CSI0_DAT15__UART5_TXD (_MX6Q_PAD_CSI0_DAT15__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT15__UART5_RXD (_MX6Q_PAD_CSI0_DAT15__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 (_MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9)
-#define MX6Q_PAD_CSI0_DAT15__GPIO_6_1 (_MX6Q_PAD_CSI0_DAT15__GPIO_6_1)
-#define MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 (_MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38)
-#define MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 (_MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12)
-
-#define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 (_MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16)
-#define MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 (_MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12)
-#define MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 (_MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20)
-#define MX6Q_PAD_CSI0_DAT16__UART4_CTS (_MX6Q_PAD_CSI0_DAT16__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT16__UART4_RTS (_MX6Q_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 (_MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10)
-#define MX6Q_PAD_CSI0_DAT16__GPIO_6_2 (_MX6Q_PAD_CSI0_DAT16__GPIO_6_2)
-#define MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 (_MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39)
-#define MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 (_MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13)
-
-#define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 (_MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17)
-#define MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 (_MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13)
-#define MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 (_MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21)
-#define MX6Q_PAD_CSI0_DAT17__UART4_CTS (_MX6Q_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 (_MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11)
-#define MX6Q_PAD_CSI0_DAT17__GPIO_6_3 (_MX6Q_PAD_CSI0_DAT17__GPIO_6_3)
-#define MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 (_MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40)
-#define MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 (_MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14)
-
-#define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 (_MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18)
-#define MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 (_MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14)
-#define MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 (_MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22)
-#define MX6Q_PAD_CSI0_DAT18__UART5_CTS (_MX6Q_PAD_CSI0_DAT18__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT18__UART5_RTS (_MX6Q_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 (_MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12)
-#define MX6Q_PAD_CSI0_DAT18__GPIO_6_4 (_MX6Q_PAD_CSI0_DAT18__GPIO_6_4)
-#define MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 (_MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41)
-#define MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 (_MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15)
-
-#define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 (_MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19)
-#define MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 (_MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15)
-#define MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 (_MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23)
-#define MX6Q_PAD_CSI0_DAT19__UART5_CTS (_MX6Q_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 (_MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13)
-#define MX6Q_PAD_CSI0_DAT19__GPIO_6_5 (_MX6Q_PAD_CSI0_DAT19__GPIO_6_5)
-#define MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 (_MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42)
-#define MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 (_MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9)
-
-#define MX6Q_PAD_JTAG_TMS__SJC_TMS (_MX6Q_PAD_JTAG_TMS__SJC_TMS)
-
-#define MX6Q_PAD_JTAG_MOD__SJC_MOD (_MX6Q_PAD_JTAG_MOD__SJC_MOD)
-
-#define MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB (_MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB)
-
-#define MX6Q_PAD_JTAG_TDI__SJC_TDI (_MX6Q_PAD_JTAG_TDI__SJC_TDI)
-
-#define MX6Q_PAD_JTAG_TCK__SJC_TCK (_MX6Q_PAD_JTAG_TCK__SJC_TCK)
-
-#define MX6Q_PAD_JTAG_TDO__SJC_TDO (_MX6Q_PAD_JTAG_TDO__SJC_TDO)
-
-#define MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 (_MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3)
-
-#define MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 (_MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2)
-
-#define MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK (_MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK)
-
-#define MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 (_MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1)
-
-#define MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 (_MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0)
-
-#define MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 (_MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3)
-
-#define MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK (_MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK)
-
-#define MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 (_MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2)
-
-#define MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 (_MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1)
-
-#define MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 (_MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0)
-
-#define MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 (_MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1)
-
-#define MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM (_MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM)
-
-#define MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ (_MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ)
-
-#define MX6Q_PAD_POR_B__SRC_POR_B (_MX6Q_PAD_POR_B__SRC_POR_B)
-
-#define MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 (_MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1)
-
-#define MX6Q_PAD_RESET_IN_B__SRC_RESET_B (_MX6Q_PAD_RESET_IN_B__SRC_RESET_B)
-
-#define MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 (_MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0)
-
-#define MX6Q_PAD_TEST_MODE__TCU_TEST_MODE (_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE)
-
-#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT7__UART1_TXD (_MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT7__UART1_RXD (_MX6Q_PAD_SD3_DAT7__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 (_MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24)
-#define MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0)
-#define MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0)
-#define MX6Q_PAD_SD3_DAT7__GPIO_6_17 (_MX6Q_PAD_SD3_DAT7__GPIO_6_17)
-#define MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 (_MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12)
-#define MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV (_MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV)
-
-#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT6__UART1_TXD (_MX6Q_PAD_SD3_DAT6__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT6__UART1_RXD (_MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 (_MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25)
-#define MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1)
-#define MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1)
-#define MX6Q_PAD_SD3_DAT6__GPIO_6_18 (_MX6Q_PAD_SD3_DAT6__GPIO_6_18)
-#define MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 (_MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13)
-#define MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 (_MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10)
-
-#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT5__UART2_TXD (_MX6Q_PAD_SD3_DAT5__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT5__UART2_RXD (_MX6Q_PAD_SD3_DAT5__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 (_MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26)
-#define MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2)
-#define MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2)
-#define MX6Q_PAD_SD3_DAT5__GPIO_7_0 (_MX6Q_PAD_SD3_DAT5__GPIO_7_0)
-#define MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 (_MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14)
-#define MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 (_MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11)
-
-#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT4__UART2_TXD (_MX6Q_PAD_SD3_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT4__UART2_RXD (_MX6Q_PAD_SD3_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 (_MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27)
-#define MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3)
-#define MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3)
-#define MX6Q_PAD_SD3_DAT4__GPIO_7_1 (_MX6Q_PAD_SD3_DAT4__GPIO_7_1)
-#define MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 (_MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15)
-#define MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 (_MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12)
-
-#define MX6Q_PAD_SD3_CMD__USDHC3_CMD (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD3_CMD__UART2_CTS (_MX6Q_PAD_SD3_CMD__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_CMD__CAN1_TXCAN (_MX6Q_PAD_SD3_CMD__CAN1_TXCAN)
-#define MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 (_MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4)
-#define MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 (_MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4)
-#define MX6Q_PAD_SD3_CMD__GPIO_7_2 (_MX6Q_PAD_SD3_CMD__GPIO_7_2)
-#define MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 (_MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16)
-#define MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 (_MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13)
-
-#define MX6Q_PAD_SD3_CLK__USDHC3_CLK (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD3_CLK__UART2_CTS (_MX6Q_PAD_SD3_CLK__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_CLK__UART2_RTS (_MX6Q_PAD_SD3_CLK__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_CLK__CAN1_RXCAN (_MX6Q_PAD_SD3_CLK__CAN1_RXCAN)
-#define MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 (_MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5)
-#define MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 (_MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5)
-#define MX6Q_PAD_SD3_CLK__GPIO_7_3 (_MX6Q_PAD_SD3_CLK__GPIO_7_3)
-#define MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 (_MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17)
-#define MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 (_MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14)
-
-#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT0__UART1_CTS (_MX6Q_PAD_SD3_DAT0__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT0__CAN2_TXCAN (_MX6Q_PAD_SD3_DAT0__CAN2_TXCAN)
-#define MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6)
-#define MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6)
-#define MX6Q_PAD_SD3_DAT0__GPIO_7_4 (_MX6Q_PAD_SD3_DAT0__GPIO_7_4)
-#define MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 (_MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18)
-#define MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 (_MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15)
-
-#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT1__UART1_CTS (_MX6Q_PAD_SD3_DAT1__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT1__UART1_RTS (_MX6Q_PAD_SD3_DAT1__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT1__CAN2_RXCAN (_MX6Q_PAD_SD3_DAT1__CAN2_RXCAN)
-#define MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7)
-#define MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7)
-#define MX6Q_PAD_SD3_DAT1__GPIO_7_5 (_MX6Q_PAD_SD3_DAT1__GPIO_7_5)
-#define MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 (_MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19)
-#define MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 (_MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0)
-
-#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 (_MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28)
-#define MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8)
-#define MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8)
-#define MX6Q_PAD_SD3_DAT2__GPIO_7_6 (_MX6Q_PAD_SD3_DAT2__GPIO_7_6)
-#define MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 (_MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20)
-#define MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 (_MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1)
-
-#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT3__UART3_CTS (_MX6Q_PAD_SD3_DAT3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 (_MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29)
-#define MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9)
-#define MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9)
-#define MX6Q_PAD_SD3_DAT3__GPIO_7_7 (_MX6Q_PAD_SD3_DAT3__GPIO_7_7)
-#define MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 (_MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21)
-#define MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 (_MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2)
-
-#define MX6Q_PAD_SD3_RST__USDHC3_RST (_MX6Q_PAD_SD3_RST__USDHC3_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD3_RST__UART3_CTS (_MX6Q_PAD_SD3_RST__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_RST__UART3_RTS (_MX6Q_PAD_SD3_RST__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 (_MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30)
-#define MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 (_MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10)
-#define MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 (_MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10)
-#define MX6Q_PAD_SD3_RST__GPIO_7_8 (_MX6Q_PAD_SD3_RST__GPIO_7_8)
-#define MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 (_MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22)
-#define MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 (_MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3)
-
-#define MX6Q_PAD_NANDF_CLE__RAWNAND_CLE (_MX6Q_PAD_NANDF_CLE__RAWNAND_CLE)
-#define MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 (_MX6Q_PAD_NANDF_CLE__IPU2_SISG_4)
-#define MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 (_MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31)
-#define MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 (_MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11)
-#define MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 (_MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11)
-#define MX6Q_PAD_NANDF_CLE__GPIO_6_7 (_MX6Q_PAD_NANDF_CLE__GPIO_6_7)
-#define MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 (_MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23)
-#define MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 (_MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0)
-
-#define MX6Q_PAD_NANDF_ALE__RAWNAND_ALE (_MX6Q_PAD_NANDF_ALE__RAWNAND_ALE)
-#define MX6Q_PAD_NANDF_ALE__USDHC4_RST (_MX6Q_PAD_NANDF_ALE__USDHC4_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 (_MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0)
-#define MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 (_MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12)
-#define MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 (_MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12)
-#define MX6Q_PAD_NANDF_ALE__GPIO_6_8 (_MX6Q_PAD_NANDF_ALE__GPIO_6_8)
-#define MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 (_MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24)
-#define MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 (_MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1)
-
-#define MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN (_MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN)
-#define MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 (_MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5)
-#define MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 (_MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1)
-#define MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13)
-#define MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13)
-#define MX6Q_PAD_NANDF_WP_B__GPIO_6_9 (_MX6Q_PAD_NANDF_WP_B__GPIO_6_9)
-#define MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 (_MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32)
-#define MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 (_MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0)
-
-#define MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 (_MX6Q_PAD_NANDF_RB0__RAWNAND_READY0)
-#define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 (_MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1)
-#define MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 (_MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2)
-#define MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 (_MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14)
-#define MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 (_MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14)
-#define MX6Q_PAD_NANDF_RB0__GPIO_6_10 (_MX6Q_PAD_NANDF_RB0__GPIO_6_10)
-#define MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 (_MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33)
-#define MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 (_MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1)
-
-#define MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N (_MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N)
-#define MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 (_MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15)
-#define MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 (_MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15)
-#define MX6Q_PAD_NANDF_CS0__GPIO_6_11 (_MX6Q_PAD_NANDF_CS0__GPIO_6_11)
-#define MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 (_MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2)
-
-#define MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N (_MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N)
-#define MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT (_MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT (_MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 (_MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3)
-#define MX6Q_PAD_NANDF_CS1__GPIO_6_14 (_MX6Q_PAD_NANDF_CS1__GPIO_6_14)
-#define MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT (_MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT)
-
-#define MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N (_MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N)
-#define MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 (_MX6Q_PAD_NANDF_CS2__IPU1_SISG_0)
-#define MX6Q_PAD_NANDF_CS2__ESAI1_TX0 (_MX6Q_PAD_NANDF_CS2__ESAI1_TX0)
-#define MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE (_MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE)
-#define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 (_MX6Q_PAD_NANDF_CS2__CCM_CLKO2)
-#define MX6Q_PAD_NANDF_CS2__GPIO_6_15 (_MX6Q_PAD_NANDF_CS2__GPIO_6_15)
-#define MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 (_MX6Q_PAD_NANDF_CS2__IPU2_SISG_0)
-
-#define MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N (_MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N)
-#define MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 (_MX6Q_PAD_NANDF_CS3__IPU1_SISG_1)
-#define MX6Q_PAD_NANDF_CS3__ESAI1_TX1 (_MX6Q_PAD_NANDF_CS3__ESAI1_TX1)
-#define MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 (_MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26)
-#define MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 (_MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4)
-#define MX6Q_PAD_NANDF_CS3__GPIO_6_16 (_MX6Q_PAD_NANDF_CS3__GPIO_6_16)
-#define MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 (_MX6Q_PAD_NANDF_CS3__IPU2_SISG_1)
-#define MX6Q_PAD_NANDF_CS3__TPSMP_CLK (_MX6Q_PAD_NANDF_CS3__TPSMP_CLK)
-
-#define MX6Q_PAD_SD4_CMD__USDHC4_CMD (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD4_CMD__RAWNAND_RDN (_MX6Q_PAD_SD4_CMD__RAWNAND_RDN)
-#define MX6Q_PAD_SD4_CMD__UART3_TXD (_MX6Q_PAD_SD4_CMD__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD4_CMD__UART3_RXD (_MX6Q_PAD_SD4_CMD__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 (_MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5)
-#define MX6Q_PAD_SD4_CMD__GPIO_7_9 (_MX6Q_PAD_SD4_CMD__GPIO_7_9)
-#define MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR (_MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR)
-
-#define MX6Q_PAD_SD4_CLK__USDHC4_CLK (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD4_CLK__RAWNAND_WRN (_MX6Q_PAD_SD4_CLK__RAWNAND_WRN)
-#define MX6Q_PAD_SD4_CLK__UART3_TXD (_MX6Q_PAD_SD4_CLK__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD4_CLK__UART3_RXD (_MX6Q_PAD_SD4_CLK__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 (_MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6)
-#define MX6Q_PAD_SD4_CLK__GPIO_7_10 (_MX6Q_PAD_SD4_CLK__GPIO_7_10)
-
-#define MX6Q_PAD_NANDF_D0__RAWNAND_D0 (_MX6Q_PAD_NANDF_D0__RAWNAND_D0)
-#define MX6Q_PAD_NANDF_D0__USDHC1_DAT4 (_MX6Q_PAD_NANDF_D0__USDHC1_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 (_MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0)
-#define MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 (_MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16)
-#define MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 (_MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16)
-#define MX6Q_PAD_NANDF_D0__GPIO_2_0 (_MX6Q_PAD_NANDF_D0__GPIO_2_0)
-#define MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 (_MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0)
-#define MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 (_MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0)
-
-#define MX6Q_PAD_NANDF_D1__RAWNAND_D1 (_MX6Q_PAD_NANDF_D1__RAWNAND_D1)
-#define MX6Q_PAD_NANDF_D1__USDHC1_DAT5 (_MX6Q_PAD_NANDF_D1__USDHC1_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 (_MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1)
-#define MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 (_MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17)
-#define MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 (_MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17)
-#define MX6Q_PAD_NANDF_D1__GPIO_2_1 (_MX6Q_PAD_NANDF_D1__GPIO_2_1)
-#define MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 (_MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1)
-#define MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 (_MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1)
-
-#define MX6Q_PAD_NANDF_D2__RAWNAND_D2 (_MX6Q_PAD_NANDF_D2__RAWNAND_D2)
-#define MX6Q_PAD_NANDF_D2__USDHC1_DAT6 (_MX6Q_PAD_NANDF_D2__USDHC1_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 (_MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2)
-#define MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 (_MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18)
-#define MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 (_MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18)
-#define MX6Q_PAD_NANDF_D2__GPIO_2_2 (_MX6Q_PAD_NANDF_D2__GPIO_2_2)
-#define MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 (_MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2)
-#define MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 (_MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2)
-
-#define MX6Q_PAD_NANDF_D3__RAWNAND_D3 (_MX6Q_PAD_NANDF_D3__RAWNAND_D3)
-#define MX6Q_PAD_NANDF_D3__USDHC1_DAT7 (_MX6Q_PAD_NANDF_D3__USDHC1_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 (_MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3)
-#define MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 (_MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19)
-#define MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 (_MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19)
-#define MX6Q_PAD_NANDF_D3__GPIO_2_3 (_MX6Q_PAD_NANDF_D3__GPIO_2_3)
-#define MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 (_MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3)
-#define MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 (_MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3)
-
-#define MX6Q_PAD_NANDF_D4__RAWNAND_D4 (_MX6Q_PAD_NANDF_D4__RAWNAND_D4)
-#define MX6Q_PAD_NANDF_D4__USDHC2_DAT4 (_MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 (_MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4)
-#define MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 (_MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20)
-#define MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 (_MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20)
-#define MX6Q_PAD_NANDF_D4__GPIO_2_4 (_MX6Q_PAD_NANDF_D4__GPIO_2_4)
-#define MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 (_MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4)
-#define MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 (_MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4)
-
-#define MX6Q_PAD_NANDF_D5__RAWNAND_D5 (_MX6Q_PAD_NANDF_D5__RAWNAND_D5)
-#define MX6Q_PAD_NANDF_D5__USDHC2_DAT5 (_MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 (_MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5)
-#define MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 (_MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21)
-#define MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 (_MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21)
-#define MX6Q_PAD_NANDF_D5__GPIO_2_5 (_MX6Q_PAD_NANDF_D5__GPIO_2_5)
-#define MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 (_MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5)
-#define MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 (_MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5)
-
-#define MX6Q_PAD_NANDF_D6__RAWNAND_D6 (_MX6Q_PAD_NANDF_D6__RAWNAND_D6)
-#define MX6Q_PAD_NANDF_D6__USDHC2_DAT6 (_MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 (_MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6)
-#define MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 (_MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22)
-#define MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 (_MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22)
-#define MX6Q_PAD_NANDF_D6__GPIO_2_6 (_MX6Q_PAD_NANDF_D6__GPIO_2_6)
-#define MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 (_MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6)
-#define MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 (_MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6)
-
-#define MX6Q_PAD_NANDF_D7__RAWNAND_D7 (_MX6Q_PAD_NANDF_D7__RAWNAND_D7)
-#define MX6Q_PAD_NANDF_D7__USDHC2_DAT7 (_MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 (_MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7)
-#define MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 (_MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23)
-#define MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 (_MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23)
-#define MX6Q_PAD_NANDF_D7__GPIO_2_7 (_MX6Q_PAD_NANDF_D7__GPIO_2_7)
-#define MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 (_MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7)
-#define MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 (_MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7)
-
-#define MX6Q_PAD_SD4_DAT0__RAWNAND_D8 (_MX6Q_PAD_SD4_DAT0__RAWNAND_D8)
-#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD4_DAT0__RAWNAND_DQS (_MX6Q_PAD_SD4_DAT0__RAWNAND_DQS)
-#define MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 (_MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24)
-#define MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 (_MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24)
-#define MX6Q_PAD_SD4_DAT0__GPIO_2_8 (_MX6Q_PAD_SD4_DAT0__GPIO_2_8)
-#define MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 (_MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8)
-#define MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 (_MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8)
-
-#define MX6Q_PAD_SD4_DAT1__RAWNAND_D9 (_MX6Q_PAD_SD4_DAT1__RAWNAND_D9)
-#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD4_DAT1__PWM3_PWMO (_MX6Q_PAD_SD4_DAT1__PWM3_PWMO)
-#define MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 (_MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25)
-#define MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 (_MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25)
-#define MX6Q_PAD_SD4_DAT1__GPIO_2_9 (_MX6Q_PAD_SD4_DAT1__GPIO_2_9)
-#define MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 (_MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9)
-#define MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 (_MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9)
-
-#define MX6Q_PAD_SD4_DAT2__RAWNAND_D10 (_MX6Q_PAD_SD4_DAT2__RAWNAND_D10)
-#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD4_DAT2__PWM4_PWMO (_MX6Q_PAD_SD4_DAT2__PWM4_PWMO)
-#define MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 (_MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26)
-#define MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 (_MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26)
-#define MX6Q_PAD_SD4_DAT2__GPIO_2_10 (_MX6Q_PAD_SD4_DAT2__GPIO_2_10)
-#define MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 (_MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10)
-#define MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 (_MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10)
-
-#define MX6Q_PAD_SD4_DAT3__RAWNAND_D11 (_MX6Q_PAD_SD4_DAT3__RAWNAND_D11)
-#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 (_MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27)
-#define MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 (_MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27)
-#define MX6Q_PAD_SD4_DAT3__GPIO_2_11 (_MX6Q_PAD_SD4_DAT3__GPIO_2_11)
-#define MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 (_MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11)
-#define MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 (_MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11)
-
-#define MX6Q_PAD_SD4_DAT4__RAWNAND_D12 (_MX6Q_PAD_SD4_DAT4__RAWNAND_D12)
-#define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD4_DAT4__UART2_TXD (_MX6Q_PAD_SD4_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD4_DAT4__UART2_RXD (_MX6Q_PAD_SD4_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 (_MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28)
-#define MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 (_MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28)
-#define MX6Q_PAD_SD4_DAT4__GPIO_2_12 (_MX6Q_PAD_SD4_DAT4__GPIO_2_12)
-#define MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 (_MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12)
-#define MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 (_MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12)
-
-#define MX6Q_PAD_SD4_DAT5__RAWNAND_D13 (_MX6Q_PAD_SD4_DAT5__RAWNAND_D13)
-#define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD4_DAT5__UART2_CTS (_MX6Q_PAD_SD4_DAT5__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD4_DAT5__UART2_RTS (_MX6Q_PAD_SD4_DAT5__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 (_MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29)
-#define MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 (_MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29)
-#define MX6Q_PAD_SD4_DAT5__GPIO_2_13 (_MX6Q_PAD_SD4_DAT5__GPIO_2_13)
-#define MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 (_MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13)
-#define MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 (_MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13)
-
-#define MX6Q_PAD_SD4_DAT6__RAWNAND_D14 (_MX6Q_PAD_SD4_DAT6__RAWNAND_D14)
-#define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD4_DAT6__UART2_CTS (_MX6Q_PAD_SD4_DAT6__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 (_MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30)
-#define MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 (_MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30)
-#define MX6Q_PAD_SD4_DAT6__GPIO_2_14 (_MX6Q_PAD_SD4_DAT6__GPIO_2_14)
-#define MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 (_MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14)
-#define MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 (_MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14)
-
-#define MX6Q_PAD_SD4_DAT7__RAWNAND_D15 (_MX6Q_PAD_SD4_DAT7__RAWNAND_D15)
-#define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD4_DAT7__UART2_TXD (_MX6Q_PAD_SD4_DAT7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD4_DAT7__UART2_RXD (_MX6Q_PAD_SD4_DAT7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
-#define MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 (_MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31)
-#define MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 (_MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31)
-#define MX6Q_PAD_SD4_DAT7__GPIO_2_15 (_MX6Q_PAD_SD4_DAT7__GPIO_2_15)
-#define MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 (_MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15)
-#define MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 (_MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15)
-
-#define MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 (_MX6Q_PAD_SD1_DAT1__ECSPI5_SS0)
-#define MX6Q_PAD_SD1_DAT1__PWM3_PWMO (_MX6Q_PAD_SD1_DAT1__PWM3_PWMO)
-#define MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 (_MX6Q_PAD_SD1_DAT1__GPT_CAPIN2)
-#define MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 (_MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7)
-#define MX6Q_PAD_SD1_DAT1__GPIO_1_17 (_MX6Q_PAD_SD1_DAT1__GPIO_1_17)
-#define MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 (_MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0)
-#define MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 (_MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8)
-
-#define MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO (_MX6Q_PAD_SD1_DAT0__ECSPI5_MISO)
-#define MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS (_MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS)
-#define MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 (_MX6Q_PAD_SD1_DAT0__GPT_CAPIN1)
-#define MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 (_MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8)
-#define MX6Q_PAD_SD1_DAT0__GPIO_1_16 (_MX6Q_PAD_SD1_DAT0__GPIO_1_16)
-#define MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 (_MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1)
-#define MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 (_MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7)
-
-#define MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 (_MX6Q_PAD_SD1_DAT3__ECSPI5_SS2)
-#define MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 (_MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3)
-#define MX6Q_PAD_SD1_DAT3__PWM1_PWMO (_MX6Q_PAD_SD1_DAT3__PWM1_PWMO)
-#define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B)
-#define MX6Q_PAD_SD1_DAT3__GPIO_1_21 (_MX6Q_PAD_SD1_DAT3__GPIO_1_21)
-#define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB)
-#define MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 (_MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6)
-
-#define MX6Q_PAD_SD1_CMD__USDHC1_CMD (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI (_MX6Q_PAD_SD1_CMD__ECSPI5_MOSI)
-#define MX6Q_PAD_SD1_CMD__PWM4_PWMO (_MX6Q_PAD_SD1_CMD__PWM4_PWMO)
-#define MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 (_MX6Q_PAD_SD1_CMD__GPT_CMPOUT1)
-#define MX6Q_PAD_SD1_CMD__GPIO_1_18 (_MX6Q_PAD_SD1_CMD__GPIO_1_18)
-#define MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 (_MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5)
-
-#define MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 (_MX6Q_PAD_SD1_DAT2__ECSPI5_SS1)
-#define MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 (_MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2)
-#define MX6Q_PAD_SD1_DAT2__PWM2_PWMO (_MX6Q_PAD_SD1_DAT2__PWM2_PWMO)
-#define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B)
-#define MX6Q_PAD_SD1_DAT2__GPIO_1_19 (_MX6Q_PAD_SD1_DAT2__GPIO_1_19)
-#define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB)
-#define MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 (_MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4)
-
-#define MX6Q_PAD_SD1_CLK__USDHC1_CLK (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK (_MX6Q_PAD_SD1_CLK__ECSPI5_SCLK)
-#define MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT (_MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT)
-#define MX6Q_PAD_SD1_CLK__GPT_CLKIN (_MX6Q_PAD_SD1_CLK__GPT_CLKIN)
-#define MX6Q_PAD_SD1_CLK__GPIO_1_20 (_MX6Q_PAD_SD1_CLK__GPIO_1_20)
-#define MX6Q_PAD_SD1_CLK__PHY_DTB_0 (_MX6Q_PAD_SD1_CLK__PHY_DTB_0)
-#define MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 (_MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0)
-
-#define MX6Q_PAD_SD2_CLK__USDHC2_CLK (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK (_MX6Q_PAD_SD2_CLK__ECSPI5_SCLK)
-#define MX6Q_PAD_SD2_CLK__KPP_COL_5 (_MX6Q_PAD_SD2_CLK__KPP_COL_5)
-#define MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS (_MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS)
-#define MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 (_MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9)
-#define MX6Q_PAD_SD2_CLK__GPIO_1_10 (_MX6Q_PAD_SD2_CLK__GPIO_1_10)
-#define MX6Q_PAD_SD2_CLK__PHY_DTB_1 (_MX6Q_PAD_SD2_CLK__PHY_DTB_1)
-#define MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 (_MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1)
-
-#define MX6Q_PAD_SD2_CMD__USDHC2_CMD (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI (_MX6Q_PAD_SD2_CMD__ECSPI5_MOSI)
-#define MX6Q_PAD_SD2_CMD__KPP_ROW_5 (_MX6Q_PAD_SD2_CMD__KPP_ROW_5)
-#define MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC (_MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC)
-#define MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 (_MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10)
-#define MX6Q_PAD_SD2_CMD__GPIO_1_11 (_MX6Q_PAD_SD2_CMD__GPIO_1_11)
-
-#define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
-#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 (_MX6Q_PAD_SD2_DAT3__ECSPI5_SS3)
-#define MX6Q_PAD_SD2_DAT3__KPP_COL_6 (_MX6Q_PAD_SD2_DAT3__KPP_COL_6)
-#define MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC (_MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC)
-#define MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 (_MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11)
-#define MX6Q_PAD_SD2_DAT3__GPIO_1_12 (_MX6Q_PAD_SD2_DAT3__GPIO_1_12)
-#define MX6Q_PAD_SD2_DAT3__SJC_DONE (_MX6Q_PAD_SD2_DAT3__SJC_DONE)
-#define MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 (_MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3)
-
-#endif
+#endif /* __ASM_ARCH_IOMUX_MX6_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Auto Generate file, please don't edit it
+ *
+ */
+
+#ifndef __ASM_ARCH_IOMUX_MX6DL_H__
+#define __ASM_ARCH_IOMUX_MX6DL_H__
+
+#define MX6_PAD_CSI0_DAT10__IPU1_CSI0_D_10 IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x0360, 0x004C, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x0360, 0x004C, 2, 0x07F8, 0, 0)
+#define MX6_PAD_CSI0_DAT10__UART1_TXD IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT10__UART1_RXD IOMUX_PAD(0x0360, 0x004C, 3, 0x08FC, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x0360, 0x004C, 4, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT10__GPIO_5_28 IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT10__SIMBA_TRACE_7 IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11 IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x0364, 0x0050, 2, 0x0800, 0, 0)
+#define MX6_PAD_CSI0_DAT11__UART1_TXD IOMUX_PAD(0x0364, 0x0050, 3, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT11__UART1_RXD IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x0364, 0x0050, 4, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT11__GPIO_5_29 IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT11__SIMBA_TRACE_8 IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12 IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8 IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 IOMUX_PAD(0x0368, 0x0054, 2, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT12__UART4_TXD IOMUX_PAD(0x0368, 0x0054, 3, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT12__UART4_RXD IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x0368, 0x0054, 4, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT12__GPIO_5_30 IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT12__SIMBA_TRACE_9 IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13 IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9 IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 IOMUX_PAD(0x036C, 0x0058, 2, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT13__UART4_TXD IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT13__UART4_RXD IOMUX_PAD(0x036C, 0x0058, 3, 0x0914, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x036C, 0x0058, 4, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT13__GPIO_5_31 IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT13__SIMBA_TRACE_10 IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14 IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10 IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 IOMUX_PAD(0x0370, 0x005C, 2, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT14__UART5_TXD IOMUX_PAD(0x0370, 0x005C, 3, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT14__UART5_RXD IOMUX_PAD(0x0370, 0x005C, 3, 0x091C, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x0370, 0x005C, 4, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT14__GPIO_6_0 IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT14__SIMBA_TRACE_11 IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15 IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11 IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 IOMUX_PAD(0x0374, 0x0060, 2, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT15__UART5_TXD IOMUX_PAD(0x0374, 0x0060, 3, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT15__UART5_RXD IOMUX_PAD(0x0374, 0x0060, 3, 0x091C, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x0374, 0x0060, 4, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT15__GPIO_6_1 IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT15__SIMBA_TRACE_12 IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16 IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12 IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 IOMUX_PAD(0x0378, 0x0064, 2, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT16__UART4_CTS IOMUX_PAD(0x0378, 0x0064, 3, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x0378, 0x0064, 3, 0x0910, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x0378, 0x0064, 4, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT16__GPIO_6_2 IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT16__SIMBA_TRACE_13 IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17 IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13 IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 IOMUX_PAD(0x037C, 0x0068, 2, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x037C, 0x0068, 3, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT17__UART4_RTS IOMUX_PAD(0x037C, 0x0068, 3, 0x0910, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x037C, 0x0068, 4, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT17__GPIO_6_3 IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT17__SIMBA_TRACE_14 IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18 IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14 IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 IOMUX_PAD(0x0380, 0x006C, 2, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT18__UART5_CTS IOMUX_PAD(0x0380, 0x006C, 3, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x0380, 0x006C, 3, 0x0918, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x0380, 0x006C, 4, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT18__GPIO_6_4 IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT18__SIMBA_TRACE_15 IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19 IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15 IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 IOMUX_PAD(0x0384, 0x0070, 2, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x0384, 0x0070, 3, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT19__UART5_RTS IOMUX_PAD(0x0384, 0x0070, 3, 0x0918, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x0384, 0x0070, 4, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT19__GPIO_6_5 IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 IOMUX_PAD(0x0384, 0x0070, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4 IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2 IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x0388, 0x0074, 2, 0x07D8, 0, 0)
+#define MX6_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x0388, 0x0074, 3, 0x08C0, 0, 0)
+#define MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT4__GPIO_5_22 IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT4__SIMBA_TRACE_1 IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5 IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3 IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x038C, 0x0078, 2, 0x07E0, 0, 0)
+#define MX6_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x038C, 0x0078, 3, 0x08CC, 0, 0)
+#define MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, MX6_ADU_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT5__GPIO_5_23 IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT5__SIMBA_TRACE_2 IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6 IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4 IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x0390, 0x007C, 2, 0x07DC, 0, 0)
+#define MX6_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x0390, 0x007C, 3, 0x08C4, 0, 0)
+#define MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT6__GPIO_5_24 IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT6__SIMBA_TRACE_3 IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7 IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5 IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x0394, 0x0080, 2, 0x07E4, 0, 0)
+#define MX6_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x0394, 0x0080, 3, 0x08D0, 0, 0)
+#define MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, MX6_ADU_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT7__GPIO_5_25 IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT7__SIMBA_TRACE_4 IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8 IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6 IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x0398, 0x0084, 2, 0x07F4, 0, 0)
+#define MX6_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x0398, 0x0084, 3, 0x08C8, 0, 0)
+#define MX6_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x0398, 0x0084, 4 | MUX_CONFIG_SION, 0x086C, 0, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT8__GPIO_5_26 IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT8__SIMBA_TRACE_5 IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9 IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7 IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x039C, 0x0088, 2, 0x07FC, 0, 0)
+#define MX6_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x039C, 0x0088, 3, 0x08D4, 0, 0)
+#define MX6_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x039C, 0x0088, 4 | MUX_CONFIG_SION, 0x0868, 0, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT9__GPIO_5_27 IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 IOMUX_PAD(0x039C, 0x0088, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DAT9__SIMBA_TRACE_6 IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 IOMUX_PAD(0x03A0, 0x008C, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 IOMUX_PAD(0x03A0, 0x008C, 2, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x03A0, 0x008C, 4, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DATA_EN__GPIO_5_20 IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 IOMUX_PAD(0x03A0, 0x008C, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_DATA_EN__SIMBA_TRCLK IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_MCLK__CCM_CLKO IOMUX_PAD(0x03A4, 0x0090, 3, 0x0000, 0, MX6_CCM_CLK0_PAD_CTRL)
+#define MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x03A4, 0x0090, 4, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_MCLK__GPIO_5_19 IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 IOMUX_PAD(0x03A4, 0x0090, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_MCLK__SIMBA_TRCTL IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 IOMUX_PAD(0x03A8, 0x0094, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_PIXCLK__SIMBA_EVENTO IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_VSYNC__GPIO_5_21 IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 IOMUX_PAD(0x03AC, 0x0098, 6, 0x0000, 0, 0)
+#define MX6_PAD_CSI0_VSYNC__SIMBA_TRACE_0 IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0)
+#define MX6_PAD_DI0_DISP_CLK__LCDIF_CLK IOMUX_PAD(0x03B0, 0x009C, 1, 0x0000, 0, 0)
+#define MX6_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 IOMUX_PAD(0x03B0, 0x009C, 3, 0x0000, 0, 0)
+#define MX6_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, 0)
+#define MX6_PAD_DI0_DISP_CLK__GPIO_4_16 IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0)
+#define MX6_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0)
+#define MX6_PAD_DI0_DISP_CLK__TPSMP_HDATA_DIR IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0)
+#define MX6_PAD_DI0_DISP_CLK__LCDIF_WR_RWN IOMUX_PAD(0x03B0, 0x009C, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN15__LCDIF_ENABLE IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 IOMUX_PAD(0x03B4, 0x00A0, 3, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN15__GPIO_4_17 IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN15__PL301_SIM_MX6_PER1_HSIZE_0 IOMUX_PAD(0x03B4, 0x00A0, 7, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN15__LCDIF_RD_E IOMUX_PAD(0x03B4, 0x00A0, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN2__LCDIF_HSYNC IOMUX_PAD(0x03B8, 0x00A4, 1, 0x08D8, 0, 0)
+#define MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 IOMUX_PAD(0x03B8, 0x00A4, 3, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN2__GPIO_4_18 IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 IOMUX_PAD(0x03B8, 0x00A4, 6, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN2__PL301_SIM_MX6_PER1_HADDR_9 IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN2__LCDIF_RS IOMUX_PAD(0x03B8, 0x00A4, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN3__LCDIF_VSYNC IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 IOMUX_PAD(0x03BC, 0x00A8, 3, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN3__GPIO_4_19 IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN3__PL301_SIM_MX6_PER1_HADDR_10 IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN3__LCDIF_CS IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN4__LCDIF_BUSY IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0)
+#define MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN4__USDHC1_WP IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x03C0, 0x00AC, 4, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN4__GPIO_4_20 IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN4__PL301_SIM_MX6_PER1_HADDR_11 IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0)
+#define MX6_PAD_DI0_PIN4__LCDIF_RESET IOMUX_PAD(0x03C0, 0x00AC, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT0__LCDIF_DAT_0 IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT0__ECSPI3_SCLK IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x03C4, 0x00B0, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT0__GPIO_4_21 IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT0__PL301_SIM_MX6_PER1_HSIZE_1 IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT1__LCDIF_DAT_1 IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT1__ECSPI3_MOSI IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT1__GPIO_4_22 IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 IOMUX_PAD(0x03C8, 0x00B4, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT1__PL301_SIM_MX6_PER1_HADDR_12 IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT10__LCDIF_DAT_10 IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 IOMUX_PAD(0x03CC, 0x00B8, 3, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 IOMUX_PAD(0x03CC, 0x00B8, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT10__PL301_SIM_MX6_PER1_HADDR_21 IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT11__LCDIF_DAT_11 IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 IOMUX_PAD(0x03D0, 0x00BC, 3, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT11__GPIO_5_5 IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT11__PL301_SIM_MX6_PER1_HADDR_22 IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT12__LCDIF_DAT_12 IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT12__GPIO_5_6 IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT12__PL301_SIM_MX6_PER1_HADDR_23 IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT13__LCDIF_DAT_13 IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, 0)
+#define MX6_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT13__GPIO_5_7 IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT13__PL301_SIM_MX6_PER1_HADDR_24 IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT14__LCDIF_DAT_14 IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, 0)
+#define MX6_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT14__GPIO_5_8 IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 IOMUX_PAD(0x03DC, 0x00C8, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT14__PL301_SIM_MX6_PER1_HSIZE_2 IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT15__LCDIF_DAT_15 IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x03E0, 0x00CC, 2, 0x07E8, 0, 0)
+#define MX6_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0804, 0, 0)
+#define MX6_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT15__GPIO_5_9 IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT15__PL301_SIM_MX6_PER1_HADDR_25 IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT16__LCDIF_DAT_16 IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x03E4, 0x00D0, 2, 0x07FC, 1, 0)
+#define MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x03E4, 0x00D0, 3, 0x07C0, 0, 0)
+#define MX6_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 IOMUX_PAD(0x03E4, 0x00D0, 4, 0x08E8, 0, 0)
+#define MX6_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT16__PL301_SIM_MX6_PER1_HADDR_26 IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT17__LCDIF_DAT_17 IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x03E8, 0x00D4, 2, 0x07F8, 1, 0)
+#define MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x03E8, 0x00D4, 3, 0x07B4, 0, 0)
+#define MX6_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 IOMUX_PAD(0x03E8, 0x00D4, 4, 0x08EC, 0, 0)
+#define MX6_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT17__PL301_SIM_MX6_PER1_HADDR_27 IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT18__LCDIF_DAT_18 IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x03EC, 0x00D8, 2, 0x0800, 1, 0)
+#define MX6_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x03EC, 0x00D8, 3, 0x07C4, 0, 0)
+#define MX6_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x03EC, 0x00D8, 4, 0x07A4, 0, 0)
+#define MX6_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT19__LCDIF_DAT_19 IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x03F0, 0x00DC, 2, 0x07F4, 1, 0)
+#define MX6_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x03F0, 0x00DC, 3, 0x07B0, 0, 0)
+#define MX6_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x03F0, 0x00DC, 4, 0x07A0, 0, 0)
+#define MX6_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT2__LCDIF_DAT_2 IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT2__ECSPI3_MISO IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT2__GPIO_4_23 IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT2__PL301_SIM_MX6_PER1_HADDR_13 IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT20__LCDIF_DAT_20 IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x03F8, 0x00E4, 2, 0x07D8, 1, 0)
+#define MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x03F8, 0x00E4, 3, 0x07A8, 0, 0)
+#define MX6_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT20__PL301_SIM_MX6_PER1_HADDR_28 IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT21__LCDIF_DAT_21 IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x03FC, 0x00E8, 2, 0x07E0, 1, 0)
+#define MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x03FC, 0x00E8, 3, 0x079C, 0, 0)
+#define MX6_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT21__PL301_SIM_MX6_PER1_HADDR_29 IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT22__LCDIF_DAT_22 IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x0400, 0x00EC, 2, 0x07DC, 1, 0)
+#define MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x0400, 0x00EC, 3, 0x07AC, 0, 0)
+#define MX6_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT22__PL301_SIM_MX6_PER1_HADDR_30 IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT23__LCDIF_DAT_23 IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x0404, 0x00F0, 2, 0x07E4, 1, 0)
+#define MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x0404, 0x00F0, 3, 0x0798, 0, 0)
+#define MX6_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT23__PL301_SIM_MX6_PER1_HADDR_31 IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT3__LCDIF_DAT_3 IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT3__ECSPI3_SS0 IOMUX_PAD(0x0408, 0x00F4, 2, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 IOMUX_PAD(0x0408, 0x00F4, 3, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT3__GPIO_4_24 IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT3__PL301_SIM_MX6_PER1_HADDR_14 IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT4__LCDIF_DAT_4 IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT4__ECSPI3_SS1 IOMUX_PAD(0x040C, 0x00F8, 2, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 IOMUX_PAD(0x040C, 0x00F8, 3, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT4__GPIO_4_25 IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT4__PL301_SIM_MX6_PER1_HADDR_15 IOMUX_PAD(0x040C, 0x00F8, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT5__LCDIF_DAT_5 IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT5__ECSPI3_SS2 IOMUX_PAD(0x0410, 0x00FC, 2, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS IOMUX_PAD(0x0410, 0x00FC, 3, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT5__GPIO_4_26 IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT5__PL301_SIM_MX6_PER1_HADDR_16 IOMUX_PAD(0x0410, 0x00FC, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT6__LCDIF_DAT_6 IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT6__ECSPI3_SS3 IOMUX_PAD(0x0414, 0x0100, 2, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC IOMUX_PAD(0x0414, 0x0100, 3, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT6__GPIO_4_27 IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT6__PL301_SIM_MX6_PER1_HADDR_17 IOMUX_PAD(0x0414, 0x0100, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT7__LCDIF_DAT_7 IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT7__ECSPI3_RDY IOMUX_PAD(0x0418, 0x0104, 2, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 IOMUX_PAD(0x0418, 0x0104, 3, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT7__GPIO_4_28 IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT7__PL301_SIM_MX6_PER1_HADDR_18 IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT8__LCDIF_DAT_8 IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x041C, 0x0108, 2, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x041C, 0x0108, 3, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x041C, 0x0108, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT8__GPIO_4_29 IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT8__PL301_SIM_MX6_PER1_HADDR_19 IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT9__LCDIF_DAT_9 IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x0420, 0x010C, 2, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x0420, 0x010C, 4, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT9__GPIO_4_30 IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0)
+#define MX6_PAD_DISP0_DAT9__PL301_SIM_MX6_PER1_HADDR_20 IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_A0__MMDC_DRAM_A_0 IOMUX_PAD(0x0424, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_A1__MMDC_DRAM_A_1 IOMUX_PAD(0x0428, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_A10__MMDC_DRAM_A_10 IOMUX_PAD(0x042C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_A11__MMDC_DRAM_A_11 IOMUX_PAD(0x0430, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_A12__MMDC_DRAM_A_12 IOMUX_PAD(0x0434, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_A13__MMDC_DRAM_A_13 IOMUX_PAD(0x0438, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_A14__MMDC_DRAM_A_14 IOMUX_PAD(0x043C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_A15__MMDC_DRAM_A_15 IOMUX_PAD(0x0440, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_A2__MMDC_DRAM_A_2 IOMUX_PAD(0x0444, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_A3__MMDC_DRAM_A_3 IOMUX_PAD(0x0448, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_A4__MMDC_DRAM_A_4 IOMUX_PAD(0x044C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_A5__MMDC_DRAM_A_5 IOMUX_PAD(0x0450, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_A6__MMDC_DRAM_A_6 IOMUX_PAD(0x0454, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_A7__MMDC_DRAM_A_7 IOMUX_PAD(0x0458, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_A8__MMDC_DRAM_A_8 IOMUX_PAD(0x045C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_A9__MMDC_DRAM_A_9 IOMUX_PAD(0x0460, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_CAS__MMDC_DRAM_CAS IOMUX_PAD(0x0464, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_CS0__MMDC_DRAM_CS_0 IOMUX_PAD(0x0468, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_CS1__MMDC_DRAM_CS_1 IOMUX_PAD(0x046C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 IOMUX_PAD(0x0470, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 IOMUX_PAD(0x0474, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 IOMUX_PAD(0x0478, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 IOMUX_PAD(0x047C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 IOMUX_PAD(0x0480, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 IOMUX_PAD(0x0484, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 IOMUX_PAD(0x0488, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 IOMUX_PAD(0x048C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_RAS__MMDC_DRAM_RAS IOMUX_PAD(0x0490, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_RESET__MMDC_DRAM_RESET IOMUX_PAD(0x0494, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 IOMUX_PAD(0x0498, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 IOMUX_PAD(0x049C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 IOMUX_PAD(0x04A0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 IOMUX_PAD(0x04A4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 IOMUX_PAD(0x04A8, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 IOMUX_PAD(0x04AC, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 IOMUX_PAD(0x04B0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 IOMUX_PAD(0x04B4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 IOMUX_PAD(0x04B8, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 IOMUX_PAD(0x04BC, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 IOMUX_PAD(0x04C0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 IOMUX_PAD(0x04C4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 IOMUX_PAD(0x04C8, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 IOMUX_PAD(0x04CC, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 IOMUX_PAD(0x04D0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 IOMUX_PAD(0x04D4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 IOMUX_PAD(0x04D8, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE IOMUX_PAD(0x04DC, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_A16__WEIM_WEIM_A_16 IOMUX_PAD(0x04E0, 0x0110, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK IOMUX_PAD(0x04E0, 0x0110, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A16__IPU1_CSI1_PIXCLK IOMUX_PAD(0x04E0, 0x0110, 2, 0x08B8, 0, 0)
+#define MX6_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 IOMUX_PAD(0x04E0, 0x0110, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A16__GPIO_2_22 IOMUX_PAD(0x04E0, 0x0110, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A16__TPSMP_HDATA_6 IOMUX_PAD(0x04E0, 0x0110, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A16__SRC_BT_CFG_16 IOMUX_PAD(0x04E0, 0x0110, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A16__EPDC_SDDO_0 IOMUX_PAD(0x04E0, 0x0110, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_A17__WEIM_WEIM_A_17 IOMUX_PAD(0x04E4, 0x0114, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12 IOMUX_PAD(0x04E4, 0x0114, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A17__IPU1_CSI1_D_12 IOMUX_PAD(0x04E4, 0x0114, 2, 0x0890, 0, 0)
+#define MX6_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 IOMUX_PAD(0x04E4, 0x0114, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A17__GPIO_2_21 IOMUX_PAD(0x04E4, 0x0114, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A17__TPSMP_HDATA_5 IOMUX_PAD(0x04E4, 0x0114, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A17__SRC_BT_CFG_17 IOMUX_PAD(0x04E4, 0x0114, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A17__EPDC_PWRSTAT IOMUX_PAD(0x04E4, 0x0114, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_A18__WEIM_WEIM_A_18 IOMUX_PAD(0x04E8, 0x0118, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13 IOMUX_PAD(0x04E8, 0x0118, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A18__IPU1_CSI1_D_13 IOMUX_PAD(0x04E8, 0x0118, 2, 0x0894, 0, 0)
+#define MX6_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 IOMUX_PAD(0x04E8, 0x0118, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A18__GPIO_2_20 IOMUX_PAD(0x04E8, 0x0118, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A18__TPSMP_HDATA_4 IOMUX_PAD(0x04E8, 0x0118, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A18__SRC_BT_CFG_18 IOMUX_PAD(0x04E8, 0x0118, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A18__EPDC_PWRCTRL_0 IOMUX_PAD(0x04E8, 0x0118, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_A19__WEIM_WEIM_A_19 IOMUX_PAD(0x04EC, 0x011C, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14 IOMUX_PAD(0x04EC, 0x011C, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A19__IPU1_CSI1_D_14 IOMUX_PAD(0x04EC, 0x011C, 2, 0x0898, 0, 0)
+#define MX6_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 IOMUX_PAD(0x04EC, 0x011C, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A19__GPIO_2_19 IOMUX_PAD(0x04EC, 0x011C, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A19__TPSMP_HDATA_3 IOMUX_PAD(0x04EC, 0x011C, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A19__SRC_BT_CFG_19 IOMUX_PAD(0x04EC, 0x011C, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A19__EPDC_PWRCTRL_1 IOMUX_PAD(0x04EC, 0x011C, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_A20__WEIM_WEIM_A_20 IOMUX_PAD(0x04F0, 0x0120, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15 IOMUX_PAD(0x04F0, 0x0120, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A20__IPU1_CSI1_D_15 IOMUX_PAD(0x04F0, 0x0120, 2, 0x089C, 0, 0)
+#define MX6_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 IOMUX_PAD(0x04F0, 0x0120, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A20__GPIO_2_18 IOMUX_PAD(0x04F0, 0x0120, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A20__TPSMP_HDATA_2 IOMUX_PAD(0x04F0, 0x0120, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A20__SRC_BT_CFG_20 IOMUX_PAD(0x04F0, 0x0120, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A20__EPDC_PWRCTRL_2 IOMUX_PAD(0x04F0, 0x0120, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_A21__WEIM_WEIM_A_21 IOMUX_PAD(0x04F4, 0x0124, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16 IOMUX_PAD(0x04F4, 0x0124, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A21__IPU1_CSI1_D_16 IOMUX_PAD(0x04F4, 0x0124, 2, 0x08A0, 0, 0)
+#define MX6_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 IOMUX_PAD(0x04F4, 0x0124, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A21__GPIO_2_17 IOMUX_PAD(0x04F4, 0x0124, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A21__TPSMP_HDATA_1 IOMUX_PAD(0x04F4, 0x0124, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A21__SRC_BT_CFG_21 IOMUX_PAD(0x04F4, 0x0124, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A21__EPDC_GDCLK IOMUX_PAD(0x04F4, 0x0124, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_A22__WEIM_WEIM_A_22 IOMUX_PAD(0x04F8, 0x0128, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17 IOMUX_PAD(0x04F8, 0x0128, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A22__IPU1_CSI1_D_17 IOMUX_PAD(0x04F8, 0x0128, 2, 0x08A4, 0, 0)
+#define MX6_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x04F8, 0x0128, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A22__TPSMP_HDATA_0 IOMUX_PAD(0x04F8, 0x0128, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A22__SRC_BT_CFG_22 IOMUX_PAD(0x04F8, 0x0128, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A22__EPDC_GDSP IOMUX_PAD(0x04F8, 0x0128, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_A23__WEIM_WEIM_A_23 IOMUX_PAD(0x04FC, 0x012C, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18 IOMUX_PAD(0x04FC, 0x012C, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A23__IPU1_CSI1_D_18 IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, 0)
+#define MX6_PAD_EIM_A23__IPU1_SISG_3 IOMUX_PAD(0x04FC, 0x012C, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A23__GPIO_6_6 IOMUX_PAD(0x04FC, 0x012C, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A23__PL301_SIM_MX6_PER1_HPROT_3 IOMUX_PAD(0x04FC, 0x012C, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A23__SRC_BT_CFG_23 IOMUX_PAD(0x04FC, 0x012C, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A23__EPDC_GDOE IOMUX_PAD(0x04FC, 0x012C, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_A24__WEIM_WEIM_A_24 IOMUX_PAD(0x0500, 0x0130, 0, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19 IOMUX_PAD(0x0500, 0x0130, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A24__IPU1_CSI1_D_19 IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, 0)
+#define MX6_PAD_EIM_A24__IPU1_SISG_2 IOMUX_PAD(0x0500, 0x0130, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x0500, 0x0130, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A24__PL301_SIM_MX6_PER1_HPROT_2 IOMUX_PAD(0x0500, 0x0130, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A24__SRC_BT_CFG_24 IOMUX_PAD(0x0500, 0x0130, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A24__EPDC_GDRL IOMUX_PAD(0x0500, 0x0130, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_A25__WEIM_WEIM_A_25 IOMUX_PAD(0x0504, 0x0134, 0, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A25__ECSPI4_SS1 IOMUX_PAD(0x0504, 0x0134, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x0504, 0x0134, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A25__IPU1_DI1_PIN12 IOMUX_PAD(0x0504, 0x0134, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A25__IPU1_DI0_D1_CS IOMUX_PAD(0x0504, 0x0134, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A25__GPIO_5_2 IOMUX_PAD(0x0504, 0x0134, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE IOMUX_PAD(0x0504, 0x0134, 6, 0x085C, 0, 0)
+#define MX6_PAD_EIM_A25__PL301_SIM_MX6_PER1_HBURST_0 IOMUX_PAD(0x0504, 0x0134, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A25__EPDC_SDDO_15 IOMUX_PAD(0x0504, 0x0134, 8, 0x0000, 0, 0)
+#define MX6_PAD_EIM_A25__WEIM_ACLK_FREERUN IOMUX_PAD(0x0504, 0x0134, 9, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, 0)
+#define MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 IOMUX_PAD(0x0508, 0x0138, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_BCLK__GPIO_6_31 IOMUX_PAD(0x0508, 0x0138, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_BCLK__TPSMP_HDATA_31 IOMUX_PAD(0x0508, 0x0138, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_BCLK__EPDC_SDCE_9 IOMUX_PAD(0x0508, 0x0138, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_CS0__WEIM_WEIM_CS_0 IOMUX_PAD(0x050C, 0x013C, 0, 0x0000, 0, 0)
+#define MX6_PAD_EIM_CS0__IPU1_DI1_PIN5 IOMUX_PAD(0x050C, 0x013C, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x050C, 0x013C, 2, 0x07F4, 2, 0)
+#define MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 IOMUX_PAD(0x050C, 0x013C, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_CS0__GPIO_2_23 IOMUX_PAD(0x050C, 0x013C, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_CS0__TPSMP_HDATA_7 IOMUX_PAD(0x050C, 0x013C, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_CS0__EPDC_SDDO_6 IOMUX_PAD(0x050C, 0x013C, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_CS1__WEIM_WEIM_CS_1 IOMUX_PAD(0x0510, 0x0140, 0, 0x0000, 0, 0)
+#define MX6_PAD_EIM_CS1__IPU1_DI1_PIN6 IOMUX_PAD(0x0510, 0x0140, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x0510, 0x0140, 2, 0x07FC, 2, 0)
+#define MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 IOMUX_PAD(0x0510, 0x0140, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_CS1__GPIO_2_24 IOMUX_PAD(0x0510, 0x0140, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_CS1__TPSMP_HDATA_8 IOMUX_PAD(0x0510, 0x0140, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_CS1__EPDC_SDDO_8 IOMUX_PAD(0x0510, 0x0140, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_D16__WEIM_WEIM_D_16 IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, MX6_ECSPI_PAD_CTRL)
+#define MX6_PAD_EIM_D16__IPU1_DI0_PIN5 IOMUX_PAD(0x0514, 0x0144, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D16__IPU1_CSI1_D_18 IOMUX_PAD(0x0514, 0x0144, 3, 0x08A8, 1, 0)
+#define MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA IOMUX_PAD(0x0514, 0x0144, 4, 0x0864, 0, 0)
+#define MX6_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x0514, 0x0144, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x0514, 0x0144, 6 | MUX_CONFIG_SION, 0x0874, 0, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_EIM_D16__TPSMP_HTRANS_0 IOMUX_PAD(0x0514, 0x0144, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D16__EPDC_SDDO_10 IOMUX_PAD(0x0514, 0x0144, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_D17__WEIM_WEIM_D_17 IOMUX_PAD(0x0518, 0x0148, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, MX6_ECSPI_PAD_CTRL)
+#define MX6_PAD_EIM_D17__IPU1_DI0_PIN6 IOMUX_PAD(0x0518, 0x0148, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D17__IPU1_CSI1_PIXCLK IOMUX_PAD(0x0518, 0x0148, 3, 0x08B8, 1, 0)
+#define MX6_PAD_EIM_D17__DCIC1_DCIC_OUT IOMUX_PAD(0x0518, 0x0148, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x0518, 0x0148, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x0518, 0x0148, 6 | MUX_CONFIG_SION, 0x0878, 0, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_EIM_D17__PL301_SIM_MX6_PER1_HBURST_1 IOMUX_PAD(0x0518, 0x0148, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D17__EPDC_VCOM_0 IOMUX_PAD(0x0518, 0x0148, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_D18__WEIM_WEIM_D_18 IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, MX6_ECSPI_PAD_CTRL)
+#define MX6_PAD_EIM_D18__IPU1_DI0_PIN7 IOMUX_PAD(0x051C, 0x014C, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D18__IPU1_CSI1_D_17 IOMUX_PAD(0x051C, 0x014C, 3, 0x08A4, 1, 0)
+#define MX6_PAD_EIM_D18__IPU1_DI1_D0_CS IOMUX_PAD(0x051C, 0x014C, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x051C, 0x014C, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x051C, 0x014C, 6 | MUX_CONFIG_SION, 0x087C, 0, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_EIM_D18__PL301_SIM_MX6_PER1_HBURST_2 IOMUX_PAD(0x051C, 0x014C, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D18__EPDC_VCOM_1 IOMUX_PAD(0x051C, 0x014C, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_D19__WEIM_WEIM_D_19 IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x0520, 0x0150, 1, 0x07E8, 1, MX6_ECSPI_PAD_CTRL)
+#define MX6_PAD_EIM_D19__IPU1_DI0_PIN8 IOMUX_PAD(0x0520, 0x0150, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D19__IPU1_CSI1_D_16 IOMUX_PAD(0x0520, 0x0150, 3, 0x08A0, 1, 0)
+#define MX6_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x0520, 0x0150, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D19__UART1_RTS IOMUX_PAD(0x0520, 0x0150, 4, 0x08F8, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D19__GPIO_3_19 IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, MX6_ECSPI_PAD_CTRL)
+#define MX6_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x0520, 0x0150, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D19__PL301_SIM_MX6_PER1_HRESP IOMUX_PAD(0x0520, 0x0150, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D19__EPDC_SDDO_12 IOMUX_PAD(0x0520, 0x0150, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_D20__WEIM_WEIM_D_20 IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_D20__ECSPI4_SS0 IOMUX_PAD(0x0524, 0x0154, 1, 0x0808, 0, 0)
+#define MX6_PAD_EIM_D20__IPU1_DI0_PIN16 IOMUX_PAD(0x0524, 0x0154, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D20__IPU1_CSI1_D_15 IOMUX_PAD(0x0524, 0x0154, 3, 0x089C, 1, 0)
+#define MX6_PAD_EIM_D20__UART1_CTS IOMUX_PAD(0x0524, 0x0154, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x0524, 0x0154, 4, 0x08F8, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D20__GPIO_3_20 IOMUX_PAD(0x0524, 0x0154, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x0524, 0x0154, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D20__TPSMP_HTRANS_1 IOMUX_PAD(0x0524, 0x0154, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_D21__WEIM_WEIM_D_21 IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_D21__ECSPI4_SCLK IOMUX_PAD(0x0528, 0x0158, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D21__IPU1_DI0_PIN17 IOMUX_PAD(0x0528, 0x0158, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D21__IPU1_CSI1_D_11 IOMUX_PAD(0x0528, 0x0158, 3, 0x088C, 0, 0)
+#define MX6_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x0528, 0x0158, 4, 0x0920, 0, 0)
+#define MX6_PAD_EIM_D21__GPIO_3_21 IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x0528, 0x0158, 6 | MUX_CONFIG_SION, 0x0868, 1, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_EIM_D21__SPDIF_IN1 IOMUX_PAD(0x0528, 0x0158, 7, 0x08F0, 0, 0)
+
+#define MX6_PAD_EIM_D22__WEIM_WEIM_D_22 IOMUX_PAD(0x052C, 0x015C, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_D22__ECSPI4_MISO IOMUX_PAD(0x052C, 0x015C, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D22__IPU1_DI0_PIN1 IOMUX_PAD(0x052C, 0x015C, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D22__IPU1_CSI1_D_10 IOMUX_PAD(0x052C, 0x015C, 3, 0x0888, 0, 0)
+#define MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D22__GPIO_3_22 IOMUX_PAD(0x052C, 0x015C, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D22__SPDIF_OUT1 IOMUX_PAD(0x052C, 0x015C, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D22__PL301_SIM_MX6_PER1_HWRITE IOMUX_PAD(0x052C, 0x015C, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D22__EPDC_SDCE_6 IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_D23__WEIM_WEIM_D_23 IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_D23__IPU1_DI0_D0_CS IOMUX_PAD(0x0530, 0x0160, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x0530, 0x0160, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D23__UART3_RTS IOMUX_PAD(0x0530, 0x0160, 2, 0x0908, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x0530, 0x0160, 3, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D23__IPU1_CSI1_DATA_EN IOMUX_PAD(0x0530, 0x0160, 4, 0x08B0, 0, 0)
+#define MX6_PAD_EIM_D23__GPIO_3_23 IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D23__IPU1_DI1_PIN2 IOMUX_PAD(0x0530, 0x0160, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D23__IPU1_DI1_PIN14 IOMUX_PAD(0x0530, 0x0160, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D23__EPDC_SDDO_11 IOMUX_PAD(0x0530, 0x0160, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_D24__WEIM_WEIM_D_24 IOMUX_PAD(0x0534, 0x0164, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_D24__ECSPI4_SS2 IOMUX_PAD(0x0534, 0x0164, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D24__UART3_TXD IOMUX_PAD(0x0534, 0x0164, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D24__UART3_RXD IOMUX_PAD(0x0534, 0x0164, 2, 0x090C, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x0534, 0x0164, 3, 0x07EC, 0, 0)
+#define MX6_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x0534, 0x0164, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D24__GPIO_3_24 IOMUX_PAD(0x0534, 0x0164, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x0534, 0x0164, 6, 0x07BC, 1, 0)
+#define MX6_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x0534, 0x0164, 7, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D24__EPDC_SDCE_7 IOMUX_PAD(0x0534, 0x0164, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_D25__WEIM_WEIM_D_25 IOMUX_PAD(0x0538, 0x0168, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_D25__ECSPI4_SS3 IOMUX_PAD(0x0538, 0x0168, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D25__UART3_TXD IOMUX_PAD(0x0538, 0x0168, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x0538, 0x0168, 2, 0x090C, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x0538, 0x0168, 3, 0x07F0, 0, 0)
+#define MX6_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x0538, 0x0168, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D25__GPIO_3_25 IOMUX_PAD(0x0538, 0x0168, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x0538, 0x0168, 6, 0x07B8, 1, 0)
+#define MX6_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x0538, 0x0168, 7, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D25__EPDC_SDCE_8 IOMUX_PAD(0x0538, 0x0168, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_D26__WEIM_WEIM_D_26 IOMUX_PAD(0x053C, 0x016C, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_D26__IPU1_DI1_PIN11 IOMUX_PAD(0x053C, 0x016C, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D26__IPU1_CSI0_D_1 IOMUX_PAD(0x053C, 0x016C, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D26__IPU1_CSI1_D_14 IOMUX_PAD(0x053C, 0x016C, 3, 0x0898, 1, 0)
+#define MX6_PAD_EIM_D26__UART2_TXD IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D26__UART2_RXD IOMUX_PAD(0x053C, 0x016C, 4, 0x0904, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D26__GPIO_3_26 IOMUX_PAD(0x053C, 0x016C, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D26__IPU1_SISG_2 IOMUX_PAD(0x053C, 0x016C, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D26__IPU1_DISP1_DAT_22 IOMUX_PAD(0x053C, 0x016C, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D26__EPDC_SDOED IOMUX_PAD(0x053C, 0x016C, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_D27__WEIM_WEIM_D_27 IOMUX_PAD(0x0540, 0x0170, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_D27__IPU1_DI1_PIN13 IOMUX_PAD(0x0540, 0x0170, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D27__IPU1_CSI0_D_0 IOMUX_PAD(0x0540, 0x0170, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D27__IPU1_CSI1_D_13 IOMUX_PAD(0x0540, 0x0170, 3, 0x0894, 1, 0)
+#define MX6_PAD_EIM_D27__UART2_TXD IOMUX_PAD(0x0540, 0x0170, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D27__UART2_RXD IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D27__GPIO_3_27 IOMUX_PAD(0x0540, 0x0170, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D27__IPU1_SISG_3 IOMUX_PAD(0x0540, 0x0170, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D27__IPU1_DISP1_DAT_23 IOMUX_PAD(0x0540, 0x0170, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D27__EPDC_SDOE IOMUX_PAD(0x0540, 0x0170, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_D28__WEIM_WEIM_D_28 IOMUX_PAD(0x0544, 0x0174, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x0544, 0x0174, 1 | MUX_CONFIG_SION, 0x086C, 1, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_EIM_D28__ECSPI4_MOSI IOMUX_PAD(0x0544, 0x0174, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D28__IPU1_CSI1_D_12 IOMUX_PAD(0x0544, 0x0174, 3, 0x0890, 1, 0)
+#define MX6_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x0544, 0x0174, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D28__UART2_RTS IOMUX_PAD(0x0544, 0x0174, 4, 0x0900, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D28__GPIO_3_28 IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D28__IPU1_EXT_TRIG IOMUX_PAD(0x0544, 0x0174, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D28__IPU1_DI0_PIN13 IOMUX_PAD(0x0544, 0x0174, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D28__EPDC_PWRCTRL_3 IOMUX_PAD(0x0544, 0x0174, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_D29__WEIM_WEIM_D_29 IOMUX_PAD(0x0548, 0x0178, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_D29__IPU1_DI1_PIN15 IOMUX_PAD(0x0548, 0x0178, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D29__ECSPI4_SS0 IOMUX_PAD(0x0548, 0x0178, 2, 0x0808, 1, 0)
+#define MX6_PAD_EIM_D29__UART2_CTS IOMUX_PAD(0x0548, 0x0178, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x0548, 0x0178, 4, 0x0900, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D29__GPIO_3_29 IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D29__IPU1_CSI1_VSYNC IOMUX_PAD(0x0548, 0x0178, 6, 0x08BC, 0, 0)
+#define MX6_PAD_EIM_D29__IPU1_DI0_PIN14 IOMUX_PAD(0x0548, 0x0178, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D29__EPDC_PWRWAKE IOMUX_PAD(0x0548, 0x0178, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_D30__WEIM_WEIM_D_30 IOMUX_PAD(0x054C, 0x017C, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_D30__IPU1_DISP1_DAT_21 IOMUX_PAD(0x054C, 0x017C, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D30__IPU1_DI0_PIN11 IOMUX_PAD(0x054C, 0x017C, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D30__IPU1_CSI0_D_3 IOMUX_PAD(0x054C, 0x017C, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x054C, 0x017C, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D30__UART3_RTS IOMUX_PAD(0x054C, 0x017C, 4, 0x0908, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D30__GPIO_3_30 IOMUX_PAD(0x054C, 0x017C, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, 0)
+#define MX6_PAD_EIM_D30__PL301_SIM_MX6_PER1_HPROT_0 IOMUX_PAD(0x054C, 0x017C, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D30__EPDC_SDOEZ IOMUX_PAD(0x054C, 0x017C, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_D31__WEIM_WEIM_D_31 IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20 IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D31__IPU1_DI0_PIN12 IOMUX_PAD(0x0550, 0x0180, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D31__IPU1_CSI0_D_2 IOMUX_PAD(0x0550, 0x0180, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D31__UART3_CTS IOMUX_PAD(0x0550, 0x0180, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x0550, 0x0180, 4, 0x0908, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_D31__GPIO_3_31 IOMUX_PAD(0x0550, 0x0180, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D31__PL301_SIM_MX6_PER1_HPROT_1 IOMUX_PAD(0x0550, 0x0180, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D31__EPDC_SDCLK IOMUX_PAD(0x0550, 0x0180, 8, 0x0000, 0, 0)
+#define MX6_PAD_EIM_D31__WEIM_ACLK_FREERUN IOMUX_PAD(0x0550, 0x0180, 9, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9 IOMUX_PAD(0x0554, 0x0184, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA0__IPU1_CSI1_D_9 IOMUX_PAD(0x0554, 0x0184, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 IOMUX_PAD(0x0554, 0x0184, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA0__GPIO_3_0 IOMUX_PAD(0x0554, 0x0184, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA0__TPSMP_HDATA_14 IOMUX_PAD(0x0554, 0x0184, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA0__SRC_BT_CFG_0 IOMUX_PAD(0x0554, 0x0184, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA0__EPDC_SDCLKN IOMUX_PAD(0x0554, 0x0184, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 IOMUX_PAD(0x0558, 0x0188, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8 IOMUX_PAD(0x0558, 0x0188, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA1__IPU1_CSI1_D_8 IOMUX_PAD(0x0558, 0x0188, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 IOMUX_PAD(0x0558, 0x0188, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE IOMUX_PAD(0x0558, 0x0188, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA1__GPIO_3_1 IOMUX_PAD(0x0558, 0x0188, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA1__TPSMP_HDATA_15 IOMUX_PAD(0x0558, 0x0188, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA1__SRC_BT_CFG_1 IOMUX_PAD(0x0558, 0x0188, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA1__EPDC_SDLE IOMUX_PAD(0x0558, 0x0188, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 IOMUX_PAD(0x055C, 0x018C, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 IOMUX_PAD(0x055C, 0x018C, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA10__IPU1_CSI1_DATA_EN IOMUX_PAD(0x055C, 0x018C, 2, 0x08B0, 1, 0)
+#define MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 IOMUX_PAD(0x055C, 0x018C, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA10__GPIO_3_10 IOMUX_PAD(0x055C, 0x018C, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA10__TPSMP_HDATA_24 IOMUX_PAD(0x055C, 0x018C, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA10__SRC_BT_CFG_10 IOMUX_PAD(0x055C, 0x018C, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA10__EPDC_SDDO_1 IOMUX_PAD(0x055C, 0x018C, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 IOMUX_PAD(0x0560, 0x0190, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_DA11__IPU1_DI1_PIN2 IOMUX_PAD(0x0560, 0x0190, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA11__IPU1_CSI1_HSYNC IOMUX_PAD(0x0560, 0x0190, 2, 0x08B4, 0, 0)
+#define MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 IOMUX_PAD(0x0560, 0x0190, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 IOMUX_PAD(0x0560, 0x0190, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA11__GPIO_3_11 IOMUX_PAD(0x0560, 0x0190, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA11__TPSMP_HDATA_25 IOMUX_PAD(0x0560, 0x0190, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA11__SRC_BT_CFG_11 IOMUX_PAD(0x0560, 0x0190, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA11__EPDC_SDDO_3 IOMUX_PAD(0x0560, 0x0190, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 IOMUX_PAD(0x0564, 0x0194, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_DA12__IPU1_DI1_PIN3 IOMUX_PAD(0x0564, 0x0194, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA12__IPU1_CSI1_VSYNC IOMUX_PAD(0x0564, 0x0194, 2, 0x08BC, 1, 0)
+#define MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 IOMUX_PAD(0x0564, 0x0194, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 IOMUX_PAD(0x0564, 0x0194, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA12__GPIO_3_12 IOMUX_PAD(0x0564, 0x0194, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA12__TPSMP_HDATA_26 IOMUX_PAD(0x0564, 0x0194, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA12__SRC_BT_CFG_12 IOMUX_PAD(0x0564, 0x0194, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA12__EPDC_SDDO_2 IOMUX_PAD(0x0564, 0x0194, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 IOMUX_PAD(0x0568, 0x0198, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS IOMUX_PAD(0x0568, 0x0198, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x0568, 0x0198, 2, 0x07D0, 0, 0)
+#define MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 IOMUX_PAD(0x0568, 0x0198, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 IOMUX_PAD(0x0568, 0x0198, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA13__GPIO_3_13 IOMUX_PAD(0x0568, 0x0198, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA13__TPSMP_HDATA_27 IOMUX_PAD(0x0568, 0x0198, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA13__SRC_BT_CFG_13 IOMUX_PAD(0x0568, 0x0198, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA13__EPDC_SDDO_13 IOMUX_PAD(0x0568, 0x0198, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 IOMUX_PAD(0x056C, 0x019C, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS IOMUX_PAD(0x056C, 0x019C, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x056C, 0x019C, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 IOMUX_PAD(0x056C, 0x019C, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 IOMUX_PAD(0x056C, 0x019C, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA14__GPIO_3_14 IOMUX_PAD(0x056C, 0x019C, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA14__TPSMP_HDATA_28 IOMUX_PAD(0x056C, 0x019C, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA14__SRC_BT_CFG_14 IOMUX_PAD(0x056C, 0x019C, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA14__EPDC_SDDO_14 IOMUX_PAD(0x056C, 0x019C, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 IOMUX_PAD(0x0570, 0x01A0, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_DA15__IPU1_DI1_PIN1 IOMUX_PAD(0x0570, 0x01A0, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA15__IPU1_DI1_PIN4 IOMUX_PAD(0x0570, 0x01A0, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 IOMUX_PAD(0x0570, 0x01A0, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA15__GPIO_3_15 IOMUX_PAD(0x0570, 0x01A0, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA15__TPSMP_HDATA_29 IOMUX_PAD(0x0570, 0x01A0, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA15__SRC_BT_CFG_15 IOMUX_PAD(0x0570, 0x01A0, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA15__EPDC_SDDO_9 IOMUX_PAD(0x0570, 0x01A0, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 IOMUX_PAD(0x0574, 0x01A4, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7 IOMUX_PAD(0x0574, 0x01A4, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA2__IPU1_CSI1_D_7 IOMUX_PAD(0x0574, 0x01A4, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 IOMUX_PAD(0x0574, 0x01A4, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE IOMUX_PAD(0x0574, 0x01A4, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA2__GPIO_3_2 IOMUX_PAD(0x0574, 0x01A4, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA2__TPSMP_HDATA_16 IOMUX_PAD(0x0574, 0x01A4, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA2__SRC_BT_CFG_2 IOMUX_PAD(0x0574, 0x01A4, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA2__EPDC_BDR_0 IOMUX_PAD(0x0574, 0x01A4, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 IOMUX_PAD(0x0578, 0x01A8, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6 IOMUX_PAD(0x0578, 0x01A8, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA3__IPU1_CSI1_D_6 IOMUX_PAD(0x0578, 0x01A8, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 IOMUX_PAD(0x0578, 0x01A8, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ IOMUX_PAD(0x0578, 0x01A8, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA3__GPIO_3_3 IOMUX_PAD(0x0578, 0x01A8, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA3__TPSMP_HDATA_17 IOMUX_PAD(0x0578, 0x01A8, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA3__SRC_BT_CFG_3 IOMUX_PAD(0x0578, 0x01A8, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA3__EPDC_BDR_1 IOMUX_PAD(0x0578, 0x01A8, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 IOMUX_PAD(0x057C, 0x01AC, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5 IOMUX_PAD(0x057C, 0x01AC, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA4__IPU1_CSI1_D_5 IOMUX_PAD(0x057C, 0x01AC, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 IOMUX_PAD(0x057C, 0x01AC, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN IOMUX_PAD(0x057C, 0x01AC, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA4__GPIO_3_4 IOMUX_PAD(0x057C, 0x01AC, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA4__TPSMP_HDATA_18 IOMUX_PAD(0x057C, 0x01AC, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA4__SRC_BT_CFG_4 IOMUX_PAD(0x057C, 0x01AC, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA4__EPDC_SDCE_0 IOMUX_PAD(0x057C, 0x01AC, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 IOMUX_PAD(0x0580, 0x01B0, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4 IOMUX_PAD(0x0580, 0x01B0, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA5__IPU1_CSI1_D_4 IOMUX_PAD(0x0580, 0x01B0, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 IOMUX_PAD(0x0580, 0x01B0, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP IOMUX_PAD(0x0580, 0x01B0, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA5__GPIO_3_5 IOMUX_PAD(0x0580, 0x01B0, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA5__TPSMP_HDATA_19 IOMUX_PAD(0x0580, 0x01B0, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA5__SRC_BT_CFG_5 IOMUX_PAD(0x0580, 0x01B0, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA5__EPDC_SDCE_1 IOMUX_PAD(0x0580, 0x01B0, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 IOMUX_PAD(0x0584, 0x01B4, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3 IOMUX_PAD(0x0584, 0x01B4, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA6__IPU1_CSI1_D_3 IOMUX_PAD(0x0584, 0x01B4, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 IOMUX_PAD(0x0584, 0x01B4, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN IOMUX_PAD(0x0584, 0x01B4, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA6__GPIO_3_6 IOMUX_PAD(0x0584, 0x01B4, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA6__TPSMP_HDATA_20 IOMUX_PAD(0x0584, 0x01B4, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA6__SRC_BT_CFG_6 IOMUX_PAD(0x0584, 0x01B4, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA6__EPDC_SDCE_2 IOMUX_PAD(0x0584, 0x01B4, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 IOMUX_PAD(0x0588, 0x01B8, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2 IOMUX_PAD(0x0588, 0x01B8, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA7__IPU1_CSI1_D_2 IOMUX_PAD(0x0588, 0x01B8, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 IOMUX_PAD(0x0588, 0x01B8, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA7__GPIO_3_7 IOMUX_PAD(0x0588, 0x01B8, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA7__TPSMP_HDATA_21 IOMUX_PAD(0x0588, 0x01B8, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA7__SRC_BT_CFG_7 IOMUX_PAD(0x0588, 0x01B8, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA7__EPDC_SDCE_3 IOMUX_PAD(0x0588, 0x01B8, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 IOMUX_PAD(0x058C, 0x01BC, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1 IOMUX_PAD(0x058C, 0x01BC, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA8__IPU1_CSI1_D_1 IOMUX_PAD(0x058C, 0x01BC, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 IOMUX_PAD(0x058C, 0x01BC, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA8__GPIO_3_8 IOMUX_PAD(0x058C, 0x01BC, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA8__TPSMP_HDATA_22 IOMUX_PAD(0x058C, 0x01BC, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA8__SRC_BT_CFG_8 IOMUX_PAD(0x058C, 0x01BC, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA8__EPDC_SDCE_4 IOMUX_PAD(0x058C, 0x01BC, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 IOMUX_PAD(0x0590, 0x01C0, 0, 0x0000, 0, MX6_WEIM_NOR_PAD_CTRL)
+#define MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0 IOMUX_PAD(0x0590, 0x01C0, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA9__IPU1_CSI1_D_0 IOMUX_PAD(0x0590, 0x01C0, 2, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 IOMUX_PAD(0x0590, 0x01C0, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA9__GPIO_3_9 IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA9__TPSMP_HDATA_23 IOMUX_PAD(0x0590, 0x01C0, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA9__SRC_BT_CFG_9 IOMUX_PAD(0x0590, 0x01C0, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_DA9__EPDC_SDCE_5 IOMUX_PAD(0x0590, 0x01C0, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_EB0__WEIM_WEIM_EB_0 IOMUX_PAD(0x0594, 0x01C4, 0, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11 IOMUX_PAD(0x0594, 0x01C4, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB0__IPU1_CSI1_D_11 IOMUX_PAD(0x0594, 0x01C4, 2, 0x088C, 1, 0)
+#define MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 IOMUX_PAD(0x0594, 0x01C4, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB0__CCM_PMIC_RDY IOMUX_PAD(0x0594, 0x01C4, 4, 0x07D4, 0, 0)
+#define MX6_PAD_EIM_EB0__GPIO_2_28 IOMUX_PAD(0x0594, 0x01C4, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB0__TPSMP_HDATA_12 IOMUX_PAD(0x0594, 0x01C4, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB0__SRC_BT_CFG_27 IOMUX_PAD(0x0594, 0x01C4, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB0__EPDC_PWRCOM IOMUX_PAD(0x0594, 0x01C4, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_EB1__WEIM_WEIM_EB_1 IOMUX_PAD(0x0598, 0x01C8, 0, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10 IOMUX_PAD(0x0598, 0x01C8, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB1__IPU1_CSI1_D_10 IOMUX_PAD(0x0598, 0x01C8, 2, 0x0888, 1, 0)
+#define MX6_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 IOMUX_PAD(0x0598, 0x01C8, 3, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB1__GPIO_2_29 IOMUX_PAD(0x0598, 0x01C8, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB1__TPSMP_HDATA_13 IOMUX_PAD(0x0598, 0x01C8, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB1__SRC_BT_CFG_28 IOMUX_PAD(0x0598, 0x01C8, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB1__EPDC_SDSHR IOMUX_PAD(0x0598, 0x01C8, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_EB2__WEIM_WEIM_EB_2 IOMUX_PAD(0x059C, 0x01CC, 0, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x059C, 0x01CC, 1, 0x07E4, 2, MX6_ECSPI_PAD_CTRL)
+#define MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x059C, 0x01CC, 2, 0x07D0, 1, 0)
+#define MX6_PAD_EIM_EB2__IPU1_CSI1_D_19 IOMUX_PAD(0x059C, 0x01CC, 3, 0x08AC, 1, 0)
+#define MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL IOMUX_PAD(0x059C, 0x01CC, 4, 0x0860, 0, 0)
+#define MX6_PAD_EIM_EB2__GPIO_2_30 IOMUX_PAD(0x059C, 0x01CC, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x059C, 0x01CC, 6 | MUX_CONFIG_SION, 0x0870, 0, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_EIM_EB2__SRC_BT_CFG_30 IOMUX_PAD(0x059C, 0x01CC, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB2__EPDC_SDDO_5 IOMUX_PAD(0x059C, 0x01CC, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_EB3__WEIM_WEIM_EB_3 IOMUX_PAD(0x05A0, 0x01D0, 0, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB3__ECSPI4_RDY IOMUX_PAD(0x05A0, 0x01D0, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB3__UART3_CTS IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0908, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x05A0, 0x01D0, 3, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EIM_EB3__IPU1_CSI1_HSYNC IOMUX_PAD(0x05A0, 0x01D0, 4, 0x08B4, 1, 0)
+#define MX6_PAD_EIM_EB3__GPIO_2_31 IOMUX_PAD(0x05A0, 0x01D0, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB3__IPU1_DI1_PIN3 IOMUX_PAD(0x05A0, 0x01D0, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB3__SRC_BT_CFG_31 IOMUX_PAD(0x05A0, 0x01D0, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB3__EPDC_SDCE_0 IOMUX_PAD(0x05A0, 0x01D0, 8, 0x0000, 0, 0)
+#define MX6_PAD_EIM_EB3__WEIM_ACLK_FREERUN IOMUX_PAD(0x05A0, 0x01D0, 9, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_LBA__WEIM_WEIM_LBA IOMUX_PAD(0x05A4, 0x01D4, 0, 0x0000, 0, 0)
+#define MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 IOMUX_PAD(0x05A4, 0x01D4, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x05A4, 0x01D4, 2, 0x0804, 1, 0)
+#define MX6_PAD_EIM_LBA__GPIO_2_27 IOMUX_PAD(0x05A4, 0x01D4, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_LBA__TPSMP_HDATA_11 IOMUX_PAD(0x05A4, 0x01D4, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_LBA__SRC_BT_CFG_26 IOMUX_PAD(0x05A4, 0x01D4, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_LBA__EPDC_SDDO_4 IOMUX_PAD(0x05A4, 0x01D4, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_OE__WEIM_WEIM_OE IOMUX_PAD(0x05A8, 0x01D8, 0, 0x0000, 0, 0)
+#define MX6_PAD_EIM_OE__IPU1_DI1_PIN7 IOMUX_PAD(0x05A8, 0x01D8, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x05A8, 0x01D8, 2, 0x07F8, 2, 0)
+#define MX6_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 IOMUX_PAD(0x05A8, 0x01D8, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_OE__GPIO_2_25 IOMUX_PAD(0x05A8, 0x01D8, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_OE__TPSMP_HDATA_9 IOMUX_PAD(0x05A8, 0x01D8, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_OE__EPDC_PWRIRQ IOMUX_PAD(0x05A8, 0x01D8, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_RW__WEIM_WEIM_RW IOMUX_PAD(0x05AC, 0x01DC, 0, 0x0000, 0, 0)
+#define MX6_PAD_EIM_RW__IPU1_DI1_PIN8 IOMUX_PAD(0x05AC, 0x01DC, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x05AC, 0x01DC, 2, 0x0800, 2, 0)
+#define MX6_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 IOMUX_PAD(0x05AC, 0x01DC, 4, 0x0000, 0, 0)
+#define MX6_PAD_EIM_RW__GPIO_2_26 IOMUX_PAD(0x05AC, 0x01DC, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_RW__TPSMP_HDATA_10 IOMUX_PAD(0x05AC, 0x01DC, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_RW__SRC_BT_CFG_29 IOMUX_PAD(0x05AC, 0x01DC, 7, 0x0000, 0, 0)
+#define MX6_PAD_EIM_RW__EPDC_SDDO_7 IOMUX_PAD(0x05AC, 0x01DC, 8, 0x0000, 0, 0)
+
+#define MX6_PAD_EIM_WAIT__WEIM_WEIM_WAIT IOMUX_PAD(0x05B0, 0x01E0, 0, 0x0000, 0, 0)
+#define MX6_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B IOMUX_PAD(0x05B0, 0x01E0, 1, 0x0000, 0, 0)
+#define MX6_PAD_EIM_WAIT__GPIO_5_0 IOMUX_PAD(0x05B0, 0x01E0, 5, 0x0000, 0, 0)
+#define MX6_PAD_EIM_WAIT__TPSMP_HDATA_30 IOMUX_PAD(0x05B0, 0x01E0, 6, 0x0000, 0, 0)
+#define MX6_PAD_EIM_WAIT__SRC_BT_CFG_25 IOMUX_PAD(0x05B0, 0x01E0, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_ENET_CRS_DV__ENET_RX_EN IOMUX_PAD(0x05B4, 0x01E4, 1, 0x0828, 0, 0)
+#define MX6_PAD_ENET_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x05B4, 0x01E4, 2, 0x0840, 0, MX6_ESAI_PAD_CTRL)
+#define MX6_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x05B4, 0x01E4, 3, 0x08F4, 0, 0)
+#define MX6_PAD_ENET_CRS_DV__GPIO_1_25 IOMUX_PAD(0x05B4, 0x01E4, 5, 0x0000, 0, 0)
+#define MX6_PAD_ENET_CRS_DV__PHY_TDO IOMUX_PAD(0x05B4, 0x01E4, 6, 0x0000, 0, 0)
+#define MX6_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD IOMUX_PAD(0x05B4, 0x01E4, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_ENET_MDC__MLB_MLBDAT IOMUX_PAD(0x05B8, 0x01E8, 0, 0x08E0, 0, 0)
+#define MX6_PAD_ENET_MDC__ENET_MDC IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_ENET_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x05B8, 0x01E8, 2, 0x0858, 0, MX6_ESAI_PAD_CTRL)
+#define MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN IOMUX_PAD(0x05B8, 0x01E8, 4, 0x0000, 0, 0)
+#define MX6_PAD_ENET_MDC__GPIO_1_31 IOMUX_PAD(0x05B8, 0x01E8, 5, 0x0000, 0, 0)
+#define MX6_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET IOMUX_PAD(0x05B8, 0x01E8, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_ENET_MDIO__ENET_MDIO IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_ENET_MDIO__ESAI1_SCKR IOMUX_PAD(0x05BC, 0x01EC, 2, 0x083C, 0, 0)
+#define MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x05BC, 0x01EC, 3, 0x0000, 0, 0)
+#define MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT IOMUX_PAD(0x05BC, 0x01EC, 4, 0x0000, 0, 0)
+#define MX6_PAD_ENET_MDIO__GPIO_1_22 IOMUX_PAD(0x05BC, 0x01EC, 5, 0x0000, 0, 0)
+#define MX6_PAD_ENET_MDIO__SPDIF_PLOCK IOMUX_PAD(0x05BC, 0x01EC, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_ENET_REF_CLK__ENET_TX_CLK IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, MX6_ENET_REF_CLK_PAD_CTRL)
+#define MX6_PAD_ENET_REF_CLK__ESAI1_FSR IOMUX_PAD(0x05C0, 0x01F0, 2, 0x082C, 0, 0)
+#define MX6_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x05C0, 0x01F0, 3, 0x0000, 0, 0)
+#define MX6_PAD_ENET_REF_CLK__GPIO_1_23 IOMUX_PAD(0x05C0, 0x01F0, 5, 0x0000, 0, 0)
+#define MX6_PAD_ENET_REF_CLK__SPDIF_SRCLK IOMUX_PAD(0x05C0, 0x01F0, 6, 0x0000, 0, 0)
+#define MX6_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH IOMUX_PAD(0x05C0, 0x01F0, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_ENET_RX_ER__ANATOP_USBOTG_ID IOMUX_PAD(0x05C4, 0x01F4, 0, 0x0790, 0, 0)
+#define MX6_PAD_ENET_RX_ER__ENET_RX_ER IOMUX_PAD(0x05C4, 0x01F4, 1, 0x0000, 0, 0)
+#define MX6_PAD_ENET_RX_ER__ESAI1_HCKR IOMUX_PAD(0x05C4, 0x01F4, 2, 0x0834, 0, MX6_ESAI_PAD_CTRL)
+#define MX6_PAD_ENET_RX_ER__SPDIF_IN1 IOMUX_PAD(0x05C4, 0x01F4, 3, 0x08F0, 1, 0)
+#define MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT IOMUX_PAD(0x05C4, 0x01F4, 4, 0x0000, 0, 0)
+#define MX6_PAD_ENET_RX_ER__GPIO_1_24 IOMUX_PAD(0x05C4, 0x01F4, 5, 0x0000, 0, 0)
+#define MX6_PAD_ENET_RX_ER__PHY_TDI IOMUX_PAD(0x05C4, 0x01F4, 6, 0x0000, 0, 0)
+#define MX6_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD IOMUX_PAD(0x05C4, 0x01F4, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_ENET_RXD0__OSC32K_32K_OUT IOMUX_PAD(0x05C8, 0x01F8, 0, 0x0000, 0, 0)
+#define MX6_PAD_ENET_RXD0__ENET_RDATA_0 IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0818, 0, 0)
+#define MX6_PAD_ENET_RXD0__ESAI1_HCKT IOMUX_PAD(0x05C8, 0x01F8, 2, 0x0838, 0, MX6_ESAI_PAD_CTRL)
+#define MX6_PAD_ENET_RXD0__SPDIF_OUT1 IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0)
+#define MX6_PAD_ENET_RXD0__GPIO_1_27 IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0)
+#define MX6_PAD_ENET_RXD0__PHY_TMS IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0)
+#define MX6_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_ENET_RXD1__MLB_MLBSIG IOMUX_PAD(0x05CC, 0x01FC, 0, 0x08E4, 0, 0)
+#define MX6_PAD_ENET_RXD1__ENET_RDATA_1 IOMUX_PAD(0x05CC, 0x01FC, 1, 0x081C, 0, 0)
+#define MX6_PAD_ENET_RXD1__ESAI1_FST IOMUX_PAD(0x05CC, 0x01FC, 2, 0x0830, 0, MX6_ESAI_PAD_CTRL)
+#define MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0)
+#define MX6_PAD_ENET_RXD1__GPIO_1_26 IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0)
+#define MX6_PAD_ENET_RXD1__PHY_TCK IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0)
+#define MX6_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_ENET_TX_EN__ENET_TX_EN IOMUX_PAD(0x05D0, 0x0200, 1, 0x0000, 0, 0)
+#define MX6_PAD_ENET_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x05D0, 0x0200, 2, 0x0850, 0, MX6_ESAI_PAD_CTRL)
+#define MX6_PAD_ENET_TX_EN__GPIO_1_28 IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0)
+#define MX6_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0)
+#define MX6_PAD_ENET_TX_EN__I2C4_SCL IOMUX_PAD(0x05D0, 0x0200, 9 | MUX_CONFIG_SION, 0x0880, 0, MX6_I2C_PAD_CTRL)
+
+#define MX6_PAD_ENET_TXD0__ENET_TDATA_0 IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0)
+#define MX6_PAD_ENET_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x05D4, 0x0204, 2, 0x0854, 0, MX6_ESAI_PAD_CTRL)
+#define MX6_PAD_ENET_TXD0__GPIO_1_30 IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0)
+#define MX6_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_ENET_TXD1__MLB_MLBCLK IOMUX_PAD(0x05D8, 0x0208, 0, 0x08DC, 0, 0)
+#define MX6_PAD_ENET_TXD1__ENET_TDATA_1 IOMUX_PAD(0x05D8, 0x0208, 1, 0x0000, 0, 0)
+#define MX6_PAD_ENET_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x05D8, 0x0208, 2, 0x084C, 0, MX6_ESAI_PAD_CTRL)
+#define MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0)
+#define MX6_PAD_ENET_TXD1__GPIO_1_29 IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0)
+#define MX6_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0)
+#define MX6_PAD_ENET_TXD1__I2C4_SDA IOMUX_PAD(0x05D8, 0x0208, 9 | MUX_CONFIG_SION, 0x0884, 0, MX6_I2C_PAD_CTRL)
+
+#define MX6_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x05DC, 0x020C, 0, 0x0000, 0, MX6_CCM_CLK0_PAD_CTRL)
+#define MX6_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x05DC, 0x020C, 2, 0x08C0, 1, 0)
+#define MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK IOMUX_PAD(0x05DC, 0x020C, 3, 0x0794, 0, 0)
+#define MX6_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_0__GPIO_1_0 IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x05DC, 0x020C, 6, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0)
+#define MX6_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0)
+#define MX6_PAD_GPIO_1__USBOTG_ID IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0)
+#define MX6_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_1__GPIO_1_1 IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_1__USDHC1_CD IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x05E4, 0x0214, 0, 0x0850, 1, 0)
+#define MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN IOMUX_PAD(0x05E4, 0x0214, 1, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT IOMUX_PAD(0x05E4, 0x0214, 0x12, 0x080C, 0, 0)
+#define MX6_PAD_GPIO_16__USDHC1_LCTL IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x05E4, 0x0214, 4, 0x08F0, 2, 0)
+#define MX6_PAD_GPIO_16__GPIO_7_11 IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x05E4, 0x0214, 6 | MUX_CONFIG_SION, 0x087C, 1, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x05E8, 0x0218, 0, 0x0844, 0, MX6_ESAI_PAD_CTRL)
+#define MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_17__CCM_PMIC_RDY IOMUX_PAD(0x05E8, 0x0218, 2, 0x07D4, 1, 0)
+#define MX6_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 IOMUX_PAD(0x05E8, 0x0218, 3, 0x08E8, 1, 0)
+#define MX6_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, MX6_SPDIF_OUT_PAD_CTRL)
+#define MX6_PAD_GPIO_17__GPIO_7_12 IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x05EC, 0x021C, 0, 0x0848, 0, 0)
+#define MX6_PAD_GPIO_18__ENET_RX_CLK IOMUX_PAD(0x05EC, 0x021C, 1, 0x0814, 0, 0)
+#define MX6_PAD_GPIO_18__USDHC3_VSELECT IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 IOMUX_PAD(0x05EC, 0x021C, 3, 0x08EC, 1, 0)
+#define MX6_PAD_GPIO_18__ASRC_ASRC_EXT_CLK IOMUX_PAD(0x05EC, 0x021C, 4, 0x0794, 1, 0)
+#define MX6_PAD_GPIO_18__GPIO_7_13 IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x05F0, 0x0220, 0, 0x08C0, 2, 0)
+#define MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT IOMUX_PAD(0x05F0, 0x0220, 1, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x05F0, 0x0220, 2, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x05F0, 0x0220, 3, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_19__GPIO_4_5 IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_19__ENET_TX_ER IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x05F4, 0x0224, 0, 0x0830, 1, 0)
+#define MX6_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x05F4, 0x0224, 2, 0x08D0, 1, 0)
+#define MX6_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_2__GPIO_1_2 IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_2__USDHC2_WP IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x05F4, 0x0224, 7, 0x08E0, 1, MX6_MLB150_PAD_CTRL)
+
+#define MX6_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x05F8, 0x0228, 0, 0x0834, 1, 0)
+#define MX6_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x05F8, 0x0228, 2 | MUX_CONFIG_SION, 0x0878, 1, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_3__GPIO_1_3 IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x05F8, 0x0228, 6, 0x0924, 1, 0)
+#define MX6_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x05F8, 0x0228, 7, 0x08DC, 1, MX6_MLB150_PAD_CTRL)
+
+#define MX6_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x05FC, 0x022C, 0, 0x0838, 1, 0)
+#define MX6_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x05FC, 0x022C, 2, 0x08C8, 1, 0)
+#define MX6_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_4__GPIO_1_4 IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_4__USDHC2_CD IOMUX_PAD(0x05FC, 0x022C, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED IOMUX_PAD(0x05FC, 0x022C, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x0600, 0x0230, 0, 0x084C, 1, MX6_ESAI_PAD_CTRL)
+#define MX6_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x0600, 0x0230, 2, 0x08D4, 1, 0)
+#define MX6_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_5__GPIO_1_5 IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x0600, 0x0230, 6 | MUX_CONFIG_SION, 0x0878, 2, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_GPIO_5__SIMBA_EVENTI IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x0604, 0x0234, 0, 0x0840, 1, 0)
+#define MX6_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x0604, 0x0234, 2 | MUX_CONFIG_SION, 0x087C, 2, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_6__GPIO_1_6 IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_6__USDHC2_LCTL IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, MX6_MLB150_PAD_CTRL)
+
+#define MX6_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x0608, 0x0238, 0, 0x0854, 1, 0)
+#define MX6_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x0608, 0x0238, 2, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_7__UART2_TXD IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_GPIO_7__UART2_RXD IOMUX_PAD(0x0608, 0x0238, 4, 0x0904, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_GPIO_7__GPIO_1_7 IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_7__I2C4_SCL IOMUX_PAD(0x0608, 0x0238, 8 | MUX_CONFIG_SION, 0x0880, 1, MX6_I2C_PAD_CTRL)
+
+#define MX6_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x060C, 0x023C, 0, 0x0858, 1, 0)
+#define MX6_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x060C, 0x023C, 2, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x060C, 0x023C, 3, 0x07C8, 0, 0)
+#define MX6_PAD_GPIO_8__UART2_TXD IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_GPIO_8__UART2_RXD IOMUX_PAD(0x060C, 0x023C, 4, 0x0904, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_GPIO_8__GPIO_1_8 IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x060C, 0x023C, 6, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_8__I2C4_SDA IOMUX_PAD(0x060C, 0x023C, 8 | MUX_CONFIG_SION, 0x0884, 1, MX6_I2C_PAD_CTRL)
+
+#define MX6_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x0610, 0x0240, 0, 0x082C, 1, MX6_ESAI_PAD_CTRL)
+#define MX6_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x0610, 0x0240, 2, 0x08C4, 1, 0)
+#define MX6_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_9__GPIO_1_9 IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0)
+#define MX6_PAD_GPIO_9__USDHC1_WP IOMUX_PAD(0x0610, 0x0240, 6, 0x092C, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_GPIO_9__SRC_EARLY_RST IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_JTAG_MOD__SJC_MOD IOMUX_PAD(0x0614, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_JTAG_TCK__SJC_TCK IOMUX_PAD(0x0618, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_JTAG_TDI__SJC_TDI IOMUX_PAD(0x061C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_JTAG_TDO__SJC_TDO IOMUX_PAD(0x0620, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_JTAG_TMS__SJC_TMS IOMUX_PAD(0x0624, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_JTAG_TRSTB__SJC_TRSTB IOMUX_PAD(0x0628, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define MX6_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x062C, 0x0244, 0, 0x07D8, 3, 0)
+#define MX6_PAD_KEY_COL0__ENET_RDATA_3 IOMUX_PAD(0x062C, 0x0244, 1, 0x0824, 0, 0)
+#define MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x062C, 0x0244, 2, 0x07C0, 1, 0)
+#define MX6_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x062C, 0x0244, 3, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL0__UART4_TXD IOMUX_PAD(0x062C, 0x0244, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_COL0__UART4_RXD IOMUX_PAD(0x062C, 0x0244, 4, 0x0914, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_COL0__GPIO_4_6 IOMUX_PAD(0x062C, 0x0244, 5, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL0__DCIC1_DCIC_OUT IOMUX_PAD(0x062C, 0x0244, 6, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x062C, 0x0244, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x0630, 0x0248, 0, 0x07DC, 3, 0)
+#define MX6_PAD_KEY_COL1__ENET_MDIO IOMUX_PAD(0x0630, 0x0248, 1, 0x0810, 1, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x0630, 0x0248, 2, 0x07C4, 1, 0)
+#define MX6_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x0630, 0x0248, 3, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL1__UART5_TXD IOMUX_PAD(0x0630, 0x0248, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_COL1__UART5_RXD IOMUX_PAD(0x0630, 0x0248, 4, 0x091C, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_COL1__GPIO_4_8 IOMUX_PAD(0x0630, 0x0248, 5, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL1__USDHC1_VSELECT IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_COL1__PL301_SIM_MX6_PER1_HADDR_1 IOMUX_PAD(0x0630, 0x0248, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x0634, 0x024C, 0, 0x07E8, 2, 0)
+#define MX6_PAD_KEY_COL2__ENET_RDATA_2 IOMUX_PAD(0x0634, 0x024C, 1, 0x0820, 0, 0)
+#define MX6_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x0634, 0x024C, 2, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x0634, 0x024C, 3, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL2__ENET_MDC IOMUX_PAD(0x0634, 0x024C, 4, 0x0000, 0, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_KEY_COL2__GPIO_4_10 IOMUX_PAD(0x0634, 0x024C, 5, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP IOMUX_PAD(0x0634, 0x024C, 6, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL2__PL301_SIM_MX6_PER1_HADDR_3 IOMUX_PAD(0x0634, 0x024C, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x0638, 0x0250, 0, 0x07F0, 1, 0)
+#define MX6_PAD_KEY_COL3__ENET_CRS IOMUX_PAD(0x0638, 0x0250, 1, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL IOMUX_PAD(0x0638, 0x0250, 2 | MUX_CONFIG_SION, 0x0860, 1, \
+ MX6_I2C_PAD_CTRL)
+#define MX6_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x0638, 0x0250, 3, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x0638, 0x0250, 4 | MUX_CONFIG_SION, 0x0870, 1, \
+ MX6_I2C_PAD_CTRL)
+#define MX6_PAD_KEY_COL3__GPIO_4_12 IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x0638, 0x0250, 6, 0x08F0, 3, 0)
+#define MX6_PAD_KEY_COL3__PL301_SIM_MX6_PER1_HADDR_5 IOMUX_PAD(0x0638, 0x0250, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x063C, 0x0254, 0, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL4__IPU1_SISG_4 IOMUX_PAD(0x063C, 0x0254, 1, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, 0)
+#define MX6_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x063C, 0x0254, 3, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL4__UART5_CTS IOMUX_PAD(0x063C, 0x0254, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x063C, 0x0254, 4, 0x0918, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_COL4__GPIO_4_14 IOMUX_PAD(0x063C, 0x0254, 5, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 IOMUX_PAD(0x063C, 0x0254, 6, 0x0000, 0, 0)
+#define MX6_PAD_KEY_COL4__PL301_SIM_MX6_PER1_HADDR_7 IOMUX_PAD(0x063C, 0x0254, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x0640, 0x0258, 0, 0x07E0, 3, 0)
+#define MX6_PAD_KEY_ROW0__ENET_TDATA_3 IOMUX_PAD(0x0640, 0x0258, 1, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, 0)
+#define MX6_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x0640, 0x0258, 3, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW0__UART4_TXD IOMUX_PAD(0x0640, 0x0258, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_ROW0__UART4_RXD IOMUX_PAD(0x0640, 0x0258, 4, 0x0914, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_ROW0__GPIO_4_7 IOMUX_PAD(0x0640, 0x0258, 5, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW0__PL301_SIM_MX6_PER1_HADDR_0 IOMUX_PAD(0x0640, 0x0258, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x0644, 0x025C, 0, 0x07E4, 3, 0)
+#define MX6_PAD_KEY_ROW1__ENET_COL IOMUX_PAD(0x0644, 0x025C, 1, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, 0)
+#define MX6_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x0644, 0x025C, 3, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW1__UART5_TXD IOMUX_PAD(0x0644, 0x025C, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_ROW1__UART5_RXD IOMUX_PAD(0x0644, 0x025C, 4, 0x091C, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_ROW1__GPIO_4_9 IOMUX_PAD(0x0644, 0x025C, 5, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW1__USDHC2_VSELECT IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_ROW1__PL301_SIM_MX6_PER1_HADDR_2 IOMUX_PAD(0x0644, 0x025C, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x0648, 0x0260, 0, 0x07EC, 1, 0)
+#define MX6_PAD_KEY_ROW2__ENET_TDATA_2 IOMUX_PAD(0x0648, 0x0260, 1, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x0648, 0x0260, 2, 0x07C8, 1, 0)
+#define MX6_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x0648, 0x0260, 3, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW2__USDHC2_VSELECT IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_ROW2__GPIO_4_11 IOMUX_PAD(0x0648, 0x0260, 5, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE IOMUX_PAD(0x0648, 0x0260, 6, 0x085C, 1, 0)
+#define MX6_PAD_KEY_ROW2__PL301_SIM_MX6_PER1_HADDR_4 IOMUX_PAD(0x0648, 0x0260, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x064C, 0x0264, 0, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, 0)
+#define MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA IOMUX_PAD(0x064C, 0x0264, 2 | MUX_CONFIG_SION, 0x0864, 1, \
+ MX6_I2C_PAD_CTRL)
+#define MX6_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x064C, 0x0264, 3, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x064C, 0x0264, 4 | MUX_CONFIG_SION, 0x0874, 1, \
+ MX6_I2C_PAD_CTRL)
+#define MX6_PAD_KEY_ROW3__GPIO_4_13 IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW3__USDHC1_VSELECT IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_ROW3__PL301_SIM_MX6_PER1_HADDR_6 IOMUX_PAD(0x064C, 0x0264, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x0650, 0x0268, 0, 0x07CC, 0, 0)
+#define MX6_PAD_KEY_ROW4__IPU1_SISG_5 IOMUX_PAD(0x0650, 0x0268, 1, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x0650, 0x0268, 3, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x0650, 0x0268, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_ROW4__UART5_RTS IOMUX_PAD(0x0650, 0x0268, 4, 0x0918, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_ROW4__GPIO_4_15 IOMUX_PAD(0x0650, 0x0268, 5, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 IOMUX_PAD(0x0650, 0x0268, 6, 0x0000, 0, 0)
+#define MX6_PAD_KEY_ROW4__PL301_SIM_MX6_PER1_HADDR_8 IOMUX_PAD(0x0650, 0x0268, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_NANDF_ALE__RAWNAND_ALE IOMUX_PAD(0x0654, 0x026C, 0, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_ALE__USDHC4_RST IOMUX_PAD(0x0654, 0x026C, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 IOMUX_PAD(0x0654, 0x026C, 2, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 IOMUX_PAD(0x0654, 0x026C, 3, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 IOMUX_PAD(0x0654, 0x026C, 4, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_ALE__GPIO_6_8 IOMUX_PAD(0x0654, 0x026C, 5, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 IOMUX_PAD(0x0654, 0x026C, 6, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_ALE__USDHC3_CLKI IOMUX_PAD(0x0654, 0x026C, 8, 0x0934, 0, MX6_USDHC_PAD_CTRL)
+
+#define MX6_PAD_NANDF_CLE__RAWNAND_CLE IOMUX_PAD(0x0658, 0x0270, 0, 0x0000, 0, MX6_GPMI_PAD_CTRL2)
+#define MX6_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 IOMUX_PAD(0x0658, 0x0270, 2, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 IOMUX_PAD(0x0658, 0x0270, 3, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 IOMUX_PAD(0x0658, 0x0270, 4, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CLE__GPIO_6_7 IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 IOMUX_PAD(0x0658, 0x0270, 6, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CLE__USDHC3_CLKO IOMUX_PAD(0x0658, 0x0270, 8, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+
+#define MX6_PAD_NANDF_CS0__RAWNAND_CE0N IOMUX_PAD(0x065C, 0x0274, 0, 0x0000, 0, MX6_GPMI_PAD_CTRL2)
+#define MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 IOMUX_PAD(0x065C, 0x0274, 3, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 IOMUX_PAD(0x065C, 0x0274, 4, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CS0__GPIO_6_11 IOMUX_PAD(0x065C, 0x0274, 5, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CS0__USDHC1_CLKO IOMUX_PAD(0x065C, 0x0274, 8, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+
+#define MX6_PAD_NANDF_CS1__RAWNAND_CE1N IOMUX_PAD(0x0660, 0x0278, 0, 0x0000, 0, MX6_GPMI_PAD_CTRL2)
+#define MX6_PAD_NANDF_CS1__USDHC4_VSELECT IOMUX_PAD(0x0660, 0x0278, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_NANDF_CS1__USDHC3_VSELECT IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 IOMUX_PAD(0x0660, 0x0278, 4, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CS1__GPIO_6_14 IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CS1__PL301_SIM_MX6_PER1_HREADYOUT IOMUX_PAD(0x0660, 0x0278, 7, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CS1__USDHC1_CLKI IOMUX_PAD(0x0660, 0x0278, 8, 0x0928, 0, MX6_USDHC_PAD_CTRL)
+
+#define MX6_PAD_NANDF_CS2__RAWNAND_CE2N IOMUX_PAD(0x0664, 0x027C, 0, 0x0000, 0, MX6_GPMI_PAD_CTRL2)
+#define MX6_PAD_NANDF_CS2__IPU1_SISG_0 IOMUX_PAD(0x0664, 0x027C, 1, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x0664, 0x027C, 2, 0x0844, 1, MX6_ESAI_PAD_CTRL)
+#define MX6_PAD_NANDF_CS2__WEIM_WEIM_CRE IOMUX_PAD(0x0664, 0x027C, 3, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CS2__CCM_CLKO2 IOMUX_PAD(0x0664, 0x027C, 4, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CS2__GPIO_6_15 IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CS2__USDHC2_CLKO IOMUX_PAD(0x0664, 0x027C, 8, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+
+#define MX6_PAD_NANDF_CS3__RAWNAND_CE3N IOMUX_PAD(0x0668, 0x0280, 0, 0x0000, 0, MX6_GPMI_PAD_CTRL2)
+#define MX6_PAD_NANDF_CS3__IPU1_SISG_1 IOMUX_PAD(0x0668, 0x0280, 1, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x0668, 0x0280, 2, 0x0848, 1, MX6_ESAI_PAD_CTRL)
+#define MX6_PAD_NANDF_CS3__WEIM_WEIM_A_26 IOMUX_PAD(0x0668, 0x0280, 3, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 IOMUX_PAD(0x0668, 0x0280, 4, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CS3__GPIO_6_16 IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CS3__TPSMP_CLK IOMUX_PAD(0x0668, 0x0280, 7, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_CS3__USDHC2_CLKI IOMUX_PAD(0x0668, 0x0280, 8, 0x0930, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_NANDF_CS3__I2C4_SDA IOMUX_PAD(0x0668, 0x0280, 9 | MUX_CONFIG_SION, 0x0884, 2, MX6_I2C_PAD_CTRL)
+
+#define MX6_PAD_NANDF_D0__RAWNAND_D0 IOMUX_PAD(0x066C, 0x0284, 0, 0x0000, 0, MX6_GPMI_PAD_CTRL2)
+#define MX6_PAD_NANDF_D0__USDHC1_DAT4 IOMUX_PAD(0x066C, 0x0284, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 IOMUX_PAD(0x066C, 0x0284, 2, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 IOMUX_PAD(0x066C, 0x0284, 3, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 IOMUX_PAD(0x066C, 0x0284, 4, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D0__GPIO_2_0 IOMUX_PAD(0x066C, 0x0284, 5, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 IOMUX_PAD(0x066C, 0x0284, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_NANDF_D1__RAWNAND_D1 IOMUX_PAD(0x0670, 0x0288, 0, 0x0000, 0, MX6_GPMI_PAD_CTRL2)
+#define MX6_PAD_NANDF_D1__USDHC1_DAT5 IOMUX_PAD(0x0670, 0x0288, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 IOMUX_PAD(0x0670, 0x0288, 2, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 IOMUX_PAD(0x0670, 0x0288, 3, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 IOMUX_PAD(0x0670, 0x0288, 4, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D1__GPIO_2_1 IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 IOMUX_PAD(0x0670, 0x0288, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_NANDF_D2__RAWNAND_D2 IOMUX_PAD(0x0674, 0x028C, 0, 0x0000, 0, MX6_GPMI_PAD_CTRL2)
+#define MX6_PAD_NANDF_D2__USDHC1_DAT6 IOMUX_PAD(0x0674, 0x028C, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 IOMUX_PAD(0x0674, 0x028C, 2, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 IOMUX_PAD(0x0674, 0x028C, 3, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 IOMUX_PAD(0x0674, 0x028C, 4, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D2__GPIO_2_2 IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 IOMUX_PAD(0x0674, 0x028C, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_NANDF_D3__RAWNAND_D3 IOMUX_PAD(0x0678, 0x0290, 0, 0x0000, 0, MX6_GPMI_PAD_CTRL2)
+#define MX6_PAD_NANDF_D3__USDHC1_DAT7 IOMUX_PAD(0x0678, 0x0290, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 IOMUX_PAD(0x0678, 0x0290, 2, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 IOMUX_PAD(0x0678, 0x0290, 3, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 IOMUX_PAD(0x0678, 0x0290, 4, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D3__GPIO_2_3 IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 IOMUX_PAD(0x0678, 0x0290, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_NANDF_D4__RAWNAND_D4 IOMUX_PAD(0x067C, 0x0294, 0, 0x0000, 0, MX6_GPMI_PAD_CTRL2)
+#define MX6_PAD_NANDF_D4__USDHC2_DAT4 IOMUX_PAD(0x067C, 0x0294, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 IOMUX_PAD(0x067C, 0x0294, 2, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 IOMUX_PAD(0x067C, 0x0294, 3, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 IOMUX_PAD(0x067C, 0x0294, 4, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D4__GPIO_2_4 IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 IOMUX_PAD(0x067C, 0x0294, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_NANDF_D5__RAWNAND_D5 IOMUX_PAD(0x0680, 0x0298, 0, 0x0000, 0, MX6_GPMI_PAD_CTRL2)
+#define MX6_PAD_NANDF_D5__USDHC2_DAT5 IOMUX_PAD(0x0680, 0x0298, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 IOMUX_PAD(0x0680, 0x0298, 2, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 IOMUX_PAD(0x0680, 0x0298, 3, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 IOMUX_PAD(0x0680, 0x0298, 4, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D5__GPIO_2_5 IOMUX_PAD(0x0680, 0x0298, 5, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 IOMUX_PAD(0x0680, 0x0298, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_NANDF_D6__RAWNAND_D6 IOMUX_PAD(0x0684, 0x029C, 0, 0x0000, 0, MX6_GPMI_PAD_CTRL2)
+#define MX6_PAD_NANDF_D6__USDHC2_DAT6 IOMUX_PAD(0x0684, 0x029C, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 IOMUX_PAD(0x0684, 0x029C, 2, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 IOMUX_PAD(0x0684, 0x029C, 3, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 IOMUX_PAD(0x0684, 0x029C, 4, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D6__GPIO_2_6 IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 IOMUX_PAD(0x0684, 0x029C, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_NANDF_D7__RAWNAND_D7 IOMUX_PAD(0x0688, 0x02A0, 0, 0x0000, 0, MX6_GPMI_PAD_CTRL2)
+#define MX6_PAD_NANDF_D7__USDHC2_DAT7 IOMUX_PAD(0x0688, 0x02A0, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 IOMUX_PAD(0x0688, 0x02A0, 2, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 IOMUX_PAD(0x0688, 0x02A0, 3, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 IOMUX_PAD(0x0688, 0x02A0, 4, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D7__GPIO_2_7 IOMUX_PAD(0x0688, 0x02A0, 5, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 IOMUX_PAD(0x0688, 0x02A0, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_NANDF_RB0__RAWNAND_READY0 IOMUX_PAD(0x068C, 0x02A4, 0, 0x0000, 0, MX6_GPMI_PAD_CTRL0)
+#define MX6_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 IOMUX_PAD(0x068C, 0x02A4, 2, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 IOMUX_PAD(0x068C, 0x02A4, 3, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 IOMUX_PAD(0x068C, 0x02A4, 4, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_RB0__GPIO_6_10 IOMUX_PAD(0x068C, 0x02A4, 5, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 IOMUX_PAD(0x068C, 0x02A4, 6, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_RB0__USDHC4_CLKI IOMUX_PAD(0x068C, 0x02A4, 8, 0x0938, 0, MX6_USDHC_PAD_CTRL)
+
+#define MX6_PAD_NANDF_WP_B__RAWNAND_RESETN IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, MX6_GPMI_PAD_CTRL2)
+#define MX6_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_WP_B__GPIO_6_9 IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0)
+#define MX6_PAD_NANDF_WP_B__USDHC4_CLKO IOMUX_PAD(0x0690, 0x02A8, 8, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_NANDF_WP_B__I2C4_SCL IOMUX_PAD(0x0690, 0x02A8, 9 | MUX_CONFIG_SION, 0x0880, 2, MX6_I2C_PAD_CTRL)
+
+#define MX6_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_RGMII_RD0__GPIO_6_25 IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_RGMII_RD1__GPIO_6_27 IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_RD1__SJC_FAIL IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_RGMII_RD2__GPIO_6_28 IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE IOMUX_PAD(0x06A0, 0x02B8, 0, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_RGMII_RD3__GPIO_6_29 IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA IOMUX_PAD(0x06A4, 0x02BC, 0 | MUX_CONFIG_SION, 0x0000, 0, MX6_USB_HSIC_PAD_CTRL)
+#define MX6_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_RGMII_RX_CTL__GPIO_6_24 IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE IOMUX_PAD(0x06A8, 0x02C0, 0 | MUX_CONFIG_SION, 0x0000, 0, MX6_USB_HSIC_PAD_CTRL)
+#define MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE_START IOMUX_PAD(0x06A8, 0x02C0, 0 | MUX_CONFIG_SION, 0x0000, 0, MX6_USB_HSIC_PAD_CTRL | MX6_PAD_CTL_PUS_47K_UP)
+#define MX6_PAD_RGMII_RXC__ENET_RGMII_RXC IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_RGMII_RXC__GPIO_6_30 IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_RGMII_TD0__GPIO_6_20 IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_RGMII_TD1__GPIO_6_21 IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_TD1__CCM_PLL3_BYP IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_RGMII_TD2__GPIO_6_22 IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_TD2__CCM_PLL2_BYP IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_RGMII_TD3__GPIO_6_23 IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE IOMUX_PAD(0x06BC, 0x02D4, 0 | MUX_CONFIG_SION, 0x0000, 0, MX6_USB_HSIC_PAD_CTRL)
+#define MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START IOMUX_PAD(0x06BC, 0x02D4, 0 | MUX_CONFIG_SION, 0x0000, 0, MX6_USB_HSIC_PAD_CTRL | MX6_PAD_CTL_PUS_47K_UP)
+#define MX6_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_RGMII_TX_CTL__GPIO_6_26 IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT IOMUX_PAD(0x06BC, 0x02D4, 7, 0x080C, 1, 0)
+
+#define MX6_PAD_RGMII_TXC__USBOH3_H2_DATA IOMUX_PAD(0x06C0, 0x02D8, 0 | MUX_CONFIG_SION, 0x0000, 0, MX6_USB_HSIC_PAD_CTRL)
+#define MX6_PAD_RGMII_TXC__ENET_RGMII_TXC IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x06C0, 0x02D8, 2, 0x08F4, 1, 0)
+#define MX6_PAD_RGMII_TXC__GPIO_6_19 IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0)
+#define MX6_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD1_CLK__USDHC1_CLK IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD1_CLK__USDHC1_CLK_50MHZ_40OHM IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, MX6_USDHC_PAD_CTRL_50MHZ_40OHM)
+#define MX6_PAD_SD1_CLK__OSC32K_32K_OUT IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD1_CLK__GPIO_1_20 IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD1_CLK__PHY_DTB_0 IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_SD1_CMD__USDHC1_CMD IOMUX_PAD(0x06C8, 0x02E0, 0 | MUX_CONFIG_SION, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD1_CMD__USDHC1_CMD_50MHZ_40OHM IOMUX_PAD(0x06C8, 0x02E0, 0 | MUX_CONFIG_SION, 0x0000, 0, MX6_USDHC_PAD_CTRL_50MHZ_40OHM)
+#define MX6_PAD_SD1_CMD__PWM4_PWMO IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD1_CMD__GPIO_1_18 IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD1_DAT0__USDHC1_DAT0 IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD1_DAT0__USDHC1_DAT0_50MHZ_40OHM IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_50MHZ_40OHM)
+#define MX6_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS IOMUX_PAD(0x06CC, 0x02E4, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT0__GPT_CAPIN1 IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT0__GPIO_1_16 IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 IOMUX_PAD(0x06CC, 0x02E4, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD1_DAT1__USDHC1_DAT1 IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD1_DAT1__USDHC1_DAT1_50MHZ_40OHM IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_50MHZ_40OHM)
+#define MX6_PAD_SD1_DAT1__PWM3_PWMO IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT1__GPT_CAPIN2 IOMUX_PAD(0x06D0, 0x02E8, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT1__GPIO_1_17 IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 IOMUX_PAD(0x06D0, 0x02E8, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD1_DAT2__USDHC1_DAT2 IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD1_DAT2__USDHC1_DAT2_50MHZ_40OHM IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_50MHZ_40OHM)
+#define MX6_PAD_SD1_DAT2__GPT_CMPOUT2 IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT2__PWM2_PWMO IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT2__WDOG1_WDOG_B IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT2__GPIO_1_19 IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 IOMUX_PAD(0x06D4, 0x02EC, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD1_DAT3__USDHC1_DAT3 IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD1_DAT3__USDHC1_DAT3_50MHZ_40OHM IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_50MHZ_40OHM)
+#define MX6_PAD_SD1_DAT3__GPT_CMPOUT3 IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT3__PWM1_PWMO IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT3__WDOG2_WDOG_B IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT3__GPIO_1_21 IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD2_CLK__USDHC2_CLK IOMUX_PAD(0x06DC, 0x02F4, 0, 0x0930, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x06DC, 0x02F4, 2, 0x08C0, 3, 0)
+#define MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x06DC, 0x02F4, 3, 0x07A4, 1, 0)
+#define MX6_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD2_CLK__GPIO_1_10 IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD2_CLK__PHY_DTB_1 IOMUX_PAD(0x06DC, 0x02F4, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_SD2_CMD__USDHC2_CMD IOMUX_PAD(0x06E0, 0x02F8, 0 | MUX_CONFIG_SION, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x06E0, 0x02F8, 2, 0x08CC, 2, 0)
+#define MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x06E0, 0x02F8, 3, 0x07A0, 1, 0)
+#define MX6_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD2_CMD__GPIO_1_11 IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0)
+
+#define MX6_PAD_SD2_DAT0__USDHC2_DAT0 IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0798, 1, 0)
+#define MX6_PAD_SD2_DAT0__KPP_ROW_7 IOMUX_PAD(0x06E4, 0x02FC, 4, 0x08D4, 2, 0)
+#define MX6_PAD_SD2_DAT0__GPIO_1_15 IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD2_DAT0__DCIC2_DCIC_OUT IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD2_DAT1__USDHC2_DAT1 IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT1__WEIM_WEIM_CS_2 IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x06E8, 0x0300, 3, 0x07AC, 1, 0)
+#define MX6_PAD_SD2_DAT1__KPP_COL_7 IOMUX_PAD(0x06E8, 0x0300, 4, 0x08C8, 2, 0)
+#define MX6_PAD_SD2_DAT1__GPIO_1_14 IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD2_DAT1__CCM_WAIT IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD2_DAT2__USDHC2_DAT2 IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT2__WEIM_WEIM_CS_3 IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXD IOMUX_PAD(0x06EC, 0x0304, 3, 0x079C, 1, 0)
+#define MX6_PAD_SD2_DAT2__KPP_ROW_6 IOMUX_PAD(0x06EC, 0x0304, 4, 0x08D0, 2, 0)
+#define MX6_PAD_SD2_DAT2__GPIO_1_13 IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD2_DAT2__CCM_STOP IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD2_DAT3__USDHC2_DAT3 IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT3__KPP_COL_6 IOMUX_PAD(0x06F0, 0x0308, 2, 0x08C4, 2, 0)
+#define MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXC IOMUX_PAD(0x06F0, 0x0308, 3, 0x07A8, 1, 0)
+#define MX6_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD2_DAT3__GPIO_1_12 IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD2_DAT3__SJC_DONE IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD3_CLK__USDHC3_CLK_50MHZ IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_CLK__USDHC3_CLK_100MHZ IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD3_CLK__USDHC3_CLK_200MHZ IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD3_CLK__UART2_CTS IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_CLK__UART2_RTS IOMUX_PAD(0x06F4, 0x030C, 1, 0x0900, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_CLK__CAN1_RXCAN IOMUX_PAD(0x06F4, 0x030C, 2, 0x07C8, 2, 0)
+#define MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD3_CLK__GPIO_7_3 IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD3_CMD__USDHC3_CMD_50MHZ IOMUX_PAD(0x06F8, 0x0310, 0 | MUX_CONFIG_SION, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_CMD__USDHC3_CMD_100MHZ IOMUX_PAD(0x06F8, 0x0310, 0 | MUX_CONFIG_SION, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD3_CMD__USDHC3_CMD_200MHZ IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD3_CMD__UART2_CTS IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MXSDL_PAD_SD3_CMD__UART2_RTS IOMUX_PAD(0x06F8, 0x0310, 1, 0x0900, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_CMD__CAN1_TXCAN IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD3_CMD__GPIO_7_2 IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_DAT0__USDHC3_DAT0_100MHZ IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD3_DAT0__USDHC3_DAT0_200MHZ IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD3_DAT0__UART1_CTS IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_DAT0__UART1_RTS IOMUX_PAD(0x06FC, 0x0314, 1, 0x08F8, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_DAT0__CAN2_TXCAN IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT0__GPIO_7_4 IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_DAT1__USDHC3_DAT1_100MHZ IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD3_DAT1__USDHC3_DAT1_200MHZ IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD3_DAT1__UART1_CTS IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_DAT1__UART1_RTS IOMUX_PAD(0x0700, 0x0318, 1, 0x08F8, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_DAT1__CAN2_RXCAN IOMUX_PAD(0x0700, 0x0318, 2, 0x07CC, 1, 0)
+#define MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT1__GPIO_7_5 IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_DAT2__USDHC3_DAT2_100MHZ IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD3_DAT2__USDHC3_DAT2_200MHZ IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT2__GPIO_7_6 IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_DAT3__USDHC3_DAT3_100MHZ IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD3_DAT3__USDHC3_DAT3_200MHZ IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD3_DAT3__UART3_CTS IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_DAT3__UART3_RTS IOMUX_PAD(0x0708, 0x0320, 1, 0x0908, 4, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT3__GPIO_7_7 IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_DAT4__USDHC3_DAT4_100MHZ IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD3_DAT4__USDHC3_DAT4_200MHZ IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD3_DAT4__UART2_TXD IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_DAT4__UART2_RXD IOMUX_PAD(0x070C, 0x0324, 1, 0x0904, 4, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT4__GPIO_7_1 IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_DAT5__USDHC3_DAT5_100MHZ IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD3_DAT5__USDHC3_DAT5_200MHZ IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD3_DAT5__UART2_TXD IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_DAT5__UART2_RXD IOMUX_PAD(0x0710, 0x0328, 1, 0x0904, 5, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 IOMUX_PAD(0x0710, 0x0328, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT5__GPIO_7_0 IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_DAT6__USDHC3_DAT6_100MHZ IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD3_DAT6__USDHC3_DAT6_200MHZ IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD3_DAT6__UART1_TXD IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_DAT6__UART1_RXD IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT6__GPIO_6_18 IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_DAT7__USDHC3_DAT7_100MHZ IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD3_DAT7__USDHC3_DAT7_200MHZ IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD3_DAT7__UART1_TXD IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_DAT7__UART1_RXD IOMUX_PAD(0x0718, 0x0330, 1, 0x08FC, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT7__GPIO_6_17 IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD3_RST__USDHC3_RST IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_RST__UART3_CTS IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_RST__UART3_RTS IOMUX_PAD(0x071C, 0x0334, 1, 0x0908, 5, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD3_RST__GPIO_7_8 IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0)
+#define MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0)
+
+#define MX6_PAD_SD4_CLK__USDHC4_CLK_50MHZ IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD4_CLK__USDHC4_CLK_100MHZ IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD4_CLK__USDHC4_CLK_200MHZ IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD4_CLK__RAWNAND_WRN IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, MX6_GPMI_PAD_CTRL2)
+#define MX6_PAD_SD4_CLK__UART3_TXD IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD4_CLK__UART3_RXD IOMUX_PAD(0x0720, 0x0338, 2, 0x090C, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD4_CLK__GPIO_7_10 IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0)
+
+#define MX6_PAD_SD4_CMD__USDHC4_CMD_50MHZ IOMUX_PAD(0x0724, 0x033C, 0 | MUX_CONFIG_SION, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD4_CMD__USDHC4_CMD_100MHZ IOMUX_PAD(0x0724, 0x033C, 0 | MUX_CONFIG_SION, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD4_CMD__USDHC4_CMD_200MHZ IOMUX_PAD(0x0724, 0x033C, 0 | MUX_CONFIG_SION, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD4_CMD__RAWNAND_RDN IOMUX_PAD(0x0724, 0x033C, 1, 0x0000, 0, MX6_GPMI_PAD_CTRL2)
+#define MX6_PAD_SD4_CMD__UART3_TXD IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD4_CMD__UART3_RXD IOMUX_PAD(0x0724, 0x033C, 2, 0x090C, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD4_CMD__GPIO_7_9 IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0)
+
+#define MX6_PAD_SD4_DAT0__RAWNAND_D8 IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD4_DAT0__USDHC4_DAT0_100MHZ IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD4_DAT0__USDHC4_DAT0_200MHZ IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD4_DAT0__RAWNAND_DQS IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, MX6_GPMI_PAD_CTRL1)
+#define MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT0__GPIO_2_8 IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_SD4_DAT1__RAWNAND_D9 IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD4_DAT1__USDHC4_DAT1_100MHZ IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD4_DAT1__USDHC4_DAT1_200MHZ IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD4_DAT1__PWM3_PWMO IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT1__GPIO_2_9 IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_SD4_DAT2__RAWNAND_D10 IOMUX_PAD(0x0730, 0x0348, 0, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD4_DAT2__USDHC4_DAT2_100MHZ IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD4_DAT2__USDHC4_DAT2_200MHZ IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD4_DAT2__PWM4_PWMO IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 IOMUX_PAD(0x0730, 0x0348, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT2__GPIO_2_10 IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 IOMUX_PAD(0x0730, 0x0348, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_SD4_DAT3__RAWNAND_D11 IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD4_DAT3__USDHC4_DAT3_100MHZ IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD4_DAT3__USDHC4_DAT3_200MHZ IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT3__GPIO_2_11 IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_SD4_DAT4__RAWNAND_D12 IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD4_DAT4__USDHC4_DAT4_100MHZ IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD4_DAT4__USDHC4_DAT4_200MHZ IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD4_DAT4__UART2_TXD IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD4_DAT4__UART2_RXD IOMUX_PAD(0x0738, 0x0350, 2, 0x0904, 6, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 IOMUX_PAD(0x0738, 0x0350, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT4__GPIO_2_12 IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_SD4_DAT5__RAWNAND_D13 IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD4_DAT5__USDHC4_DAT5_100MHZ IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD4_DAT5__USDHC4_DAT5_200MHZ IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD4_DAT5__UART2_CTS IOMUX_PAD(0x073C, 0x0354, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD4_DAT5__UART2_RTS IOMUX_PAD(0x073C, 0x0354, 2, 0x0900, 4, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 IOMUX_PAD(0x073C, 0x0354, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT5__GPIO_2_13 IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_SD4_DAT6__RAWNAND_D14 IOMUX_PAD(0x0740, 0x0358, 0, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD4_DAT6__USDHC4_DAT6_100MHZ IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD4_DAT6__USDHC4_DAT6_200MHZ IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD4_DAT6__UART2_CTS IOMUX_PAD(0x0740, 0x0358, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD4_DAT6__UART2_RTS IOMUX_PAD(0x0740, 0x0358, 2, 0x0900, 5, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 IOMUX_PAD(0x0740, 0x0358, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT6__GPIO_2_14 IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 IOMUX_PAD(0x0740, 0x0358, 6, 0x0000, 0, 0)
+
+#define MX6_PAD_SD4_DAT7__RAWNAND_D15 IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD4_DAT7__USDHC4_DAT7_100MHZ IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD4_DAT7__USDHC4_DAT7_200MHZ IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD4_DAT7__UART2_TXD IOMUX_PAD(0x0744, 0x035C, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD4_DAT7__UART2_RXD IOMUX_PAD(0x0744, 0x035C, 2, 0x0904, 7, 0)
+#define MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 IOMUX_PAD(0x0744, 0x035C, 3, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT7__GPIO_2_15 IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0)
+#define MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0)
+
+#endif /* __ASM_ARCH_IOMUX_MX6DL_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Auto Generate file, please don't edit it
+ *
+ */
+
+#ifndef __ASM_ARCH_IOMUX_MX6Q_H__
+#define __ASM_ARCH_IOMUX_MX6Q_H__
+
+#define MX6_PAD_SD2_DAT1__USDHC2_DAT1 IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD2_DAT1__ECSPI5_SS0 IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT1__WEIM_WEIM_CS_2 IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT1__KPP_COL_7 IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT1__GPIO_1_14 IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT1__CCM_WAIT IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD2_DAT2__USDHC2_DAT2 IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD2_DAT2__ECSPI5_SS1 IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT2__WEIM_WEIM_CS_3 IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXD IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT2__KPP_ROW_6 IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT2__GPIO_1_13 IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT2__CCM_STOP IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD2_DAT0__USDHC2_DAT0 IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD2_DAT0__ECSPI5_MISO IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT0__KPP_ROW_7 IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT0__GPIO_1_15 IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT0__DCIC2_DCIC_OUT IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_RGMII_TXC__USBOH3_H2_DATA IOMUX_PAD(0x036C, 0x0058, 0 | MUX_CONFIG_SION, 0x0000, 0, MUX_PAD_CTRL(MX6_USB_HSIC_PAD_CTRL))
+#define MX6_PAD_RGMII_TXC__ENET_RGMII_TXC IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_ENET_PAD_CTRL))
+#define MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_TXC__GPIO_6_19 IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_ENET_PAD_CTRL))
+#define MX6_PAD_RGMII_TD0__GPIO_6_20 IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_ENET_PAD_CTRL))
+#define MX6_PAD_RGMII_TD1__GPIO_6_21 IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_TD1__CCM_PLL3_BYP IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_ENET_PAD_CTRL))
+#define MX6_PAD_RGMII_TD2__GPIO_6_22 IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_TD2__CCM_PLL2_BYP IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_ENET_PAD_CTRL))
+#define MX6_PAD_RGMII_TD3__GPIO_6_23 IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA IOMUX_PAD(0x0380, 0x006C, 0 | MUX_CONFIG_SION, 0x0000, 0, MUX_PAD_CTRL(MX6_USB_HSIC_PAD_CTRL))
+#define MX6_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, MUX_PAD_CTRL(MX6_ENET_PAD_CTRL))
+#define MX6_PAD_RGMII_RX_CTL__GPIO_6_24 IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, MUX_PAD_CTRL(MX6_ENET_PAD_CTRL))
+#define MX6_PAD_RGMII_RD0__GPIO_6_25 IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE IOMUX_PAD(0x0388, 0x0074, 0 | MUX_CONFIG_SION, 0x0000, 0, MUX_PAD_CTRL(MX6_USB_HSIC_PAD_CTRL))
+#define MX6_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_ENET_PAD_CTRL))
+#define MX6_PAD_RGMII_TX_CTL__GPIO_6_26 IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, MUX_PAD_CTRL(MX6_ENET_PAD_CTRL))
+#define MX6_PAD_RGMII_RD1__GPIO_6_27 IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_RD1__SJC_FAIL IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, MUX_PAD_CTRL(MX6_ENET_PAD_CTRL))
+#define MX6_PAD_RGMII_RD2__GPIO_6_28 IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, MUX_PAD_CTRL(MX6_ENET_PAD_CTRL))
+#define MX6_PAD_RGMII_RD3__GPIO_6_29 IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE IOMUX_PAD(0x0398, 0x0084, 0 | MUX_CONFIG_SION, 0x0000, 0, MUX_PAD_CTRL(MX6_USB_HSIC_PAD_CTRL))
+#define MX6_PAD_RGMII_RXC__ENET_RGMII_RXC IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, MUX_PAD_CTRL(MX6_ENET_PAD_CTRL))
+#define MX6_PAD_RGMII_RXC__GPIO_6_30 IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_A25__WEIM_WEIM_A_25 IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A25__ECSPI4_SS1 IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A25__IPU1_DI1_PIN12 IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A25__IPU1_DI0_D1_CS IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A25__GPIO_5_2 IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, MUX_PAD_CTRL(MX6_HDMICEC_PAD_CTRL))
+#define MX6_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_EB2__WEIM_WEIM_EB_2 IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, MUX_PAD_CTRL(MX6_ECSPI_PAD_CTRL))
+#define MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB2__IPU2_CSI1_D_19 IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB2__GPIO_2_30 IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x03A0, 0x008C, 6 | MUX_CONFIG_SION, 0x08A0, 0, MUX_PAD_CTRL(MX6_I2C_PAD_CTRL))
+#define MX6_PAD_EIM_EB2__SRC_BT_CFG_30 IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_D16__WEIM_WEIM_D_16 IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, MUX_PAD_CTRL(MX6_ECSPI_PAD_CTRL))
+#define MX6_PAD_EIM_D16__IPU1_DI0_PIN5 IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D16__IPU2_CSI1_D_18 IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x03A4, 0x0090, 6 | MUX_CONFIG_SION, 0x08A4, 0, MUX_PAD_CTRL(MX6_I2C_PAD_CTRL))
+
+#define MX6_PAD_EIM_D17__WEIM_WEIM_D_17 IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, MUX_PAD_CTRL(MX6_ECSPI_PAD_CTRL))
+#define MX6_PAD_EIM_D17__IPU1_DI0_PIN6 IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D17__IPU2_CSI1_PIXCLK IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D17__DCIC1_DCIC_OUT IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x03A8, 0x0094, 6 | MUX_CONFIG_SION, 0x08A8, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_D18__WEIM_WEIM_D_18 IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, MUX_PAD_CTRL(MX6_ECSPI_PAD_CTRL))
+#define MX6_PAD_EIM_D18__IPU1_DI0_PIN7 IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D18__IPU2_CSI1_D_17 IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D18__IPU1_DI1_D0_CS IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x03AC, 0x0098, 6 | MUX_CONFIG_SION, 0x08AC, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_D19__WEIM_WEIM_D_19 IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, MUX_PAD_CTRL(MX6_ECSPI_PAD_CTRL))
+#define MX6_PAD_EIM_D19__IPU1_DI0_PIN8 IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D19__IPU2_CSI1_D_16 IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D19__GPIO_3_19 IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, MUX_PAD_CTRL(MX6_ECSPI_PAD_CTRL))
+#define MX6_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D19__PL301_MX6QPER1_HRESP IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_D20__WEIM_WEIM_D_20 IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_D20__ECSPI4_SS0 IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D20__IPU1_DI0_PIN16 IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D20__IPU2_CSI1_D_15 IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D20__UART1_CTS IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D20__GPIO_3_20 IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_D21__WEIM_WEIM_D_21 IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_D21__ECSPI4_SCLK IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D21__IPU1_DI0_PIN17 IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D21__IPU2_CSI1_D_11 IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D21__GPIO_3_21 IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x03B8, 0x00A4, 6 | MUX_CONFIG_SION, 0x0898, 0, MUX_PAD_CTRL(MX6_I2C_PAD_CTRL))
+#define MX6_PAD_EIM_D21__SPDIF_IN1 IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_D22__WEIM_WEIM_D_22 IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_D22__ECSPI4_MISO IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D22__IPU1_DI0_PIN1 IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D22__IPU2_CSI1_D_10 IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D22__GPIO_3_22 IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D22__SPDIF_OUT1 IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D22__PL301_MX6QPER1_HWRITE IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_D23__WEIM_WEIM_D_23 IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_D23__IPU1_DI0_D0_CS IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D23__IPU2_CSI1_DATA_EN IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D23__GPIO_3_23 IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D23__IPU1_DI1_PIN2 IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D23__IPU1_DI1_PIN14 IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_EB3__WEIM_WEIM_EB_3 IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB3__ECSPI4_RDY IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB3__UART3_CTS IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_EB3__IPU2_CSI1_HSYNC IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB3__GPIO_2_31 IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB3__IPU1_DI1_PIN3 IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB3__SRC_BT_CFG_31 IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_D24__WEIM_WEIM_D_24 IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_D24__ECSPI4_SS2 IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D24__UART3_TXD IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D24__UART3_RXD IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D24__GPIO_3_24 IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, MUX_PAD_CTRL(MX6_HIGH_DRV))
+#define MX6_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+
+#define MX6_PAD_EIM_D25__WEIM_WEIM_D_25 IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_D25__ECSPI4_SS3 IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D25__UART3_TXD IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D25__GPIO_3_25 IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+
+#define MX6_PAD_EIM_D26__WEIM_WEIM_D_26 IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_D26__IPU1_DI1_PIN11 IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D26__IPU1_CSI0_D_1 IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D26__IPU2_CSI1_D_14 IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D26__UART2_TXD IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D26__UART2_RXD IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D26__GPIO_3_26 IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D26__IPU1_SISG_2 IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D26__IPU1_DISP1_DAT_22 IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_D27__WEIM_WEIM_D_27 IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_D27__IPU1_DI1_PIN13 IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D27__IPU1_CSI0_D_0 IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D27__IPU2_CSI1_D_13 IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D27__UART2_TXD IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D27__UART2_RXD IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D27__GPIO_3_27 IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D27__IPU1_SISG_3 IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D27__IPU1_DISP1_DAT_23 IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_D28__WEIM_WEIM_D_28 IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x03D8, 0x00C4, 1 | MUX_CONFIG_SION, 0x089C, 0, MUX_PAD_CTRL(MX6_I2C_PAD_CTRL))
+#define MX6_PAD_EIM_D28__ECSPI4_MOSI IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D28__IPU2_CSI1_D_12 IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D28__UART2_RTS IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D28__GPIO_3_28 IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, MUX_PAD_CTRL(MX6_HIGH_DRV))
+#define MX6_PAD_EIM_D28__IPU1_EXT_TRIG IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D28__IPU1_DI0_PIN13 IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_D29__WEIM_WEIM_D_29 IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_D29__IPU1_DI1_PIN15 IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D29__ECSPI4_SS0 IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D29__UART2_CTS IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D29__GPIO_3_29 IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D29__IPU2_CSI1_VSYNC IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D29__IPU1_DI0_PIN14 IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_D30__WEIM_WEIM_D_30 IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_D30__IPU1_DISP1_DAT_21 IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D30__IPU1_DI0_PIN11 IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D30__IPU1_CSI0_D_3 IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D30__GPIO_3_30 IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_D31__WEIM_WEIM_D_31 IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20 IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D31__IPU1_DI0_PIN12 IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D31__IPU1_CSI0_D_2 IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D31__UART3_CTS IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_EIM_D31__GPIO_3_31 IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_A24__WEIM_WEIM_A_24 IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19 IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A24__IPU2_CSI1_D_19 IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A24__IPU2_SISG_2 IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A24__IPU1_SISG_2 IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A24__SRC_BT_CFG_24 IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_A23__WEIM_WEIM_A_23 IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18 IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A23__IPU2_CSI1_D_18 IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A23__IPU2_SISG_3 IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A23__IPU1_SISG_3 IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A23__GPIO_6_6 IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A23__SRC_BT_CFG_23 IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_A22__WEIM_WEIM_A_22 IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17 IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A22__IPU2_CSI1_D_17 IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A22__TPSMP_HDATA_0 IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A22__SRC_BT_CFG_22 IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_A21__WEIM_WEIM_A_21 IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16 IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A21__IPU2_CSI1_D_16 IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A21__RESERVED_RESERVED IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A21__GPIO_2_17 IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A21__TPSMP_HDATA_1 IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A21__SRC_BT_CFG_21 IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_A20__WEIM_WEIM_A_20 IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15 IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A20__IPU2_CSI1_D_15 IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A20__RESERVED_RESERVED IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A20__GPIO_2_18 IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A20__TPSMP_HDATA_2 IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A20__SRC_BT_CFG_20 IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_A19__WEIM_WEIM_A_19 IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14 IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A19__IPU2_CSI1_D_14 IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A19__RESERVED_RESERVED IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A19__GPIO_2_19 IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A19__TPSMP_HDATA_3 IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A19__SRC_BT_CFG_19 IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_A18__WEIM_WEIM_A_18 IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13 IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A18__IPU2_CSI1_D_13 IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A18__RESERVED_RESERVED IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A18__GPIO_2_20 IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A18__TPSMP_HDATA_4 IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A18__SRC_BT_CFG_18 IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_A17__WEIM_WEIM_A_17 IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12 IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A17__IPU2_CSI1_D_12 IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A17__RESERVED_RESERVED IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A17__GPIO_2_21 IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A17__TPSMP_HDATA_5 IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A17__SRC_BT_CFG_17 IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_A16__WEIM_WEIM_A_16 IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A16__IPU2_CSI1_PIXCLK IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A16__GPIO_2_22 IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A16__TPSMP_HDATA_6 IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_A16__SRC_BT_CFG_16 IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_CS0__WEIM_WEIM_CS_0 IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_CS0__IPU1_DI1_PIN5 IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_CS0__GPIO_2_23 IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_CS0__TPSMP_HDATA_7 IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_CS1__WEIM_WEIM_CS_1 IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_CS1__IPU1_DI1_PIN6 IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_CS1__GPIO_2_24 IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_CS1__TPSMP_HDATA_8 IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_OE__WEIM_WEIM_OE IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_OE__IPU1_DI1_PIN7 IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_OE__GPIO_2_25 IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_OE__TPSMP_HDATA_9 IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_RW__WEIM_WEIM_RW IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_RW__IPU1_DI1_PIN8 IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_RW__GPIO_2_26 IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_RW__TPSMP_HDATA_10 IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_RW__SRC_BT_CFG_29 IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_LBA__WEIM_WEIM_LBA IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_LBA__GPIO_2_27 IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_LBA__TPSMP_HDATA_11 IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_LBA__SRC_BT_CFG_26 IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_EB0__WEIM_WEIM_EB_0 IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11 IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB0__IPU2_CSI1_D_11 IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB0__CCM_PMIC_RDY IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB0__GPIO_2_28 IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB0__TPSMP_HDATA_12 IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB0__SRC_BT_CFG_27 IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_EB1__WEIM_WEIM_EB_1 IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10 IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB1__IPU2_CSI1_D_10 IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB1__GPIO_2_29 IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB1__TPSMP_HDATA_13 IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_EB1__SRC_BT_CFG_28 IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9 IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA0__IPU2_CSI1_D_9 IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA0__GPIO_3_0 IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA0__TPSMP_HDATA_14 IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA0__SRC_BT_CFG_0 IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8 IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA1__IPU2_CSI1_D_8 IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA1__GPIO_3_1 IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA1__TPSMP_HDATA_15 IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA1__SRC_BT_CFG_1 IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7 IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA2__IPU2_CSI1_D_7 IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA2__GPIO_3_2 IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA2__TPSMP_HDATA_16 IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA2__SRC_BT_CFG_2 IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6 IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA3__IPU2_CSI1_D_6 IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA3__GPIO_3_3 IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA3__TPSMP_HDATA_17 IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA3__SRC_BT_CFG_3 IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5 IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA4__IPU2_CSI1_D_5 IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA4__GPIO_3_4 IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA4__TPSMP_HDATA_18 IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA4__SRC_BT_CFG_4 IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4 IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA5__IPU2_CSI1_D_4 IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA5__GPIO_3_5 IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA5__TPSMP_HDATA_19 IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA5__SRC_BT_CFG_5 IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3 IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA6__IPU2_CSI1_D_3 IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA6__GPIO_3_6 IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA6__TPSMP_HDATA_20 IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA6__SRC_BT_CFG_6 IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2 IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA7__IPU2_CSI1_D_2 IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA7__GPIO_3_7 IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA7__TPSMP_HDATA_21 IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA7__SRC_BT_CFG_7 IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1 IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA8__IPU2_CSI1_D_1 IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA8__GPIO_3_8 IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA8__TPSMP_HDATA_22 IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA8__SRC_BT_CFG_8 IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0 IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA9__IPU2_CSI1_D_0 IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA9__GPIO_3_9 IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA9__TPSMP_HDATA_23 IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA9__SRC_BT_CFG_9 IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA10__IPU2_CSI1_DATA_EN IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA10__GPIO_3_10 IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA10__TPSMP_HDATA_24 IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA10__SRC_BT_CFG_10 IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_DA11__IPU1_DI1_PIN2 IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA11__IPU2_CSI1_HSYNC IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA11__GPIO_3_11 IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA11__TPSMP_HDATA_25 IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA11__SRC_BT_CFG_11 IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_DA12__IPU1_DI1_PIN3 IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA12__IPU2_CSI1_VSYNC IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA12__GPIO_3_12 IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA12__TPSMP_HDATA_26 IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA12__SRC_BT_CFG_12 IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA13__GPIO_3_13 IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA13__TPSMP_HDATA_27 IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA13__SRC_BT_CFG_13 IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA14__GPIO_3_14 IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA14__TPSMP_HDATA_28 IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA14__SRC_BT_CFG_14 IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_WEIM_NOR_PAD_CTRL))
+#define MX6_PAD_EIM_DA15__IPU1_DI1_PIN1 IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA15__IPU1_DI1_PIN4 IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA15__GPIO_3_15 IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA15__TPSMP_HDATA_29 IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_DA15__SRC_BT_CFG_15 IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_WAIT__WEIM_WEIM_WAIT IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_WAIT__GPIO_5_0 IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, MUX_PAD_CTRL(MX6_HIGH_DRV))
+#define MX6_PAD_EIM_WAIT__TPSMP_HDATA_30 IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_WAIT__SRC_BT_CFG_25 IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_BCLK__GPIO_6_31 IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EIM_BCLK__TPSMP_HDATA_31 IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_DISP_CLK__GPIO_4_16 IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15 IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN15__GPIO_4_17 IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DI0_PIN2__IPU2_DI0_PIN2 IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN2__GPIO_4_18 IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DI0_PIN3__IPU2_DI0_PIN3 IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN3__GPIO_4_19 IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN4__IPU2_DI0_PIN4 IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN4__USDHC1_WP IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN4__GPIO_4_20 IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT0__ECSPI3_SCLK IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT0__GPIO_4_21 IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT1__ECSPI3_MOSI IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT1__GPIO_4_22 IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT2__ECSPI3_MISO IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT2__GPIO_4_23 IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT3__ECSPI3_SS0 IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT3__GPIO_4_24 IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT4__ECSPI3_SS1 IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT4__GPIO_4_25 IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT5__ECSPI3_SS2 IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT5__GPIO_4_26 IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT6__ECSPI3_SS3 IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT6__GPIO_4_27 IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT7__ECSPI3_RDY IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT7__GPIO_4_28 IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT8__GPIO_4_29 IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT9__GPIO_4_30 IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT11__GPIO_5_5 IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT12__RESERVED_RESERVED IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT12__GPIO_5_6 IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT13__GPIO_5_7 IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT14__GPIO_5_8 IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT15__GPIO_5_9 IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_DISP_PAD_CTRL))
+#define MX6_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ENET_MDIO__RESERVED_RESERVED IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_MDIO__ENET_MDIO IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, MUX_PAD_CTRL(MX6_ENET_PAD_CTRL))
+#define MX6_PAD_ENET_MDIO__ESAI1_SCKR IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, MUX_PAD_CTRL(MX6_ESAI_PAD_CTRL))
+#define MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_MDIO__GPIO_1_22 IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_MDIO__SPDIF_PLOCK IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ENET_REF_CLK__RESERVED_RESERVED IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_REF_CLK__ENET_TX_CLK IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_ENET_REF_CLK_PAD_CTRL))
+#define MX6_PAD_ENET_REF_CLK__ESAI1_FSR IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, MUX_PAD_CTRL(MX6_ESAI_PAD_CTRL))
+#define MX6_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_REF_CLK__GPIO_1_23 IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_REF_CLK__SPDIF_SRCLK IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ENET_RX_ER__ANATOP_USBOTG_ID IOMUX_PAD(0x04EC, 0x01D8, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_RX_ER__ENET_RX_ER IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_RX_ER__ESAI1_HCKR IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, MUX_PAD_CTRL(MX6_ESAI_PAD_CTRL))
+#define MX6_PAD_ENET_RX_ER__SPDIF_IN1 IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, NO_PAD_CTRL)
+#define MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_RX_ER__GPIO_1_24 IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_RX_ER__PHY_TDI IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ENET_CRS_DV__RESERVED_RESERVED IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_CRS_DV__ENET_RX_EN IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, NO_PAD_CTRL)
+#define MX6_PAD_ENET_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, MUX_PAD_CTRL(MX6_ESAI_PAD_CTRL))
+#define MX6_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, NO_PAD_CTRL)
+#define MX6_PAD_ENET_CRS_DV__GPIO_1_25 IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_CRS_DV__PHY_TDO IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ENET_RXD1__MLB_MLBSIG IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_RXD1__ENET_RDATA_1 IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, NO_PAD_CTRL)
+#define MX6_PAD_ENET_RXD1__ESAI1_FST IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, MUX_PAD_CTRL(MX6_ESAI_PAD_CTRL))
+#define MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_RXD1__GPIO_1_26 IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_RXD1__PHY_TCK IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ENET_RXD0__OSC32K_32K_OUT IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_RXD0__ENET_RDATA_0 IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, NO_PAD_CTRL)
+#define MX6_PAD_ENET_RXD0__ESAI1_HCKT IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, MUX_PAD_CTRL(MX6_ESAI_PAD_CTRL))
+#define MX6_PAD_ENET_RXD0__SPDIF_OUT1 IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_RXD0__GPIO_1_27 IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_RXD0__PHY_TMS IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ENET_TX_EN__RESERVED_RESERVED IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_TX_EN__ENET_TX_EN IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, MUX_PAD_CTRL(MX6_ESAI_PAD_CTRL))
+#define MX6_PAD_ENET_TX_EN__GPIO_1_28 IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_TX_EN__SATA_PHY_TDI IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ENET_TXD1__MLB_MLBCLK IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_TXD1__ENET_TDATA_1 IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, MUX_PAD_CTRL(MX6_ESAI_PAD_CTRL))
+#define MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_TXD1__GPIO_1_29 IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_TXD1__SATA_PHY_TDO IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ENET_TXD0__RESERVED_RESERVED IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_TXD0__ENET_TDATA_0 IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, MUX_PAD_CTRL(MX6_ESAI_PAD_CTRL))
+#define MX6_PAD_ENET_TXD0__GPIO_1_30 IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_TXD0__SATA_PHY_TCK IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ENET_MDC__MLB_MLBDAT IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_MDC__ENET_MDC IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_ENET_PAD_CTRL))
+#define MX6_PAD_ENET_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, MUX_PAD_CTRL(MX6_ESAI_PAD_CTRL))
+#define MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_MDC__GPIO_1_31 IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_MDC__SATA_PHY_TMS IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A0__MMDC_DRAM_A_0 IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A1__MMDC_DRAM_A_1 IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A2__MMDC_DRAM_A_2 IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A3__MMDC_DRAM_A_3 IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A4__MMDC_DRAM_A_4 IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A5__MMDC_DRAM_A_5 IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A6__MMDC_DRAM_A_6 IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A7__MMDC_DRAM_A_7 IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A8__MMDC_DRAM_A_8 IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A9__MMDC_DRAM_A_9 IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A10__MMDC_DRAM_A_10 IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A11__MMDC_DRAM_A_11 IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A12__MMDC_DRAM_A_12 IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A13__MMDC_DRAM_A_13 IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A14__MMDC_DRAM_A_14 IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A15__MMDC_DRAM_A_15 IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_CAS__MMDC_DRAM_CAS IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_CS0__MMDC_DRAM_CS_0 IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_CS1__MMDC_DRAM_CS_1 IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_RAS__MMDC_DRAM_RAS IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_RESET__MMDC_DRAM_RESET IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL0__ENET_RDATA_3 IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL0__UART4_TXD IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_KEY_COL0__UART4_RXD IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_KEY_COL0__GPIO_4_6 IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL0__DCIC1_DCIC_OUT IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW0__ENET_TDATA_3 IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW0__UART4_TXD IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_KEY_ROW0__UART4_RXD IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_KEY_ROW0__GPIO_4_7 IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL1__ENET_MDIO IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, MUX_PAD_CTRL(MX6_ENET_PAD_CTRL))
+#define MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL1__UART5_TXD IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_KEY_COL1__UART5_RXD IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_KEY_COL1__GPIO_4_8 IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL1__USDHC1_VSELECT IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW1__ENET_COL IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW1__UART5_TXD IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_KEY_ROW1__UART5_RXD IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_KEY_ROW1__GPIO_4_9 IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW1__USDHC2_VSELECT IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL2__ENET_RDATA_2 IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL2__ENET_MDC IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_ENET_PAD_CTRL))
+#define MX6_PAD_KEY_COL2__GPIO_4_10 IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW2__ENET_TDATA_2 IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW2__USDHC2_VSELECT IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_KEY_ROW2__GPIO_4_11 IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, MUX_PAD_CTRL(MX6_HDMICEC_PAD_CTRL))
+#define MX6_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL3__ENET_CRS IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL IOMUX_PAD(0x05E0, 0x0210, 2 | MUX_CONFIG_SION, 0x0890, 1, MUX_PAD_CTRL(MX6_I2C_PAD_CTRL))
+#define MX6_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x05E0, 0x0210, 4 | MUX_CONFIG_SION, 0x08A0, 1, MUX_PAD_CTRL(MX6_I2C_PAD_CTRL))
+#define MX6_PAD_KEY_COL3__GPIO_4_12 IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA IOMUX_PAD(0x05E4, 0x0214, 2 | MUX_CONFIG_SION, 0x0894, 1, MUX_PAD_CTRL(MX6_I2C_PAD_CTRL))
+#define MX6_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x05E4, 0x0214, 4 | MUX_CONFIG_SION, 0x08A4, 1, MUX_PAD_CTRL(MX6_I2C_PAD_CTRL))
+#define MX6_PAD_KEY_ROW3__GPIO_4_13 IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW3__USDHC1_VSELECT IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL4__IPU1_SISG_4 IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL4__UART5_CTS IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_KEY_COL4__GPIO_4_14 IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW4__IPU1_SISG_5 IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x05EC, 0x021C, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_KEY_ROW4__GPIO_4_15 IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_CCM_CLK0_PAD_CTRL))
+#define MX6_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_0__GPIO_1_0 IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_1__USBOTG_ID IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_1__GPIO_1_1 IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_1__USDHC1_CD IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, MUX_PAD_CTRL(MX6_ESAI_PAD_CTRL))
+#define MX6_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_HIGH_DRV))
+#define MX6_PAD_GPIO_9__GPIO_1_9 IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, MUX_PAD_CTRL(MX6_HIGH_DRV))
+#define MX6_PAD_GPIO_9__USDHC1_WP IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_GPIO_9__SRC_EARLY_RST IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x05FC, 0x022C, 2 | MUX_CONFIG_SION, 0x08A8, 1, MUX_PAD_CTRL(MX6_I2C_PAD_CTRL))
+#define MX6_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_3__GPIO_1_3 IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, MUX_PAD_CTRL(MX6_MLB150_PAD_CTRL))
+
+#define MX6_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, MUX_PAD_CTRL(ENET_IRQ_PAD_CTRL))
+#define MX6_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x0600, 0x0230, 2 | MUX_CONFIG_SION, 0x08AC, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_6__GPIO_1_6 IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_6__USDHC2_LCTL IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, MUX_PAD_CTRL(MX6_MLB150_PAD_CTRL))
+
+#define MX6_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_2__GPIO_1_2 IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_2__USDHC2_WP IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, MUX_PAD_CTRL(MX6_MLB150_PAD_CTRL))
+
+#define MX6_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_4__GPIO_1_4 IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_4__USDHC2_CD IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, MUX_PAD_CTRL(MX6_ESAI_PAD_CTRL))
+#define MX6_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_5__GPIO_1_5 IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x060C, 0x023C, 6 | MUX_CONFIG_SION, 0x08A8, 2, MUX_PAD_CTRL(MX6_I2C_PAD_CTRL))
+#define MX6_PAD_GPIO_5__CHEETAH_EVENTI IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_7__ECSPI5_RDY IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_7__UART2_TXD IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_GPIO_7__UART2_RXD IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_GPIO_7__GPIO_1_7 IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_8__UART2_TXD IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_GPIO_8__UART2_RXD IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_GPIO_8__GPIO_1_8 IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT IOMUX_PAD(0x0618, 0x0248, 0x12, 0x083C, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_16__USDHC1_LCTL IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_16__GPIO_7_11 IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x0618, 0x0248, 6 | MUX_CONFIG_SION, 0x08AC, 2, MUX_PAD_CTRL(MX6_I2C_PAD_CTRL))
+#define MX6_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, MUX_PAD_CTRL(MX6_ESAI_PAD_CTRL))
+#define MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_17__CCM_PMIC_RDY IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_SPDIF_OUT_PAD_CTRL))
+#define MX6_PAD_GPIO_17__GPIO_7_12 IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_18__ENET_RX_CLK IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_18__USDHC3_VSELECT IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_18__ASRC_ASRC_EXT_CLK IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_18__GPIO_7_13 IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_19__GPIO_4_5 IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_19__ENET_TX_ER IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_PIXCLK__CHEETAH_EVENTO IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_MCLK__CCM_CLKO IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_CCM_CLK0_PAD_CTRL))
+#define MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_MCLK__GPIO_5_19 IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_MCLK__CHEETAH_TRCTL IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DATA_EN__GPIO_5_20 IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DATA_EN__CHEETAH_TRCLK IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_VSYNC__GPIO_5_21 IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4 IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2 IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT4__GPIO_5_22 IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT4__CHEETAH_TRACE_1 IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5 IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3 IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_ADU_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT5__GPIO_5_23 IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, MUX_PAD_CTRL(MX6_HIGH_DRV))
+#define MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT5__CHEETAH_TRACE_2 IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6 IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4 IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT6__GPIO_5_24 IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT6__CHEETAH_TRACE_3 IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7 IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5 IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, MUX_PAD_CTRL(MX6_ADU_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT7__GPIO_5_25 IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, MUX_PAD_CTRL(MX6_HIGH_DRV))
+#define MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT7__CHEETAH_TRACE_4 IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8 IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6 IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x0648, 0x0278, 4 | MUX_CONFIG_SION, 0x089C, 1, MUX_PAD_CTRL(MX6_I2C_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT8__GPIO_5_26 IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT8__CHEETAH_TRACE_5 IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9 IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7 IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x064C, 0x027C, 4 | MUX_CONFIG_SION, 0x0898, 1, MUX_PAD_CTRL(MX6_I2C_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT9__GPIO_5_27 IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT9__CHEETAH_TRACE_6 IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DAT10__IPU1_CSI0_D_10 IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT10__UART1_TXD IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT10__UART1_RXD IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT10__GPIO_5_28 IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT10__CHEETAH_TRACE_7 IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11 IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT11__UART1_TXD IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT11__UART1_RXD IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT11__GPIO_5_29 IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT11__CHEETAH_TRACE_8 IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12 IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8 IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT12__UART4_TXD IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT12__UART4_RXD IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT12__GPIO_5_30 IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT12__CHEETAH_TRACE_9 IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13 IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9 IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT13__UART4_TXD IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT13__UART4_RXD IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT13__GPIO_5_31 IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT13__CHEETAH_TRACE_10 IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14 IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10 IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT14__UART5_TXD IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT14__UART5_RXD IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT14__GPIO_6_0 IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT14__CHEETAH_TRACE_11 IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15 IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11 IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT15__UART5_TXD IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT15__UART5_RXD IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT15__GPIO_6_1 IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT15__CHEETAH_TRACE_12 IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16 IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12 IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT16__UART4_CTS IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT16__GPIO_6_2 IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT16__CHEETAH_TRACE_13 IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17 IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13 IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT17__GPIO_6_3 IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT17__CHEETAH_TRACE_14 IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18 IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14 IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT18__UART5_CTS IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT18__GPIO_6_4 IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT18__CHEETAH_TRACE_15 IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19 IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15 IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT19__GPIO_6_5 IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_JTAG_TMS__SJC_TMS IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_JTAG_MOD__SJC_MOD IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_JTAG_TRSTB__SJC_TRSTB IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_JTAG_TDI__SJC_TDI IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_JTAG_TCK__SJC_TCK IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_JTAG_TDO__SJC_TDO IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_DAT7__USDHC3_DAT7 IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD3_DAT7__UART1_TXD IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_DAT7__UART1_RXD IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT7__GPIO_6_17 IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_DAT6__USDHC3_DAT6 IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD3_DAT6__UART1_TXD IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_DAT6__UART1_RXD IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT6__GPIO_6_18 IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_DAT5__USDHC3_DAT5 IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD3_DAT5__UART2_TXD IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_DAT5__UART2_RXD IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT5__GPIO_7_0 IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_DAT4__USDHC3_DAT4 IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD3_DAT4__UART2_TXD IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_DAT4__UART2_RXD IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT4__GPIO_7_1 IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_CMD__USDHC3_CMD IOMUX_PAD(0x06A0, 0x02B8, 0 | MUX_CONFIG_SION, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD3_CMD__UART2_CTS IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_CMD__CAN1_TXCAN IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CMD__GPIO_7_2 IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_CLK__USDHC3_CLK IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD3_CLK__UART2_CTS IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_CLK__UART2_RTS IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_CLK__CAN1_RXCAN IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CLK__GPIO_7_3 IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_DAT0__USDHC3_DAT0 IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD3_DAT0__UART1_CTS IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_DAT0__CAN2_TXCAN IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT0__GPIO_7_4 IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_DAT1__USDHC3_DAT1 IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD3_DAT1__UART1_CTS IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_DAT1__UART1_RTS IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_DAT1__CAN2_RXCAN IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT1__GPIO_7_5 IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_DAT2__USDHC3_DAT2 IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT2__GPIO_7_6 IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_DAT3__USDHC3_DAT3 IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD3_DAT3__UART3_CTS IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT3__GPIO_7_7 IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_RST__USDHC3_RST IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD3_RST__UART3_CTS IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_RST__UART3_RTS IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_RST__GPIO_7_8 IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_NANDF_CLE__RAWNAND_CLE IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_NANDF_CLE__IPU2_SISG_4 IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CLE__GPIO_6_7 IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CLE__TPSMP_HTRANS_0 IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_NANDF_ALE__RAWNAND_ALE IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_NANDF_ALE__USDHC4_RST IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_ALE__GPIO_6_8 IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_ALE__TPSMP_HTRANS_1 IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_NANDF_WP_B__RAWNAND_RESETN IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_NANDF_WP_B__IPU2_SISG_5 IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_WP_B__GPIO_6_9 IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_NANDF_RB0__RAWNAND_READY0 IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL0))
+#define MX6_PAD_NANDF_RB0__IPU2_DI0_PIN1 IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_RB0__GPIO_6_10 IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_NANDF_CS0__RAWNAND_CE0N IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CS0__GPIO_6_11 IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_NANDF_CS1__RAWNAND_CE1N IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_NANDF_CS1__USDHC4_VSELECT IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_NANDF_CS1__USDHC3_VSELECT IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CS1__GPIO_6_14 IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_NANDF_CS2__RAWNAND_CE2N IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_NANDF_CS2__IPU1_SISG_0 IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, MUX_PAD_CTRL(MX6_ESAI_PAD_CTRL))
+#define MX6_PAD_NANDF_CS2__WEIM_WEIM_CRE IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CS2__CCM_CLKO2 IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CS2__GPIO_6_15 IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CS2__IPU2_SISG_0 IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_NANDF_CS3__RAWNAND_CE3N IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_NANDF_CS3__IPU1_SISG_1 IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, MUX_PAD_CTRL(MX6_ESAI_PAD_CTRL))
+#define MX6_PAD_NANDF_CS3__WEIM_WEIM_A_26 IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CS3__GPIO_6_16 IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CS3__IPU2_SISG_1 IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_CS3__TPSMP_CLK IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD4_CMD__USDHC4_CMD IOMUX_PAD(0x06DC, 0x02F4, 0 | MUX_CONFIG_SION, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD4_CMD__RAWNAND_RDN IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_SD4_CMD__UART3_TXD IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD4_CMD__UART3_RXD IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_CMD__GPIO_7_9 IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_CMD__TPSMP_HDATA_DIR IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD4_CLK__USDHC4_CLK IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD4_CLK__RAWNAND_WRN IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_SD4_CLK__UART3_TXD IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD4_CLK__UART3_RXD IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_CLK__GPIO_7_10 IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_NANDF_D0__RAWNAND_D0 IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_NANDF_D0__USDHC1_DAT4 IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D0__GPIO_2_0 IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_NANDF_D1__RAWNAND_D1 IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_NANDF_D1__USDHC1_DAT5 IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D1__GPIO_2_1 IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_NANDF_D2__RAWNAND_D2 IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_NANDF_D2__USDHC1_DAT6 IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D2__GPIO_2_2 IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_NANDF_D3__RAWNAND_D3 IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_NANDF_D3__USDHC1_DAT7 IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D3__GPIO_2_3 IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_NANDF_D4__RAWNAND_D4 IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_NANDF_D4__USDHC2_DAT4 IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D4__GPIO_2_4 IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_NANDF_D5__RAWNAND_D5 IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_NANDF_D5__USDHC2_DAT5 IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D5__GPIO_2_5 IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_NANDF_D6__RAWNAND_D6 IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_NANDF_D6__USDHC2_DAT6 IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D6__GPIO_2_6 IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_NANDF_D7__RAWNAND_D7 IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL2))
+#define MX6_PAD_NANDF_D7__USDHC2_DAT7 IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D7__GPIO_2_7 IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD4_DAT0__RAWNAND_D8 IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT0__USDHC4_DAT0 IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD4_DAT0__RAWNAND_DQS IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, MUX_PAD_CTRL(MX6_GPMI_PAD_CTRL1))
+#define MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT0__GPIO_2_8 IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD4_DAT1__RAWNAND_D9 IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT1__USDHC4_DAT1 IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD4_DAT1__PWM3_PWMO IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT1__GPIO_2_9 IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD4_DAT2__RAWNAND_D10 IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT2__USDHC4_DAT2 IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD4_DAT2__PWM4_PWMO IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT2__GPIO_2_10 IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD4_DAT3__RAWNAND_D11 IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT3__USDHC4_DAT3 IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT3__GPIO_2_11 IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD4_DAT4__RAWNAND_D12 IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT4__USDHC4_DAT4 IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD4_DAT4__UART2_TXD IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD4_DAT4__UART2_RXD IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT4__GPIO_2_12 IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD4_DAT5__RAWNAND_D13 IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT5__USDHC4_DAT5 IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD4_DAT5__UART2_CTS IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD4_DAT5__UART2_RTS IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT5__GPIO_2_13 IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD4_DAT6__RAWNAND_D14 IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT6__USDHC4_DAT6 IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD4_DAT6__UART2_CTS IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT6__GPIO_2_14 IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD4_DAT7__RAWNAND_D15 IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT7__USDHC4_DAT7 IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD4_DAT7__UART2_TXD IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD4_DAT7__UART2_RXD IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, MUX_PAD_CTRL(MX6_UART_PAD_CTRL))
+#define MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT7__GPIO_2_15 IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD1_DAT1__USDHC1_DAT1 IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD1_DAT1__ECSPI5_SS0 IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT1__PWM3_PWMO IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT1__GPT_CAPIN2 IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT1__GPIO_1_17 IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, MUX_PAD_CTRL(MX6_HIGH_DRV))
+#define MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD1_DAT0__USDHC1_DAT0 IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD1_DAT0__ECSPI5_MISO IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT0__GPT_CAPIN1 IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT0__GPIO_1_16 IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, MUX_PAD_CTRL(MX6_HIGH_DRV))
+#define MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD1_DAT3__USDHC1_DAT3 IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD1_DAT3__ECSPI5_SS2 IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT3__GPT_CMPOUT3 IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT3__PWM1_PWMO IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT3__WDOG2_WDOG_B IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT3__GPIO_1_21 IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD1_CMD__USDHC1_CMD IOMUX_PAD(0x0730, 0x0348, 0 | MUX_CONFIG_SION, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD1_CMD__ECSPI5_MOSI IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CMD__PWM4_PWMO IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CMD__GPIO_1_18 IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD1_DAT2__USDHC1_DAT2 IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD1_DAT2__ECSPI5_SS1 IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT2__GPT_CMPOUT2 IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT2__PWM2_PWMO IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT2__WDOG1_WDOG_B IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT2__GPIO_1_19 IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD1_CLK__USDHC1_CLK IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD1_CLK__ECSPI5_SCLK IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CLK__OSC32K_32K_OUT IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CLK__GPIO_1_20 IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CLK__PHY_DTB_0 IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CLK__SATA_PHY_DTB_0 IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD2_CLK__USDHC2_CLK IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD2_CLK__ECSPI5_SCLK IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CLK__GPIO_1_10 IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CLK__PHY_DTB_1 IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CLK__SATA_PHY_DTB_1 IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD2_CMD__USDHC2_CMD IOMUX_PAD(0x0740, 0x0358, 0 | MUX_CONFIG_SION, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD2_CMD__ECSPI5_MOSI IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CMD__GPIO_1_11 IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD2_DAT3__USDHC2_DAT3 IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, MUX_PAD_CTRL(MX6_USDHC_PAD_CTRL))
+#define MX6_PAD_SD2_DAT3__ECSPI5_SS3 IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT3__KPP_COL_6 IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXC IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT3__GPIO_1_12 IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT3__SJC_DONE IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#endif /* __ASM_ARCH_IOMUX_MX6Q_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Auto Generate file, please don't edit it
+ *
+ */
+
+#ifndef __ASM_ARCH_IOMUX_MX6SL_H__
+#define __ASM_ARCH_IOMUX_MX6SL_H__
+
+#define MX6_PAD_AUD_MCLK__AUDMUX_AUDIO_CLK_OUT IOMUX_PAD(0x02A4, 0x004C, 0, 0x0000, 0, MX6_ADU_PAD_CTRL)
+#define MX6_PAD_AUD_MCLK__PWM4_PWMO IOMUX_PAD(0x02A4, 0x004C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_MCLK__ECSPI3_RDY IOMUX_PAD(0x02A4, 0x004C, 2, 0x06B4, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_MCLK__FEC_MDC IOMUX_PAD(0x02A4, 0x004C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_MCLK__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x02A4, 0x004C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_MCLK__GPIO_1_6 IOMUX_PAD(0x02A4, 0x004C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_MCLK__SPDIF_SPDIF_EXT_CLK IOMUX_PAD(0x02A4, 0x004C, 6, 0x07F4, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_MCLK__TPSMP_HDATA_27 IOMUX_PAD(0x02A4, 0x004C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_AUD_RXC__AUDMUX_AUD3_RXC IOMUX_PAD(0x02A8, 0x0050, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_RXC__I2C1_SDA IOMUX_PAD(0x02A8, 0x0050, 1 | MUX_CONFIG_SION, 0x0720, 0, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_AUD_RXC__UART3_TXD IOMUX_PAD(0x02A8, 0x0050, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_AUD_RXC__UART3_RXD IOMUX_PAD(0x02A8, 0x0050, 2, 0x080C, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_AUD_RXC__FEC_TX_CLK IOMUX_PAD(0x02A8, 0x0050, 3, 0x070C, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_RXC__I2C3_SDA IOMUX_PAD(0x02A8, 0x0050, 4 | MUX_CONFIG_SION, 0x0730, 0, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_AUD_RXC__GPIO_1_1 IOMUX_PAD(0x02A8, 0x0050, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_RXC__ECSPI3_SS1 IOMUX_PAD(0x02A8, 0x0050, 6, 0x06C4, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_RXC__PL301_SIM_MX6_PER1_HREADYOUT IOMUX_PAD(0x02A8, 0x0050, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_AUD_RXD__AUDMUX_AUD3_RXD IOMUX_PAD(0x02AC, 0x0054, 0, 0x0000, 0, MX6_ADU_PAD_CTRL)
+#define MX6_PAD_AUD_RXD__ECSPI3_MOSI IOMUX_PAD(0x02AC, 0x0054, 1, 0x06BC, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_RXD__UART4_TXD IOMUX_PAD(0x02AC, 0x0054, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_AUD_RXD__UART4_RXD IOMUX_PAD(0x02AC, 0x0054, 2, 0x0814, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_AUD_RXD__FEC_RX_ER IOMUX_PAD(0x02AC, 0x0054, 3, 0x0708, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_RXD__USDHC1_LCTL IOMUX_PAD(0x02AC, 0x0054, 4, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_AUD_RXD__GPIO_1_2 IOMUX_PAD(0x02AC, 0x0054, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_RXD__SRC_INT_BOOT IOMUX_PAD(0x02AC, 0x0054, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_RXD__PL301_SIM_MX6_PER1_HRESP IOMUX_PAD(0x02AC, 0x0054, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_AUD_RXFS__AUDMUX_AUD3_RXFS IOMUX_PAD(0x02B0, 0x0058, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_RXFS__I2C1_SCL IOMUX_PAD(0x02B0, 0x0058, 1 | MUX_CONFIG_SION, 0x071C, 0, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_AUD_RXFS__UART3_TXD IOMUX_PAD(0x02B0, 0x0058, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_AUD_RXFS__UART3_RXD IOMUX_PAD(0x02B0, 0x0058, 2, 0x080C, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_AUD_RXFS__FEC_MDIO IOMUX_PAD(0x02B0, 0x0058, 3, 0x06F4, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_RXFS__I2C3_SCL IOMUX_PAD(0x02B0, 0x0058, 4 | MUX_CONFIG_SION, 0x072C, 0, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_AUD_RXFS__GPIO_1_0 IOMUX_PAD(0x02B0, 0x0058, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_RXFS__ECSPI3_SS0 IOMUX_PAD(0x02B0, 0x0058, 6, 0x06C0, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_RXFS__PL301_SIM_MX6_PER1_HPROT_1 IOMUX_PAD(0x02B0, 0x0058, 7, 0x07EC, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_AUD_TXC__AUDMUX_AUD3_TXC IOMUX_PAD(0x02B4, 0x005C, 0, 0x0000, 0, MX6_ADU_PAD_CTRL)
+#define MX6_PAD_AUD_TXC__ECSPI3_MISO IOMUX_PAD(0x02B4, 0x005C, 1, 0x06B8, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_TXC__UART4_TXD IOMUX_PAD(0x02B4, 0x005C, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_AUD_TXC__UART4_RXD IOMUX_PAD(0x02B4, 0x005C, 2, 0x0814, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_AUD_TXC__FEC_RX_DV IOMUX_PAD(0x02B4, 0x005C, 3, 0x0704, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_TXC__USDHC2_LCTL IOMUX_PAD(0x02B4, 0x005C, 4, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_AUD_TXC__GPIO_1_3 IOMUX_PAD(0x02B4, 0x005C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_TXC__SRC_SYSTEM_RST IOMUX_PAD(0x02B4, 0x005C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_TXC__TPSMP_HDATA_24 IOMUX_PAD(0x02B4, 0x005C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_AUD_TXD__AUDMUX_AUD3_TXD IOMUX_PAD(0x02B8, 0x0060, 0, 0x0000, 0, MX6_ADU_PAD_CTRL)
+#define MX6_PAD_AUD_TXD__ECSPI3_SCLK IOMUX_PAD(0x02B8, 0x0060, 1, 0x06B0, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_TXD__UART4_CTS IOMUX_PAD(0x02B8, 0x0060, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_AUD_TXD__UART4_RTS IOMUX_PAD(0x02B8, 0x0060, 2, 0x0810, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_AUD_TXD__FEC_TDATA_0 IOMUX_PAD(0x02B8, 0x0060, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_TXD__USDHC4_LCTL IOMUX_PAD(0x02B8, 0x0060, 4, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_AUD_TXD__GPIO_1_5 IOMUX_PAD(0x02B8, 0x0060, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_TXD__ANATOP_ANATOP_TESTI_1 IOMUX_PAD(0x02B8, 0x0060, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_TXD__TPSMP_HDATA_26 IOMUX_PAD(0x02B8, 0x0060, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_AUD_TXFS__AUDMUX_AUD3_TXFS IOMUX_PAD(0x02BC, 0x0064, 0, 0x0000, 0, MX6_ADU_PAD_CTRL)
+#define MX6_PAD_AUD_TXFS__PWM3_PWMO IOMUX_PAD(0x02BC, 0x0064, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_TXFS__UART4_CTS IOMUX_PAD(0x02BC, 0x0064, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_AUD_TXFS__UART4_RTS IOMUX_PAD(0x02BC, 0x0064, 2, 0x0810, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_AUD_TXFS__FEC_RDATA_1 IOMUX_PAD(0x02BC, 0x0064, 3, 0x06FC, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_TXFS__USDHC3_LCTL IOMUX_PAD(0x02BC, 0x0064, 4, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_AUD_TXFS__GPIO_1_4 IOMUX_PAD(0x02BC, 0x0064, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_TXFS__ANATOP_ANATOP_TESTI_0 IOMUX_PAD(0x02BC, 0x0064, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_AUD_TXFS__TPSMP_HDATA_25 IOMUX_PAD(0x02BC, 0x0064, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A0__MMDC_DRAM_A_0 IOMUX_PAD(0x02C0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A1__MMDC_DRAM_A_1 IOMUX_PAD(0x02C4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A10__MMDC_DRAM_A_10 IOMUX_PAD(0x02C8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A11__MMDC_DRAM_A_11 IOMUX_PAD(0x02CC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A12__MMDC_DRAM_A_12 IOMUX_PAD(0x02D0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A13__MMDC_DRAM_A_13 IOMUX_PAD(0x02D4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A14__MMDC_DRAM_A_14 IOMUX_PAD(0x02D8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A15__MMDC_DRAM_A_15 IOMUX_PAD(0x02DC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A2__MMDC_DRAM_A_2 IOMUX_PAD(0x02E0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A3__MMDC_DRAM_A_3 IOMUX_PAD(0x02E4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A4__MMDC_DRAM_A_4 IOMUX_PAD(0x02E8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A5__MMDC_DRAM_A_5 IOMUX_PAD(0x02EC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A6__MMDC_DRAM_A_6 IOMUX_PAD(0x02F0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A7__MMDC_DRAM_A_7 IOMUX_PAD(0x02F4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A8__MMDC_DRAM_A_8 IOMUX_PAD(0x02F8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_A9__MMDC_DRAM_A_9 IOMUX_PAD(0x02FC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_CAS__MMDC_DRAM_CAS IOMUX_PAD(0x0300, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_CS0__MMDC_DRAM_CS_0 IOMUX_PAD(0x0304, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_CS1__MMDC_DRAM_CS_1 IOMUX_PAD(0x0308, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 IOMUX_PAD(0x030C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 IOMUX_PAD(0x0310, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 IOMUX_PAD(0x0314, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 IOMUX_PAD(0x0318, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_RAS__MMDC_DRAM_RAS IOMUX_PAD(0x031C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_RESET__MMDC_DRAM_RESET IOMUX_PAD(0x0320, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 IOMUX_PAD(0x0324, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 IOMUX_PAD(0x0328, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 IOMUX_PAD(0x032C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 IOMUX_PAD(0x0330, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 IOMUX_PAD(0x0334, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 IOMUX_PAD(0x0338, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 IOMUX_PAD(0x033C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 IOMUX_PAD(0x0340, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 IOMUX_PAD(0x0344, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 IOMUX_PAD(0x0348, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 IOMUX_PAD(0x034C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 IOMUX_PAD(0x0350, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE IOMUX_PAD(0x0354, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ECSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, MX6_ECSPI_PAD_CTRL)
+#define MX6_PAD_ECSPI1_MISO__AUDMUX_AUD4_TXFS IOMUX_PAD(0x0358, 0x0068, 1, 0x05F8, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI1_MISO__UART5_CTS IOMUX_PAD(0x0358, 0x0068, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_ECSPI1_MISO__UART5_RTS IOMUX_PAD(0x0358, 0x0068, 2, 0x0818, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_ECSPI1_MISO__EPDC_BDR_0 IOMUX_PAD(0x0358, 0x0068, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI1_MISO__USDHC2_WP IOMUX_PAD(0x0358, 0x0068, 4, 0x0834, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_ECSPI1_MISO__GPIO_4_10 IOMUX_PAD(0x0358, 0x0068, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI1_MISO__CCM_PLL3_BYP IOMUX_PAD(0x0358, 0x0068, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI1_MISO__MMDC_MMDC_DEBUG_40 IOMUX_PAD(0x0358, 0x0068, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, MX6_ECSPI_PAD_CTRL)
+#define MX6_PAD_ECSPI1_MOSI__AUDMUX_AUD4_TXC IOMUX_PAD(0x035C, 0x006C, 1, 0x05F4, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI1_MOSI__UART5_TXD IOMUX_PAD(0x035C, 0x006C, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_ECSPI1_MOSI__UART5_RXD IOMUX_PAD(0x035C, 0x006C, 2, 0x081C, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_ECSPI1_MOSI__EPDC_VCOM_1 IOMUX_PAD(0x035C, 0x006C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI1_MOSI__USDHC2_VSELECT IOMUX_PAD(0x035C, 0x006C, 4, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_ECSPI1_MOSI__GPIO_4_9 IOMUX_PAD(0x035C, 0x006C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI1_MOSI__CCM_PLL2_BYP IOMUX_PAD(0x035C, 0x006C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI1_MOSI__MMDC_MMDC_DEBUG_49 IOMUX_PAD(0x035C, 0x006C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, MX6_ECSPI_PAD_CTRL)
+#define MX6_PAD_ECSPI1_SCLK__AUDMUX_AUD4_TXD IOMUX_PAD(0x0360, 0x0070, 1, 0x05E8, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI1_SCLK__UART5_TXD IOMUX_PAD(0x0360, 0x0070, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_ECSPI1_SCLK__UART5_RXD IOMUX_PAD(0x0360, 0x0070, 2, 0x081C, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_ECSPI1_SCLK__EPDC_VCOM_0 IOMUX_PAD(0x0360, 0x0070, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI1_SCLK__USDHC2_RST IOMUX_PAD(0x0360, 0x0070, 4, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_ECSPI1_SCLK__GPIO_4_8 IOMUX_PAD(0x0360, 0x0070, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI1_SCLK__USB_USBOTG2_OC IOMUX_PAD(0x0360, 0x0070, 6, 0x0820, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI1_SCLK__TPSMP_HDATA_18 IOMUX_PAD(0x0360, 0x0070, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ECSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x0364, 0x0074, 0, 0x068C, 0, MX6_ECSPI_PAD_CTRL)
+#define MX6_PAD_ECSPI1_SS0__AUDMUX_AUD4_RXD IOMUX_PAD(0x0364, 0x0074, 1, 0x05E4, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI1_SS0__UART5_CTS IOMUX_PAD(0x0364, 0x0074, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_ECSPI1_SS0__UART5_RTS IOMUX_PAD(0x0364, 0x0074, 2, 0x0818, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_ECSPI1_SS0__EPDC_BDR_1 IOMUX_PAD(0x0364, 0x0074, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI1_SS0__USDHC2_CD IOMUX_PAD(0x0364, 0x0074, 4, 0x0830, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_ECSPI1_SS0__GPIO_4_11 IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI1_SS0__USB_USBOTG2_PWR IOMUX_PAD(0x0364, 0x0074, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI1_SS0__PL301_SIM_MX6_PER1_HADDR_23 IOMUX_PAD(0x0364, 0x0074, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ECSPI2_MISO__GPIO_4_14 IOMUX_PAD(0x0368, 0x0078, 5, 0x0000, 0, MX6_CHG_PAD_CTRL)
+#define MX6_PAD_ECSPI2_MISO__USB_USBOTG1_OC IOMUX_PAD(0x0368, 0x0078, 6, 0x0824, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_MISO__TPSMP_HDATA_23 IOMUX_PAD(0x0368, 0x0078, 7, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x0368, 0x0078, 0, 0x06A0, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_MISO__SDMA_SDMA_EXT_EVENT_0 IOMUX_PAD(0x0368, 0x0078, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_MISO__UART3_CTS IOMUX_PAD(0x0368, 0x0078, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_ECSPI2_MISO__UART3_RTS IOMUX_PAD(0x0368, 0x0078, 2, 0x0808, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_ECSPI2_MISO__CSI_MCLK IOMUX_PAD(0x0368, 0x0078, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_MISO__USDHC1_WP IOMUX_PAD(0x0368, 0x0078, 4, 0x082C, 0, MX6_USDHC_PAD_CTRL)
+
+#define MX6_PAD_ECSPI2_MOSI__ECSPI2_MOSI IOMUX_PAD(0x036C, 0x007C, 0, 0x06A4, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_MOSI__SDMA_SDMA_EXT_EVENT_1 IOMUX_PAD(0x036C, 0x007C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_MOSI__UART3_TXD IOMUX_PAD(0x036C, 0x007C, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_ECSPI2_MOSI__UART3_RXD IOMUX_PAD(0x036C, 0x007C, 2, 0x080C, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_ECSPI2_MOSI__CSI_HSYNC IOMUX_PAD(0x036C, 0x007C, 3, 0x0670, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_MOSI__USDHC1_VSELECT IOMUX_PAD(0x036C, 0x007C, 4, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_ECSPI2_MOSI__GPIO_4_13 IOMUX_PAD(0x036C, 0x007C, 5, 0x0000, 0, MX6_CHG_PAD_CTRL)
+#define MX6_PAD_ECSPI2_MOSI__ANATOP_ANATOP_TESTO_1 IOMUX_PAD(0x036C, 0x007C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_MOSI__TPSMP_HDATA_22 IOMUX_PAD(0x036C, 0x007C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ECSPI2_SCLK__ECSPI2_SCLK IOMUX_PAD(0x0370, 0x0080, 0, 0x069C, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_SCLK__SPDIF_SPDIF_EXT_CLK IOMUX_PAD(0x0370, 0x0080, 1, 0x07F4, 1, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_SCLK__UART3_TXD IOMUX_PAD(0x0370, 0x0080, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_ECSPI2_SCLK__UART3_RXD IOMUX_PAD(0x0370, 0x0080, 2, 0x080C, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_ECSPI2_SCLK__CSI_PIXCLK IOMUX_PAD(0x0370, 0x0080, 3, 0x0674, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_SCLK__USDHC1_RST IOMUX_PAD(0x0370, 0x0080, 4, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_ECSPI2_SCLK__GPIO_4_12 IOMUX_PAD(0x0370, 0x0080, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_SCLK__USB_USBOTG2_OC IOMUX_PAD(0x0370, 0x0080, 6, 0x0820, 1, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_SCLK__TPSMP_HDATA_21 IOMUX_PAD(0x0370, 0x0080, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_ECSPI2_SS0__ECSPI2_SS0 IOMUX_PAD(0x0374, 0x0084, 0, 0x06A8, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_SS0__ECSPI1_SS3 IOMUX_PAD(0x0374, 0x0084, 1, 0x0698, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_SS0__UART3_CTS IOMUX_PAD(0x0374, 0x0084, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_ECSPI2_SS0__UART3_RTS IOMUX_PAD(0x0374, 0x0084, 2, 0x0808, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_ECSPI2_SS0__CSI_VSYNC IOMUX_PAD(0x0374, 0x0084, 3, 0x0678, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_SS0__USDHC1_CD IOMUX_PAD(0x0374, 0x0084, 4, 0x0828, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_ECSPI2_SS0__GPIO_4_15 IOMUX_PAD(0x0374, 0x0084, 5, 0x0000, 0, MX6_CHG_PAD_CTRL)
+#define MX6_PAD_ECSPI2_SS0__USB_USBOTG1_PWR IOMUX_PAD(0x0374, 0x0084, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_ECSPI2_SS0__PL301_SIM_MX6_PER1_HADDR_24 IOMUX_PAD(0x0374, 0x0084, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_BDR0__EPDC_BDR_0 IOMUX_PAD(0x0378, 0x0088, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_BDR0__USDHC4_CLK IOMUX_PAD(0x0378, 0x0088, 1, 0x0850, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_BDR0__UART3_CTS IOMUX_PAD(0x0378, 0x0088, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EPDC_BDR0__UART3_RTS IOMUX_PAD(0x0378, 0x0088, 2, 0x0808, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EPDC_BDR0__WEIM_WEIM_A_26 IOMUX_PAD(0x0378, 0x0088, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_BDR0__TCON_RL IOMUX_PAD(0x0378, 0x0088, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_BDR0__GPIO_2_5 IOMUX_PAD(0x0378, 0x0088, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_BDR0__EPDC_SDCE_7 IOMUX_PAD(0x0378, 0x0088, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_BDR0__MMDC_MMDC_DEBUG_9 IOMUX_PAD(0x0378, 0x0088, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_BDR1__EPDC_BDR_1 IOMUX_PAD(0x037C, 0x008C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_BDR1__USDHC4_CMD IOMUX_PAD(0x037C, 0x008C, 1, 0x0858, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_BDR1__UART3_CTS IOMUX_PAD(0x037C, 0x008C, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EPDC_BDR1__UART3_RTS IOMUX_PAD(0x037C, 0x008C, 2, 0x0808, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EPDC_BDR1__WEIM_WEIM_CRE IOMUX_PAD(0x037C, 0x008C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_BDR1__TCON_UD IOMUX_PAD(0x037C, 0x008C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_BDR1__GPIO_2_6 IOMUX_PAD(0x037C, 0x008C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_BDR1__EPDC_SDCE_8 IOMUX_PAD(0x037C, 0x008C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_BDR1__MMDC_MMDC_DEBUG_8 IOMUX_PAD(0x037C, 0x008C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_D0__EPDC_SDDO_0 IOMUX_PAD(0x0380, 0x0090, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D0__ECSPI4_MOSI IOMUX_PAD(0x0380, 0x0090, 1, 0x06D8, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D0__LCDIF_DAT_24 IOMUX_PAD(0x0380, 0x0090, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D0__CSI_D_0 IOMUX_PAD(0x0380, 0x0090, 3, 0x0630, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D0__TCON_E_DATA_0 IOMUX_PAD(0x0380, 0x0090, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D0__GPIO_1_7 IOMUX_PAD(0x0380, 0x0090, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D0__ANATOP_USBPHY1_TSTI_TX_HS_MODE IOMUX_PAD(0x0380, 0x0090, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D0__OBSERVE_MUX_OUT_0 IOMUX_PAD(0x0380, 0x0090, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_D1__EPDC_SDDO_1 IOMUX_PAD(0x0384, 0x0094, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D1__ECSPI4_MISO IOMUX_PAD(0x0384, 0x0094, 1, 0x06D4, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D1__LCDIF_DAT_25 IOMUX_PAD(0x0384, 0x0094, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D1__CSI_D_1 IOMUX_PAD(0x0384, 0x0094, 3, 0x0634, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D1__TCON_E_DATA_1 IOMUX_PAD(0x0384, 0x0094, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D1__GPIO_1_8 IOMUX_PAD(0x0384, 0x0094, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D1__ANATOP_USBPHY1_TSTI_TX_LS_MODE IOMUX_PAD(0x0384, 0x0094, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D1__OBSERVE_MUX_OUT_1 IOMUX_PAD(0x0384, 0x0094, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_D10__EPDC_SDDO_10 IOMUX_PAD(0x0388, 0x0098, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D10__ECSPI3_SS0 IOMUX_PAD(0x0388, 0x0098, 1, 0x06C0, 1, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D10__EPDC_PWRCTRL_2 IOMUX_PAD(0x0388, 0x0098, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D10__WEIM_WEIM_A_18 IOMUX_PAD(0x0388, 0x0098, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D10__TCON_E_DATA_10 IOMUX_PAD(0x0388, 0x0098, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D10__GPIO_1_17 IOMUX_PAD(0x0388, 0x0098, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D10__USDHC4_WP IOMUX_PAD(0x0388, 0x0098, 6, 0x087C, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_D10__MMDC_MMDC_DEBUG_29 IOMUX_PAD(0x0388, 0x0098, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_D11__EPDC_SDDO_11 IOMUX_PAD(0x038C, 0x009C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D11__ECSPI3_SCLK IOMUX_PAD(0x038C, 0x009C, 1, 0x06B0, 1, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D11__EPDC_PWRCTRL_3 IOMUX_PAD(0x038C, 0x009C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D11__WEIM_WEIM_A_19 IOMUX_PAD(0x038C, 0x009C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D11__TCON_E_DATA_11 IOMUX_PAD(0x038C, 0x009C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D11__GPIO_1_18 IOMUX_PAD(0x038C, 0x009C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D11__USDHC4_CD IOMUX_PAD(0x038C, 0x009C, 6, 0x0854, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_D11__MMDC_MMDC_DEBUG_28 IOMUX_PAD(0x038C, 0x009C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_D12__EPDC_SDDO_12 IOMUX_PAD(0x0390, 0x00A0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D12__UART2_TXD IOMUX_PAD(0x0390, 0x00A0, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EPDC_D12__UART2_RXD IOMUX_PAD(0x0390, 0x00A0, 1, 0x0804, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EPDC_D12__EPDC_PWRCOM IOMUX_PAD(0x0390, 0x00A0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D12__WEIM_WEIM_A_20 IOMUX_PAD(0x0390, 0x00A0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D12__TCON_E_DATA_12 IOMUX_PAD(0x0390, 0x00A0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D12__GPIO_1_19 IOMUX_PAD(0x0390, 0x00A0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D12__ECSPI3_SS1 IOMUX_PAD(0x0390, 0x00A0, 6, 0x06C4, 1, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D12__MMDC_MMDC_DEBUG_27 IOMUX_PAD(0x0390, 0x00A0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_D13__EPDC_SDDO_13 IOMUX_PAD(0x0394, 0x00A4, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D13__UART2_TXD IOMUX_PAD(0x0394, 0x00A4, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EPDC_D13__UART2_RXD IOMUX_PAD(0x0394, 0x00A4, 1, 0x0804, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EPDC_D13__EPDC_PWRIRQ IOMUX_PAD(0x0394, 0x00A4, 2, 0x06E8, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D13__WEIM_WEIM_A_21 IOMUX_PAD(0x0394, 0x00A4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D13__TCON_E_DATA_13 IOMUX_PAD(0x0394, 0x00A4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D13__GPIO_1_20 IOMUX_PAD(0x0394, 0x00A4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D13__ECSPI3_SS2 IOMUX_PAD(0x0394, 0x00A4, 6, 0x06C8, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D13__MMDC_MMDC_DEBUG_26 IOMUX_PAD(0x0394, 0x00A4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_D14__EPDC_SDDO_14 IOMUX_PAD(0x0398, 0x00A8, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D14__UART2_CTS IOMUX_PAD(0x0398, 0x00A8, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EPDC_D14__UART2_RTS IOMUX_PAD(0x0398, 0x00A8, 1, 0x0800, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EPDC_D14__EPDC_PWRSTAT IOMUX_PAD(0x0398, 0x00A8, 2, 0x06EC, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D14__WEIM_WEIM_A_22 IOMUX_PAD(0x0398, 0x00A8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D14__TCON_E_DATA_14 IOMUX_PAD(0x0398, 0x00A8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D14__GPIO_1_21 IOMUX_PAD(0x0398, 0x00A8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D14__ECSPI3_SS3 IOMUX_PAD(0x0398, 0x00A8, 6, 0x06CC, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D14__MMDC_MMDC_DEBUG_25 IOMUX_PAD(0x0398, 0x00A8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_D15__EPDC_SDDO_15 IOMUX_PAD(0x039C, 0x00AC, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D15__UART2_CTS IOMUX_PAD(0x039C, 0x00AC, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EPDC_D15__UART2_RTS IOMUX_PAD(0x039C, 0x00AC, 1, 0x0800, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EPDC_D15__EPDC_PWRWAKE IOMUX_PAD(0x039C, 0x00AC, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D15__WEIM_WEIM_A_23 IOMUX_PAD(0x039C, 0x00AC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D15__TCON_E_DATA_15 IOMUX_PAD(0x039C, 0x00AC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D15__GPIO_1_22 IOMUX_PAD(0x039C, 0x00AC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D15__ECSPI3_RDY IOMUX_PAD(0x039C, 0x00AC, 6, 0x06B4, 1, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D15__MMDC_MMDC_DEBUG_24 IOMUX_PAD(0x039C, 0x00AC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_D2__EPDC_SDDO_2 IOMUX_PAD(0x03A0, 0x00B0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D2__ECSPI4_SS0 IOMUX_PAD(0x03A0, 0x00B0, 1, 0x06DC, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D2__LCDIF_DAT_26 IOMUX_PAD(0x03A0, 0x00B0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D2__CSI_D_2 IOMUX_PAD(0x03A0, 0x00B0, 3, 0x0638, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D2__TCON_E_DATA_2 IOMUX_PAD(0x03A0, 0x00B0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D2__GPIO_1_9 IOMUX_PAD(0x03A0, 0x00B0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D2__ANATOP_USBPHY1_TSTI_TX_DN IOMUX_PAD(0x03A0, 0x00B0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D2__TPSMP_HDATA_28 IOMUX_PAD(0x03A0, 0x00B0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_D3__EPDC_SDDO_3 IOMUX_PAD(0x03A4, 0x00B4, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D3__ECSPI4_SCLK IOMUX_PAD(0x03A4, 0x00B4, 1, 0x06D0, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D3__LCDIF_DAT_27 IOMUX_PAD(0x03A4, 0x00B4, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D3__CSI_D_3 IOMUX_PAD(0x03A4, 0x00B4, 3, 0x063C, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D3__TCON_E_DATA_3 IOMUX_PAD(0x03A4, 0x00B4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D3__GPIO_1_10 IOMUX_PAD(0x03A4, 0x00B4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D3__ANATOP_USBPHY1_TSTI_TX_DP IOMUX_PAD(0x03A4, 0x00B4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D3__TPSMP_HDATA_29 IOMUX_PAD(0x03A4, 0x00B4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_D4__EPDC_SDDO_4 IOMUX_PAD(0x03A8, 0x00B8, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D4__ECSPI4_SS1 IOMUX_PAD(0x03A8, 0x00B8, 1, 0x06E0, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D4__LCDIF_DAT_28 IOMUX_PAD(0x03A8, 0x00B8, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D4__CSI_D_4 IOMUX_PAD(0x03A8, 0x00B8, 3, 0x0640, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D4__TCON_E_DATA_4 IOMUX_PAD(0x03A8, 0x00B8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D4__GPIO_1_11 IOMUX_PAD(0x03A8, 0x00B8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D4__ANATOP_USBPHY1_TSTI_TX_EN IOMUX_PAD(0x03A8, 0x00B8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D4__TPSMP_HDATA_30 IOMUX_PAD(0x03A8, 0x00B8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_D5__EPDC_SDDO_5 IOMUX_PAD(0x03AC, 0x00BC, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D5__ECSPI4_SS2 IOMUX_PAD(0x03AC, 0x00BC, 1, 0x06E4, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D5__LCDIF_DAT_29 IOMUX_PAD(0x03AC, 0x00BC, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D5__CSI_D_5 IOMUX_PAD(0x03AC, 0x00BC, 3, 0x0644, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D5__TCON_E_DATA_5 IOMUX_PAD(0x03AC, 0x00BC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D5__GPIO_1_12 IOMUX_PAD(0x03AC, 0x00BC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D5__ANATOP_USBPHY1_TSTI_TX_HIZ IOMUX_PAD(0x03AC, 0x00BC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D5__TPSMP_HDATA_31 IOMUX_PAD(0x03AC, 0x00BC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_D6__EPDC_SDDO_6 IOMUX_PAD(0x03B0, 0x00C0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D6__ECSPI4_SS3 IOMUX_PAD(0x03B0, 0x00C0, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D6__LCDIF_DAT_30 IOMUX_PAD(0x03B0, 0x00C0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D6__CSI_D_6 IOMUX_PAD(0x03B0, 0x00C0, 3, 0x0648, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D6__TCON_E_DATA_6 IOMUX_PAD(0x03B0, 0x00C0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D6__GPIO_1_13 IOMUX_PAD(0x03B0, 0x00C0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D6__ANATOP_USBPHY2_TSTO_RX_DISCON_DET IOMUX_PAD(0x03B0, 0x00C0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D6__TPSMP_HDATA_20 IOMUX_PAD(0x03B0, 0x00C0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_D7__EPDC_SDDO_7 IOMUX_PAD(0x03B4, 0x00C4, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D7__ECSPI4_RDY IOMUX_PAD(0x03B4, 0x00C4, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D7__LCDIF_DAT_31 IOMUX_PAD(0x03B4, 0x00C4, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D7__CSI_D_7 IOMUX_PAD(0x03B4, 0x00C4, 3, 0x064C, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D7__TCON_E_DATA_7 IOMUX_PAD(0x03B4, 0x00C4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D7__GPIO_1_14 IOMUX_PAD(0x03B4, 0x00C4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D7__ANATOP_USBPHY2_TSTO_RX_FS_RXD IOMUX_PAD(0x03B4, 0x00C4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D7__MMDC_MMDC_DEBUG_32 IOMUX_PAD(0x03B4, 0x00C4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_D8__EPDC_SDDO_8 IOMUX_PAD(0x03B8, 0x00C8, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D8__ECSPI3_MOSI IOMUX_PAD(0x03B8, 0x00C8, 1, 0x06BC, 1, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D8__EPDC_PWRCTRL_0 IOMUX_PAD(0x03B8, 0x00C8, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D8__WEIM_WEIM_A_16 IOMUX_PAD(0x03B8, 0x00C8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D8__TCON_E_DATA_8 IOMUX_PAD(0x03B8, 0x00C8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D8__GPIO_1_15 IOMUX_PAD(0x03B8, 0x00C8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D8__USDHC4_RST IOMUX_PAD(0x03B8, 0x00C8, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_D8__MMDC_MMDC_DEBUG_31 IOMUX_PAD(0x03B8, 0x00C8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_D9__EPDC_SDDO_9 IOMUX_PAD(0x03BC, 0x00CC, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D9__ECSPI3_MISO IOMUX_PAD(0x03BC, 0x00CC, 1, 0x06B8, 1, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D9__EPDC_PWRCTRL_1 IOMUX_PAD(0x03BC, 0x00CC, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D9__WEIM_WEIM_A_17 IOMUX_PAD(0x03BC, 0x00CC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D9__TCON_E_DATA_9 IOMUX_PAD(0x03BC, 0x00CC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D9__GPIO_1_16 IOMUX_PAD(0x03BC, 0x00CC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_D9__USDHC4_VSELECT IOMUX_PAD(0x03BC, 0x00CC, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_D9__MMDC_MMDC_DEBUG_30 IOMUX_PAD(0x03BC, 0x00CC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x03C0, 0x00D0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDCLK__ECSPI2_SS2 IOMUX_PAD(0x03C0, 0x00D0, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDCLK__TCON_YCKR IOMUX_PAD(0x03C0, 0x00D0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDCLK__CSI_PIXCLK IOMUX_PAD(0x03C0, 0x00D0, 3, 0x0674, 1, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDCLK__TCON_YCKL IOMUX_PAD(0x03C0, 0x00D0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDCLK__GPIO_1_31 IOMUX_PAD(0x03C0, 0x00D0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDCLK__USDHC2_RST IOMUX_PAD(0x03C0, 0x00D0, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_GDCLK__MMDC_MMDC_DEBUG_15 IOMUX_PAD(0x03C0, 0x00D0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_GDOE__EPDC_GDOE IOMUX_PAD(0x03C4, 0x00D4, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDOE__ECSPI2_SS3 IOMUX_PAD(0x03C4, 0x00D4, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDOE__TCON_YOER IOMUX_PAD(0x03C4, 0x00D4, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDOE__CSI_HSYNC IOMUX_PAD(0x03C4, 0x00D4, 3, 0x0670, 1, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDOE__TCON_YOEL IOMUX_PAD(0x03C4, 0x00D4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDOE__GPIO_2_0 IOMUX_PAD(0x03C4, 0x00D4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDOE__USDHC2_VSELECT IOMUX_PAD(0x03C4, 0x00D4, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_GDOE__MMDC_MMDC_DEBUG_14 IOMUX_PAD(0x03C4, 0x00D4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_GDRL__EPDC_GDRL IOMUX_PAD(0x03C8, 0x00D8, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDRL__ECSPI2_RDY IOMUX_PAD(0x03C8, 0x00D8, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDRL__TCON_YDIOUR IOMUX_PAD(0x03C8, 0x00D8, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDRL__CSI_MCLK IOMUX_PAD(0x03C8, 0x00D8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDRL__TCON_YDIOUL IOMUX_PAD(0x03C8, 0x00D8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDRL__GPIO_2_1 IOMUX_PAD(0x03C8, 0x00D8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDRL__USDHC2_WP IOMUX_PAD(0x03C8, 0x00D8, 6, 0x0834, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_GDRL__MMDC_MMDC_DEBUG_13 IOMUX_PAD(0x03C8, 0x00D8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_GDSP__EPDC_GDSP IOMUX_PAD(0x03CC, 0x00DC, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDSP__PWM4_PWMO IOMUX_PAD(0x03CC, 0x00DC, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDSP__TCON_YDIODR IOMUX_PAD(0x03CC, 0x00DC, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDSP__CSI_VSYNC IOMUX_PAD(0x03CC, 0x00DC, 3, 0x0678, 1, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDSP__TCON_YDIODL IOMUX_PAD(0x03CC, 0x00DC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDSP__GPIO_2_2 IOMUX_PAD(0x03CC, 0x00DC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_GDSP__USDHC2_CD IOMUX_PAD(0x03CC, 0x00DC, 6, 0x0830, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_GDSP__MMDC_MMDC_DEBUG_12 IOMUX_PAD(0x03CC, 0x00DC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_PWRCOM__EPDC_PWRCOM IOMUX_PAD(0x03D0, 0x00E0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCOM__USDHC4_DAT0 IOMUX_PAD(0x03D0, 0x00E0, 1, 0x085C, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCOM__LCDIF_DAT_20 IOMUX_PAD(0x03D0, 0x00E0, 2, 0x07C8, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCOM__WEIM_WEIM_BCLK IOMUX_PAD(0x03D0, 0x00E0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCOM__GPIO_2_11 IOMUX_PAD(0x03D0, 0x00E0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCOM__USDHC3_RST IOMUX_PAD(0x03D0, 0x00E0, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCOM__MMDC_MMDC_DEBUG_3 IOMUX_PAD(0x03D0, 0x00E0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL_0 IOMUX_PAD(0x03D4, 0x00E4, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL0__AUDMUX_AUD5_RXC IOMUX_PAD(0x03D4, 0x00E4, 1, 0x0604, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL0__LCDIF_DAT_16 IOMUX_PAD(0x03D4, 0x00E4, 2, 0x07B8, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL0__WEIM_WEIM_RW IOMUX_PAD(0x03D4, 0x00E4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL0__TCON_YCKL IOMUX_PAD(0x03D4, 0x00E4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 IOMUX_PAD(0x03D4, 0x00E4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL0__USDHC4_RST IOMUX_PAD(0x03D4, 0x00E4, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL0__MMDC_MMDC_DEBUG_7 IOMUX_PAD(0x03D4, 0x00E4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL_1 IOMUX_PAD(0x03D8, 0x00E8, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x03D8, 0x00E8, 1, 0x0610, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL1__LCDIF_DAT_17 IOMUX_PAD(0x03D8, 0x00E8, 2, 0x07BC, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL1__WEIM_WEIM_OE IOMUX_PAD(0x03D8, 0x00E8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL1__TCON_YOEL IOMUX_PAD(0x03D8, 0x00E8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL1__GPIO_2_8 IOMUX_PAD(0x03D8, 0x00E8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL1__USDHC4_VSELECT IOMUX_PAD(0x03D8, 0x00E8, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL1__MMDC_MMDC_DEBUG_6 IOMUX_PAD(0x03D8, 0x00E8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL_2 IOMUX_PAD(0x03DC, 0x00EC, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL2__AUDMUX_AUD5_TXD IOMUX_PAD(0x03DC, 0x00EC, 1, 0x0600, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL2__LCDIF_DAT_18 IOMUX_PAD(0x03DC, 0x00EC, 2, 0x07C0, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL2__WEIM_WEIM_CS_0 IOMUX_PAD(0x03DC, 0x00EC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL2__TCON_YDIOUL IOMUX_PAD(0x03DC, 0x00EC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL2__GPIO_2_9 IOMUX_PAD(0x03DC, 0x00EC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL2__USDHC4_WP IOMUX_PAD(0x03DC, 0x00EC, 6, 0x087C, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL2__MMDC_MMDC_DEBUG_5 IOMUX_PAD(0x03DC, 0x00EC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_PWRCTRL3__EPDC_PWRCTRL_3 IOMUX_PAD(0x03E0, 0x00F0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL3__AUDMUX_AUD5_TXC IOMUX_PAD(0x03E0, 0x00F0, 1, 0x060C, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL3__LCDIF_DAT_19 IOMUX_PAD(0x03E0, 0x00F0, 2, 0x07C4, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL3__WEIM_WEIM_CS_1 IOMUX_PAD(0x03E0, 0x00F0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL3__TCON_YDIODL IOMUX_PAD(0x03E0, 0x00F0, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL3__GPIO_2_10 IOMUX_PAD(0x03E0, 0x00F0, 5, 0x0000, 0, MX6_TSPAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL3__USDHC4_CD IOMUX_PAD(0x03E0, 0x00F0, 6, 0x0854, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRCTRL3__MMDC_MMDC_DEBUG_4 IOMUX_PAD(0x03E0, 0x00F0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_PWRINT__EPDC_PWRIRQ IOMUX_PAD(0x03E4, 0x00F4, 0, 0x06E8, 1, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRINT__USDHC4_DAT1 IOMUX_PAD(0x03E4, 0x00F4, 1, 0x0860, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRINT__LCDIF_DAT_21 IOMUX_PAD(0x03E4, 0x00F4, 2, 0x07CC, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRINT__WEIM_ACLK_FREERUN IOMUX_PAD(0x03E4, 0x00F4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRINT__ANATOP_USBOTG2_ID IOMUX_PAD(0x03E4, 0x00F4, 4, 0x05E0, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRINT__GPIO_2_12 IOMUX_PAD(0x03E4, 0x00F4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRINT__USDHC3_VSELECT IOMUX_PAD(0x03E4, 0x00F4, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRINT__MMDC_MMDC_DEBUG_2 IOMUX_PAD(0x03E4, 0x00F4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT IOMUX_PAD(0x03E8, 0x00F8, 0, 0x06EC, 1, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRSTAT__USDHC4_DAT2 IOMUX_PAD(0x03E8, 0x00F8, 1, 0x0864, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRSTAT__LCDIF_DAT_22 IOMUX_PAD(0x03E8, 0x00F8, 2, 0x07D0, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRSTAT__WEIM_WEIM_WAIT IOMUX_PAD(0x03E8, 0x00F8, 3, 0x0884, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRSTAT__KITTEN_EVENTI IOMUX_PAD(0x03E8, 0x00F8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 IOMUX_PAD(0x03E8, 0x00F8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRSTAT__USDHC3_WP IOMUX_PAD(0x03E8, 0x00F8, 6, 0x084C, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRSTAT__MMDC_MMDC_DEBUG_1 IOMUX_PAD(0x03E8, 0x00F8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_PWRWAKEUP__EPDC_PWRWAKE IOMUX_PAD(0x03EC, 0x00FC, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRWAKEUP__USDHC4_DAT3 IOMUX_PAD(0x03EC, 0x00FC, 1, 0x0868, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRWAKEUP__LCDIF_DAT_23 IOMUX_PAD(0x03EC, 0x00FC, 2, 0x07D4, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRWAKEUP__WEIM_WEIM_DTACK_B IOMUX_PAD(0x03EC, 0x00FC, 3, 0x0880, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRWAKEUP__KITTEN_EVENTO IOMUX_PAD(0x03EC, 0x00FC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 IOMUX_PAD(0x03EC, 0x00FC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRWAKEUP__USDHC3_CD IOMUX_PAD(0x03EC, 0x00FC, 6, 0x0838, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_EPDC_PWRWAKEUP__MMDC_MMDC_DEBUG_0 IOMUX_PAD(0x03EC, 0x00FC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_SDCE0__EPDC_SDCE_0 IOMUX_PAD(0x03F0, 0x0100, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE0__ECSPI2_SS1 IOMUX_PAD(0x03F0, 0x0100, 1, 0x06AC, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE0__PWM3_PWMO IOMUX_PAD(0x03F0, 0x0100, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE0__WEIM_WEIM_CS_2 IOMUX_PAD(0x03F0, 0x0100, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE0__TCON_YCKR IOMUX_PAD(0x03F0, 0x0100, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE0__GPIO_1_27 IOMUX_PAD(0x03F0, 0x0100, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV IOMUX_PAD(0x03F0, 0x0100, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE0__MMDC_MMDC_DEBUG_19 IOMUX_PAD(0x03F0, 0x0100, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_SDCE1__EPDC_SDCE_1 IOMUX_PAD(0x03F4, 0x0104, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE1__WDOG2_WDOG_B IOMUX_PAD(0x03F4, 0x0104, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE1__PWM4_PWMO IOMUX_PAD(0x03F4, 0x0104, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE1__WEIM_WEIM_LBA IOMUX_PAD(0x03F4, 0x0104, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE1__TCON_YOER IOMUX_PAD(0x03F4, 0x0104, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE1__GPIO_1_28 IOMUX_PAD(0x03F4, 0x0104, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE1__ANATOP_USBPHY1_TSTO_RX_FS_RXD IOMUX_PAD(0x03F4, 0x0104, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE1__MMDC_MMDC_DEBUG_18 IOMUX_PAD(0x03F4, 0x0104, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_SDCE2__EPDC_SDCE_2 IOMUX_PAD(0x03F8, 0x0108, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE2__I2C3_SCL IOMUX_PAD(0x03F8, 0x0108, 1 | MUX_CONFIG_SION, 0x072C, 1, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE2__PWM1_PWMO IOMUX_PAD(0x03F8, 0x0108, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE2__WEIM_WEIM_EB_0 IOMUX_PAD(0x03F8, 0x0108, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE2__TCON_YDIOUR IOMUX_PAD(0x03F8, 0x0108, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE2__GPIO_1_29 IOMUX_PAD(0x03F8, 0x0108, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE2__ANATOP_USBPHY1_TSTO_RX_HS_RXD IOMUX_PAD(0x03F8, 0x0108, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE2__MMDC_MMDC_DEBUG_17 IOMUX_PAD(0x03F8, 0x0108, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_SDCE3__EPDC_SDCE_3 IOMUX_PAD(0x03FC, 0x010C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE3__I2C3_SDA IOMUX_PAD(0x03FC, 0x010C, 1 | MUX_CONFIG_SION, 0x0730, 1, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE3__PWM2_PWMO IOMUX_PAD(0x03FC, 0x010C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE3__WEIM_WEIM_EB_1 IOMUX_PAD(0x03FC, 0x010C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE3__TCON_YDIODR IOMUX_PAD(0x03FC, 0x010C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE3__GPIO_1_30 IOMUX_PAD(0x03FC, 0x010C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE3__ANATOP_USBPHY1_TSTO_RX_SQUELCH IOMUX_PAD(0x03FC, 0x010C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCE3__MMDC_MMDC_DEBUG_16 IOMUX_PAD(0x03FC, 0x010C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x0400, 0x0110, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCLK__ECSPI2_MOSI IOMUX_PAD(0x0400, 0x0110, 1, 0x06A4, 1, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCLK__I2C2_SCL IOMUX_PAD(0x0400, 0x0110, 2 | MUX_CONFIG_SION, 0x0724, 0, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCLK__CSI_D_8 IOMUX_PAD(0x0400, 0x0110, 3, 0x0650, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCLK__TCON_CL IOMUX_PAD(0x0400, 0x0110, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCLK__GPIO_1_23 IOMUX_PAD(0x0400, 0x0110, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCLK__ANATOP_USBPHY2_TSTO_RX_HS_RXD IOMUX_PAD(0x0400, 0x0110, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDCLK__MMDC_MMDC_DEBUG_23 IOMUX_PAD(0x0400, 0x0110, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_SDLE__EPDC_SDLE IOMUX_PAD(0x0404, 0x0114, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDLE__ECSPI2_MISO IOMUX_PAD(0x0404, 0x0114, 1, 0x06A0, 1, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDLE__I2C2_SDA IOMUX_PAD(0x0404, 0x0114, 2 | MUX_CONFIG_SION, 0x0728, 0, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_EPDC_SDLE__CSI_D_9 IOMUX_PAD(0x0404, 0x0114, 3, 0x0654, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDLE__TCON_LD IOMUX_PAD(0x0404, 0x0114, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDLE__GPIO_1_24 IOMUX_PAD(0x0404, 0x0114, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDLE__ANATOP_USBPHY2_TSTO_RX_SQUELCH IOMUX_PAD(0x0404, 0x0114, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDLE__MMDC_MMDC_DEBUG_22 IOMUX_PAD(0x0404, 0x0114, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_SDOE__EPDC_SDOE IOMUX_PAD(0x0408, 0x0118, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDOE__ECSPI2_SS0 IOMUX_PAD(0x0408, 0x0118, 1, 0x06A8, 1, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDOE__TCON_XDIOR IOMUX_PAD(0x0408, 0x0118, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDOE__CSI_D_10 IOMUX_PAD(0x0408, 0x0118, 3, 0x0658, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDOE__TCON_XDIOL IOMUX_PAD(0x0408, 0x0118, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDOE__GPIO_1_25 IOMUX_PAD(0x0408, 0x0118, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDOE__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV IOMUX_PAD(0x0408, 0x0118, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDOE__MMDC_MMDC_DEBUG_21 IOMUX_PAD(0x0408, 0x0118, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x040C, 0x011C, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDSHR__ECSPI2_SCLK IOMUX_PAD(0x040C, 0x011C, 1, 0x069C, 1, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDSHR__EPDC_SDCE_4 IOMUX_PAD(0x040C, 0x011C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDSHR__CSI_D_11 IOMUX_PAD(0x040C, 0x011C, 3, 0x065C, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDSHR__TCON_XDIOR IOMUX_PAD(0x040C, 0x011C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDSHR__GPIO_1_26 IOMUX_PAD(0x040C, 0x011C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDSHR__ANATOP_USBPHY1_TSTO_RX_DISCON_DET IOMUX_PAD(0x040C, 0x011C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_SDSHR__MMDC_MMDC_DEBUG_20 IOMUX_PAD(0x040C, 0x011C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_VCOM0__EPDC_VCOM_0 IOMUX_PAD(0x0410, 0x0120, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_VCOM0__AUDMUX_AUD5_RXFS IOMUX_PAD(0x0410, 0x0120, 1, 0x0608, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_VCOM0__UART3_TXD IOMUX_PAD(0x0410, 0x0120, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EPDC_VCOM0__UART3_RXD IOMUX_PAD(0x0410, 0x0120, 2, 0x080C, 4, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EPDC_VCOM0__WEIM_WEIM_A_24 IOMUX_PAD(0x0410, 0x0120, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_VCOM0__TCON_VCOM_0 IOMUX_PAD(0x0410, 0x0120, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_VCOM0__GPIO_2_3 IOMUX_PAD(0x0410, 0x0120, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_VCOM0__EPDC_SDCE_5 IOMUX_PAD(0x0410, 0x0120, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_VCOM0__MMDC_MMDC_DEBUG_11 IOMUX_PAD(0x0410, 0x0120, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_EPDC_VCOM1__EPDC_VCOM_1 IOMUX_PAD(0x0414, 0x0124, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_VCOM1__AUDMUX_AUD5_RXD IOMUX_PAD(0x0414, 0x0124, 1, 0x05FC, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_VCOM1__UART3_TXD IOMUX_PAD(0x0414, 0x0124, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EPDC_VCOM1__UART3_RXD IOMUX_PAD(0x0414, 0x0124, 2, 0x080C, 5, MX6_UART_PAD_CTRL)
+#define MX6_PAD_EPDC_VCOM1__WEIM_WEIM_A_25 IOMUX_PAD(0x0414, 0x0124, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_VCOM1__TCON_VCOM_1 IOMUX_PAD(0x0414, 0x0124, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_VCOM1__GPIO_2_4 IOMUX_PAD(0x0414, 0x0124, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_VCOM1__EPDC_SDCE_6 IOMUX_PAD(0x0414, 0x0124, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_EPDC_VCOM1__MMDC_MMDC_DEBUG_10 IOMUX_PAD(0x0414, 0x0124, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_FEC_CRS_DV__FEC_RX_DV IOMUX_PAD(0x0418, 0x0128, 0, 0x0704, 1, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_FEC_CRS_DV__USDHC4_DAT1 IOMUX_PAD(0x0418, 0x0128, 1, 0x0860, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_CRS_DV__AUDMUX_AUD6_TXC IOMUX_PAD(0x0418, 0x0128, 2, 0x0624, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_CRS_DV__ECSPI4_MISO IOMUX_PAD(0x0418, 0x0128, 3, 0x06D4, 1, NO_PAD_CTRL)
+#define MX6_PAD_FEC_CRS_DV__GPT_CMPOUT2 IOMUX_PAD(0x0418, 0x0128, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_CRS_DV__GPIO_4_25 IOMUX_PAD(0x0418, 0x0128, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_CRS_DV__KITTEN_TRACE_31 IOMUX_PAD(0x0418, 0x0128, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_CRS_DV__PL301_SIM_MX6_PER1_HADDR_3 IOMUX_PAD(0x0418, 0x0128, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x041C, 0x012C, 0, 0x0000, 0, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_FEC_MDC__USDHC4_DAT4 IOMUX_PAD(0x041C, 0x012C, 1, 0x086C, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_MDC__AUDMUX_AUDIO_CLK_OUT IOMUX_PAD(0x041C, 0x012C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_MDC__USDHC1_RST IOMUX_PAD(0x041C, 0x012C, 3, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_MDC__USDHC3_RST IOMUX_PAD(0x041C, 0x012C, 4, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_MDC__GPIO_4_23 IOMUX_PAD(0x041C, 0x012C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_MDC__KITTEN_TRACE_29 IOMUX_PAD(0x041C, 0x012C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_MDC__PL301_SIM_MX6_PER1_HADDR_8 IOMUX_PAD(0x041C, 0x012C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x0420, 0x0130, 0, 0x06F4, 1, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_FEC_MDIO__USDHC4_CLK IOMUX_PAD(0x0420, 0x0130, 1, 0x0850, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_MDIO__AUDMUX_AUD6_RXFS IOMUX_PAD(0x0420, 0x0130, 2, 0x0620, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_MDIO__ECSPI4_SS0 IOMUX_PAD(0x0420, 0x0130, 3, 0x06DC, 1, NO_PAD_CTRL)
+#define MX6_PAD_FEC_MDIO__GPT_CAPIN1 IOMUX_PAD(0x0420, 0x0130, 4, 0x0710, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_MDIO__GPIO_4_20 IOMUX_PAD(0x0420, 0x0130, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_MDIO__KITTEN_TRACE_26 IOMUX_PAD(0x0420, 0x0130, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_MDIO__PL301_SIM_MX6_PER1_HADDR_15 IOMUX_PAD(0x0420, 0x0130, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_FEC_REF_CLK__FEC_REF_OUT IOMUX_PAD(0x0424, 0x0134, 0x10, 0x0000, 0, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_FEC_REF_CLK__USDHC4_RST IOMUX_PAD(0x0424, 0x0134, 1, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_REF_CLK__WDOG1_WDOG_B IOMUX_PAD(0x0424, 0x0134, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_REF_CLK__PWM4_PWMO IOMUX_PAD(0x0424, 0x0134, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_REF_CLK__CCM_PMIC_RDY IOMUX_PAD(0x0424, 0x0134, 4, 0x062C, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_REF_CLK__GPIO_4_26 IOMUX_PAD(0x0424, 0x0134, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_REF_CLK__SPDIF_SPDIF_EXT_CLK IOMUX_PAD(0x0424, 0x0134, 6, 0x07F4, 2, NO_PAD_CTRL)
+#define MX6_PAD_FEC_REF_CLK__PL301_SIM_MX6_PER1_HADDR_0 IOMUX_PAD(0x0424, 0x0134, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_FEC_RX_ER__GPIO_4_19 IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, MX6_HP_DET_PAD_CTRL)
+#define MX6_PAD_FEC_RX_ER__KITTEN_TRACE_25 IOMUX_PAD(0x0428, 0x0138, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_RX_ER__PL301_SIM_MX6_PER1_HADDR_5 IOMUX_PAD(0x0428, 0x0138, 7, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x0428, 0x0138, 0, 0x0708, 1, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_FEC_RX_ER__USDHC4_DAT0 IOMUX_PAD(0x0428, 0x0138, 1, 0x085C, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_RX_ER__AUDMUX_AUD6_RXD IOMUX_PAD(0x0428, 0x0138, 2, 0x0614, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_RX_ER__ECSPI4_MOSI IOMUX_PAD(0x0428, 0x0138, 3, 0x06D8, 1, NO_PAD_CTRL)
+#define MX6_PAD_FEC_RX_ER__GPT_CMPOUT1 IOMUX_PAD(0x0428, 0x0138, 4, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_FEC_RXD0__FEC_RDATA_0 IOMUX_PAD(0x042C, 0x013C, 0, 0x06F8, 0, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_FEC_RXD0__USDHC4_DAT5 IOMUX_PAD(0x042C, 0x013C, 1, 0x0870, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_RXD0__ANATOP_USBOTG1_ID IOMUX_PAD(0x042C, 0x013C, 2, 0x05DC, 1, NO_PAD_CTRL)
+#define MX6_PAD_FEC_RXD0__USDHC1_VSELECT IOMUX_PAD(0x042C, 0x013C, 3, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_RXD0__USDHC3_VSELECT IOMUX_PAD(0x042C, 0x013C, 4, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_RXD0__GPIO_4_17 IOMUX_PAD(0x042C, 0x013C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_RXD0__KITTEN_TRACE_24 IOMUX_PAD(0x042C, 0x013C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_RXD0__PL301_SIM_MX6_PER1_HADDR_7 IOMUX_PAD(0x042C, 0x013C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_FEC_RXD1__FEC_RDATA_1 IOMUX_PAD(0x0430, 0x0140, 0, 0x06FC, 1, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_FEC_RXD1__USDHC4_DAT2 IOMUX_PAD(0x0430, 0x0140, 1, 0x0864, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_RXD1__AUDMUX_AUD6_TXFS IOMUX_PAD(0x0430, 0x0140, 2, 0x0628, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_RXD1__ECSPI4_SS1 IOMUX_PAD(0x0430, 0x0140, 3, 0x06E0, 1, NO_PAD_CTRL)
+#define MX6_PAD_FEC_RXD1__GPT_CMPOUT3 IOMUX_PAD(0x0430, 0x0140, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_RXD1__GPIO_4_18 IOMUX_PAD(0x0430, 0x0140, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_RXD1__FEC_COL IOMUX_PAD(0x0430, 0x0140, 6, 0x06F0, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_RXD1__PL301_SIM_MX6_PER1_HADDR_9 IOMUX_PAD(0x0430, 0x0140, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x0434, 0x0144, 0, 0x070C, 1, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TX_CLK__USDHC4_CMD IOMUX_PAD(0x0434, 0x0144, 1, 0x0858, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_TX_CLK__AUDMUX_AUD6_RXC IOMUX_PAD(0x0434, 0x0144, 2, 0x061C, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TX_CLK__ECSPI4_SCLK IOMUX_PAD(0x0434, 0x0144, 3, 0x06D0, 1, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TX_CLK__GPT_CAPIN2 IOMUX_PAD(0x0434, 0x0144, 4, 0x0714, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TX_CLK__GPIO_4_21 IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TX_CLK__KITTEN_TRACE_27 IOMUX_PAD(0x0434, 0x0144, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TX_CLK__PL301_SIM_MX6_PER1_HADDR_4 IOMUX_PAD(0x0434, 0x0144, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x0438, 0x0148, 0, 0x0000, 0, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_FEC_TX_EN__USDHC4_DAT6 IOMUX_PAD(0x0438, 0x0148, 1, 0x0874, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_TX_EN__SPDIF_IN1 IOMUX_PAD(0x0438, 0x0148, 2, 0x07F0, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TX_EN__USDHC1_WP IOMUX_PAD(0x0438, 0x0148, 3, 0x082C, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_TX_EN__USDHC3_WP IOMUX_PAD(0x0438, 0x0148, 4, 0x084C, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_TX_EN__GPIO_4_22 IOMUX_PAD(0x0438, 0x0148, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TX_EN__KITTEN_TRACE_28 IOMUX_PAD(0x0438, 0x0148, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TX_EN__PL301_SIM_MX6_PER1_HADDR_1 IOMUX_PAD(0x0438, 0x0148, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_FEC_TXD0__FEC_TDATA_0 IOMUX_PAD(0x043C, 0x014C, 0, 0x0000, 0, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_FEC_TXD0__USDHC4_DAT3 IOMUX_PAD(0x043C, 0x014C, 1, 0x0868, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_TXD0__AUDMUX_AUD6_TXD IOMUX_PAD(0x043C, 0x014C, 2, 0x0618, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TXD0__ECSPI4_SS2 IOMUX_PAD(0x043C, 0x014C, 3, 0x06E4, 1, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TXD0__GPT_CLKIN IOMUX_PAD(0x043C, 0x014C, 4, 0x0718, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TXD0__GPIO_4_24 IOMUX_PAD(0x043C, 0x014C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TXD0__KITTEN_TRACE_30 IOMUX_PAD(0x043C, 0x014C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TXD0__PL301_SIM_MX6_PER1_HADDR_2 IOMUX_PAD(0x043C, 0x014C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_FEC_TXD1__FEC_TDATA_1 IOMUX_PAD(0x0440, 0x0150, 0, 0x0000, 0, MX6_ENET_PAD_CTRL)
+#define MX6_PAD_FEC_TXD1__USDHC4_DAT7 IOMUX_PAD(0x0440, 0x0150, 1, 0x0878, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_TXD1__SPDIF_OUT1 IOMUX_PAD(0x0440, 0x0150, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TXD1__USDHC1_CD IOMUX_PAD(0x0440, 0x0150, 3, 0x0828, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_TXD1__USDHC3_CD IOMUX_PAD(0x0440, 0x0150, 4, 0x0838, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_FEC_TXD1__GPIO_4_16 IOMUX_PAD(0x0440, 0x0150, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TXD1__FEC_RX_CLK IOMUX_PAD(0x0440, 0x0150, 6, 0x0700, 0, NO_PAD_CTRL)
+#define MX6_PAD_FEC_TXD1__PL301_SIM_MX6_PER1_HADDR_6 IOMUX_PAD(0x0440, 0x0150, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_HSIC_DAT__USB_H_DATA IOMUX_PAD(0x0444, 0x0154, 0, 0x0000, 0, MX6_USB_HSIC_PAD_CTRL)
+#define MX6_PAD_HSIC_DAT__I2C1_SCL IOMUX_PAD(0x0444, 0x0154, 1 | MUX_CONFIG_SION, 0x071C, 1, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_HSIC_DAT__PWM1_PWMO IOMUX_PAD(0x0444, 0x0154, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_HSIC_DAT__ANATOP_ANATOP_24M_OUT IOMUX_PAD(0x0444, 0x0154, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_HSIC_DAT__OSC32K_32K_OUT IOMUX_PAD(0x0444, 0x0154, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_HSIC_DAT__GPIO_3_19 IOMUX_PAD(0x0444, 0x0154, 5, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_HSIC_STROBE__USB_H_STROBE IOMUX_PAD(0x0448, 0x0158, 0, 0x0000, 0, MX6_USB_HSIC_PAD_CTRL)
+#define MX6_PAD_HSIC_STROBE__USB_H_STROBE_START IOMUX_PAD(0x0448, 0x0158, 0, 0x0000, 0, MX6_USB_HSIC_PAD_CTRL | PAD_CTL_PUS_47K_UP)
+#define MX6_PAD_HSIC_STROBE__I2C1_SDA IOMUX_PAD(0x0448, 0x0158, 1 | MUX_CONFIG_SION, 0x0720, 1, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_HSIC_STROBE__PWM2_PWMO IOMUX_PAD(0x0448, 0x0158, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_HSIC_STROBE__ANATOP_ANATOP_32K_OUT IOMUX_PAD(0x0448, 0x0158, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_HSIC_STROBE__GPIO_3_20 IOMUX_PAD(0x0448, 0x0158, 5, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x044C, 0x015C, 0 | MUX_CONFIG_SION, 0x071C, 2, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_I2C1_SCL__UART1_CTS IOMUX_PAD(0x044C, 0x015C, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_I2C1_SCL__UART1_RTS IOMUX_PAD(0x044C, 0x015C, 1, 0x07F8, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_I2C1_SCL__ECSPI3_SS2 IOMUX_PAD(0x044C, 0x015C, 2, 0x06C8, 1, NO_PAD_CTRL)
+#define MX6_PAD_I2C1_SCL__FEC_RDATA_0 IOMUX_PAD(0x044C, 0x015C, 3, 0x06F8, 1, NO_PAD_CTRL)
+#define MX6_PAD_I2C1_SCL__USDHC3_RST IOMUX_PAD(0x044C, 0x015C, 4, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_I2C1_SCL__GPIO_3_12 IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_I2C1_SCL__ECSPI1_SS1 IOMUX_PAD(0x044C, 0x015C, 6, 0x0690, 0, NO_PAD_CTRL)
+#define MX6_PAD_I2C1_SCL__PL301_SIM_MX6_PER1_HSIZE_0 IOMUX_PAD(0x044C, 0x015C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x0450, 0x0160, 0 | MUX_CONFIG_SION, 0x0720, 2, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_I2C1_SDA__UART1_CTS IOMUX_PAD(0x0450, 0x0160, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_I2C1_SDA__UART1_RTS IOMUX_PAD(0x0450, 0x0160, 1, 0x07F8, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_I2C1_SDA__ECSPI3_SS3 IOMUX_PAD(0x0450, 0x0160, 2, 0x06CC, 1, NO_PAD_CTRL)
+#define MX6_PAD_I2C1_SDA__FEC_TX_EN IOMUX_PAD(0x0450, 0x0160, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_I2C1_SDA__USDHC3_VSELECT IOMUX_PAD(0x0450, 0x0160, 4, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_I2C1_SDA__GPIO_3_13 IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_I2C1_SDA__ECSPI1_SS2 IOMUX_PAD(0x0450, 0x0160, 6, 0x0694, 0, NO_PAD_CTRL)
+#define MX6_PAD_I2C1_SDA__PL301_SIM_MX6_PER1_HSIZE_1 IOMUX_PAD(0x0450, 0x0160, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x0454, 0x0164, 0 | MUX_CONFIG_SION, 0x0724, 1, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_I2C2_SCL__AUDMUX_AUD4_RXFS IOMUX_PAD(0x0454, 0x0164, 1, 0x05F0, 0, NO_PAD_CTRL)
+#define MX6_PAD_I2C2_SCL__SPDIF_IN1 IOMUX_PAD(0x0454, 0x0164, 2, 0x07F0, 1, NO_PAD_CTRL)
+#define MX6_PAD_I2C2_SCL__FEC_TDATA_1 IOMUX_PAD(0x0454, 0x0164, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_I2C2_SCL__USDHC3_WP IOMUX_PAD(0x0454, 0x0164, 4, 0x084C, 2, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_I2C2_SCL__GPIO_3_14 IOMUX_PAD(0x0454, 0x0164, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_I2C2_SCL__ECSPI1_RDY IOMUX_PAD(0x0454, 0x0164, 6, 0x0680, 0, NO_PAD_CTRL)
+#define MX6_PAD_I2C2_SCL__PL301_SIM_MX6_PER1_HSIZE_2 IOMUX_PAD(0x0454, 0x0164, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x0458, 0x0168, 0 | MUX_CONFIG_SION, 0x0728, 1, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_I2C2_SDA__AUDMUX_AUD4_RXC IOMUX_PAD(0x0458, 0x0168, 1, 0x05EC, 0, NO_PAD_CTRL)
+#define MX6_PAD_I2C2_SDA__SPDIF_OUT1 IOMUX_PAD(0x0458, 0x0168, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_I2C2_SDA__FEC_REF_OUT IOMUX_PAD(0x0458, 0x0168, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_I2C2_SDA__USDHC3_CD IOMUX_PAD(0x0458, 0x0168, 4, 0x0838, 2, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_I2C2_SDA__GPIO_3_15 IOMUX_PAD(0x0458, 0x0168, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_I2C2_SDA__ANATOP_ANATOP_TESTO_0 IOMUX_PAD(0x0458, 0x0168, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_I2C2_SDA__PL301_SIM_MX6_PER1_HWRITE IOMUX_PAD(0x0458, 0x0168, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_JTAG_MOD__SJC_MOD IOMUX_PAD(0x045C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_JTAG_TCK__SJC_TCK IOMUX_PAD(0x0460, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_JTAG_TDI__SJC_TDI IOMUX_PAD(0x0464, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_JTAG_TDO__SJC_TDO IOMUX_PAD(0x0468, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_JTAG_TMS__SJC_TMS IOMUX_PAD(0x046C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_JTAG_TRSTB__SJC_TRSTB IOMUX_PAD(0x0470, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x0474, 0x016C, 0, 0x0734, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL0__I2C2_SCL IOMUX_PAD(0x0474, 0x016C, 1 | MUX_CONFIG_SION, 0x0724, 2, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_KEY_COL0__LCDIF_DAT_0 IOMUX_PAD(0x0474, 0x016C, 2, 0x0778, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL0__WEIM_WEIM_DA_A_0 IOMUX_PAD(0x0474, 0x016C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL0__USDHC1_CD IOMUX_PAD(0x0474, 0x016C, 4, 0x0828, 2, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_COL0__GPIO_3_24 IOMUX_PAD(0x0474, 0x016C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL0__MSHC_SCLK IOMUX_PAD(0x0474, 0x016C, 6, 0x07E8, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL0__TPSMP_HDATA_0 IOMUX_PAD(0x0474, 0x016C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x0478, 0x0170, 0, 0x0738, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL1__ECSPI4_MOSI IOMUX_PAD(0x0478, 0x0170, 1, 0x06D8, 2, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL1__LCDIF_DAT_2 IOMUX_PAD(0x0478, 0x0170, 2, 0x0780, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL1__WEIM_WEIM_DA_A_2 IOMUX_PAD(0x0478, 0x0170, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL1__USDHC3_DAT4 IOMUX_PAD(0x0478, 0x0170, 4, 0x083C, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_COL1__GPIO_3_26 IOMUX_PAD(0x0478, 0x0170, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL1__MSHC_DATA_0 IOMUX_PAD(0x0478, 0x0170, 6, 0x07D8, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL1__TPSMP_HDATA_2 IOMUX_PAD(0x0478, 0x0170, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x047C, 0x0174, 0, 0x073C, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL2__ECSPI4_SS0 IOMUX_PAD(0x047C, 0x0174, 1, 0x06DC, 2, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL2__LCDIF_DAT_4 IOMUX_PAD(0x047C, 0x0174, 2, 0x0788, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL2__WEIM_WEIM_DA_A_4 IOMUX_PAD(0x047C, 0x0174, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL2__USDHC3_DAT6 IOMUX_PAD(0x047C, 0x0174, 4, 0x0844, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_COL2__GPIO_3_28 IOMUX_PAD(0x047C, 0x0174, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL2__MSHC_DATA_2 IOMUX_PAD(0x047C, 0x0174, 6, 0x07E0, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL2__TPSMP_HDATA_4 IOMUX_PAD(0x047C, 0x0174, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x0480, 0x0178, 0, 0x0740, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL3__AUDMUX_AUD6_RXFS IOMUX_PAD(0x0480, 0x0178, 1, 0x0620, 1, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL3__LCDIF_DAT_6 IOMUX_PAD(0x0480, 0x0178, 2, 0x0790, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL3__WEIM_WEIM_DA_A_6 IOMUX_PAD(0x0480, 0x0178, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL3__USDHC4_DAT6 IOMUX_PAD(0x0480, 0x0178, 4, 0x0874, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_COL3__GPIO_3_30 IOMUX_PAD(0x0480, 0x0178, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL3__USDHC1_RST IOMUX_PAD(0x0480, 0x0178, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_COL3__TPSMP_HDATA_6 IOMUX_PAD(0x0480, 0x0178, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x0484, 0x017C, 0, 0x0744, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL4__AUDMUX_AUD6_RXD IOMUX_PAD(0x0484, 0x017C, 1, 0x0614, 1, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL4__LCDIF_DAT_8 IOMUX_PAD(0x0484, 0x017C, 2, 0x0798, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL4__WEIM_WEIM_DA_A_8 IOMUX_PAD(0x0484, 0x017C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL4__USDHC4_CLK IOMUX_PAD(0x0484, 0x017C, 4, 0x0850, 2, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_COL4__GPIO_4_0 IOMUX_PAD(0x0484, 0x017C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL4__USB_USBOTG1_PWR IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL4__TPSMP_HDATA_8 IOMUX_PAD(0x0484, 0x017C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_COL5__KPP_COL_5 IOMUX_PAD(0x0488, 0x0180, 0, 0x0748, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL5__AUDMUX_AUD6_TXFS IOMUX_PAD(0x0488, 0x0180, 1, 0x0628, 1, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL5__LCDIF_DAT_10 IOMUX_PAD(0x0488, 0x0180, 2, 0x07A0, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL5__WEIM_WEIM_DA_A_10 IOMUX_PAD(0x0488, 0x0180, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL5__USDHC4_DAT0 IOMUX_PAD(0x0488, 0x0180, 4, 0x085C, 2, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_COL5__GPIO_4_2 IOMUX_PAD(0x0488, 0x0180, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL5__USB_USBOTG2_PWR IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL5__TPSMP_HDATA_10 IOMUX_PAD(0x0488, 0x0180, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_COL6__KPP_COL_6 IOMUX_PAD(0x048C, 0x0184, 0, 0x074C, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL6__UART4_TXD IOMUX_PAD(0x048C, 0x0184, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_COL6__UART4_RXD IOMUX_PAD(0x048C, 0x0184, 1, 0x0814, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_COL6__LCDIF_DAT_12 IOMUX_PAD(0x048C, 0x0184, 2, 0x07A8, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL6__WEIM_WEIM_DA_A_12 IOMUX_PAD(0x048C, 0x0184, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL6__USDHC4_DAT2 IOMUX_PAD(0x048C, 0x0184, 4, 0x0864, 2, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_COL6__GPIO_4_4 IOMUX_PAD(0x048C, 0x0184, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL6__USDHC3_RST IOMUX_PAD(0x048C, 0x0184, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_COL6__TPSMP_HDATA_12 IOMUX_PAD(0x048C, 0x0184, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_COL7__KPP_COL_7 IOMUX_PAD(0x0490, 0x0188, 0, 0x0750, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL7__UART4_CTS IOMUX_PAD(0x0490, 0x0188, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_COL7__UART4_RTS IOMUX_PAD(0x0490, 0x0188, 1, 0x0810, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_COL7__LCDIF_DAT_14 IOMUX_PAD(0x0490, 0x0188, 2, 0x07B0, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL7__WEIM_WEIM_DA_A_14 IOMUX_PAD(0x0490, 0x0188, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_COL7__USDHC4_DAT4 IOMUX_PAD(0x0490, 0x0188, 4, 0x086C, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_COL7__GPIO_4_6 IOMUX_PAD(0x0490, 0x0188, 5, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_COL7__USDHC1_WP IOMUX_PAD(0x0490, 0x0188, 6, 0x082C, 2, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_COL7__TPSMP_HDATA_14 IOMUX_PAD(0x0490, 0x0188, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x0494, 0x018C, 0, 0x0754, 0, MX6_KEYPAD_CTRL)
+#define MX6_PAD_KEY_ROW0__I2C2_SDA IOMUX_PAD(0x0494, 0x018C, 1 | MUX_CONFIG_SION, 0x0728, 2, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_KEY_ROW0__LCDIF_DAT_1 IOMUX_PAD(0x0494, 0x018C, 2, 0x077C, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW0__WEIM_WEIM_DA_A_1 IOMUX_PAD(0x0494, 0x018C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW0__USDHC1_WP IOMUX_PAD(0x0494, 0x018C, 4, 0x082C, 3, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_ROW0__GPIO_3_25 IOMUX_PAD(0x0494, 0x018C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW0__MSHC_BS IOMUX_PAD(0x0494, 0x018C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW0__TPSMP_HDATA_1 IOMUX_PAD(0x0494, 0x018C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x0498, 0x0190, 0, 0x0758, 0, MX6_KEYPAD_CTRL)
+#define MX6_PAD_KEY_ROW1__ECSPI4_MISO IOMUX_PAD(0x0498, 0x0190, 1, 0x06D4, 2, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW1__LCDIF_DAT_3 IOMUX_PAD(0x0498, 0x0190, 2, 0x0784, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW1__WEIM_WEIM_DA_A_3 IOMUX_PAD(0x0498, 0x0190, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW1__USDHC3_DAT5 IOMUX_PAD(0x0498, 0x0190, 4, 0x0840, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_ROW1__GPIO_3_27 IOMUX_PAD(0x0498, 0x0190, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW1__MSHC_DATA_1 IOMUX_PAD(0x0498, 0x0190, 6, 0x07DC, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW1__TPSMP_HDATA_3 IOMUX_PAD(0x0498, 0x0190, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x049C, 0x0194, 0, 0x075C, 0, MX6_KEYPAD_CTRL)
+#define MX6_PAD_KEY_ROW2__ECSPI4_SCLK IOMUX_PAD(0x049C, 0x0194, 1, 0x06D0, 2, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW2__LCDIF_DAT_5 IOMUX_PAD(0x049C, 0x0194, 2, 0x078C, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW2__WEIM_WEIM_DA_A_5 IOMUX_PAD(0x049C, 0x0194, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW2__USDHC3_DAT7 IOMUX_PAD(0x049C, 0x0194, 4, 0x0848, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_ROW2__GPIO_3_29 IOMUX_PAD(0x049C, 0x0194, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW2__MSHC_DATA_3 IOMUX_PAD(0x049C, 0x0194, 6, 0x07E4, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW2__TPSMP_HDATA_5 IOMUX_PAD(0x049C, 0x0194, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x04A0, 0x0198, 0, 0x0760, 0, MX6_KEYPAD_CTRL)
+#define MX6_PAD_KEY_ROW3__AUDMUX_AUD6_RXC IOMUX_PAD(0x04A0, 0x0198, 1, 0x061C, 1, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW3__LCDIF_DAT_7 IOMUX_PAD(0x04A0, 0x0198, 2, 0x0794, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW3__WEIM_WEIM_DA_A_7 IOMUX_PAD(0x04A0, 0x0198, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW3__USDHC4_DAT7 IOMUX_PAD(0x04A0, 0x0198, 4, 0x0878, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_ROW3__GPIO_3_31 IOMUX_PAD(0x04A0, 0x0198, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW3__USDHC1_VSELECT IOMUX_PAD(0x04A0, 0x0198, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_ROW3__TPSMP_HDATA_7 IOMUX_PAD(0x04A0, 0x0198, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x04A4, 0x019C, 0, 0x0764, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW4__AUDMUX_AUD6_TXC IOMUX_PAD(0x04A4, 0x019C, 1, 0x0624, 1, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW4__LCDIF_DAT_9 IOMUX_PAD(0x04A4, 0x019C, 2, 0x079C, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW4__WEIM_WEIM_DA_A_9 IOMUX_PAD(0x04A4, 0x019C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW4__USDHC4_CMD IOMUX_PAD(0x04A4, 0x019C, 4, 0x0858, 2, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_ROW4__GPIO_4_1 IOMUX_PAD(0x04A4, 0x019C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW4__USB_USBOTG1_OC IOMUX_PAD(0x04A4, 0x019C, 6, 0x0824, 1, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW4__TPSMP_HDATA_9 IOMUX_PAD(0x04A4, 0x019C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_ROW5__KPP_ROW_5 IOMUX_PAD(0x04A8, 0x01A0, 0, 0x0768, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW5__AUDMUX_AUD6_TXD IOMUX_PAD(0x04A8, 0x01A0, 1, 0x0618, 1, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW5__LCDIF_DAT_11 IOMUX_PAD(0x04A8, 0x01A0, 2, 0x07A4, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW5__WEIM_WEIM_DA_A_11 IOMUX_PAD(0x04A8, 0x01A0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW5__USDHC4_DAT1 IOMUX_PAD(0x04A8, 0x01A0, 4, 0x0860, 2, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_ROW5__GPIO_4_3 IOMUX_PAD(0x04A8, 0x01A0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW5__USB_USBOTG2_OC IOMUX_PAD(0x04A8, 0x01A0, 6, 0x0820, 2, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW5__TPSMP_HDATA_11 IOMUX_PAD(0x04A8, 0x01A0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_ROW6__KPP_ROW_6 IOMUX_PAD(0x04AC, 0x01A4, 0, 0x076C, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW6__UART4_TXD IOMUX_PAD(0x04AC, 0x01A4, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_ROW6__UART4_RXD IOMUX_PAD(0x04AC, 0x01A4, 1, 0x0814, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_ROW6__LCDIF_DAT_13 IOMUX_PAD(0x04AC, 0x01A4, 2, 0x07AC, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW6__WEIM_WEIM_DA_A_13 IOMUX_PAD(0x04AC, 0x01A4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW6__USDHC4_DAT3 IOMUX_PAD(0x04AC, 0x01A4, 4, 0x0868, 2, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_ROW6__GPIO_4_5 IOMUX_PAD(0x04AC, 0x01A4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW6__USDHC3_VSELECT IOMUX_PAD(0x04AC, 0x01A4, 6, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_ROW6__TPSMP_HDATA_13 IOMUX_PAD(0x04AC, 0x01A4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_KEY_ROW7__KPP_ROW_7 IOMUX_PAD(0x04B0, 0x01A8, 0, 0x0770, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW7__UART4_CTS IOMUX_PAD(0x04B0, 0x01A8, 1, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_ROW7__UART4_RTS IOMUX_PAD(0x04B0, 0x01A8, 1, 0x0810, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_KEY_ROW7__LCDIF_DAT_15 IOMUX_PAD(0x04B0, 0x01A8, 2, 0x07B4, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW7__WEIM_WEIM_DA_A_15 IOMUX_PAD(0x04B0, 0x01A8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_KEY_ROW7__USDHC4_DAT5 IOMUX_PAD(0x04B0, 0x01A8, 4, 0x0870, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_ROW7__GPIO_4_7 IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_ROW7__USDHC1_CD IOMUX_PAD(0x04B0, 0x01A8, 6, 0x0828, 3, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_KEY_ROW7__TPSMP_HDATA_15 IOMUX_PAD(0x04B0, 0x01A8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_CLK__LCDIF_CLK IOMUX_PAD(0x04B4, 0x01AC, 0, 0x0000, 0, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_CLK__USDHC4_DAT4 IOMUX_PAD(0x04B4, 0x01AC, 1, 0x086C, 2, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_LCD_CLK__LCDIF_WR_RWN IOMUX_PAD(0x04B4, 0x01AC, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_CLK__WEIM_WEIM_RW IOMUX_PAD(0x04B4, 0x01AC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_CLK__PWM4_PWMO IOMUX_PAD(0x04B4, 0x01AC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_CLK__GPIO_2_15 IOMUX_PAD(0x04B4, 0x01AC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_CLK__SRC_EARLY_RST IOMUX_PAD(0x04B4, 0x01AC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_CLK__TPSMP_HTRANS_0 IOMUX_PAD(0x04B4, 0x01AC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT0__LCDIF_DAT_0 IOMUX_PAD(0x04B8, 0x01B0, 0, 0x0778, 1, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_DAT0__ECSPI1_MOSI IOMUX_PAD(0x04B8, 0x01B0, 1, 0x0688, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT0__ANATOP_USBOTG2_ID IOMUX_PAD(0x04B8, 0x01B0, 2, 0x05E0, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT0__PWM1_PWMO IOMUX_PAD(0x04B8, 0x01B0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT0__UART5_DTR IOMUX_PAD(0x04B8, 0x01B0, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_DAT0__GPIO_2_20 IOMUX_PAD(0x04B8, 0x01B0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT0__KITTEN_TRACE_0 IOMUX_PAD(0x04B8, 0x01B0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT0__SRC_BT_CFG_0 IOMUX_PAD(0x04B8, 0x01B0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT1__LCDIF_DAT_1 IOMUX_PAD(0x04BC, 0x01B4, 0, 0x077C, 1, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_DAT1__ECSPI1_MISO IOMUX_PAD(0x04BC, 0x01B4, 1, 0x0684, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT1__ANATOP_USBOTG1_ID IOMUX_PAD(0x04BC, 0x01B4, 2, 0x05DC, 2, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT1__PWM2_PWMO IOMUX_PAD(0x04BC, 0x01B4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT1__AUDMUX_AUD4_RXFS IOMUX_PAD(0x04BC, 0x01B4, 4, 0x05F0, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT1__GPIO_2_21 IOMUX_PAD(0x04BC, 0x01B4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT1__KITTEN_TRACE_1 IOMUX_PAD(0x04BC, 0x01B4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT1__SRC_BT_CFG_1 IOMUX_PAD(0x04BC, 0x01B4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT10__LCDIF_DAT_10 IOMUX_PAD(0x04C0, 0x01B8, 0, 0x07A0, 1, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_DAT10__KPP_COL_1 IOMUX_PAD(0x04C0, 0x01B8, 1, 0x0738, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT10__CSI_D_7 IOMUX_PAD(0x04C0, 0x01B8, 2, 0x064C, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT10__WEIM_WEIM_D_4 IOMUX_PAD(0x04C0, 0x01B8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT10__ECSPI2_MISO IOMUX_PAD(0x04C0, 0x01B8, 4, 0x06A0, 2, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT10__GPIO_2_30 IOMUX_PAD(0x04C0, 0x01B8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT10__KITTEN_TRACE_10 IOMUX_PAD(0x04C0, 0x01B8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT10__SRC_BT_CFG_10 IOMUX_PAD(0x04C0, 0x01B8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT11__LCDIF_DAT_11 IOMUX_PAD(0x04C4, 0x01BC, 0, 0x07A4, 1, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_DAT11__KPP_ROW_1 IOMUX_PAD(0x04C4, 0x01BC, 1, 0x0758, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT11__CSI_D_6 IOMUX_PAD(0x04C4, 0x01BC, 2, 0x0648, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT11__WEIM_WEIM_D_5 IOMUX_PAD(0x04C4, 0x01BC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT11__ECSPI2_SS1 IOMUX_PAD(0x04C4, 0x01BC, 4, 0x06AC, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT11__GPIO_2_31 IOMUX_PAD(0x04C4, 0x01BC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT11__KITTEN_TRACE_11 IOMUX_PAD(0x04C4, 0x01BC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT11__SRC_BT_CFG_11 IOMUX_PAD(0x04C4, 0x01BC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT12__LCDIF_DAT_12 IOMUX_PAD(0x04C8, 0x01C0, 0, 0x07A8, 1, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_DAT12__KPP_COL_2 IOMUX_PAD(0x04C8, 0x01C0, 1, 0x073C, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT12__CSI_D_5 IOMUX_PAD(0x04C8, 0x01C0, 2, 0x0644, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT12__WEIM_WEIM_D_6 IOMUX_PAD(0x04C8, 0x01C0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT12__UART5_CTS IOMUX_PAD(0x04C8, 0x01C0, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_DAT12__UART5_RTS IOMUX_PAD(0x04C8, 0x01C0, 4, 0x0818, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_DAT12__GPIO_3_0 IOMUX_PAD(0x04C8, 0x01C0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT12__KITTEN_TRACE_12 IOMUX_PAD(0x04C8, 0x01C0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT12__SRC_BT_CFG_12 IOMUX_PAD(0x04C8, 0x01C0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT13__LCDIF_DAT_13 IOMUX_PAD(0x04CC, 0x01C4, 0, 0x07AC, 1, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_DAT13__KPP_ROW_2 IOMUX_PAD(0x04CC, 0x01C4, 1, 0x075C, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT13__CSI_D_4 IOMUX_PAD(0x04CC, 0x01C4, 2, 0x0640, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT13__WEIM_WEIM_D_7 IOMUX_PAD(0x04CC, 0x01C4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT13__UART5_CTS IOMUX_PAD(0x04CC, 0x01C4, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_DAT13__UART5_RTS IOMUX_PAD(0x04CC, 0x01C4, 4, 0x0818, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_DAT13__GPIO_3_1 IOMUX_PAD(0x04CC, 0x01C4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT13__KITTEN_TRACE_13 IOMUX_PAD(0x04CC, 0x01C4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT13__SRC_BT_CFG_13 IOMUX_PAD(0x04CC, 0x01C4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT14__LCDIF_DAT_14 IOMUX_PAD(0x04D0, 0x01C8, 0, 0x07B0, 1, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_DAT14__KPP_COL_3 IOMUX_PAD(0x04D0, 0x01C8, 1, 0x0740, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT14__CSI_D_3 IOMUX_PAD(0x04D0, 0x01C8, 2, 0x063C, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT14__WEIM_WEIM_D_8 IOMUX_PAD(0x04D0, 0x01C8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT14__UART5_TXD IOMUX_PAD(0x04D0, 0x01C8, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_DAT14__UART5_RXD IOMUX_PAD(0x04D0, 0x01C8, 4, 0x081C, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_DAT14__GPIO_3_2 IOMUX_PAD(0x04D0, 0x01C8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT14__KITTEN_TRACE_14 IOMUX_PAD(0x04D0, 0x01C8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT14__SRC_BT_CFG_14 IOMUX_PAD(0x04D0, 0x01C8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT15__LCDIF_DAT_15 IOMUX_PAD(0x04D4, 0x01CC, 0, 0x07B4, 1, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_DAT15__KPP_ROW_3 IOMUX_PAD(0x04D4, 0x01CC, 1, 0x0760, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT15__CSI_D_2 IOMUX_PAD(0x04D4, 0x01CC, 2, 0x0638, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT15__WEIM_WEIM_D_9 IOMUX_PAD(0x04D4, 0x01CC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT15__UART5_TXD IOMUX_PAD(0x04D4, 0x01CC, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_DAT15__UART5_RXD IOMUX_PAD(0x04D4, 0x01CC, 4, 0x081C, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_DAT15__GPIO_3_3 IOMUX_PAD(0x04D4, 0x01CC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT15__KITTEN_TRACE_15 IOMUX_PAD(0x04D4, 0x01CC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT15__SRC_BT_CFG_15 IOMUX_PAD(0x04D4, 0x01CC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT16__LCDIF_DAT_16 IOMUX_PAD(0x04D8, 0x01D0, 0, 0x07B8, 1, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_DAT16__KPP_COL_4 IOMUX_PAD(0x04D8, 0x01D0, 1, 0x0744, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT16__CSI_D_1 IOMUX_PAD(0x04D8, 0x01D0, 2, 0x0634, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT16__WEIM_WEIM_D_10 IOMUX_PAD(0x04D8, 0x01D0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT16__I2C2_SCL IOMUX_PAD(0x04D8, 0x01D0, 4 | MUX_CONFIG_SION, 0x0724, 3, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_LCD_DAT16__GPIO_3_4 IOMUX_PAD(0x04D8, 0x01D0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT16__KITTEN_TRACE_16 IOMUX_PAD(0x04D8, 0x01D0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT16__SRC_BT_CFG_24 IOMUX_PAD(0x04D8, 0x01D0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT17__LCDIF_DAT_17 IOMUX_PAD(0x04DC, 0x01D4, 0, 0x07BC, 1, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_DAT17__KPP_ROW_4 IOMUX_PAD(0x04DC, 0x01D4, 1, 0x0764, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT17__CSI_D_0 IOMUX_PAD(0x04DC, 0x01D4, 2, 0x0630, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT17__WEIM_WEIM_D_11 IOMUX_PAD(0x04DC, 0x01D4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT17__I2C2_SDA IOMUX_PAD(0x04DC, 0x01D4, 4 | MUX_CONFIG_SION, 0x0728, 3, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_LCD_DAT17__GPIO_3_5 IOMUX_PAD(0x04DC, 0x01D4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT17__KITTEN_TRACE_17 IOMUX_PAD(0x04DC, 0x01D4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT17__SRC_BT_CFG_25 IOMUX_PAD(0x04DC, 0x01D4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT18__LCDIF_DAT_18 IOMUX_PAD(0x04E0, 0x01D8, 0, 0x07C0, 1, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_DAT18__KPP_COL_5 IOMUX_PAD(0x04E0, 0x01D8, 1, 0x0748, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT18__CSI_D_15 IOMUX_PAD(0x04E0, 0x01D8, 2, 0x066C, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT18__WEIM_WEIM_D_12 IOMUX_PAD(0x04E0, 0x01D8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT18__GPT_CAPIN1 IOMUX_PAD(0x04E0, 0x01D8, 4, 0x0710, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT18__GPIO_3_6 IOMUX_PAD(0x04E0, 0x01D8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT18__KITTEN_TRACE_18 IOMUX_PAD(0x04E0, 0x01D8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT18__SRC_BT_CFG_26 IOMUX_PAD(0x04E0, 0x01D8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT19__LCDIF_DAT_19 IOMUX_PAD(0x04E4, 0x01DC, 0, 0x07C4, 1, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_DAT19__KPP_ROW_5 IOMUX_PAD(0x04E4, 0x01DC, 1, 0x0768, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT19__CSI_D_14 IOMUX_PAD(0x04E4, 0x01DC, 2, 0x0668, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT19__WEIM_WEIM_D_13 IOMUX_PAD(0x04E4, 0x01DC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT19__GPT_CAPIN2 IOMUX_PAD(0x04E4, 0x01DC, 4, 0x0714, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT19__GPIO_3_7 IOMUX_PAD(0x04E4, 0x01DC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT19__KITTEN_TRACE_19 IOMUX_PAD(0x04E4, 0x01DC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT19__SRC_BT_CFG_27 IOMUX_PAD(0x04E4, 0x01DC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT2__LCDIF_DAT_2 IOMUX_PAD(0x04E8, 0x01E0, 0, 0x0780, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT2__ECSPI1_SS0 IOMUX_PAD(0x04E8, 0x01E0, 1, 0x068C, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT2__EPIT2_EPITO IOMUX_PAD(0x04E8, 0x01E0, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT2__PWM3_PWMO IOMUX_PAD(0x04E8, 0x01E0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT2__AUDMUX_AUD4_RXC IOMUX_PAD(0x04E8, 0x01E0, 4, 0x05EC, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT2__GPIO_2_22 IOMUX_PAD(0x04E8, 0x01E0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT2__KITTEN_TRACE_2 IOMUX_PAD(0x04E8, 0x01E0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT2__SRC_BT_CFG_2 IOMUX_PAD(0x04E8, 0x01E0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT20__LCDIF_DAT_20 IOMUX_PAD(0x04EC, 0x01E4, 0, 0x07C8, 1, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_DAT20__KPP_COL_6 IOMUX_PAD(0x04EC, 0x01E4, 1, 0x074C, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT20__CSI_D_13 IOMUX_PAD(0x04EC, 0x01E4, 2, 0x0664, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT20__WEIM_WEIM_D_14 IOMUX_PAD(0x04EC, 0x01E4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT20__GPT_CMPOUT1 IOMUX_PAD(0x04EC, 0x01E4, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT20__GPIO_3_8 IOMUX_PAD(0x04EC, 0x01E4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT20__KITTEN_TRACE_20 IOMUX_PAD(0x04EC, 0x01E4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT20__SRC_BT_CFG_28 IOMUX_PAD(0x04EC, 0x01E4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT21__LCDIF_DAT_21 IOMUX_PAD(0x04F0, 0x01E8, 0, 0x07CC, 1, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_DAT21__KPP_ROW_6 IOMUX_PAD(0x04F0, 0x01E8, 1, 0x076C, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT21__CSI_D_12 IOMUX_PAD(0x04F0, 0x01E8, 2, 0x0660, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT21__WEIM_WEIM_D_15 IOMUX_PAD(0x04F0, 0x01E8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT21__GPT_CMPOUT2 IOMUX_PAD(0x04F0, 0x01E8, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT21__GPIO_3_9 IOMUX_PAD(0x04F0, 0x01E8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT21__KITTEN_TRACE_21 IOMUX_PAD(0x04F0, 0x01E8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT21__SRC_BT_CFG_29 IOMUX_PAD(0x04F0, 0x01E8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT22__LCDIF_DAT_22 IOMUX_PAD(0x04F4, 0x01EC, 0, 0x07D0, 1, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_DAT22__KPP_COL_7 IOMUX_PAD(0x04F4, 0x01EC, 1, 0x0750, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT22__CSI_D_11 IOMUX_PAD(0x04F4, 0x01EC, 2, 0x065C, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT22__WEIM_WEIM_EB_3 IOMUX_PAD(0x04F4, 0x01EC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT22__GPT_CMPOUT3 IOMUX_PAD(0x04F4, 0x01EC, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT22__GPIO_3_10 IOMUX_PAD(0x04F4, 0x01EC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT22__KITTEN_TRACE_22 IOMUX_PAD(0x04F4, 0x01EC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT22__SRC_BT_CFG_30 IOMUX_PAD(0x04F4, 0x01EC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT23__LCDIF_DAT_23 IOMUX_PAD(0x04F8, 0x01F0, 0, 0x07D4, 1, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_DAT23__KPP_ROW_7 IOMUX_PAD(0x04F8, 0x01F0, 1, 0x0770, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT23__CSI_D_10 IOMUX_PAD(0x04F8, 0x01F0, 2, 0x0658, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT23__WEIM_WEIM_EB_2 IOMUX_PAD(0x04F8, 0x01F0, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT23__GPT_CLKIN IOMUX_PAD(0x04F8, 0x01F0, 4, 0x0718, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT23__GPIO_3_11 IOMUX_PAD(0x04F8, 0x01F0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT23__KITTEN_TRACE_23 IOMUX_PAD(0x04F8, 0x01F0, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT23__SRC_BT_CFG_31 IOMUX_PAD(0x04F8, 0x01F0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT3__LCDIF_DAT_3 IOMUX_PAD(0x04FC, 0x01F4, 0, 0x0784, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT3__ECSPI1_SCLK IOMUX_PAD(0x04FC, 0x01F4, 1, 0x067C, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT3__UART5_DSR IOMUX_PAD(0x04FC, 0x01F4, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_DAT3__PWM4_PWMO IOMUX_PAD(0x04FC, 0x01F4, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT3__AUDMUX_AUD4_RXD IOMUX_PAD(0x04FC, 0x01F4, 4, 0x05E4, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT3__GPIO_2_23 IOMUX_PAD(0x04FC, 0x01F4, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT3__KITTEN_TRACE_3 IOMUX_PAD(0x04FC, 0x01F4, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT3__SRC_BT_CFG_3 IOMUX_PAD(0x04FC, 0x01F4, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT4__LCDIF_DAT_4 IOMUX_PAD(0x0500, 0x01F8, 0, 0x0788, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT4__ECSPI1_SS1 IOMUX_PAD(0x0500, 0x01F8, 1, 0x0690, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT4__CSI_VSYNC IOMUX_PAD(0x0500, 0x01F8, 2, 0x0678, 2, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT4__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x0500, 0x01F8, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT4__AUDMUX_AUD4_TXC IOMUX_PAD(0x0500, 0x01F8, 4, 0x05F4, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT4__GPIO_2_24 IOMUX_PAD(0x0500, 0x01F8, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT4__KITTEN_TRACE_4 IOMUX_PAD(0x0500, 0x01F8, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT4__SRC_BT_CFG_4 IOMUX_PAD(0x0500, 0x01F8, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT5__LCDIF_DAT_5 IOMUX_PAD(0x0504, 0x01FC, 0, 0x078C, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT5__ECSPI1_SS2 IOMUX_PAD(0x0504, 0x01FC, 1, 0x0694, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT5__CSI_HSYNC IOMUX_PAD(0x0504, 0x01FC, 2, 0x0670, 2, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT5__WEIM_WEIM_CS_3 IOMUX_PAD(0x0504, 0x01FC, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT5__AUDMUX_AUD4_TXFS IOMUX_PAD(0x0504, 0x01FC, 4, 0x05F8, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT5__GPIO_2_25 IOMUX_PAD(0x0504, 0x01FC, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT5__KITTEN_TRACE_5 IOMUX_PAD(0x0504, 0x01FC, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT5__SRC_BT_CFG_5 IOMUX_PAD(0x0504, 0x01FC, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT6__LCDIF_DAT_6 IOMUX_PAD(0x0508, 0x0200, 0, 0x0790, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT6__ECSPI1_SS3 IOMUX_PAD(0x0508, 0x0200, 1, 0x0698, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT6__CSI_PIXCLK IOMUX_PAD(0x0508, 0x0200, 2, 0x0674, 2, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT6__WEIM_WEIM_D_0 IOMUX_PAD(0x0508, 0x0200, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT6__AUDMUX_AUD4_TXD IOMUX_PAD(0x0508, 0x0200, 4, 0x05E8, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT6__GPIO_2_26 IOMUX_PAD(0x0508, 0x0200, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT6__KITTEN_TRACE_6 IOMUX_PAD(0x0508, 0x0200, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT6__SRC_BT_CFG_6 IOMUX_PAD(0x0508, 0x0200, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT7__LCDIF_DAT_7 IOMUX_PAD(0x050C, 0x0204, 0, 0x0794, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT7__ECSPI1_RDY IOMUX_PAD(0x050C, 0x0204, 1, 0x0680, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT7__CSI_MCLK IOMUX_PAD(0x050C, 0x0204, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT7__WEIM_WEIM_D_1 IOMUX_PAD(0x050C, 0x0204, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT7__AUDMUX_AUDIO_CLK_OUT IOMUX_PAD(0x050C, 0x0204, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT7__GPIO_2_27 IOMUX_PAD(0x050C, 0x0204, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT7__KITTEN_TRACE_7 IOMUX_PAD(0x050C, 0x0204, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT7__SRC_BT_CFG_7 IOMUX_PAD(0x050C, 0x0204, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT8__LCDIF_DAT_8 IOMUX_PAD(0x0510, 0x0208, 0, 0x0798, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT8__KPP_COL_0 IOMUX_PAD(0x0510, 0x0208, 1, 0x0734, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT8__CSI_D_9 IOMUX_PAD(0x0510, 0x0208, 2, 0x0654, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT8__WEIM_WEIM_D_2 IOMUX_PAD(0x0510, 0x0208, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT8__ECSPI2_SCLK IOMUX_PAD(0x0510, 0x0208, 4, 0x069C, 2, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT8__GPIO_2_28 IOMUX_PAD(0x0510, 0x0208, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT8__KITTEN_TRACE_8 IOMUX_PAD(0x0510, 0x0208, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT8__SRC_BT_CFG_8 IOMUX_PAD(0x0510, 0x0208, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_DAT9__LCDIF_DAT_9 IOMUX_PAD(0x0514, 0x020C, 0, 0x079C, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT9__KPP_ROW_0 IOMUX_PAD(0x0514, 0x020C, 1, 0x0754, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT9__CSI_D_8 IOMUX_PAD(0x0514, 0x020C, 2, 0x0650, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT9__WEIM_WEIM_D_3 IOMUX_PAD(0x0514, 0x020C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT9__ECSPI2_MOSI IOMUX_PAD(0x0514, 0x020C, 4, 0x06A4, 2, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT9__GPIO_2_29 IOMUX_PAD(0x0514, 0x020C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT9__KITTEN_TRACE_9 IOMUX_PAD(0x0514, 0x020C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_DAT9__SRC_BT_CFG_9 IOMUX_PAD(0x0514, 0x020C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_ENABLE__LCDIF_ENABLE IOMUX_PAD(0x0518, 0x0210, 0, 0x0000, 0, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_ENABLE__USDHC4_DAT5 IOMUX_PAD(0x0518, 0x0210, 1, 0x0870, 2, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_LCD_ENABLE__LCDIF_RD_E IOMUX_PAD(0x0518, 0x0210, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_ENABLE__WEIM_WEIM_OE IOMUX_PAD(0x0518, 0x0210, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_ENABLE__UART2_TXD IOMUX_PAD(0x0518, 0x0210, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_ENABLE__UART2_RXD IOMUX_PAD(0x0518, 0x0210, 4, 0x0804, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_ENABLE__GPIO_2_16 IOMUX_PAD(0x0518, 0x0210, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_ENABLE__OCOTP_CTRL_WRAPPER_FUSE_LATCHED IOMUX_PAD(0x0518, 0x0210, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_ENABLE__TPSMP_HTRANS_1 IOMUX_PAD(0x0518, 0x0210, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_HSYNC__LCDIF_HSYNC IOMUX_PAD(0x051C, 0x0214, 0, 0x0774, 0, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_HSYNC__USDHC4_DAT6 IOMUX_PAD(0x051C, 0x0214, 1, 0x0874, 2, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_LCD_HSYNC__LCDIF_CS IOMUX_PAD(0x051C, 0x0214, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_HSYNC__WEIM_WEIM_CS_0 IOMUX_PAD(0x051C, 0x0214, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_HSYNC__UART2_TXD IOMUX_PAD(0x051C, 0x0214, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_HSYNC__UART2_RXD IOMUX_PAD(0x051C, 0x0214, 4, 0x0804, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_HSYNC__GPIO_2_17 IOMUX_PAD(0x051C, 0x0214, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_HSYNC__KITTEN_TRCLK IOMUX_PAD(0x051C, 0x0214, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_HSYNC__TPSMP_HDATA_16 IOMUX_PAD(0x051C, 0x0214, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_RESET__LCDIF_RESET IOMUX_PAD(0x0520, 0x0218, 0, 0x0000, 0, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_RESET__WEIM_WEIM_DTACK_B IOMUX_PAD(0x0520, 0x0218, 1, 0x0880, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_RESET__LCDIF_BUSY IOMUX_PAD(0x0520, 0x0218, 2, 0x0774, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_RESET__WEIM_WEIM_WAIT IOMUX_PAD(0x0520, 0x0218, 3, 0x0884, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_RESET__UART2_CTS IOMUX_PAD(0x0520, 0x0218, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_RESET__UART2_RTS IOMUX_PAD(0x0520, 0x0218, 4, 0x0800, 2, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_RESET__GPIO_2_19 IOMUX_PAD(0x0520, 0x0218, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_RESET__CCM_PMIC_RDY IOMUX_PAD(0x0520, 0x0218, 6, 0x062C, 1, NO_PAD_CTRL)
+#define MX6_PAD_LCD_RESET__TPSMP_HDATA_DIR IOMUX_PAD(0x0520, 0x0218, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_LCD_VSYNC__LCDIF_VSYNC IOMUX_PAD(0x0524, 0x021C, 0, 0x0000, 0, MX6_LCDIF_PAD_CTRL)
+#define MX6_PAD_LCD_VSYNC__USDHC4_DAT7 IOMUX_PAD(0x0524, 0x021C, 1, 0x0878, 2, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_LCD_VSYNC__LCDIF_RS IOMUX_PAD(0x0524, 0x021C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_VSYNC__WEIM_WEIM_CS_1 IOMUX_PAD(0x0524, 0x021C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_VSYNC__UART2_CTS IOMUX_PAD(0x0524, 0x021C, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_VSYNC__UART2_RTS IOMUX_PAD(0x0524, 0x021C, 4, 0x0800, 3, MX6_UART_PAD_CTRL)
+#define MX6_PAD_LCD_VSYNC__GPIO_2_18 IOMUX_PAD(0x0524, 0x021C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_VSYNC__KITTEN_TRCTL IOMUX_PAD(0x0524, 0x021C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_LCD_VSYNC__TPSMP_HDATA_17 IOMUX_PAD(0x0524, 0x021C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_PWM1__PWM1_PWMO IOMUX_PAD(0x0528, 0x0220, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_PWM1__CCM_CLKO IOMUX_PAD(0x0528, 0x0220, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_PWM1__AUDMUX_AUDIO_CLK_OUT IOMUX_PAD(0x0528, 0x0220, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_PWM1__FEC_REF_OUT IOMUX_PAD(0x0528, 0x0220, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_PWM1__CSI_MCLK IOMUX_PAD(0x0528, 0x0220, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_PWM1__GPIO_3_23 IOMUX_PAD(0x0528, 0x0220, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_PWM1__EPIT1_EPITO IOMUX_PAD(0x0528, 0x0220, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_PWM1__OBSERVE_MUX_OUT_4 IOMUX_PAD(0x0528, 0x0220, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_REF_CLK_24M__ANATOP_ANATOP_24M_OUT IOMUX_PAD(0x052C, 0x0224, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_REF_CLK_24M__I2C3_SCL IOMUX_PAD(0x052C, 0x0224, 1 | MUX_CONFIG_SION, 0x072C, 2, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_REF_CLK_24M__PWM3_PWMO IOMUX_PAD(0x052C, 0x0224, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_REF_CLK_24M__ANATOP_USBOTG2_ID IOMUX_PAD(0x052C, 0x0224, 3, 0x05E0, 2, NO_PAD_CTRL)
+#define MX6_PAD_REF_CLK_24M__CCM_PMIC_RDY IOMUX_PAD(0x052C, 0x0224, 4, 0x062C, 2, NO_PAD_CTRL)
+#define MX6_PAD_REF_CLK_24M__GPIO_3_21 IOMUX_PAD(0x052C, 0x0224, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_REF_CLK_24M__USDHC3_WP IOMUX_PAD(0x052C, 0x0224, 6, 0x084C, 3, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_REF_CLK_24M__TPSMP_HDATA_19 IOMUX_PAD(0x052C, 0x0224, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_REF_CLK_32K__ANATOP_ANATOP_32K_OUT IOMUX_PAD(0x0530, 0x0228, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_REF_CLK_32K__I2C3_SDA IOMUX_PAD(0x0530, 0x0228, 1 | MUX_CONFIG_SION, 0x0730, 2, MX6_I2C_PAD_CTRL)
+#define MX6_PAD_REF_CLK_32K__PWM4_PWMO IOMUX_PAD(0x0530, 0x0228, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_REF_CLK_32K__ANATOP_USBOTG1_ID IOMUX_PAD(0x0530, 0x0228, 3, 0x05DC, 3, NO_PAD_CTRL)
+#define MX6_PAD_REF_CLK_32K__USDHC1_LCTL IOMUX_PAD(0x0530, 0x0228, 4, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_REF_CLK_32K__GPIO_3_22 IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_REF_CLK_32K__USDHC3_CD IOMUX_PAD(0x0530, 0x0228, 6, 0x0838, 3, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_REF_CLK_32K__OBSERVE_MUX_OUT_3 IOMUX_PAD(0x0530, 0x0228, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD1_CLK__USDHC1_CLK_50MHZ IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD1_CLK__USDHC1_CLK_100MHZ IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD1_CLK__USDHC1_CLK_200MHZ IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD1_CLK__FEC_MDIO IOMUX_PAD(0x0534, 0x022C, 1, 0x06F4, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CLK__KPP_COL_0 IOMUX_PAD(0x0534, 0x022C, 2, 0x0734, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CLK__EPDC_SDCE_4 IOMUX_PAD(0x0534, 0x022C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CLK__MSHC_SCLK IOMUX_PAD(0x0534, 0x022C, 4, 0x07E8, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CLK__GPIO_5_15 IOMUX_PAD(0x0534, 0x022C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CLK__ANATOP_ANATOP_TESTO_2 IOMUX_PAD(0x0534, 0x022C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CLK__PL301_SIM_MX6_PER1_HADDR_25 IOMUX_PAD(0x0534, 0x022C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD1_CMD__USDHC1_CMD_50MHZ IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD1_CMD__USDHC1_CMD_100MHZ IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD1_CMD__USDHC1_CMD_200MHZ IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD1_CMD__FEC_TX_CLK IOMUX_PAD(0x0538, 0x0230, 1, 0x070C, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CMD__KPP_ROW_0 IOMUX_PAD(0x0538, 0x0230, 2, 0x0754, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CMD__EPDC_SDCE_5 IOMUX_PAD(0x0538, 0x0230, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CMD__MSHC_BS IOMUX_PAD(0x0538, 0x0230, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CMD__GPIO_5_14 IOMUX_PAD(0x0538, 0x0230, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_3 IOMUX_PAD(0x0538, 0x0230, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_CMD__PL301_SIM_MX6_PER1_HADDR_26 IOMUX_PAD(0x0538, 0x0230, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD1_DAT0__USDHC1_DAT0_50MHZ IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD1_DAT0__USDHC1_DAT0_100MHZ IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD1_DAT0__USDHC1_DAT0_200MHZ IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD1_DAT0__FEC_RX_ER IOMUX_PAD(0x053C, 0x0234, 1, 0x0708, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT0__KPP_COL_1 IOMUX_PAD(0x053C, 0x0234, 2, 0x0738, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT0__EPDC_SDCE_6 IOMUX_PAD(0x053C, 0x0234, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT0__MSHC_DATA_0 IOMUX_PAD(0x053C, 0x0234, 4, 0x07D8, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT0__GPIO_5_11 IOMUX_PAD(0x053C, 0x0234, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_4 IOMUX_PAD(0x053C, 0x0234, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT0__PL301_SIM_MX6_PER1_HADDR_27 IOMUX_PAD(0x053C, 0x0234, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD1_DAT1__USDHC1_DAT1_50MHZ IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD1_DAT1__USDHC1_DAT1_100MHZ IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD1_DAT1__USDHC1_DAT1_200MHZ IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD1_DAT1__FEC_RX_DV IOMUX_PAD(0x0540, 0x0238, 1, 0x0704, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT1__KPP_ROW_1 IOMUX_PAD(0x0540, 0x0238, 2, 0x0758, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT1__EPDC_SDCE_7 IOMUX_PAD(0x0540, 0x0238, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT1__MSHC_DATA_1 IOMUX_PAD(0x0540, 0x0238, 4, 0x07DC, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT1__GPIO_5_8 IOMUX_PAD(0x0540, 0x0238, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_5 IOMUX_PAD(0x0540, 0x0238, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT1__PL301_SIM_MX6_PER1_HADDR_28 IOMUX_PAD(0x0540, 0x0238, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD1_DAT2__USDHC1_DAT2_50MHZ IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD1_DAT2__USDHC1_DAT2_100MHZ IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD1_DAT2__USDHC1_DAT2_200MHZ IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD1_DAT2__FEC_RDATA_1 IOMUX_PAD(0x0544, 0x023C, 1, 0x06FC, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT2__KPP_COL_2 IOMUX_PAD(0x0544, 0x023C, 2, 0x073C, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT2__EPDC_SDCE_8 IOMUX_PAD(0x0544, 0x023C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT2__MSHC_DATA_2 IOMUX_PAD(0x0544, 0x023C, 4, 0x07E0, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT2__GPIO_5_13 IOMUX_PAD(0x0544, 0x023C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_6 IOMUX_PAD(0x0544, 0x023C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT2__PL301_SIM_MX6_PER1_HADDR_29 IOMUX_PAD(0x0544, 0x023C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD1_DAT3__USDHC1_DAT3_50MHZ IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD1_DAT3__USDHC1_DAT3_100MHZ IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD1_DAT3__USDHC1_DAT3_200MHZ IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD1_DAT3__FEC_TDATA_0 IOMUX_PAD(0x0548, 0x0240, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT3__KPP_ROW_2 IOMUX_PAD(0x0548, 0x0240, 2, 0x075C, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT3__EPDC_SDCE_9 IOMUX_PAD(0x0548, 0x0240, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT3__MSHC_DATA_3 IOMUX_PAD(0x0548, 0x0240, 4, 0x07E4, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT3__GPIO_5_6 IOMUX_PAD(0x0548, 0x0240, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_7 IOMUX_PAD(0x0548, 0x0240, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT3__PL301_SIM_MX6_PER1_HADDR_30 IOMUX_PAD(0x0548, 0x0240, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD1_DAT4__USDHC1_DAT4_50MHZ IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD1_DAT4__USDHC1_DAT4_100MHZ IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD1_DAT4__USDHC1_DAT4_200MHZ IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD1_DAT4__FEC_MDC IOMUX_PAD(0x054C, 0x0244, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT4__KPP_COL_3 IOMUX_PAD(0x054C, 0x0244, 2, 0x0740, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT4__EPDC_SDCLKN IOMUX_PAD(0x054C, 0x0244, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT4__UART4_TXD IOMUX_PAD(0x054C, 0x0244, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD1_DAT4__UART4_RXD IOMUX_PAD(0x054C, 0x0244, 4, 0x0814, 4, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD1_DAT4__GPIO_5_12 IOMUX_PAD(0x054C, 0x0244, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT4__ANATOP_ANATOP_TESTO_8 IOMUX_PAD(0x054C, 0x0244, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT4__PL301_SIM_MX6_PER1_HADDR_31 IOMUX_PAD(0x054C, 0x0244, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD1_DAT5__USDHC1_DAT5_50MHZ IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD1_DAT5__USDHC1_DAT5_100MHZ IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD1_DAT5__USDHC1_DAT5_200MHZ IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD1_DAT5__FEC_RDATA_0 IOMUX_PAD(0x0550, 0x0248, 1, 0x06F8, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT5__KPP_ROW_3 IOMUX_PAD(0x0550, 0x0248, 2, 0x0760, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT5__EPDC_SDOED IOMUX_PAD(0x0550, 0x0248, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT5__UART4_TXD IOMUX_PAD(0x0550, 0x0248, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD1_DAT5__UART4_RXD IOMUX_PAD(0x0550, 0x0248, 4, 0x0814, 5, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD1_DAT5__GPIO_5_9 IOMUX_PAD(0x0550, 0x0248, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT5__ANATOP_ANATOP_TESTO_9 IOMUX_PAD(0x0550, 0x0248, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT5__PL301_SIM_MX6_PER1_HPROT_3 IOMUX_PAD(0x0550, 0x0248, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD1_DAT6__USDHC1_DAT6_50MHZ IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD1_DAT6__USDHC1_DAT6_100MHZ IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD1_DAT6__USDHC1_DAT6_200MHZ IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD1_DAT6__FEC_TX_EN IOMUX_PAD(0x0554, 0x024C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT6__KPP_COL_4 IOMUX_PAD(0x0554, 0x024C, 2, 0x0744, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT6__EPDC_SDOEZ IOMUX_PAD(0x0554, 0x024C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT6__UART4_CTS IOMUX_PAD(0x0554, 0x024C, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD1_DAT6__UART4_RTS IOMUX_PAD(0x0554, 0x024C, 4, 0x0810, 4, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD1_DAT6__GPIO_5_7 IOMUX_PAD(0x0554, 0x024C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT6__ANATOP_ANATOP_TESTO_10 IOMUX_PAD(0x0554, 0x024C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT6__PL301_SIM_MX6_PER1_HPROT_2 IOMUX_PAD(0x0554, 0x024C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD1_DAT7__USDHC1_DAT7_50MHZ IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD1_DAT7__USDHC1_DAT7_100MHZ IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD1_DAT7__USDHC1_DAT7_200MHZ IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD1_DAT7__FEC_TDATA_1 IOMUX_PAD(0x0558, 0x0250, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT7__KPP_ROW_4 IOMUX_PAD(0x0558, 0x0250, 2, 0x0764, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT7__CCM_PMIC_RDY IOMUX_PAD(0x0558, 0x0250, 3, 0x062C, 3, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT7__UART4_CTS IOMUX_PAD(0x0558, 0x0250, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD1_DAT7__UART4_RTS IOMUX_PAD(0x0558, 0x0250, 4, 0x0810, 5, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD1_DAT7__GPIO_5_10 IOMUX_PAD(0x0558, 0x0250, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT7__ANATOP_ANATOP_TESTO_11 IOMUX_PAD(0x0558, 0x0250, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD1_DAT7__PL301_SIM_MX6_PER1_HMASTLOCK IOMUX_PAD(0x0558, 0x0250, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD2_CLK__USDHC2_CLK_50MHZ IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_CLK__USDHC2_CLK_100MHZ IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD2_CLK__USDHC2_CLK_200MHZ IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x055C, 0x0254, 1, 0x05F0, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CLK__ECSPI3_SCLK IOMUX_PAD(0x055C, 0x0254, 2, 0x06B0, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CLK__CSI_D_0 IOMUX_PAD(0x055C, 0x0254, 3, 0x0630, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CLK__OSC32K_32K_OUT IOMUX_PAD(0x055C, 0x0254, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CLK__GPIO_5_5 IOMUX_PAD(0x055C, 0x0254, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CLK__ANATOP_ANATOP_TESTO_13 IOMUX_PAD(0x055C, 0x0254, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CLK__PL301_SIM_MX6_PER1_HPROT_1 IOMUX_PAD(0x055C, 0x0254, 7, 0x07EC, 1, NO_PAD_CTRL)
+
+#define MX6_PAD_SD2_CMD__USDHC2_CMD_50MHZ IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_CMD__USDHC2_CMD_100MHZ IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD2_CMD__USDHC2_CMD_200MHZ IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x0560, 0x0258, 1, 0x05EC, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CMD__ECSPI3_SS0 IOMUX_PAD(0x0560, 0x0258, 2, 0x06C0, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CMD__CSI_D_1 IOMUX_PAD(0x0560, 0x0258, 3, 0x0634, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CMD__EPIT1_EPITO IOMUX_PAD(0x0560, 0x0258, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CMD__GPIO_5_4 IOMUX_PAD(0x0560, 0x0258, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CMD__ANATOP_ANATOP_TESTO_14 IOMUX_PAD(0x0560, 0x0258, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_CMD__PL301_SIM_MX6_PER1_HADDR_21 IOMUX_PAD(0x0560, 0x0258, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD2_DAT0__USDHC2_DAT0_50MHZ IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT0__USDHC2_DAT0_100MHZ IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD2_DAT0__USDHC2_DAT0_200MHZ IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD IOMUX_PAD(0x0564, 0x025C, 1, 0x05E4, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT0__ECSPI3_MOSI IOMUX_PAD(0x0564, 0x025C, 2, 0x06BC, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT0__CSI_D_2 IOMUX_PAD(0x0564, 0x025C, 3, 0x0638, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT0__UART5_CTS IOMUX_PAD(0x0564, 0x025C, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD2_DAT0__UART5_RTS IOMUX_PAD(0x0564, 0x025C, 4, 0x0818, 4, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD2_DAT0__GPIO_5_1 IOMUX_PAD(0x0564, 0x025C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_15 IOMUX_PAD(0x0564, 0x025C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT0__PL301_SIM_MX6_PER1_HPROT_0 IOMUX_PAD(0x0564, 0x025C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD2_DAT1__USDHC2_DAT1_50MHZ IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT1__USDHC2_DAT1_100MHZ IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD2_DAT1__USDHC2_DAT1_200MHZ IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXC IOMUX_PAD(0x0568, 0x0260, 1, 0x05F4, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT1__ECSPI3_MISO IOMUX_PAD(0x0568, 0x0260, 2, 0x06B8, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT1__CSI_D_3 IOMUX_PAD(0x0568, 0x0260, 3, 0x063C, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT1__UART5_CTS IOMUX_PAD(0x0568, 0x0260, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD2_DAT1__UART5_RTS IOMUX_PAD(0x0568, 0x0260, 4, 0x0818, 5, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD2_DAT1__GPIO_4_30 IOMUX_PAD(0x0568, 0x0260, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT1__MMDC_MMDC_DEBUG_39 IOMUX_PAD(0x0568, 0x0260, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT1__PL301_SIM_MX6_PER1_HBURST_1 IOMUX_PAD(0x0568, 0x0260, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD2_DAT2__USDHC2_DAT2_50MHZ IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT2__USDHC2_DAT2_100MHZ IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD2_DAT2__USDHC2_DAT2_200MHZ IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXFS IOMUX_PAD(0x056C, 0x0264, 1, 0x05F8, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT2__FEC_COL IOMUX_PAD(0x056C, 0x0264, 2, 0x06F0, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT2__CSI_D_4 IOMUX_PAD(0x056C, 0x0264, 3, 0x0640, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT2__UART5_TXD IOMUX_PAD(0x056C, 0x0264, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD2_DAT2__UART5_RXD IOMUX_PAD(0x056C, 0x0264, 4, 0x081C, 4, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD2_DAT2__GPIO_5_3 IOMUX_PAD(0x056C, 0x0264, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT2__MMDC_MMDC_DEBUG_38 IOMUX_PAD(0x056C, 0x0264, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT2__PL301_SIM_MX6_PER1_HADDR_22 IOMUX_PAD(0x056C, 0x0264, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD2_DAT3__USDHC2_DAT3_50MHZ IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT3__USDHC2_DAT3_100MHZ IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD2_DAT3__USDHC2_DAT3_200MHZ IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXD IOMUX_PAD(0x0570, 0x0268, 1, 0x05E8, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT3__FEC_RX_CLK IOMUX_PAD(0x0570, 0x0268, 2, 0x0700, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT3__CSI_D_5 IOMUX_PAD(0x0570, 0x0268, 3, 0x0644, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT3__UART5_TXD IOMUX_PAD(0x0570, 0x0268, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD2_DAT3__UART5_RXD IOMUX_PAD(0x0570, 0x0268, 4, 0x081C, 5, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD2_DAT3__GPIO_4_28 IOMUX_PAD(0x0570, 0x0268, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT3__MMDC_MMDC_DEBUG_37 IOMUX_PAD(0x0570, 0x0268, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT3__PL301_SIM_MX6_PER1_HBURST_0 IOMUX_PAD(0x0570, 0x0268, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD2_DAT4__USDHC2_DAT4_50MHZ IOMUX_PAD(0x0574, 0x026C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT4__USDHC2_DAT4_100MHZ IOMUX_PAD(0x0574, 0x026C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD2_DAT4__USDHC2_DAT4_200MHZ IOMUX_PAD(0x0574, 0x026C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD2_DAT4__USDHC3_DAT4 IOMUX_PAD(0x0574, 0x026C, 1, 0x083C, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT4__UART2_TXD IOMUX_PAD(0x0574, 0x026C, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD2_DAT4__UART2_RXD IOMUX_PAD(0x0574, 0x026C, 2, 0x0804, 4, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD2_DAT4__CSI_D_6 IOMUX_PAD(0x0574, 0x026C, 3, 0x0648, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT4__SPDIF_OUT1 IOMUX_PAD(0x0574, 0x026C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT4__GPIO_5_2 IOMUX_PAD(0x0574, 0x026C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT4__MMDC_MMDC_DEBUG_36 IOMUX_PAD(0x0574, 0x026C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT4__PL301_SIM_MX6_PER1_HADDR_10 IOMUX_PAD(0x0574, 0x026C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD2_DAT5__USDHC2_DAT5_50MHZ IOMUX_PAD(0x0578, 0x0270, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT5__USDHC2_DAT5_100MHZ IOMUX_PAD(0x0578, 0x0270, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD2_DAT5__USDHC2_DAT5_200MHZ IOMUX_PAD(0x0578, 0x0270, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD2_DAT5__USDHC3_DAT5 IOMUX_PAD(0x0578, 0x0270, 1, 0x0840, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT5__UART2_TXD IOMUX_PAD(0x0578, 0x0270, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD2_DAT5__UART2_RXD IOMUX_PAD(0x0578, 0x0270, 2, 0x0804, 5, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD2_DAT5__CSI_D_7 IOMUX_PAD(0x0578, 0x0270, 3, 0x064C, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT5__SPDIF_IN1 IOMUX_PAD(0x0578, 0x0270, 4, 0x07F0, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT5__GPIO_4_31 IOMUX_PAD(0x0578, 0x0270, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT5__MMDC_MMDC_DEBUG_35 IOMUX_PAD(0x0578, 0x0270, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT5__PL301_SIM_MX6_PER1_HADDR_20 IOMUX_PAD(0x0578, 0x0270, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD2_DAT6__USDHC2_DAT6_50MHZ IOMUX_PAD(0x057C, 0x0274, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT6__USDHC2_DAT6_100MHZ IOMUX_PAD(0x057C, 0x0274, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD2_DAT6__USDHC2_DAT6_200MHZ IOMUX_PAD(0x057C, 0x0274, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD2_DAT6__USDHC3_DAT6 IOMUX_PAD(0x057C, 0x0274, 1, 0x0844, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT6__UART2_CTS IOMUX_PAD(0x057C, 0x0274, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD2_DAT6__UART2_RTS IOMUX_PAD(0x057C, 0x0274, 2, 0x0800, 4, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD2_DAT6__CSI_D_8 IOMUX_PAD(0x057C, 0x0274, 3, 0x0650, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT6__USDHC2_WP IOMUX_PAD(0x057C, 0x0274, 4, 0x0834, 2, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT6__GPIO_4_29 IOMUX_PAD(0x057C, 0x0274, 5, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT6__MMDC_MMDC_DEBUG_34 IOMUX_PAD(0x057C, 0x0274, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT6__PL301_SIM_MX6_PER1_HADDR_19 IOMUX_PAD(0x057C, 0x0274, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD2_DAT7__USDHC2_DAT7_50MHZ IOMUX_PAD(0x0580, 0x0278, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT7__USDHC2_DAT7_100MHZ IOMUX_PAD(0x0580, 0x0278, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD2_DAT7__USDHC2_DAT7_200MHZ IOMUX_PAD(0x0580, 0x0278, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD2_DAT7__USDHC3_DAT7 IOMUX_PAD(0x0580, 0x0278, 1, 0x0848, 1, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT7__UART2_CTS IOMUX_PAD(0x0580, 0x0278, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD2_DAT7__UART2_RTS IOMUX_PAD(0x0580, 0x0278, 2, 0x0800, 5, MX6_UART_PAD_CTRL)
+#define MX6_PAD_SD2_DAT7__CSI_D_9 IOMUX_PAD(0x0580, 0x0278, 3, 0x0654, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT7__USDHC2_CD IOMUX_PAD(0x0580, 0x0278, 4, 0x0830, 2, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT7__GPIO_5_0 IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_DAT7__MMDC_MMDC_DEBUG_33 IOMUX_PAD(0x0580, 0x0278, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_DAT7__PL301_SIM_MX6_PER1_HADDR_16 IOMUX_PAD(0x0580, 0x0278, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD2_RST__USDHC2_RST IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD2_RST__FEC_REF_OUT IOMUX_PAD(0x0584, 0x027C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_RST__WDOG2_WDOG_B IOMUX_PAD(0x0584, 0x027C, 2, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_RST__SPDIF_OUT1 IOMUX_PAD(0x0584, 0x027C, 3, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_RST__CSI_MCLK IOMUX_PAD(0x0584, 0x027C, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_RST__GPIO_4_27 IOMUX_PAD(0x0584, 0x027C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_RST__ANATOP_ANATOP_TESTO_12 IOMUX_PAD(0x0584, 0x027C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD2_RST__PL301_SIM_MX6_PER1_HBURST_2 IOMUX_PAD(0x0584, 0x027C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_CLK__USDHC3_CLK_50MHZ IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_CLK__USDHC3_CLK_100MHZ IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD3_CLK__USDHC3_CLK_200MHZ IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD3_CLK__AUDMUX_AUD5_RXFS IOMUX_PAD(0x0588, 0x0280, 1, 0x0608, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CLK__KPP_COL_5 IOMUX_PAD(0x0588, 0x0280, 2, 0x0748, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CLK__CSI_D_10 IOMUX_PAD(0x0588, 0x0280, 3, 0x0658, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CLK__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x0588, 0x0280, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CLK__GPIO_5_18 IOMUX_PAD(0x0588, 0x0280, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CLK__USB_USBOTG1_PWR IOMUX_PAD(0x0588, 0x0280, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CLK__PL301_SIM_MX6_PER1_HADDR_13 IOMUX_PAD(0x0588, 0x0280, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_CMD__USDHC3_CMD_50MHZ IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_CMD__USDHC3_CMD_100MHZ IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD3_CMD__USDHC3_CMD_200MHZ IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD3_CMD__AUDMUX_AUD5_RXC IOMUX_PAD(0x058C, 0x0284, 1, 0x0604, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CMD__KPP_ROW_5 IOMUX_PAD(0x058C, 0x0284, 2, 0x0768, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CMD__CSI_D_11 IOMUX_PAD(0x058C, 0x0284, 3, 0x065C, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CMD__ANATOP_USBOTG2_ID IOMUX_PAD(0x058C, 0x0284, 4, 0x05E0, 3, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CMD__GPIO_5_21 IOMUX_PAD(0x058C, 0x0284, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CMD__USB_USBOTG2_PWR IOMUX_PAD(0x058C, 0x0284, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_CMD__PL301_SIM_MX6_PER1_HADDR_18 IOMUX_PAD(0x058C, 0x0284, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_DAT0__USDHC3_DAT0_100MHZ IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD3_DAT0__USDHC3_DAT0_200MHZ IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD3_DAT0__AUDMUX_AUD5_RXD IOMUX_PAD(0x0590, 0x0288, 1, 0x05FC, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT0__KPP_COL_6 IOMUX_PAD(0x0590, 0x0288, 2, 0x074C, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT0__CSI_D_12 IOMUX_PAD(0x0590, 0x0288, 3, 0x0660, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT0__ANATOP_USBOTG1_ID IOMUX_PAD(0x0590, 0x0288, 4, 0x05DC, 4, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT0__GPIO_5_19 IOMUX_PAD(0x0590, 0x0288, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT0__SJC_JTAG_ACT IOMUX_PAD(0x0590, 0x0288, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT0__PL301_SIM_MX6_PER1_HADDR_11 IOMUX_PAD(0x0590, 0x0288, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_DAT1__USDHC3_DAT1_100MHZ IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD3_DAT1__USDHC3_DAT1_200MHZ IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD3_DAT1__AUDMUX_AUD5_TXC IOMUX_PAD(0x0594, 0x028C, 1, 0x060C, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT1__KPP_ROW_6 IOMUX_PAD(0x0594, 0x028C, 2, 0x076C, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT1__CSI_D_13 IOMUX_PAD(0x0594, 0x028C, 3, 0x0664, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT1__USDHC1_VSELECT IOMUX_PAD(0x0594, 0x028C, 4, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_DAT1__GPIO_5_20 IOMUX_PAD(0x0594, 0x028C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT1__SJC_DE_B IOMUX_PAD(0x0594, 0x028C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT1__PL301_SIM_MX6_PER1_HADDR_17 IOMUX_PAD(0x0594, 0x028C, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_DAT2__USDHC3_DAT2_100MHZ IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD3_DAT2__USDHC3_DAT2_200MHZ IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD3_DAT2__AUDMUX_AUD5_TXFS IOMUX_PAD(0x0598, 0x0290, 1, 0x0610, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT2__KPP_COL_7 IOMUX_PAD(0x0598, 0x0290, 2, 0x0750, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT2__CSI_D_14 IOMUX_PAD(0x0598, 0x0290, 3, 0x0668, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT2__EPIT1_EPITO IOMUX_PAD(0x0598, 0x0290, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT2__GPIO_5_16 IOMUX_PAD(0x0598, 0x0290, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT2__USB_USBOTG2_OC IOMUX_PAD(0x0598, 0x0290, 6, 0x0820, 3, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT2__PL301_SIM_MX6_PER1_HADDR_14 IOMUX_PAD(0x0598, 0x0290, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL)
+#define MX6_PAD_SD3_DAT3__USDHC3_DAT3_100MHZ IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_100MHZ)
+#define MX6_PAD_SD3_DAT3__USDHC3_DAT3_200MHZ IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, MX6_USDHC_PAD_CTRL_200MHZ)
+#define MX6_PAD_SD3_DAT3__AUDMUX_AUD5_TXD IOMUX_PAD(0x059C, 0x0294, 1, 0x0600, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT3__KPP_ROW_7 IOMUX_PAD(0x059C, 0x0294, 2, 0x0770, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT3__CSI_D_15 IOMUX_PAD(0x059C, 0x0294, 3, 0x066C, 1, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT3__EPIT2_EPITO IOMUX_PAD(0x059C, 0x0294, 4, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT3__GPIO_5_17 IOMUX_PAD(0x059C, 0x0294, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT3__USB_USBOTG1_OC IOMUX_PAD(0x059C, 0x0294, 6, 0x0824, 2, NO_PAD_CTRL)
+#define MX6_PAD_SD3_DAT3__PL301_SIM_MX6_PER1_HADDR_12 IOMUX_PAD(0x059C, 0x0294, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_UART1_RXD__UART1_TXD IOMUX_PAD(0x05A0, 0x0298, 0, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_UART1_RXD__PWM1_PWMO IOMUX_PAD(0x05A0, 0x0298, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_UART1_RXD__UART4_TXD IOMUX_PAD(0x05A0, 0x0298, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_UART1_RXD__UART4_RXD IOMUX_PAD(0x05A0, 0x0298, 2, 0x0814, 6, NO_PAD_CTRL)
+#define MX6_PAD_UART1_RXD__FEC_COL IOMUX_PAD(0x05A0, 0x0298, 3, 0x06F0, 2, NO_PAD_CTRL)
+#define MX6_PAD_UART1_RXD__UART5_TXD IOMUX_PAD(0x05A0, 0x0298, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_UART1_RXD__UART5_RXD IOMUX_PAD(0x05A0, 0x0298, 4, 0x081C, 6, MX6_UART_PAD_CTRL)
+#define MX6_PAD_UART1_RXD__GPIO_3_16 IOMUX_PAD(0x05A0, 0x0298, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_UART1_RXD__ANATOP_ANATOP_TESTI_2 IOMUX_PAD(0x05A0, 0x0298, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_UART1_RXD__TPSMP_CLK IOMUX_PAD(0x05A0, 0x0298, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#define MX6_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_UART1_TXD__UART1_RXD IOMUX_PAD(0x05A4, 0x029C, 0, 0x07FC, 1, MX6_UART_PAD_CTRL)
+#define MX6_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x05A4, 0x029C, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_UART1_TXD__UART4_TXD IOMUX_PAD(0x05A4, 0x029C, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_UART1_TXD__UART4_RXD IOMUX_PAD(0x05A4, 0x029C, 2, 0x0814, 7, MX6_UART_PAD_CTRL)
+#define MX6_PAD_UART1_TXD__FEC_RX_CLK IOMUX_PAD(0x05A4, 0x029C, 3, 0x0700, 2, NO_PAD_CTRL)
+#define MX6_PAD_UART1_TXD__UART5_TXD IOMUX_PAD(0x05A4, 0x029C, 4, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_UART1_TXD__UART5_RXD IOMUX_PAD(0x05A4, 0x029C, 4, 0x081C, 7, MX6_UART_PAD_CTRL)
+#define MX6_PAD_UART1_TXD__GPIO_3_17 IOMUX_PAD(0x05A4, 0x029C, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_UART1_TXD__ANATOP_ANATOP_TESTI_3 IOMUX_PAD(0x05A4, 0x029C, 6, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_UART1_TXD__UART5_DCD IOMUX_PAD(0x05A4, 0x029C, 7, 0x0000, 0, MX6_UART_PAD_CTRL)
+
+#define MX6_PAD_WDOG_B__WDOG1_WDOG_B IOMUX_PAD(0x05A8, 0x02A0, 0, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_WDOG_B__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x05A8, 0x02A0, 1, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_WDOG_B__UART5_RI IOMUX_PAD(0x05A8, 0x02A0, 2, 0x0000, 0, MX6_UART_PAD_CTRL)
+#define MX6_PAD_WDOG_B__GPIO_3_18 IOMUX_PAD(0x05A8, 0x02A0, 5, 0x0000, 0, NO_PAD_CTRL)
+#define MX6_PAD_WDOG_B__OBSERVE_MUX_OUT_2 IOMUX_PAD(0x05A8, 0x02A0, 7, 0x0000, 0, NO_PAD_CTRL)
+
+#endif /* __ASM_ARCH_IOMUX_MX6SL_H__*/
+++ /dev/null
-/*
- * Based on Linux i.MX iomux-v3.h file:
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- * <armlinux@phytec.de>
- *
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_IOMUX_V3_H__
-#define __MACH_IOMUX_V3_H__
-
-/*
- * build IOMUX_PAD structure
- *
- * This iomux scheme is based around pads, which are the physical balls
- * on the processor.
- *
- * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
- * things like driving strength and pullup/pulldown.
- * - Each pad can have but not necessarily does have an output routing register
- * (IOMUXC_SW_MUX_CTL_PAD_x).
- * - Each pad can have but not necessarily does have an input routing register
- * (IOMUXC_x_SELECT_INPUT)
- *
- * The three register sets do not have a fixed offset to each other,
- * hence we order this table by pad control registers (which all pads
- * have) and put the optional i/o routing registers into additional
- * fields.
- *
- * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
- *
- * IOMUX/PAD Bit field definitions
- *
- * MUX_CTRL_OFS: 0..11 (12)
- * PAD_CTRL_OFS: 12..23 (12)
- * SEL_INPUT_OFS: 24..35 (12)
- * MUX_MODE + SION: 36..40 (5)
- * PAD_CTRL + PAD_CTRL_VALID: 41..58 (18)
- * SEL_INP: 59..61 (3)
- * reserved: 62..63 (2)
-*/
-
-typedef u64 iomux_v3_cfg_t;
-
-#define MUX_CTRL_OFS_SHIFT 0
-#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
-#define MUX_PAD_CTRL_OFS_SHIFT 12
-#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
- MUX_PAD_CTRL_OFS_SHIFT)
-#define MUX_SEL_INPUT_OFS_SHIFT 24
-#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
- MUX_SEL_INPUT_OFS_SHIFT)
-
-#define MUX_MODE_SHIFT 36
-#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
-#define MUX_PAD_CTRL_SHIFT 41
-#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT)
-#define MUX_SEL_INPUT_SHIFT 59
-#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0x7 << MUX_SEL_INPUT_SHIFT)
-
-#define MUX_PAD_CTRL(x) (((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) | \
- PAD_CTRL_VALID)
-
-#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
- sel_input, pad_ctrl) \
- (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
- ((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
- ((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
- ((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
- ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
- ((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
-
-#define NO_MUX_I 0
-#define NO_PAD_I 0
-
-#define PAD_CTRL_VALID ((iomux_v3_cfg_t)1 << (MUX_PAD_CTRL_SHIFT + 17))
-
-#define GPIO_PIN_MASK 0xf
-#define GPIO_PORT_SHIFT 5
-#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
-#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
-#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
-#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
-#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
-#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
-#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
-
-#define IOMUX_CONFIG_SION (0x1 << 4)
-
-int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
-int imx_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list, unsigned count);
-
-/*
- * IOMUXC_GPR13 bit fields
- */
-#define IOMUXC_GPR13_SDMA_STOP_REQ (1 << 30)
-#define IOMUXC_GPR13_CAN2_STOP_REQ (1 << 29)
-#define IOMUXC_GPR13_CAN1_STOP_REQ (1 << 28)
-#define IOMUXC_GPR13_ENET_STOP_REQ (1 << 27)
-#define IOMUXC_GPR13_SATA_PHY_8_MASK (7 << 24)
-#define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f << 19)
-#define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16
-#define IOMUXC_GPR13_SATA_PHY_6_MASK (7 << IOMUXC_GPR13_SATA_PHY_6_SHIFT)
-#define IOMUXC_GPR13_SATA_SPEED_MASK (1 << 15)
-#define IOMUXC_GPR13_SATA_PHY_5_MASK (1 << 14)
-#define IOMUXC_GPR13_SATA_PHY_4_MASK (7 << 11)
-#define IOMUXC_GPR13_SATA_PHY_3_MASK (0x1f << 7)
-#define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f << 2)
-#define IOMUXC_GPR13_SATA_PHY_1_MASK (3 << 0)
-
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0b000 << 24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (0b001 << 24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (0b010 << 24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (0b011 << 24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (0b100 << 24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (0b101 << 24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (0b110 << 24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (0b111 << 24)
-
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000 << 19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000 << 19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010 << 19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010 << 19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010 << 19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010 << 19)
-
-#define IOMUXC_GPR13_SATA_SPEED_1P5G (0 << 15)
-#define IOMUXC_GPR13_SATA_SPEED_3G (1 << 15)
-
-#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED (0 << 14)
-#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED (1 << 14)
-
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16 (0 << 11)
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16 (1 << 11)
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 (2 << 11)
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16 (3 << 11)
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4 << 11)
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5 << 11)
-
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0b0000 << 7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (0b0001 << 7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (0b0010 << 7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (0b0011 << 7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (0b0100 << 7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (0b0101 << 7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (0b0110 << 7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (0b0111 << 7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (0b1000 << 7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (0b1001 << 7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0b1010 << 7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0b1011 << 7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0b1100 << 7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0b1101 << 7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0b1110 << 7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0b1111 << 7)
-
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0b00000 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (0b00001 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (0b00010 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (0b00011 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (0b00100 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (0b00101 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (0b00110 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (0b00111 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (0b01000 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (0b01001 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0b01010 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0b01011 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0b01100 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0b01101 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0b01110 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0b01111 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0b10000 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0b10001 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0b10010 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0b10011 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0b10100 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0b10101 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0b10110 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0b10111 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0b11000 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0b11001 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0b11010 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0b11011 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0b11100 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0b11101 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0b11110 << 2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0b11111 << 2)
-
-#define IOMUXC_GPR13_SATA_PHY_1_FAST 0
-#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1
-#define IOMUXC_GPR13_SATA_PHY_1_SLOW 2
-
-#define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \
- |IOMUXC_GPR13_SATA_PHY_7_MASK \
- |IOMUXC_GPR13_SATA_PHY_6_MASK \
- |IOMUXC_GPR13_SATA_SPEED_MASK \
- |IOMUXC_GPR13_SATA_PHY_5_MASK \
- |IOMUXC_GPR13_SATA_PHY_4_MASK \
- |IOMUXC_GPR13_SATA_PHY_3_MASK \
- |IOMUXC_GPR13_SATA_PHY_2_MASK \
- |IOMUXC_GPR13_SATA_PHY_1_MASK)
-
-#endif /* __MACH_IOMUX_V3_H__*/
+++ /dev/null
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- */
-
-#ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__
-#define __ASM_ARCH_MX6_MX6DL_PINS_H__
-
-#include <asm/imx-common/iomux-v3.h>
-
-/* Use to set PAD control */
-#define PAD_CTL_HYS (1 << 16)
-#define PAD_CTL_PUS_100K_DOWN (0 << 14)
-#define PAD_CTL_PUS_47K_UP (1 << 14)
-#define PAD_CTL_PUS_100K_UP (2 << 14)
-#define PAD_CTL_PUS_22K_UP (3 << 14)
-
-#define PAD_CTL_PUE (1 << 13)
-#define PAD_CTL_PKE (1 << 12)
-#define PAD_CTL_ODE (1 << 11)
-#define PAD_CTL_SPEED_LOW (1 << 6)
-#define PAD_CTL_SPEED_MED (2 << 6)
-#define PAD_CTL_SPEED_HIGH (3 << 6)
-#define PAD_CTL_DSE_DISABLE (0 << 3)
-#define PAD_CTL_DSE_240ohm (1 << 3)
-#define PAD_CTL_DSE_120ohm (2 << 3)
-#define PAD_CTL_DSE_80ohm (3 << 3)
-#define PAD_CTL_DSE_60ohm (4 << 3)
-#define PAD_CTL_DSE_48ohm (5 << 3)
-#define PAD_CTL_DSE_40ohm (6 << 3)
-#define PAD_CTL_DSE_34ohm (7 << 3)
-#define PAD_CTL_SRE_FAST (1 << 0)
-#define PAD_CTL_SRE_SLOW (0 << 0)
-
-#define IOMUX_CONFIG_SION 0x10
-#define NO_MUX_I 0
-#define NO_PAD_I 0
-enum {
- MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
- MX6DL_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
- MX6DL_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
- MX6DL_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
- MX6DL_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
- MX6DL_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
- MX6DL_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
- MX6DL_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
- MX6DL_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
- MX6DL_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
- MX6DL_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
- MX6DL_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
- MX6DL_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
- MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
- MX6DL_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
- MX6DL_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
- MX6DL_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
- MX6DL_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
- MX6DL_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
- MX6DL_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
- MX6DL_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
- MX6DL_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
- MX6DL_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
- MX6DL_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
- MX6DL_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
- MX6DL_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
- MX6DL_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
- MX6DL_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
- MX6DL_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
- MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
- MX6DL_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
- MX6DL_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
- MX6DL_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
- MX6DL_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
- MX6DL_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
- MX6DL_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
- MX6DL_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
- MX6DL_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
- MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
- MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
- MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
- MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
-};
-#endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */
*
* IOMUX/PAD Bit field definitions
*
- * MUX_CTRL_OFS: 0..11 (12)
- * PAD_CTRL_OFS: 12..23 (12)
- * SEL_INPUT_OFS: 24..35 (12)
- * MUX_MODE + SION: 36..40 (5)
+ * MUX_CTRL_OFS: 0..11 (12)
+ * PAD_CTRL_OFS: 12..23 (12)
+ * SEL_INPUT_OFS: 24..35 (12)
+ * MUX_MODE + SION: 36..40 (5)
* PAD_CTRL + PAD_CTRL_VALID: 41..58 (18)
- * SEL_INP: 59..62 (4)
- * reserved: 63 (1)
+ * SEL_INP: 59..61 (3)
+ * reserved: 62..63 (2)
*/
typedef u64 iomux_v3_cfg_t;
#define MUX_MODE_SHIFT 36
#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
#define MUX_PAD_CTRL_SHIFT 41
-#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
+#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT)
#define MUX_SEL_INPUT_SHIFT 59
-#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
+#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0x7 << MUX_SEL_INPUT_SHIFT)
-#define MUX_PAD_CTRL(x) (((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) | \
- PAD_CTRL_VALID)
+#define __MUX_PAD_CTRL(x) ((x) | __PAD_CTRL_VALID)
+#define MUX_PAD_CTRL(x) (((iomux_v3_cfg_t)__MUX_PAD_CTRL(x) << \
+ MUX_PAD_CTRL_SHIFT))
#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
sel_input, pad_ctrl) \
((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
-#define NO_PAD_CTRL (1 << 17)
+#define NO_MUX_I 0
+#define NO_PAD_I 0
+
+#define NO_PAD_CTRL 0
+#define __PAD_CTRL_VALID (1 << 17)
+#define PAD_CTRL_VALID ((iomux_v3_cfg_t)__PAD_CTRL_VALID << MUX_PAD_CTRL_SHIFT)
#define GPIO_PIN_MASK 0x1f
-#define PAD_CTRL_VALID ((iomux_v3_cfg_t)1 << (MUX_PAD_CTRL_SHIFT + 17))
#define GPIO_PORT_SHIFT 5
#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
#define MUX_CONFIG_SION (0x1 << 4)
-int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
-int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+int imx_iomux_v3_setup_pad(const iomux_v3_cfg_t pad);
+int imx_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,
unsigned count);
#endif /* __ASM_ARCH_IOMUX_V3_H__*/
}
iomux_v3_cfg_t const uart4_pads[] = {
- MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_CS0__GPIO_6_11, /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads[] = {
- MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
}
iomux_v3_cfg_t const uart4_pads[] = {
- MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads[] = {
- MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_enet(void)
}
iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_CS2__GPIO_6_15,
};
static void setup_iomux_uart(void)
}
iomux_v3_cfg_t const uart1_pads[] = {
- MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart2_pads[] = {
- MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1, SGTL5000 */
struct i2c_pads_info i2c_pad_info0 = {
.scl = {
- .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6Q_PAD_EIM_D21__GPIO_3_21 | PC,
+ .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
- .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6Q_PAD_EIM_D28__GPIO_3_28 | PC,
+ .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
.gp = IMX_GPIO_NR(3, 28)
}
};
/* I2C2 Camera, MIPI */
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
- .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO_4_12 | PC,
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
- .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO_4_13 | PC,
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
/* I2C3, J15 - RGB connector */
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
- .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL | PC,
- .gpio_mode = MX6Q_PAD_GPIO_5__GPIO_1_5 | PC,
+ .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
.gp = IMX_GPIO_NR(1, 5)
},
.sda = {
- .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA | PC,
- .gpio_mode = MX6Q_PAD_GPIO_16__GPIO_7_11 | PC,
+ .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
.gp = IMX_GPIO_NR(7, 11)
}
};
iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__GPIO_7_0, /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D6__GPIO_2_6, /* CD */
};
iomux_v3_cfg_t const enet_pads1[] = {
- MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* pin 35 - 1 (PHY_AD2) on reset */
- MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__GPIO_6_30,
/* pin 32 - 1 - (MODE0) all */
- MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__GPIO_6_25,
/* pin 31 - 1 - (MODE1) all */
- MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__GPIO_6_27,
/* pin 28 - 1 - (MODE2) all */
- MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__GPIO_6_28,
/* pin 27 - 1 - (MODE3) all */
- MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__GPIO_6_29,
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
- MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__GPIO_6_24,
/* pin 42 PHY nRST */
- MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D23__GPIO_3_23,
};
iomux_v3_cfg_t const enet_pads2[] = {
- MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
/* Button assignments for J14 */
static iomux_v3_cfg_t const button_pads[] = {
/* Menu */
- MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Back */
- MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Labelled Search (mapped to Power under Android) */
- MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Home */
- MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Volume Down */
- MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Volume Up */
- MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
};
static void setup_iomux_enet(void)
}
iomux_v3_cfg_t const usb_pads[] = {
- MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO_17__GPIO_7_12,
};
static void setup_iomux_uart(void)
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
- MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
};
void setup_spi(void)
static iomux_v3_cfg_t const backlight_pads[] = {
/* Backlight on RGB connector: J15 */
- MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__GPIO_1_21,
#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
/* Backlight on LVDS connector: J6 */
- MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD1_CMD__GPIO_1_18,
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
};
static iomux_v3_cfg_t const rgb_pads[] = {
- MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
- MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,
- MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,
- MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,
- MX6Q_PAD_DI0_PIN4__GPIO_4_20,
- MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
- MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
- MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
- MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
- MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
- MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
- MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
- MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
- MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
- MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
- MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
- MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
- MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
- MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
- MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
- MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
- MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
- MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
- MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
- MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
- MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
- MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
- MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
- MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
+ MX6_PAD_DI0_PIN4__GPIO_4_20,
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
};
struct display_info_t {
}
iomux_v3_cfg_t const uart1_pads[] = {
- MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads[] = {
- MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* AR8031 PHY Reset */
- MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_ENET_CRS_DV__GPIO_1_25,
};
static void setup_iomux_enet(void)
}
iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D2__GPIO_2_2, /* CD */
};
iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D0__GPIO_2_0, /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static void setup_iomux_uart(void)
static const char *karo_touchpanels[] = {
"ti,tsc2007",
"edt,edt-ft5x06",
+#ifdef CONFIG_MX28
"fsl,imx28-lradc",
+#endif
};
static void fdt_del_tp_node(void *blob, const char *name)
off = fdt_path_offset(blob, node);
if (off < 0) {
- printf("Failed to find node %s\n", node);
+ debug("Failed to find node %s\n", node);
return;
}
if (off < 0)
return off;
do {
- const char *n;
- int d = 1;
+ const char *n, *endp;
+ int len, d = 1;
off = fdt_next_node(blob, off, &d);
if (d > 2) {
if (off < 0 || d < 1)
break;
- n = fdt_getprop(blob, off, "panel-name", NULL);
+ n = fdt_getprop(blob, off, "panel-name", &len);
if (!n) {
printf("Missing 'panel-name' property in node '%s'\n",
fdt_get_name(blob, off, NULL));
continue;
}
- debug("Checking panel-name '%s'\n", n);
- if (strcasecmp(n, name) == 0) {
- fdt_init_fb_mode(blob, off, fb_mode);
- return fdt_update_native_fb_mode(blob, off);
-
+ for (endp = n + len; n < endp; n += strlen(n) + 1) {
+ debug("Checking panel-name '%s'\n", n);
+ if (strcasecmp(n, name) == 0) {
+ fdt_init_fb_mode(blob, off, fb_mode);
+ return fdt_update_native_fb_mode(blob, off);
+ }
}
} while (off > 0);
return -EINVAL;
* GNU General Public License for more details.
*
*/
+struct fb_videomode;
#ifdef CONFIG_OF_LIBFDT
void karo_fdt_remove_node(void *blob, const char *node);
static inline int karo_fdt_get_fb_mode(void *blob, const char *name,
struct fb_videomode *fb_mode)
{
- return NULL;
+ return 0;
}
static inline int karo_fdt_update_fb_mode(void *blob, const char *name)
{
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "Ka-Ro TX6Q module";
+ compatible = "karo,imx6q-tx6q", "fsl,imx6q";
+
+ memory {
+ reg = <0 0>; /* filled in by U-Boot */
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_3 &pinctrl_uart1_4>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_5 &pinctrl_uart2_6>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_4>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet_1>;
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1_2>;
+ cd-gpios = <&gpio7 2 0>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_2>;
+ cd-gpios = <&gpio7 3 0>;
+ status = "okay";
+};
LIB = $(obj)lib$(BOARD).o
-COBJS := tx6q.o
+COBJS := tx6qdl.o
SOBJS := lowlevel_init.o
-ifeq ($(CONFIG_SPL_BUILD),y)
- COBJS += spl_boot.o
-else
ifeq ($(CONFIG_CMD_ROMUPDATE),y)
COBJS += flash.o
endif
-endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
LOGO_BMP = logos/karo.bmp
#PLATFORM_CPPFLAGS += -DDEBUG
-PLATFORM_CPPFLAGS += -Wno-unused-but-set-variable
-
+#PLATFORM_CPPFLAGS += -Wno-unused-but-set-variable
PLATFORM_CPPFLAGS += -Werror
-#ifneq ($(CONFIG_SPL_BUILD),y)
-# ALL-y += $(obj)u-boot.sb
-#endif
--- /dev/null
+#include <config.h>
+#include <configs/tx6.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+
+#ifndef CCM_CCR
+#error asm-offsets not included
+#endif
+
+#define DEBUG_LED_BIT 20
+#define LED_GPIO_BASE GPIO2_BASE_ADDR
+#define LED_MUX_OFFSET 0x0ec
+#define LED_MUX_MODE 0x15
+
+#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
+
+#ifdef PHYS_SDRAM_2_SIZE
+#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#else
+#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
+#endif
+
+#define CPU_2_BE_32(l) \
+ ((((l) << 24) & 0xFF000000) | \
+ (((l) << 8) & 0x00FF0000) | \
+ (((l) >> 8) & 0x0000FF00) | \
+ (((l) >> 24) & 0x000000FF))
+
+#define CHECK_DCD_ADDR(a) ( \
+ ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \
+ ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \
+ ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \
+ ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \
+ ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
+ ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \
+ ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
+
+ .macro mxc_dcd_item addr, val
+ .ifne CHECK_DCD_ADDR(\addr)
+ .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
+ .else
+ .error "Address \addr not accessible from DCD"
+ .endif
+ .endm
+
+#define MXC_DCD_ITEM(addr, val) mxc_dcd_item addr, val
+
+#define MXC_DCD_CMD_SZ_BYTE 1
+#define MXC_DCD_CMD_SZ_SHORT 2
+#define MXC_DCD_CMD_SZ_WORD 4
+#define MXC_DCD_CMD_FLAG_WRITE 0x0
+#define MXC_DCD_CMD_FLAG_CLR 0x1
+#define MXC_DCD_CMD_FLAG_SET 0x3
+#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
+#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
+#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
+
+#define MXC_DCD_CMD_WRT(type, flags, next) \
+ .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
+
+#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
+ .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
+ CPU_2_BE_32(addr), CPU_2_BE_32(mask)
+
+#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
+ .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
+ CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
+
+#define MXC_DCD_CMD_NOP \
+ .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+
+#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
+#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+
+ .macro CK_VAL, name, clks, offs, max
+ .iflt \clks - \offs
+ .set \name, 0
+ .else
+ .ifle \clks - \offs - \max
+ .set \name, \clks - \offs
+ .else
+ .error "Value \clks out of range for parameter \name"
+ .endif
+ .endif
+ .endm
+
+ .macro NS_VAL, name, ns, offs, max
+ .iflt \ns - \offs
+ .set \name, 0
+ .else
+ CK_VAL \name, NS_TO_CK(\ns), \offs, \max
+ .endif
+ .endm
+
+ .macro CK_MAX, name, ck1, ck2, offs, max
+ .ifgt \ck1 - \ck2
+ CK_VAL \name, \ck1, \offs, \max
+ .else
+ CK_VAL \name, \ck2, \offs, \max
+ .endif
+ .endm
+
+#define MDMISC_DDR_TYPE_DDR3 0
+#define MDMISC_DDR_TYPE_LPDDR2 1
+#define MDMISC_DDR_TYPE_DDR2 2
+
+#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
+
+#define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */
+
+/* DDR3 SDRAM */
+#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
+#define BANK_ADDR_BITS 2
+#else
+#define BANK_ADDR_BITS 1
+#endif
+#define SDRAM_BURST_LENGTH 8
+#define RALAT 5
+#define WALAT 0
+#define BI_ON 1
+#define ADDR_MIRROR 1
+#define DDR_TYPE MDMISC_DDR_TYPE_DDR3
+
+/* 512/1024MiB SDRAM: NT5CB128M16P-CG */
+/* MDCFG0 0x0c */
+NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
+CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
+CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
+CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
+NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */
+
+/* MDCFG1 0x10 */
+NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
+NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
+NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */
+
+/* MDCFG2 0x14 */
+CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
+CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+
+/* MDOR 0x30 */
+CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
+#define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
+#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
+
+/* MDOTC 0x08 */
+NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */
+
+/* MDPDC 0x04 */
+CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7
+CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
+CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
+
+#define PRCT 0
+#define PWDT 5
+#define SLOW_PD 0
+#define BOTH_CS_PD 1
+
+#define MDPDC_VAL_0 ( \
+ (PRCT << 28) | \
+ (PRCT << 24) | \
+ (tCKE << 16) | \
+ (SLOW_PD << 7) | \
+ (BOTH_CS_PD << 6) | \
+ (tCKSRX << 3) | \
+ (tCKSRE << 0) \
+ )
+
+#define MDPDC_VAL_1 (MDPDC_VAL_0 | \
+ (PWDT << 12) | \
+ (PWDT << 8) \
+ )
+
+#define ROW_ADDR_BITS 14
+#define COL_ADDR_BITS 10
+
+ .iflt tWR - 7
+ .set mr0_val, ((1 << 8) /* DLL Reset */ | \
+ ((tWR + 1 - 4) << 9) | \
+ (((tCL + 3) - 4) << 4))
+ .else
+ .set mr0_val, ((1 << 8) /* DLL Reset */ | \
+ (((tWR + 1) / 2) << 9) | \
+ (((tCL + 3) - 4) << 4))
+ .endif
+
+#define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
+ (1 << 15) /* CON REQ */ | \
+ (3 << 4) /* MRS command */ | \
+ ((cs) << 3) | \
+ ((mr) << 0))
+
+#define mr1_val 0x0040
+#define mr2_val 0x0408
+
+#define MDCFG0_VAL ( \
+ (tRFC << 24) | \
+ (tXS << 16) | \
+ (tXP << 13) | \
+ (tXPDLL << 9) | \
+ (tFAW << 4) | \
+ (tCL << 0)) \
+
+#define MDCFG1_VAL ( \
+ (tRCD << 29) | \
+ (tRP << 26) | \
+ (tRC << 21) | \
+ (tRAS << 16) | \
+ (tRPA << 15) | \
+ (tWR << 9) | \
+ (tMRD << 5) | \
+ (tCWL << 0)) \
+
+#define MDCFG2_VAL ( \
+ (tDLLK << 16) | \
+ (tRTP << 6) | \
+ (tWTR << 3) | \
+ (tRRD << 0))
+
+#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
+
+#if PHYS_SDRAM_1_WIDTH == 64
+#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
+ ((COL_ADDR_BITS - 9) << 20) | \
+ (BURST_LEN << 19) | \
+ (2 << 16) | /* SDRAM bus width */ \
+ ((-1) << (32 - BANK_ADDR_BITS)))
+#else
+#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
+ ((COL_ADDR_BITS - 9) << 20) | \
+ (BURST_LEN << 19) | \
+ (1 << 16) | /* SDRAM bus width */ \
+ ((-1) << (32 - BANK_ADDR_BITS)))
+#endif
+
+#define MDMISC_VAL ((ADDR_MIRROR << 19) | \
+ (WALAT << 16) | \
+ (BI_ON << 12) | \
+ (0x3 << 9) | \
+ (RALAT << 6) | \
+ (DDR_TYPE << 3))
+
+#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
+
+#define MDOTC_VAL ((tAOFPD << 27) | \
+ (tAONPD << 24) | \
+ (tANPD << 20) | \
+ (tAXPD << 16) | \
+ (tODTLon << 12) | \
+ (tODTLoff << 4))
+
+fcb_start:
+ b _start
+ .org 0x400
+ivt_header:
+ .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
+app_start_addr:
+ .long _start
+ .long 0x0
+dcd_ptr:
+ .long dcd_hdr
+boot_data_ptr:
+ .word boot_data
+self_ptr:
+ .word ivt_header
+app_code_csf:
+ .word 0x0
+ .word 0x0
+boot_data:
+ .long fcb_start
+image_len:
+ .long CONFIG_U_BOOT_IMG_SIZE
+plugin:
+ .word 0
+ivt_end:
+#define DCD_VERSION 0x40
+
+#define CLKCTL_CCGR0 0x68
+#define CLKCTL_CCGR1 0x6c
+#define CLKCTL_CCGR2 0x70
+#define CLKCTL_CCGR3 0x74
+#define CLKCTL_CCGR4 0x78
+#define CLKCTL_CCGR5 0x7c
+#define CLKCTL_CCGR6 0x80
+#define CLKCTL_CCGR7 0x84
+#define CLKCTL_CMEOR 0x88
+
+#define DDR_SEL_VAL 3
+#define DSE_VAL 6
+#define ODT_VAL 2
+
+#define DDR_SEL_SHIFT 18
+#define DDR_MODE_SHIFT 17
+#define ODT_SHIFT 8
+#define DSE_SHIFT 3
+#define HYS_SHIFT 16
+#define PKE_SHIFT 12
+#define PUE_SHIFT 13
+#define PUS_SHIFT 14
+
+#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
+#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT)
+#define DSE_MASK (DSE_VAL << DSE_SHIFT)
+#define ODT_MASK (ODT_VAL << ODT_SHIFT)
+
+#define DQM_MASK (DDR_MODE_MASK | DSE_MASK)
+#define SDQS_MASK DSE_MASK
+#define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK)
+#define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define DDR_ADDR_MASK 0
+#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK)
+
+#define MMDC1_MDCTL 0x021b0000
+#define MMDC1_MDPDC 0x021b0004
+#define MMDC1_MDOTC 0x021b0008
+#define MMDC1_MDCFG0 0x021b000c
+#define MMDC1_MDCFG1 0x021b0010
+#define MMDC1_MDCFG2 0x021b0014
+#define MMDC1_MDMISC 0x021b0018
+#define MMDC1_MDSCR 0x021b001c
+#define MMDC1_MDREF 0x021b0020
+#define MMDC1_MDRWD 0x021b002c
+#define MMDC1_MDOR 0x021b0030
+#define MMDC1_MDASP 0x021b0040
+#define MMDC1_MAPSR 0x021b0404
+#define MMDC1_MPZQHWCTRL 0x021b0800
+#define MMDC1_MPWLGCR 0x021b0808
+#define MMDC1_MPODTCTRL 0x021b0818
+#define MMDC1_MPRDDQBY0DL 0x021b081c
+#define MMDC1_MPRDDQBY1DL 0x021b0820
+#define MMDC1_MPRDDQBY2DL 0x021b0824
+#define MMDC1_MPRDDQBY3DL 0x021b0828
+#define MMDC1_MPDGCTRL0 0x021b083c
+#define MMDC1_MPRDDLCTL 0x021b0848
+#define MMDC1_MPWRDLCTL 0x021b0850
+#define MMDC1_MPRDDLHWCTL 0x021b0860
+#define MMDC1_MPWRDLHWCTL 0x021b0864
+#define MMDC1_MPPDCMPR2 0x021b0890
+#define MMDC1_MPMUR0 0x021b08b8
+#define MMDC2_MPZQHWCTRL 0x021b4800
+#define MMDC2_MPWLGCR 0x021b4808
+#define MMDC2_MPODTCTRL 0x021b4818
+#define MMDC2_MPRDDQBY0DL 0x021b481c
+#define MMDC2_MPRDDQBY1DL 0x021b4820
+#define MMDC2_MPRDDQBY2DL 0x021b4824
+#define MMDC2_MPRDDQBY3DL 0x021b4828
+#define MMDC2_MPDGCTRL0 0x021b483c
+#define MMDC2_MPRDDLCTL 0x021b4848
+#define MMDC2_MPWRDLCTL 0x021b4850
+#define MMDC2_MPRDDLHWCTL 0x021b4860
+#define MMDC2_MPWRDLHWCTL 0x021b4864
+#define MMDC2_MPMUR0 0x021b48b8
+
+#ifdef CONFIG_MX6Q
+#define IOMUXC_GPR1 0x020e0004
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e024c
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e02a8
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x020e02ac
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x020e02c0
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x020e02c4
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e02d4
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e02d8
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e02dc
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY 0x020e02e0
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x020e02e4
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x020e02ec
+#define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x020e02f4
+#define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x020e02f8
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x020e02fc
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x020e0300
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x020e0304
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x020e0308
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x020e030c
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0310
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e0314
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e0318
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x020e050c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x020e0510
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x020e0514
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P 0x020e0518
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x020e051c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x020e0520
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x020e0524
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x020e0528
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x020e052c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x020e0530
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x020e0534
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x020e0538
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x020e053c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x020e0540
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x020e0544
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x020e0548
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x020e054c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x020e0550
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x020e0554
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x020e0558
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x020e055c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x020e0560
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x020e0564
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x020e0568
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x020e056c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x020e0578
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x020e057c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x020e0580
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x020e0584
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x020e0588
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x020e058c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x020e0590
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P 0x020e0594
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x020e0598
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x020e059c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x020e05a0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x020e05a8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x020e05ac
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x020e05b0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x020e05b4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P 0x020e05b8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020e05bc
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x020e05c0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020e05c4
+#define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020e0748
+#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c
+#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750
+#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0 0x020e0754
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e0758
+#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1 0x020e075c
+#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2 0x020e0760
+#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3 0x020e0764
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0768
+#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4 0x020e076c
+#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e0770
+#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e0774
+#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5 0x020e0778
+#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6 0x020e077c
+#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7 0x020e0780
+#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0784
+#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x020e0788
+#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x020e078c
+#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x020e0794
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x020e0798
+#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x020e079c
+#define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x020e07a0
+#define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x020e07a4
+#define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x020e07a8
+#define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e091c
+#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920
+#endif
+
+#ifdef CONFIG_MX6DL
+#define IOMUXC_GPR1 0x020e0004
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e0218
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e0330
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x020e032c
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x020e0314
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x020e0318
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e0270
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e026c
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e02a8
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY 0x020e02a4
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x020e0274
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x020e027c
+#define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x020e033c
+#define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x020e0338
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x020e0284
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x020e0288
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x020e028c
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x020e0290
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x020e0294
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0298
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e029c
+#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e02a0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x020e04d0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x020e0484
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x020e0480
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P 0x020e04cc
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x020e04c8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x020e047c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x020e04c4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x020e0478
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x020e0424
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x020e0428
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x020e0444
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x020e0448
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x020e044c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x020e0450
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x020e0454
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x020e0458
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x020e045c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x020e0460
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x020e042c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x020e0430
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x020e0434
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x020e0438
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x020e043c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x020e0440
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x020e0464
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x020e0490
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x020e0494
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x020e0498
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x020e049c
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x020e04ac
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x020e04a0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x020e04a4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P 0x020e04b0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x020e04a8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x020e04b4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x020e04b8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x020e04bc
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x020e0470
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x020e04c0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x020e0474
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P 0x020e04d4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020e0488
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x020e04d8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020e048c
+#define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020e0748
+#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c
+#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e0754
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0754
+#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e075c
+#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e0760
+#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0784
+#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x020e0788
+#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x020e078c
+#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x020e0794
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x020e0798
+#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x020e079c
+#define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x020e07a0
+#define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x020e07a4
+#define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x020e07a8
+#define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e091c
+#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920
+#endif
+
+dcd_hdr:
+ .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
+dcd_start:
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset)
+ /* RESET_OUT GPIO_7_12 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
+
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* CS2CDR default: 0x007236c1 */
+
+ MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
+
+ /* enable all relevant clocks... */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
+
+ /* IOMUX: */
+ MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */
+ /* UART1 pad config */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7, 0x00000001) /* UART1 TXD */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6, 0x00000001) /* UART1 RXD */
+ MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003) /* UART1 RXD INPUT_SEL */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0, 0x00000001) /* UART1 CTS */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1, 0x00000001) /* UART1 RTS */
+ MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT, 0x00000003) /* UART1 RTS INPUT_SEL */
+
+ /* NAND */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE, 0x00000000) /* NANDF_CLE: NANDF_CLE */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE, 0x00000000) /* NANDF_ALE: NANDF_ALE */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CMD, 0x00000001) /* SD4_CMD: NANDF_RDn */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CLK, 0x00000001) /* SD4_CLK: NANDF_WRn */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000) /* NANDF_D0: NANDF_D0 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000) /* NANDF_D1: NANDF_D1 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000) /* NANDF_D2: NANDF_D2 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000) /* NANDF_D3: NANDF_D3 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000) /* NANDF_D4: NANDF_D4 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000) /* NANDF_D5: NANDF_D5 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000) /* NANDF_D6: NANDF_D6 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000) /* NANDF_D7: NANDF_D7 */
+
+ /* ext. mem CS */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000) /* NANDF_CS2: NANDF_CS2 */
+ /* DRAM_DQM[0..7] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, DQM_MASK)
+#endif
+
+ /* DRAM_A[0..15] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, DDR_ADDR_MASK)
+ /* DRAM_CAS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK)
+ /* DRAM_RAS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK)
+ /* DRAM_SDCLK[0..1] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, SDCLK_MASK)
+ /* DRAM_RESET */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK)
+ /* DRAM_SDCKE[0..1] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK)
+ /* DRAM_SDBA[0..2] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000)
+ /* DRAM_SDODT[0..1] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
+ /* DRAM_B[0..7]DS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE_MASK)
+#endif
+ /* ADDDS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE_MASK)
+ /* DDRMODE_CTL */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
+ /* DDRPKE */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, 0x00000000)
+ /* DDRMODE */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
+ /* CTLDS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE_MASK)
+ /* DDR_TYPE */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
+ /* DDRPK */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT)
+ /* DDRHYS */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
+
+#ifdef CONFIG_MX6Q
+ /* TERM_CTL[0..7] */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2, ODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3, ODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4, ODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, ODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
+#endif
+
+ /* SDRAM initialization */
+ /* MPRDDQBY[0..7]DL */
+ MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
+ MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
+ MXC_DCD_ITEM(MMDC1_MPRDDQBY2DL, 0x33333333)
+ MXC_DCD_ITEM(MMDC1_MPRDDQBY3DL, 0x33333333)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(MMDC2_MPRDDQBY0DL, 0x33333333)
+ MXC_DCD_ITEM(MMDC2_MPRDDQBY1DL, 0x33333333)
+ MXC_DCD_ITEM(MMDC2_MPRDDQBY2DL, 0x33333333)
+ MXC_DCD_ITEM(MMDC2_MPRDDQBY3DL, 0x33333333)
+#endif
+ /* MDMISC */
+ MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
+ddr_reset:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack)
+
+ /* MSDSCR Conf Req */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000)
+con_ack:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib)
+ /* MDCTL */
+ MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
+ddr_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
+
+ MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
+ MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL)
+ MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL)
+ MXC_DCD_ITEM(MMDC1_MDRWD, 0x000026d2) /* MDRWD */
+ MXC_DCD_ITEM(MMDC1_MDOR, MDOR_VAL)
+ MXC_DCD_ITEM(MMDC1_MDOTC, MDOTC_VAL)
+ MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_0)
+ MXC_DCD_ITEM(MMDC1_MDASP, (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1) /* MDASP */
+
+ /* CS0 MRS: */
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val))
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
+#if BANK_ADDR_BITS > 1
+ /* CS1 MRS: MR2 */
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
+#endif
+
+ MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
+
+ MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00011112) /* MPODTCTRL */
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(MMDC2_MPODTCTRL, 0x00011112)
+#endif
+
+ /* DDR3 calibration */
+ MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
+ MXC_DCD_ITEM(MMDC1_MAPSR, 0x00011007)
+
+ /* ZQ calibration */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
+
+ MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa139002b)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(MMDC2_MPZQHWCTRL, 0xa138002b)
+#endif
+
+zq_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
+
+ /* Write leveling */
+ MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(MMDC2_MPZQHWCTRL, 0xa1380000)
+#endif
+
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x00808231) /* MRS: start write leveling */
+
+ MXC_DCD_ITEM(MMDC1_MPWLGCR, 0x00000001) /* initiate Write leveling */
+wl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000001)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000f00)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000001)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000f00)
+#endif
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset)
+
+ MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(MMDC2_MPZQHWCTRL, 0xa138002b)
+#endif
+
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
+
+ /* DQS gating calibration */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
+#endif
+ MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | (7 << 6) | (3 << 16)) /* RALAT/WALAT max. */
+
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
+
+ MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
+ MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
+ MXC_DCD_ITEM(MMDC1_MPMUR0, 0x00000800)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
+ MXC_DCD_ITEM(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
+ MXC_DCD_ITEM(MMDC2_MPMUR0, 0x00000800)
+#endif
+
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */
+dqs_fifo_reset:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2)
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */
+dqs_fifo_reset2:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
+dqs_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10000000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x00001000)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPDGCTRL0, 0x10000000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPDGCTRL0, 0x00001000)
+#endif
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
+
+ /* DRAM_SDQS[0..7] pad config */
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
+ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
+#endif
+
+ MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
+
+ /* Read delay calibration */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
+ MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_RD_DL_EN */
+rd_dl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000000f)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000000f)
+#endif
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
+
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
+ MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
+wr_dl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000000f)
+#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000000f)
+#endif
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr)
+
+ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
+ MXC_DCD_ITEM(MMDC1_MDREF, 0x00005800) /* MDREF */
+ MXC_DCD_ITEM(MMDC1_MAPSR, 0x00011006) /* MAPSR */
+ MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
+
+ /* MDSCR: Normal operation */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)
+
+con_ack_clr:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDSCR, 0x00004000)
+dcd_end:
+ .ifgt dcd_end - dcd_start - 1768
+ .error "DCD too large!"
+ .endif
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-//#define DEBUG
+#define DEBUG
//#define TIMER_TEST
#include <common.h>
#include "../common/karo.h"
-#define TX6Q_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
-#define TX6Q_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
-#define TX6Q_FEC_INT_GPIO IMX_GPIO_NR(2, 4)
-#define TX6Q_LED_GPIO IMX_GPIO_NR(2, 20)
+#define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
+#define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
+#define TX6_FEC_INT_GPIO IMX_GPIO_NR(2, 4)
+#define TX6_LED_GPIO IMX_GPIO_NR(2, 20)
-#define TX6Q_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
-#define TX6Q_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
-#define TX6Q_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
+#define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
+#define TX6_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
+#define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
-#define TX6Q_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
+#define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
#define TEMPERATURE_MIN -40
#define TEMPERATURE_HOT 80
DECLARE_GLOBAL_DATA_PTR;
-#define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
+#define MUX_CFG_SION IOMUX_PAD(0, 0, MUX_CONFIG_SION, 0, 0, 0)
-static const iomux_v3_cfg_t tx6q_pads[] = {
+static const iomux_v3_cfg_t tx6qdl_pads[] = {
/* NAND flash pads */
- MX6Q_PAD_NANDF_CLE__RAWNAND_CLE,
- MX6Q_PAD_NANDF_ALE__RAWNAND_ALE,
- MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN,
- MX6Q_PAD_NANDF_RB0__RAWNAND_READY0,
- MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N,
- MX6Q_PAD_SD4_CMD__RAWNAND_RDN,
- MX6Q_PAD_SD4_CLK__RAWNAND_WRN,
- MX6Q_PAD_NANDF_D0__RAWNAND_D0,
- MX6Q_PAD_NANDF_D1__RAWNAND_D1,
- MX6Q_PAD_NANDF_D2__RAWNAND_D2,
- MX6Q_PAD_NANDF_D3__RAWNAND_D3,
- MX6Q_PAD_NANDF_D4__RAWNAND_D4,
- MX6Q_PAD_NANDF_D5__RAWNAND_D5,
- MX6Q_PAD_NANDF_D6__RAWNAND_D6,
- MX6Q_PAD_NANDF_D7__RAWNAND_D7,
+ MX6_PAD_NANDF_CLE__RAWNAND_CLE,
+ MX6_PAD_NANDF_ALE__RAWNAND_ALE,
+ MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
+ MX6_PAD_NANDF_RB0__RAWNAND_READY0,
+ MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
+ MX6_PAD_SD4_CMD__RAWNAND_RDN,
+ MX6_PAD_SD4_CLK__RAWNAND_WRN,
+ MX6_PAD_NANDF_D0__RAWNAND_D0,
+ MX6_PAD_NANDF_D1__RAWNAND_D1,
+ MX6_PAD_NANDF_D2__RAWNAND_D2,
+ MX6_PAD_NANDF_D3__RAWNAND_D3,
+ MX6_PAD_NANDF_D4__RAWNAND_D4,
+ MX6_PAD_NANDF_D5__RAWNAND_D5,
+ MX6_PAD_NANDF_D6__RAWNAND_D6,
+ MX6_PAD_NANDF_D7__RAWNAND_D7,
/* RESET_OUT */
- MX6Q_PAD_GPIO_17__GPIO_7_12,
+ MX6_PAD_GPIO_17__GPIO_7_12,
/* UART pads */
#if CONFIG_MXC_UART_BASE == UART1_BASE
- MX6Q_PAD_SD3_DAT7__UART1_TXD,
- MX6Q_PAD_SD3_DAT6__UART1_RXD,
- MX6Q_PAD_SD3_DAT1__UART1_RTS,
- MX6Q_PAD_SD3_DAT0__UART1_CTS,
+ MX6_PAD_SD3_DAT7__UART1_TXD,
+ MX6_PAD_SD3_DAT6__UART1_RXD,
+ MX6_PAD_SD3_DAT1__UART1_RTS,
+ MX6_PAD_SD3_DAT0__UART1_CTS,
#endif
#if CONFIG_MXC_UART_BASE == UART2_BASE
- MX6Q_PAD_SD4_DAT4__UART2_RXD,
- MX6Q_PAD_SD4_DAT7__UART2_TXD,
- MX6Q_PAD_SD4_DAT5__UART2_RTS,
- MX6Q_PAD_SD4_DAT6__UART2_CTS,
+ MX6_PAD_SD4_DAT4__UART2_RXD,
+ MX6_PAD_SD4_DAT7__UART2_TXD,
+ MX6_PAD_SD4_DAT5__UART2_RTS,
+ MX6_PAD_SD4_DAT6__UART2_CTS,
#endif
#if CONFIG_MXC_UART_BASE == UART3_BASE
- MX6Q_PAD_EIM_D24__UART3_TXD,
- MX6Q_PAD_EIM_D25__UART3_RXD,
- MX6Q_PAD_SD3_RST__UART3_RTS,
- MX6Q_PAD_SD3_DAT3__UART3_CTS,
+ MX6_PAD_EIM_D24__UART3_TXD,
+ MX6_PAD_EIM_D25__UART3_RXD,
+ MX6_PAD_SD3_RST__UART3_RTS,
+ MX6_PAD_SD3_DAT3__UART3_CTS,
#endif
/* internal I2C */
- MX6Q_PAD_EIM_D28__I2C1_SDA,
- MX6Q_PAD_EIM_D21__I2C1_SCL,
+ MX6_PAD_EIM_D28__I2C1_SDA,
+ MX6_PAD_EIM_D21__I2C1_SCL,
/* FEC PHY GPIO functions */
- MX6Q_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
- MX6Q_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
- MX6Q_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
+ MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
+ MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
+ MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
};
-static const iomux_v3_cfg_t tx6q_fec_pads[] = {
+static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
/* FEC functions */
- MX6Q_PAD_ENET_MDC__ENET_MDC,
- MX6Q_PAD_ENET_MDIO__ENET_MDIO,
- MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
- MX6Q_PAD_ENET_RX_ER__ENET_RX_ER,
- MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN,
- MX6Q_PAD_ENET_RXD1__ENET_RDATA_1,
- MX6Q_PAD_ENET_RXD0__ENET_RDATA_0,
- MX6Q_PAD_ENET_TX_EN__ENET_TX_EN,
- MX6Q_PAD_ENET_TXD1__ENET_TDATA_1,
- MX6Q_PAD_ENET_TXD0__ENET_TDATA_0,
+ MX6_PAD_ENET_MDC__ENET_MDC,
+ MX6_PAD_ENET_MDIO__ENET_MDIO,
+ MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
+ MX6_PAD_ENET_RX_ER__ENET_RX_ER,
+ MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
+ MX6_PAD_ENET_RXD1__ENET_RDATA_1,
+ MX6_PAD_ENET_RXD0__ENET_RDATA_0,
+ MX6_PAD_ENET_TX_EN__ENET_TX_EN,
+ MX6_PAD_ENET_TXD1__ENET_TDATA_1,
+ MX6_PAD_ENET_TXD0__ENET_TDATA_0,
};
-static const struct gpio tx6q_gpios[] = {
- { TX6Q_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
- { TX6Q_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
- { TX6Q_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
- { TX6Q_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
+static const struct gpio tx6qdl_gpios[] = {
+ { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
+ { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
+ { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
+ { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
};
/*
int board_early_init_f(void)
{
- gpio_request_array(tx6q_gpios, ARRAY_SIZE(tx6q_gpios));
- imx_iomux_v3_setup_multiple_pads(tx6q_pads, ARRAY_SIZE(tx6q_pads));
+ gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
+ imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
return 0;
}
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
-#if 1
+#ifdef CONFIG_OF_LIBFDT
+ gd->bd->bi_arch_number = -1;
+#else
gd->bd->bi_arch_number = 4429;
#endif
ret = setup_pmic_voltages();
#ifdef CONFIG_CMD_MMC
static const iomux_v3_cfg_t mmc0_pads[] = {
- MX6Q_PAD_SD1_CMD__USDHC1_CMD,
- MX6Q_PAD_SD1_CLK__USDHC1_CLK,
- MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
- MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
- MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
- MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
+ MX6_PAD_SD1_CMD__USDHC1_CMD,
+ MX6_PAD_SD1_CLK__USDHC1_CLK,
+ MX6_PAD_SD1_DAT0__USDHC1_DAT0,
+ MX6_PAD_SD1_DAT1__USDHC1_DAT1,
+ MX6_PAD_SD1_DAT2__USDHC1_DAT2,
+ MX6_PAD_SD1_DAT3__USDHC1_DAT3,
/* SD1 CD */
- MX6Q_PAD_SD3_CMD__GPIO_7_2,
+ MX6_PAD_SD3_CMD__GPIO_7_2,
};
static const iomux_v3_cfg_t mmc1_pads[] = {
- MX6Q_PAD_SD2_CMD__USDHC2_CMD,
- MX6Q_PAD_SD2_CLK__USDHC2_CLK,
- MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
- MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
- MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
- MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
+ MX6_PAD_SD2_CMD__USDHC2_CMD,
+ MX6_PAD_SD2_CLK__USDHC2_CLK,
+ MX6_PAD_SD2_DAT0__USDHC2_DAT0,
+ MX6_PAD_SD2_DAT1__USDHC2_DAT1,
+ MX6_PAD_SD2_DAT2__USDHC2_DAT2,
+ MX6_PAD_SD2_DAT3__USDHC2_DAT3,
/* SD2 CD */
- MX6Q_PAD_SD3_CLK__GPIO_7_3,
+ MX6_PAD_SD3_CLK__GPIO_7_3,
};
static struct tx6q_esdhc_cfg {
int num_pads;
enum mxc_clock clkid;
struct fsl_esdhc_cfg cfg;
-} tx6q_esdhc_cfg[] = {
+} tx6qdl_esdhc_cfg[] = {
{
.pads = mmc0_pads,
.num_pads = ARRAY_SIZE(mmc0_pads),
return cfg->cd_gpio;
debug("SD card %d is %spresent\n",
- to_tx6q_esdhc_cfg(cfg) - tx6q_esdhc_cfg, gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
+ to_tx6q_esdhc_cfg(cfg) - tx6qdl_esdhc_cfg,
+ gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
return !gpio_get_value(cfg->cd_gpio);
}
{
int i;
- for (i = 0; i < ARRAY_SIZE(tx6q_esdhc_cfg); i++) {
+ for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
struct mmc *mmc;
- struct fsl_esdhc_cfg *cfg = &tx6q_esdhc_cfg[i].cfg;
+ struct fsl_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i].cfg;
if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
break;
- cfg->sdhc_clk = mxc_get_clock(tx6q_esdhc_cfg[i].clkid);
- imx_iomux_v3_setup_multiple_pads(tx6q_esdhc_cfg[i].pads,
- tx6q_esdhc_cfg[i].num_pads);
+ cfg->sdhc_clk = mxc_get_clock(tx6qdl_esdhc_cfg[i].clkid);
+ imx_iomux_v3_setup_multiple_pads(tx6qdl_esdhc_cfg[i].pads,
+ tx6qdl_esdhc_cfg[i].num_pads);
debug("%s: Initializing MMC slot %d\n", __func__, i);
fsl_esdhc_initialize(bis, cfg);
/* delay at least 21ms for the PHY internal POR signal to deassert */
udelay(22000);
- imx_iomux_v3_setup_multiple_pads(tx6q_fec_pads, ARRAY_SIZE(tx6q_fec_pads));
+ imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
/* Deassert RESET to the external phy */
- gpio_set_value(TX6Q_FEC_RST_GPIO, 1);
+ gpio_set_value(TX6_FEC_RST_GPIO, 1);
ret = cpu_eth_init(bis);
if (ret)
if (led_state == LED_STATE_INIT) {
last = get_timer(0);
- gpio_set_value(TX6Q_LED_GPIO, 1);
+ gpio_set_value(TX6_LED_GPIO, 1);
led_state = LED_STATE_ON;
blink_rate = calc_blink_rate(check_cpu_temperature(0));
} else {
blink_rate = calc_blink_rate(check_cpu_temperature(0));
last = get_timer_masked();
if (led_state == LED_STATE_ON) {
- gpio_set_value(TX6Q_LED_GPIO, 0);
+ gpio_set_value(TX6_LED_GPIO, 0);
} else {
- gpio_set_value(TX6Q_LED_GPIO, 1);
+ gpio_set_value(TX6_LED_GPIO, 1);
}
led_state = 1 - led_state;
}
static const iomux_v3_cfg_t stk5_pads[] = {
/* SW controlled LED on STK5 baseboard */
- MX6Q_PAD_EIM_A18__GPIO_2_20,
+ MX6_PAD_EIM_A18__GPIO_2_20,
/* LCD data pins */
- MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
- MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
- MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
- MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
- MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
- MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
- MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
- MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
- MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
- MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
- MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
- MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
- MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
- MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
- MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
- MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
- MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
- MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
- MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
- MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
- MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
- MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
- MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
- MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
- MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
- MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
- MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
- MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
/* I2C bus on DIMM pins 40/41 */
- MX6Q_PAD_GPIO_6__I2C3_SDA,
- MX6Q_PAD_GPIO_3__I2C3_SCL,
+ MX6_PAD_GPIO_6__I2C3_SDA,
+ MX6_PAD_GPIO_3__I2C3_SCL,
/* TSC200x PEN IRQ */
- MX6Q_PAD_EIM_D26__GPIO_3_26,
+ MX6_PAD_EIM_D26__GPIO_3_26,
/* EDT-FT5x06 Polytouch panel */
- MX6Q_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
- MX6Q_PAD_EIM_A16__GPIO_2_22, /* RESET */
- MX6Q_PAD_EIM_A17__GPIO_2_21, /* WAKE */
+ MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
+ MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
+ MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
/* USBH1 */
- MX6Q_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
- MX6Q_PAD_EIM_D30__GPIO_3_30, /* OC */
+ MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
+ MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
/* USBOTG */
- MX6Q_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
- MX6Q_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
- MX6Q_PAD_GPIO_8__GPIO_1_8, /* OC */
-
- /* DEBUG */
- MX6Q_PAD_GPIO_0__CCM_CLKO,
- MX6Q_PAD_NANDF_CS2__CCM_CLKO2,
+ MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
+ MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
+ MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
};
static const struct gpio stk5_gpios[] = {
- { TX6Q_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
+ { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
{ IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
{ IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
.vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
};
-static struct fb_videomode tx6q_fb_mode = {
- /* Standard VGA timing */
- .name = "VGA",
- .refresh = 60,
- .xres = 640,
- .yres = 480,
- .pixclock = KHZ2PICOS(25175),
- .left_margin = 48,
- .hsync_len = 96,
- .right_margin = 16,
- .upper_margin = 31,
- .vsync_len = 2,
- .lower_margin = 12,
- .sync = FB_SYNC_CLK_LAT_FALL,
- .vmode = FB_VMODE_NONINTERLACED,
+static struct fb_videomode tx6_fb_modes[] = {
+ {
+ /* Standard VGA timing */
+ .name = "VGA",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ETV570 640 x 480 display. Syncs low active,
+ * DE high active, 115.2 mm x 86.4 mm display area
+ * VGA compatible timing
+ */
+ .name = "ETV570",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 114,
+ .hsync_len = 30,
+ .right_margin = 16,
+ .upper_margin = 32,
+ .vsync_len = 3,
+ .lower_margin = 10,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0350G0DH6 320 x 240 display.
+ * 70.08 mm x 52.56 mm display area.
+ */
+ .name = "ET0350",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6500),
+ .left_margin = 68 - 34,
+ .hsync_len = 34,
+ .right_margin = 20,
+ .upper_margin = 18 - 3,
+ .vsync_len = 3,
+ .lower_margin = 4,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0430G0DH6 480 x 272 display.
+ * 95.04 mm x 53.856 mm display area.
+ */
+ .name = "ET0430",
+ .refresh = 60,
+ .xres = 480,
+ .yres = 272,
+ .pixclock = KHZ2PICOS(9000),
+ .left_margin = 2,
+ .hsync_len = 41,
+ .right_margin = 2,
+ .upper_margin = 2,
+ .vsync_len = 10,
+ .lower_margin = 2,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0500G0DH6 800 x 480 display.
+ * 109.6 mm x 66.4 mm display area.
+ */
+ .name = "ET0500",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ETQ570G0DH6 320 x 240 display.
+ * 115.2 mm x 86.4 mm display area.
+ */
+ .name = "ETQ570",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6400),
+ .left_margin = 38,
+ .hsync_len = 30,
+ .right_margin = 30,
+ .upper_margin = 16, /* 15 according to datasheet */
+ .vsync_len = 3, /* TVP -> 1>x>5 */
+ .lower_margin = 4, /* 4.5 according to datasheet */
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0700G0DH6 800 x 480 display.
+ * 152.4 mm x 91.44 mm display area.
+ */
+ .name = "ET0700",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* unnamed entry for assigning parameters parsed from 'video_mode' string */
+ .refresh = 60,
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
};
static int lcd_enabled = 1;
karo_load_splashimage(1);
if (lcd_enabled) {
debug("Switching LCD on\n");
- gpio_set_value(TX6Q_LCD_PWR_GPIO, 1);
+ gpio_set_value(TX6_LCD_PWR_GPIO, 1);
udelay(100);
- gpio_set_value(TX6Q_LCD_RST_GPIO, 1);
+ gpio_set_value(TX6_LCD_RST_GPIO, 1);
udelay(300000);
- gpio_set_value(TX6Q_LCD_BACKLIGHT_GPIO, 0);
+ gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 0);
}
}
static const iomux_v3_cfg_t stk5_lcd_pads[] = {
/* LCD RESET */
- MX6Q_PAD_EIM_D29__GPIO_3_29,
+ MX6_PAD_EIM_D29__GPIO_3_29,
/* LCD POWER_ENABLE */
- MX6Q_PAD_EIM_EB3__GPIO_2_31,
+ MX6_PAD_EIM_EB3__GPIO_2_31,
/* LCD Backlight (PWM) */
- MX6Q_PAD_GPIO_1__GPIO_1_1,
+ MX6_PAD_GPIO_1__GPIO_1_1,
/* Display */
- MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
- MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,
- MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,
- MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,
- MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
- MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
- MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
- MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
- MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
- MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
- MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
- MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
- MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
- MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
- MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
- MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
- MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
- MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
- MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
- MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
- MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
- MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
- MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
- MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
- MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
- MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
- MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
- MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
-
- /* LVDS option */
- MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
- MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
- MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
- MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
- MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
- MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
- MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
- MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
- MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
- MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
};
static const struct gpio stk5_lcd_gpios[] = {
- { TX6Q_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
- { TX6Q_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
- { TX6Q_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+ { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
+ { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
+ { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
};
void lcd_ctrl_init(void *lcdbase)
char *vm;
unsigned long val;
int refresh = 60;
- struct fb_videomode *p = &tx6q_fb_mode;
+ struct fb_videomode *p = &tx6_fb_modes[0];
+ struct fb_videomode fb_mode;
int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
int pix_fmt = 0;
ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
return;
}
+ karo_fdt_move_fdt();
+
vm = getenv("video_mode");
if (vm == NULL) {
debug("Disabling LCD\n");
lcd_enabled = 0;
return;
}
+ if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
+ p = &fb_mode;
+ debug("Using video mode from FDT\n");
+ vm += strlen(vm);
+ if (fb_mode.xres < panel_info.vl_col)
+ panel_info.vl_col = fb_mode.xres;
+ if (fb_mode.yres < panel_info.vl_row)
+ panel_info.vl_row = fb_mode.yres;
+ }
+ if (p->name != NULL)
+ debug("Trying compiled-in video modes\n");
+ while (p->name != NULL) {
+ if (strcmp(p->name, vm) == 0) {
+ debug("Using video mode: '%s'\n", p->name);
+ vm += strlen(vm);
+ break;
+ }
+ p++;
+ }
+ if (*vm != '\0')
+ debug("Trying to decode video_mode: '%s'\n", vm);
while (*vm != '\0') {
if (*vm >= '0' && *vm <= '9') {
char *end;
vm++;
}
}
- switch (color_depth) {
- case 8:
- panel_info.vl_bpix = 3;
- break;
-
- case 16:
- panel_info.vl_bpix = 4;
- break;
-
- case 18:
- case 24:
- panel_info.vl_bpix = 5;
+ if (p->xres == 0 || p->yres == 0) {
+ printf("Invalid video mode: %s\n", getenv("video_mode"));
+ lcd_enabled = 0;
+ printf("Supported video modes are:");
+ for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
+ printf(" %s", p->name);
+ }
+ printf("\n");
+ return;
}
p->pixclock = KHZ2PICOS(refresh *
gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
"Flexcan Transceiver");
- imx_iomux_v3_setup_pad(MX6Q_PAD_DISP0_DAT0__GPIO_4_21);
+ imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
}
-static void tx6q_set_cpu_clock(void)
+static void tx6qdl_set_cpu_clock(void)
{
unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
int ret = 0;
const char *baseboard;
- tx6q_set_cpu_clock();
+ tx6qdl_set_cpu_clock();
karo_fdt_move_fdt();
baseboard = getenv("baseboard");
exit:
tx6_init_mac();
- gpio_set_value(TX6Q_RESET_OUT_GPIO, 1);
+ gpio_set_value(TX6_RESET_OUT_GPIO, 1);
return ret;
}
-#define iomux_field(v,f) (((iomux_v3_cfg_t)(v) << f##_SHIFT) & f##_MASK)
-
-#define chk_iomux_field(f1,f2) ({ \
- iomux_v3_cfg_t __c = iomux_field(~0, f1); \
- if (__c & f2##_MASK) { \
- printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \
- #f1, f1##_MASK, \
- #f2, f2##_MASK); \
- } \
- (__c & f2##_MASK) != 0; \
-})
-
-#define chk_iomux_bit(f1,f2) ({ \
- iomux_v3_cfg_t __c = iomux_field(~0, f1); \
- if (__c & f2) { \
- printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \
- #f1, f1##_MASK, \
- #f2, (iomux_v3_cfg_t)f2); \
- } \
- (__c & f2) != 0; \
-})
-
int checkboard(void)
{
print_cpuinfo();
-
+#if defined(CONFIG_MX6Q)
printf("Board: Ka-Ro TX6Q\n");
+#elif defined(CONFIG_MX6DL)
+ printf("Board: Ka-Ro TX6DL\n");
+#else
+#error Unsupported i.MX6 variant selected
+#endif
#ifdef TIMER_TEST
{
#define fdt_fixup_mtdparts(b,n,c) do { } while (0)
#endif
-static void tx6q_fixup_flexcan(void *blob)
+static void tx6qdl_fixup_flexcan(void *blob)
{
const char *baseboard = getenv("baseboard");
fdt_fixup_ethernet(blob);
karo_fdt_fixup_touchpanel(blob);
- karo_fdt_fixup_usb_otg(blob, "", 0);
- tx6q_fixup_flexcan(blob);
+ karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
+ tx6qdl_fixup_flexcan(blob);
}
#endif
. = ALIGN(4);
.text :
{
- board/karo/tx6q/lowlevel_init.o (.text*)
+ board/karo/tx6/lowlevel_init.o (.text*)
__image_copy_start = .;
CPUDIR/start.o (.text*)
*(.text*)
+++ /dev/null
-#include <config.h>
-#include <configs/tx6q.h>
-#include <asm/arch/imx-regs.h>
-
-#define DEBUG_LED_BIT 20
-#define LED_GPIO_BASE GPIO2_BASE_ADDR
-#define LED_MUX_OFFSET 0x0ec
-#define LED_MUX_MODE 0x15
-
-#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
-
-#ifdef PHYS_SDRAM_2_SIZE
-#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
-#else
-#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
-#endif
-
-#define CPU_2_BE_32(l) \
- ((((l) << 24) & 0xFF000000) | \
- (((l) << 8) & 0x00FF0000) | \
- (((l) >> 8) & 0x0000FF00) | \
- (((l) >> 24) & 0x000000FF))
-
-#define CHECK_DCD_ADDR(a) ( \
- ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \
- ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \
- ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \
- ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \
- ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
- ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \
- ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
-
- .macro mxc_dcd_item addr, val
- .ifne CHECK_DCD_ADDR(\addr)
- .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
- .else
- .error "Address \addr not accessible from DCD"
- .endif
- .endm
-
-#define MXC_DCD_ITEM(addr, val) mxc_dcd_item addr, val
-
-#define MXC_DCD_CMD_SZ_BYTE 1
-#define MXC_DCD_CMD_SZ_SHORT 2
-#define MXC_DCD_CMD_SZ_WORD 4
-#define MXC_DCD_CMD_FLAG_WRITE 0x0
-#define MXC_DCD_CMD_FLAG_CLR 0x1
-#define MXC_DCD_CMD_FLAG_SET 0x3
-#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
-#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
-#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
-
-#define MXC_DCD_CMD_WRT(type, flags, next) \
- .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
-
-#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
- .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
- CPU_2_BE_32(addr), CPU_2_BE_32(mask)
-
-#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
- .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
- CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
-
-#define MXC_DCD_CMD_NOP \
- .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
-
-#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
-#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
-
- .macro CK_VAL, name, clks, offs, max
- .iflt \clks - \offs
- .set \name, 0
- .else
- .ifle \clks - \offs - \max
- .set \name, \clks - \offs
- .else
- .error "Value \clks out of range for parameter \name"
- .endif
- .endif
- .endm
-
- .macro NS_VAL, name, ns, offs, max
- .iflt \ns - \offs
- .set \name, 0
- .else
- CK_VAL \name, NS_TO_CK(\ns), \offs, \max
- .endif
- .endm
-
- .macro CK_MAX, name, ck1, ck2, offs, max
- .ifgt \ck1 - \ck2
- CK_VAL \name, \ck1, \offs, \max
- .else
- CK_VAL \name, \ck2, \offs, \max
- .endif
- .endm
-
-#define MDMISC_DDR_TYPE_DDR3 0
-#define MDMISC_DDR_TYPE_LPDDR2 1
-#define MDMISC_DDR_TYPE_DDR2 2
-
-#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
-
-#define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */
-
-/* DDR3 SDRAM */
-#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
-#define BANK_ADDR_BITS 2
-#else
-#define BANK_ADDR_BITS 1
-#endif
-#define SDRAM_BURST_LENGTH 8
-#define RALAT 5
-#define WALAT 0
-#define BI_ON 1
-#define ADDR_MIRROR 1
-#define DDR_TYPE MDMISC_DDR_TYPE_DDR3
-
-/* 512/1024MiB SDRAM: NT5CB128M16P-CG */
-/* MDCFG0 0x0c */
-NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
-CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
-CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
-CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
-NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
-CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */
-
-/* MDCFG1 0x10 */
-NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
-NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
-NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
-NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
-CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
-NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
-CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
-CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */
-
-/* MDCFG2 0x14 */
-CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
-CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
-CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
-CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
-
-/* MDOR 0x30 */
-CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
-#define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
-#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
-
-/* MDOTC 0x08 */
-NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */
-NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */
-CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
-CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
-CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */
-CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */
-
-/* MDPDC 0x04 */
-CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7
-CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
-CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
-
-#define PRCT 0
-#define PWDT 5
-#define SLOW_PD 0
-#define BOTH_CS_PD 1
-
-#define MDPDC_VAL_0 ( \
- (PRCT << 28) | \
- (PRCT << 24) | \
- (tCKE << 16) | \
- (SLOW_PD << 7) | \
- (BOTH_CS_PD << 6) | \
- (tCKSRX << 3) | \
- (tCKSRE << 0) \
- )
-
-#define MDPDC_VAL_1 (MDPDC_VAL_0 | \
- (PWDT << 12) | \
- (PWDT << 8) \
- )
-
-#define ROW_ADDR_BITS 14
-#define COL_ADDR_BITS 10
-
- .iflt tWR - 7
- .set mr0_val, ((1 << 8) /* DLL Reset */ | \
- ((tWR + 1 - 4) << 9) | \
- (((tCL + 3) - 4) << 4))
- .else
- .set mr0_val, ((1 << 8) /* DLL Reset */ | \
- (((tWR + 1) / 2) << 9) | \
- (((tCL + 3) - 4) << 4))
- .endif
-
-#define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
- (1 << 15) /* CON REQ */ | \
- (3 << 4) /* MRS command */ | \
- ((cs) << 3) | \
- ((mr) << 0))
-
-#define mr1_val 0x0040
-#define mr2_val 0x0408
-
-#define MDCFG0_VAL ( \
- (tRFC << 24) | \
- (tXS << 16) | \
- (tXP << 13) | \
- (tXPDLL << 9) | \
- (tFAW << 4) | \
- (tCL << 0)) \
-
-#define MDCFG1_VAL ( \
- (tRCD << 29) | \
- (tRP << 26) | \
- (tRC << 21) | \
- (tRAS << 16) | \
- (tRPA << 15) | \
- (tWR << 9) | \
- (tMRD << 5) | \
- (tCWL << 0)) \
-
-#define MDCFG2_VAL ( \
- (tDLLK << 16) | \
- (tRTP << 6) | \
- (tWTR << 3) | \
- (tRRD << 0))
-
-#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
-#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
- ((COL_ADDR_BITS - 9) << 20) | \
- (BURST_LEN << 19) | \
- (2 << 16) | /* SDRAM bus width */ \
- ((-1) << (32 - BANK_ADDR_BITS)))
-
-#define MDMISC_VAL ((ADDR_MIRROR << 19) | \
- (WALAT << 16) | \
- (BI_ON << 12) | \
- (0x3 << 9) | \
- (RALAT << 6) | \
- (DDR_TYPE << 3))
-
-#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
-
-#define MDOTC_VAL ((tAOFPD << 27) | \
- (tAONPD << 24) | \
- (tANPD << 20) | \
- (tAXPD << 16) | \
- (tODTLon << 12) | \
- (tODTLoff << 4))
-
-fcb_start:
- b _start
- .org 0x400
-ivt_header:
- .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
-app_start_addr:
- .long _start
- .long 0x0
-dcd_ptr:
- .long dcd_hdr
-boot_data_ptr:
- .word boot_data
-self_ptr:
- .word ivt_header
-app_code_csf:
- .word 0x0
- .word 0x0
-boot_data:
- .long fcb_start
-image_len:
- .long CONFIG_U_BOOT_IMG_SIZE
-plugin:
- .word 0
-ivt_end:
-#define DCD_VERSION 0x40
-
-#define CLKCTL_CCGR0 0x68
-#define CLKCTL_CCGR1 0x6c
-#define CLKCTL_CCGR2 0x70
-#define CLKCTL_CCGR3 0x74
-#define CLKCTL_CCGR4 0x78
-#define CLKCTL_CCGR5 0x7c
-#define CLKCTL_CCGR6 0x80
-#define CLKCTL_CCGR7 0x84
-#define CLKCTL_CMEOR 0x88
-
-#define DDR_SEL_VAL 3
-#define DSE_VAL 6
-#define ODT_VAL 2
-
-#define DDR_SEL_SHIFT 18
-#define DDR_MODE_SHIFT 17
-#define ODT_SHIFT 8
-#define DSE_SHIFT 3
-#define HYS_SHIFT 16
-#define PKE_SHIFT 12
-#define PUE_SHIFT 13
-#define PUS_SHIFT 14
-
-#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
-#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT)
-#define DSE_MASK (DSE_VAL << DSE_SHIFT)
-#define ODT_MASK (ODT_VAL << ODT_SHIFT)
-
-#define DQM_MASK (DDR_MODE_MASK | DSE_MASK)
-#define SDQS_MASK DSE_MASK
-#define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
-#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK)
-#define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
-#define DDR_ADDR_MASK 0
-#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK)
-
-dcd_hdr:
- .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
-dcd_start:
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset)
- /* RESET_OUT GPIO_7_12 */
- MXC_DCD_ITEM(0x020e024c, 0x00000005)
-
- MXC_DCD_ITEM(0x020c402c, 0x006336c1) /* CS2CDR default: 0x007236c1 */
-
- MXC_DCD_ITEM(0x020c80e0, 0x00002001) /* ENET PLL */
-
- /* enable all relevant clocks... */
- MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
- MXC_DCD_ITEM(0x020c406c, 0xf0fc0c00) /* default: 0xf0fc0000 */
- MXC_DCD_ITEM(0x020c4070, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
- MXC_DCD_ITEM(0x020c4074, 0x3ff00000) /* default: 0x3ff00000 */
- MXC_DCD_ITEM(0x020c4078, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
- MXC_DCD_ITEM(0x020c407c, 0xff033f0f) /* default: 0xf0033f0f UART1 */
- MXC_DCD_ITEM(0x020c4080, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
-
- /* IOMUX: */
- MXC_DCD_ITEM(0x020e0004, 0x48640005) /* default: 0x48400005 ENET_CLK output */
- /* UART1 pad config */
- MXC_DCD_ITEM(0x020e02a8, 0x00000001) /* UART1 TXD */
- MXC_DCD_ITEM(0x020e02ac, 0x00000001) /* UART1 RXD */
- MXC_DCD_ITEM(0x020e0920, 0x00000003) /* UART1 RXD INPUT_SEL */
- MXC_DCD_ITEM(0x020e02c0, 0x00000001) /* UART1 CTS */
- MXC_DCD_ITEM(0x020e02c4, 0x00000001) /* UART1 RTS */
- MXC_DCD_ITEM(0x020e091c, 0x00000003) /* UART1 RTS INPUT_SEL */
-
- /* NAND */
- MXC_DCD_ITEM(0x020e02d4, 0x00000000) /* NANDF_CLE: NANDF_CLE */
- MXC_DCD_ITEM(0x020e02d8, 0x00000000) /* NANDF_ALE: NANDF_ALE */
- MXC_DCD_ITEM(0x020e02dc, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
- MXC_DCD_ITEM(0x020e02e0, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
- MXC_DCD_ITEM(0x020e02e4, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
- MXC_DCD_ITEM(0x020e02f4, 0x00000001) /* SD4_CMD: NANDF_RDn */
- MXC_DCD_ITEM(0x020e02f8, 0x00000001) /* SD4_CLK: NANDF_WRn */
- MXC_DCD_ITEM(0x020e02fc, 0x00000000) /* NANDF_D0: NANDF_D0 */
- MXC_DCD_ITEM(0x020e0300, 0x00000000) /* NANDF_D1: NANDF_D1 */
- MXC_DCD_ITEM(0x020e0304, 0x00000000) /* NANDF_D2: NANDF_D2 */
- MXC_DCD_ITEM(0x020e0308, 0x00000000) /* NANDF_D3: NANDF_D3 */
- MXC_DCD_ITEM(0x020e030c, 0x00000000) /* NANDF_D4: NANDF_D4 */
- MXC_DCD_ITEM(0x020e0310, 0x00000000) /* NANDF_D5: NANDF_D5 */
- MXC_DCD_ITEM(0x020e0314, 0x00000000) /* NANDF_D6: NANDF_D6 */
- MXC_DCD_ITEM(0x020e0318, 0x00000000) /* NANDF_D7: NANDF_D7 */
-
- /* ext. mem CS */
- MXC_DCD_ITEM(0x020e02ec, 0x00000000) /* NANDF_CS2: NANDF_CS2 */
- /* DRAM_DQM[0..7] */
- MXC_DCD_ITEM(0x020e05ac, DQM_MASK)
- MXC_DCD_ITEM(0x020e05b4, DQM_MASK)
- MXC_DCD_ITEM(0x020e0528, DQM_MASK)
- MXC_DCD_ITEM(0x020e0520, DQM_MASK)
- MXC_DCD_ITEM(0x020e0514, DQM_MASK)
- MXC_DCD_ITEM(0x020e0510, DQM_MASK)
- MXC_DCD_ITEM(0x020e05bc, DQM_MASK)
- MXC_DCD_ITEM(0x020e05c4, DQM_MASK)
- /* DRAM_A[0..15] */
- MXC_DCD_ITEM(0x020e052c, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0530, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0534, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0538, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e053c, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0540, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0544, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0548, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e054c, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0550, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0554, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0558, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e055c, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0560, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0564, DDR_ADDR_MASK)
- MXC_DCD_ITEM(0x020e0568, DDR_ADDR_MASK)
- /* DRAM_CAS */
- MXC_DCD_ITEM(0x020e056c, DDR_CTRL_MASK)
- /* DRAM_RAS */
- MXC_DCD_ITEM(0x020e0578, DDR_CTRL_MASK)
- /* DRAM_SDCLK[0..1] */
- MXC_DCD_ITEM(0x020e0588, SDCLK_MASK)
- MXC_DCD_ITEM(0x020e0594, SDCLK_MASK)
- /* DRAM_RESET */
- MXC_DCD_ITEM(0x020e057c, DDR_CTRL_MASK)
- /* DRAM_SDCKE[0..1] */
- MXC_DCD_ITEM(0x020e0590, SDCKE_MASK)
- MXC_DCD_ITEM(0x020e0598, SDCKE_MASK)
- /* DRAM_SDBA[0..2] */
- MXC_DCD_ITEM(0x020e0580, 0x00000000)
- MXC_DCD_ITEM(0x020e0584, 0x00000000)
- MXC_DCD_ITEM(0x020e058c, 0x00000000)
- /* DRAM_SDODT[0..1] */
- MXC_DCD_ITEM(0x020e059c, SDODT_MASK)
- MXC_DCD_ITEM(0x020e05a0, SDODT_MASK)
- /* DRAM_B[0..7]DS */
- MXC_DCD_ITEM(0x020e0784, DSE_MASK)
- MXC_DCD_ITEM(0x020e0788, DSE_MASK)
- MXC_DCD_ITEM(0x020e0794, DSE_MASK)
- MXC_DCD_ITEM(0x020e079c, DSE_MASK)
- MXC_DCD_ITEM(0x020e07a0, DSE_MASK)
- MXC_DCD_ITEM(0x020e07a4, DSE_MASK)
- MXC_DCD_ITEM(0x020e07a8, DSE_MASK)
- MXC_DCD_ITEM(0x020e0748, DSE_MASK)
- /* ADDDS */
- MXC_DCD_ITEM(0x020e074c, DSE_MASK)
- /* DDRMODE_CTL */
- MXC_DCD_ITEM(0x020e0750, DDR_MODE_MASK)
- /* DDRPKE */
- MXC_DCD_ITEM(0x020e0758, 0x00000000)
- /* DDRMODE */
- MXC_DCD_ITEM(0x020e0774, DDR_MODE_MASK)
- /* CTLDS */
- MXC_DCD_ITEM(0x020e078c, DSE_MASK)
- /* DDR_TYPE */
- MXC_DCD_ITEM(0x020e0798, DDR_SEL_MASK)
- /* DDRPK */
- MXC_DCD_ITEM(0x020e0768, 1 << PUE_SHIFT)
- /* DDRHYS */
- MXC_DCD_ITEM(0x020e0770, 0x00000000)
- /* TERM_CTL[0..7] */
- MXC_DCD_ITEM(0x020e0754, ODT_MASK)
- MXC_DCD_ITEM(0x020e075c, ODT_MASK)
- MXC_DCD_ITEM(0x020e0760, ODT_MASK)
- MXC_DCD_ITEM(0x020e0764, ODT_MASK)
- MXC_DCD_ITEM(0x020e076c, ODT_MASK)
- MXC_DCD_ITEM(0x020e0778, ODT_MASK)
- MXC_DCD_ITEM(0x020e077c, ODT_MASK)
- MXC_DCD_ITEM(0x020e0780, ODT_MASK)
-
- /* SDRAM initialization */
- /* MPRDDQBY[0..7]DL */
- MXC_DCD_ITEM(0x021b081c, 0x33333333)
- MXC_DCD_ITEM(0x021b481c, 0x33333333)
- MXC_DCD_ITEM(0x021b0820, 0x33333333)
- MXC_DCD_ITEM(0x021b4820, 0x33333333)
- MXC_DCD_ITEM(0x021b0824, 0x33333333)
- MXC_DCD_ITEM(0x021b4824, 0x33333333)
- MXC_DCD_ITEM(0x021b0828, 0x33333333)
- MXC_DCD_ITEM(0x021b4828, 0x33333333)
- /* MDMISC */
- MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | 2) /* reset MMDC FSM */
-ddr_reset:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0018, 0x00000002)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack)
-
- /* MSDSCR Conf Req */
- MXC_DCD_ITEM(0x021b001c, 0x00008000)
-con_ack:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b001c, 0x00004000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib)
- /* MDCTL */
- MXC_DCD_ITEM(0x021b0000, MDCTL_VAL)
-ddr_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b0018, 0x40000000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
-
- MXC_DCD_ITEM(0x021b000c, MDCFG0_VAL)
- MXC_DCD_ITEM(0x021b0010, MDCFG1_VAL)
- MXC_DCD_ITEM(0x021b0014, MDCFG2_VAL)
- MXC_DCD_ITEM(0x021b002c, 0x000026d2) /* MDRWD */
- MXC_DCD_ITEM(0x021b0030, MDOR_VAL)
- MXC_DCD_ITEM(0x021b0008, MDOTC_VAL)
- MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_0)
- MXC_DCD_ITEM(0x021b0040, 0x00000027) /* MDASP */
-
- /* CS0 MRS: */
- MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 0, mr0_val))
- MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val))
- MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 2, mr2_val))
- MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0))
-#if BANK_ADDR_BITS > 1
- /* CS1 MRS: MR2 */
- MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 0, mr0_val))
- MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 1, mr1_val))
- MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 2, mr2_val))
- MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
-#endif
- MXC_DCD_ITEM(0x021b0020, 0x0000c000) /* disable refresh */
-
- MXC_DCD_ITEM(0x021b0818, 0x00011112) /* MPODTCTRL */
- MXC_DCD_ITEM(0x021b4818, 0x00011112)
-
- /* DDR3 calibration */
- MXC_DCD_ITEM(0x021b0890, 0x00000003) /* select default compare pattern for DQ calibration */
- MXC_DCD_ITEM(0x021b0404, 0x00011007)
-
- /* ZQ calibration */
- MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */
- MXC_DCD_ITEM(0x021b001c, 0x04008040) /* MRS: ZQ calibration */
-
- MXC_DCD_ITEM(0x021b4800, 0xa138002b)
- MXC_DCD_ITEM(0x021b0800, 0xa139002b)
-zq_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0800, 0x00010000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
-
- /* Write leveling */
- MXC_DCD_ITEM(0x021b4800, 0xa1380000)
- MXC_DCD_ITEM(0x021b0800, 0xa1380000)
-
- MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
- MXC_DCD_ITEM(0x021b001c, 0x00808231) /* MRS: start write leveling */
-
- MXC_DCD_ITEM(0x021b0808, 0x00000001) /* initiate Write leveling */
-wl_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000001)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000f00)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000001)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000f00)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset)
-
- MXC_DCD_ITEM(0x021b0800, 0xa138002b)
- MXC_DCD_ITEM(0x021b4800, 0xa138002b)
-
- MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
-
- /* DQS gating calibration */
- MXC_DCD_ITEM(0x020e05a8, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
- MXC_DCD_ITEM(0x020e05b0, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(0x020e0524, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(0x020e051c, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(0x020e0518, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(0x020e050c, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(0x020e05b8, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(0x020e05c0, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | (7 << 6) | (3 << 16)) /* RALAT/WALAT max. */
-
- MXC_DCD_ITEM(0x021b001c, 0x00008020) /* issue one refresh cycle */
- MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
-
- MXC_DCD_ITEM(0x021b0848, 0x40404040) /* DQ RD Delay default values */
- MXC_DCD_ITEM(0x021b4848, 0x40404040)
- MXC_DCD_ITEM(0x021b0850, 0x40404040) /* DQ WR Delay default values */
- MXC_DCD_ITEM(0x021b4850, 0x40404040)
- MXC_DCD_ITEM(0x021b48b8, 0x00000800)
- MXC_DCD_ITEM(0x021b08b8, 0x00000800)
-
- MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue fifo reset */
-dqs_fifo_reset:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2)
- MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue 2nd fifo reset */
-dqs_fifo_reset2:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
- MXC_DCD_ITEM(0x021b083c, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
-dqs_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x10000000)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x00001000)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x10000000)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x00001000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
-
- /* DRAM_SDQS[0..7] pad config */
- MXC_DCD_ITEM(0x020e05a8, SDQS_MASK)
- MXC_DCD_ITEM(0x020e05b0, SDQS_MASK)
- MXC_DCD_ITEM(0x020e0524, SDQS_MASK)
- MXC_DCD_ITEM(0x020e051c, SDQS_MASK)
- MXC_DCD_ITEM(0x020e0518, SDQS_MASK)
- MXC_DCD_ITEM(0x020e050c, SDQS_MASK)
- MXC_DCD_ITEM(0x020e05b8, SDQS_MASK)
- MXC_DCD_ITEM(0x020e05c0, SDQS_MASK)
-
- MXC_DCD_ITEM(0x021b0018, MDMISC_VAL)
-
- /* Read delay calibration */
- MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
- MXC_DCD_ITEM(0x021b0860, 0x00000030) /* MPRDDLHWCTL: HW_RD_DL_EN */
-rd_dl_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x00000010)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x00000010)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x0000000f)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x0000000f)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
-
- MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
- MXC_DCD_ITEM(0x021b0864, 0x00000030) /* start WR DL calibration */
-wr_dl_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x00000010)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x00000010)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x0000000f)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x0000000f)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr)
-
- MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
- MXC_DCD_ITEM(0x021b0020, 0x00005800) /* MDREF */
- MXC_DCD_ITEM(0x021b0404, 0x00011006) /* MAPSR */
- MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_1)
-
- /* MDSCR: Normal operation */
- MXC_DCD_ITEM(0x021b001c, 0x00000000)
-con_ack_clr:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b001c, 0x00004000)
-dcd_end:
- .ifgt dcd_end - dcd_start - 1768
- .error "DCD too large!"
- .endif
+++ /dev/null
-/*
- * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
- * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/iomux-mx6.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-
-#define MUX_CONFIG_LED MX6_PAD_CTL_DSE_80ohm
-#define MUX_CONFIG_LCD (MX6_PAD_CTL_SPEED_HIGH | MX6_PAD_CTL_SRE_FAST | \
- MX6_PAD_CTL_DSE_80ohm)
-#define MUX_CONFIG_TSC (MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_DSE_80ohm | \
- MX6_PAD_CTL_PUS_47K_UP)
-#define MUX_CONFIG_GPMI MX6_PAD_CTL_DSE_80ohm
-#define MUX_CONFIG_EMI MX6Q_HIGH_DRV
-#define MUX_CONFIG_GPIO MX6_PAD_CTL_PUS_47K_UP
-
-static iomux_v3_cfg_t tx6q_stk5_pads[] = {
- /* LED */
- MX6Q_PAD_EIM_A18__GPIO_2_20,
-
- /* framebuffer */
- MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
- MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
- MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
- MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
- MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
- MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
- MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
- MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
- MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
- MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
- MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
- MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
- MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
- MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
- MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
- MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
- MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
- MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
- MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
- MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
- MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
- MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
- MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
- MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
- MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* LCD VSYNC */
- MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* LCD HSYNC */
- MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LCD DOTCLK */
- MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* LCD OE/ACD */
-
- /* UART1 pads */
- MX6Q_PAD_SD3_DAT7__UART1_TXD,
- MX6Q_PAD_SD3_DAT6__UART1_RXD,
- MX6Q_PAD_SD3_DAT1__UART1_RTS,
- MX6Q_PAD_SD3_DAT0__UART1_CTS,
-
- /* EMI */
- MX6_PAD_EMI_D00__EMI_DATA0,
- MX6_PAD_EMI_D01__EMI_DATA1,
- MX6_PAD_EMI_D02__EMI_DATA2,
- MX6_PAD_EMI_D03__EMI_DATA3,
- MX6_PAD_EMI_D04__EMI_DATA4,
- MX6_PAD_EMI_D05__EMI_DATA5,
- MX6_PAD_EMI_D06__EMI_DATA6,
- MX6_PAD_EMI_D07__EMI_DATA7,
- MX6_PAD_EMI_D08__EMI_DATA8,
- MX6_PAD_EMI_D09__EMI_DATA9,
- MX6_PAD_EMI_D10__EMI_DATA10,
- MX6_PAD_EMI_D11__EMI_DATA11,
- MX6_PAD_EMI_D12__EMI_DATA12,
- MX6_PAD_EMI_D13__EMI_DATA13,
- MX6_PAD_EMI_D14__EMI_DATA14,
- MX6_PAD_EMI_D15__EMI_DATA15,
- MX6_PAD_EMI_ODT0__EMI_ODT0,
- MX6_PAD_EMI_DQM0__EMI_DQM0,
- MX6_PAD_EMI_ODT1__EMI_ODT1,
- MX6_PAD_EMI_DQM1__EMI_DQM1,
- MX6_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK,
- MX6_PAD_EMI_CLK__EMI_CLK,
- MX6_PAD_EMI_DQS0__EMI_DQS0,
- MX6_PAD_EMI_DQS1__EMI_DQS1,
- MX6_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN,
-
- MX6_PAD_EMI_A00__EMI_ADDR0,
- MX6_PAD_EMI_A01__EMI_ADDR1,
- MX6_PAD_EMI_A02__EMI_ADDR2,
- MX6_PAD_EMI_A03__EMI_ADDR3,
- MX6_PAD_EMI_A04__EMI_ADDR4,
- MX6_PAD_EMI_A05__EMI_ADDR5,
- MX6_PAD_EMI_A06__EMI_ADDR6,
- MX6_PAD_EMI_A07__EMI_ADDR7,
- MX6_PAD_EMI_A08__EMI_ADDR8,
- MX6_PAD_EMI_A09__EMI_ADDR9,
- MX6_PAD_EMI_A10__EMI_ADDR10,
- MX6_PAD_EMI_A11__EMI_ADDR11,
- MX6_PAD_EMI_A12__EMI_ADDR12,
- MX6_PAD_EMI_A13__EMI_ADDR13,
- MX6_PAD_EMI_A14__EMI_ADDR14,
- MX6_PAD_EMI_BA0__EMI_BA0,
- MX6_PAD_EMI_BA1__EMI_BA1,
- MX6_PAD_EMI_BA2__EMI_BA2,
- MX6_PAD_EMI_CASN__EMI_CASN,
- MX6_PAD_EMI_RASN__EMI_RASN,
- MX6_PAD_EMI_WEN__EMI_WEN,
- MX6_PAD_EMI_CE0N__EMI_CE0N,
- MX6_PAD_EMI_CE1N__EMI_CE1N,
- MX6_PAD_EMI_CKE__EMI_CKE,
-
- /* FEC pads */
- MX6_PAD_PWM4__GPIO_3_29,
- MX6_PAD_ENET0_RX_CLK__GPIO_4_13,
- MX6_PAD_ENET0_MDC__ENET0_MDC,
- MX6_PAD_ENET0_MDIO__ENET0_MDIO,
- MX6_PAD_ENET0_RX_EN__GPIO_4_2, /* COL/CRS_DV/MODE2 */
- MX6_PAD_ENET0_RXD0__GPIO_4_3, /* RXD0/MODE0 */
- MX6_PAD_ENET0_RXD1__GPIO_4_4, /* RXD1/MODE1 */
- MX6_PAD_ENET0_TX_CLK__GPIO_4_5, /* nINT/TX_ER/TXD4 */
- MX6_PAD_ENET0_TX_EN__ENET0_TX_EN,
- MX6_PAD_ENET0_TXD0__ENET0_TXD0,
- MX6_PAD_ENET0_TXD1__ENET0_TXD1,
- MX6_PAD_ENET_CLK__CLKCTRL_ENET,
-
- /* MMC pads */
- MX6_PAD_SSP0_DATA0__SSP0_D0,
- MX6_PAD_SSP0_DATA1__SSP0_D1,
- MX6_PAD_SSP0_DATA2__SSP0_D2,
- MX6_PAD_SSP0_DATA3__SSP0_D3,
- MX6_PAD_SSP0_CMD__SSP0_CMD,
- MX6_PAD_SSP0_DETECT__SSP0_CARD_DETECT,
- MX6_PAD_SSP0_SCK__SSP0_SCK,
-
- /* GPMI pads */
- MX6_PAD_GPMI_D00__GPMI_D0,
- MX6_PAD_GPMI_D01__GPMI_D1,
- MX6_PAD_GPMI_D02__GPMI_D2,
- MX6_PAD_GPMI_D03__GPMI_D3,
- MX6_PAD_GPMI_D04__GPMI_D4,
- MX6_PAD_GPMI_D05__GPMI_D5,
- MX6_PAD_GPMI_D06__GPMI_D6,
- MX6_PAD_GPMI_D07__GPMI_D7,
- MX6_PAD_GPMI_CE0N__GPMI_CE0N,
- MX6_PAD_GPMI_RDY0__GPMI_READY0,
- MX6_PAD_GPMI_RDN__GPMI_RDN,
- MX6_PAD_GPMI_WRN__GPMI_WRN,
- MX6_PAD_GPMI_ALE__GPMI_ALE,
- MX6_PAD_GPMI_CLE__GPMI_CLE,
- MX6_PAD_GPMI_RESETN__GPMI_RESETN,
-
- /* maybe used for EDT-FT5x06 */
- MX6_PAD_SSP0_DATA5__GPIO_2_5,
- MX6_PAD_SSP0_DATA6__GPIO_2_6,
- MX6_PAD_ENET0_RXD2__GPIO_4_9,
-
- /* unused pads */
- MX6_PAD_GPMI_RDY1__GPIO_0_21,
- MX6_PAD_GPMI_RDY2__GPIO_0_22,
- MX6_PAD_GPMI_RDY3__GPIO_0_23,
- MX6_PAD_GPMI_CE1N__GPIO_0_17,
- MX6_PAD_GPMI_CE2N__GPIO_0_18,
- MX6_PAD_GPMI_CE3N__GPIO_0_19,
-
- MX6_PAD_SSP0_DATA4__GPIO_2_4,
- MX6_PAD_SSP0_DATA7__GPIO_2_7,
-
- MX6_PAD_SSP2_SS0__GPIO_2_19,
- MX6_PAD_SSP2_SS1__GPIO_2_20,
- MX6_PAD_SSP2_SS2__GPIO_2_21,
- MX6_PAD_SSP3_SS0__GPIO_2_27,
-
- MX6_PAD_ENET0_TXD2__GPIO_4_11,
- MX6_PAD_ENET0_TXD3__GPIO_4_12,
- MX6_PAD_ENET0_CRS__GPIO_4_15,
-};
-
-static void tx6q_stk5_lcd_init(void)
-{
- gpio_direction_output(MX6_PAD_PWM0__GPIO_3_16, 1);
- gpio_direction_output(MX6_PAD_LCD_RESET__GPIO_3_30, 0);
- gpio_direction_output(MX6_PAD_LCD_ENABLE__GPIO_1_31, 0);
-}
-
-static void tx6q_stk5_led_on(void)
-{
- gpio_direction_output(MX6Q_PAD_EIM_A18__GPIO_2_20, 1);
-}
-
-void board_init_ll(void)
-{
- mx6_common_spl_init(tx6q_stk5_pads, ARRAY_SIZE(tx6q_stk5_pads));
- tx6q_stk5_lcd_init();
- tx6q_stk5_led_on();
-}
tx53-xx21 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=2,SYS_TX53_HWREV_2
tx53-xx30 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=1
tx53-xx31 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=2
-tx6q arm armv7 tx6q karo mx6
-tx6q_mfg arm armv7 tx6q karo mx6 tx6q:MFG
-tx6q_noenv arm armv7 tx6q karo mx6 tx6q:ENV_IS_NOWHERE
+tx6dl arm armv7 tx6 karo mx6 tx6:MX6DL
+tx6dl_mfg arm armv7 tx6 karo mx6 tx6:MX6DL,MFG
+tx6dl_noenv arm armv7 tx6 karo mx6 tx6:MX6DL,ENV_IS_NOWHERE
+tx6q arm armv7 tx6 karo mx6 tx6:MX6Q
+tx6q_mfg arm armv7 tx6 karo mx6 tx6:MX6Q,MFG
+tx6q_noenv arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_NOWHERE
mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
debug("panel size = %d x %d\n", width, height);
if ((v_sync_width == 0) || (h_sync_width == 0))
- return EINVAL;
+ return -EINVAL;
adapt_panel_to_ipu_restricitions(&pixel_clk, width, height,
h_start_width, h_end_width,
"bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
" root=/dev/mtdblock3 rootfstype=jffs2\0" \
"bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
- " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\
+ " root=/dev/nfs ip=dhcp nfsroot=${nfs_server}:${nfsroot},nolock\0"\
"bootcmd_mmc=set autostart no;run bootargs_mmc;" \
"fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \
"bootcmd_nand=set autostart no;run bootargs_nand;" \
"nboot linux;run bootm_cmd\0" \
"bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
"run bootm_cmd\0" \
- "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \
+ "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
"default_bootargs=set bootargs " CONFIG_BOOTARGS \
" mxsfb.mode=${video_mode} ${append_bootargs}\0" \
"fdtaddr=41000000\0" \
*/
#ifdef CONFIG_OF_LIBFDT
#define TX48_BOOTM_CMD \
- "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0"
+ "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0"
#define TX48_MTDPARTS_CMD ""
#else
#define TX48_BOOTM_CMD \
" root=/dev/mtdblock4 rootfstype=jffs2\0" \
"nfsroot=/tftpboot/rootfs\0" \
"bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
- " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\
+ " root=/dev/nfs ip=dhcp nfsroot=${nfs_server}:${nfsroot},nolock\0"\
"bootcmd_mmc=set autostart no;run bootargs_mmc;" \
" fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \
"bootcmd_nand=set autostart no;run bootargs_nand;" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"otg_mode=device\0" \
"touchpanel=tsc2007\0" \
- "video_mode=640x480MR-24@60\0"
+ "video_mode=da8xx-fb:640x480MR-24@60\0"
#define MTD_NAME "omap2-nand.0"
#define MTDIDS_DEFAULT "nand0=" MTD_NAME
" root=/dev/mtdblock3 rootfstype=jffs2\0" \
"nfsroot=/tftpboot/rootfs\0" \
"bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
- " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\
+ " root=/dev/nfs ip=dhcp nfsroot=${nfs_server}:${nfsroot},nolock\0"\
"bootcmd_mmc=set autostart no;run bootargs_mmc;" \
"mmc read ${loadaddr} 100 3000;run bootm_cmd\0" \
"bootcmd_nand=set autostart no;run bootargs_nand;" \
"nboot linux;run bootm_cmd\0" \
"bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
"run bootm_cmd\0" \
- "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \
+ "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
"default_bootargs=set bootargs " CONFIG_BOOTARGS \
" video=${video_mode} ${append_bootargs}\0" \
"cpu_clk=" xstr(CONFIG_SYS_CPU_CLK) "\0" \
" root=/dev/mtdblock3 rootfstype=jffs2\0" \
"nfsroot=/tftpboot/rootfs\0" \
"bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
- " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\
+ " root=/dev/nfs ip=dhcp nfsroot=${nfs_server}:${nfsroot},nolock\0"\
"bootcmd_mmc=set autostart no;run bootargs_mmc;" \
"mmc read ${loadaddr} 100 3000;run bootm_cmd\0" \
"bootcmd_nand=set autostart no;run bootargs_nand;" \
"nboot linux;run bootm_cmd\0" \
"bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
"run bootm_cmd\0" \
- "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \
+ "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
"default_bootargs=set bootargs " CONFIG_BOOTARGS \
" video=${video_mode} ${append_bootargs}\0" \
"cpu_clk=800\0" \
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-#ifndef __TX6Q_H
-#define __TX6Q_H
+#ifndef __TX6_H
+#define __TX6_H
#include <asm/sizes.h>
/*
- * Ka-Ro TX6Q board - SoC configuration
+ * Ka-Ro TX6 board - SoC configuration
*/
#define CONFIG_MX6
-#define CONFIG_MX6Q
#define CONFIG_SYS_MX6_HCLK 24000000
#define CONFIG_SYS_MX6_CLK32 32768
#define CONFIG_SYS_HZ 1000 /* Ticks per second */
*/
#define CONFIG_NR_DRAM_BANKS 1 /* # of SDRAM banks */
#define PHYS_SDRAM_1 0x10000000 /* Base address of bank 1 */
+#ifdef CONFIG_MX6Q
#define PHYS_SDRAM_1_SIZE SZ_1G
+#define PHYS_SDRAM_1_WIDTH 64
+#define CONFIG_SYS_SDRAM_CLK 528
+#else
+#define PHYS_SDRAM_1_SIZE SZ_512M
+#define PHYS_SDRAM_1_WIDTH 32
+#define CONFIG_SYS_SDRAM_CLK 400
+#endif
#define CONFIG_STACKSIZE SZ_128K
#define CONFIG_SYS_MALLOC_LEN SZ_8M
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M)
-#define CONFIG_SYS_SDRAM_CLK 528
/*
* U-Boot general configurations
*/
#define CONFIG_SYS_LONGHELP
+#ifdef CONFIG_MX6Q
#define CONFIG_SYS_PROMPT "TX6Q U-Boot > "
+#else
+#define CONFIG_SYS_PROMPT "TX6DL U-Boot > "
+#endif
#define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */
#define CONFIG_FDT_FIXUP_PARTITIONS
#define CONFIG_OF_EMBED
#define CONFIG_OF_BOARD_SETUP
+#ifdef CONFIG_MX6Q
#define CONFIG_DEFAULT_DEVICE_TREE tx6q
#define CONFIG_ARCH_DEVICE_TREE mx6q
+#else
+#define CONFIG_DEFAULT_DEVICE_TREE tx6dl
+#define CONFIG_ARCH_DEVICE_TREE mx6dl
+#endif
#define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
#endif /* CONFIG_OF_LIBFDT */
#endif /* CONFIG_MFG */
/*
* Boot Linux
*/
-#define xstr(s) str(s)
-#define str(s) #s
+#define xstr(s) str(s)
+#define str(s) #s
#define __pfx(x, s) (x##s)
#define _pfx(x, s) __pfx(x, s)
"bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
" root=/dev/mtdblock3 rootfstype=jffs2\0" \
"bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
- " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\
+ " root=/dev/nfs ip=dhcp nfsroot=${nfs_server}:${nfsroot},nolock\0"\
"bootcmd_mmc=set autostart no;run bootargs_mmc;" \
"fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \
"bootcmd_nand=set autostart no;run bootargs_nand;" \
"nboot linux;run bootm_cmd\0" \
"bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
"run bootm_cmd\0" \
- "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \
+ "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
"cpu_clk=800\0" \
+ "bootdelay=-1\0" \
"default_bootargs=set bootargs " CONFIG_BOOTARGS \
" video=${video_mode} ${append_bootargs}\0" \
"fdtaddr=11000000\0" \
#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE 4
#endif
+#ifndef CONFIG_SYS_NAND_ERASE_SIZE
+#define CONFIG_SYS_NAND_ERASE_SIZE SZ_128K
+#endif
#define CONFIG_NAND_MXS
#define CONFIG_NAND_MXS_NO_BBM_SWAP
#define CONFIG_APBH_DMA
#define CONFIG_APBH_DMA_BURST
#define CONFIG_APBH_DMA_BURST8
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_ERASE_SIZE
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_SYS_MXS_DMA_CHANNEL 4
-#define CONFIG_SYS_MAX_FLASH_SECT 1024
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
#define CONFIG_ENV_SIZE SZ_128K
-#define CONFIG_ENV_RANGE 0x60000
+#define CONFIG_ENV_RANGE (3 * CONFIG_SYS_NAND_ERASE_SIZE)
#ifdef CONFIG_ENV_OFFSET_REDUND
-#define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_ENV_RANGE) \
+#define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_SYS_ENV_PART_SIZE) \
"(env)," \
- xstr(CONFIG_ENV_RANGE) \
+ xstr(CONFIG_SYS_ENV_PART_SIZE) \
"(env2),"
-#define CONFIG_SYS_USERFS_PART_STR "91520k(userfs)"
+#define CONFIG_SYS_USERFS_PART_STR xstr(CONFIG_SYS_USERFS_PART_SIZE) "(userfs)"
#else
-#define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_ENV_RANGE) \
+#define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_SYS_ENV_PART_SIZE) \
"(env),"
-#define CONFIG_SYS_USERFS_PART_STR "91904k(userfs)"
+#define CONFIG_SYS_USERFS_PART_STR xstr(CONFIG_SYS_USERFS_PART_SIZE2) "(userfs)"
#endif /* CONFIG_ENV_OFFSET_REDUND */
/*
#endif
#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
- "1m@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) "(u-boot)," \
+ xstr(CONFIG_SYS_U_BOOT_PART_SIZE) \
+ "@" xstr(CONFIG_SYS_U_BOOT_OFFSET) \
+ "(u-boot)," \
CONFIG_SYS_ENV_PART_STR \
- "4m(linux),32m(rootfs),256k(dtb)," \
- CONFIG_SYS_USERFS_PART_STR ",512k@0x7f80000(bbt)ro"
+ "4m(linux),32m(rootfs)," CONFIG_SYS_USERFS_PART_STR "," \
+ xstr(CONFIG_SYS_DTB_PART_SIZE) \
+ "(dtb)," \
+ xstr(CONFIG_SYS_NAND_BBT_SIZE) \
+ "@" xstr(CONFIG_SYS_NAND_BBT_OFFSET) "(bbt)ro"
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
projects / karo-tx-uboot.git / commitdiff