mxs: add delay after enabling ENET PLL

otherwise the first accesses to the PHY will fail

diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index 66d5169087140658859106b403077e9e41b9f2e0..bf29f0ae08b28e536f7c984bb0a68d592167d039 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -276,6 +276,7 @@ int cpu_eth_init(bd_t *bis)
        writel(CLKCTRL_PLL2CTRL0_CLKGATE,
                &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
 
+       udelay(6000);
        return 0;
 }
 #endif