Heiko Schocher <hs@denx.de>
+ cam_enc_4xx davinci/ARM926EJS
charon MPC5200
ids8247 MPC8247
jupiter MPC5200
Stefano Babic <sbabic@denx.de>
ea20 davinci
+ flea3 i.MX35
mx35pdk i.MX35
mx51evk i.MX51
polaris xscale/pxa
omap3_pandora ARM ARMV7 (OMAP3xx SoC)
+Michael Jones <michael.jones@matrix-vision.de>
+
+ omap3_mvblx ARM ARMV7 (OMAP3xx SoC)
+
Matthias Kaehlcke <matthias@kaehlcke.net>
edb9301 ARM920T (EP9301)
edb9302 ARM920T (EP9302)
davinci_dm365evm ARM926EJS
davinci_dm6467evm ARM926EJS
+Helmut Raiger <helmut.raiger@hale.at>
+
+ tt01 i.MX31
+
Linus Walleij <linus.walleij@linaro.org>
integratorap various
integratorcp various
$(obj)u-boot.dis: $(obj)u-boot
$(OBJDUMP) -d $< > $@
-$(obj)u-boot.ubl: $(obj)u-boot-nand.bin
+$(obj)u-boot.ubl: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-ubl.bin
$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
- -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
+ -e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-ubl.bin $(obj)u-boot.ubl
+ rm $(obj)u-boot-ubl.bin
+ rm $(obj)spl/u-boot-spl-pad.bin
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/')
ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')
-#########################################################################
-## Coldfire
-#########################################################################
-M52277EVB_config \
-M52277EVB_spansion_config \
-M52277EVB_stmicro_config : unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/freescale/m52277evb
- @case "$@" in \
- M52277EVB_config) FLASH=SPANSION;; \
- M52277EVB_spansion_config) FLASH=SPANSION;; \
- M52277EVB_stmicro_config) FLASH=STMICRO;; \
- esac; \
- if [ "$${FLASH}" = "SPANSION" ] ; then \
- echo "#define CONFIG_SYS_SPANSION_BOOT" >> $(obj)include/config.h ; \
- echo "CONFIG_SYS_TEXT_BASE = 0x00000000" > $(obj)board/freescale/m52277evb/config.tmp ; \
- fi; \
- if [ "$${FLASH}" = "STMICRO" ] ; then \
- echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
- echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \
- echo "CONFIG_SYS_TEXT_BASE = 0x43E00000" > $(obj)board/freescale/m52277evb/config.tmp ; \
- fi
- @$(MKCONFIG) -n $@ -a M52277EVB m68k mcf5227x m52277evb freescale
-
-M5235EVB_config \
-M5235EVB_Flash16_config \
-M5235EVB_Flash32_config: unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/freescale/m5235evb
- @case "$@" in \
- M5235EVB_config) FLASH=16;; \
- M5235EVB_Flash16_config) FLASH=16;; \
- M5235EVB_Flash32_config) FLASH=32;; \
- esac; \
- if [ "$${FLASH}" != "16" ] ; then \
- echo "#define NORFLASH_PS32BIT 1" >> $(obj)include/config.h ; \
- echo "CONFIG_SYS_TEXT_BASE = 0xFFC00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
- else \
- echo "CONFIG_SYS_TEXT_BASE = 0xFFE00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
- fi
- @$(MKCONFIG) -n $@ -a M5235EVB m68k mcf523x m5235evb freescale
-
-EB+MCF-EV123_config : unconfig
- @mkdir -p $(obj)board/BuS/EB+MCF-EV123
- @echo "CONFIG_SYS_TEXT_BASE = 0xFFE00000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
- @$(MKCONFIG) -n $@ EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
-
-EB+MCF-EV123_internal_config : unconfig
- @mkdir -p $(obj)board/BuS/EB+MCF-EV123
- @echo "CONFIG_SYS_TEXT_BASE = 0xF0000000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
- @$(MKCONFIG) -n $@ EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
-
-M54451EVB_config \
-M54451EVB_stmicro_config : unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/freescale/m54451evb
- @case "$@" in \
- M54451EVB_config) FLASH=NOR;; \
- M54451EVB_stmicro_config) FLASH=STMICRO;; \
- esac; \
- if [ "$${FLASH}" = "NOR" ] ; then \
- echo "CONFIG_SYS_TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54451evb/config.tmp ; \
- fi; \
- if [ "$${FLASH}" = "STMICRO" ] ; then \
- echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
- echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \
- echo "CONFIG_SYS_TEXT_BASE = 0x47E00000" > $(obj)board/freescale/m54451evb/config.tmp ; \
- fi; \
- echo "#define CONFIG_SYS_INPUT_CLKSRC 24000000" >> $(obj)include/config.h ;
- @$(MKCONFIG) -n $@ -a M54451EVB m68k mcf5445x m54451evb freescale
-
-M54455EVB_config \
-M54455EVB_atmel_config \
-M54455EVB_intel_config \
-M54455EVB_a33_config \
-M54455EVB_a66_config \
-M54455EVB_i33_config \
-M54455EVB_i66_config \
-M54455EVB_stm33_config : unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/freescale/m54455evb
- @case "$@" in \
- M54455EVB_config) FLASH=ATMEL; FREQ=33333333;; \
- M54455EVB_atmel_config) FLASH=ATMEL; FREQ=33333333;; \
- M54455EVB_intel_config) FLASH=INTEL; FREQ=33333333;; \
- M54455EVB_a33_config) FLASH=ATMEL; FREQ=33333333;; \
- M54455EVB_a66_config) FLASH=ATMEL; FREQ=66666666;; \
- M54455EVB_i33_config) FLASH=INTEL; FREQ=33333333;; \
- M54455EVB_i66_config) FLASH=INTEL; FREQ=66666666;; \
- M54455EVB_stm33_config) FLASH=STMICRO; FREQ=33333333;; \
- esac; \
- if [ "$${FLASH}" = "INTEL" ] ; then \
- echo "#define CONFIG_SYS_INTEL_BOOT" >> $(obj)include/config.h ; \
- echo "CONFIG_SYS_TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
- fi; \
- if [ "$${FLASH}" = "ATMEL" ] ; then \
- echo "#define CONFIG_SYS_ATMEL_BOOT" >> $(obj)include/config.h ; \
- echo "CONFIG_SYS_TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
- fi; \
- if [ "$${FLASH}" = "STMICRO" ] ; then \
- echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
- echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \
- echo "CONFIG_SYS_TEXT_BASE = 0x4FE00000" > $(obj)board/freescale/m54455evb/config.tmp ; \
- fi; \
- echo "#define CONFIG_SYS_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
- $(XECHO) "... with $${FREQ}Hz input clock"
- @$(MKCONFIG) -n $@ -a M54455EVB m68k mcf5445x m54455evb freescale
-
#========================================================================
# ARM
#========================================================================
CONFIG_RTC_MPC8xx - use internal RTC of MPC8xx
CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC
- CONFIG_RTC_MC13783 - use MC13783 RTC
+ CONFIG_RTC_MC13XXX - use MC13783 or MC13892 RTC
CONFIG_RTC_MC146818 - use MC146818 RTC
CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC
CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC
CONFIG_MXC_SPI
Enables the driver for the SPI controllers on i.MX and MXC
- SoCs. Currently only i.MX31 is supported.
+ SoCs. Currently i.MX31/35/51 are supported.
- FPGA Support: CONFIG_FPGA
that is executed before the actual U-Boot. E.g. when
compiling a NAND SPL.
+- CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+ define this, if you want to read first the oob data
+ and then the data. This is used for example on
+ davinci plattforms.
+
- CONFIG_USE_ARCH_MEMCPY
CONFIG_USE_ARCH_MEMSET
If these options are used a optimized version of memcpy/memset will
}
#endif
+#ifdef CONFIG_SYS_MX31_UART2
+void mx31_uart2_hw_init(void)
+{
+ /* setup pins for UART2 */
+ mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX);
+ mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX);
+ mx31_gpio_mux(MUX_RTS2__UART2_RTS_B);
+ mx31_gpio_mux(MUX_CTS2__UART2_CTS_B);
+}
+#endif
+
#ifdef CONFIG_MXC_SPI
+/*
+ * Note: putting several spi setups here makes no sense as they may differ
+ * at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3)
+ */
void mx31_spi2_hw_init(void)
{
/* SPI2 */
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
+#define IOMUXGPR (IOMUXC_BASE + 0x008)
+
static u32 mx31_decode_pll(u32 reg, u32 infreq)
{
u32 mfi = GET_PLL_MFI(reg);
}
+void mx31_set_gpr(enum iomux_gp_func gp, char en)
+{
+ u32 l;
+
+ l = readl(IOMUXGPR);
+ if (en)
+ l |= gp;
+ else
+ l &= ~gp;
+
+ writel(l, IOMUXGPR);
+}
+
void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
{
struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
""
);
+static char *get_reset_cause(void)
+{
+ /* read RCSR register from CCM module */
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ u32 cause = readl(&ccm->rcsr) & 0x0F;
+
+ switch (cause) {
+ case 0x0000:
+ return "POR";
+ case 0x0002:
+ return "JTAG";
+ case 0x0004:
+ return "RST";
+ case 0x0008:
+ return "WDOG";
+ default:
+ return "unknown reset";
+ }
+}
+
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
- printf("CPU: Freescale i.MX35 at %d MHz\n",
+ u32 srev = get_cpu_rev();
+
+ printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n",
+ (srev & 0xF0) >> 4, (srev & 0x0F),
get_mcu_main_clk() / 1000000);
- /* mxc_dump_clocks(); */
+
+ printf("Reset cause: %s\n", get_reset_cause());
+
return 0;
}
#endif
COBJS-$(CONFIG_SOC_DM646X) += dm646x.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o
+ifdef CONFIG_SPL_BUILD
+COBJS-y += spl.o
+COBJS-y += dm365_lowlevel.o
+endif
+
SOBJS = reset.o
ifndef CONFIG_SKIP_LOWLEVEL_INIT
return 8;
else
return pll_div(pllbase, PLLC_PREDIV);
+#elif defined(CONFIG_SOC_DM365)
+ return pll_div(pllbase, PLLC_PREDIV);
#endif
return 1;
}
static inline unsigned pll_postdiv(volatile void *pllbase)
{
-#ifdef CONFIG_SOC_DM355
+#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
return pll_div(pllbase, PLLC_POSTDIV);
#elif defined(CONFIG_SOC_DM6446)
if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
#endif
/* the PLL might be bypassed */
- if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
+ if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
base /= pll_prediv(pllbase);
+#if defined(CONFIG_SOC_DM365)
+ base *= 2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
+#else
base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
+#endif
base /= pll_postdiv(pllbase);
}
return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
/* REVISIT fetch and display CPU ID and revision information
* too ... that will matter as more revisions appear.
*/
+#if defined(CONFIG_SOC_DM365)
+ printf("Cores: ARM %d MHz",
+ pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV));
+#else
printf("Cores: ARM %d MHz",
pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
+#endif
#ifdef DSP_PLLDIV
printf(", DSP %d MHz",
printf("\nDDR: %d MHz\n",
/* DDR PHY uses an x2 input clock */
+#if defined(CONFIG_SOC_DM365)
+ pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV)
+ / 2);
+#else
pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
/ 2);
+#endif
return 0;
}
return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
}
#endif
+
+#if defined(CONFIG_SOC_DM365)
+unsigned int davinci_clk_get(unsigned int div)
+{
+ return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
+}
+#endif
#endif /* CONFIG_DISPLAY_CPUINFO */
#endif /* !CONFIG_SOC_DA8XX */
--- /dev/null
+/*
+ * SoC-specific lowlevel code for tms320dm365 and similar chips
+ * Actually used for booting from NAND with nand_spl.
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+#include <nand.h>
+#include <ns16550.h>
+#include <post.h>
+#include <asm/arch/dm365_lowlevel.h>
+#include <asm/arch/hardware.h>
+
+void dm365_waitloop(unsigned long loopcnt)
+{
+ unsigned long i;
+
+ for (i = 0; i < loopcnt; i++)
+ asm(" NOP");
+}
+
+int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
+{
+ unsigned int clksrc = 0x0;
+
+ /* Power up the PLL */
+ clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
+
+ clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
+ setbits_le32(&dv_pll0_regs->pllctl, clksrc << 8);
+
+ /*
+ * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
+ * through MMR
+ */
+ clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
+
+ /* Set PLLEN=0 => PLL BYPASS MODE */
+ clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
+
+ dm365_waitloop(150);
+
+ /* PLLRST=1(reset assert) */
+ setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
+
+ dm365_waitloop(300);
+
+ /*Bring PLL out of Reset*/
+ clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
+
+ /* Program the Multiper and Pre-Divider for PLL1 */
+ writel(pllmult, &dv_pll0_regs->pllm);
+ writel(prediv, &dv_pll0_regs->prediv);
+
+ /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
+ writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
+ PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
+ /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
+ writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
+ &dv_pll0_regs->secctl);
+ /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
+ writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
+ /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
+ writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
+
+ /* Program the PostDiv for PLL1 */
+ writel(0x8000, &dv_pll0_regs->postdiv);
+
+ /* Post divider setting for PLL1 */
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
+ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
+
+ dm365_waitloop(300);
+
+ /* Set the GOSET bit */
+ writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
+
+ dm365_waitloop(300);
+
+ /* Wait for PLL to LOCK */
+ while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
+ == PLL0_LOCK))
+ ;
+
+ /* Enable the PLL Bit of PLLCTL*/
+ setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
+
+ return 0;
+}
+
+int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
+{
+ unsigned int clksrc = 0x0;
+
+ /* Power up the PLL*/
+ clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
+
+ /*
+ * Select the Clock Mode as Onchip Oscilator or External Clock on
+ * MXI pin
+ * VDB has input on MXI pin
+ */
+ clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
+ setbits_le32(&dv_pll1_regs->pllctl, clksrc << 8);
+
+ /*
+ * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
+ * through MMR
+ */
+ clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
+
+ /* Set PLLEN=0 => PLL BYPASS MODE */
+ clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
+
+ dm365_waitloop(50);
+
+ /* PLLRST=1(reset assert) */
+ setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
+
+ dm365_waitloop(300);
+
+ /* Bring PLL out of Reset */
+ clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
+
+ /* Program the Multiper and Pre-Divider for PLL2 */
+ writel(pllm, &dv_pll1_regs->pllm);
+ writel(prediv, &dv_pll1_regs->prediv);
+
+ writel(0x8000, &dv_pll1_regs->postdiv);
+
+ /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
+ writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
+ PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
+ /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
+ writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
+ &dv_pll1_regs->secctl);
+ /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
+ writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
+ /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
+ writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
+
+ /* Post divider setting for PLL2 */
+ writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
+ writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
+ writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
+ writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
+ writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
+
+ /* GoCmd for PostDivider to take effect */
+ writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
+
+ dm365_waitloop(150);
+
+ /* Wait for PLL to LOCK */
+ while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
+ == PLL1_LOCK))
+ ;
+
+ dm365_waitloop(4100);
+
+ /* Enable the PLL2 */
+ setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
+
+ /* do this after PLL's have been set up */
+ writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
+ &dv_sys_module_regs->peri_clkctl);
+
+ return 0;
+}
+
+int dm365_ddr_setup(void)
+{
+ lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+ clrbits_le32(&dv_sys_module_regs->vtpiocr,
+ VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
+
+ /* Set bit CLRZ (bit 13) */
+ setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
+
+ /* Check VTP READY Status */
+ while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
+ ;
+
+ /* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
+ setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
+
+ /* Set bit LOCK(bit7) */
+ setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
+
+ /*
+ * Powerdown VTP as it is locked (bit 6)
+ * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
+ */
+ setbits_le32(&dv_sys_module_regs->vtpiocr,
+ VPTIO_IOPWRDN | VPTIO_PWRDN);
+
+ /* Wait for calibration to complete */
+ dm365_waitloop(150);
+
+ /* Set the DDR2 to synreset, then enable it again */
+ lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
+ lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+ writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
+
+ /* Program SDRAM Bank Config Register */
+ writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
+ &dv_ddr2_regs_ctrl->sdbcr);
+ writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
+ &dv_ddr2_regs_ctrl->sdbcr);
+
+ /* Program SDRAM Timing Control Register1 */
+ writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
+ /* Program SDRAM Timing Control Register2 */
+ writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
+
+ writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
+
+ writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
+
+ /* Program SDRAM Refresh Control Register */
+ writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
+
+ lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
+ lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+ return 0;
+}
+
+void dm365_vpss_sync_reset(void)
+{
+ unsigned int PdNum = 0;
+
+ /* VPSS_CLKMD 1:1 */
+ setbits_le32(&dv_sys_module_regs->vpss_clkctl,
+ VPSS_CLK_CTL_VPSS_CLKMD);
+
+ /* LPSC SyncReset DDR Clock Enable */
+ writel(((readl(&dv_psc_regs->mdctl[47]) & ~PSC_MD_STATE_MSK) |
+ PSC_SYNCRESET), &dv_psc_regs->mdctl[47]);
+
+ writel((1 << PdNum), &dv_psc_regs->ptcmd);
+
+ while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
+ ;
+ while (!((readl(&dv_psc_regs->mdstat[47]) & PSC_MD_STATE_MSK) ==
+ PSC_SYNCRESET))
+ ;
+}
+
+void dm365_por_reset(void)
+{
+ if (readl(&dv_pll0_regs->rstype) & 3)
+ dm365_vpss_sync_reset();
+}
+
+void dm365_psc_init(void)
+{
+ unsigned char i = 0;
+ unsigned char lpsc_start;
+ unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
+ unsigned int PdNum = 0;
+
+ lpscmin = 0;
+ lpscmax = 2;
+
+ for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
+ if (lpscgroup == 0) {
+ lpsc_start = 0; /* Enabling LPSC 3 to 28 SCR first */
+ lpsc_end = 28;
+ } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
+ lpsc_start = 38;
+ lpsc_end = 47;
+ } else {
+ lpsc_start = 50;
+ lpsc_end = 51;
+ }
+
+ /* NEXT=0x3, Enable LPSC's */
+ for (i = lpsc_start; i <= lpsc_end; i++)
+ setbits_le32(&dv_psc_regs->mdctl[i], 0x3);
+
+ /*
+ * Program goctl to start transition sequence for LPSCs
+ * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
+ * Domain 0 Modules
+ */
+ writel((1 << PdNum), &dv_psc_regs->ptcmd);
+
+ /*
+ * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
+ */
+ while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
+ == 0))
+ ;
+
+ /* Wait for MODSTAT = ENABLE from LPSC's */
+ for (i = lpsc_start; i <= lpsc_end; i++)
+ while (!((readl(&dv_psc_regs->mdstat[i]) &
+ PSC_MD_STATE_MSK) == 0x3))
+ ;
+ }
+}
+
+static void dm365_emif_init(void)
+{
+ writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
+ writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
+
+ setbits_le32(&davinci_emif_regs->nandfcr, 1);
+
+ writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
+
+ return;
+}
+
+void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
+ unsigned long value)
+{
+ clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
+ setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
+}
+
+__attribute__((weak))
+void board_gpio_init(void)
+{
+ return;
+}
+
+#if defined(CONFIG_POST)
+int post_log(char *format, ...)
+{
+ return 0;
+}
+#endif
+
+void dm36x_lowlevel_init(ulong bootflag)
+{
+ /*
+ * copied from arch/arm/cpu/arm926ejs/start.S
+ *
+ * flush v4 I/D caches
+ */
+ asm("mov r0, #0");
+ asm("mcr p15, 0, r0, c7, c7, 0"); /* flush v3/v4 cache */
+ asm("mcr p15, 0, r0, c8, c7, 0"); /* flush v4 TLB */
+
+ /*
+ * disable MMU stuff and caches
+ */
+ asm("mrc p15, 0, r0, c1, c0, 0");
+ /* clear bits 13, 9:8 (--V- --RS) */
+ asm("bic r0, r0, #0x00002300");
+ /* clear bits 7, 2:0 (B--- -CAM) */
+ asm("bic r0, r0, #0x00000087");
+ /* set bit 2 (A) Align */
+ asm("orr r0, r0, #0x00000002");
+ /* set bit 12 (I) I-Cache */
+ asm("orr r0, r0, #0x00001000");
+ asm("mcr p15, 0, r0, c1, c0, 0");
+
+ /* Mask all interrupts */
+ writel(0x04, &dv_aintc_regs->intctl);
+ writel(0x0, &dv_aintc_regs->eabase);
+ writel(0x0, &dv_aintc_regs->eint0);
+ writel(0x0, &dv_aintc_regs->eint1);
+
+ /* Clear all interrupts */
+ writel(0xffffffff, &dv_aintc_regs->fiq0);
+ writel(0xffffffff, &dv_aintc_regs->fiq1);
+ writel(0xffffffff, &dv_aintc_regs->irq0);
+ writel(0xffffffff, &dv_aintc_regs->irq1);
+
+ /* System PSC setup - enable all */
+ dm365_psc_init();
+
+ /* Setup Pinmux */
+ dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
+ dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
+ dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
+ dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
+ dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
+
+ /* PLL setup */
+ dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
+ CONFIG_SYS_DM36x_PLL1_PREDIV);
+ dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
+ CONFIG_SYS_DM36x_PLL2_PREDIV);
+
+ /* GPIO setup */
+ board_gpio_init();
+
+ NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
+ CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
+ /*
+ * Fix Power and Emulation Management Register
+ * see sprufh2.pdf page 38 Table 22
+ */
+ writel(0x0000e003, (CONFIG_SYS_NS16550_COM1 + 0x30));
+ puts("ddr init\n");
+ dm365_ddr_setup();
+
+ puts("emif init\n");
+ dm365_emif_init();
+
+#if defined(CONFIG_POST)
+ /*
+ * Do memory tests, calls arch_memory_failure_handle()
+ * if error detected.
+ */
+ memory_post_test(0);
+#endif
+}
*/
/* Works on Always On power domain only (no PD argument) */
-void lpsc_on(unsigned int id)
+static void lpsc_transition(unsigned int id, unsigned int state)
{
dv_reg_p mdstat, mdctl, ptstat, ptcmd;
#ifdef CONFIG_SOC_DA8XX
while (readl(ptstat) & 0x01)
continue;
- if ((readl(mdstat) & PSC_MDSTAT_STATE) == 0x03)
- return; /* Already on and enabled */
+ if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
+ return; /* Already in that state */
- writel(readl(mdctl) | 0x03, mdctl);
+ writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
switch (id) {
#ifdef CONFIG_SOC_DM644X
while (readl(ptstat) & 0x01)
continue;
- while ((readl(mdstat) & PSC_MDSTAT_STATE) != 0x03)
+ while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
continue;
}
+void lpsc_on(unsigned int id)
+{
+ lpsc_transition(id, 0x03);
+}
+
+void lpsc_syncreset(unsigned int id)
+{
+ lpsc_transition(id, 0x01);
+}
+
/* Not all DaVinci chips have a DSP power domain. */
#ifdef CONFIG_SOC_DM644X
--- /dev/null
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <nand.h>
+#include <asm/arch/dm365_lowlevel.h>
+#include <ns16550.h>
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), '\r');
+
+ NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
+}
+
+inline void hang(void)
+{
+ puts("### ERROR ### Please RESET the board ###\n");
+ for (;;)
+ ;
+}
+
+void board_init_f(ulong dummy)
+{
+ dm36x_lowlevel_init(0);
+ relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE);
+}
+
+void board_init_r(gd_t *id, ulong dummy)
+{
+
+ nand_init();
+ puts("Nand boot...\n");
+ nand_boot();
+}
.globl _TEXT_BASE
_TEXT_BASE:
+#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
.word CONFIG_SYS_TEXT_BASE
+#else
+#ifdef CONFIG_SPL_BUILD
+ .word CONFIG_SPL_TEXT_BASE
+#else
+ .word CONFIG_SYS_TEXT_BASE
+#endif
+#endif
/*
* These are defined in the board-specific linker script.
_end_ofs:
.word _end - _start
+#ifdef CONFIG_NAND_U_BOOT
+.globl _end
+_end:
+ .word __bss_end__
+#endif
+
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
+#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
+ ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+#else
+#ifdef CONFIG_SPL_BUILD
+ ldr sp, =(CONFIG_SPL_STACK)
+#else
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+#endif
+#endif
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
mov sp, r4
adr r0, _start
+ sub r9, r6, r0 /* r9 <- relocation offset */
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy loop */
#endif
clear_bss:
-#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_BUILD
+ /* No relocation for SPL */
+ ldr r0, =__bss_start
+ ldr r1, =__bss_end__
+#else
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
+#endif
mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */
cmp r0, r1
bne clbss_l
+#ifndef CONFIG_SPL_BUILD
bl coloured_LED_init
bl red_led_on
#endif
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
+#else
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ ldr r1, =0x0
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+ str r1, [r0, #CLKCTL_CCGR7]
+
+ ldr r1, =0x00030000
+ str r1, [r0, #CLKCTL_CCGR4]
+ ldr r1, =0x00FFF030
+ str r1, [r0, #CLKCTL_CCGR5]
+ ldr r1, =0x0F00030F
+ str r1, [r0, #CLKCTL_CCGR6]
#endif
/* Switch ARM to step clock */
serial_init(); /* serial communications setup */
+ gd->have_console = 1;
+
/* Avoid a second "U-Boot" coming from this string */
u_boot_rev = &u_boot_rev[7];
#define _SYS_PROTO_H_
#define BOARD_REV_ID 0x0
-struct {
- u32 board_type_v1;
- u32 board_type_v2;
- u32 mtype;
- char *board_string;
- char *nand_string;
-} board_sysinfo;
u32 get_cpu_rev(void);
u32 get_sysboot_value(void);
#include <asm/arch/armada100.h>
#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+/* default Dcache Line length for armada100 */
+#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
--- /dev/null
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DV_AINTC_DEFS_H_
+#define _DV_AINTC_DEFS_H_
+
+struct dv_aintc_regs {
+ unsigned int fiq0; /* 0x00 */
+ unsigned int fiq1; /* 0x04 */
+ unsigned int irq0; /* 0x08 */
+ unsigned int irq1; /* 0x0c */
+ unsigned int fiqentry; /* 0x10 */
+ unsigned int irqentry; /* 0x14 */
+ unsigned int eint0; /* 0x18 */
+ unsigned int eint1; /* 0x1c */
+ unsigned int intctl; /* 0x20 */
+ unsigned int eabase; /* 0x24 */
+ unsigned char rsvd0[8]; /* 0x28 */
+ unsigned int intpri0; /* 0x30 */
+ unsigned int intpri1; /* 0x34 */
+ unsigned int intpri2; /* 0x38 */
+ unsigned int intpri3; /* 0x3c */
+ unsigned int intpri4; /* 0x40 */
+ unsigned int intpri5; /* 0x44 */
+ unsigned int intpri6; /* 0x48 */
+ unsigned int intpri7; /* 0x4c */
+};
+
+#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
+
+#endif /* _DV_AINTC_DEFS_H_ */
--- /dev/null
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2008-2009 MontaVista Software Inc.
+ * Copyright (C) 2008-2009 Texas Instruments Inc
+ *
+ * Based on the LCD driver for TI Avalanche processors written by
+ * Ajay Singh and Shalom Hai.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef DA8XX_FB_H
+#define DA8XX_FB_H
+
+enum panel_type {
+ QVGA = 0
+};
+
+enum panel_shade {
+ MONOCHROME = 0,
+ COLOR_ACTIVE,
+ COLOR_PASSIVE,
+};
+
+enum raster_load_mode {
+ LOAD_DATA = 1,
+ LOAD_PALETTE,
+};
+
+struct display_panel {
+ enum panel_type panel_type; /* QVGA */
+ int max_bpp;
+ int min_bpp;
+ enum panel_shade panel_shade;
+};
+
+struct da8xx_panel {
+ const char name[25]; /* Full name <vendor>_<model> */
+ unsigned short width;
+ unsigned short height;
+ int hfp; /* Horizontal front porch */
+ int hbp; /* Horizontal back porch */
+ int hsw; /* Horizontal Sync Pulse Width */
+ int vfp; /* Vertical front porch */
+ int vbp; /* Vertical back porch */
+ int vsw; /* Vertical Sync Pulse Width */
+ unsigned int pxl_clk; /* Pixel clock */
+ unsigned char invert_pxl_clk; /* Invert Pixel clock */
+};
+
+struct da8xx_lcdc_platform_data {
+ const char manu_name[10];
+ void *controller_data;
+ const char type[25];
+ void (*panel_power_ctrl)(int);
+};
+
+struct lcd_ctrl_config {
+ const struct display_panel *p_disp_panel;
+
+ /* AC Bias Pin Frequency */
+ int ac_bias;
+
+ /* AC Bias Pin Transitions per Interrupt */
+ int ac_bias_intrpt;
+
+ /* DMA burst size */
+ int dma_burst_sz;
+
+ /* Bits per pixel */
+ int bpp;
+
+ /* FIFO DMA Request Delay */
+ int fdd;
+
+ /* TFT Alternative Signal Mapping (Only for active) */
+ unsigned char tft_alt_mode;
+
+ /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
+ unsigned char stn_565_mode;
+
+ /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
+ unsigned char mono_8bit_mode;
+
+ /* Invert line clock */
+ unsigned char invert_line_clock;
+
+ /* Invert frame clock */
+ unsigned char invert_frm_clock;
+
+ /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
+ unsigned char sync_edge;
+
+ /* Horizontal and Vertical Sync: Control: 0=ignore */
+ unsigned char sync_ctrl;
+
+ /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
+ unsigned char raster_order;
+};
+
+struct lcd_sync_arg {
+ int back_porch;
+ int front_porch;
+ int pulse_width;
+};
+
+void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel);
+
+#endif /* ifndef DA8XX_FB_H */
+
--- /dev/null
+/*
+ * SoC-specific lowlevel code for tms320dm365 and similar chips
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __DM365_LOWLEVEL_H
+#define __DM365_LOWLEVEL_H
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+void dm365_waitloop(unsigned long loopcnt);
+int dm365_pll1_init(unsigned long pllmult, unsigned long prediv);
+int dm365_pll2_init(unsigned long pllm, unsigned long prediv);
+int dm365_ddr_setup(void);
+void dm365_por_reset(void);
+void dm365_psc_init(void);
+void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
+ unsigned long value);
+void dm36x_lowlevel_init(ulong bootflag);
+
+#endif /* #ifndef __DM365_LOWLEVEL_H */
#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
#define DAVINCI_UART0_BASE (0x01c20000)
#define DAVINCI_UART1_BASE (0x01c20400)
+#define DAVINCI_TIMER3_BASE (0x01c20800)
#define DAVINCI_I2C_BASE (0x01c21000)
#define DAVINCI_TIMER0_BASE (0x01c21400)
#define DAVINCI_TIMER1_BASE (0x01c21800)
#define DAVINCI_PWM0_BASE (0x01c22000)
#define DAVINCI_PWM1_BASE (0x01c22400)
#define DAVINCI_PWM2_BASE (0x01c22800)
+#define DAVINCI_TIMER4_BASE (0x01c23800)
#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
#define DAVINCI_MMC_SD1_BASE 0x01d00000
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
#define DAVINCI_MMC_SD0_BASE 0x01d11000
+#define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000
+#define DAVINCI_SPI0_BASE 0x01c66000
+#define DAVINCI_SPI1_BASE 0x01c66800
#elif defined(CONFIG_SOC_DM646X)
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
#define DAVINCI_INTC_BASE 0xfffee000
#define DAVINCI_BOOTCFG_BASE 0x01c14000
+#define DAVINCI_LCD_CNTL_BASE 0x01e13000
#define DAVINCI_L3CBARAM_BASE 0x80000000
#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
#define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24)
#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
+#define GPIO_BANK6_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x88)
+#define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c)
+#define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90)
+#define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94)
#endif /* CONFIG_SOC_DA8XX */
/* Power and Sleep Controller (PSC) Domains */
#endif /* CONFIG_SOC_DA8XX */
void lpsc_on(unsigned int id);
+void lpsc_syncreset(unsigned int id);
void dsp_on(void);
void davinci_enable_uart0(void);
#endif /* CONFIG_SOC_DA8XX */
#define PSC_MDSTAT_STATE 0x3f
+#define PSC_MDCTL_NEXT 0x07
#ifndef CONFIG_SOC_DA8XX
dv_reg rsvd[13];
dv_reg kick0;
dv_reg kick1;
- dv_reg rsvd1[56];
+ dv_reg rsvd1[53];
+ dv_reg mstpri[3];
dv_reg pinmux[20];
dv_reg suspsrc;
dv_reg chipsig;
#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
-#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
+#define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18)
#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
struct davinci_syscfg1_regs {
#endif /* CONFIG_SOC_DA8XX */
+#if defined(CONFIG_SOC_DM365)
+#include <asm/arch/aintc_defs.h>
+#include <asm/arch/ddr2_defs.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pll_defs.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/syscfg_defs.h>
+#include <asm/arch/timer_defs.h>
+#endif
#endif /* __ASM_ARCH_HARDWARE_H */
--- /dev/null
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DV_PLL_DEFS_H_
+#define _DV_PLL_DEFS_H_
+
+struct dv_pll_regs {
+ unsigned int pid; /* 0x00 */
+ unsigned char rsvd0[224]; /* 0x04 */
+ unsigned int rstype; /* 0xe4 */
+ unsigned char rsvd1[24]; /* 0xe8 */
+ unsigned int pllctl; /* 0x100 */
+ unsigned char rsvd2[4]; /* 0x104 */
+ unsigned int secctl; /* 0x108 */
+ unsigned int rv; /* 0x10c */
+ unsigned int pllm; /* 0x110 */
+ unsigned int prediv; /* 0x114 */
+ unsigned int plldiv1; /* 0x118 */
+ unsigned int plldiv2; /* 0x11c */
+ unsigned int plldiv3; /* 0x120 */
+ unsigned int oscdiv1; /* 0x124 */
+ unsigned int postdiv; /* 0x128 */
+ unsigned int bpdiv; /* 0x12c */
+ unsigned char rsvd5[8]; /* 0x130 */
+ unsigned int pllcmd; /* 0x138 */
+ unsigned int pllstat; /* 0x13c */
+ unsigned int alnctl; /* 0x140 */
+ unsigned int dchange; /* 0x144 */
+ unsigned int cken; /* 0x148 */
+ unsigned int ckstat; /* 0x14c */
+ unsigned int systat; /* 0x150 */
+ unsigned char rsvd6[12]; /* 0x154 */
+ unsigned int plldiv4; /* 0x160 */
+ unsigned int plldiv5; /* 0x164 */
+ unsigned int plldiv6; /* 0x168 */
+ unsigned int plldiv7; /* 0x16C */
+ unsigned int plldiv8; /* 0x170 */
+ unsigned int plldiv9; /* 0x174 */
+};
+
+#define PLLCTL_PLLEN (1 << 0)
+#define PLLCTL_PLLPWRDN (1 << 1)
+#define PLLCTL_PLLRST (1 << 3)
+#define PLLCTL_PLLENSRC (1 << 5)
+#define PLLCTL_RES_9 (1 << 8)
+
+#define PLLSECCTL_TINITZ (1 << 16)
+#define PLLSECCTL_TENABLE (1 << 17)
+#define PLLSECCTL_TENABLEDIV (1 << 18)
+#define PLLSECCTL_STOPMODE (1 << 22)
+
+#define PLLCMD_GOSET (1 << 0)
+
+#define PLL0_LOCK 0x07000000
+#define PLL1_LOCK 0x07000000
+
+#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
+
+#define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2))
+#define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7))
+#define SPI_PLLDIV (offsetof(struct dv_pll_regs, plldiv4))
+
+unsigned int davinci_clk_get(unsigned int div);
+#endif /* _DV_PLL_DEFS_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DV_PSC_DEFS_H_
+#define _DV_PSC_DEFS_H_
+
+/*
+ * Power/Sleep Ctrl Register structure
+ * See sprufb3.pdf, Chapter 7
+ */
+struct dv_psc_regs {
+ unsigned int pid; /* 0x000 */
+ unsigned char rsvd0[16]; /* 0x004 */
+ unsigned char rsvd1[4]; /* 0x014 */
+ unsigned int inteval; /* 0x018 */
+ unsigned char rsvd2[36]; /* 0x01C */
+ unsigned int merrpr0; /* 0x040 */
+ unsigned int merrpr1; /* 0x044 */
+ unsigned char rsvd3[8]; /* 0x048 */
+ unsigned int merrcr0; /* 0x050 */
+ unsigned int merrcr1; /* 0x054 */
+ unsigned char rsvd4[8]; /* 0x058 */
+ unsigned int perrpr; /* 0x060 */
+ unsigned char rsvd5[4]; /* 0x064 */
+ unsigned int perrcr; /* 0x068 */
+ unsigned char rsvd6[4]; /* 0x06C */
+ unsigned int epcpr; /* 0x070 */
+ unsigned char rsvd7[4]; /* 0x074 */
+ unsigned int epccr; /* 0x078 */
+ unsigned char rsvd8[144]; /* 0x07C */
+ unsigned char rsvd9[20]; /* 0x10C */
+ unsigned int ptcmd; /* 0x120 */
+ unsigned char rsvd10[4]; /* 0x124 */
+ unsigned int ptstat; /* 0x128 */
+ unsigned char rsvd11[212]; /* 0x12C */
+ unsigned int pdstat0; /* 0x200 */
+ unsigned int pdstat1; /* 0x204 */
+ unsigned char rsvd12[248]; /* 0x208 */
+ unsigned int pdctl0; /* 0x300 */
+ unsigned int pdctl1; /* 0x304 */
+ unsigned char rsvd13[536]; /* 0x308 */
+ unsigned int mckout0; /* 0x520 */
+ unsigned int mckout1; /* 0x524 */
+ unsigned char rsvd14[728]; /* 0x528 */
+ unsigned int mdstat[52]; /* 0x800 */
+ unsigned char rsvd15[304]; /* 0x8D0 */
+ unsigned int mdctl[52]; /* 0xA00 */
+};
+
+/* PSC constants */
+#define EMURSTIE_MASK (0x00000200)
+
+#define PD0 (0)
+
+#define PSC_ENABLE (0x3)
+#define PSC_DISABLE (0x2)
+#define PSC_SYNCRESET (0x1)
+#define PSC_SWRSTDISABLE (0x0)
+
+#define PSC_GOSTAT (1 << 0)
+#define PSC_MD_STATE_MSK (0x1f)
+
+#define PSC_CMD_GO (1 << 0)
+
+#define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE)
+
+#endif /* _DV_PSC_DEFS_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DV_SYSCFG_DEFS_H_
+#define _DV_SYSCFG_DEFS_H_
+
+#ifndef CONFIG_SOC_DA8XX
+/* System Control Module register structure for DM365 */
+struct dv_sys_module_regs {
+ unsigned int pinmux[5]; /* 0x00 */
+ unsigned int bootcfg; /* 0x14 */
+ unsigned int arm_intmux; /* 0x18 */
+ unsigned int edma_evtmux; /* 0x1C */
+ unsigned int ddr_slew; /* 0x20 */
+ unsigned int clkout; /* 0x24 */
+ unsigned int device_id; /* 0x28 */
+ unsigned int vdac_config; /* 0x2C */
+ unsigned int timer64_ctl; /* 0x30 */
+ unsigned int usbbphy_ctl; /* 0x34 */
+ unsigned int misc; /* 0x38 */
+ unsigned int mstpri[2]; /* 0x3C */
+ unsigned int vpss_clkctl; /* 0x44 */
+ unsigned int peri_clkctl; /* 0x48 */
+ unsigned int deepsleep; /* 0x4C */
+ unsigned int dft_enable; /* 0x50 */
+ unsigned int debounce[8]; /* 0x54 */
+ unsigned int vtpiocr; /* 0x74 */
+ unsigned int pupdctl0; /* 0x78 */
+ unsigned int pupdctl1; /* 0x7C */
+ unsigned int hdimcopbt; /* 0x80 */
+ unsigned int pll0_config; /* 0x84 */
+ unsigned int pll1_config; /* 0x88 */
+};
+
+#define VPTIO_RDY (1 << 15)
+#define VPTIO_IOPWRDN (1 << 14)
+#define VPTIO_CLRZ (1 << 13)
+#define VPTIO_LOCK (1 << 7)
+#define VPTIO_PWRDN (1 << 6)
+
+#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7)
+
+#define dv_sys_module_regs \
+ ((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE)
+
+#endif /* !CONFIG_SOC_DA8XX */
+#endif /* _DV_SYSCFG_DEFS_H_ */
#include <asm/arch/kirkwood.h>
#define CONFIG_ARM926EJS 1 /* Basic Architecture */
-
+#define CONFIG_SYS_CACHELINE_SIZE 32
+ /* default Dcache Line length for kirkwood */
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
extern u32 imx_get_uartclk(void);
extern void mx31_gpio_mux(unsigned long mode);
extern void mx31_set_pad(enum iomux_pins pin, u32 config);
+extern void mx31_set_gpr(enum iomux_gp_func gp, char en);
void mx31_uart1_hw_init(void);
+void mx31_uart2_hw_init(void);
void mx31_spi2_hw_init(void);
void mxc_hw_watchdog_enable(void);
void mxc_hw_watchdog_reset(void);
MX31_PIN_CAPTURE = IOMUX_PIN(7, 327),
};
+/*
+ * various IOMUX general purpose functions
+ */
+enum iomux_gp_func {
+ MUX_PGP_FIRI = 1 << 0,
+ MUX_DDR_MODE = 1 << 1,
+ MUX_PGP_CSPI_BB = 1 << 2,
+ MUX_PGP_ATA_1 = 1 << 3,
+ MUX_PGP_ATA_2 = 1 << 4,
+ MUX_PGP_ATA_3 = 1 << 5,
+ MUX_PGP_ATA_4 = 1 << 6,
+ MUX_PGP_ATA_5 = 1 << 7,
+ MUX_PGP_ATA_6 = 1 << 8,
+ MUX_PGP_ATA_7 = 1 << 9,
+ MUX_PGP_ATA_8 = 1 << 10,
+ MUX_PGP_UH2 = 1 << 11,
+ MUX_SDCTL_CSD0_SEL = 1 << 12,
+ MUX_SDCTL_CSD1_SEL = 1 << 13,
+ MUX_CSPI1_UART3 = 1 << 14,
+ MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
+ MUX_TAMPER_DETECT_EN = 1 << 16,
+ MUX_PGP_USB_4WIRE = 1 << 17,
+ MUX_PGP_USB_COMMON = 1 << 18,
+ MUX_SDHC_MEMSTICK1 = 1 << 19,
+ MUX_SDHC_MEMSTICK2 = 1 << 20,
+ MUX_PGP_SPLL_BYP = 1 << 21,
+ MUX_PGP_UPLL_BYP = 1 << 22,
+ MUX_PGP_MSHC1_CLK_SEL = 1 << 23,
+ MUX_PGP_MSHC2_CLK_SEL = 1 << 24,
+ MUX_CSPI3_UART5_SEL = 1 << 25,
+ MUX_PGP_ATA_9 = 1 << 26,
+ MUX_PGP_USB_SUSPEND = 1 << 27,
+ MUX_PGP_USB_OTG_LOOPBACK = 1 << 28,
+ MUX_PGP_USB_HS1_LOOPBACK = 1 << 29,
+ MUX_PGP_USB_HS2_LOOPBACK = 1 << 30,
+ MUX_CLKO_DDR_MODE = 1 << 31,
+};
+
/* Bit definitions for RCSR register in CCM */
#define CCM_RCSR_NF16B (1 << 31)
#define CCM_RCSR_NFMS (1 << 30)
struct mx31_weim_cscr cscr[6];
};
+/* ESD control registers */
+struct esdc_regs {
+ u32 ctl0;
+ u32 cfg0;
+ u32 ctl1;
+ u32 cfg1;
+ u32 misc;
+ u32 dly[5];
+ u32 dlyl;
+};
+
#endif
#define __REG(x) (*((volatile u32 *)(x)))
#define ESDCTL_BL(x) ((x) << 7)
#define ESDCTL_PRCT(x) ((x) << 0)
+#define ESDCTL_BASE_ADDR 0xB8001000
+
/* 13 fields of the upper CS control register */
#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
cnc, wsc, ew, wws, edc) \
/* Register offsets based on IOMUXC_BASE */
/* 0x00 .. 0x7b */
+#define MUX_CTL_CSPI3_MISO 0x0c
+#define MUX_CTL_CSPI3_SCLK 0x0d
+#define MUX_CTL_CSPI3_SPI_RDY 0x0e
+#define MUX_CTL_CSPI3_MOSI 0x13
+
#define MUX_CTL_USBH2_DATA1 0x40
#define MUX_CTL_USBH2_DIR 0x44
#define MUX_CTL_USBH2_STP 0x45
#define MUX_CTL_USBH2_NXT 0x46
#define MUX_CTL_USBH2_DATA0 0x47
#define MUX_CTL_USBH2_CLK 0x4B
+
+#define MUX_CTL_TXD2 0x70
+#define MUX_CTL_RTS2 0x71
+#define MUX_CTL_CTS2 0x72
+#define MUX_CTL_RXD2 0x77
+
#define MUX_CTL_RTS1 0x7c
#define MUX_CTL_CTS1 0x7d
#define MUX_CTL_DTR_DCE1 0x7e
#define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
#define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
+#define MUX_RXD2__UART2_RXD_MUX IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC)
+#define MUX_TXD2__UART2_TXD_MUX IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC)
+#define MUX_RTS2__UART2_RTS_B IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC)
+#define MUX_CTS2__UART2_CTS_B IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC)
+
#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
#define PLL_MFI(x) (((x) & 0xf) << 10)
#define PLL_MFN(x) (((x) & 0x3ff) << 0)
+#define _PLL_BRM(x) ((x) << 31)
+#define _PLL_PD(x) (((x) - 1) << 26)
+#define _PLL_MFD(x) (((x) - 1) << 16)
+#define _PLL_MFI(x) ((x) << 10)
+#define _PLL_MFN(x) (x)
+#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
+ (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
+ _PLL_MFN(mfn))
+
+#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1)
+#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
+#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
+
#define CSCR_U(x) (WEIM_CTRL_CS#x + 0)
#define CSCR_L(x) (WEIM_CTRL_CS#x + 4)
#define CSCR_A(x) (WEIM_CTRL_CS#x + 8)
u16 wmcr; /* Misc Control */
};
+struct esdc_regs {
+ u32 esdctl0;
+ u32 esdcfg0;
+ u32 esdctl1;
+ u32 esdcfg1;
+ u32 esdmisc;
+ u32 reserved[4];
+ u32 esdcdly[5];
+ u32 esdcdlyl;
+};
+
+#define ESDC_MISC_RST (1 << 1)
+#define ESDC_MISC_MDDR_EN (1 << 2)
+#define ESDC_MISC_MDDR_DL_RST (1 << 3)
+#define ESDC_MISC_DDR_EN (1 << 8)
+#define ESDC_MISC_DDR2_EN (1 << 9)
+
/*
* NFMS bit in RCSR register for pagesize of nandflash
*/
#define CCM_RCSR_NF_16BIT_SEL (1 << 14)
-extern unsigned int get_board_rev(void);
-extern int is_soc_rev(int rev);
-extern int sdhc_init(void);
-
#endif
#endif /* __ASM_ARCH_MX35_H */
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.
+ */
+.macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, =AIPS1_BASE_ADDR
+ ldr r1, =AIPS_MPR_CONFIG
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, =AIPS2_BASE_ADDR
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+
+ /*
+ * Clear the on and off peripheral modules Supervisor Protect bit
+ * for SDMA to access them. Did not change the AIPS control registers
+ * (offset 0x20) access type
+ */
+ ldr r0, =AIPS1_BASE_ADDR
+ ldr r1, =AIPS_OPACR_CONFIG
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ str r1, [r0, #0x50]
+ ldr r0, =AIPS2_BASE_ADDR
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ str r1, [r0, #0x50]
+.endm
+
+/* MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+ ldr r0, =MAX_BASE_ADDR
+ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+ ldr r1, =MAX_MPR_CONFIG
+ str r1, [r0, #0x000] /* for S0 */
+ str r1, [r0, #0x100] /* for S1 */
+ str r1, [r0, #0x200] /* for S2 */
+ str r1, [r0, #0x300] /* for S3 */
+ str r1, [r0, #0x400] /* for S4 */
+ /* SGPCR - always park on last master */
+ ldr r1, =MAX_SGPCR_CONFIG
+ str r1, [r0, #0x010] /* for S0 */
+ str r1, [r0, #0x110] /* for S1 */
+ str r1, [r0, #0x210] /* for S2 */
+ str r1, [r0, #0x310] /* for S3 */
+ str r1, [r0, #0x410] /* for S4 */
+ /* MGPCR - restore default values */
+ ldr r1, =MAX_MGPCR_CONFIG
+ str r1, [r0, #0x800] /* for M0 */
+ str r1, [r0, #0x900] /* for M1 */
+ str r1, [r0, #0xA00] /* for M2 */
+ str r1, [r0, #0xB00] /* for M3 */
+ str r1, [r0, #0xC00] /* for M4 */
+ str r1, [r0, #0xD00] /* for M5 */
+.endm
+
+/* M3IF setup */
+.macro init_m3if
+ /* Configure M3IF registers */
+ ldr r1, =M3IF_BASE_ADDR
+ /*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+ ldr r0, =M3IF_CONFIG
+ str r0, [r1] /* M3IF control reg */
+.endm
+
+.macro core_init
+ mrc 15, 0, r1, c1, c0, 0
+
+ mrc 15, 0, r0, c1, c0, 1
+ orr r0, r0, #7
+ mcr 15, 0, r0, c1, c0, 1
+ orr r1, r1, #(1<<11)
+
+ /* Set unaligned access enable */
+ orr r1, r1, #(1<<22)
+
+ /* Set low int latency enable */
+ orr r1, r1, #(1<<21)
+
+ mcr 15, 0, r1, c1, c0, 0
+
+ mov r0, #0
+
+ /* Set branch prediction enable */
+ mcr 15, 0, r0, c15, c2, 4
+
+ mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
+ mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
+
+ /*
+ * initializes very early AIPS
+ * Then it also initializes Multi-Layer AHB Crossbar Switch,
+ * M3IF
+ * Also setup the Peripheral Port Remap register inside the core
+ */
+ ldr r0, =0x40000015 /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+.endm
MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780),
MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784),
MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788),
+
+ MX35_PIN_RTS2_UART3_RXD_MUX = _MXC_BUILD_NON_GPIO_PIN(0x1a0, 0x5e4),
+ MX35_PIN_CTS2_UART3_TXD_MUX = _MXC_BUILD_NON_GPIO_PIN(0x1a4, 0x5e8),
} iomux_pin_name_t;
#endif
#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
-/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
- * ACTIMA
- * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
- * TDPL (Twr) = 15/6 = 2.5 -> 3
- * TRRD = 12/6 = 2
- * TRCD = 18/6 = 3
- * TRP = 18/6 = 3
- * TRAS = 42/6 = 7
- * TRC = 60/6 = 10
- * TRFC = 72/6 = 12
- * ACTIMB
- * TCKE = 2
- * XSR = 120/6 = 20
- */
-#define INFINEON_TDAL_165 6
-#define INFINEON_TDPL_165 3
-#define INFINEON_TRRD_165 2
-#define INFINEON_TRCD_165 3
-#define INFINEON_TRP_165 3
-#define INFINEON_TRAS_165 7
-#define INFINEON_TRC_165 10
-#define INFINEON_TRFC_165 12
-#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | \
- (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) | \
- (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) | \
- (INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) | \
- (INFINEON_TDAL_165))
+/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */
+#define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */
+#define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */
+#define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */
+#define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */
+#define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */
+#define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */
+#define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */
+#define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */
+
+#define ACTIM_CTRLA(a,b,c,d,e,f,g,h) \
+ ACTIM_CTRLA_TRFC(a) | \
+ ACTIM_CTRLA_TRC(b) | \
+ ACTIM_CTRLA_TRAS(b) | \
+ ACTIM_CTRLA_TRP(d) | \
+ ACTIM_CTRLA_TRCD(e) | \
+ ACTIM_CTRLA_TRRD(f) | \
+ ACTIM_CTRLA_TDPL(g) | \
+ ACTIM_CTRLA_TDAL(h)
+
+/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */
+#define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */
+#define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */
+#define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */
+#define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */
+
+#define ACTIM_CTRLB(a,b,c,d) \
+ ACTIM_CTRLB_TWTR(a) | \
+ ACTIM_CTRLB_TCKE(b) | \
+ ACTIM_CTRLB_TXP(b) | \
+ ACTIM_CTRLB_TXSR(d)
+
+/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
+#define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
+ /* 15/6 + 18/6 = 5.5 -> 6 */
+#define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
+#define INFINEON_TRRD_165 2 /* 12/6 = 2 */
+#define INFINEON_TRCD_165 3 /* 18/6 = 3 */
+#define INFINEON_TRP_165 3 /* 18/6 = 3 */
+#define INFINEON_TRAS_165 7 /* 42/6 = 7 */
+#define INFINEON_TRC_165 10 /* 60/6 = 10 */
+#define INFINEON_TRFC_165 12 /* 72/6 = 12 */
+
+#define INFINEON_V_ACTIMA_165 \
+ ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \
+ INFINEON_TRAS_165, INFINEON_TRP_165, \
+ INFINEON_TRCD_165, INFINEON_TRRD_165, \
+ INFINEON_TDPL_165, INFINEON_TDAL_165)
#define INFINEON_TWTR_165 1
#define INFINEON_TCKE_165 2
#define INFINEON_TXP_165 2
-#define INFINEON_XSR_165 20
-#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | \
- (INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) | \
- (INFINEON_TWTR_165 << 16))
-
-/* Micron part of 3430 EVM (165MHz optimized) 6.06ns
- * ACTIMA
- * TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6
- * TDPL (Twr) = 15/6 = 2.5 -> 3
- * TRRD = 12/6 = 2
- * TRCD = 18/6 = 3
- * TRP = 18/6 = 3
- * TRAS = 42/6 = 7
- * TRC = 60/6 = 10
- * TRFC = 125/6 = 21
- * ACTIMB
- * TWTR = 1
- * TCKE = 1
- * TXSR = 138/6 = 23
- * TXP = 25/6 = 4.1 ~5
- */
-#define MICRON_TDAL_165 6
-#define MICRON_TDPL_165 3
-#define MICRON_TRRD_165 2
-#define MICRON_TRCD_165 3
-#define MICRON_TRP_165 3
-#define MICRON_TRAS_165 7
-#define MICRON_TRC_165 10
-#define MICRON_TRFC_165 21
-#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | \
- (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) | \
- (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) | \
- (MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) | \
- (MICRON_TDAL_165))
+#define INFINEON_XSR_165 20 /* 120/6 = 20 */
+
+#define INFINEON_V_ACTIMB_165 \
+ ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \
+ INFINEON_TXP_165, INFINEON_XSR_165)
+
+/* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
+#define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */
+ /* 15/6 + 18/6 = 5.5 -> 6 */
+#define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
+#define MICRON_TRRD_165 2 /* 12/6 = 2 */
+#define MICRON_TRCD_165 3 /* 18/6 = 3 */
+#define MICRON_TRP_165 3 /* 18/6 = 3 */
+#define MICRON_TRAS_165 7 /* 42/6 = 7 */
+#define MICRON_TRC_165 10 /* 60/6 = 10 */
+#define MICRON_TRFC_165 21 /* 125/6 = 21 */
+
+#define MICRON_V_ACTIMA_165 \
+ ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \
+ MICRON_TRAS_165, MICRON_TRP_165, \
+ MICRON_TRCD_165, MICRON_TRRD_165, \
+ MICRON_TDPL_165, MICRON_TDAL_165)
#define MICRON_TWTR_165 1
#define MICRON_TCKE_165 1
-#define MICRON_XSR_165 23
-#define MICRON_TXP_165 5
-#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | \
- (MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \
- (MICRON_TWTR_165 << 16))
+#define MICRON_XSR_165 23 /* 138/6 = 23 */
+#define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */
+
+#define MICRON_V_ACTIMB_165 \
+ ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \
+ MICRON_TXP_165, MICRON_XSR_165)
#define MICRON_RAMTYPE 0x1
#define MICRON_DDRTYPE 0x0
#define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \
(MICRON_SIL << 3) | (MICRON_BL))
-/*
- * NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns
- * ACTIMA
- * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
- * TDPL (Twr) = 15/6 = 2.5 -> 3
- * TRRD = 12/6 = 2
- * TRCD = 22.5/6 = 3.75 -> 4
- * TRP = 18/6 = 3
- * TRAS = 42/6 = 7
- * TRC = 60/6 = 10
- * TRFC = 140/6 = 23.3 -> 24
- * ACTIMB
- * TWTR = 2
- * TCKE = 2
- * TXSR = 200/6 = 33.3 -> 34
- * TXP = 1.0 + 1.1 = 2.1 -> 3
- */
-#define NUMONYX_TDAL_165 6
-#define NUMONYX_TDPL_165 3
-#define NUMONYX_TRRD_165 2
-#define NUMONYX_TRCD_165 4
-#define NUMONYX_TRP_165 3
-#define NUMONYX_TRAS_165 7
-#define NUMONYX_TRC_165 10
-#define NUMONYX_TRFC_165 24
-#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | \
- (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) | \
- (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) | \
- (NUMONYX_TRRD_165 << 9) | (NUMONYX_TDPL_165 << 6) | \
- (NUMONYX_TDAL_165))
-
-#define NUMONYX_TWTR_165 2
-#define NUMONYX_TCKE_165 2
-#define NUMONYX_TXP_165 3
-#define NUMONYX_XSR_165 34
-#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | \
- (NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \
- (NUMONYX_TWTR_165 << 16))
+/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
+#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
+ /* 15/6 + 18/6 = 5.5 -> 6 */
+#define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
+#define NUMONYX_TRRD_165 2 /* 12/6 = 2 */
+#define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */
+#define NUMONYX_TRP_165 3 /* 18/6 = 3 */
+#define NUMONYX_TRAS_165 7 /* 42/6 = 7 */
+#define NUMONYX_TRC_165 10 /* 60/6 = 10 */
+#define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */
+
+#define NUMONYX_V_ACTIMA_165 \
+ ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \
+ NUMONYX_TRAS_165, NUMONYX_TRP_165, \
+ NUMONYX_TRCD_165, NUMONYX_TRRD_165, \
+ NUMONYX_TDPL_165, NUMONYX_TDAL_165)
+
+#define NUMONYX_TWTR_165 2
+#define NUMONYX_TCKE_165 2
+#define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */
+#define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */
+
+#define NUMONYX_V_ACTIMB_165 \
+ ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \
+ NUMONYX_TXP_165, NUMONYX_XSR_165)
#ifdef CONFIG_OMAP3_INFINEON_DDR
-#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
-#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
+#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
+#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
#endif
#ifdef CONFIG_OMAP3_MICRON_DDR
-#define V_ACTIMA_165 MICRON_V_ACTIMA_165
-#define V_ACTIMB_165 MICRON_V_ACTIMB_165
+#define V_ACTIMA_165 MICRON_V_ACTIMA_165
+#define V_ACTIMB_165 MICRON_V_ACTIMB_165
#define V_MCFG MICRON_V_MCFG
#define V_RFR_CTRL MICRON_V_RFR_CTRL
#define V_MR MICRON_V_MR
#endif
#ifdef CONFIG_OMAP3_NUMONYX_DDR
-#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
-#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
+#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
+#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
#endif
#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
#include <asm/arch/pantheon.h>
#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+/* default Dcache Line length for pantheon */
+#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
status = mpc_reg_in(®s->msr);
while (timeout-- && (status & I2C_BB)) {
-#if 1
- volatile int temp;
mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
- temp = mpc_reg_in(®s->mdr);
+ (void)mpc_reg_in(®s->mdr);
mpc_reg_out(®s->mcr, 0, I2C_STA);
mpc_reg_out(®s->mcr, 0, 0);
mpc_reg_out(®s->mcr, I2C_EN, 0);
-#endif
udelay(15);
status = mpc_reg_in(®s->msr);
}
static void dl_transfer_length(td_t * td)
{
- __u32 tdINFO, tdBE, tdCBP;
+ __u32 tdBE, tdCBP;
urb_priv_t *lurb_priv = &urb_priv;
- tdINFO = ohci_cpu_to_le32 (td->hwINFO);
tdBE = ohci_cpu_to_le32 (td->hwBE);
tdCBP = ohci_cpu_to_le32 (td->hwCBP);
frame = (NBUF *) pRbd->dataPointer;
frame_length = pRbd->dataLength - 4;
-#if (0)
- {
+ /* DEBUG code */
+ if (_DEBUG) {
int i;
printf ("recv data hdr:");
printf ("%x ", *(frame->head + i));
printf ("\n");
}
-#endif
+
/*
* Fill the buffer and pass it to upper layers
*/
status = mpc_reg_in (®s->sr);
while (timeout-- && (status & I2C_BB)) {
-#if 1
- volatile int temp;
mpc_reg_out (®s->cr, I2C_STA, I2C_STA);
- temp = mpc_reg_in (®s->dr);
+ (void)mpc_reg_in (®s->dr);
mpc_reg_out (®s->cr, 0, I2C_STA);
mpc_reg_out (®s->cr, 0, 0);
mpc_reg_out (®s->cr, I2C_EN, 0);
-#endif
+
udelay (1000);
status = mpc_reg_in (®s->sr);
}
#include <asm/cpm_8260.h>
#include <i2c.h>
-/* define to enable debug messages */
-#undef DEBUG_I2C
-
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_I2C_MULTI_BUS)
-static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0;
+static unsigned int i2c_bus_num __attribute__ ((section(".data"))) = 0;
#endif /* CONFIG_I2C_MULTI_BUS */
/* uSec to wait between polls of the i2c */
*/
#define TOUT_LOOP 5
-/*-----------------------------------------------------------------------
+/*
* Set default values
*/
#ifndef CONFIG_SYS_I2C_SPEED
#define CONFIG_SYS_I2C_SPEED 50000
#endif
-/*-----------------------------------------------------------------------
- */
-typedef void (*i2c_ecb_t)(int, int, void *); /* error callback function */
+typedef void (*i2c_ecb_t) (int, int, void *); /* error callback function */
/* This structure keeps track of the bd and buffer space usage. */
typedef struct i2c_state {
- int rx_idx; /* index to next free Rx BD */
- int tx_idx; /* index to next free Tx BD */
- void *rxbd; /* pointer to next free Rx BD */
- void *txbd; /* pointer to next free Tx BD */
- int tx_space; /* number of Tx bytes left */
- unsigned char *tx_buf; /* pointer to free Tx area */
- i2c_ecb_t err_cb; /* error callback function */
- void *cb_data; /* private data to be passed */
+ int rx_idx; /* index to next free Rx BD */
+ int tx_idx; /* index to next free Tx BD */
+ void *rxbd; /* pointer to next free Rx BD */
+ void *txbd; /* pointer to next free Tx BD */
+ int tx_space; /* number of Tx bytes left */
+ unsigned char *tx_buf; /* pointer to free Tx area */
+ i2c_ecb_t err_cb; /* error callback function */
+ void *cb_data; /* private data to be passed */
} i2c_state_t;
/* flags for i2c_send() and i2c_receive() */
-#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
-#define I2CF_START_COND 0x02 /* tx: generate start condition */
-#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
+#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
+#define I2CF_START_COND 0x02 /* tx: generate start condition */
+#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
/* return codes */
-#define I2CERR_NO_BUFFERS 1 /* no more BDs or buffer space */
-#define I2CERR_MSG_TOO_LONG 2 /* tried to send/receive to much data */
-#define I2CERR_TIMEOUT 3 /* timeout in i2c_doio() */
-#define I2CERR_QUEUE_EMPTY 4 /* i2c_doio called without send/receive */
-#define I2CERR_IO_ERROR 5 /* had an error during comms */
+#define I2CERR_NO_BUFFERS 1 /* no more BDs or buffer space */
+#define I2CERR_MSG_TOO_LONG 2 /* tried to send/receive to much data */
+#define I2CERR_TIMEOUT 3 /* timeout in i2c_doio() */
+#define I2CERR_QUEUE_EMPTY 4 /* i2c_doio called without send/rcv */
+#define I2CERR_IO_ERROR 5 /* had an error during comms */
/* error callback flags */
-#define I2CECB_RX_ERR 0x10 /* this is a receive error */
-#define I2CECB_RX_OV 0x02 /* receive overrun error */
-#define I2CECB_RX_MASK 0x0f /* mask for error bits */
-#define I2CECB_TX_ERR 0x20 /* this is a transmit error */
-#define I2CECB_TX_CL 0x01 /* transmit collision error */
-#define I2CECB_TX_UN 0x02 /* transmit underflow error */
-#define I2CECB_TX_NAK 0x04 /* transmit no ack error */
-#define I2CECB_TX_MASK 0x0f /* mask for error bits */
-#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
+#define I2CECB_RX_ERR 0x10 /* this is a receive error */
+#define I2CECB_RX_OV 0x02 /* receive overrun error */
+#define I2CECB_RX_MASK 0x0f /* mask for error bits */
+#define I2CECB_TX_ERR 0x20 /* this is a transmit error */
+#define I2CECB_TX_CL 0x01 /* transmit collision error */
+#define I2CECB_TX_UN 0x02 /* transmit underflow error */
+#define I2CECB_TX_NAK 0x04 /* transmit no ack error */
+#define I2CECB_TX_MASK 0x0f /* mask for error bits */
+#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
#define ERROR_I2C_NONE 0
#define ERROR_I2C_LENGTH 1
#define NUM_TX_BDS 4
#define MAX_TX_SPACE 256
-typedef struct I2C_BD
-{
- unsigned short status;
- unsigned short length;
- unsigned char *addr;
+typedef struct I2C_BD {
+ unsigned short status;
+ unsigned short length;
+ unsigned char *addr;
} I2C_BD;
-#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
+
+#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
#define BD_I2C_TX_CL 0x0001 /* collision error */
#define BD_I2C_TX_UN 0x0002 /* underflow error */
#define BD_I2C_RX_ERR BD_SC_OV
-#ifdef DEBUG_I2C
-#define PRINTD(x) printf x
-#else
-#define PRINTD(x)
-#endif
-
/*
* Returns the best value of I2BRG to meet desired clock speed of I2C with
* input parameters (clock speed, filter, and predivider value).
*/
static inline int
i2c_roundrate(int hz, int speed, int filter, int modval,
- int *brgval, int *totspeed)
+ int *brgval, int *totspeed)
{
- int moddiv = 1 << (5-(modval & 3)), brgdiv, div;
+ int moddiv = 1 << (5 - (modval & 3)), brgdiv, div;
- PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
- hz, speed, filter, modval));
+ debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
+ hz, speed, filter, modval);
- div = moddiv * speed;
- brgdiv = (hz + div - 1) / div;
+ div = moddiv * speed;
+ brgdiv = (hz + div - 1) / div;
- PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv));
+ debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv);
- *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter);
+ *brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter);
- if ((*brgval < 0) || (*brgval > 255)) {
- PRINTD(("\t\trejected brgval=%d\n", *brgval));
- return -1;
- }
+ if ((*brgval < 0) || (*brgval > 255)) {
+ debug("\t\trejected brgval=%d\n", *brgval);
+ return -1;
+ }
- brgdiv = 2 * (*brgval + 3 + (2 * filter));
- div = moddiv * brgdiv ;
- *totspeed = hz / div;
+ brgdiv = 2 * (*brgval + 3 + (2 * filter));
+ div = moddiv * brgdiv;
+ *totspeed = hz / div;
- PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed));
+ debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed);
- return 0;
+ return 0;
}
/*
*/
static int i2c_setrate(int hz, int speed)
{
- immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
- volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
- int brgval,
- modval, /* 0-3 */
- bestspeed_diff = speed,
- bestspeed_brgval=0,
- bestspeed_modval=0,
- bestspeed_filter=0,
- totspeed,
- filter = 0; /* Use this fixed value */
-
- for (modval = 0; modval < 4; modval++)
- {
- if (i2c_roundrate (hz, speed, filter, modval, &brgval, &totspeed) == 0)
- {
- int diff = speed - totspeed ;
-
- if ((diff >= 0) && (diff < bestspeed_diff))
- {
- bestspeed_diff = diff ;
- bestspeed_modval = modval;
- bestspeed_brgval = brgval;
- bestspeed_filter = filter;
+ immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
+ int brgval,
+ modval, /* 0-3 */
+ bestspeed_diff = speed,
+ bestspeed_brgval = 0,
+ bestspeed_modval = 0,
+ bestspeed_filter = 0,
+ totspeed,
+ filter = 0; /* Use this fixed value */
+
+ for (modval = 0; modval < 4; modval++) {
+ if (i2c_roundrate(hz, speed, filter, modval, &brgval, &totspeed)
+ == 0) {
+ int diff = speed - totspeed;
+
+ if ((diff >= 0) && (diff < bestspeed_diff)) {
+ bestspeed_diff = diff;
+ bestspeed_modval = modval;
+ bestspeed_brgval = brgval;
+ bestspeed_filter = filter;
}
}
}
- PRINTD(("[I2C] Best is:\n"));
- PRINTD(("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
- hz, speed,
- bestspeed_filter, bestspeed_modval, bestspeed_brgval,
- bestspeed_diff));
+ debug("[I2C] Best is:\n");
+ debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
+ hz, speed, bestspeed_filter, bestspeed_modval, bestspeed_brgval,
+ bestspeed_diff);
- i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
- i2c->i2c_i2brg = bestspeed_brgval & 0xff;
+ i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) |
+ (bestspeed_filter << 3);
+ i2c->i2c_i2brg = bestspeed_brgval & 0xff;
- PRINTD(("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, i2c->i2c_i2brg));
+ debug("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod,
+ i2c->i2c_i2brg);
- return 1 ;
+ return 1;
}
void i2c_init(int speed, int slaveadd)
{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
- volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
+ volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
volatile iic_t *iip;
ulong rbase, tbase;
volatile I2C_BD *rxbd, *txbd;
uint dpaddr;
#ifdef CONFIG_SYS_I2C_INIT_BOARD
- /* call board specific i2c bus reset routine before accessing the */
- /* environment, which might be in a chip on that bus. For details */
- /* about this problem see doc/I2C_Edge_Conditions. */
+ /*
+ * call board specific i2c bus reset routine before accessing the
+ * environment, which might be in a chip on that bus. For details
+ * about this problem see doc/I2C_Edge_Conditions.
+ */
i2c_init_board();
#endif
- dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
+ dpaddr = *((unsigned short *) (&immap->im_dprambase[PROFF_I2C_BASE]));
if (dpaddr == 0) {
- /* need to allocate dual port ram */
- dpaddr = m8260_cpm_dpalloc(64 +
- (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) +
- MAX_TX_SPACE, 64);
- *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])) = dpaddr;
+ /* need to allocate dual port ram */
+ dpaddr = m8260_cpm_dpalloc(64 +
+ (NUM_RX_BDS * sizeof(I2C_BD)) +
+ (NUM_TX_BDS * sizeof(I2C_BD)) +
+ MAX_TX_SPACE, 64);
+ *((unsigned short *)(&immap->im_dprambase[PROFF_I2C_BASE])) =
+ dpaddr;
}
/*
* initialise data in dual port ram:
*
- * dpaddr -> parameter ram (64 bytes)
+ * dpaddr -> parameter ram (64 bytes)
* rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
* tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
* tx buffer (MAX_TX_SPACE bytes)
*/
iip = (iic_t *)&immap->im_dprambase[dpaddr];
- memset((void*)iip, 0, sizeof(iic_t));
+ memset((void *)iip, 0, sizeof(iic_t));
rbase = dpaddr + 64;
tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
* and current CPU rate (we assume sccr dfbgr field is 0;
* divide BRGCLK by 1)
*/
- PRINTD(("[I2C] Setting rate...\n"));
- i2c_setrate (gd->brg_clk, CONFIG_SYS_I2C_SPEED) ;
+ debug("[I2C] Setting rate...\n");
+ i2c_setrate(gd->brg_clk, CONFIG_SYS_I2C_SPEED);
/* Set I2C controller in master mode */
i2c->i2c_i2com = 0x01;
/* Initialize Tx/Rx parameters */
iip->iic_rbase = rbase;
iip->iic_tbase = tbase;
- rxbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_rbase]);
- txbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_tbase]);
+ rxbd = (I2C_BD *)((unsigned char *) &immap->
+ im_dprambase[iip->iic_rbase]);
+ txbd = (I2C_BD *)((unsigned char *) &immap->
+ im_dprambase[iip->iic_tbase]);
- PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
- PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
- PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
- PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
+ debug("[I2C] rbase = %04x\n", iip->iic_rbase);
+ debug("[I2C] tbase = %04x\n", iip->iic_tbase);
+ debug("[I2C] rxbd = %08x\n", (int) rxbd);
+ debug("[I2C] txbd = %08x\n", (int) txbd);
/* Set big endian byte order */
iip->iic_tfcr = 0x10;
/* Set maximum receive size. */
iip->iic_mrblr = I2C_RXTX_LEN;
- cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE,
- CPM_CR_I2C_SBLOCK,
- 0x00,
- CPM_CR_INIT_TRX) | CPM_CR_FLG;
- do {
- __asm__ __volatile__ ("eieio");
- } while (cp->cp_cpcr & CPM_CR_FLG);
+ cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE,
+ CPM_CR_I2C_SBLOCK,
+ 0x00, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+ do {
+ __asm__ __volatile__("eieio");
+ } while (cp->cp_cpcr & CPM_CR_FLG);
/* Clear events and interrupts */
i2c->i2c_i2cer = 0xff;
static
void i2c_newio(i2c_state_t *state)
{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile iic_t *iip;
uint dpaddr;
- PRINTD(("[I2C] i2c_newio\n"));
+ debug("[I2C] i2c_newio\n");
- dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
+ dpaddr = *((unsigned short *)(&immap->im_dprambase[PROFF_I2C_BASE]));
iip = (iic_t *)&immap->im_dprambase[dpaddr];
state->rx_idx = 0;
state->tx_idx = 0;
- state->rxbd = (void*)&immap->im_dprambase[iip->iic_rbase];
- state->txbd = (void*)&immap->im_dprambase[iip->iic_tbase];
+ state->rxbd = (void *)&immap->im_dprambase[iip->iic_rbase];
+ state->txbd = (void *)&immap->im_dprambase[iip->iic_tbase];
state->tx_space = MAX_TX_SPACE;
- state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
+ state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
state->err_cb = NULL;
state->cb_data = NULL;
- PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
- PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
- PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
+ debug("[I2C] rxbd = %08x\n", (int)state->rxbd);
+ debug("[I2C] txbd = %08x\n", (int)state->txbd);
+ debug("[I2C] tx_buf = %08x\n", (int)state->tx_buf);
/* clear the buffer memory */
- memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
+ memset((char *) state->tx_buf, 0, MAX_TX_SPACE);
}
static
int i2c_send(i2c_state_t *state,
- unsigned char address,
- unsigned char secondary_address,
- unsigned int flags,
- unsigned short size,
- unsigned char *dataout)
+ unsigned char address,
+ unsigned char secondary_address,
+ unsigned int flags, unsigned short size, unsigned char *dataout)
{
volatile I2C_BD *txbd;
- int i,j;
+ int i, j;
- PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
- address, secondary_address, flags, size));
+ debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
+ address, secondary_address, flags, size);
/* trying to send message larger than BD */
if (size > I2C_RXTX_LEN)
- return I2CERR_MSG_TOO_LONG;
+ return I2CERR_MSG_TOO_LONG;
/* no more free bds */
if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
- return I2CERR_NO_BUFFERS;
+ return I2CERR_NO_BUFFERS;
txbd = (I2C_BD *)state->txbd;
txbd->addr = state->tx_buf;
- PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
-
- if (flags & I2CF_START_COND)
- {
- PRINTD(("[I2C] Formatting addresses...\n"));
- if (flags & I2CF_ENABLE_SECONDARY)
- {
- txbd->length = size + 2; /* Length of message plus dest addresses */
- txbd->addr[0] = address << 1;
- txbd->addr[1] = secondary_address;
- i = 2;
- }
- else
- {
- txbd->length = size + 1; /* Length of message plus dest address */
- txbd->addr[0] = address << 1; /* Write destination address to BD */
- i = 1;
+ debug("[I2C] txbd = %08x\n", (int) txbd);
+
+ if (flags & I2CF_START_COND) {
+ debug("[I2C] Formatting addresses...\n");
+ if (flags & I2CF_ENABLE_SECONDARY) {
+ /* Length of message plus dest addresses */
+ txbd->length = size + 2;
+ txbd->addr[0] = address << 1;
+ txbd->addr[1] = secondary_address;
+ i = 2;
+ } else {
+ /* Length of message plus dest address */
+ txbd->length = size + 1;
+ /* Write destination address to BD */
+ txbd->addr[0] = address << 1;
+ i = 1;
+ }
+ } else {
+ txbd->length = size; /* Length of message */
+ i = 0;
}
- }
- else
- {
- txbd->length = size; /* Length of message */
- i = 0;
- }
/* set up txbd */
txbd->status = BD_SC_READY;
if (flags & I2CF_START_COND)
- txbd->status |= BD_I2C_TX_START;
+ txbd->status |= BD_I2C_TX_START;
if (flags & I2CF_STOP_COND)
- txbd->status |= BD_SC_LAST | BD_SC_WRAP;
+ txbd->status |= BD_SC_LAST | BD_SC_WRAP;
/* Copy data to send into buffer */
- PRINTD(("[I2C] copy data...\n"));
- for(j = 0; j < size; i++, j++)
- txbd->addr[i] = dataout[j];
+ debug("[I2C] copy data...\n");
+ for (j = 0; j < size; i++, j++)
+ txbd->addr[i] = dataout[j];
- PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
- txbd->length,
- txbd->status,
- txbd->addr[0],
- txbd->addr[1]));
+ debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
+ txbd->length, txbd->status, txbd->addr[0], txbd->addr[1]);
/* advance state */
state->tx_buf += txbd->length;
state->tx_space -= txbd->length;
state->tx_idx++;
- state->txbd = (void*)(txbd + 1);
+ state->txbd = (void *) (txbd + 1);
return 0;
}
static
int i2c_receive(i2c_state_t *state,
- unsigned char address,
- unsigned char secondary_address,
- unsigned int flags,
- unsigned short size_to_expect,
- unsigned char *datain)
+ unsigned char address,
+ unsigned char secondary_address,
+ unsigned int flags,
+ unsigned short size_to_expect, unsigned char *datain)
{
volatile I2C_BD *rxbd, *txbd;
- PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags));
+ debug("[I2C] i2c_receive %02d %02d %02d\n", address,
+ secondary_address, flags);
/* Expected to receive too much */
if (size_to_expect > I2C_RXTX_LEN)
- return I2CERR_MSG_TOO_LONG;
+ return I2CERR_MSG_TOO_LONG;
/* no more free bds */
if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
- || state->tx_space < 2)
- return I2CERR_NO_BUFFERS;
+ || state->tx_space < 2)
+ return I2CERR_NO_BUFFERS;
- rxbd = (I2C_BD *)state->rxbd;
- txbd = (I2C_BD *)state->txbd;
+ rxbd = (I2C_BD *) state->rxbd;
+ txbd = (I2C_BD *) state->txbd;
- PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
- PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
+ debug("[I2C] rxbd = %08x\n", (int) rxbd);
+ debug("[I2C] txbd = %08x\n", (int) txbd);
txbd->addr = state->tx_buf;
/* set up TXBD for destination address */
- if (flags & I2CF_ENABLE_SECONDARY)
- {
+ if (flags & I2CF_ENABLE_SECONDARY) {
txbd->length = 2;
- txbd->addr[0] = address << 1; /* Write data */
- txbd->addr[1] = secondary_address; /* Internal address */
+ txbd->addr[0] = address << 1; /* Write data */
+ txbd->addr[1] = secondary_address; /* Internal address */
txbd->status = BD_SC_READY;
- }
- else
- {
+ } else {
txbd->length = 1 + size_to_expect;
txbd->addr[0] = (address << 1) | 0x01;
txbd->status = BD_SC_READY;
rxbd->addr = datain;
txbd->status |= BD_I2C_TX_START;
- if (flags & I2CF_STOP_COND)
- {
+ if (flags & I2CF_STOP_COND) {
txbd->status |= BD_SC_LAST | BD_SC_WRAP;
rxbd->status |= BD_SC_WRAP;
}
- PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
- txbd->length,
- txbd->status,
- txbd->addr[0],
- txbd->addr[1]));
- PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
- rxbd->length,
- rxbd->status,
- rxbd->addr[0],
- rxbd->addr[1]));
+ debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
+ txbd->length, txbd->status, txbd->addr[0], txbd->addr[1]);
+ debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
+ rxbd->length, rxbd->status, rxbd->addr[0], rxbd->addr[1]);
/* advance state */
state->tx_buf += txbd->length;
state->tx_space -= txbd->length;
state->tx_idx++;
- state->txbd = (void*)(txbd + 1);
+ state->txbd = (void *) (txbd + 1);
state->rx_idx++;
- state->rxbd = (void*)(rxbd + 1);
+ state->rxbd = (void *) (rxbd + 1);
return 0;
}
static
int i2c_doio(i2c_state_t *state)
{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile iic_t *iip;
- volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
+ volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
volatile I2C_BD *txbd, *rxbd;
- int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0;
+ int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0;
uint dpaddr;
- PRINTD(("[I2C] i2c_doio\n"));
+ debug("[I2C] i2c_doio\n");
if (state->tx_idx <= 0 && state->rx_idx <= 0) {
- PRINTD(("[I2C] No I/O is queued\n"));
+ debug("[I2C] No I/O is queued\n");
return I2CERR_QUEUE_EMPTY;
}
- dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
+ dpaddr = *((unsigned short *)(&immap->im_dprambase[PROFF_I2C_BASE]));
iip = (iic_t *)&immap->im_dprambase[dpaddr];
iip->iic_rbptr = iip->iic_rbase;
iip->iic_tbptr = iip->iic_tbase;
/* Enable I2C */
- PRINTD(("[I2C] Enabling I2C...\n"));
+ debug("[I2C] Enabling I2C...\n");
i2c->i2c_i2mod |= 0x01;
/* Begin transmission */
/* Loop until transmit & receive completed */
- if ((n = state->tx_idx) > 0) {
+ n = state->tx_idx;
+
+ if (n > 0) {
- txbd = ((I2C_BD*)state->txbd) - n;
+ txbd = ((I2C_BD *) state->txbd) - n;
for (i = 0; i < n; i++) {
txtimeo += TOUT_LOOP * txbd->length;
txbd++;
}
- txbd--; /* wait until last in list is done */
+ txbd--; /* wait until last in list is done */
- PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
+ debug("[I2C] Transmitting...(txbd=0x%08lx)\n",
+ (ulong) txbd);
udelay(START_DELAY_US); /* give it time to start */
- while((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) {
+ while ((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) {
udelay(DELAY_US);
if (ctrlc())
- return (-1);
- __asm__ __volatile__ ("eieio");
+ return -1;
+ __asm__ __volatile__("eieio");
}
}
- if (txcnt < txtimeo && (n = state->rx_idx) > 0) {
+ n = state->rx_idx;
- rxbd = ((I2C_BD*)state->rxbd) - n;
+ if (txcnt < txtimeo && n > 0) {
+
+ rxbd = ((I2C_BD *) state->rxbd) - n;
for (i = 0; i < n; i++) {
rxtimeo += TOUT_LOOP * rxbd->length;
rxbd++;
}
- rxbd--; /* wait until last in list is done */
+ rxbd--; /* wait until last in list is done */
- PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
+ debug("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong) rxbd);
udelay(START_DELAY_US); /* give it time to start */
- while((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) {
+ while ((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) {
udelay(DELAY_US);
if (ctrlc())
- return (-1);
- __asm__ __volatile__ ("eieio");
+ return -1;
+ __asm__ __volatile__("eieio");
}
}
/* Turn off I2C */
i2c->i2c_i2mod &= ~0x01;
- if ((n = state->tx_idx) > 0) {
+ n = state->tx_idx;
+
+ if (n > 0) {
for (i = 0; i < n; i++) {
- txbd = ((I2C_BD*)state->txbd) - (n - i);
- if ((b = txbd->status & BD_I2C_TX_ERR) != 0) {
+ txbd = ((I2C_BD *) state->txbd) - (n - i);
+ b = txbd->status & BD_I2C_TX_ERR;
+ if (b != 0) {
if (state->err_cb != NULL)
- (*state->err_cb)(I2CECB_TX_ERR|b, i,
- state->cb_data);
+ (*state->err_cb) (I2CECB_TX_ERR | b,
+ i, state->cb_data);
if (rc == 0)
rc = I2CERR_IO_ERROR;
}
}
}
- if ((n = state->rx_idx) > 0) {
+ n = state->rx_idx;
+
+ if (n > 0) {
for (i = 0; i < n; i++) {
- rxbd = ((I2C_BD*)state->rxbd) - (n - i);
- if ((b = rxbd->status & BD_I2C_RX_ERR) != 0) {
+ rxbd = ((I2C_BD *) state->rxbd) - (n - i);
+ b = rxbd->status & BD_I2C_RX_ERR;
+ if (b != 0) {
if (state->err_cb != NULL)
- (*state->err_cb)(I2CECB_RX_ERR|b, i,
- state->cb_data);
+ (*state->err_cb) (I2CECB_RX_ERR | b,
+ i, state->cb_data);
if (rc == 0)
rc = I2CERR_IO_ERROR;
}
}
}
- if ((txtimeo > 0 && txcnt >= txtimeo) || \
+ if ((txtimeo > 0 && txcnt >= txtimeo) ||
(rxtimeo > 0 && rxcnt >= rxtimeo)) {
if (state->err_cb != NULL)
- (*state->err_cb)(I2CECB_TIMEOUT, -1, state->cb_data);
+ (*state->err_cb) (I2CECB_TIMEOUT, -1, state->cb_data);
if (rc == 0)
rc = I2CERR_TIMEOUT;
}
- return (rc);
+ return rc;
}
-static void
-i2c_probe_callback(int flags, int xnum, void *data)
+static void i2c_probe_callback(int flags, int xnum, void *data)
{
/*
* the only acceptable errors are a transmit NAK or a receive
* means the device must have responded to the slave address
* even though the transfer failed
*/
- if (flags == (I2CECB_TX_ERR|I2CECB_TX_NAK))
- *(int *)data |= 1;
- if (flags == (I2CECB_RX_ERR|I2CECB_RX_OV))
- *(int *)data |= 2;
+ if (flags == (I2CECB_TX_ERR | I2CECB_TX_NAK))
+ *(int *) data |= 1;
+ if (flags == (I2CECB_RX_ERR | I2CECB_RX_OV))
+ *(int *) data |= 2;
}
-int
-i2c_probe(uchar chip)
+int i2c_probe(uchar chip)
{
i2c_state_t state;
int rc, err_flag;
state.cb_data = (void *) &err_flag;
err_flag = 0;
- rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf);
+ rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1,
+ buf);
if (rc != 0)
- return (rc); /* probe failed */
+ return rc; /* probe failed */
rc = i2c_doio(&state);
if (rc == 0)
- return (0); /* device exists - read succeeded */
+ return 0; /* device exists - read succeeded */
if (rc == I2CERR_TIMEOUT)
- return (-1); /* device does not exist - timeout */
+ return -1; /* device does not exist - timeout */
if (rc != I2CERR_IO_ERROR || err_flag == 0)
- return (rc); /* probe failed */
+ return rc; /* probe failed */
if (err_flag & 1)
- return (-1); /* device does not exist - had transmit NAK */
+ return -1; /* device does not exist - had transmit NAK */
- return (0); /* device exists - had receive overrun */
+ return 0; /* device exists - had receive overrun */
}
-int
-i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
i2c_state_t state;
uchar xaddr[4];
xaddr[0] = (addr >> 24) & 0xFF;
xaddr[1] = (addr >> 16) & 0xFF;
- xaddr[2] = (addr >> 8) & 0xFF;
- xaddr[3] = addr & 0xFF;
+ xaddr[2] = (addr >> 8) & 0xFF;
+ xaddr[3] = addr & 0xFF;
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
- /*
- * EEPROM chips that implement "address overflow" are ones
- * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
- * and the extra bits end up in the "chip address" bit slots.
- * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
- * chips.
- *
- * Note that we consider the length of the address field to still
- * be one byte because the extra address bits are hidden in the
- * chip address.
- */
+ /*
+ * EEPROM chips that implement "address overflow" are ones
+ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
+ * and the extra bits end up in the "chip address" bit slots.
+ * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
+ * chips.
+ *
+ * Note that we consider the length of the address field to still
+ * be one byte because the extra address bits are hidden in the
+ * chip address.
+ */
chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
i2c_newio(&state);
- rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
+ rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
+ &xaddr[4 - alen]);
if (rc != 0) {
printf("i2c_read: i2c_send failed (%d)\n", rc);
return 1;
return 0;
}
-int
-i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
i2c_state_t state;
uchar xaddr[4];
xaddr[0] = (addr >> 24) & 0xFF;
xaddr[1] = (addr >> 16) & 0xFF;
- xaddr[2] = (addr >> 8) & 0xFF;
- xaddr[3] = addr & 0xFF;
+ xaddr[2] = (addr >> 8) & 0xFF;
+ xaddr[3] = addr & 0xFF;
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
- /*
- * EEPROM chips that implement "address overflow" are ones
- * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
- * and the extra bits end up in the "chip address" bit slots.
- * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
- * chips.
- *
- * Note that we consider the length of the address field to still
- * be one byte because the extra address bits are hidden in the
- * chip address.
- */
+ /*
+ * EEPROM chips that implement "address overflow" are ones
+ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
+ * and the extra bits end up in the "chip address" bit slots.
+ * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
+ * chips.
+ *
+ * Note that we consider the length of the address field to still
+ * be one byte because the extra address bits are hidden in the
+ * chip address.
+ */
chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
i2c_newio(&state);
- rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
+ rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
+ &xaddr[4 - alen]);
if (rc != 0) {
printf("i2c_write: first i2c_send failed (%d)\n", rc);
return 1;
if (bus < CONFIG_SYS_MAX_I2C_BUS) {
i2c_bus_num = bus;
} else {
- int ret;
+ int ret;
ret = i2x_mux_select_mux(bus);
if (ret == 0)
return 0;
}
-#endif /* CONFIG_I2C_MULTI_BUS */
-#endif /* CONFIG_HARD_I2C */
+#endif /* CONFIG_I2C_MULTI_BUS */
+#endif /* CONFIG_HARD_I2C */
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
ulong clkin;
ulong sccr, dfbrg;
- ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
+ ulong scmr, corecnf, plldf, pllmf;
corecnf_t *cp;
#if !defined(CONFIG_8260_CLKIN)
corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
cp = &corecnf_tab[corecnf];
- busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
- cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
-
/* HiP7, HiP7 Rev01, HiP7 RevA */
if ((get_pvr () == PVR_8260_HIP7) ||
(get_pvr () == PVR_8260_HIP7R1) ||
plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
}
-#if 0
- if (gd->vco_out / (busdf + 1) != clkin) {
- /* aaarrrggghhh!!! */
- return (1);
- }
-#endif
gd->cpm_clk = gd->vco_out / 2;
gd->bus_clk = clkin;
{
volatile spi_t *spi;
volatile immap_t *immr;
- volatile cpm8260_t *cp;
volatile cbd_t *tbdf, *rbdf;
immr = (immap_t *) CONFIG_SYS_IMMR;
- cp = (cpm8260_t *) &immr->im_cpm;
spi = (spi_t *)&immr->im_dprambase[PROFF_SPI];
ssize_t spi_xfer (size_t count)
{
volatile immap_t *immr;
- volatile cpm8260_t *cp;
volatile spi_t *spi;
cbd_t *tbdf, *rbdf;
int tm;
DPRINT (("*** spi_xfer entered ***\n"));
immr = (immap_t *) CONFIG_SYS_IMMR;
- cp = (cpm8260_t *) &immr->im_cpm;
spi = (spi_t *)&immr->im_dprambase[PROFF_SPI];
#include <commproc.h>
#include <netdev.h>
#include <asm/cache.h>
+#include <linux/compiler.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
uint k, m;
char buf[32];
char pre = 'X';
- char *mid = "xx";
+ __maybe_unused char *mid = "xx";
char *suf;
/* the highest 16 bits should be 0x0050 for a 8xx */
{
bd_t *bd = gd->bd;
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile fec_t *fecp;
-
- /*
- * only two FECs please
- */
- if ((unsigned int)fecidx >= 2)
- hang();
-
- if (fecidx == 0)
- fecp = &immr->im_cpm.cp_fec1;
- else
- fecp = &immr->im_cpm.cp_fec2;
/*
* Set MII speed to 2.5 MHz or slightly below.
- * * According to the MPC860T (Rev. D) Fast ethernet controller user
- * * manual (6.2.14),
- * * the MII management interface clock must be less than or equal
- * * to 2.5 MHz.
- * * This MDC frequency is equal to system clock / (2 * MII_SPEED).
- * * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
+ *
+ * According to the MPC860T (Rev. D) Fast ethernet controller user
+ * manual (6.2.14),
+ * the MII management interface clock must be less than or equal
+ * to 2.5 MHz.
+ * This MDC frequency is equal to system clock / (2 * MII_SPEED).
+ * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
*
* All MII configuration is done via FEC1 registers:
*/
immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
- /* our PHYs are the limit at 2.5 MHz */
- fecp->fec_mii_speed <<= 1;
+ {
+ volatile fec_t *fecp;
+
+ /*
+ * only two FECs please
+ */
+ if ((unsigned int)fecidx >= 2)
+ hang();
+
+ if (fecidx == 0)
+ fecp = &immr->im_cpm.cp_fec1;
+ else
+ fecp = &immr->im_cpm.cp_fec2;
+
+ /* our PHYs are the limit at 2.5 MHz */
+ fecp->fec_mii_speed <<= 1;
+ }
#endif
#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
int fec8xx_miiphy_write(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
- short rdreg; /* register working value */
#ifdef MII_DEBUG
printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
- rdreg = mii_send(mk_mii_write(addr, reg, value));
+ (void)mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf ("0x%04x\n", value);
DECLARE_GLOBAL_DATA_PTR;
-/* define to enable debug messages */
-#undef DEBUG_I2C
-
/* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
#define TOUT_LOOP 1000000
#define MAX_TX_SPACE 256
#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
-typedef struct I2C_BD
-{
- unsigned short status;
- unsigned short length;
- unsigned char *addr;
+typedef struct I2C_BD {
+ unsigned short status;
+ unsigned short length;
+ unsigned char *addr;
} I2C_BD;
-#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
+
+#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
#define BD_I2C_TX_CL 0x0001 /* collision error */
#define BD_I2C_TX_UN 0x0002 /* underflow error */
#define BD_I2C_RX_ERR BD_SC_OV
-typedef void (*i2c_ecb_t)(int, int); /* error callback function */
+typedef void (*i2c_ecb_t) (int, int); /* error callback function */
/* This structure keeps track of the bd and buffer space usage. */
typedef struct i2c_state {
- int rx_idx; /* index to next free Rx BD */
- int tx_idx; /* index to next free Tx BD */
- void *rxbd; /* pointer to next free Rx BD */
- void *txbd; /* pointer to next free Tx BD */
- int tx_space; /* number of Tx bytes left */
- unsigned char *tx_buf; /* pointer to free Tx area */
- i2c_ecb_t err_cb; /* error callback function */
+ int rx_idx; /* index to next free Rx BD */
+ int tx_idx; /* index to next free Tx BD */
+ void *rxbd; /* pointer to next free Rx BD */
+ void *txbd; /* pointer to next free Tx BD */
+ int tx_space; /* number of Tx bytes left */
+ unsigned char *tx_buf; /* pointer to free Tx area */
+ i2c_ecb_t err_cb; /* error callback function */
} i2c_state_t;
/* flags for i2c_send() and i2c_receive() */
-#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
-#define I2CF_START_COND 0x02 /* tx: generate start condition */
-#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
+#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
+#define I2CF_START_COND 0x02 /* tx: generate start condition */
+#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
/* return codes */
-#define I2CERR_NO_BUFFERS 0x01 /* no more BDs or buffer space */
-#define I2CERR_MSG_TOO_LONG 0x02 /* tried to send/receive to much data */
-#define I2CERR_TIMEOUT 0x03 /* timeout in i2c_doio() */
-#define I2CERR_QUEUE_EMPTY 0x04 /* i2c_doio called without send/receive */
+#define I2CERR_NO_BUFFERS 0x01 /* no more BDs or buffer space */
+#define I2CERR_MSG_TOO_LONG 0x02 /* tried to send/receive to much data */
+#define I2CERR_TIMEOUT 0x03 /* timeout in i2c_doio() */
+#define I2CERR_QUEUE_EMPTY 0x04 /* i2c_doio called without send/receive */
/* error callback flags */
-#define I2CECB_RX_ERR 0x10 /* this is a receive error */
-#define I2CECB_RX_ERR_OV 0x02 /* receive overrun error */
-#define I2CECB_RX_MASK 0x0f /* mask for error bits */
-#define I2CECB_TX_ERR 0x20 /* this is a transmit error */
-#define I2CECB_TX_CL 0x01 /* transmit collision error */
-#define I2CECB_TX_UN 0x02 /* transmit underflow error */
-#define I2CECB_TX_NAK 0x04 /* transmit no ack error */
-#define I2CECB_TX_MASK 0x0f /* mask for error bits */
-#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
-
-#ifdef DEBUG_I2C
-#define PRINTD(x) printf x
-#else
-#define PRINTD(x)
-#endif
+#define I2CECB_RX_ERR 0x10 /* this is a receive error */
+#define I2CECB_RX_ERR_OV 0x02 /* receive overrun error */
+#define I2CECB_RX_MASK 0x0f /* mask for error bits */
+#define I2CECB_TX_ERR 0x20 /* this is a transmit error */
+#define I2CECB_TX_CL 0x01 /* transmit collision error */
+#define I2CECB_TX_UN 0x02 /* transmit underflow error */
+#define I2CECB_TX_NAK 0x04 /* transmit no ack error */
+#define I2CECB_TX_MASK 0x0f /* mask for error bits */
+#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
/*
* Returns the best value of I2BRG to meet desired clock speed of I2C with
*/
static inline int
i2c_roundrate(int hz, int speed, int filter, int modval,
- int *brgval, int *totspeed)
+ int *brgval, int *totspeed)
{
- int moddiv = 1 << (5-(modval & 3)), brgdiv, div;
+ int moddiv = 1 << (5 - (modval & 3)), brgdiv, div;
- PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
- hz, speed, filter, modval));
+ debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
+ hz, speed, filter, modval);
- div = moddiv * speed;
- brgdiv = (hz + div - 1) / div;
+ div = moddiv * speed;
+ brgdiv = (hz + div - 1) / div;
- PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv));
+ debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv);
- *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter);
+ *brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter);
- if ((*brgval < 0) || (*brgval > 255)) {
- PRINTD(("\t\trejected brgval=%d\n", *brgval));
- return -1;
- }
+ if ((*brgval < 0) || (*brgval > 255)) {
+ debug("\t\trejected brgval=%d\n", *brgval);
+ return -1;
+ }
- brgdiv = 2 * (*brgval + 3 + (2 * filter));
- div = moddiv * brgdiv ;
- *totspeed = hz / div;
+ brgdiv = 2 * (*brgval + 3 + (2 * filter));
+ div = moddiv * brgdiv;
+ *totspeed = hz / div;
- PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed));
+ debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed);
- return 0;
+ return 0;
}
/*
* Sets the I2C clock predivider and divider to meet required clock speed.
*/
-static int
-i2c_setrate (int hz, int speed)
+static int i2c_setrate(int hz, int speed)
{
- immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c;
- int brgval,
- modval, /* 0-3 */
- bestspeed_diff = speed,
- bestspeed_brgval = 0,
- bestspeed_modval = 0,
- bestspeed_filter = 0,
- totspeed,
- filter = 0; /* Use this fixed value */
+ int brgval,
+ modval, /* 0-3 */
+ bestspeed_diff = speed,
+ bestspeed_brgval = 0,
+ bestspeed_modval = 0,
+ bestspeed_filter = 0,
+ totspeed,
+ filter = 0; /* Use this fixed value */
for (modval = 0; modval < 4; modval++) {
- if (i2c_roundrate(hz,speed,filter,modval,&brgval,&totspeed) == 0) {
+ if (i2c_roundrate
+ (hz, speed, filter, modval, &brgval, &totspeed) == 0) {
int diff = speed - totspeed;
if ((diff >= 0) && (diff < bestspeed_diff)) {
}
}
- PRINTD (("[I2C] Best is:\n"));
- PRINTD (("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
+ debug("[I2C] Best is:\n");
+ debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
hz,
speed,
bestspeed_filter,
bestspeed_modval,
bestspeed_brgval,
- bestspeed_diff));
+ bestspeed_diff);
- i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
+ i2c->i2c_i2mod |=
+ ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
i2c->i2c_i2brg = bestspeed_brgval & 0xff;
- PRINTD (("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod,
- i2c->i2c_i2brg));
+ debug("[I2C] i2mod=%08x i2brg=%08x\n",
+ i2c->i2c_i2mod,
+ i2c->i2c_i2brg);
return 1;
}
-void
-i2c_init(int speed, int slaveaddr)
+void i2c_init(int speed, int slaveaddr)
{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
- volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
+ volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
ulong rbase, tbase;
volatile I2C_BD *rxbd, *txbd;
#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = iip->iic_rbase;
if (dpaddr == 0) {
- /* need to allocate dual port ram */
- dpaddr = dpram_alloc_align(
- (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) +
- MAX_TX_SPACE, 8);
+ /* need to allocate dual port ram */
+ dpaddr = dpram_alloc_align((NUM_RX_BDS * sizeof(I2C_BD)) +
+ (NUM_TX_BDS * sizeof(I2C_BD)) +
+ MAX_TX_SPACE, 8);
}
#else
dpaddr = CPM_I2C_BASE;
* and current CPU rate (we assume sccr dfbgr field is 0;
* divide BRGCLK by 1)
*/
- PRINTD(("[I2C] Setting rate...\n"));
- i2c_setrate (gd->cpu_clk, CONFIG_SYS_I2C_SPEED) ;
+ debug("[I2C] Setting rate...\n");
+ i2c_setrate(gd->cpu_clk, CONFIG_SYS_I2C_SPEED);
/* Set I2C controller in master mode */
i2c->i2c_i2com = 0x01;
/* Set SDMA bus arbitration level to 5 (SDCR) */
- immap->im_siu_conf.sc_sdcr = 0x0001 ;
+ immap->im_siu_conf.sc_sdcr = 0x0001;
/* Initialize Tx/Rx parameters */
iip->iic_rbase = rbase;
iip->iic_tbase = tbase;
- rxbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_rbase]);
- txbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_tbase]);
+ rxbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_rbase]);
+ txbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_tbase]);
- PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
- PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
- PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
- PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
+ debug("[I2C] rbase = %04x\n", iip->iic_rbase);
+ debug("[I2C] tbase = %04x\n", iip->iic_tbase);
+ debug("[I2C] rxbd = %08x\n", (int)rxbd);
+ debug("[I2C] txbd = %08x\n", (int)txbd);
/* Set big endian byte order */
iip->iic_tfcr = 0x10;
/*
* Initialize required parameters if using microcode patch.
*/
- iip->iic_rbptr = iip->iic_rbase;
- iip->iic_tbptr = iip->iic_tbase;
+ iip->iic_rbptr = iip->iic_rbase;
+ iip->iic_tbptr = iip->iic_tbase;
iip->iic_rstate = 0;
iip->iic_tstate = 0;
#else
cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
do {
- __asm__ __volatile__ ("eieio");
+ __asm__ __volatile__("eieio");
} while (cp->cp_cpcr & CPM_CR_FLG);
#endif
i2c->i2c_i2cmr = 0x00;
}
-static void
-i2c_newio(i2c_state_t *state)
+static void i2c_newio(i2c_state_t *state)
{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
- PRINTD(("[I2C] i2c_newio\n"));
+ debug("[I2C] i2c_newio\n");
#ifdef CONFIG_SYS_I2C_UCODE_PATCH
iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
#endif
state->rx_idx = 0;
state->tx_idx = 0;
- state->rxbd = (void*)&cp->cp_dpmem[iip->iic_rbase];
- state->txbd = (void*)&cp->cp_dpmem[iip->iic_tbase];
+ state->rxbd = (void *)&cp->cp_dpmem[iip->iic_rbase];
+ state->txbd = (void *)&cp->cp_dpmem[iip->iic_tbase];
state->tx_space = MAX_TX_SPACE;
- state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
+ state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
state->err_cb = NULL;
- PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
- PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
- PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
+ debug("[I2C] rxbd = %08x\n", (int)state->rxbd);
+ debug("[I2C] txbd = %08x\n", (int)state->txbd);
+ debug("[I2C] tx_buf = %08x\n", (int)state->tx_buf);
/* clear the buffer memory */
memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
i2c_send(i2c_state_t *state,
unsigned char address,
unsigned char secondary_address,
- unsigned int flags,
- unsigned short size,
- unsigned char *dataout)
+ unsigned int flags, unsigned short size, unsigned char *dataout)
{
volatile I2C_BD *txbd;
- int i,j;
+ int i, j;
- PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
- address, secondary_address, flags, size));
+ debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
+ address, secondary_address, flags, size);
/* trying to send message larger than BD */
if (size > I2C_RXTX_LEN)
- return I2CERR_MSG_TOO_LONG;
+ return I2CERR_MSG_TOO_LONG;
/* no more free bds */
if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
- return I2CERR_NO_BUFFERS;
+ return I2CERR_NO_BUFFERS;
- txbd = (I2C_BD *)state->txbd;
+ txbd = (I2C_BD *) state->txbd;
txbd->addr = state->tx_buf;
- PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
+ debug("[I2C] txbd = %08x\n", (int)txbd);
if (flags & I2CF_START_COND) {
- PRINTD(("[I2C] Formatting addresses...\n"));
+ debug("[I2C] Formatting addresses...\n");
if (flags & I2CF_ENABLE_SECONDARY) {
- txbd->length = size + 2; /* Length of msg + dest addr */
+ /* Length of msg + dest addr */
+ txbd->length = size + 2;
+
txbd->addr[0] = address << 1;
txbd->addr[1] = secondary_address;
i = 2;
} else {
- txbd->length = size + 1; /* Length of msg + dest addr */
- txbd->addr[0] = address << 1; /* Write dest addr to BD */
+ /* Length of msg + dest addr */
+ txbd->length = size + 1;
+ /* Write dest addr to BD */
+ txbd->addr[0] = address << 1;
i = 1;
}
} else {
- txbd->length = size; /* Length of message */
+ txbd->length = size; /* Length of message */
i = 0;
}
/* set up txbd */
txbd->status = BD_SC_READY;
if (flags & I2CF_START_COND)
- txbd->status |= BD_I2C_TX_START;
+ txbd->status |= BD_I2C_TX_START;
if (flags & I2CF_STOP_COND)
- txbd->status |= BD_SC_LAST | BD_SC_WRAP;
+ txbd->status |= BD_SC_LAST | BD_SC_WRAP;
/* Copy data to send into buffer */
- PRINTD(("[I2C] copy data...\n"));
+ debug("[I2C] copy data...\n");
for(j = 0; j < size; i++, j++)
- txbd->addr[i] = dataout[j];
+ txbd->addr[i] = dataout[j];
- PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
- txbd->length,
- txbd->status,
- txbd->addr[0],
- txbd->addr[1]));
+ debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
+ txbd->length,
+ txbd->status,
+ txbd->addr[0],
+ txbd->addr[1]);
/* advance state */
state->tx_buf += txbd->length;
state->tx_space -= txbd->length;
state->tx_idx++;
- state->txbd = (void*)(txbd + 1);
+ state->txbd = (void *) (txbd + 1);
return 0;
}
unsigned char address,
unsigned char secondary_address,
unsigned int flags,
- unsigned short size_to_expect,
- unsigned char *datain)
+ unsigned short size_to_expect, unsigned char *datain)
{
volatile I2C_BD *rxbd, *txbd;
- PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags));
+ debug("[I2C] i2c_receive %02d %02d %02d\n",
+ address, secondary_address, flags);
/* Expected to receive too much */
if (size_to_expect > I2C_RXTX_LEN)
- return I2CERR_MSG_TOO_LONG;
+ return I2CERR_MSG_TOO_LONG;
/* no more free bds */
if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
- || state->tx_space < 2)
- return I2CERR_NO_BUFFERS;
+ || state->tx_space < 2)
+ return I2CERR_NO_BUFFERS;
- rxbd = (I2C_BD *)state->rxbd;
- txbd = (I2C_BD *)state->txbd;
+ rxbd = (I2C_BD *) state->rxbd;
+ txbd = (I2C_BD *) state->txbd;
- PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
- PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
+ debug("[I2C] rxbd = %08x\n", (int)rxbd);
+ debug("[I2C] txbd = %08x\n", (int)txbd);
txbd->addr = state->tx_buf;
/* set up TXBD for destination address */
if (flags & I2CF_ENABLE_SECONDARY) {
txbd->length = 2;
- txbd->addr[0] = address << 1; /* Write data */
- txbd->addr[1] = secondary_address; /* Internal address */
+ txbd->addr[0] = address << 1; /* Write data */
+ txbd->addr[1] = secondary_address; /* Internal address */
txbd->status = BD_SC_READY;
} else {
txbd->length = 1 + size_to_expect;
rxbd->status |= BD_SC_WRAP;
}
- PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
- txbd->length,
- txbd->status,
- txbd->addr[0],
- txbd->addr[1]));
- PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
- rxbd->length,
- rxbd->status,
- rxbd->addr[0],
- rxbd->addr[1]));
+ debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
+ txbd->length,
+ txbd->status,
+ txbd->addr[0],
+ txbd->addr[1]);
+ debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
+ rxbd->length,
+ rxbd->status,
+ rxbd->addr[0],
+ rxbd->addr[1]);
/* advance state */
state->tx_buf += txbd->length;
state->tx_space -= txbd->length;
state->tx_idx++;
- state->txbd = (void*)(txbd + 1);
+ state->txbd = (void *) (txbd + 1);
state->rx_idx++;
- state->rxbd = (void*)(rxbd + 1);
+ state->rxbd = (void *) (rxbd + 1);
return 0;
}
static int i2c_doio(i2c_state_t *state)
{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
- volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
+ volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
volatile I2C_BD *txbd, *rxbd;
volatile int j = 0;
- PRINTD(("[I2C] i2c_doio\n"));
+ debug("[I2C] i2c_doio\n");
#ifdef CONFIG_SYS_I2C_UCODE_PATCH
iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
#endif
if (state->tx_idx <= 0 && state->rx_idx <= 0) {
- PRINTD(("[I2C] No I/O is queued\n"));
+ debug("[I2C] No I/O is queued\n");
return I2CERR_QUEUE_EMPTY;
}
iip->iic_tbptr = iip->iic_tbase;
/* Enable I2C */
- PRINTD(("[I2C] Enabling I2C...\n"));
+ debug("[I2C] Enabling I2C...\n");
i2c->i2c_i2mod |= 0x01;
/* Begin transmission */
if (state->tx_idx > 0) {
txbd = ((I2C_BD*)state->txbd) - 1;
- PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
- while((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) {
- if (ctrlc()) {
+
+ debug("[I2C] Transmitting...(txbd=0x%08lx)\n",
+ (ulong)txbd);
+
+ while ((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) {
+ if (ctrlc())
return (-1);
- }
- __asm__ __volatile__ ("eieio");
+
+ __asm__ __volatile__("eieio");
}
}
if ((state->rx_idx > 0) && (j < TOUT_LOOP)) {
rxbd = ((I2C_BD*)state->rxbd) - 1;
- PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
- while((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) {
- if (ctrlc()) {
+
+ debug("[I2C] Receiving...(rxbd=0x%08lx)\n",
+ (ulong)rxbd);
+
+ while ((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) {
+ if (ctrlc())
return (-1);
- }
- __asm__ __volatile__ ("eieio");
+
+ __asm__ __volatile__("eieio");
}
}
if ((n = state->tx_idx) > 0) {
for (i = 0; i < n; i++) {
- txbd = ((I2C_BD*)state->txbd) - (n - i);
+ txbd = ((I2C_BD *) state->txbd) - (n - i);
if ((b = txbd->status & BD_I2C_TX_ERR) != 0)
- (*state->err_cb)(I2CECB_TX_ERR|b, i);
+ (*state->err_cb) (I2CECB_TX_ERR | b,
+ i);
}
}
if ((n = state->rx_idx) > 0) {
for (i = 0; i < n; i++) {
- rxbd = ((I2C_BD*)state->rxbd) - (n - i);
+ rxbd = ((I2C_BD *) state->rxbd) - (n - i);
if ((b = rxbd->status & BD_I2C_RX_ERR) != 0)
- (*state->err_cb)(I2CECB_RX_ERR|b, i);
+ (*state->err_cb) (I2CECB_RX_ERR | b,
+ i);
}
}
if (j >= TOUT_LOOP)
- (*state->err_cb)(I2CECB_TIMEOUT, 0);
+ (*state->err_cb) (I2CECB_TIMEOUT, 0);
}
return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0;
static int had_tx_nak;
-static void
-i2c_test_callback(int flags, int xnum)
+static void i2c_test_callback(int flags, int xnum)
{
if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK))
had_tx_nak = 1;
state.err_cb = i2c_test_callback;
had_tx_nak = 0;
- rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf);
+ rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1,
+ buf);
if (rc != 0)
return (rc);
xaddr[0] = (addr >> 24) & 0xFF;
xaddr[1] = (addr >> 16) & 0xFF;
- xaddr[2] = (addr >> 8) & 0xFF;
- xaddr[3] = addr & 0xFF;
+ xaddr[2] = (addr >> 8) & 0xFF;
+ xaddr[3] = addr & 0xFF;
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
* be one byte because the extra address bits are hidden in the
* chip address.
*/
- chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
i2c_newio(&state);
- rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
+ rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
+ &xaddr[4 - alen]);
if (rc != 0) {
printf("i2c_read: i2c_send failed (%d)\n", rc);
return 1;
xaddr[0] = (addr >> 24) & 0xFF;
xaddr[1] = (addr >> 16) & 0xFF;
- xaddr[2] = (addr >> 8) & 0xFF;
- xaddr[3] = addr & 0xFF;
+ xaddr[2] = (addr >> 8) & 0xFF;
+ xaddr[3] = addr & 0xFF;
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
* be one byte because the extra address bits are hidden in the
* chip address.
*/
- chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
i2c_newio(&state);
- rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
+ rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
+ &xaddr[4 - alen]);
if (rc != 0) {
printf("i2c_write: first i2c_send failed (%d)\n", rc);
return 1;
return 0;
}
-#endif /* CONFIG_HARD_I2C */
+#endif /* CONFIG_HARD_I2C */
volatile spi_t *spi;
volatile immap_t *immr;
- volatile cpic8xx_t *cpi;
volatile cpm8xx_t *cp;
- volatile iop8xx_t *iop;
volatile cbd_t *tbdf, *rbdf;
immr = (immap_t *) CONFIG_SYS_IMMR;
- cpi = (cpic8xx_t *)&immr->im_cpic;
- iop = (iop8xx_t *) &immr->im_ioport;
cp = (cpm8xx_t *) &immr->im_cpm;
#ifdef CONFIG_SYS_SPI_UCODE_PATCH
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/io.h>
+#include <linux/compiler.h>
#ifdef CONFIG_ADDR_MAP
#include <addr_map.h>
int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
{
- int batn = -1;
+ __maybe_unused int batn = -1;
sync();
/*
- * (C) Copyright 2000-2010
+ * (C) Copyright 2000-2011
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#endif
#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
-extern int update_flash_size (int flash_size);
+extern int update_flash_size(int flash_size);
#endif
#if defined(CONFIG_SC3)
#endif
#if defined(CONFIG_CMD_DOC)
-void doc_init (void);
+void doc_init(void);
#endif
#if defined(CONFIG_HARD_I2C) || \
defined(CONFIG_SOFT_I2C)
#include <bedbug/type.h>
#endif
-/************************************************************************
- * Utilities *
- ************************************************************************
+/*
+ * Utilities
*/
/*
* argument, and returns an integer return code, where 0 means
* "continue" and != 0 means "fatal error, hang the system".
*/
-typedef int (init_fnc_t) (void);
+typedef int (init_fnc_t)(void);
-/************************************************************************
- * Init Utilities *
- ************************************************************************
+/*
+ * Init Utilities
+ *
* Some of this code should be moved into the core functions,
* but let's get it working (again) first...
*/
-static int init_baudrate (void)
+static int init_baudrate(void)
{
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
return 0;
{
/* please define platform specific board_add_ram_info() */
}
-void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info")));
+
+void board_add_ram_info(int)
+ __attribute__ ((weak, alias("__board_add_ram_info")));
int __board_flash_wp_on(void)
{
*/
return 0;
}
-int board_flash_wp_on(void) __attribute__((weak, alias("__board_flash_wp_on")));
+
+int board_flash_wp_on(void)
+ __attribute__ ((weak, alias("__board_flash_wp_on")));
void __cpu_secondary_init_r(void)
{
}
+
void cpu_secondary_init_r(void)
-__attribute__((weak, alias("__cpu_secondary_init_r")));
+ __attribute__ ((weak, alias("__cpu_secondary_init_r")));
-static int init_func_ram (void)
+static int init_func_ram(void)
{
#ifdef CONFIG_BOARD_TYPES
int board_type = gd->board_type;
#else
int board_type = 0; /* use dummy arg */
#endif
- puts ("DRAM: ");
+ puts("DRAM: ");
- if ((gd->ram_size = initdram (board_type)) > 0) {
- print_size (gd->ram_size, "");
+ gd->ram_size = initdram(board_type);
+
+ if (gd->ram_size > 0) {
+ print_size(gd->ram_size, "");
board_add_ram_info(0);
putc('\n');
- return (0);
+ return 0;
}
- puts (failed);
- return (1);
+ puts(failed);
+ return 1;
}
/***********************************************************************/
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
-static int init_func_i2c (void)
+static int init_func_i2c(void)
{
- puts ("I2C: ");
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- puts ("ready\n");
- return (0);
+ puts("I2C: ");
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ puts("ready\n");
+ return 0;
}
#endif
#if defined(CONFIG_HARD_SPI)
-static int init_func_spi (void)
+static int init_func_spi(void)
{
- puts ("SPI: ");
- spi_init ();
- puts ("ready\n");
- return (0);
+ puts("SPI: ");
+ spi_init();
+ puts("ready\n");
+ return 0;
}
#endif
/***********************************************************************/
#if defined(CONFIG_WATCHDOG)
-static int init_func_watchdog_init (void)
+static int init_func_watchdog_init(void)
{
- puts (" Watchdog enabled\n");
- WATCHDOG_RESET ();
- return (0);
+ puts(" Watchdog enabled\n");
+ WATCHDOG_RESET();
+ return 0;
}
-# define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init,
-static int init_func_watchdog_reset (void)
+#define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init,
+
+static int init_func_watchdog_reset(void)
{
- WATCHDOG_RESET ();
- return (0);
+ WATCHDOG_RESET();
+ return 0;
}
-# define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset,
+
+#define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset,
#else
-# define INIT_FUNC_WATCHDOG_INIT /* undef */
-# define INIT_FUNC_WATCHDOG_RESET /* undef */
+#define INIT_FUNC_WATCHDOG_INIT /* undef */
+#define INIT_FUNC_WATCHDOG_RESET /* undef */
#endif /* CONFIG_WATCHDOG */
-/************************************************************************
- * Initialization sequence *
- ************************************************************************
+/*
+ * Initialization sequence
*/
init_fnc_t *init_sequence[] = {
#endif
env_init,
#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
- get_clocks_866, /* get CPU and bus clocks according to the environment variable */
- sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */
+ /* get CPU and bus clocks according to the environment variable */
+ get_clocks_866,
+ /* adjust sdram refresh rate according to the new clock */
+ sdram_adjust_866,
init_timebase,
#endif
init_baudrate,
#ifdef CONFIG_POST
post_init_f,
#endif
- INIT_FUNC_WATCHDOG_RESET
- init_func_ram,
+ INIT_FUNC_WATCHDOG_RESET init_func_ram,
#if defined(CONFIG_SYS_DRAM_TEST)
testdram,
#endif /* CONFIG_SYS_DRAM_TEST */
INIT_FUNC_WATCHDOG_RESET
-
- NULL, /* Terminate this list */
+ NULL, /* Terminate this list */
};
ulong get_effective_memsize(void)
#else
/* limit stack to what we can reasonable map */
return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
- CONFIG_MAX_MEM_MAPPED : gd->ram_size);
+ CONFIG_MAX_MEM_MAPPED : gd->ram_size);
#endif
}
-/************************************************************************
- *
+/*
* This is the first part of the initialization sequence that is
* implemented in C, but still running from ROM.
*
*
* Be aware of the restrictions: global data is read-only, BSS is not
* initialized, and stack space is limited to a few kB.
- *
- ************************************************************************
*/
#ifdef CONFIG_LOGBUFFER
}
#endif
-void board_init_f (ulong bootflag)
+void board_init_f(ulong bootflag)
{
bd_t *bd;
ulong len, addr, addr_sp;
ulong *s;
gd_t *id;
init_fnc_t **init_fnc_ptr;
+
#ifdef CONFIG_PRAM
ulong reg;
#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* compiler optimization barrier needed for GCC >= 3.4 */
- __asm__ __volatile__("": : :"memory");
+ __asm__ __volatile__("":::"memory");
#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
!defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
!defined(CONFIG_MPC86xx)
/* Clear initial global data */
- memset ((void *) gd, 0, sizeof (gd_t));
+ memset((void *) gd, 0, sizeof(gd_t));
#endif
- for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
- if ((*init_fnc_ptr) () != 0) {
- hang ();
- }
- }
+ for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr)
+ if ((*init_fnc_ptr) () != 0)
+ hang();
#ifdef CONFIG_POST
post_bootmode_init();
*/
if (addr > determine_mp_bootpg()) {
addr = determine_mp_bootpg();
- debug ("Reserving MP boot page to %08lx\n", addr);
+ debug("Reserving MP boot page to %08lx\n", addr);
}
#endif
#ifndef CONFIG_ALT_LB_ADDR
/* reserve kernel log buffer */
addr -= (LOGBUFF_RESERVE);
- debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr);
+ debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
+ addr);
#endif
#endif
* reserve protected RAM
*/
reg = getenv_ulong("pram", 10, CONFIG_PRAM);
- addr -= (reg << 10); /* size is in kB */
+ addr -= (reg << 10); /* size is in kB */
debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
#endif /* CONFIG_PRAM */
/* round down to next 4 kB limit */
addr &= ~(4096 - 1);
- debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
+ debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
#ifdef CONFIG_LCD
#ifdef CONFIG_FB_ADDR
gd->fb_base = CONFIG_FB_ADDR;
#else
/* reserve memory for LCD display (always full pages) */
- addr = lcd_setmem (addr);
+ addr = lcd_setmem(addr);
gd->fb_base = addr;
#endif /* CONFIG_FB_ADDR */
#endif /* CONFIG_LCD */
#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx)
/* reserve memory for video display (always full pages) */
- addr = video_setmem (addr);
+ addr = video_setmem(addr);
gd->fb_base = addr;
#endif /* CONFIG_VIDEO */
addr &= ~(65536 - 1);
#endif
- debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
+ debug("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
/*
* reserve memory for malloc() arena
*/
addr_sp = addr - TOTAL_MALLOC_LEN;
- debug ("Reserving %dk for malloc() at: %08lx\n",
- TOTAL_MALLOC_LEN >> 10, addr_sp);
+ debug("Reserving %dk for malloc() at: %08lx\n",
+ TOTAL_MALLOC_LEN >> 10, addr_sp);
/*
* (permanently) allocate a Board Info struct
* and a permanent copy of the "global" data
*/
- addr_sp -= sizeof (bd_t);
+ addr_sp -= sizeof(bd_t);
bd = (bd_t *) addr_sp;
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
- debug ("Reserving %zu Bytes for Board Info at: %08lx\n",
- sizeof (bd_t), addr_sp);
- addr_sp -= sizeof (gd_t);
+ debug("Reserving %zu Bytes for Board Info at: %08lx\n",
+ sizeof(bd_t), addr_sp);
+ addr_sp -= sizeof(gd_t);
id = (gd_t *) addr_sp;
- debug ("Reserving %zu Bytes for Global Data at: %08lx\n",
- sizeof (gd_t), addr_sp);
+ debug("Reserving %zu Bytes for Global Data at: %08lx\n",
+ sizeof(gd_t), addr_sp);
/*
* Finally, we set up a new (bigger) stack.
*/
addr_sp -= 16;
addr_sp &= ~0xF;
- s = (ulong *)addr_sp;
+ s = (ulong *) addr_sp;
*s-- = 0;
*s-- = 0;
- addr_sp = (ulong)s;
- debug ("Stack Pointer at: %08lx\n", addr_sp);
+ addr_sp = (ulong) s;
+ debug("Stack Pointer at: %08lx\n", addr_sp);
/*
* Save local variables to board info struct
*/
- bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM memory */
- bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
+ bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
+ bd->bi_memsize = gd->ram_size; /* size in bytes */
#ifdef CONFIG_SYS_SRAM_BASE
- bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM memory */
- bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM memory */
+ bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
+ bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
#endif
#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
#endif
#if defined(CONFIG_MPC8220)
bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
- bd->bi_inpfreq = gd->inp_clk;
- bd->bi_pcifreq = gd->pci_clk;
- bd->bi_vcofreq = gd->vco_clk;
- bd->bi_pevfreq = gd->pev_clk;
- bd->bi_flbfreq = gd->flb_clk;
+ bd->bi_inpfreq = gd->inp_clk;
+ bd->bi_pcifreq = gd->pci_clk;
+ bd->bi_vcofreq = gd->vco_clk;
+ bd->bi_pevfreq = gd->pev_clk;
+ bd->bi_flbfreq = gd->flb_clk;
/* store bootparam to sram (backward compatible), here? */
{
- u32 *sram = (u32 *)CONFIG_SYS_SRAM_BASE;
+ u32 *sram = (u32 *) CONFIG_SYS_SRAM_BASE;
+
*sram++ = gd->ram_size;
*sram++ = gd->bus_clk;
*sram++ = gd->inp_clk;
*sram++ = gd->cpu_clk;
*sram++ = gd->vco_clk;
*sram++ = gd->flb_clk;
- *sram++ = 0xb8c3ba11; /* boot signature */
+ *sram++ = 0xb8c3ba11; /* boot signature */
}
#endif
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
#if defined(CONFIG_CPM2)
bd->bi_cpmfreq = gd->cpm_clk;
bd->bi_brgfreq = gd->brg_clk;
bd->bi_sccfreq = gd->scc_clk;
- bd->bi_vco = gd->vco_out;
+ bd->bi_vco = gd->vco_out;
#endif /* CONFIG_CPM2 */
#if defined(CONFIG_MPC512X)
bd->bi_ipsfreq = gd->ips_clk;
bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
#ifdef CONFIG_SYS_EXTBDINFO
- strncpy ((char *)bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
- strncpy ((char *)bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version));
+ strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
+ strncpy((char *) bd->bi_r_version, U_BOOT_VERSION,
+ sizeof(bd->bi_r_version));
bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
bd->bi_plb_busfreq = gd->bus_clk;
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
- bd->bi_pci_busfreq = get_PCI_freq ();
- bd->bi_opbfreq = get_OPB_freq ();
+ bd->bi_pci_busfreq = get_PCI_freq();
+ bd->bi_opbfreq = get_OPB_freq();
#elif defined(CONFIG_XILINX_405)
- bd->bi_pci_busfreq = get_PCI_freq ();
+ bd->bi_pci_busfreq = get_PCI_freq();
#endif
#endif
- debug ("New Stack Pointer is: %08lx\n", addr_sp);
+ debug("New Stack Pointer is: %08lx\n", addr_sp);
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
- gd->relocaddr = addr; /* Record relocation address, useful for debug */
+ gd->relocaddr = addr; /* Store relocation addr, useful for debug */
- memcpy (id, (void *)gd, sizeof (gd_t));
+ memcpy(id, (void *) gd, sizeof(gd_t));
- relocate_code (addr_sp, id, addr);
+ relocate_code(addr_sp, id, addr);
/* NOTREACHED - relocate_code() does not return */
}
-/************************************************************************
- *
+/*
* This is the next part if the initialization sequence: we are now
* running from RAM and have a "normal" C environment, i. e. global
* data can be written, BSS has been cleared, the stack size in not
* that critical any more, etc.
- *
- ************************************************************************
*/
-void board_init_r (gd_t *id, ulong dest_addr)
+void board_init_r(gd_t *id, ulong dest_addr)
{
bd_t *bd;
ulong malloc_start;
-#if defined(CONFIG_SYS_FLASH_CHECKSUM) || defined(CONFIG_CMD_NET)
- char *s;
-#endif
+
#ifndef CONFIG_SYS_NO_FLASH
ulong flash_size;
#endif
serial_initialize();
#endif
- debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
+ debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
/*
* Setup trap handlers
*/
- trap_init (dest_addr);
+ trap_init(dest_addr);
#ifdef CONFIG_ADDR_MAP
init_addr_map();
#endif
#if defined(CONFIG_BOARD_EARLY_INIT_R)
- board_early_init_r ();
+ board_early_init_r();
#endif
monitor_flash_len = (ulong)&__init_end - dest_addr;
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
#ifdef CONFIG_LOGBUFFER
- logbuff_init_ptrs ();
+ logbuff_init_ptrs();
#endif
#ifdef CONFIG_POST
- post_output_backlog ();
+ post_output_backlog();
#endif
WATCHDOG_RESET();
#if defined(CONFIG_SYS_DELAYED_ICACHE)
- icache_enable (); /* it's time to enable the instruction cache */
+ icache_enable(); /* it's time to enable the instruction cache */
#endif
#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
* Do early PCI configuration _before_ the flash gets initialised,
* because PCU ressources are crucial for flash access on some boards.
*/
- pci_init ();
+ pci_init();
#endif
#if defined(CONFIG_WINBOND_83C553)
/*
* Initialise the ISA bridge
*/
- initialise_w83c553f ();
+ initialise_w83c553f();
#endif
- asm ("sync ; isync");
+ asm("sync ; isync");
- mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
+ mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
#if !defined(CONFIG_SYS_NO_FLASH)
- puts ("Flash: ");
+ puts("Flash: ");
if (board_flash_wp_on()) {
printf("Uninitialized - Write Protect On\n");
/* Since WP is on, we can't find real size. Set to 0 */
flash_size = 0;
- } else if ((flash_size = flash_init ()) > 0) {
-# ifdef CONFIG_SYS_FLASH_CHECKSUM
+ } else if ((flash_size = flash_init()) > 0) {
+#ifdef CONFIG_SYS_FLASH_CHECKSUM
char *s;
- print_size (flash_size, "");
+ print_size(flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
- s = getenv ("flashchecksum");
+ s = getenv("flashchecksum");
if (s && (*s == 'y')) {
- printf (" CRC: %08X",
- crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size)
- );
+ printf(" CRC: %08X",
+ crc32(0,
+ (const unsigned char *)
+ CONFIG_SYS_FLASH_BASE, flash_size)
+ );
}
- putc ('\n');
-# else /* !CONFIG_SYS_FLASH_CHECKSUM */
- print_size (flash_size, "\n");
-# endif /* CONFIG_SYS_FLASH_CHECKSUM */
+ putc('\n');
+#else /* !CONFIG_SYS_FLASH_CHECKSUM */
+ print_size(flash_size, "\n");
+#endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
- puts (failed);
- hang ();
+ puts(failed);
+ hang();
}
- bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; /* update start of FLASH memory */
- bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
+ /* update start of FLASH memory */
+ bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+ /* size of FLASH memory (final value) */
+ bd->bi_flashsize = flash_size;
#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
/* Make a update of the Memctrl. */
- update_flash_size (flash_size);
+ update_flash_size(flash_size);
#endif
-# if defined(CONFIG_OXC) || defined(CONFIG_RMU)
+#if defined(CONFIG_OXC) || defined(CONFIG_RMU)
/* flash mapped at end of memory map */
bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size;
-# elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
- bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */
-# endif
+#elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
+ bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */
+#endif
#endif /* !CONFIG_SYS_NO_FLASH */
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
/* initialize higher level parts of CPU like time base and timers */
- cpu_init_r ();
+ cpu_init_r();
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
#ifdef CONFIG_SPI
-# if !defined(CONFIG_ENV_IS_IN_EEPROM)
- spi_init_f ();
-# endif
- spi_init_r ();
+#if !defined(CONFIG_ENV_IS_IN_EEPROM)
+ spi_init_f();
+#endif
+ spi_init_r();
#endif
#if defined(CONFIG_CMD_NAND)
- WATCHDOG_RESET ();
- puts ("NAND: ");
+ WATCHDOG_RESET();
+ puts("NAND: ");
nand_init(); /* go init the NAND */
#endif
* Thus It is required that operations like pin multiplexer
* be put in board_init.
*/
- WATCHDOG_RESET ();
- puts ("MMC: ");
- mmc_initialize (bd);
+ WATCHDOG_RESET();
+ puts("MMC: ");
+ mmc_initialize(bd);
#endif
/* relocate environment function pointers etc. */
- env_relocate ();
+ env_relocate();
/*
* after non-volatile devices & environment is setup and cpu code have
* "i2cfast" into account
*/
{
- char *s = getenv ("i2cfast");
+ char *s = getenv("i2cfast");
+
if (s && ((*s == 'y') || (*s == 'Y'))) {
bd->bi_iic_fast[0] = 1;
bd->bi_iic_fast[1] = 1;
}
}
-#endif /* CONFIG_I2CFAST */
-#endif /* CONFIG_405GP, CONFIG_405EP */
-#endif /* CONFIG_SYS_EXTBDINFO */
+#endif /* CONFIG_I2CFAST */
+#endif /* CONFIG_405GP, CONFIG_405EP */
+#endif /* CONFIG_SYS_EXTBDINFO */
#if defined(CONFIG_SC3)
sc3_read_eeprom();
#endif
-#if defined (CONFIG_ID_EEPROM) || defined (CONFIG_SYS_I2C_MAC_OFFSET)
+#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
mac_read_from_eeprom();
#endif
#endif /* CONFIG_CMD_NET */
/* IP Address */
- bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
+ bd->bi_ip_addr = getenv_IPaddr("ipaddr");
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT)
/*
* Do pci configuration
*/
- pci_init ();
+ pci_init();
#endif
/** leave this here (after malloc(), environment and PCI are working) **/
/* Initialize stdio devices */
- stdio_init ();
+ stdio_init();
/* Initialize the jump table for applications */
- jumptable_init ();
+ jumptable_init();
#if defined(CONFIG_API)
/* Initialize API */
- api_init ();
+ api_init();
#endif
/* Initialize the console (after the relocation and devices init) */
- console_init_r ();
+ console_init_r();
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
- misc_init_r ();
+ misc_init_r();
#endif
#ifdef CONFIG_HERMES
if (bd->bi_ethspeed != 0xFFFF)
- hermes_start_lxt980 ((int) bd->bi_ethspeed);
+ hermes_start_lxt980((int) bd->bi_ethspeed);
#endif
#if defined(CONFIG_CMD_KGDB)
- WATCHDOG_RESET ();
- puts ("KGDB: ");
- kgdb_init ();
+ WATCHDOG_RESET();
+ puts("KGDB: ");
+ kgdb_init();
#endif
- debug ("U-Boot relocated to %08lx\n", dest_addr);
+ debug("U-Boot relocated to %08lx\n", dest_addr);
/*
* Enable Interrupts
*/
- interrupt_init ();
+ interrupt_init();
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
- status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
#endif
- udelay (20);
+ udelay(20);
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
}
#endif
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
#if defined(CONFIG_CMD_SCSI)
- WATCHDOG_RESET ();
- puts ("SCSI: ");
- scsi_init ();
+ WATCHDOG_RESET();
+ puts("SCSI: ");
+ scsi_init();
#endif
#if defined(CONFIG_CMD_DOC)
- WATCHDOG_RESET ();
- puts ("DOC: ");
- doc_init ();
+ WATCHDOG_RESET();
+ puts("DOC: ");
+ doc_init();
#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
- WATCHDOG_RESET ();
- puts ("Net: ");
- eth_initialize (bd);
+ WATCHDOG_RESET();
+ puts("Net: ");
+ eth_initialize(bd);
#endif
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
- WATCHDOG_RESET ();
- debug ("Reset Ethernet PHY\n");
- reset_phy ();
+ WATCHDOG_RESET();
+ debug("Reset Ethernet PHY\n");
+ reset_phy();
#endif
#ifdef CONFIG_POST
- post_run (NULL, POST_RAM | post_bootmode_get(0));
+ post_run(NULL, POST_RAM | post_bootmode_get(0));
#endif
#if defined(CONFIG_CMD_PCMCIA) \
&& !defined(CONFIG_CMD_IDE)
- WATCHDOG_RESET ();
- puts ("PCMCIA:");
- pcmcia_init ();
+ WATCHDOG_RESET();
+ puts("PCMCIA:");
+ pcmcia_init();
#endif
#if defined(CONFIG_CMD_IDE)
- WATCHDOG_RESET ();
-# ifdef CONFIG_IDE_8xx_PCCARD
- puts ("PCMCIA:");
-# else
- puts ("IDE: ");
+ WATCHDOG_RESET();
+#ifdef CONFIG_IDE_8xx_PCCARD
+ puts("PCMCIA:");
+#else
+ puts("IDE: ");
#endif
#if defined(CONFIG_START_IDE)
if (board_start_ide())
- ide_init ();
+ ide_init();
#else
- ide_init ();
+ ide_init();
#endif
#endif
#ifdef CONFIG_LAST_STAGE_INIT
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
/*
* Some parts can be only initialized if all others (like
* Interrupts) are up and running (i.e. the PC-style ISA
* keyboard).
*/
- last_stage_init ();
+ last_stage_init();
#endif
#if defined(CONFIG_CMD_BEDBUG)
- WATCHDOG_RESET ();
- bedbug_init ();
+ WATCHDOG_RESET();
+ bedbug_init();
#endif
#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
#ifdef CONFIG_LOGBUFFER
#ifndef CONFIG_ALT_LB_ADDR
/* Also take the logbuffer into account (pram is in kB) */
- pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024;
+ pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
#endif
#endif
- sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
- setenv ("mem", (char *)memsz);
+ sprintf((char *) memsz, "%ldk",
+ (bd->bi_memsize / 1024) - pram);
+ setenv("mem", (char *) memsz);
}
#endif
#ifdef CONFIG_PS2KBD
- puts ("PS/2: ");
+ puts("PS/2: ");
kbd_init();
#endif
#ifdef CONFIG_MODEM_SUPPORT
- {
- extern int do_mdm_init;
- do_mdm_init = gd->do_mdm_init;
- }
+ {
+ extern int do_mdm_init;
+
+ do_mdm_init = gd->do_mdm_init;
+ }
#endif
/* Initialization complete - start the monitor */
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;) {
- WATCHDOG_RESET ();
- main_loop ();
+ WATCHDOG_RESET();
+ main_loop();
}
/* NOTREACHED - no way out of command loop except booting */
}
-void hang (void)
+void hang(void)
{
- puts ("### ERROR ### Please RESET the board ###\n");
+ puts("### ERROR ### Please RESET the board ###\n");
show_boot_progress(-30);
- for (;;);
+ for (;;)
+ ;
}
-#if 0 /* We could use plain global data, but the resulting code is bigger */
+#if 0 /* We could use plain global data, but the resulting code is bigger */
/*
* Pointer to initial global data area
*
*/
#undef XTRN_DECLARE_GLOBAL_DATA_PTR
#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
-DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-#endif /* 0 */
+DECLARE_GLOBAL_DATA_PTR =
+ (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+#endif /* 0 */
/************************************************************************/
# MA 02111-1307 USA
#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/textbase.mk
ifndef CONFIG_SYS_TEXT_BASE
CONFIG_SYS_TEXT_BASE = 0xFE000000
endif
+++ /dev/null
-CONFIG_SYS_TEXT_BASE = 0xFFE00000
--- /dev/null
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := flea3.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+
+#ifndef CONFIG_BOARD_EARLY_INIT_F
+#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
+#endif
+
+#define CCM_CCMR_CONFIG 0x003F4208
+
+#define ESDCTL_DDR2_CONFIG 0x007FFC3F
+#define ESDCTL_0x92220000 0x92220000
+#define ESDCTL_0xA2220000 0xA2220000
+#define ESDCTL_0xB2220000 0xB2220000
+#define ESDCTL_0x82228080 0x82228080
+#define ESDCTL_DDR2_EMR2 0x04000000
+#define ESDCTL_DDR2_EMR3 0x06000000
+#define ESDCTL_PRECHARGE 0x00000400
+#define ESDCTL_DDR2_EN_DLL 0x02000400
+#define ESDCTL_DDR2_RESET_DLL 0x00000333
+#define ESDCTL_DDR2_MR 0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+#define ESDCTL_DELAY_LINE5 0x00F49F00
+
+static inline void dram_wait(unsigned int count)
+{
+ volatile unsigned int wait = count;
+
+ while (wait--)
+ ;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+static void board_setup_sdram_bank(u32 start_address)
+
+{
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+ u32 *cfg_reg, *ctl_reg;
+ u32 val;
+
+ switch (start_address) {
+ case CSD0_BASE_ADDR:
+ cfg_reg = &esdc->esdcfg0;
+ ctl_reg = &esdc->esdctl0;
+ break;
+ case CSD1_BASE_ADDR:
+ cfg_reg = &esdc->esdcfg1;
+ ctl_reg = &esdc->esdctl1;
+ break;
+ default:
+ return;
+ }
+
+ /* Initialize MISC register for DDR2 */
+ val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+ ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+ writel(val, &esdc->esdmisc);
+ val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+ writel(val, &esdc->esdmisc);
+
+ /*
+ * according to DDR2 specs, wait a while before
+ * the PRECHARGE_ALL command
+ */
+ dram_wait(0x20000);
+
+ /* Load DDR2 config and timing */
+ writel(ESDCTL_DDR2_CONFIG, cfg_reg);
+
+ /* Precharge ALL */
+ writel(ESDCTL_0x92220000,
+ ctl_reg);
+ writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+ /* Load mode */
+ writel(ESDCTL_0xB2220000,
+ ctl_reg);
+ writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
+ writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
+ writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+ writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+ /* Precharge ALL */
+ writel(ESDCTL_0x92220000,
+ ctl_reg);
+ writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+ /* Set mode auto refresh : at least two refresh are required */
+ writel(ESDCTL_0xA2220000,
+ ctl_reg);
+ writel(0xda, start_address);
+ writel(0xda, start_address);
+
+ writel(ESDCTL_0xB2220000,
+ ctl_reg);
+ writeb(0xda, start_address + ESDCTL_DDR2_MR);
+ writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
+
+ /* OCD mode exit */
+ writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+ /* Set normal mode */
+ writel(ESDCTL_0x82228080,
+ ctl_reg);
+
+ dram_wait(0x20000);
+
+ /* Do not set delay lines, only for MDDR */
+}
+
+static void board_setup_sdram(void)
+{
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+ /* Initialize with default values both CSD0/1 */
+ writel(0x2000, &esdc->esdctl0);
+ writel(0x2000, &esdc->esdctl1);
+
+ board_setup_sdram_bank(CSD1_BASE_ADDR);
+}
+
+static void setup_iomux_uart3(void)
+{
+ mxc_request_iomux(MX35_PIN_RTS2_UART3_RXD_MUX, MUX_CONFIG_ALT7);
+ mxc_request_iomux(MX35_PIN_CTS2_UART3_TXD_MUX, MUX_CONFIG_ALT7);
+}
+
+static void setup_iomux_i2c(void)
+{
+ int pad;
+
+ mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
+
+ pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
+ | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
+
+ mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
+ mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+
+ mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1);
+ mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1);
+
+ mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad);
+ mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad);
+}
+
+
+static void setup_iomux_spi(void)
+{
+ mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+}
+
+static void setup_iomux_fec(void)
+{
+ /* setup pins for FEC */
+ mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+
+}
+
+int board_early_init_f(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ /* setup GPIO3_1 to set HighVCore signal */
+ mxc_request_iomux(MX35_PIN_ATA_DATA1, MUX_CONFIG_ALT5);
+ gpio_direction_output(65, 1);
+
+ /* initialize PLL and clock configuration */
+ writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+ writel(CCM_MPLL_532_HZ, &ccm->mpctl);
+ writel(CCM_PPLL_300_HZ, &ccm->ppctl);
+
+ /* Set the core to run at 532 Mhz */
+ writel(0x00001000, &ccm->pdr0);
+
+ /* Set-up RAM */
+ board_setup_sdram();
+
+ /* enable clocks */
+ writel(readl(&ccm->cgr0) |
+ MXC_CCM_CGR0_EMI_MASK |
+ MXC_CCM_CGR0_EDI0_MASK |
+ MXC_CCM_CGR0_EPIT1_MASK,
+ &ccm->cgr0);
+
+ writel(readl(&ccm->cgr1) |
+ MXC_CCM_CGR1_FEC_MASK |
+ MXC_CCM_CGR1_GPIO1_MASK |
+ MXC_CCM_CGR1_GPIO2_MASK |
+ MXC_CCM_CGR1_GPIO3_MASK |
+ MXC_CCM_CGR1_I2C1_MASK |
+ MXC_CCM_CGR1_I2C2_MASK |
+ MXC_CCM_CGR1_I2C3_MASK,
+ &ccm->cgr1);
+
+ /* Set-up NAND */
+ __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+ /* Set pinmux for the required peripherals */
+ setup_iomux_uart3();
+ setup_iomux_i2c();
+ setup_iomux_fec();
+ setup_iomux_spi();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ int rev = 0;
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * Configuration for the flea3 board.
+ * These defines are used by the included macros and must
+ * be defined first
+ */
+#define AIPS_MPR_CONFIG 0x77777777
+#define AIPS_OPACR_CONFIG 0x00000000
+
+/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_MPR_CONFIG 0x00302154
+
+/* SGPCR - always park on last master */
+#define MAX_SGPCR_CONFIG 0x00000010
+
+/* MGPCR - restore default values */
+#define MAX_MGPCR_CONFIG 0x00000000
+
+/*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+#define M3IF_CONFIG 0x00000040
+
+#define CCM_PDR0_CONFIG 0x00801000
+
+/*
+ * includes MX35 utility macros
+ */
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+ core_init
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ mov pc, lr
--- /dev/null
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000618 # DDR Configuration register
+# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x00000008 # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 10, Cs0size=512Mb
+# bit5-4: 00, Cs2width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000632 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 1, DDR drive strenght reduced
+# bit2: 1, DDR ODT control lsd enabled
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, enabled
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 1 , D2P Latency enabled
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
+# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
+# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
# bit12-11: TW2W
# bit31-13: zero required
-DATA 0xFFD01410 0x0000CCCC # DDR Address Control
-# bit1-0: 01, Cs0width=x16
+DATA 0xFFD01410 0x0000000C # DDR Address Control
+# bit1-0: 00, Cs0width=x8
# bit3-2: 11, Cs0size=1Gb
# bit5-4: 00, Cs2width=nonexistent
# bit7-6: 00, Cs1size =nonexistent
#include <miiphy.h>
#include <netdev.h>
#include <command.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
#include <asm/arch/gpio.h>
#include <common.h>
#include <miiphy.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
#include "dreamplug.h"
#include <miiphy.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
#include "dockstar.h"
DECLARE_GLOBAL_DATA_PTR;
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+SOBJS :=
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <linux/mtd/nand.h>
+#include <nand.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/nand_defs.h>
+#include <asm/arch/davinci_misc.h>
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SPL_BUILD
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_MAX_RAM_BANK_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+static struct davinci_timer *timer =
+ (struct davinci_timer *)DAVINCI_TIMER3_BASE;
+
+static unsigned long get_timer_val(void)
+{
+ unsigned long now = readl(&timer->tim34);
+
+ return now;
+}
+
+static void stop_timer(void)
+{
+ writel(0x0, &timer->tcr);
+ return;
+}
+
+int checkboard(void)
+{
+ printf("Board: AIT CAM ENC 4XX\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+int board_eth_init(bd_t *bis)
+{
+ davinci_emac_initialize();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+static int
+davinci_std_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int page)
+{
+ struct nand_chip *this = mtd->priv;
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ uint8_t *p = buf;
+ uint8_t *oob = chip->oob_poi;
+
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
+
+ chip->read_buf(mtd, oob, mtd->oobsize);
+
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page & this->pagemask);
+
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ int stat;
+
+ chip->ecc.hwctl(mtd, NAND_ECC_READ);
+ chip->read_buf(mtd, p, eccsize);
+ chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
+
+ if (chip->ecc.prepad)
+ oob += chip->ecc.prepad;
+
+ stat = chip->ecc.correct(mtd, p, oob, NULL);
+
+ if (stat == -1)
+ mtd->ecc_stats.failed++;
+ else
+ mtd->ecc_stats.corrected += stat;
+
+ oob += eccbytes;
+
+ if (chip->ecc.postpad)
+ oob += chip->ecc.postpad;
+ }
+
+ /* Calculate remaining oob bytes */
+ i = mtd->oobsize - (oob - chip->oob_poi);
+ if (i)
+ chip->read_buf(mtd, oob, i);
+
+ return 0;
+}
+
+static void davinci_std_write_page_syndrome(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf)
+{
+ unsigned char davinci_ecc_buf[NAND_MAX_OOBSIZE];
+ struct nand_chip *this = mtd->priv;
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
+ int offset = 0;
+ const uint8_t *p = buf;
+ uint8_t *oob = chip->oob_poi;
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+ chip->write_buf(mtd, p, eccsize);
+
+ /* Calculate ECC without prepad */
+ chip->ecc.calculate(mtd, p, oob + chip->ecc.prepad);
+
+ if (chip->ecc.prepad) {
+ offset = (chip->ecc.steps - eccsteps) * chunk;
+ memcpy(&davinci_ecc_buf[offset], oob, chip->ecc.prepad);
+ oob += chip->ecc.prepad;
+ }
+
+ offset = ((chip->ecc.steps - eccsteps) * chunk) +
+ chip->ecc.prepad;
+ memcpy(&davinci_ecc_buf[offset], oob, eccbytes);
+ oob += eccbytes;
+
+ if (chip->ecc.postpad) {
+ offset = ((chip->ecc.steps - eccsteps) * chunk) +
+ chip->ecc.prepad + eccbytes;
+ memcpy(&davinci_ecc_buf[offset], oob,
+ chip->ecc.postpad);
+ oob += chip->ecc.postpad;
+ }
+ }
+
+ /*
+ * Write the sparebytes into the page once
+ * all eccsteps have been covered
+ */
+ for (i = 0; i < mtd->oobsize; i++)
+ writeb(davinci_ecc_buf[i], this->IO_ADDR_W);
+
+ /* Calculate remaining oob bytes */
+ i = mtd->oobsize - (oob - chip->oob_poi);
+ if (i)
+ chip->write_buf(mtd, oob, i);
+}
+
+static int davinci_std_write_oob_syndrome(struct mtd_info *mtd,
+ struct nand_chip *chip, int page)
+{
+ int pos, status = 0;
+ const uint8_t *bufpoi = chip->oob_poi;
+
+ pos = mtd->writesize;
+
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
+
+ chip->write_buf(mtd, bufpoi, mtd->oobsize);
+
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+ status = chip->waitfunc(mtd, chip);
+
+ return status & NAND_STATUS_FAIL ? -1 : 0;
+}
+
+static int davinci_std_read_oob_syndrome(struct mtd_info *mtd,
+ struct nand_chip *chip, int page, int sndcmd)
+{
+ struct nand_chip *this = mtd->priv;
+ uint8_t *buf = chip->oob_poi;
+ uint8_t *bufpoi = buf;
+
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
+
+ chip->read_buf(mtd, bufpoi, mtd->oobsize);
+
+ return 1;
+}
+
+static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct nand_chip *this = mtd->priv;
+ unsigned long wbase = (unsigned long) this->IO_ADDR_W;
+ unsigned long rbase = (unsigned long) this->IO_ADDR_R;
+
+ if (chip == 1) {
+ __set_bit(14, &wbase);
+ __set_bit(14, &rbase);
+ } else {
+ __clear_bit(14, &wbase);
+ __clear_bit(14, &rbase);
+ }
+ this->IO_ADDR_W = (void *)wbase;
+ this->IO_ADDR_R = (void *)rbase;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ davinci_nand_init(nand);
+ nand->select_chip = nand_dm365evm_select_chip;
+
+ return 0;
+}
+
+struct nand_ecc_ctrl org_ecc;
+static int notsaved = 1;
+
+static int nand_switch_hw_func(int mode)
+{
+ struct nand_chip *nand;
+ struct mtd_info *mtd;
+
+ if (nand_curr_device < 0 ||
+ nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
+ !nand_info[nand_curr_device].name) {
+ printf("Error: Can't switch hw functions," \
+ " no devices available\n");
+ return -1;
+ }
+
+ mtd = &nand_info[nand_curr_device];
+ nand = mtd->priv;
+
+ if (mode == 0) {
+ printf("switching to uboot hw functions.\n");
+ memcpy(&nand->ecc, &org_ecc, sizeof(struct nand_ecc_ctrl));
+ } else {
+ /* RBL */
+ printf("switching to RBL hw functions.\n");
+ if (notsaved == 1) {
+ memcpy(&org_ecc, &nand->ecc,
+ sizeof(struct nand_ecc_ctrl));
+ notsaved = 0;
+ }
+ nand->ecc.mode = NAND_ECC_HW_SYNDROME;
+ nand->ecc.prepad = 6;
+ nand->ecc.read_page = davinci_std_read_page_syndrome;
+ nand->ecc.write_page = davinci_std_write_page_syndrome;
+ nand->ecc.read_oob = davinci_std_read_oob_syndrome;
+ nand->ecc.write_oob = davinci_std_write_oob_syndrome;
+ }
+ return mode;
+}
+
+static int hwmode;
+
+static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (argc != 2)
+ goto usage;
+ if (strncmp(argv[1], "rbl", 2) == 0)
+ hwmode = nand_switch_hw_func(1);
+ else if (strncmp(argv[1], "uboot", 2) == 0)
+ hwmode = nand_switch_hw_func(0);
+ else
+ goto usage;
+
+ return 0;
+
+usage:
+ printf("Usage: nandrbl %s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(
+ nandrbl, 2, 1, do_switch_ecc,
+ "switch between rbl/uboot NAND ECC calculation algorithm",
+ "[rbl/uboot] - Switch between rbl/uboot NAND ECC algorithm"
+);
+
+
+#endif /* #ifdef CONFIG_NAND_DAVINCI */
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .input_clk = 121500000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ int err;
+
+ /* Add slot-0 to mmc subsystem */
+ err = davinci_mmc_init(bis, &mmc_sd0);
+
+ return err;
+}
+#endif
+
+int board_late_init(void)
+{
+ struct davinci_gpio *gpio = davinci_gpio_bank45;
+
+ /* 24MHz InputClock / 15 prediv -> 1.6 MHz timer running */
+ while (get_timer_val() < 0x186a00)
+ ;
+
+ /* 1 sec reached -> stop timer, clear all LED */
+ stop_timer();
+ clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
+ return 0;
+}
+
+void reset_phy(void)
+{
+ char *name = "GENERIC @ 0x00";
+
+ /* reset the phy */
+ miiphy_reset(name, 0x0);
+}
+
+#else /* #ifndef CONFIG_SPL_BUILD */
+static void cam_enc_4xx_set_all_led(void)
+{
+ struct davinci_gpio *gpio = davinci_gpio_bank45;
+
+ setbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
+}
+
+/*
+ * TIMER 0 is used for tick
+ */
+static struct davinci_timer *timer =
+ (struct davinci_timer *)DAVINCI_TIMER3_BASE;
+
+#define TIMER_LOAD_VAL 0xffffffff
+#define TIM_CLK_DIV 16
+
+static int cam_enc_4xx_timer_init(void)
+{
+ /* We are using timer34 in unchained 32-bit mode, full speed */
+ writel(0x0, &timer->tcr);
+ writel(0x0, &timer->tgcr);
+ writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
+ writel(0x0, &timer->tim34);
+ writel(TIMER_LOAD_VAL, &timer->prd34);
+ writel(2 << 22, &timer->tcr);
+ return 0;
+}
+
+void board_gpio_init(void)
+{
+ struct davinci_gpio *gpio;
+
+ cam_enc_4xx_set_all_led();
+ cam_enc_4xx_timer_init();
+ gpio = davinci_gpio_bank01;
+ clrbits_le32(&gpio->dir, ~0xfdfffffe);
+ /* clear LED D14 = GPIO25 */
+ clrbits_le32(&gpio->out_data, 0x02000000);
+ gpio = davinci_gpio_bank23;
+ clrbits_le32(&gpio->dir, ~0x5ff0afef);
+ /* set GPIO61 to 1 -> intern UART0 as Console */
+ setbits_le32(&gpio->out_data, 0x20000000);
+ /*
+ * PHY out of reset GIO 50 = 1
+ * NAND WP off GIO 51 = 1
+ */
+ setbits_le32(&gpio->out_data, 0x000c0004);
+ gpio = davinci_gpio_bank45;
+ clrbits_le32(&gpio->dir, ~(0xdb2fffff) | CONFIG_CAM_ENC_LED_MASK);
+ /*
+ * clear LED:
+ * D17 = GPIO86
+ * D11 = GPIO87
+ * GPIO88
+ * GPIO89
+ * D13 = GPIO90
+ * GPIO91
+ */
+ clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
+ gpio = davinci_gpio_bank67;
+ clrbits_le32(&gpio->dir, ~0x000007ff);
+}
+
+/*
+ * functions for the post memory test.
+ */
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ *vstart = CONFIG_SYS_SDRAM_BASE;
+ *size = PHYS_SDRAM_1_SIZE;
+ *phys_offset = 0;
+ return 0;
+}
+
+void arch_memory_failure_handle(void)
+{
+ cam_enc_4xx_set_all_led();
+ puts("mem failure\n");
+ while (1)
+ ;
+}
+#endif
--- /dev/null
+#
+# AIT cam_enc_4xx board
+# cam_enc_4xx board has 1 bank of 256 MB DDR RAM
+# Physical Address: 8000'0000 to 9000'0000
+#
+# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+PAD_TO := 12320
+UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg
+ifndef CONFIG_SPL_BUILD
+ALL-y += $(obj)u-boot.ubl
+endif
/*
- * (C) Copyright 2011
- * Chander Kashyap, Samsung Electronics, <k.chander@samsung.com>
- *
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2008 Texas Instruments
- *
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* MA 02111-1307 USA
*/
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
. = 0x00000000;
. = ALIGN(4);
- .text :
+ .text :
{
- start.o (.text)
- *(.text)
- }
+ __start = .;
+ arch/arm/cpu/arm926ejs/start.o (.text)
+ *(.text*)
+ } >.sram
. = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
. = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = ALIGN(4);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
-
- __image_copy_end = .;
-
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
__rel_dyn_end = .;
- }
+ } >.sram
.dynsym : {
__dynsym_start = .;
*(.dynsym)
- }
-
- _end = .;
+ } >.sram
- .bss __rel_dyn_start (OVERLAY) : {
+ .bss :
+ {
+ . = ALIGN(4);
__bss_start = .;
- *(.bss)
- . = ALIGN(4);
+ *(.bss*)
+ . = ALIGN(4);
__bss_end__ = .;
- }
+ } >.sram
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
+ __image_copy_end = .;
+ _end = .;
}
--- /dev/null
+#
+# (C Copyright 2011
+# Heiko Schocher DENX Software Engineering hs@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer doc/README.ublimage for more details about how-to configure
+# and create ublimage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# UBL special mode : one of
+# safe (the board has no nand neither onenand)
+MODE safe
+
+# Entry point address for the user bootloader (absolute address)
+# nand spl TEXT_BASE = 0x20 !!
+ENTRY 0x00000020
+
+# Number of pages (size of user bootloader in number of pages)
+# @ nand spl 6 pages
+PAGES 6
+
+# Block number where user bootloader is present
+# RBL starts always with block 1
+START_BLOCK 5
+
+# Page number where user bootloader is present
+# Page 0 is always UBL header
+START_PAGE 0
+
+LD_ADDR 0x20
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0, intel = 0;
if ((s_first < 0) || (s_first > s_last)) {
}
start = get_timer (0);
- last = start;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
printf (" done\n");
}
}
+ if (flag)
+ enable_interrupts();
+
return rcode;
}
{
FPWV *addr = (FPWV *) dest;
ulong start;
- int flag;
+ int flag, rc = 0;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
/* wait while polling the status register */
while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
- return (1);
+ rc = 1;
+ goto OUT;
}
}
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
+OUT:
+ *addr = (FPW)0x00FF00FF; /* restore read mode */
- return (0);
+ if (flag)
+ enable_interrupts();
+
+ return rc;
}
/*-----------------------------------------------------------------------
FPWV *srcaddr = (FPWV *) src;
FPWV *dstaddr = (FPWV *) dest;
ulong start;
- int flag, i;
+ int flag, i, rc = 0;
/* Check if Flash is (sufficiently) erased */
for (i = 0; i < WR_BLOCK; i++)
start = get_timer (0);
/* wait while polling the status register */
- while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */
- return (1);
+ while ((*dstaddr & (FPW)0x00800080) != (FPW)0x00800080) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ rc = 1;
+ goto OUT;
}
}
}
}
- *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */
+OUT:
+ *dstaddr = (FPW)0x00FF00FF; /* restore read mode */
+ if (flag)
+ enable_interrupts();
- return (0);
+ return rc;
}
/*-----------------------------------------------------------------------
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
volatile immap_t *immap;
- volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
ushort sreg;
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
immap = (immap_t *)CONFIG_SYS_IMMR;
- cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
/*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
#include <common.h>
#include <board/cogent/flash.h>
+#include <linux/compiler.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
{
unsigned long total;
int i;
- flash_info_t *fip;
+ __maybe_unused flash_info_t *fip;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CPS;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC));
#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
- writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8);
+ mx31_set_gpr(MUX_PGP_UH2, 1);
return 0;
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/da8xx-fb.h>
DECLARE_GLOBAL_DATA_PTR;
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
+static const struct da8xx_panel lcd_panel = {
+ /* Casio COM57H531x */
+ .name = "Casio_COM57H531x",
+ .width = 640,
+ .height = 480,
+ .hfp = 12,
+ .hbp = 144,
+ .hsw = 30,
+ .vfp = 10,
+ .vbp = 35,
+ .vsw = 3,
+ .pxl_clk = 25000000,
+ .invert_pxl_clk = 0,
+};
+
/* SPI0 pin muxer settings */
static const struct pinmux_config spi1_pins[] = {
{ pinmux(5), 1, 1 },
{ pinmux(5), 1, 5 }
};
-/* UART pin muxer settings */
+/* I2C pin muxer settings */
+static const struct pinmux_config i2c_pins[] = {
+ { pinmux(4), 2, 2 },
+ { pinmux(4), 2, 3 }
+};
+
+/* UART0 pin muxer settings */
static const struct pinmux_config uart_pins[] = {
- { pinmux(0), 4, 6 },
- { pinmux(0), 4, 7 },
- { pinmux(4), 2, 4 },
- { pinmux(4), 2, 5 }
+ { pinmux(3), 2, 7 },
+ { pinmux(3), 2, 6 },
+ { pinmux(3), 2, 4 },
+ { pinmux(3), 2, 5 }
};
#ifdef CONFIG_DRIVER_TI_EMAC
#ifdef CONFIG_NAND_DAVINCI
const struct pinmux_config nand_pins[] = {
- { pinmux(7), 1, 1 },
- { pinmux(7), 1, 2 },
- { pinmux(7), 1, 4 },
- { pinmux(7), 1, 5 },
- { pinmux(9), 1, 0 },
- { pinmux(9), 1, 1 },
- { pinmux(9), 1, 2 },
- { pinmux(9), 1, 3 },
- { pinmux(9), 1, 4 },
- { pinmux(9), 1, 5 },
- { pinmux(9), 1, 6 },
- { pinmux(9), 1, 7 },
- { pinmux(12), 1, 5 },
- { pinmux(12), 1, 6 }
+ { pinmux(7), 1, 0}, /* CS2 */
+ { pinmux(7), 0, 1}, /* CS3 in three state*/
+ { pinmux(7), 1, 4 }, /* EMA_WE */
+ { pinmux(7), 1, 5 }, /* EMA_OE */
+ { pinmux(9), 1, 0 }, /* EMA_D[7] */
+ { pinmux(9), 1, 1 }, /* EMA_D[6] */
+ { pinmux(9), 1, 2 }, /* EMA_D[5] */
+ { pinmux(9), 1, 3 }, /* EMA_D[4] */
+ { pinmux(9), 1, 4 }, /* EMA_D[3] */
+ { pinmux(9), 1, 5 }, /* EMA_D[2] */
+ { pinmux(9), 1, 6 }, /* EMA_D[1] */
+ { pinmux(9), 1, 7 }, /* EMA_D[0] */
+ { pinmux(12), 1, 5 }, /* EMA_A[2] */
+ { pinmux(12), 1, 6 }, /* EMA_A[1] */
+ { pinmux(6), 1, 0 } /* EMA_CLK */
};
#endif
+const struct pinmux_config gpio_pins[] = {
+ { pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/
+ { pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/
+ { pinmux(13), 8, 3 }, /* GPIO6[12] U0_SW1 on EA20-00101_2*/
+ { pinmux(19), 8, 5 }, /* GPIO6[1] DISP_ON */
+ { pinmux(14), 8, 1 } /* GPIO6[6] LCD_B_PWR*/
+};
+
+const struct pinmux_config lcd_pins[] = {
+ { pinmux(17), 2, 1 }, /* LCD_D_0 */
+ { pinmux(17), 2, 0 }, /* LCD_D_1 */
+ { pinmux(16), 2, 7 }, /* LCD_D_2 */
+ { pinmux(16), 2, 6 }, /* LCD_D_3 */
+ { pinmux(16), 2, 5 }, /* LCD_D_4 */
+ { pinmux(16), 2, 4 }, /* LCD_D_5 */
+ { pinmux(16), 2, 3 }, /* LCD_D_6 */
+ { pinmux(16), 2, 2 }, /* LCD_D_7 */
+ { pinmux(18), 2, 1 }, /* LCD_D_8 */
+ { pinmux(18), 2, 0 }, /* LCD_D_9 */
+ { pinmux(17), 2, 7 }, /* LCD_D_10 */
+ { pinmux(17), 2, 6 }, /* LCD_D_11 */
+ { pinmux(17), 2, 5 }, /* LCD_D_12 */
+ { pinmux(17), 2, 4 }, /* LCD_D_13 */
+ { pinmux(17), 2, 3 }, /* LCD_D_14 */
+ { pinmux(17), 2, 2 }, /* LCD_D_15 */
+ { pinmux(18), 2, 6 }, /* LCD_PCLK */
+ { pinmux(19), 2, 0 }, /* LCD_HSYNC */
+ { pinmux(19), 2, 1 }, /* LCD_VSYNC */
+ { pinmux(19), 2, 6 }, /* DA850_NLCD_AC_ENB_CS */
+};
+
+const struct pinmux_config halten_pin[] = {
+ { pinmux(3), 4, 2 } /* GPIO8[6] HALTEN */
+};
+
static const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_SPI_FLASH
PINMUX_ITEM(spi1_pins),
#endif
PINMUX_ITEM(uart_pins),
+ PINMUX_ITEM(i2c_pins),
#ifdef CONFIG_NAND_DAVINCI
PINMUX_ITEM(nand_pins),
#endif
+#ifdef CONFIG_VIDEO
+ PINMUX_ITEM(lcd_pins),
+#endif
};
static const struct lpsc_resource lpsc[] = {
{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
{ DAVINCI_LPSC_SPI1 }, /* Serial Flash */
{ DAVINCI_LPSC_EMAC }, /* image download */
- { DAVINCI_LPSC_UART2 }, /* console */
+ { DAVINCI_LPSC_UART0 }, /* console */
{ DAVINCI_LPSC_GPIO },
+ { DAVINCI_LPSC_LCDC }, /* LCD */
};
-int board_init(void)
+int board_early_init_f(void)
{
+ struct davinci_gpio *gpio6_base =
+ (struct davinci_gpio *)DAVINCI_GPIO_BANK67;
+
+ /* PinMux for GPIO */
+ if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
+ return 1;
+
+ /* Set the RESETOUTn low */
+ writel((readl(&gpio6_base->set_data) & ~(1 << 15)),
+ &gpio6_base->set_data);
+ writel((readl(&gpio6_base->dir) & ~(1 << 15)), &gpio6_base->dir);
+
+ /* Set U0_SW0 low for UART0 as console*/
+ writel((readl(&gpio6_base->set_data) & ~(1 << 10)),
+ &gpio6_base->set_data);
+ writel((readl(&gpio6_base->dir) & ~(1 << 10)), &gpio6_base->dir);
+
+ /* Set U0_SW1 low for UART0 as console*/
+ writel((readl(&gpio6_base->set_data) & ~(1 << 12)),
+ &gpio6_base->set_data);
+ writel((readl(&gpio6_base->dir) & ~(1 << 12)), &gpio6_base->dir);
+
+ /* Set LCD_B_PWR low to power down LCD Backlight*/
+ writel((readl(&gpio6_base->set_data) & ~(1 << 6)),
+ &gpio6_base->set_data);
+ writel((readl(&gpio6_base->dir) & ~(1 << 6)), &gpio6_base->dir);
+
+ /* Set DISP_ON low to disable LCD output*/
+ writel((readl(&gpio6_base->set_data) & ~(1 << 1)),
+ &gpio6_base->set_data);
+ writel((readl(&gpio6_base->dir) & ~(1 << 1)), &gpio6_base->dir);
+
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
-
-#ifdef CONFIG_NAND_DAVINCI
/*
* NAND CS setup - cycle counts based on da850evm NAND timings in the
* Linux kernel @ 25MHz EMIFA
*/
+#ifdef CONFIG_NAND_DAVINCI
writel((DAVINCI_ABCR_WSETUP(0) |
- DAVINCI_ABCR_WSTROBE(0) |
+ DAVINCI_ABCR_WSTROBE(1) |
DAVINCI_ABCR_WHOLD(0) |
DAVINCI_ABCR_RSETUP(0) |
DAVINCI_ABCR_RSTROBE(1) |
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(0) |
DAVINCI_ABCR_ASIZE_8BIT),
- &davinci_emif_regs->ab2cr); /* CS3 */
+ &davinci_emif_regs->ab1cr); /* CS2 */
#endif
- /* arch number of the board */
- gd->bd->bi_arch_number = MACH_TYPE_EA20;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
/*
* Power on required peripherals
* ARM does not have access by default to PSC0 and PSC1
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
- DAVINCI_SYSCFG_SUSPSRC_UART2),
+ DAVINCI_SYSCFG_SUSPSRC_UART0),
&davinci_syscfg_regs->suspsrc);
/* configure pinmux settings */
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
- &davinci_uart2_ctrl_regs->pwremu_mgmt);
+ &davinci_uart0_ctrl_regs->pwremu_mgmt);
+
+ /*
+ * Reconfigure the LCDC priority to the highest to ensure that
+ * the throughput/latency requirements for the LCDC are met.
+ */
+ writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff,
+ &davinci_syscfg_regs->mstpri[2]);
+
+ /* Set LCD_B_PWR low to power up LCD Backlight*/
+ writel((readl(&gpio6_base->set_data) | (1 << 6)),
+ &gpio6_base->set_data);
+
+ /* Set DISP_ON low to disable LCD output*/
+ writel((readl(&gpio6_base->set_data) | (1 << 1)),
+ &gpio6_base->set_data);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_EA20;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ da8xx_video_init(&lcd_panel, 16);
+
+ return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+
+int board_late_init(void)
+{
+ struct davinci_gpio *gpio8_base =
+ (struct davinci_gpio *)DAVINCI_GPIO_BANK8;
+
+ /* PinMux for HALTEN */
+ if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0)
+ return 1;
+
+ /* Set HALTEN to high */
+ writel((readl(&gpio8_base->set_data) | (1 << 6)),
+ &gpio8_base->set_data);
+ writel((readl(&gpio8_base->dir) & ~(1 << 6)), &gpio8_base->dir);
+
+ setenv("stdout", "serial");
return 0;
}
+#endif /* BOARD_LATE_INIT */
#ifdef CONFIG_DRIVER_TI_EMAC
{
ulong cp, wp;
FPW data;
- int count, i, l, rc, port_width;
+ int i, l, rc, port_width;
if (info->flash_id == FLASH_UNKNOWN) {
return 4;
*/
if ((l = addr - wp) != 0) {
data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
+ for (i=0, cp=wp; i<l; ++i, ++cp)
data = (data << 8) | (*(uchar *)cp);
- }
+
for (; i<port_width && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
/*
* handle word aligned part
*/
- count = 0;
while (cnt >= port_width) {
data = 0;
for (i=0; i<port_width; ++i) {
#include <pci.h>
#endif
#include <miiphy.h>
+#include <linux/compiler.h>
/*
* I/O Port configuration table
uint psdmr = CONFIG_SYS_PSDMR;
int i;
- unsigned char ramtmp;
unsigned char *ramptr1 = (unsigned char *)0x00000110;
+ __maybe_unused unsigned char ramtmp;
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword)
{
- cfiptr_t ctladdr;
cfiptr_t cptr;
int flag;
- ctladdr.cp = flash_make_addr(info, 0, 0);
- cptr.cp = (uchar *) dest;
+ cptr.cp = (uchar *)dest;
/* Check if Flash is (sufficiently) erased */
switch (info->portwidth) {
int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
- int status;
+ if (argv[1][0] == '0')
+ (void)phypower(0);
+ else
+ (void)phypower(1);
- if (argv[1][0] == '0') {
- status = phypower(0);
- } else {
- status = phypower(1);
- }
return (0);
}
#include <common.h>
#include <asm/io.h>
#include <pci.h>
+#include <linux/compiler.h>
#include "multiverse.h"
void multiv_auto_slot_id(unsigned long base)
{
- unsigned int vector;
+ __maybe_unused unsigned int vector;
int slot_id = 1;
if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) {
*(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe;
#include <common.h>
#include <mpc8xx.h>
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
/*-----------------------------------------------------------------------
* Functions
*/
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
+static ulong flash_get_size(vu_long *addr, flash_info_t *info);
+static int write_word(flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
/*-----------------------------------------------------------------------
*/
-unsigned long flash_init (void)
+unsigned long flash_init(void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0, size_b1;
+ unsigned long size_b0;
int i;
/* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
flash_info[i].flash_id = FLASH_UNKNOWN;
- }
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
- size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
- if (size_b1 > size_b0) {
- printf ("## ERROR: "
- "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
- size_b1, size_b1<<20,
- size_b0, size_b0<<20
- );
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[0].sector_count = -1;
- flash_info[1].sector_count = -1;
- flash_info[0].size = 0;
- flash_info[1].size = 0;
- return (0);
- }
-
/* Remap FLASH according to real size */
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
#ifdef CONFIG_FLASH_16BIT
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */
+ memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
+ BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */
#else
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+ memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
+ BR_MS_GPCM | BR_V;
#endif
/* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+ size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE,
+ &flash_info[0]);
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+ flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
&flash_info[0]);
#endif
- if (size_b1) {
- memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
-#ifdef CONFIG_FLASH_16BIT
- memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
- BR_MS_GPCM | BR_V | BR_PS_16;
-#else
- memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
- BR_MS_GPCM | BR_V;
-#endif
-
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
- &flash_info[1]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[1]);
-#endif
- } else {
- memctl->memc_br1 = 0; /* invalidate bank */
-
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
+ memctl->memc_br1 = 0; /* invalidate bank 1 */
flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
- return (size_b0 + size_b1);
+ return size_b0;
}
/*-----------------------------------------------------------------------
*/
-static void flash_get_offsets (ulong base, flash_info_t *info)
+static void flash_get_offsets(ulong base, flash_info_t *info)
{
int i;
- if (info->flash_id == FLASH_UNKNOWN) {
+ if (info->flash_id == FLASH_UNKNOWN)
return;
- }
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- for (i = 0; i < info->sector_count; i++) {
+ for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00002000);
- }
+
return;
}
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
+ for (i = 4; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000) - 0x00030000;
#else
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x0000C000;
info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
+ for (i = 4; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00020000) - 0x00060000;
#endif
- }
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00008000;
info->start[i--] = base + info->size - 0x0000C000;
info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
+ for (; i >= 0; i--)
info->start[i] = base + i * 0x00020000;
- }
}
-
}
/*-----------------------------------------------------------------------
*/
-void flash_print_info (flash_info_t *info)
+void flash_print_info(flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
+ printf("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- default: printf ("Unknown Vendor "); break;
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ case FLASH_MAN_SST:
+ printf("SST ");
+ break;
+ case FLASH_MAN_STM:
+ printf("STM ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_SST200A: printf ("39xF200A (2M = 128K x 16)\n");
- break;
- case FLASH_SST400A: printf ("39xF400A (4M = 256K x 16)\n");
- break;
- case FLASH_SST800A: printf ("39xF800A (8M = 512K x 16)\n");
- break;
- case FLASH_STM800AB: printf ("M29W800AB (8M = 512K x 16)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
+ case FLASH_AM400B:
+ printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T:
+ printf("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T:
+ printf("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B:
+ printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T:
+ printf("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B:
+ printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_SST200A:
+ printf("39xF200A (2M = 128K x 16)\n");
+ break;
+ case FLASH_SST400A:
+ printf("39xF400A (4M = 256K x 16)\n");
+ break;
+ case FLASH_SST800A:
+ printf("39xF800A (8M = 512K x 16)\n");
+ break;
+ case FLASH_STM800AB:
+ printf("M29W800AB (8M = 512K x 16)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
}
- printf (" Size: %ld MB in %d Sectors\n",
+ printf(" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
+ printf("\n ");
+ printf(" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
- printf ("\n");
+ printf("\n");
return;
}
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
/*
* The following code cannot be run from FLASH!
*/
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+static ulong flash_get_size(vu_long *addr, flash_info_t *info)
{
short i;
ulong value;
/* Write auto select command: read Manufacturer ID */
#ifdef CONFIG_FLASH_16BIT
- vu_short *s_addr = (vu_short*)addr;
+ vu_short *s_addr = (vu_short *)addr;
s_addr[0x5555] = 0x00AA;
s_addr[0x2AAA] = 0x0055;
s_addr[0x5555] = 0x0090;
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
- return (0); /* no or unknown flash */
+ return 0; /* no or unknown flash */
}
#ifdef CONFIG_FLASH_16BIT
value = s_addr[1];
#endif
break;
-#if 0 /* enable when device IDs are available */
- case AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
case SST_ID_xF200A:
info->flash_id += FLASH_SST200A;
- info->sector_count = 64; /* 39xF200A ID ( 2M = 128K x 16 ) */
+ info->sector_count = 64; /* 39xF200A (2M = 128K x 16) */
info->size = 0x00080000;
break;
case SST_ID_xF400A:
info->flash_id += FLASH_SST400A;
- info->sector_count = 128; /* 39xF400A ID ( 4M = 256K x 16 ) */
+ info->sector_count = 128; /* 39xF400A (4M = 256K x 16) */
info->size = 0x00100000;
break;
case SST_ID_xF800A:
info->flash_id += FLASH_SST800A;
- info->sector_count = 256; /* 39xF800A ID ( 8M = 512K x 16 ) */
+ info->sector_count = 256; /* 39xF800A (8M = 512K x 16) */
info->size = 0x00200000;
break; /* => 2 MB */
case STM_ID_x800AB:
break; /* => 2 MB */
default:
info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
+ return 0; /* => no or unknown flash */
}
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
+ printf("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- for (i = 0; i < info->sector_count; i++) {
+ for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00002000);
- }
} else { /* AMD and Fujitsu types */
/* set up sector start address table */
if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
+ /* set sector offsets for bottom boot block type */
#ifdef CONFIG_FLASH_16BIT
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ for (i = 4; i < info->sector_count; i++)
+ info->start[i] = base +
+ (i * 0x00010000) - 0x00030000;
#else
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x0000C000;
info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
+ for (i = 4; i < info->sector_count; i++)
+ info->start[i] = base +
+ (i * 0x00020000) - 0x00060000;
#endif
- }
} else {
- /* set sector offsets for top boot block type */
+ /* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00008000;
info->start[i--] = base + info->size - 0x0000C000;
info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
+ for (; i >= 0; i--)
info->start[i] = base + i * 0x00020000;
- }
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address:
+ /*
+ * read sector protection at sector address:
* (A7 .. A0) = 0x02
* D0 = 1 if protected
*/
#endif
}
- return (info->size);
+ return info->size;
}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase(flash_info_t *info, int s_first, int s_last)
{
- vu_long *addr = (vu_long*)(info->start[0]);
+ vu_long *addr = (vu_long *)(info->start[0]);
int flag, prot, sect;
ulong start, now, last;
#ifdef CONFIG_FLASH_16BIT
- vu_short *s_addr = (vu_short*)addr;
+ vu_short *s_addr = (vu_short *)addr;
#endif
if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
+ if (info->flash_id == FLASH_UNKNOWN)
+ printf("- missing\n");
+ else
+ printf("- no sectors to erase\n");
return 1;
}
/*#ifndef CONFIG_FLASH_16BIT
}
#endif*/
prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
prot++;
- }
}
if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
+ printf("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
- printf ("\n");
+ printf("\n");
}
- start = get_timer (0);
+ start = get_timer(0);
last = start;
/* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
+ for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
#ifdef CONFIG_FLASH_16BIT
- vu_short *s_sect_addr = (vu_short*)(info->start[sect]);
+ vu_short *s_sect_addr = (vu_short *)(info->start[sect]);
#else
- vu_long *sect_addr = (vu_long*)(info->start[sect]);
+ vu_long *sect_addr = (vu_long *)(info->start[sect]);
#endif
- /* Disable interrupts which might cause a timeout here */
+ /* Disable interrupts which might cause a timeout */
flag = disable_interrupts();
#ifdef CONFIG_FLASH_16BIT
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
- udelay (1000);
+ udelay(1000);
#ifdef CONFIG_FLASH_16BIT
while ((s_sect_addr[0] & 0x0080) != 0x0080) {
#else
while ((sect_addr[0] & 0x00800080) != 0x00800080) {
#endif
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
+ now = get_timer(start);
+ if (now > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
return 1;
}
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
+ /* show every second that we're waiting */
+ if ((now - last) > 1000) {
+ putc('.');
last = now;
}
}
addr[0] = 0x00F000F0; /* reset bank */
#endif
- printf (" done\n");
+ printf(" done\n");
return 0;
}
* 4 - Flash not identified
*/
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
- if (info->flash_id == FLASH_UNKNOWN) {
+ if (info->flash_id == FLASH_UNKNOWN)
return 4;
- }
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
- if ((l = addr - wp) != 0) {
+ l = addr - wp;
+
+ if (l != 0) {
data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
+ for (i = 0, cp = wp; i < l; ++i, ++cp)
data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
+
+ for (; i < 4 && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
- for (; cnt==0 && i<4; ++i, ++cp) {
+ for (; cnt == 0 && i < 4; ++i, ++cp)
data = (data << 8) | (*(uchar *)cp);
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
+ rc = write_word(info, wp, data);
+
+ if (rc != 0)
+ return rc;
+
wp += 4;
}
*/
while (cnt >= 4) {
data = 0;
- for (i=0; i<4; ++i) {
+ for (i = 0; i < 4; ++i)
data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
+
+ rc = write_word(info, wp, data);
+ if (rc != 0)
+ return rc;
+
wp += 4;
cnt -= 4;
}
- if (cnt == 0) {
- return (0);
- }
+ if (cnt == 0)
+ return 0;
/*
* handle unaligned tail bytes
*/
data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
- for (; i<4; ++i, ++cp) {
+ for (; i < 4; ++i, ++cp)
data = (data << 8) | (*(uchar *)cp);
- }
- return (write_word(info, wp, data));
+ return write_word(info, wp, data);
}
/*-----------------------------------------------------------------------
* 1 - write timeout
* 2 - Flash not erased
*/
-static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int write_word(flash_info_t *info, ulong dest, ulong data)
{
- vu_long *addr = (vu_long*)(info->start[0]);
+ vu_long *addr = (vu_long *)(info->start[0]);
#ifdef CONFIG_FLASH_16BIT
vu_short high_data;
vu_short low_data;
- vu_short *s_addr = (vu_short*)addr;
+ vu_short *s_addr = (vu_short *)addr;
#endif
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
+ if ((*((vu_long *)dest) & data) != data)
+ return 2;
#ifdef CONFIG_FLASH_16BIT
/* Write the 16 higher-bits */
*((vu_short *)dest) = high_data;
-
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
- start = get_timer (0);
+ start = get_timer(0);
while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+ return 1;
}
-
/* Write the 16 lower-bits */
#endif
enable_interrupts();
/* data polling for D7 */
- start = get_timer (0);
+ start = get_timer(0);
#ifdef CONFIG_FLASH_16BIT
while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) {
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
#endif
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+ return 1;
}
- return (0);
+ return 0;
}
-
-/*-----------------------------------------------------------------------
- */
phys_size_t initdram (int board_type)
{
uint sdramsz = 0; /* size of sdram in Mbytes */
- uint base = 0; /* base of dram in bytes */
uint m = 0; /* size of dram in Mbytes */
#ifndef CONFIG_MPC885ADS
+ uint base = 0; /* base of dram in bytes */
uint k, s;
#endif
#ifdef CONFIG_FADS
if (!initsdram (0x00000000, &sdramsz)) {
+#ifndef CONFIG_MPC885ADS
base = sdramsz << 20;
+#endif
printf ("(%u MB SDRAM) ", sdramsz);
}
#endif
arch/m68k/cpu/mcf5227x/libmcf5227x.o (.text*)
arch/m68k/lib/libm68k.o (.text*)
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.text*)
-
*(.text*)
}
_etext = .;
/*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2011
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Modified during 2001 by
const iop_conf_t iop_conf_tab[4][32] = {
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
+ },
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
+ },
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
+ },
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
+ }
};
typedef struct bscr_ {
void reset_phy(void)
{
- volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR;
+ volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR;
- /* reset the FEC port */
- bcsr->bcsr1 &= ~FETH_RST;
- bcsr->bcsr1 |= FETH_RST;
+ /* reset the FEC port */
+ bcsr->bcsr1 &= ~FETH_RST;
+ bcsr->bcsr1 |= FETH_RST;
}
-int board_early_init_f (void)
+int board_early_init_f(void)
{
- volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR;
- volatile pci_ic_t *pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT;
+ volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR;
+ volatile pci_ic_t *pci_ic = (pci_ic_t *)CONFIG_SYS_PCI_INT;
- bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2;
+ bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2;
- /* mask all PCI interrupts */
- pci_ic->pci_int_mask |= 0xfff00000;
+ /* mask all PCI interrupts */
+ pci_ic->pci_int_mask |= 0xfff00000;
- return 0;
+ return 0;
}
int checkboard(void)
{
- puts ("Board: Motorola MPC8266ADS\n");
- return 0;
+ puts("Board: Motorola MPC8266ADS\n");
+ return 0;
}
phys_size_t initdram(int board_type)
{
/* Autoinit part stolen from board/sacsng/sacsng.c */
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar c = 0xff;
- volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8);
- uint psdmr = CONFIG_SYS_PSDMR;
- int i;
-
- uint psrt = 0x21; /* for no SPD */
- uint chipselects = 1; /* for no SPD */
- uint sdram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; /* for no SPD */
- uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */
- uint data_width;
- uint rows;
- uint banks;
- uint cols;
- uint caslatency;
- uint width;
- uint rowst;
- uint sdam;
- uint bsma;
- uint sda10;
- u_char spd_size;
- u_char data;
- u_char cksum;
- int j;
-
- /* Keep the compiler from complaining about potentially uninitialized vars */
- data_width = rows = banks = cols = caslatency = 0;
-
- /*
- * Read the SDRAM SPD EEPROM via I2C.
- */
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
- spd_size = data;
- cksum = data;
- for(j = 1; j < 64; j++)
- { /* read only the checksummed bytes */
- /* note: the I2C address autoincrements when alen == 0 */
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+ volatile uchar c = 0xff;
+ volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
+ uint psdmr = CONFIG_SYS_PSDMR;
+ int i;
+
+ uint psrt = 0x21; /* for no SPD */
+ uint chipselects = 1; /* for no SPD */
+ uint sdram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; /* for no SPD */
+ uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */
+ uint data_width;
+ uint rows;
+ uint banks;
+ uint cols;
+ uint caslatency;
+ uint width;
+ uint rowst;
+ uint sdam;
+ uint bsma;
+ uint sda10;
+ u_char data;
+ u_char cksum;
+ int j;
+
+ /*
+ * Keep the compiler from complaining about
+ * potentially uninitialized vars
+ */
+ data_width = rows = banks = cols = caslatency = 0;
+
+ /*
+ * Read the SDRAM SPD EEPROM via I2C.
+ */
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
+ cksum = data;
+ for (j = 1; j < 64; j++) { /* read only the checksummed bytes */
+ /* note: the I2C address autoincrements when alen == 0 */
i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
- /*printf("addr %d = 0x%02x\n", j, data);*/
- if(j == 5) chipselects = data & 0x0F;
- else if(j == 6) data_width = data;
- else if(j == 7) data_width |= data << 8;
- else if(j == 3) rows = data & 0x0F;
- else if(j == 4) cols = data & 0x0F;
- else if(j == 12)
- {
+ /*printf("addr %d = 0x%02x\n", j, data); */
+ if (j == 5)
+ chipselects = data & 0x0F;
+ else if (j == 6)
+ data_width = data;
+ else if (j == 7)
+ data_width |= data << 8;
+ else if (j == 3)
+ rows = data & 0x0F;
+ else if (j == 4)
+ cols = data & 0x0F;
+ else if (j == 12) {
/*
- * Refresh rate: this assumes the prescaler is set to
- * approximately 0.39uSec per tick and the target refresh period
- * is about 85% of maximum.
+ * Refresh rate: this assumes the prescaler is set to
+ * approximately 0.39uSec per tick and the target
+ * refresh period is about 85% of maximum.
*/
- switch(data & 0x7F)
- {
- default:
- case 0: psrt = 0x21; /* 15.625uS */ break;
- case 1: psrt = 0x07; /* 3.9uS */ break;
- case 2: psrt = 0x0F; /* 7.8uS */ break;
- case 3: psrt = 0x43; /* 31.3uS */ break;
- case 4: psrt = 0x87; /* 62.5uS */ break;
- case 5: psrt = 0xFF; /* 125uS */ break;
+ switch (data & 0x7F) {
+ default:
+ case 0:
+ psrt = 0x21; /* 15.625uS */
+ break;
+ case 1:
+ psrt = 0x07; /* 3.9uS */
+ break;
+ case 2:
+ psrt = 0x0F; /* 7.8uS */
+ break;
+ case 3:
+ psrt = 0x43; /* 31.3uS */
+ break;
+ case 4:
+ psrt = 0x87; /* 62.5uS */
+ break;
+ case 5:
+ psrt = 0xFF; /* 125uS */
+ break;
}
- }
- else if(j == 17) banks = data;
- else if(j == 18)
- {
- caslatency = 3; /* default CL */
-# if(PESSIMISTIC_SDRAM)
- if((data & 0x04) != 0) caslatency = 3;
- else if((data & 0x02) != 0) caslatency = 2;
- else if((data & 0x01) != 0) caslatency = 1;
-# else
- if((data & 0x01) != 0) caslatency = 1;
- else if((data & 0x02) != 0) caslatency = 2;
- else if((data & 0x04) != 0) caslatency = 3;
-# endif
- else
- {
- printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
+ } else if (j == 17)
+ banks = data;
+ else if (j == 18) {
+ caslatency = 3; /* default CL */
+#if (PESSIMISTIC_SDRAM)
+ if ((data & 0x04) != 0)
+ caslatency = 3;
+ else if ((data & 0x02) != 0)
+ caslatency = 2;
+ else if ((data & 0x01) != 0)
+ caslatency = 1;
+#else
+ if ((data & 0x01) != 0)
+ caslatency = 1;
+ else if ((data & 0x02) != 0)
+ caslatency = 2;
+ else if ((data & 0x04) != 0)
+ caslatency = 3;
+#endif
+ else {
+ printf("WARNING: Unknown CAS latency 0x%02X, using 3\n",
data);
}
- }
- else if(j == 63)
- {
- if(data != cksum)
- {
- printf ("WARNING: Configuration data checksum failure:"
+ } else if (j == 63) {
+ if (data != cksum) {
+ printf("WARNING: Configuration data checksum failure:"
" is 0x%02x, calculated 0x%02x\n",
- data, cksum);
+ data, cksum);
}
}
cksum += data;
- }
+ }
- /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
- if(caslatency < 2) {
+ /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
+ if (caslatency < 2) {
printf("CL was %d, forcing to 2\n", caslatency);
caslatency = 2;
- }
- if(rows > 14) {
- printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
+ }
+ if (rows > 14) {
+ printf("This doesn't look good, rows = %d, should be <= 14\n",
+ rows);
rows = 14;
- }
- if(cols > 11) {
- printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
+ }
+ if (cols > 11) {
+ printf("This doesn't look good, columns = %d, should be <= 11\n",
+ cols);
cols = 11;
- }
+ }
- if((data_width != 64) && (data_width != 72))
- {
+ if ((data_width != 64) && (data_width != 72)) {
printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
data_width);
- }
- width = 3; /* 2^3 = 8 bytes = 64 bits wide */
- /*
- * Convert banks into log2(banks)
- */
- if (banks == 2) banks = 1;
- else if(banks == 4) banks = 2;
- else if(banks == 8) banks = 3;
-
-
- sdram_size = 1 << (rows + cols + banks + width);
- /* hack for high density memory (512MB per CS) */
- /* !!!!! Will ONLY work with Page Based Interleave !!!!!
- ( PSDMR[PBI] = 1 )
- */
- /* mamory actually has 11 column addresses, but the memory controller
- doesn't really care.
- the calculations that follow will however move the rows so that
- they are muxed one bit off if you use 11 bit columns.
- The solution is to tell the memory controller the correct size of the memory
- but change the number of columns to 10 afterwards.
- The 11th column addre will still be mucxed correctly onto the bus.
-
- Also be aware that the MPC8266ADS board Rev B has not connected
- Row address 13 to anything.
-
- The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
- */
- if (cols > 10)
- cols = 10;
-
-#if(CONFIG_PBI == 0) /* bank-based interleaving */
- rowst = ((32 - 6) - (rows + cols + width)) * 2;
+ }
+ width = 3; /* 2^3 = 8 bytes = 64 bits wide */
+ /*
+ * Convert banks into log2(banks)
+ */
+ if (banks == 2)
+ banks = 1;
+ else if (banks == 4)
+ banks = 2;
+ else if (banks == 8)
+ banks = 3;
+
+
+ sdram_size = 1 << (rows + cols + banks + width);
+ /* hack for high density memory (512MB per CS) */
+ /* !!!!! Will ONLY work with Page Based Interleave !!!!!
+ ( PSDMR[PBI] = 1 )
+ */
+ /*
+ * memory actually has 11 column addresses, but the memory
+ * controller doesn't really care.
+ *
+ * the calculations that follow will however move the rows so
+ * that they are muxed one bit off if you use 11 bit columns.
+ *
+ * The solution is to tell the memory controller the correct
+ * size of the memory but change the number of columns to 10
+ * afterwards.
+ *
+ * The 11th column addre will still be mucxed correctly onto
+ * the bus.
+ *
+ * Also be aware that the MPC8266ADS board Rev B has not
+ * connected Row address 13 to anything.
+ *
+ * The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
+ */
+ if (cols > 10)
+ cols = 10;
+
+#if (CONFIG_PBI == 0) /* bank-based interleaving */
+ rowst = ((32 - 6) - (rows + cols + width)) * 2;
#else
- rowst = 32 - (rows + banks + cols + width);
+ rowst = 32 - (rows + banks + cols + width);
#endif
- or = ~(sdram_size - 1) | /* SDAM address mask */
- ((banks-1) << 13) | /* banks per device */
- (rowst << 9) | /* rowst */
- ((rows - 9) << 6); /* numr */
-
-
- /*printf("memctl->memc_or2 = 0x%08x\n", or);*/
-
- /*
- * SDAM specifies the number of columns that are multiplexed
- * (reference AN2165/D), defined to be (columns - 6) for page
- * interleave, (columns - 8) for bank interleave.
- *
- * BSMA is 14 - max(rows, cols). The bank select lines come
- * into play above the highest "address" line going into the
- * the SDRAM.
- */
-#if(CONFIG_PBI == 0) /* bank-based interleaving */
- sdam = cols - 8;
- bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
- sda10 = sdam + 2;
+ or = ~(sdram_size - 1) | /* SDAM address mask */
+ ((banks - 1) << 13) | /* banks per device */
+ (rowst << 9) | /* rowst */
+ ((rows - 9) << 6); /* numr */
+
+
+ /*printf("memctl->memc_or2 = 0x%08x\n", or); */
+
+ /*
+ * SDAM specifies the number of columns that are multiplexed
+ * (reference AN2165/D), defined to be (columns - 6) for page
+ * interleave, (columns - 8) for bank interleave.
+ *
+ * BSMA is 14 - max(rows, cols). The bank select lines come
+ * into play above the highest "address" line going into the
+ * the SDRAM.
+ */
+#if (CONFIG_PBI == 0) /* bank-based interleaving */
+ sdam = cols - 8;
+ bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+ sda10 = sdam + 2;
#else
- sdam = cols + banks - 8;
- bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
- sda10 = sdam;
+ sdam = cols + banks - 8;
+ bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+ sda10 = sdam;
#endif
-#if(PESSIMISTIC_SDRAM)
- psdmr = (CONFIG_PBI |\
- PSDMR_RFEN |\
- PSDMR_RFRC_16_CLK |\
- PSDMR_PRETOACT_8W |\
- PSDMR_ACTTORW_8W |\
- PSDMR_WRC_4C |\
- PSDMR_EAMUX |\
- PSDMR_BUFCMD) |\
- caslatency |\
- ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
- (sdam << 24) |\
- (bsma << 21) |\
- (sda10 << 18);
+#if (PESSIMISTIC_SDRAM)
+ psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK |
+ PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C |
+ PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency |
+ ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */
+ (sdam << 24) | (bsma << 21) | (sda10 << 18);
#else
- psdmr = (CONFIG_PBI |\
- PSDMR_RFEN |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \
- PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
- PSDMR_WRC_1C | /* 1 clock + 7nSec */
- EAMUX |\
- BUFCMD) |\
- caslatency |\
- ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
- (sdam << 24) |\
- (bsma << 21) |\
- (sda10 << 18);
+ psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK |
+ PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */
+ PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */
+ PSDMR_WRC_1C | /* 1 clock + 7nSec */
+ EAMUX | BUFCMD) | caslatency |
+ ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */
+ (sdam << 24) | (bsma << 21) | (sda10 << 18);
#endif
- /*printf("psdmr = 0x%08x\n", psdmr);*/
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * Quote from Micron MT48LC8M16A2 data sheet:
- *
- * "...the SDRAM requires a 100uS delay prior to issuing any
- * command other than a COMMAND INHIBIT or NOP. Starting at some
- * point during this 100uS period and continuing at least through
- * the end of this period, COMMAND INHIBIT or NOP commands should
- * be applied."
- *
- * "Once the 100uS delay has been satisfied with at least one COMMAND
- * INHIBIT or NOP command having been applied, a /PRECHARGE command/
- * should be applied. All banks must then be precharged, thereby
- * placing the device in the all banks idle state."
- *
- * "Once in the idle state, /two/ AUTO REFRESH cycles must be
- * performed. After the AUTO REFRESH cycles are complete, the
- * SDRAM is ready for mode register programming."
- *
- * (/emphasis/ mine, gvb)
- *
- * The way I interpret this, Micron start up sequence is:
- * 1. Issue a PRECHARGE-BANK command (initial precharge)
- * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
- * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
- * 4. Issue a MODE-SET command to initialize the mode register
- *
- * --------
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
- memctl->memc_psrt = psrt;
-
- memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
- memctl->memc_or2 = or;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
+ /*printf("psdmr = 0x%08x\n", psdmr); */
+
+ /*
+ * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+ *
+ * "At system reset, initialization software must set up the
+ * programmable parameters in the memory controller banks registers
+ * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+ * system software should execute the following initialization sequence
+ * for each SDRAM device.
+ *
+ * 1. Issue a PRECHARGE-ALL-BANKS command
+ * 2. Issue eight CBR REFRESH commands
+ * 3. Issue a MODE-SET command to initialize the mode register
+ *
+ * Quote from Micron MT48LC8M16A2 data sheet:
+ *
+ * "...the SDRAM requires a 100uS delay prior to issuing any
+ * command other than a COMMAND INHIBIT or NOP. Starting at some
+ * point during this 100uS period and continuing at least through
+ * the end of this period, COMMAND INHIBIT or NOP commands should
+ * be applied."
+ *
+ * "Once the 100uS delay has been satisfied with at least one COMMAND
+ * INHIBIT or NOP command having been applied, a /PRECHARGE command/
+ * should be applied. All banks must then be precharged, thereby
+ * placing the device in the all banks idle state."
+ *
+ * "Once in the idle state, /two/ AUTO REFRESH cycles must be
+ * performed. After the AUTO REFRESH cycles are complete, the
+ * SDRAM is ready for mode register programming."
+ *
+ * (/emphasis/ mine, gvb)
+ *
+ * The way I interpret this, Micron start up sequence is:
+ * 1. Issue a PRECHARGE-BANK command (initial precharge)
+ * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
+ * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
+ * 4. Issue a MODE-SET command to initialize the mode register
+ *
+ * --------
+ *
+ * The initial commands are executed by setting P/LSDMR[OP] and
+ * accessing the SDRAM with a single-byte transaction."
+ *
+ * The appropriate BRx/ORx registers have already been set
+ * when we get here. The SDRAM can be accessed at the address
+ * CONFIG_SYS_SDRAM_BASE.
+ */
+
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+ memctl->memc_psrt = psrt;
+
+ memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
+ memctl->memc_or2 = or;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
*ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
- *ramaddr = c;
+ memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+ for (i = 0; i < 8; i++)
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+ *ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *ramaddr = c;
+ memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+ *ramaddr = c;
- /*
- * Do it a second time for the second set of chips if the DIMM has
- * two chip selects (double sided).
- */
- if(chipselects > 1)
- {
- ramaddr += sdram_size;
+ /*
+ * Do it a second time for the second set of chips if the DIMM has
+ * two chip selects (double sided).
+ */
+ if (chipselects > 1) {
+ ramaddr += sdram_size;
memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
memctl->memc_or3 = or;
memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*ramaddr = c;
- }
+ }
/* print info */
printf("SDRAM configuration read from SPD\n");
printf("\tSize per side = %dMB\n", sdram_size >> 20);
- printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);
+ printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n",
+ chipselects, 1 << (banks), cols, rows, data_width);
printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency);
-#if(CONFIG_PBI == 0) /* bank-based interleaving */
- printf(", Using Bank Based Interleave\n");
+#if (CONFIG_PBI == 0) /* bank-based interleaving */
+ printf(", Using Bank Based Interleave\n");
#else
- printf(", Using Page Based Interleave\n");
+ printf(", Using Page Based Interleave\n");
#endif
printf("\tTotal size: ");
- /* this delay only needed for original 16MB DIMM...
- * Not needed for any other memory configuration */
- if ((sdram_size * chipselects) == (16 *1024 *1024))
- udelay (250000);
- return (sdram_size * chipselects);
- /*return (16 * 1024 * 1024);*/
-}
+ /* this delay only needed for original 16MB DIMM...
+ * Not needed for any other memory configuration */
+ if ((sdram_size * chipselects) == (16 * 1024 * 1024))
+ udelay(250000);
+ return sdram_size * chipselects;
+}
#ifdef CONFIG_PCI
struct pci_controller hose;
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <watchdog.h>
+#include <pmic.h>
+#include <fsl_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+void enable_caches(void)
+{
+ icache_enable();
+ dcache_enable();
+}
+
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+ enable_caches();
+
return 0;
}
int board_late_init(void)
{
+ u32 val;
+ struct pmic *p;
+
+ pmic_init();
+ p = get_pmic();
+
+ /* Enable RTC battery */
+ pmic_reg_read(p, REG_POWER_CTL0, &val);
+ pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
+ pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
#ifdef CONFIG_HW_WATCHDOG
mxc_hw_watchdog_enable();
#endif
#define CCM_CCMR_CONFIG 0x003F4208
#define CCM_PDR0_CONFIG 0x00801000
-#define PLL_BRM_OFFSET 31
-#define PLL_PD_OFFSET 26
-#define PLL_MFD_OFFSET 16
-#define PLL_MFI_OFFSET 10
-
-#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET)
-#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET)
-#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET)
-#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET)
-#define _PLL_MFN(x) (x)
-#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
- (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
- _PLL_MFN(mfn))
-
-#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1)
-#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
-#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
-
/* MEMORY SETTING */
#define ESDCTL_0x92220000 0x92220000
#define ESDCTL_0xA2220000 0xA2220000
DECLARE_GLOBAL_DATA_PTR;
-static u32 system_rev;
-
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR, 1},
};
#endif
-u32 get_board_rev(void)
-{
- return system_rev;
-}
-
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
pmic_reg_write(p, REG_MODE_1, val);
udelay(200);
- gpio_direction_output(46, 0);
-
- /* Reset the ethernet controller over GPIO */
- writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
-
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
VVIDEOEN | VAUDIOEN | VSDEN;
pmic_reg_write(p, REG_MODE_1, val);
+ mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
+ gpio_direction_output(46, 0);
+
udelay(500);
gpio_set_value(46, 1);
int board_init(void)
{
- system_rev = get_cpu_rev();
-
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
DECLARE_GLOBAL_DATA_PTR;
-u32 get_board_rev(void)
-{
- return get_cpu_rev();
-}
-
int dram_init(void)
{
u32 size1, size2;
DECLARE_GLOBAL_DATA_PTR;
-u32 get_board_rev(void)
-{
- return get_cpu_rev();
-}
-
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
DECLARE_GLOBAL_DATA_PTR;
-u32 get_board_rev(void)
-{
- return get_cpu_rev();
-}
-
int dram_init(void)
{
u32 size1, size2;
DECLARE_GLOBAL_DATA_PTR;
-u32 get_board_rev(void)
-{
- return get_cpu_rev();
-}
-
int dram_init(void)
{
u32 size1, size2;
#include <mpc8260.h>
#include <asm/m8260_pci.h>
#include <miiphy.h>
+#include <linux/compiler.h>
#include "m88e6060.h"
int misc_init_r (void)
{
volatile ioport_t *iop;
- unsigned char temp;
+ __maybe_unused unsigned char temp;
#if 0
/* DUMP UPMA RAM */
volatile immap_t *immap;
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2011
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#include <common.h>
#include <mpc8xx.h>
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
/*-----------------------------------------------------------------------
* Functions
*/
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
+static ulong flash_get_size(vu_long *addr, flash_info_t *info);
+static int write_word(flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
/*-----------------------------------------------------------------------
*/
-unsigned long flash_init (void)
+unsigned long flash_init(void)
{
- unsigned long size_b0, size_b1;
+ unsigned long size_b0;
int i;
/* Init: no FLASHes known */
- for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- flash_info[i].flash_id = FLASH_UNKNOWN;
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+ flash_info[i].flash_id = FLASH_UNKNOWN;
/* Detect size */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+ size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE,
+ &flash_info[0]);
/* Setup offsets */
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+ flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* Monitor protection ON by default */
&flash_info[0]);
#endif
- size_b1 = 0 ;
-
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
-
flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
- return (size_b0 + size_b1);
+ return size_b0;
}
/*-----------------------------------------------------------------------
* Fix this to support variable sector sizes
*/
-static void flash_get_offsets (ulong base, flash_info_t *info)
+static void flash_get_offsets(ulong base, flash_info_t *info)
{
int i;
/*-----------------------------------------------------------------------
*/
-void flash_print_info (flash_info_t *info)
+void flash_print_info(flash_info_t *info)
{
int i;
- if (info->flash_id == FLASH_UNKNOWN)
- {
- puts ("missing or unknown FLASH type\n");
+ if (info->flash_id == FLASH_UNKNOWN) {
+ puts("missing or unknown FLASH type\n");
return;
}
- switch (info->flash_id & FLASH_VENDMASK)
- {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
- default: printf ("Unknown Vendor "); break;
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ case FLASH_MAN_BM:
+ printf("BRIGHT MICRO ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
}
- switch (info->flash_id & FLASH_TYPEMASK)
- {
- case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
- break;
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040:
+ printf("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+ break;
+ case FLASH_AM400B:
+ printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T:
+ printf("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T:
+ printf("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B:
+ printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T:
+ printf("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B:
+ printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
}
if (info->size >> 20) {
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20,
- info->sector_count);
+ printf(" Size: %ld MB in %d Sectors\n",
+ info->size >> 20,
+ info->sector_count);
} else {
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10,
- info->sector_count);
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10,
+ info->sector_count);
}
- puts (" Sector Start Addresses:");
+ puts(" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i)
- {
+ for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
- {
- puts ("\n ");
- }
+ puts("\n ");
- printf (" %08lX%s",
+ printf(" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " ");
}
- putc ('\n');
+ putc('\n');
return;
}
/*-----------------------------------------------------------------------
* The following code cannot be run from FLASH!
*/
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+static ulong flash_get_size(vu_long *addr, flash_info_t *info)
{
short i;
volatile unsigned char *caddr;
/* Write auto select command: read Manufacturer ID */
-#if 0
- printf("Base address is: %08x\n", caddr);
-#endif
+ debug("Base address is: %8p\n", caddr);
caddr[0x0555] = 0xAA;
caddr[0x02AA] = 0x55;
value = caddr[0];
-#if 0
- printf("Manufact ID: %02x\n", value);
-#endif
- switch (value)
- {
- case 0x1: /* AMD_MANUFACT */
- info->flash_id = FLASH_MAN_AMD;
- break;
+ debug("Manufact ID: %02x\n", value);
- case 0x4: /* FUJ_MANUFACT */
- info->flash_id = FLASH_MAN_FUJ;
+ switch (value) {
+ case 0x1: /* AMD_MANUFACT */
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case 0x4: /* FUJ_MANUFACT */
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
}
value = caddr[1]; /* device ID */
-#if 0
- printf("Device ID: %02x\n", value);
-#endif
- switch (value)
- {
- case AMD_ID_LV040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break; /* => 512Kb */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
+ debug("Device ID: %02x\n", value);
+
+ switch (value) {
+ case AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x00080000;
+ break; /* => 512Kb */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return 0; /* => no or unknown flash */
}
- flash_get_offsets ((ulong)addr, &flash_info[0]);
+ flash_get_offsets((ulong)addr, &flash_info[0]);
/* check for protected sectors */
- for (i = 0; i < info->sector_count; i++)
- {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
+ for (i = 0; i < info->sector_count; i++) {
+ /*
+ * read sector protection at sector address,
+ * (A7 .. A0) = 0x02
+ * D0 = 1 if protected
+ */
caddr = (volatile unsigned char *)(info->start[i]);
info->protect[i] = caddr[2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
- if (info->flash_id != FLASH_UNKNOWN)
- {
+ if (info->flash_id != FLASH_UNKNOWN) {
caddr = (volatile unsigned char *)info->start[0];
*caddr = 0xF0; /* reset bank */
}
- return (info->size);
+ return info->size;
}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase(flash_info_t *info, int s_first, int s_last)
{
- volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
+ volatile unsigned char *addr =
+ (volatile unsigned char *)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
+ if (info->flash_id == FLASH_UNKNOWN)
+ printf("- missing\n");
+ else
+ printf("- no sectors to erase\n");
+
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type - aborted\n");
+ printf("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
prot++;
- }
}
if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
+ printf("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
- printf ("\n");
+ printf("\n");
}
l_sect = -1;
addr[0x02AA] = 0x55;
/* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
+ for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (volatile unsigned char *)(info->start[sect]);
addr[0] = 0x30;
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
- udelay (1000);
+ udelay(1000);
/*
* We wait for the last triggered sector
if (l_sect < 0)
goto DONE;
- start = get_timer (0);
+ start = get_timer(0);
last = start;
addr = (volatile unsigned char *)(info->start[l_sect]);
- while ((addr[0] & 0xFF) != 0xFF)
- {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
+ while ((addr[0] & 0xFF) != 0xFF) {
+
+ now = get_timer(start);
+
+ if (now > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
- putc ('.');
+ putc('.');
last = now;
}
}
addr[0] = 0xF0; /* reset bank */
- printf (" done\n");
+ printf(" done\n");
return 0;
}
* 2 - Flash not erased
*/
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
/*
* handle unaligned start bytes
*/
- if ((l = addr - wp) != 0) {
+ l = addr - wp;
+
+ if (l != 0) {
data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
+ for (i = 0, cp = wp; i < l; ++i, ++cp)
data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
+
+ for (; i < 4 && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
- for (; cnt==0 && i<4; ++i, ++cp) {
+ for (; cnt == 0 && i < 4; ++i, ++cp)
data = (data << 8) | (*(uchar *)cp);
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
+ rc = write_word(info, wp, data);
+
+ if (rc != 0)
+ return rc;
+
wp += 4;
}
*/
while (cnt >= 4) {
data = 0;
- for (i=0; i<4; ++i) {
+ for (i = 0; i < 4; ++i)
data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
+
+ rc = write_word(info, wp, data);
+
+ if (rc != 0)
+ return rc;
+
wp += 4;
cnt -= 4;
}
- if (cnt == 0) {
- return (0);
- }
+ if (cnt == 0)
+ return 0;
/*
* handle unaligned tail bytes
*/
data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
- for (; i<4; ++i, ++cp) {
+ for (; i < 4; ++i, ++cp)
data = (data << 8) | (*(uchar *)cp);
- }
- return (write_word(info, wp, data));
+ return write_word(info, wp, data);
}
/*-----------------------------------------------------------------------
* 1 - write timeout
* 2 - Flash not erased
*/
-static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int write_word(flash_info_t *info, ulong dest, ulong data)
{
- volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]),
- *cdest,*cdata;
+ volatile unsigned char *cdest, *cdata;
+ volatile unsigned char *addr =
+ (volatile unsigned char *)(info->start[0]);
ulong start;
int flag, count = 4 ;
cdata = (volatile unsigned char *)&data ;
/* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
+ if ((*((vu_long *)dest) & data) != data)
+ return 2;
- while(count--)
- {
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
+ while (count--) {
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0xA0;
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
- *cdest = *cdata;
+ addr[0x0555] = 0xAA;
+ addr[0x02AA] = 0x55;
+ addr[0x0555] = 0xA0;
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
+ *cdest = *cdata;
- /* data polling for D7 */
- start = get_timer (0);
- while ((*cdest ^ *cdata) & 0x80)
- {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((*cdest ^ *cdata) & 0x80) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+ return 1;
}
- }
- cdata++ ;
- cdest++ ;
+ cdata++ ;
+ cdest++ ;
}
- return (0);
+ return 0;
}
-
-/*-----------------------------------------------------------------------
- */
/* functions */
/*********************************************************************/
-/*********************************************************************/
-/* NAME: flash_init() - initializes flash banks */
-/* */
-/* DESCRIPTION: */
-/* This function initializes the flash bank(s). */
-/* */
-/* RETURNS: */
-/* The size in bytes of the flash */
-/* */
-/* RESTRICTIONS/LIMITATIONS: */
-/* */
-/* */
-/*********************************************************************/
-unsigned long flash_init (void)
+/*
+ * NAME: flash_init() - initializes flash banks
+ *
+ * DESCRIPTION:
+ * This function initializes the flash bank(s).
+ *
+ * RETURNS:
+ * The size in bytes of the flash
+ *
+ * RESTRICTIONS/LIMITATIONS:
+ *
+ *
+ */
+unsigned long flash_init(void)
{
- unsigned long size;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* for now, only support the 4 MB Flash SIMM */
- size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
-
- /*
- * protect monitor and environment sectors
- */
-
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+
+ /* for now, only support the 4 MB Flash SIMM */
+ (void)flash_get_size((vu_long *) CONFIG_SYS_FLASH0_BASE,
+ &flash_info[0]);
+ /*
+ * protect monitor and environment sectors
+ */
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+ &flash_info[0]);
#endif
#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
+#ifndef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#endif
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
#endif
- return (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024); /*size*/
+ return CONFIG_SYS_FLASH0_SIZE * 1024 * 1024; /*size */
}
/*********************************************************************/
--- /dev/null
+#
+# (C) Copyright 2009 HALE electronic <helmut.raiger@hale.at>
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+COBJS := tt01.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ * (C) Copyright 2011 Helmut Raiger <helmut.raiger@hale.at>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/macro.h>
+
+.globl lowlevel_init
+lowlevel_init:
+ /* Also setup the Peripheral Port Remap register inside the core */
+ ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+ mov pc, lr
--- /dev/null
+/*
+ * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <command.h>
+#include <pmic.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BOARD_STRING "Board: HALE TT-01"
+
+/* Clock configuration */
+#define CCM_CCMR_SETUP 0x074B0BF5
+
+static void board_setup_clocks(void)
+{
+ struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE;
+ volatile int wait = 0x10000;
+
+ writel(CCM_CCMR_SETUP, &ccm->ccmr);
+ while (wait--)
+ ;
+
+ writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr);
+ writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
+
+ /* Set up clock to 532MHz */
+ writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) |
+ PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
+ PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
+ PDR0_MCU_PODF(0), &ccm->pdr0);
+ writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12),
+ &ccm->mpctl);
+ writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1),
+ &ccm->spctl);
+}
+
+/* DRAM configuration */
+
+#define ESDMISC_MDDR_SETUP 0x00000004
+#define ESDMISC_MDDR_RESET_DL 0x0000000c
+/*
+ * decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below:
+ * tXP = 11, tWTR = 0, tRP = 10, tMRD = 10
+ * tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11
+ * tRCD = 011, tRC = 010
+ * note: all but tWTR (1), tRC (111) are reset defaults,
+ * the same values work in the jtag configuration
+ *
+ * Bluetechnix setup has 0x75e73a (for 128MB) =
+ * 0b 0111 0101 1110 0111 0011 1010
+ * tXP = 11, tWTR = 1, tRP = 01, tMRD = 01
+ * tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11
+ * tRCD = 011, tRC = 010
+ */
+#define ESDCFG0_MDDR_SETUP 0x006ac73a
+#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
+#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
+ ESDCTL_DSIZ(2) | ESDCTL_BL(1))
+#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
+#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
+#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
+#define ESDCTL_RW ESDCTL_SETTINGS
+
+static void board_setup_sdram(void)
+{
+ u32 *pad;
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+ /*
+ * setup pad control for the controller pins
+ * no loopback, no pull, no keeper, no open drain,
+ * standard input, standard drive, slow slew rate
+ */
+ for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B;
+ pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++)
+ *pad = 0;
+
+ /* set up MX31 DDR Memory Controller */
+ writel(ESDMISC_MDDR_SETUP, &esdc->misc);
+ writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0);
+
+ /* perform DDR init sequence for CSD0 */
+ writel(ESDCTL_PRECHARGE, &esdc->ctl0);
+ writel(0x12344321, CSD0_BASE+0x0f00);
+ writel(ESDCTL_AUTOREFRESH, &esdc->ctl0);
+ writel(0x12344321, CSD0_BASE);
+ writel(0x12344321, CSD0_BASE);
+ writel(ESDCTL_LOADMODEREG, &esdc->ctl0);
+ writeb(0xda, CSD0_BASE+0x33);
+ writeb(0xff, CSD0_BASE+0x1000000);
+ writel(ESDCTL_RW, &esdc->ctl0);
+ writel(0xDEADBEEF, CSD0_BASE);
+ writel(ESDMISC_MDDR_RESET_DL, &esdc->misc);
+}
+
+static void tt01_spi3_hw_init(void)
+{
+ /* CSPI3 */
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC));
+ /* CSPI3, SS0 = Atlas */
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1));
+
+ /* start CSPI3 clock (3 = always on except if PLL off) */
+ setbits_le32(CCM_CGR0, 3 << 16);
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ /* CS4: FPGA incl. network controller */
+ struct mxc_weimcs cs4 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
+ };
+
+ /* this seems essential, won't start without, but why? */
+ writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF);
+
+ board_setup_clocks();
+ board_setup_sdram();
+ mxc_setup_weimcs(4, &cs4);
+
+ /* Setup UART2 and SPI3 pins */
+ mx31_uart2_hw_init();
+ tt01_spi3_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+ return 0;
+}
+
+int board_late_init(void)
+{
+ pmic_init();
+
+#ifdef CONFIG_HW_WATCHDOG
+ mxc_hw_watchdog_enable();
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts(BOARD_STRING "\n");
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
if (n == 17) {
int i;
char *p, *q;
- uchar ea[6];
/* see if it looks like an ethernet address */
for (i = 0; i < 6; i++) {
char term = (i == 5 ? '\0' : ':');
- ea[i] = simple_strtol (p, &q, 16);
+ (void)simple_strtol (p, &q, 16);
if ((q - p) != 2 || *q++ != term)
break;
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0, size_b1;
+ unsigned long size_b0;
int i;
/* Init: no FLASHes known */
- for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
flash_info[i].flash_id = FLASH_UNKNOWN;
- }
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 >> 20);
}
- if (FLASH_BASE1_PRELIM != 0x0) {
- size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
- if (size_b1 > size_b0) {
- printf ("## ERROR: Bank 1 (0x%08lx = %ld MB)"
- " > Bank 0 (0x%08lx = %ld MB)\n",
- size_b1, size_b1 >> 20,
- size_b0, size_b0 >> 20);
-
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[0].sector_count = -1;
- flash_info[1].sector_count = -1;
- flash_info[0].size = 0;
- flash_info[1].size = 0;
- return (0);
- }
- } else {
- size_b1 = 0;
- }
-
/* Remap FLASH according to real size */
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
#endif
/* ICU862 Board has only one Flash Bank */
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
-
flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
- return (size_b0 + size_b1);
+ return size_b0;
}
static void cfg_port_B (void)
{
- volatile immap_t *immap;
volatile cpm8xx_t *cp;
uint reg;
- immap = (immap_t *)CONFIG_SYS_IMMR;
cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
/*
- * Configure Port B for TPS2205 PC-Card Power-Interface Switch
- *
- * Switch off all voltages, assert shutdown
- */
+ * Configure Port B for TPS2205 PC-Card Power-Interface Switch
+ *
+ * Switch off all voltages, assert shutdown
+ */
reg = cp->cp_pbdat;
reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */
TPS2205_VCC3 | TPS2205_VCC5 | /* VAVCC => Hi-Z */
int pcmcia_hardware_enable(int slot)
{
- volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
udelay(10000);
- immap = (immap_t *)CONFIG_SYS_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
- volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
- immap = (immap_t *)CONFIG_SYS_IMMR;
cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
/*
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
- long psize, lsize;
+ long psize;
psize = 16 * 1024 * 1024;
- lsize = 0;
memctl->memc_psrt = CONFIG_SYS_PSRT;
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
mx25_uart1_init_pins();
#endif
/* board id for linux */
- gd->bd->bi_arch_number = MACH_TYPE_TX25;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
if (wait_for_ne != NULL) {
if (strcmp(wait_for_ne, "true") == 0) {
int cnt = 0;
+ int abort = 0;
puts("NE go: ");
while (startup_allowed() == 0) {
+ if (tstc()) {
+ (void) getc(); /* consume input */
+ abort = 1;
+ break;
+ }
udelay(200000);
cnt++;
if (cnt == 5)
puts(" \b\b\b\b");
}
}
- puts("OK\n");
+ if (abort == 1)
+ printf("\nAbort waiting for ne\n");
+ else
+ puts("OK\n");
}
}
#endif
kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
#endif
-
+#if defined(CONFIG_KM_RECONFIG_XLX)
+ /* trigger the reconfiguration of the xilinx fpga */
+ kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
+ kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
+ kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
+#endif
return 0;
}
int board_init(void)
{
- /*
- * arch number of board
- */
- gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
-
/* address of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
#endif
#if defined(CONFIG_BOOTCOUNT_LIMIT)
+const ulong patterns[] = { 0x00000000,
+ 0xFFFFFFFF,
+ 0xFF00FF00,
+ 0x0F0F0F0F,
+ 0xF0F0F0F0};
+const ulong NBR_OF_PATTERNS = sizeof(patterns)/sizeof(*patterns);
+const ulong OFFS_PATTERN = 3;
+const ulong REPEAT_PATTERN = 1000;
+
void bootcount_store(ulong a)
{
volatile ulong *save_addr;
save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
writel(a, save_addr);
writel(BOOTCOUNT_MAGIC, &save_addr[1]);
+
+ for (i = 0; i < REPEAT_PATTERN; i++)
+ writel(patterns[i % NBR_OF_PATTERNS],
+ &save_addr[i+OFFS_PATTERN]);
+
}
ulong bootcount_load(void)
{
volatile ulong *save_addr;
volatile ulong size = 0;
- int i;
+ ulong counter = 0;
+ int i, tmp;
+
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
size += gd->bd->bi_dram[i].size;
}
save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
- if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC)
- return 0;
- else
- return readl(save_addr);
+
+ counter = readl(&save_addr[0]);
+
+ /* Is the counter reliable, check in the big pattern for bit errors */
+ for (i = 0; (i < REPEAT_PATTERN) && (counter != 0); i++) {
+ tmp = readl(&save_addr[i+OFFS_PATTERN]);
+ if (tmp != patterns[i % NBR_OF_PATTERNS])
+ counter = 0;
+ }
+ return counter;
}
#endif
int pcmcia_hardware_enable(int slot)
{
- volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
udelay(10000);
- immap = (immap_t *)CONFIG_SYS_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
/*
- * Configure SIUMCR to enable PCMCIA port B
- * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
- */
+ * Configure SIUMCR to enable PCMCIA port B
+ * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+ */
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_per &= ~PCMCIA_MASK(slot);
/*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
+ * Disable interrupts, DMA, and PCMCIA buffers
+ * (isolate the interface) and assert RESET signal
+ */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
udelay(2500);
/*
- * Configure Port B pins for
- * 3 Volts enable
- */
+ * Configure Port B pins for
+ * 3 Volts enable
+ */
if (slot) { /* Slot A is built-in */
cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
}
/*
- * Make sure there is a card in the slot, then configure the interface.
- */
+ * Make sure there is a card in the slot, then configure the interface.
+ */
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
}
/*
- * Power On.
- */
+ * Power On.
+ */
printf("%s Slot %c:", slot ? "" : "\n", 'A' + slot);
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
reg = pcmp->pcmc_pipr;
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
- volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
if (!slot) /* Slot A is not configurable */
return 0;
- immap = (immap_t *)CONFIG_SYS_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
/*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(slot);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
debug ("PCMCIA power OFF\n");
/*
- * Configure Port B pins for
- * 3 Volts enable
- */
+ * Configure Port B pins for
+ * 3 Volts enable
+ */
cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
/* remove all power */
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size = 0;
- uchar *latch,rev,mod,tmp;
+ uchar *latch, rev, tmp;
/*
* Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision
latch = (uchar *)0x90000200;
tmp = swapbyte(*latch);
rev = (tmp & 0xF8) >> 3;
- mod = (tmp & 0x07);
upmconfig(UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
&ide_bus_offset32);
ide_bus_offset[0] = ide_bus_offset32 & 0xfffffffe;
ide_bus_offset[0] = pci_hose_bus_to_phys(&hose,
- ide_bus_offset[0] & 0xfffffffe,
- PCI_REGION_IO);
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2,
- (u32 *) &ide_bus_offset[1]);
- ide_bus_offset[1] &= 0xfffffffe;
- ide_bus_offset[1] = pci_hose_bus_to_phys(&hose,
- ide_bus_offset[1] & 0xfffffffe,
- PCI_REGION_IO);
+ ide_bus_offset[0] & 0xfffffffe,
+ PCI_REGION_IO);
+ if (CONFIG_SYS_IDE_MAXBUS > 1) {
+ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2,
+ (u32 *) &ide_bus_offset[1]);
+ ide_bus_offset[1] &= 0xfffffffe;
+ ide_bus_offset[1] = pci_hose_bus_to_phys(&hose,
+ ide_bus_offset[1] & 0xfffffffe,
+ PCI_REGION_IO);
+ }
}
if (pci_find_device (PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212, 0) != -1) {
int pcmcia_hardware_enable(int slot)
{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, mask;
#endif
udelay(10000);
- immap = (immap_t *)CONFIG_SYS_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
/*
* Configure SIUMCR to enable PCMCIA port B
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
- volatile immap_t *immap;
volatile pcmconf8xx_t *pcmp;
u_long reg;
uchar val;
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
- immap = (immap_t *)CONFIG_SYS_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
/*
* Disable PCMCIA buffers (isolate the interface)
immap = (immap_t *)CONFIG_SYS_IMMR;
/*
- * Configure Port A for MAX1602 PC-Card Power-Interface Switch
- */
+ * Configure Port A for MAX1602 PC-Card Power-Interface Switch
+ */
immap->im_ioport.iop_padat &= ~0x8000; /* set port x output to low */
immap->im_ioport.iop_padir |= 0x8000; /* enable port x as output */
int pcmcia_hardware_enable(int slot)
{
volatile immap_t *immap;
- volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, mask;
immap = (immap_t *)CONFIG_SYS_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
cfg_ports ();
/*
- * Configure SIUMCR to enable PCMCIA port B
- * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
- */
+ * Configure SIUMCR to enable PCMCIA port B
+ * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+ */
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
/*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
+ * Disable interrupts, DMA, and PCMCIA buffers
+ * (isolate the interface) and assert RESET signal
+ */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
udelay(500);
/*
- * Make sure there is a card in the slot, then configure the interface.
- */
+ * Make sure there is a card in the slot, then configure the interface.
+ */
udelay(10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
}
/*
- * Power On.
- */
+ * Power On.
+ */
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
reg = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
reg,
(reg&PCMCIA_VS1(slot))?"n":"ff",
(reg&PCMCIA_VS2(slot))?"n":"ff");
- if ((reg & mask) == mask) {
+
+ if ((reg & mask) == mask)
puts (" 5.0V card found: ");
- } else {
+ else
puts (" 3.3V card found: ");
- }
/* switch VCC on */
immap->im_ioport.iop_padat |= 0x8000; /* power enable 3.3V */
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
- volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("voltage_set: "
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
- immap = (immap_t *)CONFIG_SYS_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
/*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
udelay(500);
/*
- * Configure Port C pins for
- * 5 Volts Enable and 3 Volts enable,
- * Turn all power pins to Hi-Z
- */
+ * Configure Port C pins for
+ * 5 Volts Enable and 3 Volts enable,
+ * Turn all power pins to Hi-Z
+ */
debug ("PCMCIA power OFF\n");
cfg_ports (); /* Enables switch, but all in Hi-Z */
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += mvblx.o fpga.o
+COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o
+COBJS := $(COBJS-y)
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+CFLAGS += -Werror
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2011
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ * Michael Jones, Matrix Vision GmbH, michael.jones@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include <asm/gpio.h>
+#include "fpga.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+ fpga_null_fn, /* Altera_pre_fn */
+ fpga_config_fn,
+ fpga_status_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ fpga_null_fn,
+ fpga_null_fn,
+};
+
+Altera_desc cyclone2 = {
+ Altera_CYC2,
+ fast_passive_parallel,
+ Altera_EP3C5_SIZE,
+ (void *) &altera_fns,
+ NULL,
+ 0
+};
+
+#define GPIO_RESET 43
+#define GPIO_DCLK 65
+#define GPIO_nSTATUS 157
+#define GPIO_CONF_DONE 158
+#define GPIO_nCONFIG 159
+#define GPIO_DATA0 54
+#define GPIO_DATA1 55
+#define GPIO_DATA2 56
+#define GPIO_DATA3 57
+#define GPIO_DATA4 58
+#define GPIO_DATA5 60
+#define GPIO_DATA6 61
+#define GPIO_DATA7 62
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* return FPGA_SUCCESS on success, else FPGA_FAIL
+ */
+int mvblx_init_fpga(void)
+{
+ fpga_debug("Initializing FPGA interface\n");
+ fpga_init();
+ fpga_add(fpga_altera, &cyclone2);
+
+ if (gpio_request(GPIO_DCLK, "dclk") ||
+ gpio_request(GPIO_nSTATUS, "nStatus") ||
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ gpio_request(GPIO_CONF_DONE, "conf_done") ||
+#endif
+ gpio_request(GPIO_nCONFIG, "nConfig") ||
+ gpio_request(GPIO_DATA0, "data0") ||
+ gpio_request(GPIO_DATA1, "data1") ||
+ gpio_request(GPIO_DATA2, "data2") ||
+ gpio_request(GPIO_DATA3, "data3") ||
+ gpio_request(GPIO_DATA4, "data4") ||
+ gpio_request(GPIO_DATA5, "data5") ||
+ gpio_request(GPIO_DATA6, "data6") ||
+ gpio_request(GPIO_DATA7, "data7")) {
+ printf("%s: error requesting GPIOs.", __func__);
+ return FPGA_FAIL;
+ }
+
+ /* set up outputs */
+ gpio_direction_output(GPIO_DCLK, 0);
+ gpio_direction_output(GPIO_nCONFIG, 0);
+ gpio_direction_output(GPIO_DATA0, 0);
+ gpio_direction_output(GPIO_DATA1, 0);
+ gpio_direction_output(GPIO_DATA2, 0);
+ gpio_direction_output(GPIO_DATA3, 0);
+ gpio_direction_output(GPIO_DATA4, 0);
+ gpio_direction_output(GPIO_DATA5, 0);
+ gpio_direction_output(GPIO_DATA6, 0);
+ gpio_direction_output(GPIO_DATA7, 0);
+
+ /* NB omap_free_gpio() resets to an input, so we can't
+ * free ie. nCONFIG, or else the FPGA would reset
+ * Q: presumably gpio_free() has the same effect?
+ */
+
+ /* set up inputs */
+ gpio_direction_input(GPIO_nSTATUS);
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ gpio_direction_input(GPIO_CONF_DONE);
+#endif
+
+ fpga_config_fn(0, 1, 0);
+ udelay(60);
+
+ return FPGA_SUCCESS;
+}
+
+int fpga_null_fn(int cookie)
+{
+ return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+ fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert);
+ if (flush) {
+ gpio_set_value(GPIO_nCONFIG, !assert);
+ udelay(1);
+ gpio_set_value(GPIO_nCONFIG, assert);
+ }
+
+ return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+ int result = 0;
+
+ /* since revA of BLX, we will not get this signal. */
+ udelay(10);
+#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ fpga_debug("not waiting for CONF_DONE.");
+ result = 1;
+#else
+ fpga_debug("CONF_DONE check ... ");
+ if (gpio_get_value(GPIO_CONF_DONE)) {
+ fpga_debug("high\n");
+ result = 1;
+ } else
+ fpga_debug("low\n");
+ gpio_free(GPIO_CONF_DONE);
+#endif
+
+ return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+ int result = 0;
+ fpga_debug("STATUS check ... ");
+
+ result = gpio_get_value(GPIO_nSTATUS);
+
+ if (result < 0)
+ fpga_debug("error\n");
+ else if (result > 0)
+ fpga_debug("high\n");
+ else
+ fpga_debug("low\n");
+
+ return result;
+}
+
+static inline int _write_fpga(u8 byte)
+{
+ gpio_set_value(GPIO_DATA0, byte & 0x01);
+ gpio_set_value(GPIO_DATA1, (byte >> 1) & 0x01);
+ gpio_set_value(GPIO_DATA2, (byte >> 2) & 0x01);
+ gpio_set_value(GPIO_DATA3, (byte >> 3) & 0x01);
+ gpio_set_value(GPIO_DATA4, (byte >> 4) & 0x01);
+ gpio_set_value(GPIO_DATA5, (byte >> 5) & 0x01);
+ gpio_set_value(GPIO_DATA6, (byte >> 6) & 0x01);
+ gpio_set_value(GPIO_DATA7, (byte >> 7) & 0x01);
+
+ /* clock */
+ gpio_set_value(GPIO_DCLK, 1);
+ udelay(1);
+ gpio_set_value(GPIO_DCLK, 0);
+ udelay(1);
+
+ return 0;
+}
+
+int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
+{
+ unsigned char *data = (unsigned char *) buf;
+ int i;
+
+ fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+ for (i = 0; i < len; i++)
+ _write_fpga(data[i]);
+ fpga_debug("-%s\n", __func__);
+
+ return FPGA_SUCCESS;
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvblx_init_fpga(void);
+
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
--- /dev/null
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from Beagle and Overo
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "mvblx.h"
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void);
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ printf("mvBlueLYNX-X\n");
+ if (get_cpu_family() == CPU_OMAP36XX)
+ setenv("mpurate", "1000");
+ else
+ setenv("mpurate", "600");
+
+ twl4030_power_init();
+
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif /* CONFIG_CMD_NET */
+
+ mvblx_init_fpga();
+
+ mac_read_from_eeprom();
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_MVBLX();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0);
+ omap_mmc_init(1);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET)
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ /* Configure GPMC registers */
+ writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1);
+ writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2);
+ writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3);
+ writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4);
+ writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5);
+ writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6);
+ writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+
+ /* Make GPIO 139 as output pin */
+ writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe);
+
+ /* Now send a pulse on the GPIO pin */
+ writel(GPIO11, &gpio5_base->setdataout);
+ udelay(1);
+ writel(GPIO11, &gpio5_base->cleardataout);
+ udelay(1);
+ writel(GPIO11, &gpio5_base->setdataout);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+
+int overwrite_console(void)
+{
+ /* return TRUE if console should be overwritten */
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET */
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MVBLX_H_
+#define _MVBLX_H_
+
+#include <asm/arch/sys_proto.h>
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "OMAP3 mvBlueLYNX-X camera",
+ "no NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_MVBLX() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M4)) /*GPIO_41*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO_42*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO_43*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO54*/\
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4)) /*GPIO55*/\
+ MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) /*GPIO56*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) /*GPIO57*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) /*GPIO58*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IEN | PTU | EN | M4)) /*GPIO60*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M4)) /*GPIO61*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTU | EN | M4)) /*GPIO62*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4)) /*GPIO65*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card 1*/\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M7)) /*GPIO_129 disabled*/\
+ /*Expansion card 2 */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | DIS | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M1)) /*UART2_RX*/\
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) /*GPIO_150*/ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\
+ MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IDIS | PTU | DIS | M4)) /*GPIO_171*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTU | DIS | M4)) /*GPIO_172*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IDIS | PTU | DIS | M4)) /*GPIO_173*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTD | DIS | M4)) /*GPIO_174*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /*GPIO_177*/\
+ /* USB EHCI (port 2) not used */\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+ MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+ MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+ MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) /*GPIO_10*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT2*/\
+ /* USB EHCI (port 1) */\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M4)) /*GPIO_25*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M4)) /*GPIO_26*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M4)) /*GPIO_27*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M4)) /*GPIO_28*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M4)) /*GPIO_29*/\
+ /*Die to Die */\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+
+#endif
--- /dev/null
+/*
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ * York Sun (yorksun@freescale.com)
+ * Haiying Wang (haiying.wang@freescale.com)
+ * Timur Tabi (timur@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+
+/* #define DEBUG */
+
+/*
+ * static eeprom: EEPROM layout
+ */
+static struct __attribute__ ((__packed__)) eeprom {
+ u8 id[16]; /* 0x01 - 0x0F Type e.g. 100wG-5111 */
+ u8 sn[10]; /* 0x10 - 0x19 Serial Number */
+ u8 date[6]; /* 0x1A - 0x1F Build Date */
+ u8 mac[6]; /* 0x20 - 0x25 MAC address */
+ u8 reserved[10];/* 0x26 - 0x2f reserved */
+ u32 crc; /* x+1 CRC32 checksum */
+} e;
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read;
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
+{
+ unsigned int crc;
+ char safe_string[16];
+
+#ifdef DEBUG
+ int i;
+#endif
+ u8 *p;
+
+ /* ID */
+ strncpy(safe_string, (char *)e.id, sizeof(e.id));
+ safe_string[sizeof(e.id)-1] = 0;
+ printf("ID: mvBlueLYNX-X%s\n", safe_string);
+
+ /* Serial number */
+ strncpy(safe_string, (char *)e.sn, sizeof(e.sn));
+ safe_string[sizeof(e.sn)-1] = 0;
+ printf("SN: %s\n", safe_string);
+
+ /* Build date, BCD date values, as YYMMDDhhmmss */
+ printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
+ e.date[0], e.date[1], e.date[2],
+ e.date[3] & 0x7F, e.date[4], e.date[5],
+ e.date[3] & 0x80 ? "PM" : "");
+
+ /* Show MAC address */
+ p = e.mac;
+ printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ p[0], p[1], p[2], p[3], p[4], p[5]);
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+ if (crc == be32_to_cpu(e.crc))
+ printf("CRC: %08x\n", be32_to_cpu(e.crc));
+ else
+ printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc);
+
+#ifdef DEBUG
+ printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
+ for (i = 0; i < sizeof(e); i++) {
+ if ((i % 16) == 0)
+ printf("%02X: ", i);
+ printf("%02X ", ((u8 *)&e)[i]);
+ if (((i % 16) == 15) || (i == sizeof(e) - 1))
+ printf("\n");
+ }
+#endif
+}
+
+/**
+ * read_eeprom - read the EEPROM into memory
+ */
+static int read_eeprom(void)
+{
+ int ret;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ if (has_been_read)
+ return 0;
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e, sizeof(e));
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+#ifdef DEBUG
+ show_eeprom();
+#endif
+
+ has_been_read = (ret == 0) ? 1 : 0;
+
+ return ret;
+}
+
+/**
+ * update_crc - update the CRC
+ *
+ * This function should be called after each update to the EEPROM structure,
+ * to make sure the CRC is always correct.
+ */
+static void update_crc(void)
+{
+ u32 crc;
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+ e.crc = cpu_to_be32(crc);
+}
+
+/**
+ * prog_eeprom - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
+{
+ int ret = 0;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ update_crc();
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e, sizeof(e));
+
+ if (!ret) {
+ /* Verify the write by reading back the EEPROM and comparing */
+ struct eeprom e2;
+#ifdef DEBUG
+ printf("%s verifying...\n", __func__);
+#endif
+ ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e2, sizeof(e2));
+
+ if (!ret && memcmp(&e, &e2, sizeof(e)))
+ ret = -1;
+ }
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+ if (ret) {
+ printf("Programming failed.\n");
+ has_been_read = 0;
+ return -1;
+ }
+
+ printf("Programming passed.\n");
+ return 0;
+}
+
+/**
+ * h2i - converts hex character into a number
+ *
+ * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
+ * the integer equivalent.
+ */
+static inline u8 h2i(char p)
+{
+ if ((p >= '0') && (p <= '9'))
+ return p - '0';
+
+ if ((p >= 'A') && (p <= 'F'))
+ return (p - 'A') + 10;
+
+ if ((p >= 'a') && (p <= 'f'))
+ return (p - 'a') + 10;
+
+ return 0;
+}
+
+/**
+ * set_date - stores the build date into the EEPROM
+ *
+ * This function takes a pointer to a string in the format "YYMMDDhhmmss"
+ * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
+ * and stores it in the build date field of the EEPROM local copy.
+ */
+static void set_date(const char *string)
+{
+ unsigned int i;
+
+ if (strlen(string) != 12) {
+ printf("Usage: mac date YYMMDDhhmmss\n");
+ return;
+ }
+
+ for (i = 0; i < 6; i++)
+ e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
+
+ update_crc();
+}
+
+/**
+ * set_mac_address - stores a MAC address into the EEPROM
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
+ * stores it in the MAC address field in the EEPROM local copy.
+ */
+static void set_mac_address(const char *string)
+{
+ char *p = (char *) string;
+ unsigned int i;
+
+ for (i = 0; *p && (i < 6); i++) {
+ e.mac[i] = simple_strtoul(p, &p, 16);
+ if (*p == ':')
+ p++;
+ }
+
+ update_crc();
+}
+
+int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char cmd;
+
+ if (argc == 1) {
+ show_eeprom();
+ return 0;
+ }
+
+ cmd = argv[1][0];
+
+ if (cmd == 'r') {
+#ifdef DEBUG
+ printf("%s read\n", __func__);
+#endif
+ read_eeprom();
+ return 0;
+ }
+
+ if (argc == 2) {
+ switch (cmd) {
+ case 's': /* save */
+#ifdef DEBUG
+ printf("%s save\n", __func__);
+#endif
+ prog_eeprom();
+ break;
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+ }
+
+ /* We know we have at least one parameter */
+
+ switch (cmd) {
+ case 'n': /* serial number */
+#ifdef DEBUG
+ printf("%s serial number\n", __func__);
+#endif
+ memset(e.sn, 0, sizeof(e.sn));
+ strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
+ update_crc();
+ break;
+ case 'd': /* date BCD format YYMMDDhhmmss */
+ set_date(argv[2]);
+ break;
+ case 'e': /* errata */
+ printf("mac errata not implemented\n");
+ break;
+ case 'i': /* id */
+ memset(e.id, 0, sizeof(e.id));
+ strncpy((char *)e.id, argv[2], sizeof(e.id) - 1);
+ update_crc();
+ break;
+ case 'p': /* ports */
+ printf("mac ports not implemented (always 1 port)\n");
+ break;
+ case '0' ... '9':
+ /* we only have "mac 0" but any digit can be used here */
+ set_mac_address(argv[2]);
+ break;
+ case 'h': /* help */
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+}
+
+int mac_read_from_eeprom(void)
+{
+ u32 crc, crc_offset = offsetof(struct eeprom, crc);
+ u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+
+ if (read_eeprom()) {
+ printf("EEPROM Read failed.\n");
+ return -1;
+ }
+
+ crc = crc32(0, (void *)&e, crc_offset);
+ crcp = (void *)&e + crc_offset;
+ if (crc != be32_to_cpu(*crcp)) {
+ printf("EEPROM CRC mismatch (%08x != %08x)\n", crc,
+ be32_to_cpu(e.crc));
+ return -1;
+ }
+
+ if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) &&
+ memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
+ char ethaddr[9];
+
+ sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+ e.mac[0],
+ e.mac[1],
+ e.mac[2],
+ e.mac[3],
+ e.mac[4],
+ e.mac[5]);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv("ethaddr"))
+ setenv("ethaddr", ethaddr);
+ }
+
+ if (memcmp(&e.sn, "\0\0\0\0\0\0\0\0\0\0", 10) &&
+ memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) {
+ char serial_num[12];
+
+ strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv("serial#"))
+ setenv("serial#", serial_num);
+ }
+
+ /* TODO should I calculate CRC here? */
+ return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *serial = getenv("serial#");
+
+ if (serial && (strlen(serial) > 3)) {
+ /* use the numerical part of the serial number LXnnnnnn */
+ serialnr->high = 0;
+ serialnr->low = simple_strtoul(serial + 2, NULL, 10);
+ } else {
+ serialnr->high = 0;
+ serialnr->low = 0;
+ }
+}
+#endif
/* ------------------------------------------------------------------------- */
+#ifdef CONFIG_SYS_USE_OSCCLK
static unsigned int get_reffreq(void);
+#endif
static unsigned int board_get_cpufreq(void);
void mbx_init (void)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
- ulong speed, refclock, plprcr, sccr;
+ ulong speed, plprcr, sccr;
ulong br0_32 = memctl->memc_br0 & 0x400;
/* real-time clock status and control register */
immr->im_clkrst.car_sccr = sccr;
speed = board_get_cpufreq ();
- refclock = get_reffreq ();
#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0)
plprcr = CONFIG_SYS_PLPRCR;
#endif
#ifdef CONFIG_SYS_USE_OSCCLK /* See doc/README.MBX ! */
- plprcr |= ((speed + refclock / 2) / refclock - 1) << 20;
+ plprcr |= ((speed + get_reffreq() / 2) / refclock - 1) << 20;
#endif
immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
{
#ifndef CONFIG_8xx_GCLK_FREQ
vpd_packet_t *packet;
+ ulong *p;
packet = vpd_find_packet (VPD_PID_ICS);
- return *((ulong *) packet->data);
+ p = (ulong *)packet->data;
+ return *p;
#else
return((unsigned int)CONFIG_8xx_GCLK_FREQ );
#endif /* CONFIG_8xx_GCLK_FREQ */
}
+#ifdef CONFIG_SYS_USE_OSCCLK
static unsigned int get_reffreq (void)
{
vpd_packet_t *packet;
+ ulong *p;
packet = vpd_find_packet (VPD_PID_RCS);
- return *((ulong *) packet->data);
+ p = (ulong *)packet->data;
+ return *p;
}
+#endif
static void board_get_enetaddr(uchar *addr)
{
int pcmcia_hardware_enable (int slot)
{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
uint reg, mask;
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n",
udelay (10000);
- immap = (immap_t *) CONFIG_SYS_IMMR;
- sysp = (sysconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_cpm));
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK (_slot_);
{
block_dev_desc_t *stor_dev;
long sz;
- int i, res = 0, bitmap_first, cnt, old_ctrlc, got_ctrlc;
+ int i, res = 0, cnt, old_ctrlc;
char *env;
long start, end;
/* make sure that we see CTRL-C and save the old state */
old_ctrlc = disable_ctrlc(0);
- bitmap_first = 0;
-
/* validate the images first */
for (i = 0; i < AU_MAXFILES; i++) {
ulong imsize;
/* this is really not a good idea, but it's what the */
/* customer wants. */
cnt = 0;
- got_ctrlc = 0;
do {
res = au_do_update(i, sz);
/* let the user break out of the loop */
if (ctrlc() || had_ctrlc()) {
clear_ctrlc();
- if (res < 0)
- got_ctrlc = 1;
break;
}
cnt++;
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
- vu_long *addr = (vu_long *) (info->start[0]);
- int prot, sect, l_sect;
+ int prot, sect;
flash_dev_t *dev = NULL;
if ((s_first < 0) || (s_first > s_last)) {
printf ("\n");
}
- l_sect = -1;
-
/* Start erase on unprotected sectors */
dev = getFlashDevFromInfo (info);
if (dev) {
printf ("Erase FLASH[%s] -%d sectors:", dev->name, dev->sectors);
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long *) (dev->base);
- /* printf("erase_sector: sector=%d, addr=0x%x\n",
- sect, addr); */
printf (".");
if (ERROR == flashEraseSector (dev, sect)) {
printf ("ERROR: could not erase sector %d on FLASH[%s]\n", sect, dev->name);
{
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
volatile FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
int i, rcode = 0;
printf ("\n");
}
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
rcode |= wait_for_DQ7(info, sect);
}
}
- l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
-#if 0
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
- wait_for_DQ7(info, l_sect);
-
-DONE:
-#endif
/* reset to read mode */
addr = (FLASH_WORD_SIZE *)info->start[0];
addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
static void s_write_BR(int s_id, unsigned int regno, unsigned int val)
{
unsigned int address;
- unsigned int v;
address = 0x70 | (regno & 15);
val &= 0xff;
- v = s_transfer_internal(s_id, address, val);
+ (void)s_transfer_internal(s_id, address, val);
}
static void s_write_OR(int s_id, unsigned int regno, unsigned int val)
{
unsigned int address;
- unsigned int v;
address = 0x70 | (regno & 15);
val &= 0xff;
- v = s_transfer_internal(s_id, address, val);
+ (void)s_transfer_internal(s_id, address, val);
}
static void s_write_NR(int s_id, unsigned int regno, unsigned int val)
{
unsigned int address;
- unsigned int v;
address = (regno & 7) << 4;
val &= 0xf;
- v = s_transfer_internal(s_id, address | val, 0x00);
+ (void)s_transfer_internal(s_id, address | val, 0x00);
}
#define BR7_IFR 0x08 /* IDL2 free run */
static void cfg_ports (void)
{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
-
- immap = (immap_t *)CONFIG_SYS_IMMR;
- cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
-
-
cfg_vppd(0); cfg_vppd(1); /* VPPD0,VPPD1 VAVPP => Hi-Z */
cfg_vccd(0); cfg_vccd(1); /* 3V and 5V off */
cfg_shdn();
cfg_oc();
/*
- * Configure Port A for TPS2211 PC-Card Power-Interface Switch
- *
- * Switch off all voltages, assert shutdown
- */
+ * Configure Port A for TPS2211 PC-Card Power-Interface Switch
+ *
+ * Switch off all voltages, assert shutdown
+ */
set_vppd(0, 1); set_vppd(1, 1);
set_vccd(0, 0); set_vccd(1, 0);
set_shdn(1);
int pcmcia_hardware_enable(int slot)
{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
- volatile sysconf8xx_t *sysp;
uint reg, pipr, mask;
int i;
udelay(10000);
- immap = (immap_t *)CONFIG_SYS_IMMR;
- sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
cfg_ports ();
pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
/*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
+ * Disable interrupts, DMA, and PCMCIA buffers
+ * (isolate the interface) and assert RESET signal
+ */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
}
/*
- * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
- */
+ * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
+ */
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
pipr = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
#if defined(CONFIG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
- volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
- immap = (immap_t *)CONFIG_SYS_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
/* Configure PCMCIA General Control Register */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
u_long reg;
- ushort sreg;
debug ("voltage_set: "
PCMCIA_BOARD_MSG
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
- immap = (immap_t *)CONFIG_SYS_IMMR;
- cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
/*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(_slot_);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
udelay(500);
/*
- * Configure Port C pins for
- * 5 Volts Enable and 3 Volts enable,
- * Turn all power pins to Hi-Z
- */
+ * Configure Port C pins for
+ * 5 Volts Enable and 3 Volts enable,
+ * Turn all power pins to Hi-Z
+ */
debug ("PCMCIA power OFF\n");
cfg_ports (); /* Enables switch, but all in Hi-Z */
- sreg = immap->im_ioport.iop_pcdat;
set_vppd(0, 1); set_vppd(1, 1);
switch(vcc) {
- case 0:
- break; /* Switch off */
+ case 0:
+ break; /* Switch off */
- case 33:
- set_vccd(0, 1); set_vccd(1, 0);
- break;
+ case 33:
+ set_vccd(0, 1); set_vccd(1, 0);
+ break;
- case 50:
- set_vccd(0, 0); set_vccd(1, 1);
- break;
+ case 50:
+ set_vccd(0, 0); set_vccd(1, 1);
+ break;
- default:
- goto done;
+ default:
+ goto done;
}
/* Checking supported voltages */
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
}
start = get_timer (0);
- last = start;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
printf (" done\n");
}
}
+
+ if (flag)
+ enable_interrupts();
+
return rcode;
}
ulong status;
ulong start;
int flag;
+ int rcode = 0;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
- return (1);
+ rcode = 1;
+ break;
}
}
*addr = (FPW) 0x00FF00FF; /* restore read mode */
- return (0);
+ if (flag)
+ enable_interrupts();
+
+ return rcode;
}
void inline spin_wheel (void)
int pcmcia_hardware_enable(int slot)
{
volatile immap_t *immap;
- volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, mask;
immap = (immap_t *)CONFIG_SYS_IMMR;
sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
- cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
/*
* Configure SIUMCR to enable PCMCIA port B
int pcmcia_hardware_disable(int slot)
{
volatile immap_t *immap;
- volatile pcmconf8xx_t *pcmp;
u_long reg;
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
immap = (immap_t *)CONFIG_SYS_IMMR;
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
/* remove all power */
immap->im_ioport.iop_pcdat |= 0x0400;
#include <common.h>
#include <mpc8xx.h>
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-/*-----------------------------------------------------------------------
+/*
* Functions
*/
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
+static ulong flash_get_size(vu_long *addr, flash_info_t *info);
+static int write_word(flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
-unsigned long flash_init (void)
+unsigned long flash_init(void)
{
- unsigned long size_b0, size_b1;
+ unsigned long size_b0;
int i;
/* Init: no FLASHes known */
- for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- flash_info[i].flash_id = FLASH_UNKNOWN;
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+ flash_info[i].flash_id = FLASH_UNKNOWN;
/* Detect size */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+ size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE,
+ &flash_info[0]);
/* Setup offsets */
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+ flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* Monitor protection ON by default */
&flash_info[0]);
#endif
- size_b1 = 0 ;
-
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
-
flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
- return (size_b0 + size_b1);
+ return size_b0;
}
/*-----------------------------------------------------------------------
* Fix this to support variable sector sizes
*/
-static void flash_get_offsets (ulong base, flash_info_t *info)
+static void flash_get_offsets(ulong base, flash_info_t *info)
{
int i;
/*-----------------------------------------------------------------------
*/
-void flash_print_info (flash_info_t *info)
+void flash_print_info(flash_info_t *info)
{
int i;
- if (info->flash_id == FLASH_UNKNOWN)
- {
- puts ("missing or unknown FLASH type\n");
+ if (info->flash_id == FLASH_UNKNOWN) {
+ puts("missing or unknown FLASH type\n");
return;
}
- switch (info->flash_id & FLASH_VENDMASK)
- {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
- default: printf ("Unknown Vendor "); break;
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ case FLASH_MAN_BM:
+ printf("BRIGHT MICRO ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
}
- switch (info->flash_id & FLASH_TYPEMASK)
- {
- case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
- break;
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040:
+ printf("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+ break;
+ case FLASH_AM400B:
+ printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T:
+ printf("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T:
+ printf("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B:
+ printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T:
+ printf("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B:
+ printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
}
if (info->size >> 20) {
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20,
- info->sector_count);
+ printf(" Size: %ld MB in %d Sectors\n",
+ info->size >> 20,
+ info->sector_count);
} else {
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10,
- info->sector_count);
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10,
+ info->sector_count);
}
- puts (" Sector Start Addresses:");
+ puts(" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i)
- {
+ for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
- {
- puts ("\n ");
- }
+ puts("\n ");
- printf (" %08lX%s",
+ printf(" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " ");
}
- putc ('\n');
+ putc('\n');
return;
}
-/*-----------------------------------------------------------------------
- */
/*
* The following code cannot be run from FLASH!
*/
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+static ulong flash_get_size(vu_long *addr, flash_info_t *info)
{
short i;
volatile unsigned char *caddr;
/* Write auto select command: read Manufacturer ID */
-#if 0
- printf("Base address is: %08x\n", caddr);
-#endif
+ debug("Base address is: %8p\n", caddr);
caddr[0x0555] = 0xAA;
caddr[0x02AA] = 0x55;
value = caddr[0];
-#if 0
- printf("Manufact ID: %02x\n", value);
-#endif
- switch (value)
- {
- case 0x01: /*AMD_MANUFACT*/
- info->flash_id = FLASH_MAN_AMD;
+ debug("Manufact ID: %02x\n", value);
+
+ switch (value) {
+ case 0x01: /*AMD_MANUFACT*/
+ info->flash_id = FLASH_MAN_AMD;
break;
- case 0x04: /*FUJ_MANUFACT*/
- info->flash_id = FLASH_MAN_FUJ;
+ case 0x04: /*FUJ_MANUFACT*/
+ info->flash_id = FLASH_MAN_FUJ;
break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ break;
}
value = caddr[1]; /* device ID */
-#if 0
- printf("Device ID: %02x\n", value);
-#endif
- switch (value)
- {
- case AMD_ID_LV040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break; /* => 512Kb */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
+ debug("Device ID: %02x\n", value);
+
+ switch (value) {
+ case AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x00080000;
+ break; /* => 512Kb */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return 0; /* => no or unknown flash */
}
- flash_get_offsets ((ulong)addr, &flash_info[0]);
+ flash_get_offsets((ulong)addr, &flash_info[0]);
/* check for protected sectors */
- for (i = 0; i < info->sector_count; i++)
- {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
+ for (i = 0; i < info->sector_count; i++) {
+ /*
+ * read sector protection at sector address,
+ * (A7 .. A0) = 0x02
+ * D0 = 1 if protected
+ */
caddr = (volatile unsigned char *)(info->start[i]);
info->protect[i] = caddr[2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
- if (info->flash_id != FLASH_UNKNOWN)
- {
+ if (info->flash_id != FLASH_UNKNOWN) {
caddr = (volatile unsigned char *)info->start[0];
*caddr = 0xF0; /* reset bank */
}
- return (info->size);
+ return info->size;
}
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase(flash_info_t *info, int s_first, int s_last)
{
- volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
+ volatile unsigned char *addr =
+ (volatile unsigned char *)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
+ if (info->flash_id == FLASH_UNKNOWN)
+ printf("- missing\n");
+ else
+ printf("- no sectors to erase\n");
+
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type - aborted\n");
+ printf("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
prot++;
- }
}
if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
+ printf("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
- printf ("\n");
+ printf("\n");
}
l_sect = -1;
addr[0x02AA] = 0x55;
/* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
+ for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (volatile unsigned char *)(info->start[sect]);
addr[0] = 0x30;
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
- udelay (1000);
+ udelay(1000);
/*
* We wait for the last triggered sector
if (l_sect < 0)
goto DONE;
- start = get_timer (0);
+ start = get_timer(0);
last = start;
addr = (volatile unsigned char *)(info->start[l_sect]);
- while ((addr[0] & 0xFF) != 0xFF)
- {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
+ while ((addr[0] & 0xFF) != 0xFF) {
+ now = get_timer(start);
+ if (now > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
- putc ('.');
+ putc('.');
last = now;
}
}
addr[0] = 0xF0; /* reset bank */
- printf (" done\n");
+ printf(" done\n");
return 0;
}
-/*-----------------------------------------------------------------------
+/*
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
/*
* handle unaligned start bytes
*/
- if ((l = addr - wp) != 0) {
+ l = addr - wp;
+
+ if (l != 0) {
data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
+ for (i = 0, cp = wp; i < l; ++i, ++cp)
data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
+
+ for (; i < 4 && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
- for (; cnt==0 && i<4; ++i, ++cp) {
+
+ for (; cnt == 0 && i < 4; ++i, ++cp)
data = (data << 8) | (*(uchar *)cp);
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
+ rc = write_word(info, wp, data);
+
+ if (rc != 0)
+ return rc;
+
wp += 4;
}
*/
while (cnt >= 4) {
data = 0;
- for (i=0; i<4; ++i) {
+ for (i = 0; i < 4; ++i)
data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
+
+ rc = write_word(info, wp, data);
+
+ if (rc != 0)
+ return rc;
+
wp += 4;
cnt -= 4;
}
- if (cnt == 0) {
- return (0);
- }
+ if (cnt == 0)
+ return 0;
/*
* handle unaligned tail bytes
*/
data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
- for (; i<4; ++i, ++cp) {
+ for (; i < 4; ++i, ++cp)
data = (data << 8) | (*(uchar *)cp);
- }
- return (write_word(info, wp, data));
+ return write_word(info, wp, data);
}
-/*-----------------------------------------------------------------------
+/*
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
-static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int write_word(flash_info_t *info, ulong dest, ulong data)
{
- volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]),
- *cdest,*cdata;
+ volatile unsigned char *cdest, *cdata;
+ volatile unsigned char *addr =
+ (volatile unsigned char *)(info->start[0]);
ulong start;
int flag, count = 4 ;
cdata = (volatile unsigned char *)&data ;
/* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
+ if ((*((vu_long *)dest)&data) != data)
+ return 2;
- while(count--)
- {
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
+ while (count--) {
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0xA0;
+ addr[0x0555] = 0xAA;
+ addr[0x02AA] = 0x55;
+ addr[0x0555] = 0xA0;
- *cdest = *cdata;
+ *cdest = *cdata;
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
- /* data polling for D7 */
- start = get_timer (0);
- while ((*cdest ^ *cdata) & 0x80)
- {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((*cdest ^ *cdata) & 0x80) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+ return 1;
}
- }
- cdata++ ;
- cdest++ ;
+ cdata++ ;
+ cdest++ ;
}
- return (0);
+ return 0;
}
-
-/*-----------------------------------------------------------------------
- */
/*-----------------------------------------------------------------------
*/
-unsigned long flash_init (void)
+unsigned long flash_init(void)
{
- unsigned long size;
- int i;
+ int i;
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+ flash_info[i].flash_id = FLASH_UNKNOWN;
- /* for now, only support the 4 MB Flash SIMM */
- size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
+ /* for now, only support the 4 MB Flash SIMM */
+ (void)flash_get_size((vu_long *) CONFIG_SYS_FLASH0_BASE,
+ &flash_info[0]);
- /*
- * protect monitor and environment sectors
- */
+ /*
+ * protect monitor and environment sectors
+ */
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+ &flash_info[0]);
#endif
#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
+#ifndef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#endif
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
#endif
- return /*size*/ (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024);
+ return CONFIG_SYS_FLASH0_SIZE * 1024 * 1024;
}
/*-----------------------------------------------------------------------
#endif /* CONFIG_ETHER_LOOPBACK_TEST */
#include "clkinit.h"
-#include "ioconfig.h" /* I/O configuration table */
+#include "ioconfig.h" /* I/O configuration table */
/*
* PBI Page Based Interleaving
/*
* ADC/DAC Defines:
*/
-#define INITIAL_SAMPLE_RATE 10016 /* Initial Daq sample rate */
-#define INITIAL_RIGHT_JUST 0 /* Initial DAC right justification */
-#define INITIAL_MCLK_DIVIDE 0 /* Initial MCLK Divide */
-#define INITIAL_SAMPLE_64X 1 /* Initial 64x clocking mode */
-#define INITIAL_SAMPLE_128X 0 /* Initial 128x clocking mode */
+#define INITIAL_SAMPLE_RATE 10016 /* Initial Daq sample rate */
+#define INITIAL_RIGHT_JUST 0 /* Initial DAC right justification */
+#define INITIAL_MCLK_DIVIDE 0 /* Initial MCLK Divide */
+#define INITIAL_SAMPLE_64X 1 /* Initial 64x clocking mode */
+#define INITIAL_SAMPLE_128X 0 /* Initial 128x clocking mode */
/*
* ADC Defines:
*/
-#define I2C_ADC_1_ADDR 0x0E /* I2C Address of the ADC #1 */
-#define I2C_ADC_2_ADDR 0x0F /* I2C Address of the ADC #2 */
+#define I2C_ADC_1_ADDR 0x0E /* I2C Address of the ADC #1 */
+#define I2C_ADC_2_ADDR 0x0F /* I2C Address of the ADC #2 */
-#define ADC_SDATA1_MASK 0x00020000 /* PA14 - CH12SDATA_PU */
-#define ADC_SDATA2_MASK 0x00010000 /* PA15 - CH34SDATA_PU */
+#define ADC_SDATA1_MASK 0x00020000 /* PA14 - CH12SDATA_PU */
+#define ADC_SDATA2_MASK 0x00010000 /* PA15 - CH34SDATA_PU */
-#define ADC_VREF_CAP 100 /* VREF capacitor in uF */
-#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */
-#define ADC_SDATA_DELAY 100 /* ADC SDATA release delay in usec */
+#define ADC_VREF_CAP 100 /* VREF capacitor in uF */
+#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */
+#define ADC_SDATA_DELAY 100 /* ADC SDATA release delay in usec */
#define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500)
- /* Wait at least 4100 LRCLK's */
-
-#define ADC_REG1_FRAME_START 0x80 /* Frame start */
-#define ADC_REG1_GROUND_CAL 0x40 /* Ground calibration enable */
-#define ADC_REG1_ANA_MOD_PDOWN 0x20 /* Analog modulator section in power down */
-#define ADC_REG1_DIG_MOD_PDOWN 0x10 /* Digital modulator section in power down */
-
-#define ADC_REG2_128x 0x80 /* Oversample at 128x */
-#define ADC_REG2_CAL 0x40 /* System calibration enable */
-#define ADC_REG2_CHANGE_SIGN 0x20 /* Change sign enable */
-#define ADC_REG2_LR_DISABLE 0x10 /* Left/Right output disable */
-#define ADC_REG2_HIGH_PASS_DIS 0x08 /* High pass filter disable */
-#define ADC_REG2_SLAVE_MODE 0x04 /* Slave mode */
-#define ADC_REG2_DFS 0x02 /* Digital format select */
-#define ADC_REG2_MUTE 0x01 /* Mute */
-
-#define ADC_REG7_ADDR_ENABLE 0x80 /* Address enable */
-#define ADC_REG7_PEAK_ENABLE 0x40 /* Peak enable */
-#define ADC_REG7_PEAK_UPDATE 0x20 /* Peak update */
-#define ADC_REG7_PEAK_FORMAT 0x10 /* Peak display format */
-#define ADC_REG7_DIG_FILT_PDOWN 0x04 /* Digital filter power down enable */
-#define ADC_REG7_FIR2_IN_EN 0x02 /* External FIR2 input enable */
-#define ADC_REG7_PSYCHO_EN 0x01 /* External pyscho filter input enable */
+ /* Wait at least 4100 LRCLK's */
+
+#define ADC_REG1_FRAME_START 0x80 /* Frame start */
+#define ADC_REG1_GROUND_CAL 0x40 /* Ground calibration enable */
+#define ADC_REG1_ANA_MOD_PDOWN 0x20 /* Analog modulator section in power down */
+#define ADC_REG1_DIG_MOD_PDOWN 0x10 /* Digital modulator section in power down */
+
+#define ADC_REG2_128x 0x80 /* Oversample at 128x */
+#define ADC_REG2_CAL 0x40 /* System calibration enable */
+#define ADC_REG2_CHANGE_SIGN 0x20 /* Change sign enable */
+#define ADC_REG2_LR_DISABLE 0x10 /* Left/Right output disable */
+#define ADC_REG2_HIGH_PASS_DIS 0x08 /* High pass filter disable */
+#define ADC_REG2_SLAVE_MODE 0x04 /* Slave mode */
+#define ADC_REG2_DFS 0x02 /* Digital format select */
+#define ADC_REG2_MUTE 0x01 /* Mute */
+
+#define ADC_REG7_ADDR_ENABLE 0x80 /* Address enable */
+#define ADC_REG7_PEAK_ENABLE 0x40 /* Peak enable */
+#define ADC_REG7_PEAK_UPDATE 0x20 /* Peak update */
+#define ADC_REG7_PEAK_FORMAT 0x10 /* Peak display format */
+#define ADC_REG7_DIG_FILT_PDOWN 0x04 /* Digital filter power down enable */
+#define ADC_REG7_FIR2_IN_EN 0x02 /* External FIR2 input enable */
+#define ADC_REG7_PSYCHO_EN 0x01 /* External pyscho filter input enable */
/*
* DAC Defines:
*/
-#define I2C_DAC_ADDR 0x11 /* I2C Address of the DAC */
+#define I2C_DAC_ADDR 0x11 /* I2C Address of the DAC */
-#define DAC_RST_MASK 0x00008000 /* PA16 - DAC_RST* */
-#define DAC_RESET_DELAY 100 /* DAC reset delay in usec */
-#define DAC_INITIAL_DELAY 5000 /* DAC initialization delay in usec */
+#define DAC_RST_MASK 0x00008000 /* PA16 - DAC_RST* */
+#define DAC_RESET_DELAY 100 /* DAC reset delay in usec */
+#define DAC_INITIAL_DELAY 5000 /* DAC initialization delay in usec */
-#define DAC_REG1_AMUTE 0x80 /* Auto-mute */
+#define DAC_REG1_AMUTE 0x80 /* Auto-mute */
-#define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit */
-#define DAC_REG1_I2S_24_BIT (1 << 4) /* Fmt 1: I2S up to 24 bit */
-#define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */
-#define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */
-#define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */
-#define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */
+#define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit */
+#define DAC_REG1_I2S_24_BIT (1 << 4) /* Fmt 1: I2S up to 24 bit */
+#define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */
+#define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */
+#define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */
+#define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */
-#define DAC_REG1_DEM_NO (0 << 2) /* No De-emphasis */
-#define DAC_REG1_DEM_44KHZ (1 << 2) /* 44.1KHz De-emphasis */
-#define DAC_REG1_DEM_48KHZ (2 << 2) /* 48KHz De-emphasis */
-#define DAC_REG1_DEM_32KHZ (3 << 2) /* 32KHz De-emphasis */
+#define DAC_REG1_DEM_NO (0 << 2) /* No De-emphasis */
+#define DAC_REG1_DEM_44KHZ (1 << 2) /* 44.1KHz De-emphasis */
+#define DAC_REG1_DEM_48KHZ (2 << 2) /* 48KHz De-emphasis */
+#define DAC_REG1_DEM_32KHZ (3 << 2) /* 32KHz De-emphasis */
-#define DAC_REG1_SINGLE 0 /* 4- 50KHz sample rate */
-#define DAC_REG1_DOUBLE 1 /* 50-100KHz sample rate */
-#define DAC_REG1_QUAD 2 /* 100-200KHz sample rate */
-#define DAC_REG1_DSD 3 /* Direct Stream Data, DSD */
+#define DAC_REG1_SINGLE 0 /* 4- 50KHz sample rate */
+#define DAC_REG1_DOUBLE 1 /* 50-100KHz sample rate */
+#define DAC_REG1_QUAD 2 /* 100-200KHz sample rate */
+#define DAC_REG1_DSD 3 /* Direct Stream Data, DSD */
-#define DAC_REG5_INVERT_A 0x80 /* Invert channel A */
-#define DAC_REG5_INVERT_B 0x40 /* Invert channel B */
-#define DAC_REG5_I2C_MODE 0x20 /* Control port (I2C) mode */
-#define DAC_REG5_POWER_DOWN 0x10 /* Power down mode */
-#define DAC_REG5_MUTEC_A_B 0x08 /* Mutec A=B */
-#define DAC_REG5_FREEZE 0x04 /* Freeze */
-#define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */
-#define DAC_REG5_RESERVED 0x01 /* Reserved */
-
-/* ------------------------------------------------------------------------- */
+#define DAC_REG5_INVERT_A 0x80 /* Invert channel A */
+#define DAC_REG5_INVERT_B 0x40 /* Invert channel B */
+#define DAC_REG5_I2C_MODE 0x20 /* Control port (I2C) mode */
+#define DAC_REG5_POWER_DOWN 0x10 /* Power down mode */
+#define DAC_REG5_MUTEC_A_B 0x08 /* Mutec A=B */
+#define DAC_REG5_FREEZE 0x04 /* Freeze */
+#define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */
+#define DAC_REG5_RESERVED 0x01 /* Reserved */
/*
* Check Board Identity:
int checkboard(void)
{
- printf ("SACSng\n");
+ printf("SACSng\n");
- return 0;
+ return 0;
}
-/* ------------------------------------------------------------------------- */
-
phys_size_t initdram(int board_type)
{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar c = 0;
- volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8);
- uint psdmr = CONFIG_SYS_PSDMR;
- int i;
- uint psrt = 14; /* for no SPD */
- uint chipselects = 1; /* for no SPD */
- uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */
- uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+ volatile uchar c = 0;
+ volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8);
+ uint psdmr = CONFIG_SYS_PSDMR;
+ int i;
+ uint psrt = 14; /* for no SPD */
+ uint chipselects = 1; /* for no SPD */
+ uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */
+ uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */
+
#ifdef SDRAM_SPD_ADDR
- uint data_width;
- uint rows;
- uint banks;
- uint cols;
- uint caslatency;
- uint width;
- uint rowst;
- uint sdam;
- uint bsma;
- uint sda10;
- u_char spd_size;
- u_char data;
- u_char cksum;
- int j;
+ uint data_width;
+ uint rows;
+ uint banks;
+ uint cols;
+ uint caslatency;
+ uint width;
+ uint rowst;
+ uint sdam;
+ uint bsma;
+ uint sda10;
+ u_char data;
+ u_char cksum;
+ int j;
#endif
#ifdef SDRAM_SPD_ADDR
- /* Keep the compiler from complaining about potentially uninitialized vars */
- data_width = chipselects = rows = banks = cols = caslatency = psrt = 0;
-
- /*
- * Read the SDRAM SPD EEPROM via I2C.
- */
- i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
- spd_size = data;
- cksum = data;
- for(j = 1; j < 64; j++) { /* read only the checksummed bytes */
- /* note: the I2C address autoincrements when alen == 0 */
- i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
- if(j == 5) chipselects = data & 0x0F;
- else if(j == 6) data_width = data;
- else if(j == 7) data_width |= data << 8;
- else if(j == 3) rows = data & 0x0F;
- else if(j == 4) cols = data & 0x0F;
- else if(j == 12) {
- /*
- * Refresh rate: this assumes the prescaler is set to
- * approximately 1uSec per tick.
- */
- switch(data & 0x7F) {
- default:
- case 0: psrt = 14 ; /* 15.625uS */ break;
- case 1: psrt = 2; /* 3.9uS */ break;
- case 2: psrt = 6; /* 7.8uS */ break;
- case 3: psrt = 29; /* 31.3uS */ break;
- case 4: psrt = 60; /* 62.5uS */ break;
- case 5: psrt = 120; /* 125uS */ break;
- }
- }
- else if(j == 17) banks = data;
- else if(j == 18) {
- caslatency = 3; /* default CL */
+ /* Keep the compiler from complaining about potentially uninitialized vars */
+ data_width = chipselects = rows = banks = cols = caslatency = psrt =
+ 0;
+
+ /*
+ * Read the SDRAM SPD EEPROM via I2C.
+ */
+ i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
+ cksum = data;
+ for (j = 1; j < 64; j++) { /* read only the checksummed bytes */
+ /* note: the I2C address autoincrements when alen == 0 */
+ i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
+ if (j == 5)
+ chipselects = data & 0x0F;
+ else if (j == 6)
+ data_width = data;
+ else if (j == 7)
+ data_width |= data << 8;
+ else if (j == 3)
+ rows = data & 0x0F;
+ else if (j == 4)
+ cols = data & 0x0F;
+ else if (j == 12) {
+ /*
+ * Refresh rate: this assumes the prescaler is set to
+ * approximately 1uSec per tick.
+ */
+ switch (data & 0x7F) {
+ default:
+ case 0:
+ psrt = 14; /* 15.625uS */
+ break;
+ case 1:
+ psrt = 2; /* 3.9uS */
+ break;
+ case 2:
+ psrt = 6; /* 7.8uS */
+ break;
+ case 3:
+ psrt = 29; /* 31.3uS */
+ break;
+ case 4:
+ psrt = 60; /* 62.5uS */
+ break;
+ case 5:
+ psrt = 120; /* 125uS */
+ break;
+ }
+ } else if (j == 17)
+ banks = data;
+ else if (j == 18) {
+ caslatency = 3; /* default CL */
#if(PESSIMISTIC_SDRAM)
- if((data & 0x04) != 0) caslatency = 3;
- else if((data & 0x02) != 0) caslatency = 2;
- else if((data & 0x01) != 0) caslatency = 1;
+ if ((data & 0x04) != 0)
+ caslatency = 3;
+ else if ((data & 0x02) != 0)
+ caslatency = 2;
+ else if ((data & 0x01) != 0)
+ caslatency = 1;
#else
- if((data & 0x01) != 0) caslatency = 1;
- else if((data & 0x02) != 0) caslatency = 2;
- else if((data & 0x04) != 0) caslatency = 3;
+ if ((data & 0x01) != 0)
+ caslatency = 1;
+ else if ((data & 0x02) != 0)
+ caslatency = 2;
+ else if ((data & 0x04) != 0)
+ caslatency = 3;
#endif
- else {
- printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
- data);
- }
+ else {
+ printf("WARNING: Unknown CAS latency 0x%02X, using 3\n", data);
+ }
+ } else if (j == 63) {
+ if (data != cksum) {
+ printf("WARNING: Configuration data checksum failure:" " is 0x%02x, calculated 0x%02x\n", data, cksum);
+ }
+ }
+ cksum += data;
}
- else if(j == 63) {
- if(data != cksum) {
- printf ("WARNING: Configuration data checksum failure:"
- " is 0x%02x, calculated 0x%02x\n",
- data, cksum);
- }
+
+ /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
+ if (caslatency < 2) {
+ printf("WARNING: CL was %d, forcing to 2\n", caslatency);
+ caslatency = 2;
+ }
+ if (rows > 14) {
+ printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n",
+ rows);
+ rows = 14;
+ }
+ if (cols > 11) {
+ printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n",
+ cols);
+ cols = 11;
+ }
+
+ if ((data_width != 64) && (data_width != 72)) {
+ printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
+ data_width);
}
- cksum += data;
- }
-
- /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
- if(caslatency < 2) {
- printf("WARNING: CL was %d, forcing to 2\n", caslatency);
- caslatency = 2;
- }
- if(rows > 14) {
- printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", rows);
- rows = 14;
- }
- if(cols > 11) {
- printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", cols);
- cols = 11;
- }
-
- if((data_width != 64) && (data_width != 72))
- {
- printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
- data_width);
- }
- width = 3; /* 2^3 = 8 bytes = 64 bits wide */
- /*
- * Convert banks into log2(banks)
- */
- if (banks == 2) banks = 1;
- else if(banks == 4) banks = 2;
- else if(banks == 8) banks = 3;
-
- sdram_size = 1 << (rows + cols + banks + width);
-
-#if(CONFIG_PBI == 0) /* bank-based interleaving */
- rowst = ((32 - 6) - (rows + cols + width)) * 2;
+ width = 3; /* 2^3 = 8 bytes = 64 bits wide */
+ /*
+ * Convert banks into log2(banks)
+ */
+ if (banks == 2)
+ banks = 1;
+ else if (banks == 4)
+ banks = 2;
+ else if (banks == 8)
+ banks = 3;
+
+ sdram_size = 1 << (rows + cols + banks + width);
+
+#if(CONFIG_PBI == 0) /* bank-based interleaving */
+ rowst = ((32 - 6) - (rows + cols + width)) * 2;
#else
- rowst = 32 - (rows + banks + cols + width);
+ rowst = 32 - (rows + banks + cols + width);
#endif
- or = ~(sdram_size - 1) | /* SDAM address mask */
- ((banks-1) << 13) | /* banks per device */
- (rowst << 9) | /* rowst */
- ((rows - 9) << 6); /* numr */
-
- memctl->memc_or2 = or;
-
- /*
- * SDAM specifies the number of columns that are multiplexed
- * (reference AN2165/D), defined to be (columns - 6) for page
- * interleave, (columns - 8) for bank interleave.
- *
- * BSMA is 14 - max(rows, cols). The bank select lines come
- * into play above the highest "address" line going into the
- * the SDRAM.
- */
-#if(CONFIG_PBI == 0) /* bank-based interleaving */
- sdam = cols - 8;
- bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
- sda10 = sdam + 2;
+ or = ~(sdram_size - 1) | /* SDAM address mask */
+ ((banks - 1) << 13) | /* banks per device */
+ (rowst << 9) | /* rowst */
+ ((rows - 9) << 6); /* numr */
+
+ memctl->memc_or2 = or;
+
+ /*
+ * SDAM specifies the number of columns that are multiplexed
+ * (reference AN2165/D), defined to be (columns - 6) for page
+ * interleave, (columns - 8) for bank interleave.
+ *
+ * BSMA is 14 - max(rows, cols). The bank select lines come
+ * into play above the highest "address" line going into the
+ * the SDRAM.
+ */
+#if(CONFIG_PBI == 0) /* bank-based interleaving */
+ sdam = cols - 8;
+ bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+ sda10 = sdam + 2;
#else
- sdam = cols - 6;
- bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
- sda10 = sdam;
+ sdam = cols - 6;
+ bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+ sda10 = sdam;
#endif
#if(PESSIMISTIC_SDRAM)
- psdmr = (CONFIG_PBI |\
- PSDMR_RFEN |\
- PSDMR_RFRC_16_CLK |\
- PSDMR_PRETOACT_8W |\
- PSDMR_ACTTORW_8W |\
- PSDMR_WRC_4C |\
- PSDMR_EAMUX |\
- PSDMR_BUFCMD) |\
- caslatency |\
- ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
- (sdam << 24) |\
- (bsma << 21) |\
- (sda10 << 18);
+ psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK |
+ PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C |
+ PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency |
+ ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */
+ (sdam << 24) | (bsma << 21) | (sda10 << 18);
#else
- psdmr = (CONFIG_PBI |\
- PSDMR_RFEN |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \
- PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
- PSDMR_WRC_1C | /* 1 clock + 7nSec */
- EAMUX |\
- BUFCMD) |\
- caslatency |\
- ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
- (sdam << 24) |\
- (bsma << 21) |\
- (sda10 << 18);
+ psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK |
+ PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */
+ PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */
+ PSDMR_WRC_1C | /* 1 clock + 7nSec */
+ EAMUX | BUFCMD) |
+ caslatency | ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */
+ (sdam << 24) | (bsma << 21) | (sda10 << 18);
#endif
#endif
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * Quote from Micron MT48LC8M16A2 data sheet:
- *
- * "...the SDRAM requires a 100uS delay prior to issuing any
- * command other than a COMMAND INHIBIT or NOP. Starting at some
- * point during this 100uS period and continuing at least through
- * the end of this period, COMMAND INHIBIT or NOP commands should
- * be applied."
- *
- * "Once the 100uS delay has been satisfied with at least one COMMAND
- * INHIBIT or NOP command having been applied, a /PRECHARGE command/
- * should be applied. All banks must then be precharged, thereby
- * placing the device in the all banks idle state."
- *
- * "Once in the idle state, /two/ AUTO REFRESH cycles must be
- * performed. After the AUTO REFRESH cycles are complete, the
- * SDRAM is ready for mode register programming."
- *
- * (/emphasis/ mine, gvb)
- *
- * The way I interpret this, Micron start up sequence is:
- * 1. Issue a PRECHARGE-BANK command (initial precharge)
- * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
- * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
- * 4. Issue a MODE-SET command to initialize the mode register
- *
- * --------
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
- */
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
- memctl->memc_psrt = psrt;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *ramaddr = c;
-
- /*
- * Do it a second time for the second set of chips if the DIMM has
- * two chip selects (double sided).
- */
- if(chipselects > 1) {
- ramaddr += sdram_size;
+ /*
+ * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+ *
+ * "At system reset, initialization software must set up the
+ * programmable parameters in the memory controller banks registers
+ * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+ * system software should execute the following initialization sequence
+ * for each SDRAM device.
+ *
+ * 1. Issue a PRECHARGE-ALL-BANKS command
+ * 2. Issue eight CBR REFRESH commands
+ * 3. Issue a MODE-SET command to initialize the mode register
+ *
+ * Quote from Micron MT48LC8M16A2 data sheet:
+ *
+ * "...the SDRAM requires a 100uS delay prior to issuing any
+ * command other than a COMMAND INHIBIT or NOP. Starting at some
+ * point during this 100uS period and continuing at least through
+ * the end of this period, COMMAND INHIBIT or NOP commands should
+ * be applied."
+ *
+ * "Once the 100uS delay has been satisfied with at least one COMMAND
+ * INHIBIT or NOP command having been applied, a /PRECHARGE command/
+ * should be applied. All banks must then be precharged, thereby
+ * placing the device in the all banks idle state."
+ *
+ * "Once in the idle state, /two/ AUTO REFRESH cycles must be
+ * performed. After the AUTO REFRESH cycles are complete, the
+ * SDRAM is ready for mode register programming."
+ *
+ * (/emphasis/ mine, gvb)
+ *
+ * The way I interpret this, Micron start up sequence is:
+ * 1. Issue a PRECHARGE-BANK command (initial precharge)
+ * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
+ * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
+ * 4. Issue a MODE-SET command to initialize the mode register
+ *
+ * --------
+ *
+ * The initial commands are executed by setting P/LSDMR[OP] and
+ * accessing the SDRAM with a single-byte transaction."
+ *
+ * The appropriate BRx/ORx registers have already been set when we
+ * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+ */
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
- memctl->memc_or3 = or;
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+ memctl->memc_psrt = psrt;
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
*ramaddr = c;
memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
for (i = 0; i < 8; i++)
- *ramaddr = c;
+ *ramaddr = c;
memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
*ramaddr = c;
memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*ramaddr = c;
- }
- /* return total ram size */
- return (sdram_size * chipselects);
+ /*
+ * Do it a second time for the second set of chips if the DIMM has
+ * two chip selects (double sided).
+ */
+ if (chipselects > 1) {
+ ramaddr += sdram_size;
+
+ memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
+ memctl->memc_or3 = or;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+ for (i = 0; i < 8; i++)
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+ *ramaddr = c;
+ }
+
+ /* return total ram size */
+ return (sdram_size * chipselects);
}
/*-----------------------------------------------------------------------
* Board Control Functions
*/
-void board_poweroff (void)
+void board_poweroff(void)
{
- while (1); /* hang forever */
+ while (1); /* hang forever */
}
/* ------------------------------------------------------------------------- */
int misc_init_r(void)
{
- /*
- * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
- */
- volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
- volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
-
- int reg; /* I2C register value */
- char *ep; /* Environment pointer */
- char str_buf[12] ; /* sprintf output buffer */
- int sample_rate; /* ADC/DAC sample rate */
- int sample_64x; /* Use 64/4 clocking for the ADC/DAC */
- int sample_128x; /* Use 128/4 clocking for the ADC/DAC */
- int right_just; /* Is the data to the DAC right justified? */
- int mclk_divide; /* MCLK Divide */
- int quiet; /* Quiet or minimal output mode */
-
- quiet = 0;
- if ((ep = getenv("quiet")) != NULL) {
- quiet = simple_strtol(ep, NULL, 10);
- }
- else {
- setenv("quiet", "0");
- }
-
- /*
- * SACSng custom initialization:
- * Start the ADC and DAC clocks, since the Crystal parts do not
- * work on the I2C bus until the clocks are running.
- */
-
- sample_rate = INITIAL_SAMPLE_RATE;
- if ((ep = getenv("DaqSampleRate")) != NULL) {
- sample_rate = simple_strtol(ep, NULL, 10);
- }
-
- sample_64x = INITIAL_SAMPLE_64X;
- sample_128x = INITIAL_SAMPLE_128X;
- if ((ep = getenv("Daq64xSampling")) != NULL) {
- sample_64x = simple_strtol(ep, NULL, 10);
+ /*
+ * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
+ */
+ volatile ioport_t *iopa =
+ ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */ );
+ volatile ioport_t *iop =
+ ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
+
+ int reg; /* I2C register value */
+ char *ep; /* Environment pointer */
+ char str_buf[12]; /* sprintf output buffer */
+ int sample_rate; /* ADC/DAC sample rate */
+ int sample_64x; /* Use 64/4 clocking for the ADC/DAC */
+ int sample_128x; /* Use 128/4 clocking for the ADC/DAC */
+ int right_just; /* Is the data to the DAC right justified? */
+ int mclk_divide; /* MCLK Divide */
+ int quiet; /* Quiet or minimal output mode */
+
+ quiet = 0;
+
+ if ((ep = getenv("quiet")) != NULL)
+ quiet = simple_strtol(ep, NULL, 10);
+ else
+ setenv("quiet", "0");
+
+ /*
+ * SACSng custom initialization:
+ * Start the ADC and DAC clocks, since the Crystal parts do not
+ * work on the I2C bus until the clocks are running.
+ */
+
+ sample_rate = INITIAL_SAMPLE_RATE;
+ if ((ep = getenv("DaqSampleRate")) != NULL)
+ sample_rate = simple_strtol(ep, NULL, 10);
+
+ sample_64x = INITIAL_SAMPLE_64X;
+ sample_128x = INITIAL_SAMPLE_128X;
+ if ((ep = getenv("Daq64xSampling")) != NULL) {
+ sample_64x = simple_strtol(ep, NULL, 10);
+ if (sample_64x)
+ sample_128x = 0;
+ else
+ sample_128x = 1;
+ } else {
+ if ((ep = getenv("Daq128xSampling")) != NULL) {
+ sample_128x = simple_strtol(ep, NULL, 10);
+ if (sample_128x)
+ sample_64x = 0;
+ else
+ sample_64x = 1;
+ }
+ }
+
+ /*
+ * Stop the clocks and wait for at least 1 LRCLK period
+ * to make sure the clocking has really stopped.
+ */
+ Daq_Stop_Clocks();
+ udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
+
+ /*
+ * Initialize the clocks with the new rates
+ */
+ Daq_Init_Clocks(sample_rate, sample_64x);
+ sample_rate = Daq_Get_SampleRate();
+
+ /*
+ * Start the clocks and wait for at least 1 LRCLK period
+ * to make sure the clocking has become stable.
+ */
+ Daq_Start_Clocks(sample_rate);
+ udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
+
+ sprintf(str_buf, "%d", sample_rate);
+ setenv("DaqSampleRate", str_buf);
+
if (sample_64x) {
- sample_128x = 0;
+ setenv("Daq64xSampling", "1");
+ setenv("Daq128xSampling", NULL);
+ } else {
+ setenv("Daq64xSampling", NULL);
+ setenv("Daq128xSampling", "1");
}
- else {
- sample_128x = 1;
+
+ /*
+ * Display the ADC/DAC clocking information
+ */
+ if (!quiet)
+ Daq_Display_Clocks();
+
+ /*
+ * Determine the DAC data justification
+ */
+
+ right_just = INITIAL_RIGHT_JUST;
+ if ((ep = getenv("DaqDACRightJustified")) != NULL)
+ right_just = simple_strtol(ep, NULL, 10);
+
+ sprintf(str_buf, "%d", right_just);
+ setenv("DaqDACRightJustified", str_buf);
+
+ /*
+ * Determine the DAC MCLK Divide
+ */
+
+ mclk_divide = INITIAL_MCLK_DIVIDE;
+ if ((ep = getenv("DaqDACMClockDivide")) != NULL)
+ mclk_divide = simple_strtol(ep, NULL, 10);
+
+ sprintf(str_buf, "%d", mclk_divide);
+ setenv("DaqDACMClockDivide", str_buf);
+
+ /*
+ * Initializing the I2C address in the Crystal A/Ds:
+ *
+ * 1) Wait for VREF cap to settle (10uSec per uF)
+ * 2) Release pullup on SDATA
+ * 3) Write the I2C address to register 6
+ * 4) Enable address matching by setting the MSB in register 7
+ */
+
+ if (!quiet)
+ printf("Initializing the ADC...\n");
+
+ udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */
+
+ iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */
+ udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
+
+ i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR); /* set address */
+ i2c_reg_write(I2C_ADC_1_ADDR, 0x07, /* turn on ADDREN */
+ ADC_REG7_ADDR_ENABLE);
+
+ i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */
+ (sample_64x ? 0 : ADC_REG2_128x) |
+ ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
+
+ reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F;
+ if (reg != I2C_ADC_1_ADDR) {
+ printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n",
+ reg, I2C_ADC_1_ADDR);
}
- }
- else {
- if ((ep = getenv("Daq128xSampling")) != NULL) {
- sample_128x = simple_strtol(ep, NULL, 10);
- if (sample_128x) {
- sample_64x = 0;
- }
- else {
- sample_64x = 1;
- }
+
+ iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */
+ udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
+
+ /* set address (do not set ADDREN yet) */
+ i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR);
+
+ i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */
+ (sample_64x ? 0 : ADC_REG2_128x) |
+ ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
+
+ reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F;
+ if (reg != I2C_ADC_2_ADDR) {
+ printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n",
+ reg, I2C_ADC_2_ADDR);
}
- }
-
- /*
- * Stop the clocks and wait for at least 1 LRCLK period
- * to make sure the clocking has really stopped.
- */
- Daq_Stop_Clocks();
- udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
-
- /*
- * Initialize the clocks with the new rates
- */
- Daq_Init_Clocks(sample_rate, sample_64x);
- sample_rate = Daq_Get_SampleRate();
-
- /*
- * Start the clocks and wait for at least 1 LRCLK period
- * to make sure the clocking has become stable.
- */
- Daq_Start_Clocks(sample_rate);
- udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
-
- sprintf(str_buf, "%d", sample_rate);
- setenv("DaqSampleRate", str_buf);
-
- if (sample_64x) {
- setenv("Daq64xSampling", "1");
- setenv("Daq128xSampling", NULL);
- }
- else {
- setenv("Daq64xSampling", NULL);
- setenv("Daq128xSampling", "1");
- }
-
- /*
- * Display the ADC/DAC clocking information
- */
- if (!quiet) {
- Daq_Display_Clocks();
- }
-
- /*
- * Determine the DAC data justification
- */
-
- right_just = INITIAL_RIGHT_JUST;
- if ((ep = getenv("DaqDACRightJustified")) != NULL) {
- right_just = simple_strtol(ep, NULL, 10);
- }
-
- sprintf(str_buf, "%d", right_just);
- setenv("DaqDACRightJustified", str_buf);
-
- /*
- * Determine the DAC MCLK Divide
- */
-
- mclk_divide = INITIAL_MCLK_DIVIDE;
- if ((ep = getenv("DaqDACMClockDivide")) != NULL) {
- mclk_divide = simple_strtol(ep, NULL, 10);
- }
-
- sprintf(str_buf, "%d", mclk_divide);
- setenv("DaqDACMClockDivide", str_buf);
-
- /*
- * Initializing the I2C address in the Crystal A/Ds:
- *
- * 1) Wait for VREF cap to settle (10uSec per uF)
- * 2) Release pullup on SDATA
- * 3) Write the I2C address to register 6
- * 4) Enable address matching by setting the MSB in register 7
- */
-
- if (!quiet) {
- printf("Initializing the ADC...\n");
- }
- udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */
-
- iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */
- udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
-
- i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR); /* set address */
- i2c_reg_write(I2C_ADC_1_ADDR, 0x07, /* turn on ADDREN */
- ADC_REG7_ADDR_ENABLE);
-
- i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */
- (sample_64x ? 0 : ADC_REG2_128x) |
- ADC_REG2_HIGH_PASS_DIS |
- ADC_REG2_SLAVE_MODE);
-
- reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F;
- if(reg != I2C_ADC_1_ADDR)
- printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n",
- reg, I2C_ADC_1_ADDR);
-
- iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */
- udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
-
- i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR); /* set address (do not set ADDREN yet) */
-
- i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */
- (sample_64x ? 0 : ADC_REG2_128x) |
- ADC_REG2_HIGH_PASS_DIS |
- ADC_REG2_SLAVE_MODE);
-
- reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F;
- if(reg != I2C_ADC_2_ADDR)
- printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n",
- reg, I2C_ADC_2_ADDR);
-
- i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */
- ADC_REG1_FRAME_START |
- ADC_REG1_GROUND_CAL);
-
- i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */
- (sample_64x ? 0 : ADC_REG2_128x) |
- ADC_REG2_CAL |
- ADC_REG2_HIGH_PASS_DIS |
- ADC_REG2_SLAVE_MODE);
-
- udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */
- i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */
-
- /*
- * Now that we have synchronized the ADC's, enable address
- * selection on the second ADC as well as the first.
- */
- i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE);
-
- /*
- * Initialize the Crystal DAC
- *
- * Two of the config lines are used for I2C so we have to set them
- * to the proper initialization state without inadvertantly
- * sending an I2C "start" sequence. When we bring the I2C back to
- * the normal state, we send an I2C "stop" sequence.
- */
- if (!quiet) {
- printf("Initializing the DAC...\n");
- }
-
- /*
- * Bring the I2C clock and data lines low for initialization
- */
- I2C_SCL(0);
- I2C_DELAY;
- I2C_SDA(0);
- I2C_ACTIVE;
- I2C_DELAY;
-
- /* Reset the DAC */
- iopa->pdat &= ~DAC_RST_MASK;
- udelay(DAC_RESET_DELAY);
-
- /* Release the DAC reset */
- iopa->pdat |= DAC_RST_MASK;
- udelay(DAC_INITIAL_DELAY);
-
- /*
- * Cause the DAC to:
- * Enable control port (I2C mode)
- * Going into power down
- */
- i2c_reg_write(I2C_DAC_ADDR, 0x05,
- DAC_REG5_I2C_MODE |
- DAC_REG5_POWER_DOWN);
-
- /*
- * Cause the DAC to:
- * Enable control port (I2C mode)
- * Going into power down
- * . MCLK divide by 1
- * . MCLK divide by 2
- */
- i2c_reg_write(I2C_DAC_ADDR, 0x05,
- DAC_REG5_I2C_MODE |
- DAC_REG5_POWER_DOWN |
- (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
-
- /*
- * Cause the DAC to:
- * Auto-mute disabled
- * . Format 0, left justified 24 bits
- * . Format 3, right justified 24 bits
- * No de-emphasis
- * . Single speed mode
- * . Double speed mode
- */
- i2c_reg_write(I2C_DAC_ADDR, 0x01,
- (right_just ? DAC_REG1_RIGHT_JUST_24BIT :
- DAC_REG1_LEFT_JUST_24_BIT) |
- DAC_REG1_DEM_NO |
- (sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
-
- sprintf(str_buf, "%d",
- sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE);
- setenv("DaqDACFunctionalMode", str_buf);
-
- /*
- * Cause the DAC to:
- * Enable control port (I2C mode)
- * Remove power down
- * . MCLK divide by 1
- * . MCLK divide by 2
- */
- i2c_reg_write(I2C_DAC_ADDR, 0x05,
- DAC_REG5_I2C_MODE |
- (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
-
- /*
- * Create a I2C stop condition:
- * low->high on data while clock is high.
- */
- I2C_SCL(1);
- I2C_DELAY;
- I2C_SDA(1);
- I2C_DELAY;
- I2C_TRISTATE;
-
- if (!quiet) {
- printf("\n");
- }
+ i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */
+ ADC_REG1_FRAME_START | ADC_REG1_GROUND_CAL);
+
+ i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */
+ (sample_64x ? 0 : ADC_REG2_128x) |
+ ADC_REG2_CAL |
+ ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
+
+ udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */
+ i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */
+
+ /*
+ * Now that we have synchronized the ADC's, enable address
+ * selection on the second ADC as well as the first.
+ */
+ i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE);
+
+ /*
+ * Initialize the Crystal DAC
+ *
+ * Two of the config lines are used for I2C so we have to set them
+ * to the proper initialization state without inadvertantly
+ * sending an I2C "start" sequence. When we bring the I2C back to
+ * the normal state, we send an I2C "stop" sequence.
+ */
+ if (!quiet)
+ printf("Initializing the DAC...\n");
+
+ /*
+ * Bring the I2C clock and data lines low for initialization
+ */
+ I2C_SCL(0);
+ I2C_DELAY;
+ I2C_SDA(0);
+ I2C_ACTIVE;
+ I2C_DELAY;
+
+ /* Reset the DAC */
+ iopa->pdat &= ~DAC_RST_MASK;
+ udelay(DAC_RESET_DELAY);
+
+ /* Release the DAC reset */
+ iopa->pdat |= DAC_RST_MASK;
+ udelay(DAC_INITIAL_DELAY);
+
+ /*
+ * Cause the DAC to:
+ * Enable control port (I2C mode)
+ * Going into power down
+ */
+ i2c_reg_write(I2C_DAC_ADDR, 0x05,
+ DAC_REG5_I2C_MODE | DAC_REG5_POWER_DOWN);
+
+ /*
+ * Cause the DAC to:
+ * Enable control port (I2C mode)
+ * Going into power down
+ * . MCLK divide by 1
+ * . MCLK divide by 2
+ */
+ i2c_reg_write(I2C_DAC_ADDR, 0x05,
+ DAC_REG5_I2C_MODE |
+ DAC_REG5_POWER_DOWN |
+ (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
+
+ /*
+ * Cause the DAC to:
+ * Auto-mute disabled
+ * . Format 0, left justified 24 bits
+ * . Format 3, right justified 24 bits
+ * No de-emphasis
+ * . Single speed mode
+ * . Double speed mode
+ */
+ i2c_reg_write(I2C_DAC_ADDR, 0x01,
+ (right_just ? DAC_REG1_RIGHT_JUST_24BIT :
+ DAC_REG1_LEFT_JUST_24_BIT) |
+ DAC_REG1_DEM_NO |
+ (sample_rate >=
+ 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
+
+ sprintf(str_buf, "%d",
+ sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE);
+ setenv("DaqDACFunctionalMode", str_buf);
+
+ /*
+ * Cause the DAC to:
+ * Enable control port (I2C mode)
+ * Remove power down
+ * . MCLK divide by 1
+ * . MCLK divide by 2
+ */
+ i2c_reg_write(I2C_DAC_ADDR, 0x05,
+ DAC_REG5_I2C_MODE |
+ (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
+
+ /*
+ * Create a I2C stop condition:
+ * low->high on data while clock is high.
+ */
+ I2C_SCL(1);
+ I2C_DELAY;
+ I2C_SDA(1);
+ I2C_DELAY;
+ I2C_TRISTATE;
+
+ if (!quiet)
+ printf("\n");
#ifdef CONFIG_ETHER_LOOPBACK_TEST
- /*
- * Run the Ethernet loopback test
- */
- eth_loopback_test ();
+ /*
+ * Run the Ethernet loopback test
+ */
+ eth_loopback_test();
#endif /* CONFIG_ETHER_LOOPBACK_TEST */
#ifdef CONFIG_SHOW_BOOT_PROGRESS
- /*
- * Turn off the RED fail LED now that we are up and running.
- */
- status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
+ /*
+ * Turn off the RED fail LED now that we are up and running.
+ */
+ status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
#endif
- return 0;
+ return 0;
}
#ifdef CONFIG_SHOW_BOOT_PROGRESS
*/
static void flash_code(uchar number, uchar modulo, uchar digits)
{
- int j;
-
- /*
- * Recursively do upper digits.
- */
- if(digits > 1) {
- flash_code(number / modulo, modulo, digits - 1);
- }
-
- number = number % modulo;
-
- /*
- * Zero is indicated by one long flash (dash).
- */
- if(number == 0) {
- status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
- udelay(1000000);
- status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
- udelay(200000);
- } else {
- /*
- * Non-zero is indicated by short flashes, one per count.
- */
- for(j = 0; j < number; j++) {
- status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
- udelay(100000);
- status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
- udelay(200000);
- }
- }
- /*
- * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total
- */
- udelay(700000);
-}
-
-static int last_boot_progress;
+ int j;
-void show_boot_progress (int status)
-{
- int i,j;
- if(status > 0) {
- last_boot_progress = status;
- } else {
/*
- * If a specific failure code is given, flash this code
- * else just use the last success code we've seen
+ * Recursively do upper digits.
*/
- if(status < -1)
- last_boot_progress = -status;
+ if (digits > 1)
+ flash_code(number / modulo, modulo, digits - 1);
+
+ number = number % modulo;
/*
- * Flash this code 5 times
+ * Zero is indicated by one long flash (dash).
*/
- for(j=0; j<5; j++) {
- /*
- * Houston, we have a problem.
- * Blink the last OK status which indicates where things failed.
- */
- status_led_set(STATUS_LED_RED, STATUS_LED_ON);
- flash_code(last_boot_progress, 5, 3);
-
- /*
- * Delay 5 seconds between repetitions,
- * with the fault LED blinking
- */
- for(i=0; i<5; i++) {
- status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
- udelay(500000);
- status_led_set(STATUS_LED_RED, STATUS_LED_ON);
- udelay(500000);
- }
+ if (number == 0) {
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+ udelay(1000000);
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+ udelay(200000);
+ } else {
+ /*
+ * Non-zero is indicated by short flashes, one per count.
+ */
+ for (j = 0; j < number; j++) {
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+ udelay(100000);
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+ udelay(200000);
+ }
}
-
/*
- * Reset the board to retry initialization.
+ * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total
*/
- do_reset (NULL, 0, 0, NULL);
- }
+ udelay(700000);
+}
+
+static int last_boot_progress;
+
+void show_boot_progress(int status)
+{
+ int i, j;
+
+ if (status > 0) {
+ last_boot_progress = status;
+ } else {
+ /*
+ * If a specific failure code is given, flash this code
+ * else just use the last success code we've seen
+ */
+ if (status < -1)
+ last_boot_progress = -status;
+
+ /*
+ * Flash this code 5 times
+ */
+ for (j = 0; j < 5; j++) {
+ /*
+ * Houston, we have a problem.
+ * Blink the last OK status which indicates where things failed.
+ */
+ status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+ flash_code(last_boot_progress, 5, 3);
+
+ /*
+ * Delay 5 seconds between repetitions,
+ * with the fault LED blinking
+ */
+ for (i = 0; i < 5; i++) {
+ status_led_set(STATUS_LED_RED,
+ STATUS_LED_OFF);
+ udelay(500000);
+ status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+ udelay(500000);
+ }
+ }
+
+ /*
+ * Reset the board to retry initialization.
+ */
+ do_reset(NULL, 0, 0, NULL);
+ }
}
#endif /* CONFIG_SHOW_BOOT_PROGRESS */
#define SPI_DAC_CS_MASK 0x00001000
static const u32 cs_mask[] = {
- SPI_ADC_CS_MASK,
- SPI_DAC_CS_MASK,
+ SPI_ADC_CS_MASK,
+ SPI_DAC_CS_MASK,
};
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
- return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]);
+ return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]);
}
void spi_cs_activate(struct spi_slave *slave)
{
- volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */);
+ volatile ioport_t *iopd =
+ ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ );
- iopd->pdat &= ~cs_mask[slave->cs];
+ iopd->pdat &= ~cs_mask[slave->cs];
}
void spi_cs_deactivate(struct spi_slave *slave)
{
- volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */);
+ volatile ioport_t *iopd =
+ ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ );
- iopd->pdat |= cs_mask[slave->cs];
+ iopd->pdat |= cs_mask[slave->cs];
}
#endif
ALL +=$(obj).depend $(LIB)
ifdef CONFIG_SPL_BUILD
-ALL += tools/mk$(BOARD)spl.exe
+ALL += $(OBJTREE)/tools/mk$(BOARD)spl
endif
all: $(ALL)
$(call cmd_link_o_target, $(OBJS))
ifdef CONFIG_SPL_BUILD
-tools/mk$(BOARD)spl.exe: tools/mkv310_image.c
- $(HOSTCC) tools/mkv310_image.c -o tools/mk$(BOARD)spl.exe
+$(OBJTREE)/tools/mk$(BOARD)spl: tools/mkv310_image.c
+ $(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl
endif
#########################################################################
SOBJS := mem_setup.o
SOBJS += lowlevel_init.o
+ifndef CONFIG_SPL_BUILD
COBJS += smdkv310.o
+endif
+
+ifdef CONFIG_SPL_BUILD
+COBJS += mmc_boot.o
+endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
-all: $(obj).depend $(LIB)
+ALL := $(obj).depend $(LIB)
+
+ifdef CONFIG_SPL_BUILD
+ALL += $(OBJTREE)/tools/mk$(BOARD)spl
+endif
+
+all: $(ALL)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+ifdef CONFIG_SPL_BUILD
+$(OBJTREE)/tools/mk$(BOARD)spl: tools/mkv310_image.c
+ $(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl
+endif
+
#########################################################################
# defines $(obj).depend target
#include<common.h>
#include<config.h>
-typedef u32(*copy_sd_mmc_to_mem) \
- (u32 start_block, u32 block_count, u32 *dest_addr);
-
-
+/*
+* Copy U-boot from mmc to RAM:
+* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
+* API (Data transfer from mmc to ram)
+*/
void copy_uboot_to_ram(void)
{
- copy_sd_mmc_to_mem copy_bl2 = (copy_sd_mmc_to_mem)(0x00002488);
- copy_bl2(BL2_START_OFFSET,\
- BL2_SIZE_BLOC_COUNT, (u32 *)CONFIG_SYS_TEXT_BASE);
+ u32 (*copy_bl2)(u32, u32, u32) = (void *)COPY_BL2_FNPTR_ADDR;
+
+ copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
}
void board_init_f(unsigned long bootflag)
smc9115_pre_init();
- gd->bd->bi_arch_number = MACH_TYPE_SMDKV310;
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \
+ PHYS_SDRAM_1_SIZE);
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \
+ PHYS_SDRAM_2_SIZE);
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \
+ PHYS_SDRAM_3_SIZE);
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+ gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \
+ PHYS_SDRAM_4_SIZE);
}
int board_eth_init(bd_t *bis)
#include <asm/arch/adc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
+#include <pmic.h>
DECLARE_GLOBAL_DATA_PTR;
check_hw_revision();
printf("HW Revision:\t0x%x\n", board_rev);
+#if defined(CONFIG_PMIC)
+ pmic_init();
+#endif
+
return 0;
}
#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
+#include <linux/compiler.h>
#include "scm.h"
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immr->im_memctl;
volatile can_reg_t *can = (volatile can_reg_t *) CONFIG_SYS_CAN0_BASE;
- volatile uint tmp, i;
+ __maybe_unused volatile uint tmp, i;
/* Initialize OR3 / BR3 for CAN Bus Controller 0 */
memctl->memc_or3 = CONFIG_SYS_CAN0_OR3;
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#endif
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
/*-----------------------------------------------------------------------
* Functions
*/
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-#if 0
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-#endif
-#ifdef CONFIG_BOOT_8B
-static int my_in_8( unsigned char *addr);
-static void my_out_8( unsigned char *addr, int val);
+static int write_word(flash_info_t *info, ulong dest, ulong data);
+
+#ifdef CONFIG_BOOT_8B
+static int my_in_8(unsigned char *addr);
+static void my_out_8(unsigned char *addr, int val);
#endif
-#ifdef CONFIG_BOOT_16B
-static int my_in_be16( unsigned short *addr);
-static void my_out_be16( unsigned short *addr, int val);
+#ifdef CONFIG_BOOT_16B
+static int my_in_be16(unsigned short *addr);
+static void my_out_be16(unsigned short *addr, int val);
#endif
-#ifdef CONFIG_BOOT_32B
-static unsigned my_in_be32( unsigned *addr);
-static void my_out_be32( unsigned *addr, int val);
+#ifdef CONFIG_BOOT_32B
+static unsigned my_in_be32(unsigned *addr);
+static void my_out_be32(unsigned *addr, int val);
#endif
/*-----------------------------------------------------------------------
*/
-unsigned long flash_init (void)
+unsigned long flash_init(void)
{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size_b0, size_b1;
int i;
- size_b0=0;
- size_b1=0;
+ size_b0 = 0;
+ size_b1 = 0;
/* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
flash_info[i].flash_id = FLASH_UNKNOWN;
- }
+
#ifdef CONFIG_SYS_DOC_BASE
#ifndef CONFIG_FEL8xx_AT
- memctl->memc_or5 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC ); /* 32k bytes */
+ /* 32k bytes */
+ memctl->memc_or5 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC);
memctl->memc_br5 = CONFIG_SYS_DOC_BASE | 0x401;
#else
- memctl->memc_or3 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC ); /* 32k bytes */
+ /* 32k bytes */
+ memctl->memc_or3 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC);
memctl->memc_br3 = CONFIG_SYS_DOC_BASE | 0x401;
#endif
#endif
-#if defined( CONFIG_BOOT_8B)
-/* memctl->memc_or0 = 0xfff80ff4; /###* 4MB bytes */
-/* memctl->memc_br0 = 0x40000401; */
- size_b0 = 0x80000; /* 512 K */
+#if defined(CONFIG_BOOT_8B)
+ size_b0 = 0x80000; /* 512 K */
+
flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM040;
flash_info[0].sector_count = 8;
flash_info[0].size = 0x00080000;
+
/* set up sector start address table */
for (i = 0; i < flash_info[0].sector_count; i++)
- flash_info[0].start[i] = 0x40000000 + (i * 0x10000);
+ flash_info[0].start[i] = 0x40000000 + (i * 0x10000);
+
/* protect all sectors */
for (i = 0; i < flash_info[0].sector_count; i++)
- flash_info[0].protect[i] = 0x1;
-#elif defined (CONFIG_BOOT_16B)
-/* memctl->memc_or0 = 0xfff80ff4; /###* 4MB bytes */
-/* memctl->memc_br0 = 0x40000401; */
- size_b0 = 0x400000; /* 4MB , assume AMD29LV320B */
+ flash_info[0].protect[i] = 0x1;
+
+#elif defined(CONFIG_BOOT_16B)
+ size_b0 = 0x400000; /* 4MB , assume AMD29LV320B */
+
flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM320B;
flash_info[0].sector_count = 67;
flash_info[0].size = 0x00400000;
+
/* set up sector start address table */
- flash_info[0].start[0] = 0x40000000 ;
+ flash_info[0].start[0] = 0x40000000;
flash_info[0].start[1] = 0x40000000 + 0x4000;
flash_info[0].start[2] = 0x40000000 + 0x6000;
flash_info[0].start[3] = 0x40000000 + 0x8000;
- for (i = 4; i < flash_info[0].sector_count; i++)
- flash_info[0].start[i] = 0x40000000 + 0x10000 + ((i-4) * 0x10000);
+
+ for (i = 4; i < flash_info[0].sector_count; i++) {
+ flash_info[0].start[i] =
+ 0x40000000 + 0x10000 + ((i - 4) * 0x10000);
+ }
+
/* protect all sectors */
for (i = 0; i < flash_info[0].sector_count; i++)
- flash_info[0].protect[i] = 0x1;
+ flash_info[0].protect[i] = 0x1;
#endif
-
#ifdef CONFIG_BOOT_32B
/* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+ size_b0 = flash_get_size((vu_long *) FLASH_BASE0_PRELIM,
+ &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
}
- size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+ size_b1 = flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
+ &flash_info[1]);
if (size_b1 > size_b0) {
- printf ("## ERROR: "
+ printf("## ERROR: "
"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
- size_b1, size_b1<<20,
- size_b0, size_b0<<20
- );
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[0].sector_count = -1;
- flash_info[1].sector_count = -1;
- flash_info[0].size = 0;
- flash_info[1].size = 0;
- return (0);
+ size_b1, size_b1 << 20, size_b0, size_b0 << 20);
+ flash_info[0].flash_id = FLASH_UNKNOWN;
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[0].sector_count = -1;
+ flash_info[1].sector_count = -1;
+ flash_info[0].size = 0;
+ flash_info[1].size = 0;
+
+ return 0;
}
/* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+ memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH |
+ (-size_b0 & OR_AM_MSK);
+ memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
+ BR_MS_GPCM | BR_V;
/* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+ size_b0 = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE,
+ &flash_info[0]);
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+ flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+ &flash_info[0]);
#endif
#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
- &flash_info[0]);
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
#endif
if (size_b1) {
- memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
- memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
- BR_MS_GPCM | BR_V;
+ memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH |
+ (-size_b1 & 0xFFFF8000);
+ memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE +
+ size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
/* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
- &flash_info[1]);
+ size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE +
+ size_b0), &flash_info[1]);
- flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
+ flash_get_offsets(CONFIG_SYS_FLASH_BASE + size_b0,
+ &flash_info[1]);
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[1]);
#endif
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
&flash_info[1]);
#endif
} else {
- memctl->memc_br1 = 0; /* invalidate bank */
+ memctl->memc_br1 = 0; /* invalidate bank */
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
flash_info[1].size = size_b1;
-#endif /* CONFIG_BOOT_32B */
+#endif /* CONFIG_BOOT_32B */
- return (size_b0 + size_b1);
+ return size_b0 + size_b1;
}
-#if 0
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-}
-#endif
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
+
+void flash_print_info(flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
+ printf("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
+ case FLASH_AM400B:
+ printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T:
+ printf("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T:
+ printf("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B:
+ printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T:
+ printf("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B:
+ printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
}
- printf (" Size: %ld MB in %d Sectors\n",
+ printf(" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
+ printf("\n ");
+ printf(" %08lX%s",
+ info->start[i], info->protect[i] ? " (RO)" : " ");
}
- printf ("\n");
+ printf("\n");
return;
}
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
/*
* The following code cannot be run from FLASH!
*/
-#if 0
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00900090;
- value = addr[0];
-
- switch (value) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- switch (value) {
- case AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile unsigned long *)info->start[0];
-
- *addr = 0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-#endif
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase(flash_info_t *info, int s_first, int s_last)
{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect,in_mid,in_did;
+ vu_long *addr = (vu_long *) (info->start[0]);
+ int flag, prot, sect, l_sect, in_mid, in_did;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
+ if (info->flash_id == FLASH_UNKNOWN)
+ printf("- missing\n");
+ else
+ printf("- no sectors to erase\n");
+
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
+ printf("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
return 1;
}
prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
prot++;
- }
}
if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
+ printf("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
- printf ("\n");
+ printf("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
-#if defined (CONFIG_BOOT_8B )
- my_out_8( (unsigned char * ) ((ulong)addr+0x555) , 0xaa );
- my_out_8( (unsigned char * ) ((ulong)addr+0x2aa) , 0x55 );
- my_out_8( (unsigned char * ) ((ulong)addr+0x555) , 0x90 );
- in_mid=my_in_8( (unsigned char * ) addr );
- in_did=my_in_8( (unsigned char * ) ((ulong)addr+1) );
- printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did );
- my_out_8( (unsigned char *)addr, 0xf0);
+
+#if defined(CONFIG_BOOT_8B)
+ my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa);
+ my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55);
+ my_out_8((unsigned char *)((ulong)addr + 0x555), 0x90);
+
+ in_mid = my_in_8((unsigned char *)addr);
+ in_did = my_in_8((unsigned char *)((ulong)addr + 1));
+
+ printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did);
+
+ my_out_8((unsigned char *)addr, 0xf0);
udelay(1);
- my_out_8( (unsigned char *) ((ulong)addr+0x555),0xaa );
- my_out_8( (unsigned char *) ((ulong)addr+0x2aa),0x55 );
- my_out_8( (unsigned char *) ((ulong)addr+0x555),0x80 );
- my_out_8( (unsigned char *) ((ulong)addr+0x555),0xaa );
- my_out_8( (unsigned char *) ((ulong)addr+0x2aa),0x55 );
+
+ my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa);
+ my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55);
+ my_out_8((unsigned char *)((ulong)addr + 0x555), 0x80);
+ my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa);
+ my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55);
+
/* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
+ for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long*)(info->start[sect]);
+ addr = (vu_long *) (info->start[sect]);
/*addr[0] = 0x00300030; */
- my_out_8( (unsigned char *) ((ulong)addr),0x30 );
+ my_out_8((unsigned char *)((ulong)addr), 0x30);
l_sect = sect;
}
}
-#elif defined(CONFIG_BOOT_16B )
- my_out_be16( (unsigned short * ) ((ulong)addr+ (0xaaa)) , 0xaa );
- my_out_be16( (unsigned short * ) ((ulong)addr+ (0x554)) , 0x55 );
- my_out_be16( (unsigned short * ) ((ulong)addr+ (0xaaa)) , 0x90 );
- in_mid=my_in_be16( (unsigned short * ) addr );
- in_did=my_in_be16 ( (unsigned short * ) ((ulong)addr+2) );
- printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did );
- my_out_be16( (unsigned short *)addr, 0xf0);
+#elif defined(CONFIG_BOOT_16B)
+ my_out_be16((unsigned short *)((ulong)addr + (0xaaa)), 0xaa);
+ my_out_be16((unsigned short *)((ulong)addr + (0x554)), 0x55);
+ my_out_be16((unsigned short *)((ulong)addr + (0xaaa)), 0x90);
+ in_mid = my_in_be16((unsigned short *)addr);
+ in_did = my_in_be16((unsigned short *)((ulong)addr + 2));
+ printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did);
+ my_out_be16((unsigned short *)addr, 0xf0);
udelay(1);
- my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xaa );
- my_out_be16( (unsigned short *) ((ulong)addr+0x554),0x55 );
- my_out_be16( (unsigned short *) ((ulong)addr+0xaaa),0x80 );
- my_out_be16( (unsigned short *) ((ulong)addr+0xaaa),0xaa );
- my_out_be16( (unsigned short *) ((ulong)addr+0x554),0x55 );
+ my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa);
+ my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55);
+ my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0x80);
+ my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa);
+ my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55);
/* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
+ for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long*)(info->start[sect]);
- my_out_be16( (unsigned short *) ((ulong)addr),0x30 );
+ addr = (vu_long *) (info->start[sect]);
+ my_out_be16((unsigned short *)((ulong)addr), 0x30);
l_sect = sect;
}
}
#elif defined(CONFIG_BOOT_32B)
- my_out_be32( (unsigned * ) ((ulong)addr+0x1554) , 0xaa );
- my_out_be32( (unsigned * ) ((ulong)addr+0xaa8) , 0x55 );
- my_out_be32( (unsigned *) ((ulong)addr+0x1554) , 0x90 );
- in_mid=my_in_be32( (unsigned * ) addr );
- in_did=my_in_be32( (unsigned * ) ((ulong)addr+4) );
- printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did );
- my_out_be32( (unsigned *)addr, 0xf0);
+ my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa);
+ my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55);
+ my_out_be32((unsigned *)((ulong)addr + 0x1554), 0x90);
+
+ in_mid = my_in_be32((unsigned *)addr);
+ in_did = my_in_be32((unsigned *)((ulong)addr + 4));
+
+ printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did);
+
+ my_out_be32((unsigned *) addr, 0xf0);
udelay(1);
- my_out_be32( (unsigned *) ((ulong)addr+0x1554),0xaa );
- my_out_be32( (unsigned *) ((ulong)addr+0xaa8),0x55 );
- my_out_be32( (unsigned *) ((ulong)addr+0x1554),0x80 );
- my_out_be32( (unsigned *) ((ulong)addr+0x1554),0xaa );
- my_out_be32( (unsigned *) ((ulong)addr+0xaa8),0x55 );
+
+ my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa);
+ my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55);
+ my_out_be32((unsigned *)((ulong)addr + 0x1554), 0x80);
+ my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa);
+ my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55);
+
/* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
+ for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long*)(info->start[sect]);
- my_out_be32( (unsigned *) ((ulong)addr),0x00300030 );
+ addr = (vu_long *) (info->start[sect]);
+ my_out_be32((unsigned *)((ulong)addr), 0x00300030);
l_sect = sect;
}
}
#else
-# error CONFIG_BOOT_(size)B missing.
+#error CONFIG_BOOT_(size)B missing.
#endif
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
- udelay (1000);
+ udelay(1000);
/*
* We wait for the last triggered sector
if (l_sect < 0)
goto DONE;
- start = get_timer (0);
- last = start;
- addr = (vu_long*)(info->start[l_sect]);
-#if defined (CONFIG_BOOT_8B)
- while ( (my_in_8((unsigned char *)addr) & 0x80) != 0x80 )
-#elif defined(CONFIG_BOOT_16B )
- while ( (my_in_be16((unsigned short *)addr) & 0x0080) != 0x0080 )
+ start = get_timer(0);
+ last = start;
+ addr = (vu_long *) (info->start[l_sect]);
+#if defined(CONFIG_BOOT_8B)
+ while ((my_in_8((unsigned char *) addr) & 0x80) != 0x80)
+#elif defined(CONFIG_BOOT_16B)
+ while ((my_in_be16((unsigned short *) addr) & 0x0080) != 0x0080)
#elif defined(CONFIG_BOOT_32B)
- while ( (my_in_be32((unsigned *)addr) & 0x00800080) != 0x00800080 )
+ while ((my_in_be32((unsigned *) addr) & 0x00800080) != 0x00800080)
#else
-# error CONFIG_BOOT_(size)B missing.
+#error CONFIG_BOOT_(size)B missing.
#endif
{
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
+ now = get_timer(start);
+ if (now > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
- putc ('.');
+ putc('.');
last = now;
}
}
DONE:
/* reset to read mode */
- addr = (volatile unsigned long *)info->start[0];
-#if defined (CONFIG_BOOT_8B)
- my_out_8( (unsigned char *)addr, 0xf0);
-#elif defined(CONFIG_BOOT_16B )
- my_out_be16( (unsigned short * ) addr , 0x00f0 );
+ addr = (volatile unsigned long *) info->start[0];
+
+#if defined(CONFIG_BOOT_8B)
+ my_out_8((unsigned char *) addr, 0xf0);
+#elif defined(CONFIG_BOOT_16B)
+ my_out_be16((unsigned short *) addr, 0x00f0);
#elif defined(CONFIG_BOOT_32B)
- my_out_be32 ( (unsigned *)addr, 0x00F000F0 ); /* reset bank */
+ my_out_be32((unsigned *) addr, 0x00F000F0); /* reset bank */
#else
-# error CONFIG_BOOT_(size)B missing.
+#error CONFIG_BOOT_(size)B missing.
#endif
- printf (" done\n");
+ printf(" done\n");
return 0;
}
-/*-----------------------------------------------------------------------
+/*
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
/*
* handle unaligned start bytes
*/
- if ((l = addr - wp) != 0) {
+ l = addr - wp;
+
+ if (l != 0) {
data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
+ for (i = 0, cp = wp; i < l; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ for (; i < 4 && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
+ for (; cnt == 0 && i < 4; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ rc = write_word(info, wp, data);
+
+ if (rc != 0)
+ return rc;
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
wp += 4;
}
*/
while (cnt >= 4) {
data = 0;
- for (i=0; i<4; ++i) {
+ for (i = 0; i < 4; ++i)
data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
+
+ rc = write_word(info, wp, data);
+
+ if (rc != 0)
+ return rc;
+
+ wp += 4;
cnt -= 4;
}
- if (cnt == 0) {
- return (0);
- }
+ if (cnt == 0)
+ return 0;
/*
* handle unaligned tail bytes
*/
data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
+ for (; i < 4; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
- return (write_word(info, wp, data));
+ return write_word(info, wp, data);
}
-/*-----------------------------------------------------------------------
+/*
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
-static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int write_word(flash_info_t *info, ulong dest, ulong data)
{
- ulong addr = (ulong)(info->start[0]);
- ulong start,last;
+ ulong addr = (ulong) (info->start[0]);
+ ulong start;
int flag;
ulong i;
- int data_short[2];
+ int data_short[2];
/* Check if Flash is (sufficiently) erased */
- if ( ((ulong) *(ulong *)dest & data) != data ) {
- return (2);
- }
+ if (((ulong)*(ulong *)dest & data) != data)
+ return 2;
+
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
#if defined(CONFIG_BOOT_8B)
#ifdef DEBUG
{
- int in_mid,in_did;
- my_out_8( (unsigned char * ) (addr+0x555) , 0xaa );
- my_out_8( (unsigned char * ) (addr+0x2aa) , 0x55 );
- my_out_8( (unsigned char * ) (addr+0x555) , 0x90 );
- in_mid=my_in_8( (unsigned char * ) addr );
- in_did=my_in_8( (unsigned char * ) (addr+1) );
- printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did );
- my_out_8( (unsigned char *)addr, 0xf0);
- udelay(1);
+ int in_mid, in_did;
+
+ my_out_8((unsigned char *) (addr + 0x555), 0xaa);
+ my_out_8((unsigned char *) (addr + 0x2aa), 0x55);
+ my_out_8((unsigned char *) (addr + 0x555), 0x90);
+
+ in_mid = my_in_8((unsigned char *) addr);
+ in_did = my_in_8((unsigned char *) (addr + 1));
+
+ printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did);
+
+ my_out_8((unsigned char *) addr, 0xf0);
+ udelay(1);
}
#endif
- {
- int data_ch[4];
- data_ch[0]=(int ) ((data>>24) & 0xff);
- data_ch[1]=(int ) ((data>>16) &0xff );
- data_ch[2]=(int ) ((data >>8) & 0xff);
- data_ch[3]=(int ) (data & 0xff);
- for (i=0;i<4;i++ ){
- my_out_8( (unsigned char *) (addr+0x555),0xaa);
- my_out_8((unsigned char *) (addr+0x2aa),0x55);
- my_out_8( (unsigned char *) (addr+0x555),0xa0);
- my_out_8((unsigned char *) (dest+i) ,data_ch[i]);
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
- last = start;
- while( ( my_in_8((unsigned char *) (dest+i)) ) != ( data_ch[i] ) ) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) {
- return 1;
- }
- }
- }/* for */
- }
-#elif defined( CONFIG_BOOT_16B)
- data_short[0]=(int) (data>>16) & 0xffff;
- data_short[1]=(int ) data & 0xffff ;
- for (i=0;i<2;i++ ){
- my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xaa );
- my_out_be16( (unsigned short *) ((ulong)addr+ 0x554),0x55 );
- my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xa0 );
- my_out_be16( (unsigned short *) (dest+(i*2)) ,data_short[i]);
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
- start = get_timer (0);
- last = start;
- while( ( my_in_be16((unsigned short *) (dest+(i*2))) ) != ( data_short[i] ) ) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) {
- return 1;
- }
- }
+ {
+ int data_ch[4];
+
+ data_ch[0] = (int) ((data >> 24) & 0xff);
+ data_ch[1] = (int) ((data >> 16) & 0xff);
+ data_ch[2] = (int) ((data >> 8) & 0xff);
+ data_ch[3] = (int) (data & 0xff);
+
+ for (i = 0; i < 4; i++) {
+ my_out_8((unsigned char *) (addr + 0x555), 0xaa);
+ my_out_8((unsigned char *) (addr + 0x2aa), 0x55);
+ my_out_8((unsigned char *) (addr + 0x555), 0xa0);
+ my_out_8((unsigned char *) (dest + i), data_ch[i]);
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer(0);
+ while ((my_in_8((unsigned char *)(dest + i))) !=
+ (data_ch[i])) {
+ if (get_timer(start) >
+ CONFIG_SYS_FLASH_WRITE_TOUT) {
+ return 1;
+ }
+ }
+ } /* for */
+ }
+#elif defined(CONFIG_BOOT_16B)
+ data_short[0] = (int) (data >> 16) & 0xffff;
+ data_short[1] = (int) data & 0xffff;
+ for (i = 0; i < 2; i++) {
+ my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa);
+ my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55);
+ my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xa0);
+ my_out_be16((unsigned short *)(dest + (i * 2)),
+ data_short[i]);
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer(0);
+ while ((my_in_be16((unsigned short *)(dest + (i * 2)))) !=
+ (data_short[i])) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+ return 1;
+ }
}
-#elif defined( CONFIG_BOOT_32B)
+#elif defined(CONFIG_BOOT_32B)
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
addr[0x0555] = 0x00A000A0;
enable_interrupts();
/* data polling for D7 */
- start = get_timer (0);
+ start = get_timer(0);
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+ return 1;
}
#endif
-
-
- return (0);
+ return 0;
}
-#ifdef CONFIG_BOOT_8B
-static int my_in_8 ( unsigned char *addr)
+
+#ifdef CONFIG_BOOT_8B
+static int my_in_8(unsigned char *addr)
{
- int ret;
- __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
- return ret;
+ int ret;
+ __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr));
+
+ return ret;
}
-static void my_out_8 ( unsigned char *addr, int val)
+static void my_out_8(unsigned char *addr, int val)
{
- __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+ __asm__ __volatile__("stb%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val));
}
#endif
-#ifdef CONFIG_BOOT_16B
-static int my_in_be16( unsigned short *addr)
+#ifdef CONFIG_BOOT_16B
+static int my_in_be16(unsigned short *addr)
{
- int ret;
- __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
- return ret;
+ int ret;
+ __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr));
+
+ return ret;
}
-static void my_out_be16( unsigned short *addr, int val)
+
+static void my_out_be16(unsigned short *addr, int val)
{
- __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+ __asm__ __volatile__("sth%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val));
}
#endif
-#ifdef CONFIG_BOOT_32B
-static unsigned my_in_be32( unsigned *addr)
+#ifdef CONFIG_BOOT_32B
+static unsigned my_in_be32(unsigned *addr)
{
unsigned ret;
- __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
- return ret;
+ __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr));
+
+ return ret;
}
-static void my_out_be32( unsigned *addr, int val)
+
+static void my_out_be32(unsigned *addr, int val)
{
- __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+ __asm__ __volatile__("stw%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val));
}
#endif
char buf[64];
int i;
int l = getenv_f("serial#", buf, sizeof(buf));
- int board_type;
if (l < 0 || strncmp(buf, "SVM8", 4)) {
printf("### No HW ID - assuming SVM SC8xx\n");
return (0);
}
- board_type = 1;
-
for (i = 0; i < l; ++i) {
if (buf[i] == ' ')
break;
putc('\n');
- return (0);
+ return 0;
}
/* ------------------------------------------------------------------------- */
writel(0x00000010, &ccnt->cmux_md);
gd->flags = 0;
- gd->bd->bi_arch_number = MACH_TYPE_JADECPU;
gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000;
icache_enable();
{
int rc = 0;
#ifdef CONFIG_SMC911X
+#define STR_ENV_ETHADDR "ethaddr"
+
+ struct eth_device *dev;
+ uchar eth_addr[6];
+
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+
+ if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
+ dev = eth_get_dev_by_index(0);
+ if (dev) {
+ eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
+ } else {
+ printf("omap3evm: Couldn't get eth device\n");
+ rc = -1;
+ }
+ }
#endif
return rc;
}
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN)
printf("\n");
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN)
printf("\n");
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30003000; /* sector erase */
- l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
static int spi_transmit(unsigned char data)
{
- int dummy;
struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
spi->dr = data;
/* wait for SPI transmission completed */
- while(!(spi->sr & 0x80))
- {
- if (spi->sr & 0x40) /* if write collision occured */
- {
+ while (!(spi->sr & 0x80)) {
+ if (spi->sr & 0x40) { /* if write collision occured */
+ int dummy;
+
/* do dummy read to clear status register */
dummy = spi->dr;
- printf ("SPI write collision\n");
+ printf("SPI write collision: dr=0x%x\n", dummy);
return -1;
}
}
psc->ccr = 0x1F03; /* 16 bit data width; 5.617MHz MCLK */
psc->ctur = 0x0F; /* 16 bit frame width */
- for(i=0;i<128;i++)
- {
+ for (i = 0; i < 128; i++)
psc->psc_buffer_32 = 0; /* clear tx fifo */
- }
}
static int i2s_play_wave(unsigned long addr, unsigned long len)
unsigned long i;
unsigned char *wave_file = (uchar *)addr + 44; /* quick'n dirty: skip
* wav header*/
- unsigned char swapped[4];
struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
/*
psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
for(i = 0;i < (len / 4); i++) {
+ unsigned char swapped[4];
+ unsigned long *p = (unsigned long*)swapped;
+
swapped[3] = *wave_file++;
swapped[2] = *wave_file++;
swapped[1] = *wave_file++;
swapped[0] = *wave_file++;
- psc->psc_buffer_32 = *((unsigned long*)swapped);
+
+ psc->psc_buffer_32 = *p;
+
while (psc->tfnum > 400) {
if(ctrlc())
return 0;
#ifndef CONFIG_SYS_RAMBOOT
long size8, size9;
#endif
- long psize, lsize;
+ long psize;
psize = 16 * 1024 * 1024;
- lsize = 0;
memctl->memc_psrt = CONFIG_SYS_PSRT;
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
#include <asm/arch/iomux.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
-#include <asm/errno.h>
#include <i2c.h>
#include <mmc.h>
#include <pmic.h>
DECLARE_GLOBAL_DATA_PTR;
-static u32 system_rev;
-
static struct fb_videomode nec_nl6448bc26_09c = {
"NEC_NL6448BC26-09C",
60, /* Refresh */
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
}
-u32 get_board_rev(void)
-{
- system_rev = get_cpu_rev();
-
- return system_rev;
-}
-
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
imx31_phycore arm arm1136 - - mx31
imx31_phycore_eet arm arm1136 imx31_phycore - mx31 imx31_phycore:IMX31_PHYCORE_EET
mx31pdk arm arm1136 - freescale mx31 mx31pdk:NAND_U_BOOT
+tt01 arm arm1136 - hale mx31
+flea3 arm arm1136 - CarMediaLab mx35
mx35pdk arm arm1136 - freescale mx35
omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
pm9g45 arm arm926ejs pm9g45 ronetix at91 pm9g45:AT91SAM9G45
da830evm arm arm926ejs da8xxevm davinci davinci
da850evm arm arm926ejs da8xxevm davinci davinci
+cam_enc_4xx arm arm926ejs cam_enc_4xx ait davinci cam_enc_4xx
hawkboard arm arm926ejs da8xxevm davinci davinci
hawkboard_nand arm arm926ejs da8xxevm davinci davinci hawkboard:NAND_U_BOOT
hawkboard_uart arm arm926ejs da8xxevm davinci davinci hawkboard:UART_U_BOOT
davinci_sffsdr arm arm926ejs sffsdr davinci davinci
davinci_sonata arm arm926ejs sonata davinci davinci
km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_DISABLE_PCI
-km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood
+km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_RECONFIG_XLX
mgcoge3un arm arm926ejs km_arm keymile kirkwood
portl2 arm arm926ejs km_arm keymile kirkwood
inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood netspace_v2:INETSPACE_V2
dig297 arm armv7 dig297 comelit omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
omap3_zoom2 arm armv7 zoom2 logicpd omap3
+omap3_mvblx arm armv7 mvblx matrix_vision omap3
omap3_beagle arm armv7 beagle ti omap3
omap3_evm arm armv7 evm ti omap3
+omap3_evm_quick_mmc arm armv7 evm ti omap3
+omap3_evm_quick_nand arm armv7 evm ti omap3
omap3_sdp3430 arm armv7 sdp3430 ti omap3
devkit8000 arm armv7 devkit8000 timll omap3
omap4_panda arm armv7 panda ti omap4
M5272C3 m68k mcf52x2 m5272c3 freescale
M5275EVB m68k mcf52x2 m5275evb freescale
M5282EVB m68k mcf52x2 m5282evb freescale
+M52277EVB m68k mcf5227x m52277evb freescale - M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000
+M52277EVB_stmicro m68k mcf5227x m52277evb freescale - M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000
+EB-MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS - EB+MCF-EV123:SYS_TEXT_BASE=0xFFE00000
+EB-MCF-EV123_internal m68k mcf52x2 EB+MCF-EV123 BuS - EB+MCF-EV123:SYS_TEXT_BASE=0xF0000000
+M5235EVB m68k mcf523x m5235evb freescale - M5235EVB:SYS_TEXT_BASE=0xFFE00000
+M5235EVB_Flash32 m68k mcf523x m5235evb freescale - M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000
+M54455EVB m68k mcf5445x m54455evb freescale - M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333
+M54455EVB_intel m68k mcf5445x m54455evb freescale - M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333
+M54455EVB_a66 m68k mcf5445x m54455evb freescale - M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666
+M54455EVB_i66 m68k mcf5445x m54455evb freescale - M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666
+M54455EVB_stm33 m68k mcf5445x m54455evb freescale - M54455EVB:SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333
+M54451EVB m68k mcf5445x m54451evb freescale - M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000
+M54451EVB_stmicro m68k mcf5445x m54451evb freescale - M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000
astro_mcf5373l m68k mcf532x mcf5373l astro
M53017EVB m68k mcf532x m53017evb freescale
M5329AFEE m68k mcf532x m5329evb freescale - M5329EVB:NANDFLASH_SIZE=0
int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#ifndef CONFIG_SYS_NO_FLASH
- flash_info_t *info;
+ flash_info_t *info = NULL;
ulong bank, addr_first, addr_last;
- int n, sect_first, sect_last;
+ int n, sect_first = 0, sect_last = 0;
#if defined(CONFIG_CMD_MTDPARTS)
struct mtd_device *dev;
struct part_info *part;
{
int rcode = 0;
#ifndef CONFIG_SYS_NO_FLASH
- flash_info_t *info;
+ flash_info_t *info = NULL;
ulong bank;
- int i, n, sect_first, sect_last;
+ int i, n, sect_first = 0, sect_last = 0;
#if defined(CONFIG_CMD_MTDPARTS)
struct mtd_device *dev;
struct part_info *part;
device = device->next;
}
} else {
- I2C_MUX_DEVICE *dev;
-
- dev = i2c_mux_ident_muxstring ((uchar *)argv[1]);
+ (void)i2c_mux_ident_muxstring ((uchar *)argv[1]);
ret = 0;
}
return ret;
# Option checker (courtesy linux kernel) to ensure
# only supported compiler options are used
#
-cc-option = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null \
- > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;)
+CC_OPTIONS_CACHE_FILE := $(OBJTREE)/include/generated/cc_options.mk
+
+$(if $(wildcard $(CC_OPTIONS_CACHE_FILE)),,\
+ $(shell mkdir -p $(dir $(CC_OPTIONS_CACHE_FILE))))
+
+-include $(CC_OPTIONS_CACHE_FILE)
+
+cc-option-sys = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null \
+ > /dev/null 2>&1; then \
+ echo 'CC_OPTIONS += $(strip $1)' >> $(CC_OPTIONS_CACHE_FILE); \
+ echo "$(1)"; fi)
+
+ifeq ($(CONFIG_CC_OPT_CACHE_DISABLE),y)
+cc-option = $(strip $(if $(call cc-option-sys,$1),$1,$2))
+else
+cc-option = $(strip $(if $(findstring $1,$(CC_OPTIONS)),$1,\
+ $(if $(call cc-option-sys,$1),$1,$2)))
+endif
#
# Include the make variables (CC, etc...)
CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o)
+CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
+CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o)
--- /dev/null
+With this approach, we don't need the UBL any more on DaVinci boards.
+A "make boardname" will compile a u-boot.ubl, with UBL Header, which is
+needed for the RBL to find the "UBL", which actually is a UBL-compatible
+header, nand spl code and u-boot code.
+
+
+As the RBL uses another read function as the "standard" u-boot,
+we need a command, which switches between this two read/write
+functions, so we can write the UBL header and the spl
+code in a format, which the RBL can read. This is realize
+(at the moment in board specific code) in the u-boot command
+nandrbl
+
+nandrbl without arguments returns actual mode (rbl or uboot).
+with nandrbl mode (mode = "rbl" or "uboot") you can switch
+between the two NAND read/write modes.
+
+
+To set up mkimage you need a config file for mkimage, example:
+board/ait/cam_enc_4xx/ublimage.cfg
+
+For information about the configuration please see:
+doc/README.ublimage
+
+Example for the cam_enc_4xx board:
+On the cam_enc_4xx board we have a NAND flash with blocksize = 0x20000 and
+pagesize = 0x800, so the u-boot.ubl image (which you get with:
+"make cam_enc_4xx") looks like this:
+
+00000000 00 ed ac a1 20 00 00 00 06 00 00 00 05 00 00 00 |.... ...........|
+00000010 00 00 00 00 20 00 00 00 ff ff ff ff ff ff ff ff |.... ...........|
+00000020 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
+*
+00000800 14 00 00 ea 14 f0 9f e5 10 f0 9f e5 0c f0 9f e5 |................|
+00000810 08 f0 9f e5 04 f0 9f e5 00 f0 9f e5 04 f0 1f e5 |................|
+00000820 00 01 00 00 78 56 34 12 78 56 34 12 78 56 34 12 |....xV4.xV4.xV4.|
+[...]
+*
+00001fe0 00 00 00 00 00 00 00 00 ff ff ff ff ff ff ff ff |................|
+00001ff0 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
+*
+00003800 14 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................|
+00003810 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................|
+00003820 80 01 08 81 e0 01 08 81 40 02 08 81 a0 02 08 81 |........@.......|
+
+In the first "page" of the image, we have the UBL Header, needed for
+the RBL to find the spl code.
+
+The spl code starts in the second "page" of the image, with a size
+defined by:
+
+#define CONFIG_SYS_NROF_PAGES_NAND_SPL 6
+
+After the spl code, there comes the "real" u-boot code
+@ (6 + 1) * pagesize = 0x3800
+
+------------------------------------------------------------------------
+Setting up spl code:
+
+/*
+ * RBL searches from Block n (n = 1..24)
+ * so we can define, how many UBL Headers
+ * we write before the real spl code
+ */
+#define CONFIG_SYS_NROF_UBL_HEADER 5
+#define CONFIG_SYS_NROF_PAGES_NAND_SPL 6
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS ((CONFIG_SYS_NROF_UBL_HEADER * \
+ CONFIG_SYS_NAND_BLOCK_SIZE) + \
+ (CONFIG_SYS_NROF_PAGES_NAND_SPL) * \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+------------------------------------------------------------------------
+
+Burning into NAND:
+
+step 1:
+The RBL searches from Block n ( n = 1..24) on page 0 for valid UBL
+Headers, so you have to burn the UBL header page from the u-boot.ubl
+image to the blocks, you want to have the UBL header.
+!! Don;t forget to switch to rbl nand read/write functions with
+ "nandrbl rbl"
+
+step 2:
+You need to setup in the ublimage.cfg, where the RBL can find the spl
+code, and how big it is.
+
+!! RBL always starts reading from page 0 !!
+
+For the AIT board, we have:
+PAGES 6
+START_BLOCK 5
+
+So we need to copy the spl code to block 5 page 0
+!! Don;t forget to switch to rbl nand read/write functions with
+ "nandrbl rbl"
+
+step 3:
+You need to copy the u-boot image to the block/page
+where the spl code reads it (CONFIG_SYS_NAND_U_BOOT_OFFS)
+!! Don;t forget to switch to rbl nand read/write functions with
+ "nandrbl uboot", which is default.
+
+On the cam_enc_4xx board it is:
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (0xc0000)
+
+-> this results in following NAND usage on the cam_enc_4xx board:
+
+addr
+
+20000 possible UBL Header
+40000 possible UBL Header
+60000 possible UBL Header
+80000 possilbe UBL Header
+a0000 spl code
+c0000 u-boot code
+
+The above steps are executeed through the following environment vars:
+(using 80000 as address for the UBL header)
+
+pagesz=800
+uboot=/tftpboot/cam_enc_4xx/u-boot.ubl
+load=tftp 80000000 ${uboot}
+writeheader nandrbl rbl;nand erase 80000 ${pagesz};nand write 80000000 80000 ${pagesz};nandrbl uboot
+writenand_spl nandrbl rbl;nand erase a0000 3000;nand write 80000800 a0000 3000;nandrbl uboot
+writeuboot nandrbl uboot;nand erase c0000 5d000;nand write 80003800 c0000 5d000
+update=run load writeheader writenand_spl writeuboot
+
+If you do a "run load update" u-boot, spl + ubl header
+are magically updated ;-)
+
+Note:
+- There seem to be a bug in the RBL code (at least on my HW),
+ In the UBL block, I can set the page to values != 0, so it
+ is possible to burn step 1 and step 2 in one step into the
+ flash, but the RBL ignores the page settings, so I have to
+ burn the UBL Header to a page 0 and the spl code to
+ a page 0 ... :-(
+- If we make the nand read/write functions in the RBL equal to
+ the functions in u-boot (as I have no RBL code, it is only
+ possible in u-boot), we could burn the complete image in
+ one step ... that would be nice ...
make cm_t35_config
make
+* BlueLYNX-X:
+
+make omap3_mvblx_config
+make
+
Custom commands
===============
return speed;
}
+unsigned int get_i2c_clock(int bus)
+{
+ if (bus)
+ return gd->i2c2_clk; /* I2C2 clock */
+ else
+ return gd->i2c1_clk; /* I2C1 clock */
+}
+
void
i2c_init(int speed, int slaveadd)
{
struct fsl_i2c *dev;
unsigned int temp;
+ int bus_num, i;
#ifdef CONFIG_SYS_I2C_INIT_BOARD
/* Call board specific i2c bus reset routine before accessing the
*/
i2c_init_board();
#endif
- dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
-
- writeb(0, &dev->cr); /* stop I2C controller */
- udelay(5); /* let it shutdown in peace */
- temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed);
- if (gd->flags & GD_FLG_RELOC)
- i2c_bus_speed[0] = temp;
- writeb(slaveadd << 1, &dev->adr); /* write slave address */
- writeb(0x0, &dev->sr); /* clear status register */
- writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
-
-#ifdef CONFIG_SYS_I2C2_OFFSET
- dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET);
-
- writeb(0, &dev->cr); /* stop I2C controller */
- udelay(5); /* let it shutdown in peace */
- temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed);
- if (gd->flags & GD_FLG_RELOC)
- i2c_bus_speed[1] = temp;
- writeb(slaveadd << 1, &dev->adr); /* write slave address */
- writeb(0x0, &dev->sr); /* clear status register */
- writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
+#ifdef CONFIG_SYS_I2C2_OFFSET
+ bus_num = 2;
+#else
+ bus_num = 1;
#endif
+ for (i = 0; i < bus_num; i++) {
+ dev = i2c_dev[i];
+
+ writeb(0, &dev->cr); /* stop I2C controller */
+ udelay(5); /* let it shutdown in peace */
+ temp = set_i2c_bus_speed(dev, get_i2c_clock(i), speed);
+ if (gd->flags & GD_FLG_RELOC)
+ i2c_bus_speed[i] = temp;
+ writeb(slaveadd << 1, &dev->adr);/* write slave address */
+ writeb(0x0, &dev->sr); /* clear status register */
+ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
+ }
#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
/* Call board specific i2c bus reset routine AFTER the bus has been
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <i2c.h>
struct mxc_i2c_regs {
uint32_t iadr;
#define I2C_BASE I2C2_BASE_ADDR
#elif defined(CONFIG_SYS_I2C_MX35_PORT1)
#define I2C_BASE I2C_BASE_ADDR
+#elif defined(CONFIG_SYS_I2C_MX35_PORT2)
+#define I2C_BASE I2C2_BASE_ADDR
+#elif defined(CONFIG_SYS_I2C_MX35_PORT3)
+#define I2C_BASE I2C3_BASE_ADDR
#else
#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
#endif
{ 3072, 0x1E }, { 3840, 0x1F }
};
-static u8 clk_div;
-
/*
* Calculate and set proper clock divider
*/
-static void i2c_imx_set_clk(unsigned int rate)
+static uint8_t i2c_imx_get_clk(unsigned int rate)
{
- struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
unsigned int i2c_clk_rate;
unsigned int div;
+ u8 clk_div;
#if defined(CONFIG_MX31)
struct clock_control_regs *sc_regs =
;
/* Store divider value */
- writeb(i2c_clk_div[clk_div][1], &i2c_regs->ifdr);
+ return clk_div;
}
/*
*/
void i2c_init(int speed, int unused)
{
- i2c_imx_set_clk(speed);
+ struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+ u8 clk_idx = i2c_imx_get_clk(speed);
+ u8 idx = i2c_clk_div[clk_idx][1];
+
+ /* Store divider value */
+ writeb(idx, &i2c_regs->ifdr);
+
i2c_reset();
}
*/
unsigned int i2c_get_bus_speed(void)
{
+ struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+ u8 clk_idx = readb(&i2c_regs->ifdr);
+ u8 clk_div;
+
+ for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
+ ;
+
return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0];
}
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
unsigned int temp = 0;
int result;
+ int speed = i2c_get_bus_speed();
+ u8 clk_idx = i2c_imx_get_clk(speed);
+ u8 idx = i2c_clk_div[clk_idx][1];
- writeb(i2c_clk_div[clk_div][1], &i2c_regs->ifdr);
+ /* Store divider value */
+ writeb(idx, &i2c_regs->ifdr);
/* Enable I2C controller */
writeb(0, &i2c_regs->i2sr);
int i2c_imx_set_reg_addr(uint addr, int alen)
{
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
- int ret;
- int i;
+ int ret = 0;
- for (i = 0; i < (8 * alen); i += 8) {
- writeb((addr >> i) & 0xff, &i2c_regs->i2dr);
+ while (alen--) {
+ writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->i2dr);
ret = i2c_imx_trx_complete();
if (ret)
#if defined(CONFIG_PMIC_SPI)
static u32 pmic_spi_prepare_tx(u32 reg, u32 *val, u32 write)
{
- if ((val == NULL) && (write))
- return *val & ~(1 << 31);
- else
- return (write << 31) | (reg << 25) | (*val & 0x00FFFFFF);
+ return (write << 31) | (reg << 25) | (*val & 0x00FFFFFF);
}
#endif
}
if (write) {
- pmic_tx = p->hw.spi.prepare_tx(0, NULL, write);
- pmic_tx &= ~(1 << 31);
+ pmic_tx = p->hw.spi.prepare_tx(reg, val, 0);
tmp = cpu_to_be32(pmic_tx);
if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx,
pmic_spi_flags)) {
ifdef CONFIG_SPL_NAND_SIMPLE
COBJS-y += nand_spl_simple.o
endif
+ifdef CONFIG_SPL_NAND_LOAD
+COBJS-y += nand_spl_load.o
+endif
else
COBJS-y += nand.o
COBJS-y += nand_bbt.o
--- /dev/null
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+
+/*
+ * The main entry for NAND booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from NAND into SDRAM and starts it from there.
+ */
+void nand_boot(void)
+{
+ int ret;
+ __attribute__((noreturn)) void (*uboot)(void);
+
+ /*
+ * Load U-Boot image from NAND into RAM
+ */
+ ret = nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+
+#ifdef CONFIG_NAND_ENV_DST
+ ret = nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (void *)CONFIG_NAND_ENV_DST);
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+ ret = nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+ (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+#endif
+#endif
+
+ /*
+ * Jump to U-Boot image
+ */
+ uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ (*uboot)();
+}
return 0;
}
+#if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
+static int nand_read_page(int block, int page, uchar *dst)
+{
+ struct nand_chip *this = mtd.priv;
+ u_char *ecc_calc;
+ u_char *ecc_code;
+ u_char *oob_data;
+ int i;
+ int eccsize = CONFIG_SYS_NAND_ECCSIZE;
+ int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
+ uint8_t *p = dst;
+ int stat;
+
+ /*
+ * No malloc available for now, just use some temporary locations
+ * in SDRAM
+ */
+ ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
+ ecc_code = ecc_calc + 0x100;
+ oob_data = ecc_calc + 0x200;
+
+ nand_command(block, page, 0, NAND_CMD_READOOB);
+ this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+ nand_command(block, page, 0, NAND_CMD_READ0);
+
+ /* Pick the ECC bytes out of the oob data */
+ for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
+ ecc_code[i] = oob_data[nand_ecc_pos[i]];
+
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ this->ecc.hwctl(&mtd, NAND_ECC_READ);
+ this->read_buf(&mtd, p, eccsize);
+ this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+ stat = this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+ }
+
+ return 0;
+}
+#else
static int nand_read_page(int block, int page, void *dst)
{
struct nand_chip *this = mtd.priv;
return 0;
}
+#endif
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
{
mtd.priv = &nand_chip;
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
(void __iomem *)CONFIG_SYS_NAND_BASE;
- nand_chip.options = 0;
board_nand_init(&nand_chip);
if (nand_chip.select_chip)
#define emac_gigabit_enable(phy_addr) /* no gigabit to enable */
#endif
+#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
+#define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \
+ EMAC_MDIO_CLOCK_FREQ) - 1)
+#endif
+
static void davinci_eth_mdio_enable(void);
static int gen_init_phy(int phy_addr);
{
u_int32_t clkdiv;
- clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
+ clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
writel((clkdiv & 0xff) |
MDIO_CONTROL_ENABLE |
#endif
/* Init MDIO & get link state */
- clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
+ clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
&adap_mdio->CONTROL);
phy[i].auto_negotiate = gen_auto_negotiate;
}
- debug("Ethernet PHY: %s\n", phy.name);
+ debug("Ethernet PHY: %s\n", phy[i].name);
miiphy_register(phy[i].name, davinci_mii_phy_read,
davinci_mii_phy_write);
#include <asm/types.h>
#include <asm/system.h>
#include <asm/byteorder.h>
+#include <asm/arch/cpu.h>
#if defined(CONFIG_KIRKWOOD)
#include <asm/arch/kirkwood.h>
#include <asm/io.h>
#include <pci.h>
-#if 0
#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
-#endif
-#if PCNET_DEBUG_LEVEL > 0
-#define PCNET_DEBUG1(fmt,args...) printf (fmt ,##args)
-#if PCNET_DEBUG_LEVEL > 1
-#define PCNET_DEBUG2(fmt,args...) printf (fmt ,##args)
-#else
-#define PCNET_DEBUG2(fmt,args...)
-#endif
-#else
-#define PCNET_DEBUG1(fmt,args...)
-#define PCNET_DEBUG2(fmt,args...)
-#endif
+#define PCNET_DEBUG1(fmt,args...) \
+ debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
+#define PCNET_DEBUG2(fmt,args...) \
+ debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
#error "Macro for PCnet chip version is not defined!"
#define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
-#undef DEBUG_TX
-#undef DEBUG_RX
+#define DEBUG_TX 0 /* set to 1 to enable debug code */
+#define DEBUG_RX 0 /* set to 1 to enable debug code */
-#define currticks() get_timer(0)
#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
{
int i;
- int speed10, fullduplex;
int addr_len;
unsigned short *ap = (unsigned short *)dev->enetaddr;
for (i = 0; i < 3; i++)
*ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));
- speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10;
- fullduplex = inw(ioaddr + MII_BMCR) & BMCRDuplex;
-
rtl_reset(dev);
if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
* from the configuration EEPROM default, because the card manufacturer
* should have set that to match the card. */
-#ifdef DEBUG_RX
- printf("rx ring address is %X\n",(unsigned long)rx_ring);
-#endif
+ debug_cond(DEBUG_RX,
+ "rx ring address is %lX\n",(unsigned long)rx_ring);
flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
memcpy((char *)tx_buffer, (char *)packet, (int)length);
-#ifdef DEBUG_TX
- printf("sending %d bytes\n", len);
-#endif
+ debug_cond(DEBUG_TX, "sending %d bytes\n", len);
/* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
* bytes are sent automatically for the FCS, totalling to 64 bytes). */
if (status & TxOK) {
cur_tx = (cur_tx + 1) % NUM_TX_DESC;
-#ifdef DEBUG_TX
- printf("tx done (%d ticks), status %hX txstatus %X\n",
- to-currticks(), status, txstatus);
-#endif
+
+ debug_cond(DEBUG_TX,
+ "tx done, status %hX txstatus %lX\n",
+ status, txstatus);
+
return length;
} else {
-#ifdef DEBUG_TX
- printf("tx timeout/error (%d usecs), status %hX txstatus %X\n",
- 10*i, status, txstatus);
-#endif
+
+ debug_cond(DEBUG_TX,
+ "tx timeout/error (%d usecs), status %hX txstatus %lX\n",
+ 10*i, status, txstatus);
+
rtl_reset(dev);
return 0;
/* See below for the rest of the interrupt acknowledges. */
outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
-#ifdef DEBUG_RX
- printf("rtl_poll: int %hX ", status);
-#endif
+ debug_cond(DEBUG_RX, "rtl_poll: int %hX ", status);
ring_offs = cur_rx % RX_BUF_LEN;
/* ring_offs is guaranteed being 4-byte aligned */
memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
NetReceive(rxdata, length);
-#ifdef DEBUG_RX
- printf("rx packet %d+%d bytes", semi_count,rx_size-4-semi_count);
-#endif
+ debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
+ semi_count, rx_size-4-semi_count);
} else {
NetReceive(rx_ring + ring_offs + 4, length);
-#ifdef DEBUG_RX
- printf("rx packet %d bytes", rx_size-4);
-#endif
+ debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size-4);
}
flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
static int rtl_init(struct eth_device *dev, bd_t *bis)
{
static int board_idx = -1;
- static int printed_version = 0;
int i, rc;
int option = -1, Cap10_100 = 0, Cap1000 = 0;
board_idx++;
- printed_version = 1;
-
/* point to private storage */
tpc = &tpx;
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
+#include <linux/compiler.h>
#undef CONFIG_PCMCIA
{
u_long reg, base;
pcmcia_win_t *win;
- u_int slotbit;
u_int rc, slot;
+ __maybe_unused u_int slotbit;
int i;
debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
COBJS-$(CONFIG_RTC_M41T94) += m41t94.o
COBJS-$(CONFIG_RTC_M48T35A) += m48t35ax.o
COBJS-$(CONFIG_RTC_MAX6900) += max6900.o
-COBJS-$(CONFIG_RTC_MC13783) += mc13783-rtc.o
+COBJS-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o
COBJS-$(CONFIG_RTC_MC146818) += mc146818.o
COBJS-$(CONFIG_MCFRTC) += mcfrtc.o
COBJS-$(CONFIG_RTC_MK48T59) += mk48t59.o
#if defined(CONFIG_CMD_DATE)
-/*---------------------------------------------------------------------*/
-#undef DEBUG_RTC
-
-#ifdef DEBUG_RTC
-#define DEBUGR(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGR(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
/*
* RTC register addresses
*/
mon_cent = rtc_read (RTC_MON_REG_ADDR);
year = rtc_read (RTC_YR_REG_ADDR);
- DEBUGR ("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
+ debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
year, mon_cent, mday, wday, hour, min, sec, control, status);
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
- DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
{
uchar century;
- DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#include <common.h>
#include <command.h>
#include <rtc.h>
+#include <asm/io.h>
#include "mvrtc.h"
/* This RTC does not support century, so we assume 20 */
tmp->tm_yday = 0;
tmp->tm_isdst = 0;
-#ifdef RTC_DEBUG
- printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ debug( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
-#endif
return 0;
}
{
int ret;
unsigned char buf[RTC_RV3029_PAGE_LEN];
-#ifdef RTC_DEBUG
- printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+
+ debug( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-#endif
if (tmp->tm_year < 2000) {
printf("RTC: year %d < 2000 not possible\n", tmp->tm_year);
/* give the RTC some time to update */
udelay(1000);
- return 0;
+ return ret;
}
/* sets EERE-Bit (automatic EEPROM refresh) */
static void set_eere_bit(int state)
{
- int ret;
unsigned char reg_ctrl1;
- ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL1, 1,
+ (void)i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL1, 1,
®_ctrl1, 1);
if (state)
else
reg_ctrl1 &= (~RTC_RV3029_CTRL1_EERE);
- ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL1, 1,
+ (void)i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL1, 1,
®_ctrl1, 1);
}
/* waits until EEPROM page is no longer busy (times out after 10ms*loops) */
static int wait_eebusy(int loops)
{
- int i, ret;
+ int i;
unsigned char ctrl_status;
for (i = 0; i < loops; i++) {
- ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL_STATUS,
+ (void)i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL_STATUS,
1, &ctrl_status, 1);
if ((ctrl_status & RTC_RV3029_CTRLS_EEBUSY) == 0)
void rtc_reset (void)
{
- int ret;
unsigned char buf[RTC_RV3029_PAGE_LEN];
buf[0] = RTC_RV3029_CTRL_SYS_R;
- ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL_RESET, 1,
+ (void)i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL_RESET, 1,
buf, 1);
#if defined(CONFIG_SYS_RV3029_TCR)
set_eere_bit(0);
wait_eebusy(100);
/* read current trickle charger setting */
- ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_EEPROM_CTRL,
+ (void)i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_EEPROM_CTRL,
1, buf, 1);
/* enable automatic EEPROM refresh again */
set_eere_bit(1);
*/
set_eere_bit(0);
wait_eebusy(100);
- ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR,
+ (void)i2c_write(CONFIG_SYS_I2C_RTC_ADDR,
RTC_RV3029_EEPROM_CTRL, 1, buf, 1);
/*
* it is necessary to wait 10ms before EEBUSY-Bit may be read
udelay(80);
- /* Take USB2 */
ehci = (struct usb_ehci *)(IMX_USB_BASE +
(0x200 * CONFIG_MXC_USB_PORT));
hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
#include "davinci.h"
#include <asm/arch/hardware.h>
+#if !defined(CONFIG_DV_USBPHY_CTL)
+#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN)
+#endif
+
/* MUSB platform configuration */
struct musb_config musb_cfg = {
.regs = (struct musb_regs *)MENTOR_USB0_BASE,
writel(USBPHY_PHY24MHZ | USBPHY_SESNDEN |
USBPHY_VBDTCTEN, USBPHY_CTL_PADDR);
#else
- writel(USBPHY_SESNDEN | USBPHY_VBDTCTEN, USBPHY_CTL_PADDR);
+ writel(CONFIG_DV_USBPHY_CTL, USBPHY_CTL_PADDR);
#endif
timeout = musb_cfg.timeout;
writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN, USBPHY_CTL_PADDR);
}
+void __enable_vbus(void)
+{
+ /*
+ * nothing to do, vbus is handled through the cpu.
+ * Define this function in board code, if it is
+ * different on your board.
+ */
+}
+void enable_vbus(void)
+ __attribute__((weak, alias("__enable_vbus")));
+
/*
* This function performs Davinci platform specific initialization for usb0.
*/
u32 revision;
/* enable USB VBUS */
-#ifndef DAVINCI_DM365EVM
enable_vbus();
-#endif
+
/* start the on-chip USB phy and its pll */
if (!phy_on())
return -1;
COBJS-$(CONFIG_SED156X) += sed156x.o
COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
+COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
#include <common.h>
#include <version.h>
#include <malloc.h>
+#include <linux/compiler.h>
/*
* Console device defines with SMI graphic
static void *video_logo(void)
{
char info[128];
- int space, len, y_off = 0;
+ int space, len;
+ __maybe_unused int y_off = 0;
#ifdef CONFIG_SPLASH_SCREEN
char *s;
--- /dev/null
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2008-2009 MontaVista Software Inc.
+ * Copyright (C) 2008-2009 Texas Instruments Inc
+ *
+ * Based on the LCD driver for TI Avalanche processors written by
+ * Ajay Singh and Shalom Hai.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <video_fb.h>
+#include <linux/list.h>
+#include <linux/fb.h>
+
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#include "videomodes.h"
+#include <asm/arch/da8xx-fb.h>
+
+#define DRIVER_NAME "da8xx_lcdc"
+
+/* LCD Status Register */
+#define LCD_END_OF_FRAME1 (1 << 9)
+#define LCD_END_OF_FRAME0 (1 << 8)
+#define LCD_PL_LOAD_DONE (1 << 6)
+#define LCD_FIFO_UNDERFLOW (1 << 5)
+#define LCD_SYNC_LOST (1 << 2)
+
+/* LCD DMA Control Register */
+#define LCD_DMA_BURST_SIZE(x) ((x) << 4)
+#define LCD_DMA_BURST_1 0x0
+#define LCD_DMA_BURST_2 0x1
+#define LCD_DMA_BURST_4 0x2
+#define LCD_DMA_BURST_8 0x3
+#define LCD_DMA_BURST_16 0x4
+#define LCD_END_OF_FRAME_INT_ENA (1 << 2)
+#define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
+
+/* LCD Control Register */
+#define LCD_CLK_DIVISOR(x) ((x) << 8)
+#define LCD_RASTER_MODE 0x01
+
+/* LCD Raster Control Register */
+#define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
+#define PALETTE_AND_DATA 0x00
+#define PALETTE_ONLY 0x01
+#define DATA_ONLY 0x02
+
+#define LCD_MONO_8BIT_MODE (1 << 9)
+#define LCD_RASTER_ORDER (1 << 8)
+#define LCD_TFT_MODE (1 << 7)
+#define LCD_UNDERFLOW_INT_ENA (1 << 6)
+#define LCD_PL_ENABLE (1 << 4)
+#define LCD_MONOCHROME_MODE (1 << 1)
+#define LCD_RASTER_ENABLE (1 << 0)
+#define LCD_TFT_ALT_ENABLE (1 << 23)
+#define LCD_STN_565_ENABLE (1 << 24)
+
+/* LCD Raster Timing 2 Register */
+#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
+#define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
+#define LCD_SYNC_CTRL (1 << 25)
+#define LCD_SYNC_EDGE (1 << 24)
+#define LCD_INVERT_PIXEL_CLOCK (1 << 22)
+#define LCD_INVERT_LINE_CLOCK (1 << 21)
+#define LCD_INVERT_FRAME_CLOCK (1 << 20)
+
+/* LCD Block */
+struct da8xx_lcd_regs {
+ u32 revid;
+ u32 ctrl;
+ u32 stat;
+ u32 lidd_ctrl;
+ u32 lidd_cs0_conf;
+ u32 lidd_cs0_addr;
+ u32 lidd_cs0_data;
+ u32 lidd_cs1_conf;
+ u32 lidd_cs1_addr;
+ u32 lidd_cs1_data;
+ u32 raster_ctrl;
+ u32 raster_timing_0;
+ u32 raster_timing_1;
+ u32 raster_timing_2;
+ u32 raster_subpanel;
+ u32 reserved;
+ u32 dma_ctrl;
+ u32 dma_frm_buf_base_addr_0;
+ u32 dma_frm_buf_ceiling_addr_0;
+ u32 dma_frm_buf_base_addr_1;
+ u32 dma_frm_buf_ceiling_addr_1;
+};
+
+#define LCD_NUM_BUFFERS 1
+
+#define WSI_TIMEOUT 50
+#define PALETTE_SIZE 256
+#define LEFT_MARGIN 64
+#define RIGHT_MARGIN 64
+#define UPPER_MARGIN 32
+#define LOWER_MARGIN 32
+
+#define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
+#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
+
+static struct da8xx_lcd_regs *da8xx_fb_reg_base;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* graphics setup */
+static GraphicDevice gpanel;
+static const struct da8xx_panel *lcd_panel;
+static struct fb_info *da8xx_fb_info;
+static int bits_x_pixel;
+
+static inline unsigned int lcdc_read(u32 *addr)
+{
+ return (unsigned int)readl(addr);
+}
+
+static inline void lcdc_write(unsigned int val, u32 *addr)
+{
+ writel(val, addr);
+}
+
+struct da8xx_fb_par {
+ u32 p_palette_base;
+ unsigned char *v_palette_base;
+ dma_addr_t vram_phys;
+ unsigned long vram_size;
+ void *vram_virt;
+ unsigned int dma_start;
+ unsigned int dma_end;
+ struct clk *lcdc_clk;
+ int irq;
+ unsigned short pseudo_palette[16];
+ unsigned int palette_sz;
+ unsigned int pxl_clk;
+ int blank;
+ int vsync_flag;
+ int vsync_timeout;
+};
+
+
+/* Variable Screen Information */
+static struct fb_var_screeninfo da8xx_fb_var = {
+ .xoffset = 0,
+ .yoffset = 0,
+ .transp = {0, 0, 0},
+ .nonstd = 0,
+ .activate = 0,
+ .height = -1,
+ .width = -1,
+ .pixclock = 46666, /* 46us - AUO display */
+ .accel_flags = 0,
+ .left_margin = LEFT_MARGIN,
+ .right_margin = RIGHT_MARGIN,
+ .upper_margin = UPPER_MARGIN,
+ .lower_margin = LOWER_MARGIN,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+static struct fb_fix_screeninfo da8xx_fb_fix = {
+ .id = "DA8xx FB Drv",
+ .type = FB_TYPE_PACKED_PIXELS,
+ .type_aux = 0,
+ .visual = FB_VISUAL_PSEUDOCOLOR,
+ .xpanstep = 0,
+ .ypanstep = 1,
+ .ywrapstep = 0,
+ .accel = FB_ACCEL_NONE
+};
+
+static const struct display_panel disp_panel = {
+ QVGA,
+ 16,
+ 16,
+ COLOR_ACTIVE,
+};
+
+static const struct lcd_ctrl_config lcd_cfg = {
+ &disp_panel,
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 16,
+ .fdd = 255,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+};
+
+/* Enable the Raster Engine of the LCD Controller */
+static inline void lcd_enable_raster(void)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+ if (!(reg & LCD_RASTER_ENABLE))
+ lcdc_write(reg | LCD_RASTER_ENABLE,
+ &da8xx_fb_reg_base->raster_ctrl);
+}
+
+/* Disable the Raster Engine of the LCD Controller */
+static inline void lcd_disable_raster(void)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+ if (reg & LCD_RASTER_ENABLE)
+ lcdc_write(reg & ~LCD_RASTER_ENABLE,
+ &da8xx_fb_reg_base->raster_ctrl);
+}
+
+static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
+{
+ u32 start;
+ u32 end;
+ u32 reg_ras;
+ u32 reg_dma;
+
+ /* init reg to clear PLM (loading mode) fields */
+ reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+ reg_ras &= ~(3 << 20);
+
+ reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
+
+ if (load_mode == LOAD_DATA) {
+ start = par->dma_start;
+ end = par->dma_end;
+
+ reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
+ reg_dma |= LCD_END_OF_FRAME_INT_ENA;
+
+#if (LCD_NUM_BUFFERS == 2)
+ reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
+ lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+ lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+#else
+ reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
+ lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+ lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+#endif
+
+ } else if (load_mode == LOAD_PALETTE) {
+ start = par->p_palette_base;
+ end = start + par->palette_sz - 1;
+
+ reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
+ reg_ras |= LCD_PL_ENABLE;
+
+ lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ }
+
+ lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
+ lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
+
+ /*
+ * The Raster enable bit must be set after all other control fields are
+ * set.
+ */
+ lcd_enable_raster();
+}
+
+/* Configure the Burst Size of DMA */
+static int lcd_cfg_dma(int burst_size)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
+ switch (burst_size) {
+ case 1:
+ reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
+ break;
+ case 2:
+ reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
+ break;
+ case 4:
+ reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
+ break;
+ case 8:
+ reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
+ break;
+ case 16:
+ reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
+ break;
+ default:
+ return -EINVAL;
+ }
+ lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
+
+ return 0;
+}
+
+static void lcd_cfg_ac_bias(int period, int transitions_per_int)
+{
+ u32 reg;
+
+ /* Set the AC Bias Period and Number of Transisitons per Interrupt */
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
+ reg |= LCD_AC_BIAS_FREQUENCY(period) |
+ LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
+}
+
+static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
+ int front_porch)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
+ reg |= ((back_porch & 0xff) << 24)
+ | ((front_porch & 0xff) << 16)
+ | ((pulse_width & 0x3f) << 10);
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
+}
+
+static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
+ int front_porch)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
+ reg |= ((back_porch & 0xff) << 24)
+ | ((front_porch & 0xff) << 16)
+ | ((pulse_width & 0x3f) << 10);
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
+}
+
+static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
+{
+ u32 reg;
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
+ LCD_MONO_8BIT_MODE |
+ LCD_MONOCHROME_MODE);
+
+ switch (cfg->p_disp_panel->panel_shade) {
+ case MONOCHROME:
+ reg |= LCD_MONOCHROME_MODE;
+ if (cfg->mono_8bit_mode)
+ reg |= LCD_MONO_8BIT_MODE;
+ break;
+ case COLOR_ACTIVE:
+ reg |= LCD_TFT_MODE;
+ if (cfg->tft_alt_mode)
+ reg |= LCD_TFT_ALT_ENABLE;
+ break;
+
+ case COLOR_PASSIVE:
+ if (cfg->stn_565_mode)
+ reg |= LCD_STN_565_ENABLE;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ /* enable additional interrupts here */
+ reg |= LCD_UNDERFLOW_INT_ENA;
+
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
+
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
+
+ if (cfg->sync_ctrl)
+ reg |= LCD_SYNC_CTRL;
+ else
+ reg &= ~LCD_SYNC_CTRL;
+
+ if (cfg->sync_edge)
+ reg |= LCD_SYNC_EDGE;
+ else
+ reg &= ~LCD_SYNC_EDGE;
+
+ if (cfg->invert_line_clock)
+ reg |= LCD_INVERT_LINE_CLOCK;
+ else
+ reg &= ~LCD_INVERT_LINE_CLOCK;
+
+ if (cfg->invert_frm_clock)
+ reg |= LCD_INVERT_FRAME_CLOCK;
+ else
+ reg &= ~LCD_INVERT_FRAME_CLOCK;
+
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
+
+ return 0;
+}
+
+static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
+ u32 bpp, u32 raster_order)
+{
+ u32 reg;
+
+ /* Set the Panel Width */
+ /* Pixels per line = (PPL + 1)*16 */
+ /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
+ width &= 0x3f0;
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
+ reg &= 0xfffffc00;
+ reg |= ((width >> 4) - 1) << 4;
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
+
+ /* Set the Panel Height */
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
+ reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
+
+ /* Set the Raster Order of the Frame Buffer */
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
+ if (raster_order)
+ reg |= LCD_RASTER_ORDER;
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
+
+ switch (bpp) {
+ case 1:
+ case 2:
+ case 4:
+ case 16:
+ par->palette_sz = 16 * 2;
+ break;
+
+ case 8:
+ par->palette_sz = 256 * 2;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
+ unsigned blue, unsigned transp,
+ struct fb_info *info)
+{
+ struct da8xx_fb_par *par = info->par;
+ unsigned short *palette = (unsigned short *) par->v_palette_base;
+ u_short pal;
+ int update_hw = 0;
+
+ if (regno > 255)
+ return 1;
+
+ if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
+ return 1;
+
+ if (info->var.bits_per_pixel == 8) {
+ red >>= 4;
+ green >>= 8;
+ blue >>= 12;
+
+ pal = (red & 0x0f00);
+ pal |= (green & 0x00f0);
+ pal |= (blue & 0x000f);
+
+ if (palette[regno] != pal) {
+ update_hw = 1;
+ palette[regno] = pal;
+ }
+ } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
+ red >>= (16 - info->var.red.length);
+ red <<= info->var.red.offset;
+
+ green >>= (16 - info->var.green.length);
+ green <<= info->var.green.offset;
+
+ blue >>= (16 - info->var.blue.length);
+ blue <<= info->var.blue.offset;
+
+ par->pseudo_palette[regno] = red | green | blue;
+
+ if (palette[0] != 0x4000) {
+ update_hw = 1;
+ palette[0] = 0x4000;
+ }
+ }
+
+ /* Update the palette in the h/w as needed. */
+ if (update_hw)
+ lcd_blit(LOAD_PALETTE, par);
+
+ return 0;
+}
+
+static void lcd_reset(struct da8xx_fb_par *par)
+{
+ /* Disable the Raster if previously Enabled */
+ lcd_disable_raster();
+
+ /* DMA has to be disabled */
+ lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
+ lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
+}
+
+static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
+{
+ unsigned int lcd_clk, div;
+
+ /* Get clock from sysclk2 */
+ lcd_clk = clk_get(2);
+
+ div = lcd_clk / par->pxl_clk;
+ debug("LCD Clock: 0x%x Divider: 0x%x PixClk: 0x%x\n",
+ lcd_clk, div, par->pxl_clk);
+
+ /* Configure the LCD clock divisor. */
+ lcdc_write(LCD_CLK_DIVISOR(div) |
+ (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
+}
+
+static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
+ const struct da8xx_panel *panel)
+{
+ u32 bpp;
+ int ret = 0;
+
+ lcd_reset(par);
+
+ /* Calculate the divider */
+ lcd_calc_clk_divider(par);
+
+ if (panel->invert_pxl_clk)
+ lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
+ LCD_INVERT_PIXEL_CLOCK),
+ &da8xx_fb_reg_base->raster_timing_2);
+ else
+ lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
+ ~LCD_INVERT_PIXEL_CLOCK),
+ &da8xx_fb_reg_base->raster_timing_2);
+
+ /* Configure the DMA burst size. */
+ ret = lcd_cfg_dma(cfg->dma_burst_sz);
+ if (ret < 0)
+ return ret;
+
+ /* Configure the AC bias properties. */
+ lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
+
+ /* Configure the vertical and horizontal sync properties. */
+ lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
+ lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
+
+ /* Configure for disply */
+ ret = lcd_cfg_display(cfg);
+ if (ret < 0)
+ return ret;
+
+ if (QVGA != cfg->p_disp_panel->panel_type)
+ return -EINVAL;
+
+ if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
+ cfg->bpp >= cfg->p_disp_panel->min_bpp)
+ bpp = cfg->bpp;
+ else
+ bpp = cfg->p_disp_panel->max_bpp;
+ if (bpp == 12)
+ bpp = 16;
+ ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
+ (unsigned int)panel->height, bpp,
+ cfg->raster_order);
+ if (ret < 0)
+ return ret;
+
+ /* Configure FDD */
+ lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
+ (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
+
+ return 0;
+}
+
+static void lcdc_dma_start(void)
+{
+ struct da8xx_fb_par *par = da8xx_fb_info->par;
+ lcdc_write(par->dma_start,
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(par->dma_end,
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ lcdc_write(0,
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+ lcdc_write(0,
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+}
+
+static u32 lcdc_irq_handler(void)
+{
+ struct da8xx_fb_par *par = da8xx_fb_info->par;
+ u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
+ u32 reg_ras;
+
+ if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
+ debug("LCD_SYNC_LOST\n");
+ lcd_disable_raster();
+ lcdc_write(stat, &da8xx_fb_reg_base->stat);
+ lcd_enable_raster();
+ return LCD_SYNC_LOST;
+ } else if (stat & LCD_PL_LOAD_DONE) {
+ debug("LCD_PL_LOAD_DONE\n");
+ /*
+ * Must disable raster before changing state of any control bit.
+ * And also must be disabled before clearing the PL loading
+ * interrupt via the following write to the status register. If
+ * this is done after then one gets multiple PL done interrupts.
+ */
+ lcd_disable_raster();
+
+ lcdc_write(stat, &da8xx_fb_reg_base->stat);
+
+ /* Disable PL completion inerrupt */
+ reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+ reg_ras &= ~LCD_PL_ENABLE;
+ lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
+
+ /* Setup and start data loading mode */
+ lcd_blit(LOAD_DATA, par);
+ return LCD_PL_LOAD_DONE;
+ } else {
+ lcdc_write(stat, &da8xx_fb_reg_base->stat);
+
+ if (stat & LCD_END_OF_FRAME0)
+ debug("LCD_END_OF_FRAME0\n");
+
+ lcdc_write(par->dma_start,
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(par->dma_end,
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ par->vsync_flag = 1;
+ return LCD_END_OF_FRAME0;
+ }
+ return stat;
+}
+
+static u32 wait_for_event(u32 event)
+{
+ u32 timeout = 50000;
+ u32 ret;
+
+ do {
+ ret = lcdc_irq_handler();
+ udelay(1000);
+ } while (!(ret & event));
+
+ if (timeout <= 0) {
+ printf("%s: event %d not hit\n", __func__, event);
+ return -1;
+ }
+
+ return 0;
+
+}
+
+void *video_hw_init(void)
+{
+ struct da8xx_fb_par *par;
+ int ret;
+ u32 size;
+ char *p;
+
+ if (!lcd_panel) {
+ printf("Display not initialized\n");
+ return NULL;
+ }
+ gpanel.winSizeX = lcd_panel->width;
+ gpanel.winSizeY = lcd_panel->height;
+ gpanel.plnSizeX = lcd_panel->width;
+ gpanel.plnSizeY = lcd_panel->height;
+
+ switch (bits_x_pixel) {
+ case 24:
+ gpanel.gdfBytesPP = 4;
+ gpanel.gdfIndex = GDF_32BIT_X888RGB;
+ break;
+ case 16:
+ gpanel.gdfBytesPP = 2;
+ gpanel.gdfIndex = GDF_16BIT_565RGB;
+ break;
+ default:
+ gpanel.gdfBytesPP = 1;
+ gpanel.gdfIndex = GDF__8BIT_INDEX;
+ break;
+ }
+
+ da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE;
+
+ debug("Resolution: %dx%d %x\n",
+ gpanel.winSizeX,
+ gpanel.winSizeY,
+ lcd_cfg.bpp);
+
+ size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
+ da8xx_fb_info = malloc(size);
+ debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
+
+ if (!da8xx_fb_info) {
+ printf("Memory allocation failed for fb_info\n");
+ return NULL;
+ }
+ memset(da8xx_fb_info, 0, size);
+ p = (char *)da8xx_fb_info;
+ da8xx_fb_info->par = p + sizeof(struct fb_info);
+ debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
+
+ par = da8xx_fb_info->par;
+ par->pxl_clk = lcd_panel->pxl_clk;
+
+ if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) {
+ printf("lcd_init failed\n");
+ ret = -EFAULT;
+ goto err_release_fb;
+ }
+
+ /* allocate frame buffer */
+ par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp;
+ par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
+
+ par->vram_virt = malloc(par->vram_size);
+
+ par->vram_phys = (dma_addr_t) par->vram_virt;
+ debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
+ (unsigned int)par->vram_size,
+ (unsigned int)par->vram_virt);
+ if (!par->vram_virt) {
+ printf("GLCD: malloc for frame buffer failed\n");
+ ret = -EINVAL;
+ goto err_release_fb;
+ }
+
+ gpanel.frameAdrs = (unsigned int)par->vram_virt;
+ da8xx_fb_info->screen_base = (char *) par->vram_virt;
+ da8xx_fb_fix.smem_start = gpanel.frameAdrs;
+ da8xx_fb_fix.smem_len = par->vram_size;
+ da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8;
+
+ par->dma_start = par->vram_phys;
+ par->dma_end = par->dma_start + lcd_panel->height *
+ da8xx_fb_fix.line_length - 1;
+
+ /* allocate palette buffer */
+ par->v_palette_base = malloc(PALETTE_SIZE);
+ if (!par->v_palette_base) {
+ printf("GLCD: malloc for palette buffer failed\n");
+ goto err_release_fb_mem;
+ }
+ memset(par->v_palette_base, 0, PALETTE_SIZE);
+ par->p_palette_base = (unsigned int)par->v_palette_base;
+
+ /* Initialize par */
+ da8xx_fb_info->var.bits_per_pixel = lcd_cfg.bpp;
+
+ da8xx_fb_var.xres = lcd_panel->width;
+ da8xx_fb_var.xres_virtual = lcd_panel->width;
+
+ da8xx_fb_var.yres = lcd_panel->height;
+ da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
+
+ da8xx_fb_var.grayscale =
+ lcd_cfg.p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
+ da8xx_fb_var.bits_per_pixel = lcd_cfg.bpp;
+
+ da8xx_fb_var.hsync_len = lcd_panel->hsw;
+ da8xx_fb_var.vsync_len = lcd_panel->vsw;
+
+ /* Initialize fbinfo */
+ da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
+ da8xx_fb_info->fix = da8xx_fb_fix;
+ da8xx_fb_info->var = da8xx_fb_var;
+ da8xx_fb_info->pseudo_palette = par->pseudo_palette;
+ da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
+ FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
+
+ /* Clear interrupt */
+ memset((void *)par->vram_virt, 0, par->vram_size);
+ lcd_disable_raster();
+ lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
+ debug("Palette at 0x%x size %d\n", par->p_palette_base,
+ par->palette_sz);
+ lcdc_dma_start();
+
+ /* Load a default palette */
+ fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
+
+ /* Check that the palette is loaded */
+ wait_for_event(LCD_PL_LOAD_DONE);
+
+ /* Wait until DMA is working */
+ wait_for_event(LCD_END_OF_FRAME0);
+
+ return (void *)&gpanel;
+
+err_release_fb_mem:
+ free(par->vram_virt);
+
+err_release_fb:
+ free(da8xx_fb_info);
+
+ return NULL;
+}
+
+void video_set_lut(unsigned int index, /* color number */
+ unsigned char r, /* red */
+ unsigned char g, /* green */
+ unsigned char b /* blue */
+ )
+{
+
+ return;
+}
+
+void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel)
+{
+ lcd_panel = panel;
+ bits_x_pixel = bits_pixel;
+}
int video_get_params (struct ctfb_res_modes *pPar, char *penv)
{
char *p, *s, *val_s;
- int i = 0, t;
+ int i = 0;
int bpp;
int mode;
+
/* first search for the environment containing the real param string */
s = penv;
- if ((p = getenv (s)) != NULL) {
+
+ if ((p = getenv (s)) != NULL)
s = p;
- }
- /* in case of the bootargs line, we have to start
+
+ /*
+ * in case of the bootargs line, we have to start
* after "video=ctfb:"
*/
i = video_search_param (s, "video=ctfb:");
}
/* search for mode as a default value */
p = s;
- t = 0;
mode = 0; /* default */
+
while ((i = video_get_param_len (p, ',')) != 0) {
GET_OPTION ("mode:", mode)
p += i;
if (*p != 0)
p++; /* skip ',' */
}
+
if (mode >= RES_MODES_COUNT)
mode = 0;
+
*pPar = res_mode_init[mode]; /* copy default values */
bpp = 24 - ((mode % 3) * 8);
p = s; /* restart */
+
while ((i = video_get_param_len (p, ',')) != 0) {
GET_OPTION ("x:", pPar->xres)
GET_OPTION ("y:", pPar->yres)
int fat_register_device (block_dev_desc_t * dev_desc, int part_no)
{
unsigned char buffer[dev_desc->blksz];
- disk_partition_t info;
if (!dev_desc->block_read)
return -1;
defined(CONFIG_CMD_USB) || \
defined(CONFIG_MMC) || \
defined(CONFIG_SYSTEMACE) )
- /* First we assume there is a MBR */
- if (!get_partition_info(dev_desc, part_no, &info)) {
- part_offset = info.start;
- cur_part = part_no;
- } else if ((strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3) == 0) ||
- (strncmp((char *)&buffer[DOS_FS32_TYPE_OFFSET], "FAT32", 5) == 0)) {
- /* ok, we assume we are on a PBR only */
- cur_part = 1;
- part_offset = 0;
- } else {
- printf("** Partition %d not valid on device %d **\n",
- part_no, dev_desc->dev);
- return -1;
+ {
+ disk_partition_t info;
+
+ /* First we assume there is a MBR */
+ if (!get_partition_info(dev_desc, part_no, &info)) {
+ part_offset = info.start;
+ cur_part = part_no;
+ } else if ((strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],
+ "FAT", 3) == 0) ||
+ (strncmp((char *)&buffer[DOS_FS32_TYPE_OFFSET],
+ "FAT32", 5) == 0)) {
+ /* ok, we assume we are on a PBR only */
+ cur_part = 1;
+ part_offset = 0;
+ } else {
+ printf("** Partition %d not valid on device %d **\n",
+ part_no, dev_desc->dev);
+ return -1;
+ }
}
-
#else
if ((strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3) == 0) ||
(strncmp((char *)&buffer[DOS_FS32_TYPE_OFFSET], "FAT32", 5) == 0)) {
/* ok, we assume we are on a PBR only */
cur_part = 1;
part_offset = 0;
- info.start = part_offset;
} else {
/* FIXME we need to determine the start block of the
* partition where the DOS FS resides. This can be done
/*
* Configuration for environment
- * Environment is embedded in u-boot in the second sector of the flash
+ * Environment is not embedded in u-boot. First time runing may have env
+ * crc error warning if there is no correct environment on the flash.
*/
#ifdef CONFIG_CF_SBF
# define CONFIG_ENV_IS_IN_SPI_FLASH
*/
#ifdef CONFIG_SYS_STMICRO_BOOT
# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
# define CONFIG_ENV_OFFSET 0x30000
# define CONFIG_ENV_SIZE 0x1000
# define CONFIG_ENV_SECT_SIZE 0x10000
#ifdef CONFIG_SYS_SPANSION_BOOT
# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000)
+# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
# define CONFIG_ENV_SIZE 0x1000
# define CONFIG_ENV_SECT_SIZE 0x8000
#endif
#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 * 1024))
#define CONFIG_SYS_PROMPT "AM335X# "
#define CONFIG_SYS_NO_FLASH
+#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
#define CONFIG_CMD_ASKENV
--- /dev/null
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* SoC Configuration */
+#define CONFIG_ARM926EJS /* arm926ejs CPU */
+#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SOC_DM365
+
+#define CONFIG_MACH_TYPE MACH_TYPE_DAVINCI_DM365_EVM
+
+#define CONFIG_HOSTNAME cam_enc_4xx
+
+#define BOARD_LATE_INIT
+#define CONFIG_CAM_ENC_LED_MASK 0x0fc00000
+
+/* Memory Info */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MiB */
+#define DDR_4BANKS /* 4-bank DDR2 (256MB) */
+#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* Serial Driver info: UART0 for console */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM1 0x01c20000
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Network Configuration */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM 0
+#define CONFIG_SYS_EMAC_TI_CLKDIV 0xa9 /* 1MHz */
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#define CONFIG_CMD_MII
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_RESET_PHY_R
+
+/* I2C */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
+
+/* NAND: socketed, two chipselects, normally 2 GBytes */
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS 2
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
+/* socket has two chipselects, nCE0 gated by address BIT(14) */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+
+/* SPI support */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK davinci_clk_get(SPI_PLLDIV)
+#define CONFIG_SF_DEFAULT_SPEED 3000000
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_CMD_SF
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#define CONFIG_MMC_MBLOCK
+
+/* U-Boot command configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+
+#ifdef CONFIG_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#endif
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* U-Boot general configuration */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "cam_enc_4xx> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_LONGHELP
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x0
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_CMD_ENV
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
+#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
+#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_TIMESTAMP
+
+/* U-Boot memory configuration */
+#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
+#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
+#define CONFIG_SYS_MEMTEST_START 0x80000000 /* physical address */
+#define CONFIG_SYS_MEMTEST_END 0x81000000 /* test 16MB RAM */
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
+#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
+
+#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
+
+#ifdef CONFIG_SYS_NAND_LARGEPAGE
+/* Use same layout for 128K/256K blocks; allow some bad blocks */
+#define PART_BOOT "2m(bootloader)ro,"
+#endif
+
+#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
+#define PART_REST "-(filesystem)"
+
+#define MTDPARTS_DEFAULT \
+ "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
+
+#define CONFIG_SYS_NAND_PAGE_SIZE (0x800)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (0x20000)
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_LOAD
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POST_MEM_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds"
+#define CONFIG_SPL_STACK (0x00010000 + 0x7f00)
+
+#define CONFIG_SPL_TEXT_BASE 0x0000020 /*CONFIG_SYS_SRAM_START*/
+#define CONFIG_SPL_MAX_SIZE 12320
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_TEXT_BASE 0x81080000
+#endif
+
+#define CONFIG_SYS_NAND_BASE 0x02000000
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+
+#define CONFIG_SYS_NAND_ECCPOS { \
+ 24, 25, 26, 27, 28, \
+ 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
+ 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
+ 59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_ECCSIZE 0x200
+#define CONFIG_SYS_NAND_ECCBYTES 10
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
+ CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL (40)
+
+/*
+ * RBL searches from Block n (n = 1..24)
+ * so we can define, how many UBL Headers
+ * we can write before the real spl code
+ */
+#define CONFIG_SYS_NROF_UBL_HEADER 5
+#define CONFIG_SYS_NROF_PAGES_NAND_SPL 6
+
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x81080000 /* u-boot TEXT_BASE */
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+
+/*
+ * Post tests for memory testing
+ */
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY
+#define _POST_WORD_ADDR 0x0
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0xc0000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
+
+/*
+ * U-Boot is a 3rd stage loader and if booting with spl, cpu setup is
+ * done in board_init_f from c code.
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* for UBL header */
+#define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE)
+
+#define CONFIG_SYS_DM36x_PLL1_PLLM 0x55
+#define CONFIG_SYS_DM36x_PLL1_PREDIV 0x8005
+#define CONFIG_SYS_DM36x_PLL2_PLLM 0x09
+#define CONFIG_SYS_DM36x_PLL2_PREDIV 0x8000
+#define CONFIG_SYS_DM36x_PERI_CLK_CTRL 0x243F04FC
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV1 0x801b
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV2 0x8001
+/* POST DIV 680/2 = 340Mhz -> MJCP and HDVICP bus interface clock */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV3 0x8001
+/*
+ * POST DIV 680/4 = 170Mhz -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
+ * interface clk)
+ */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV4 0x8003
+/* POST DIV 680/2 = 340Mhz -> VPSS */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV5 0x8001
+/* POST DIV 680/9 = 75.6 Mhz -> VENC */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV6 0x8008
+/*
+ * POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
+ * down to 340 Mhz)
+ */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV7 0x8000
+/* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV8 0x8006
+/* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV9 0x801b
+
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV1 0x8011
+/* POST DIV 432/1=432 Mhz -> ARM926/(HDVICP block) clk */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV2 0x8000
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV3 0x8001
+/* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV4 0x8014
+/* POST DIV 432/16=27 Mhz -> VENC(For SD modes, requires) */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV5 0x800f
+
+/*
+ * READ LATENCY 7 (CL + 2)
+ * CONFIG_PWRDNEN = 1
+ * CONFIG_EXT_STRBEN = 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_DDRPHYCR (0 \
+ | DV_DDR_PHY_EXT_STRBEN \
+ | DV_DDR_PHY_PWRDNEN \
+ | (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+/*
+ * T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
+ * T_RP = (trp/DDR_CLK) - 1 = (12.5 / 2.941) - 1
+ * T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
+ * T_WR = (twr/DDR_CLK) - 1 = (15 / 2.941) - 1
+ * T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
+ * T_RC = (trc/DDR_CLK) - 1 = (57.5 / 2.941) - 1
+ * T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ * T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_SDTIMR (0 \
+ | (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
+ | (4 << DV_DDR_SDTMR1_RP_SHIFT) \
+ | (4 << DV_DDR_SDTMR1_RCD_SHIFT) \
+ | (5 << DV_DDR_SDTMR1_WR_SHIFT) \
+ | (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
+ | (19 << DV_DDR_SDTMR1_RC_SHIFT) \
+ | (2 << DV_DDR_SDTMR1_RRD_SHIFT) \
+ | (2 << DV_DDR_SDTMR1_WTR_SHIFT))
+
+/*
+ * T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
+ * T_XP = tCKE - 1 = 3 - 2
+ * T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
+ * T_XSRD = txsrd - 1 = 200 - 1
+ * T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ * T_CKE = tcke - 1 = 3 - 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_SDTIMR2 (0 \
+ | (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) \
+ | (2 << DV_DDR_SDTMR2_XP_SHIFT) \
+ | (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
+ | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) \
+ | (2 << DV_DDR_SDTMR2_RTP_SHIFT) \
+ | (2 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+/* PR_OLD_COUNT = 0xfe */
+#define CONFIG_SYS_DM36x_DDR2_PBBPR 0x000000FE
+/* refresh rate = 0x768 */
+#define CONFIG_SYS_DM36x_DDR2_SDRCR 0x00000768
+
+#define CONFIG_SYS_DM36x_DDR2_SDBCR (0 \
+ | (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
+ | (3 << DV_DDR_SDCR_IBANK_SHIFT) \
+ | (5 << DV_DDR_SDCR_CL_SHIFT) \
+ | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \
+ | (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
+ | (1 << DV_DDR_SDCR_DDREN_SHIFT) \
+ | (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) \
+ | (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
+ | (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
+ | (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
+
+#define CONFIG_SYS_DM36x_AWCCR 0xff
+#define CONFIG_SYS_DM36x_AB1CR 0x40400204
+#define CONFIG_SYS_DM36x_AB2CR 0x04ca2650
+
+/* All Video Inputs */
+#define CONFIG_SYS_DM36x_PINMUX0 0x00000000
+/*
+ * All Video Outputs,
+ * GPIO 86, 87 + 90 0x0000f030
+ */
+#define CONFIG_SYS_DM36x_PINMUX1 0x00530002
+#define CONFIG_SYS_DM36x_PINMUX2 0x00001815
+/*
+ * SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
+ * GPIO 25 0x60000000
+ */
+#define CONFIG_SYS_DM36x_PINMUX3 0x9b5affff
+/*
+ * MMC/SD0 instead of MS, SPI0
+ * GPIO 34 0x0000c000
+ */
+#define CONFIG_SYS_DM36x_PINMUX4 0x00002655
+
+/*
+ * Default environment settings
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define DVN4XX_UBOOT_ADDR_R_RAM 0x80000000
+/* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
+#define DVN4XX_UBOOT_ADDR_R_NAND_SPL 0x80000800
+/*
+ * (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
+ * CONFIG_SYS_NAND_PAGE_SIZE))
+ */
+#define DVN4XX_UBOOT_ADDR_R_UBOOT 0x80003800
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "u_boot_addr_r=" xstr(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.ubl\0" \
+ "load=tftp ${u_boot_addr_r} ${uboot}\0" \
+ "pagesz=" xstr(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \
+ "writeheader=nandrbl rbl;nand erase 80000 ${pagesz};" \
+ "nand write ${u_boot_addr_r} 80000 ${pagesz};" \
+ "nandrbl uboot\0" \
+ "writenand_spl=nandrbl rbl;nand erase a0000 3000;" \
+ "nand write " xstr(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \
+ " a0000 3000;nandrbl uboot\0" \
+ "writeuboot=nandrbl uboot;" \
+ "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
+ xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \
+ ";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT) \
+ " " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
+ xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
+ "update=run load writenand_spl writeuboot\0" \
+ "bootcmd=run bootcmd\0" \
+ "rootpath=/opt/eldk-arm/arm\0" \
+ "\0"
+
+/* USB Configuration */
+#define CONFIG_USB_DAVINCI
+#define CONFIG_MUSB_HCD
+#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
+ USBPHY_PHY24MHZ)
+
+#define CONFIG_CMD_USB /* include support for usb cmd */
+#define CONFIG_USB_STORAGE /* MSC class support */
+#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
+#define CONFIG_CMD_FAT /* inclue support for FAT/storage */
+#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
+
+#undef DAVINCI_DM365EVM
+#define PINMUX4_USBDRVBUS_BITCLEAR 0x3000
+#define PINMUX4_USBDRVBUS_BITSET 0x2000
+
+#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <asm/mach-types.h>
+#ifdef MACH_TYPE_OMAP3_CPS
+#error "MACH_TYPE_OMAP3_CPS has been defined properly, please remove this."
+#else
+#define MACH_TYPE_OMAP3_CPS 2751
+#endif
+#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS
+
/*
* High Level Configuration Options
*/
*/
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_USE_SPIFLASH
+#define CONFIG_SYS_USE_NAND
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_BOARD_EARLY_INIT_F
+#define BOARD_LATE_INIT
+#define CONFIG_VIDEO
+#define CONFIG_PREBOOT
/*
* SoC Configuration
/*
* Memory Info
*/
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 4*1024*1024) /* malloc() len */
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
-#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 100000
+
/*
* Network & Ethernet Configuration
*/
#undef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (8 << 10)
-#define CONFIG_ENV_OFFSET (256 << 10)
+#define CONFIG_ENV_OFFSET 0x80000
#define CONFIG_ENV_SECT_SIZE (64 << 10)
#define CONFIG_SYS_NO_FLASH
#endif
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_VIDEO_DA8XX
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_CMD_BMP
+#endif
+
/*
* U-Boot general configuration
*/
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_I2C
#ifndef CONFIG_DRIVER_TI_EMAC
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_PING
#endif
-#ifdef CONFIG_USE_NAND
+/* NAND Setup */
+#ifdef CONFIG_SYS_USE_NAND
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
#define CONFIG_RBTREE
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
+
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS 2
+#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
+/* SPI Flash */
#ifdef CONFIG_USE_SPIFLASH
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_SAVEENV
#endif
-#if !defined(CONFIG_USE_NAND) && \
+#if !defined(CONFIG_SYS_USE_NAND) && \
!defined(CONFIG_USE_NOR) && \
!defined(CONFIG_USE_SPIFLASH)
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_SDRAM_BASE 0xc0000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
GENERATED_GBL_DATA_SIZE)
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+
+#define CONFIG_HOSTNAME ea20
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "as=3\0" \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "rfsbargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rfsbpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "mtdids=nand0=davinci_nand.0\0" \
+ "mtdparts=mtdparts=davinci_nand.0:8m(Settings),8m(aKernel)," \
+ "8m(bKernel),76m(aRootfs),76m(bRootfs),-(MassSD)\0" \
+ "nandargs=setenv bootargs rootfstype=ubifs ro chk_data_crc " \
+ "ubi.mtd=${as} root=ubi0:rootfs\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=${consoledev},${baudrate}n8\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "addmem=setenv bootargs ${bootargs} mem=${memory}\0" \
+ "consoledev=ttyS0\0" \
+ "loadaddr=c0000014\0" \
+ "memory=32M\0" \
+ "kernel_addr_r=c0700000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc addmem;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc addmem;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run nfsargs addip addtty addmtd addmisc addmem;" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_rfsb=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run rfsbargs addip addtty addmtd addmisc addmem; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "nand_nand=ubi part nand0,${as};ubifsmount rootfs;" \
+ "ubifsload ${kernel_addr_r} /boot/uImage;" \
+ "ubifsumount; run nandargs addip addtty " \
+ "addmtd addmisc addmem;bootm ${kernel_addr_r}\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load_magic=if sf probe 0;then sf " \
+ "read c0000000 0x10000 0x60000;fi\0" \
+ "load_nand=ubi part nand0,${as};ubifsmount rootfs;" \
+ "if ubifsload c0000014 /boot/u-boot.bin;" \
+ "then mw c0000008 ${filesize};else echo Error reading " \
+ "u-boot from nand!;fi\0" \
+ "load_net=if sf probe 0;then sf read c0000000 0x10000 0x60000;" \
+ "tftp c0000014 ${u-boot};" \
+ "mw c0000008 ${filesize};" \
+ "fi\0" \
+ "upd=if sf probe 0;then sf erase 10000 60000;" \
+ "sf write c0000000 10000 60000;" \
+ "fi\0" \
+ "ubootupd_net=if run load_net;then echo Updating u-boot;" \
+ "if run upd; then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "ubootupd_nand=echo run load_magic,run load_nand,run upd;\0" \
+ "bootcmd=run net_nfs\0"
+
#endif /* __CONFIG_H */
#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_EARLY_INIT_F
+#define MACH_TYPE_EB_CPUX9K2 1977
+#define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2
/*--------------------------------------------------------------------------*/
#define CONFIG_SYS_TEXT_BASE 0x00000000
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
#define CONFIG_FSL_PMIC_CLK 25000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13783
+#define CONFIG_RTC_MC13XXX
#endif
/*
--- /dev/null
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration for the flea3 board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX35
+#define CONFIG_MX35_HCLK_FREQ 24000000
+
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Only in case the value is not present in mach-types.h */
+#ifndef MACH_TYPE_FLEA3
+#define MACH_TYPE_FLEA3 3668
+#endif
+
+#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
+
+/* Set TEXT at the beginning of the NOR flash */
+#define CONFIG_SYS_TEXT_BASE 0xA0000000
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+/* This is required to setup the ESDC controller */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_MX35_PORT3
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX35_UART3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
+
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "flea3 U-Boot > "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD1_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE CSD1_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:196m(root1)," \
+ "196m(root2),-(user);" \
+ "physmap-flash.0:512k(u-boot),64k(env1)," \
+ "64k(env2),3776k(kernel1),3776k(kernel2)"
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
+#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_HOSTNAME flea3
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=ttymxc0,${baudrate}\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "loadaddr=90800000\0" \
+ "kernel_addr_r=90800000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "net_self=if run net_self_load;then " \
+ "run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
+ "else echo Images not loades;fi\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "update=protect off ${uboot_addr} +40000;" \
+ "erase ${uboot_addr} +40000;" \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
+ "upd=if run load;then echo Updating u-boot;if run update;" \
+ "then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "bootcmd=run net_nfs\0"
+
+#endif /* __CONFIG_H */
#ifndef __CONFIG_GPLUGD_H
#define __CONFIG_GPLUGD_H
+/*
+ * FIXME: fix for error caused due to recent update to mach-types.h
+ */
+#include <asm/mach-types.h>
+#ifdef MACH_TYPE_SHEEVAD
+#error "MACH_TYPE_SHEEVAD has been defined properly, please remove this."
+#else
+#define MACH_TYPE_SHEEVAD 2625
+#endif
+
/*
* Version number information
*/
#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
#define CONFIG_ARMADA100 1 /* SOC Family Name */
#define CONFIG_ARMADA168 1 /* SOC Used on this Board */
-#define CONFIG_MACH_SHEEVAD /* Machine type */
+#define CONFIG_MACH_TYPE MACH_TYPE_SHEEVAD /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_SYS_TEXT_BASE 0x00f00000
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13783
+#define CONFIG_RTC_MC13XXX
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#include <asm/arch/imx-regs.h>
- /* High Level Configuration Options */
-#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
-#define CONFIG_MX31 1 /* in a mx31 */
+/* High Level Configuration Options */
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 /* in a mx31 */
#define CONFIG_MX31_HCLK_FREQ 26000000
#define CONFIG_MX31_CLK32 32000
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-/* Temporarily disabled */
-#if 0
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_FIT 1
-#define CONFIG_FIT_VERBOSE 1
-#endif
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
/*
* Size of malloc() pool
* Hardware drivers
*/
-#define CONFIG_HARD_I2C 1
-#define CONFIG_I2C_MXC 1
-#define CONFIG_SYS_I2C_MX31_PORT2 1
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_MX31_PORT2
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
-#define CONFIG_MXC_UART 1
-#define CONFIG_SYS_MX31_UART1 1
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX31_UART1
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BOOTDELAY 3
-#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)"
+#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro," \
+ "1536k(kernel),-(root)"
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.23.168
#define CONFIG_SERVERIP 192.168.23.2
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
- "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
- "bootargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2 rootfstype=jffs2" \
- "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)" \
- "bootcmd=run bootcmd_net\0" \
- "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 $(uimage); bootm\0" \
- "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash; bootm 0x80000000\0" \
- "unlock=yes\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "prg_uboot=tftpboot 0x80000000 $(uboot); protect off 0xa0000000 +0x20000; erase 0xa0000000 +0x20000; cp.b 0x80000000 0xa0000000 $(filesize)\0" \
- "prg_kernel=tftpboot 0x80000000 $(uimage); erase 0xa0040000 +0x180000; cp.b 0x80000000 0xa0040000 $(filesize)\0" \
- "prg_jffs2=tftpboot 0x80000000 $(jffs2); erase 0xa01c0000 0xa1ffffff; cp.b 0x80000000 0xa01c0000 $(filesize)\0" \
- "videomode=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1,sync:1241513985,vmode:0\0"
-
-
-#define CONFIG_SMC911X 1
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
+ "bootargs_flash=setenv bootargs $(bootargs) " \
+ "root=/dev/mtdblock2 rootfstype=jffs2\0" \
+ "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \
+ "tftpboot 0x80000000 $(uimage);bootm\0" \
+ "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \
+ "bootm 0x80000000\0" \
+ "unlock=yes\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "prg_uboot=tftpboot 0x80000000 $(uboot);" \
+ "protect off 0xa0000000 +0x20000;" \
+ "erase 0xa0000000 +0x20000;" \
+ "cp.b 0x80000000 0xa0000000 $(filesize)\0" \
+ "prg_kernel=tftpboot 0x80000000 $(uimage);" \
+ "erase 0xa0040000 +0x180000;" \
+ "cp.b 0x80000000 0xa0040000 $(filesize)\0" \
+ "prg_jffs2=tftpboot 0x80000000 $(jffs2);" \
+ "erase 0xa01c0000 0xa1ffffff;" \
+ "cp.b 0x80000000 0xa01c0000 $(filesize)\0" \
+ "videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \
+ "pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \
+ "sync:1241513985,vmode:0\0"
+
+
+#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE 0xa8000000
-#define CONFIG_SMC911X_32_BIT 1
+#define CONFIG_SMC911X_32_BIT
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "uboot> "
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x10000
#define CONFIG_SYS_HZ 1000
-#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_CMDLINE_EDITING
-/*-----------------------------------------------------------------------
+/*
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-/*-----------------------------------------------------------------------
+/*
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x80000000
-#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_TEXT_BASE 0xA0000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_GBL_DATA_OFFSET)
-/*-----------------------------------------------------------------------
+/*
* FLASH and environment organization
*/
#define CONFIG_SYS_FLASH_BASE 0xa0000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max number of sectors on one chip */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
-
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 0x00 /* environment starts here */
-#define CONFIG_ENV_SIZE 4096
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET 0x00 /* env. starts here */
+#define CONFIG_ENV_SIZE 4096
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* length of byte address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */
-/*-----------------------------------------------------------------------
+/*
* CFI FLASH driver setup
*/
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
+/*
+ * Timeout for Flash Erase and Flash Write
+ * timeout values are in ticks
+ */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ)
/*
* JFFS2 partitions
#define CONFIG_MXC_GPIO
-#define CONFIG_HARD_SPI 1
-#define CONFIG_MXC_SPI 1
+#define CONFIG_HARD_SPI
+#define CONFIG_MXC_SPI
#define CONFIG_CMD_SPI
-#define CONFIG_S6E63D6 1
+#define CONFIG_S6E63D6
#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_USE_ARCH_MEMSET
+#define MACH_TYPE_JADECPU 2636
+
+#define CONFIG_MACH_TYPE MACH_TYPE_JADECPU
+
/*
* Environment settings
*/
#ifndef _CONFIG_KM_ARM_H
#define _CONFIG_KM_ARM_H
+/* We got removed from Linux mach-types.h */
+#define MACH_TYPE_KM_KIRKWOOD 2255
+
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_MACH_KM_KIRKWOOD /* Machine type */
+#define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD
+
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
/* architecture specific default bootargs */
#define CONFIG_KM_DEF_BOOT_ARGS_CPU \
- "bootcountaddr=${bootcountaddr} ${mtdparts}"
+ "bootcountaddr=${bootcountaddr} ${mtdparts}" \
+ " boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"
#define CONFIG_KM_DEF_ENV_CPU \
"boot=bootm ${load_addr_r} - -\0" \
#if defined(CONFIG_SYS_NO_FLASH)
#define CONFIG_KM_UBI_PARTITION_NAME "ubi0"
#undef CONFIG_FLASH_CFI_MTD
-#undef CONFIG_CMD_JFFS2
#undef CONFIG_JFFS2_CMDLINE
#endif
#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
+/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
+#define KM_XLX_PROGRAM_B_PIN 39
+
#endif /* _CONFIG_KM_KIRKWOOD */
*/
#define CONFIG_SYS_TEXT_BASE 0x20002000
+/*
+ * since a number of boards are not being listed in linux
+ * arch/arm/tools/mach-types any more, the mach-types have to be
+ * defined here
+ */
+#define MACH_TYPE_MEESC 2165
+#define MACH_TYPE_ETHERCAN2 2407
+
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
MVGBE_SET_GMII_SPEED_TO_10_100 |\
MVGBE_SET_MII_SPEED_TO_100)
+#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0"
+
/*
* PCIe port not used on mgcoge3un
*/
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13783
+#define CONFIG_RTC_MC13XXX
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13783
+#define CONFIG_RTC_MC13XXX
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_PMIC_I2C
#define CONFIG_PMIC_FSL
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
+#define CONFIG_RTC_MC13XXX
/*
* MFD MC9SDZ60
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_NET_RETRY_COUNT 100
+#define CONFIG_CMD_DATE
#define CONFIG_BOOTDELAY 3
* increase in the final file size: 144260 vs. 109536 Bytes.
*/
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
-#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_LIBFDT
#define CONFIG_MACH_TYPE MACH_TYPE_MX51_BABBAGE
/*
#define CONFIG_FSL_PMIC_CLK 2500000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN 32
+#define CONFIG_RTC_MC13XXX
/*
* MMC Configs
#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_DATE
+
#define CONFIG_BOOTDELAY 3
-#define CONFIG_PRIME "FEC0"
+#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
#include <asm/arch/imx-regs.h>
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_BOOTDELAY 3
-#define CONFIG_PRIME "smc911x"
+#define CONFIG_ETHPRIME "smc911x"
/*Support LAN9217*/
#define CONFIG_SMC911X
#include <asm/arch/imx-regs.h>
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
-#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_LIBFDT
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_SYS_MX53_UART1
/* I2C Configs */
-#define CONFIG_CMD_I2C 1
-#define CONFIG_HARD_I2C 1
-#define CONFIG_I2C_MXC 1
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_MX53_PORT2 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
#define CONFIG_PMIC_I2C
#define CONFIG_PMIC_FSL
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8
+#define CONFIG_RTC_MC13XXX
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
+#define CONFIG_CMD_DATE
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BOOTDELAY 3
-#define CONFIG_PRIME "FEC0"
+#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
#define CONFIG_SYS_TEXT_BASE 0x77800000
#include <asm/arch/imx-regs.h>
#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_BOOTDELAY 3
-#define CONFIG_PRIME "FEC0"
+#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
#define CONFIG_SYS_TEXT_BASE 0x77800000
#include <asm/arch/imx-regs.h>
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_BOOTDELAY 3
-#define CONFIG_PRIME "FEC0"
+#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
#define CONFIG_SYS_TEXT_BASE 0x77800000
*/
#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
+#define CONFIG_NR_DRAM_BANKS 1
+#ifdef CONFIG_INETSPACE_V2
+/* Different SDRAM configuration and size for Internet Space v2 */
+#define CONFIG_SYS_KWD_CONFIG ($(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg)
+#endif
+
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
-#define CONFIG_NR_DRAM_BANKS 2
#include "mv-common.h"
/* Remove or override few declarations from mv-common.h */
*/
#define CONFIG_KIRKWOOD_GPIO
+/*
+ * Enable I2C support
+ */
+#ifdef CONFIG_CMD_I2C
+/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */
+#endif /* CONFIG_CMD_I2C */
+
/*
* File systems support
*/
/*
- * (C) Copyright 2006-2008
- * Texas Instruments.
+ * Configuration settings for the TI OMAP3 EVM board.
+ *
+ * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
* Author :
* Manikandan Pillai <mani.pillai@ti.com>
* Derived from Beagle Board and 3430 SDP code by
*
* Manikandan Pillai <mani.pillai@ti.com>
*
- * Configuration settings for the TI OMAP3 EVM board.
- *
* See file CREDITS for list of people who contributed to this
* project.
*
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
-#define CONFIG_OMAP3_EVM 1 /* working with EVM */
-
-#define CONFIG_SDRC /* The chip has SDRC controller */
+#ifndef __OMAP3EVM_CONFIG_H
+#define __OMAP3EVM_CONFIG_H
-#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/cpu.h>
#include <asm/arch/omap3.h>
-/*
- * Display CPU and Board information
+/* ----------------------------------------------------------------------------
+ * Supported U-boot commands
+ * ----------------------------------------------------------------------------
*/
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
+#include <config_cmd_default.h>
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
-#undef CONFIG_USE_IRQ /* no support for IRQs */
-#define CONFIG_MISC_INIT_R
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
- /* Sector */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-/*
- * Hardware drivers
+/* ----------------------------------------------------------------------------
+ * Supported U-boot features
+ * ----------------------------------------------------------------------------
*/
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+/* Display CPU and Board information */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
-#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
+/* Add auto-completion support */
+#define CONFIG_AUTO_COMPLETE
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-#define CONFIG_MMC 1
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_DOS_PARTITION 1
+/* ----------------------------------------------------------------------------
+ * Supported hardware
+ * ----------------------------------------------------------------------------
+ */
-/* DDR - I use Micron DDR */
-#define CONFIG_OMAP3_MICRON_DDR 1
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
/* USB
+ *
* Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
* Enable CONFIG_MUSB_UDD for Device functionalities.
*/
-#define CONFIG_USB_OMAP3 1
-#define CONFIG_MUSB_HCD 1
-/* #define CONFIG_MUSB_UDC 1 */
-
-#ifdef CONFIG_USB_OMAP3
-
-#ifdef CONFIG_MUSB_HCD
-#define CONFIG_CMD_USB
-
-#define CONFIG_USB_STORAGE
-#define CONGIG_CMD_STORAGE
-#define CONFIG_CMD_FAT
-
-#ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_USB_EVENT_POLL
-#define CONFIG_PREBOOT "usb start"
-#endif /* CONFIG_USB_KEYBOARD */
-
-#endif /* CONFIG_MUSB_HCD */
+#define CONFIG_USB_OMAP3
+#define CONFIG_MUSB_HCD
+/* #define CONFIG_MUSB_UDC */
-#ifdef CONFIG_MUSB_UDC
-/* USB device configuration */
-#define CONFIG_USB_DEVICE 1
-#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID 0x0451
-#define CONFIG_USBD_PRODUCTID 0x5678
-#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME "EVM"
-#endif /* CONFIG_MUSB_UDC */
-
-#endif /* CONFIG_USB_OMAP3 */
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
-
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
-#define CONFIG_CMD_NAND /* NAND support */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_IMLS /* List all found images */
-
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
-
-/*
- * TWL4030
+/* -----------------------------------------------------------------------------
+ * Include common board configuration
+ * -----------------------------------------------------------------------------
*/
-#define CONFIG_TWL4030_POWER 1
+#include "omap3_evm_common.h"
-/*
- * Board NAND Info.
+/* -----------------------------------------------------------------------------
+ * Default environment
+ * -----------------------------------------------------------------------------
*/
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
-#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
- /* to access */
- /* nand at CS0 */
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
- /* NAND devices */
-#define CONFIG_JFFS2_NAND
-/* nand device jffs2 lives on */
-#define CONFIG_JFFS2_DEV "nand0"
-/* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_OFFSET 0x680000
-#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
-
-/* Environment information */
#define CONFIG_BOOTDELAY 10
-#define CONFIG_BOOTFILE "uImage"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"usbtty=cdc_acm\0" \
"fi; " \
"else run nandboot; fi"
-#define CONFIG_AUTO_COMPLETE 1
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT "OMAP3_EVM # "
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command */
- /* args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
-#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
- 0x01F00000) /* 31MB */
-
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
- /* address */
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C 1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
-#elif defined(CONFIG_CMD_ONENAND)
-#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
-#endif
-
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-
-#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#elif defined(CONFIG_CMD_ONENAND)
-#define CONFIG_ENV_IS_IN_ONENAND 1
-#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
-#endif
-
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
-
-/*
- * Support for relocation
- */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-/*
- * Define the board revision statically
- */
-/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
-
-/*----------------------------------------------------------------------------
- * SMSC9115 Ethernet from SMSC9118 family
- *----------------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_NET)
-
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_32_BIT
-#define CONFIG_SMC911X_BASE 0x2C000000
-
-#endif /* (CONFIG_CMD_NET) */
-
-/*
- * BOOTP fields
- */
-
-#define CONFIG_BOOTP_SUBNETMASK 0x00000001
-#define CONFIG_BOOTP_GATEWAY 0x00000002
-#define CONFIG_BOOTP_HOSTNAME 0x00000004
-#define CONFIG_BOOTP_BOOTPATH 0x00000010
-
-#endif /* __CONFIG_H */
+#endif /* __OMAP3EVM_CONFIG_H */
--- /dev/null
+/*
+ * Common configuration settings for the TI OMAP3 EVM board.
+ *
+ * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __OMAP3_EVM_COMMON_H
+#define __OMAP3_EVM_COMMON_H
+
+/*
+ * High level configuration options
+ */
+#define CONFIG_OMAP /* This is TI OMAP core */
+#define CONFIG_OMAP34XX /* belonging to 34XX family */
+#define CONFIG_OMAP3430 /* which is in a 3430 */
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
+#define CONFIG_OMAP3_MICRON_DDR /* with MICRON DDR part */
+#define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+
+/*
+ * Clock related definitions
+ */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/* Size of environment - 128KB */
+#define CONFIG_ENV_SIZE (128 << 10)
+
+/* Size of malloc pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Stack sizes
+ * These values are used in start.S
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
+#endif
+
+/*
+ * Physical Memory Map
+ * Note 1: CS1 may or may not be populated
+ * Note 2: SDRAM size is expected to be at least 32MB
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20)
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C
+
+/* Limits for memtest */
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+ 0x01F00000) /* 31MB */
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
+
+/* -----------------------------------------------------------------------------
+ * Hardware drivers
+ * -----------------------------------------------------------------------------
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
+#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_OMAP34XX_I2C
+
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+
+/*
+ * PISMO support
+ */
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
+
+/* Monitor at start of flash - Reserve 2 sectors */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+
+/* Start location & size of environment */
+#define ONENAND_ENV_OFFSET 0x260000
+#define SMNAND_ENV_OFFSET 0x260000
+
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+
+/*
+ * NAND
+ */
+/* Physical address to access NAND */
+#define CONFIG_SYS_NAND_ADDR NAND_BASE
+
+/* Physical address to access NAND at CS0 */
+#define CONFIG_SYS_NAND_BASE NAND_BASE
+
+/* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+/* Timeout values (in ticks) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
+ CONFIG_SYS_MAX_NAND_DEVICE)
+
+#define CONFIG_SYS_JFFS2_MEM_NAND
+#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV "nand0"
+/* Start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET 0x680000
+/* Size of jffs2 partition */
+#define CONFIG_JFFS2_PART_SIZE 0xf980000
+
+/*
+ * USB
+ */
+#ifdef CONFIG_USB_OMAP3
+
+#ifdef CONFIG_MUSB_HCD
+#define CONFIG_CMD_USB
+
+#define CONFIG_USB_STORAGE
+#define CONGIG_CMD_STORAGE
+#define CONFIG_CMD_FAT
+
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_PREBOOT "usb start"
+#endif /* CONFIG_USB_KEYBOARD */
+
+#endif /* CONFIG_MUSB_HCD */
+
+#ifdef CONFIG_MUSB_UDC
+/* USB device configuration */
+#define CONFIG_USB_DEVICE
+#define CONFIG_USB_TTY
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID 0x0451
+#define CONFIG_USBD_PRODUCTID 0x5678
+#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME "EVM"
+#endif /* CONFIG_MUSB_UDC */
+
+#endif /* CONFIG_USB_OMAP3 */
+
+/* ----------------------------------------------------------------------------
+ * U-boot features
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_SYS_PROMPT "OMAP3_EVM # "
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_MAXARGS 16 /* max args for a command */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of Console IO buffer */
+#define CONFIG_SYS_CBSIZE 512
+
+/* Size of print buffer */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Size of bootarg buffer */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_BOOTFILE "uImage"
+
+/*
+ * NAND / OneNAND
+ */
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#elif defined(CONFIG_CMD_ONENAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
+#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+#endif
+
+#if !defined(CONFIG_ENV_IS_NOWHERE)
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#elif defined(CONFIG_CMD_ONENAND)
+#define CONFIG_ENV_IS_IN_ONENAND
+#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
+#endif
+#endif /* CONFIG_ENV_IS_NOWHERE */
+
+#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
+
+#if defined(CONFIG_CMD_NET)
+
+/* Ethernet (SMSC9115 from SMSC9118 family) */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE 0x2C000000
+
+/* BOOTP fields */
+#define CONFIG_BOOTP_SUBNETMASK 0x00000001
+#define CONFIG_BOOTP_GATEWAY 0x00000002
+#define CONFIG_BOOTP_HOSTNAME 0x00000004
+#define CONFIG_BOOTP_BOOTPATH 0x00000010
+
+#endif /* CONFIG_CMD_NET */
+
+/* Support for relocation */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+/* -----------------------------------------------------------------------------
+ * Board specific
+ * -----------------------------------------------------------------------------
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Uncomment to define the board revision statically */
+/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
+
+#endif /* __OMAP3_EVM_COMMON_H */
--- /dev/null
+/*
+ * Configuration settings for quick boot from MMC on OMAP3 EVM.
+ *
+ * Copyright (C) 2006-2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author :
+ * Sanjeev Premi <premi@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __OMAP3_EVM_QUICK_MMC_H
+#define __OMAP3_EVM_QUICK_MMC_H
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/* ----------------------------------------------------------------------------
+ * Supported U-boot commands
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+
+/*
+ * Board revision is detected by probing the Ethernet chip.
+ *
+ * When revision is statically configured via CONFIG_STATIC_BOARD_REV,
+ * this option can be removed. Generated binary is leaner by ~16Kbytes.
+ */
+#define CONFIG_CMD_NET
+
+/* ----------------------------------------------------------------------------
+ * Supported U-boot features
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_ENV_IS_NOWHERE
+
+/* ----------------------------------------------------------------------------
+ * Supported hardware
+ * ----------------------------------------------------------------------------
+ */
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* -----------------------------------------------------------------------------
+ * Include common board configuration
+ * -----------------------------------------------------------------------------
+ */
+#include "omap3_evm_common.h"
+
+/* -----------------------------------------------------------------------------
+ * Default environment
+ * -----------------------------------------------------------------------------
+ */
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=no\0" \
+ "silent=1"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc rescan 0; " \
+ "fatload mmc 0 0x82000000 uImage; " \
+ "bootm 0x82000000;"
+
+/*
+ * Update the bootargs as necessary e.g. size of memory, partition and fstype
+ */
+#define CONFIG_BOOTARGS \
+ "quiet " \
+ "console=ttyO0,115200n8 " \
+ "mem=128M " \
+ "noinitrd " \
+ "root=/dev/mmcblk0p2 rw " \
+ "rootfstype=ext3 rootwait"
+
+#endif /* __OMAP3_EVM_QUICK_MMC_H */
--- /dev/null
+/*
+ * Configuration settings for quick boot from NAND on OMAP3 EVM.
+ *
+ * Copyright (C) 2006-2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author :
+ * Sanjeev Premi <premi@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __OMAP3_EVM_QUICK_NAND_H
+#define __OMAP3_EVM_QUICK_NAND_H
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/* ----------------------------------------------------------------------------
+ * Supported U-boot commands
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_CMD_NAND
+
+/*
+ * Board revision is detected by probing the Ethernet chip.
+ *
+ * When revision is statically configured via CONFIG_STATIC_BOARD_REV,
+ * this option can be removed. Generated binary is leaner by ~16Kbytes.
+ */
+#define CONFIG_CMD_NET
+
+/* ----------------------------------------------------------------------------
+ * Supported U-boot features
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_ENV_IS_NOWHERE
+
+/* -----------------------------------------------------------------------------
+ * Include common board configuration
+ * -----------------------------------------------------------------------------
+ */
+#include "omap3_evm_common.h"
+
+/* -----------------------------------------------------------------------------
+ * Default environment
+ * -----------------------------------------------------------------------------
+ */
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=no\0" \
+ "silent=1"
+
+#define CONFIG_BOOTCOMMAND \
+ "nandecc hw; " \
+ "nand read.i 0x80000000 280000 300000; " \
+ "bootm 0x80000000;"
+
+/*
+ * Update the bootargs as necessary e.g. size of memory, partition and fstype
+ */
+#define CONFIG_BOOTARGS \
+ "quiet " \
+ "console=ttyO0,115200n8 " \
+ "mem=128M " \
+ "noinitrd " \
+ "root=/dev/mtdblock4 rw " \
+ "rootfstype=jffs2 "
+
+#endif /* __OMAP3_EVM_QUICK_NAND_H */
--- /dev/null
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from omap3_beagle.h:
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the TI OMAP3530 Beagle board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
+#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT 1
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SERIAL_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3 /* UART3 */
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
+#define CONFIG_USBD_VENDORID 0x164c
+#define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201
+#define CONFIG_USBD_PRODUCTID_CDCACM 0x0201
+#define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH"
+#define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X"
+
+/* no FLASH available */
+#define CONFIG_SYS_NO_FLASH
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_FPGA
+
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0
+#define CONFIG_SYS_I2C_BUS 0 /* This isn't used anywhere ?? */
+#define CONFIG_SYS_I2C_BUS_SELECT 1 /* This isn't used anywhere ?? */
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
+/* Environment information */
+#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
+ "console=ttyO2,115200n8\0" \
+ "mpurate=600\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768-24@60\0" \
+ "defaultdisplay=dvi\0" \
+ "fpgafilename=mvbluelynx_x.rbf\0" \
+ "loadfpga=if fatload mmc ${mmcdev} ${loadaddr} ${fpgafilename}; then " \
+ "fpga load 0 ${loadaddr} ${filesize}; " \
+ "fi;\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype} " \
+ "${cmdline_suffix}\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "mmcbootcmd= " \
+ "echo Trying mmc${mmcdev}; " \
+ "mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loading boot environment from mmc${mmcdev}; " \
+ "run importbootenv; " \
+ "fi;" \
+ "run loadfpga; " \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "fi;" \
+ "fi\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv mmcdev 1;" \
+ "run mmcbootcmd || " \
+ "setenv mmcdev 0;" \
+ "run mmcbootcmd"
+
+
+#define CONFIG_AUTO_COMPLETE 1
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "mvblx # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */
+#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */
+#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+#define CONFIG_ENV_IS_NOWHERE 1
+
+/*----------------------------------------------------------------------------
+ * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_NET_MULTI
+ #define CONFIG_SMC911X 1
+ #define CONFIG_SMC911X_32_BIT
+ #define CONFIG_SMC911X_BASE 0x2C000000
+#endif /* (CONFIG_CMD_NET) */
+
+#define CONFIG_FPGA_COUNT 1
+#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_EEPROM_BUS_NUM 2
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_OMAP3_SPI
+
+#endif /* __CONFIG_H */
#define COPY_BL2_SIZE 0x80000
#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
#endif /* __CONFIG_H */
*/
#define CONFIG_SYS_TEXT_BASE 0x20002000
+/*
+ * since a number of boards are not being listed in linux
+ * arch/arm/tools/mach-types any more, the mach-types have to be
+ * defined here
+ */
+#define MACH_TYPE_OTC570 2166
+
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
#define CONFIG_PORTL2
#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
-#define KM_ENV_BUS "pca9544a:70:a" /* I2C2 (Mux-Port 2)*/
+/*
+ * Note: This is only valid for HW > P1A if you got an outdated P1A
+ * use KM_ENV_BUS "pca9544a:70:a"
+ */
+#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
/*
* portl2 has a fixed link to the XMPP backplane
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
-#define CONFIG_MX31 1 /* in a mx31 */
-#define CONFIG_QONG 1
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 /* in a mx31 */
+#define CONFIG_QONG
#define CONFIG_MX31_HCLK_FREQ 26000000 /* 26MHz */
#define CONFIG_MX31_CLK32 32768
#define CONFIG_SYS_TEXT_BASE 0xa0000000
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
/*
* Size of malloc() pool
*/
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1536 * 1024)
/*
* Hardware drivers
#define CONFIG_MXC_SPI
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_RTC_MC13783
+#define CONFIG_RTC_MC13XXX
#define CONFIG_PMIC
#define CONFIG_PMIC_SPI
/* FPGA */
#define CONFIG_FPGA
-#define CONFIG_QONG_FPGA 1
+#define CONFIG_QONG_FPGA
#define CONFIG_FPGA_BASE (CS1_BASE)
#define CONFIG_FPGA_LATTICE
#define CONFIG_FPGA_COUNT 1
#ifdef CONFIG_QONG_FPGA
/* Ethernet */
-#define CONFIG_DNET 1
+#define CONFIG_DNET
#define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
/* Framebuffer and LCD */
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
/* USB */
#define CONFIG_CMD_USB
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_SPI
+#define CONFIG_CMD_UNZIP
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_HZ 1000
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
-#define CONFIG_MISC_INIT_R 1
+#define CONFIG_MISC_INIT_R
/*-----------------------------------------------------------------------
* Stack sizes
*
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
-#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
* CFI FLASH driver setup
*/
/* Flash memory is CFI compliant */
-#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_SYS_FLASH_CFI
/* Use drivers/cfi_flash.c */
-#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER
/* Use buffered writes (~10x faster) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
/* Use hardware sector protection */
-#define CONFIG_SYS_FLASH_PROTECTION 1
+#define CONFIG_SYS_FLASH_PROTECTION
/*
* Filesystem
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
-#define CONFIG_BOARD_EARLY_INIT_F 1
+#define CONFIG_BOARD_EARLY_INIT_F
#endif /* __CONFIG_H */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#define CONFIG_PMIC
#define CONFIG_PMIC_I2C
#define CONFIG_PMIC_MAX8998
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#include <asm/arch/gpio.h>
+/*
+ * I2C Settings
+ */
+#define CONFIG_SOFT_I2C_GPIO_SCL s5pc210_gpio_part1_get_nr(b, 7)
+#define CONFIG_SOFT_I2C_GPIO_SDA s5pc210_gpio_part1_get_nr(b, 6)
+
+#define CONFIG_SOFT_I2C
+#define CONFIG_SOFT_I2C_READ_REPEATED_START
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS 7
+
+#define CONFIG_PMIC
+#define CONFIG_PMIC_I2C
+#define CONFIG_PMIC_MAX8998
+
#endif /* __CONFIG_H */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+/* Mach Type */
+#define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310
+
/* Keep L2 Cache Disabled */
#define CONFIG_L2_OFF 1
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_MMC_U_BOOT
+
+/* MMC SPL */
+#define CONFIG_SPL
+#define COPY_BL2_FNPTR_ADDR 0x00002488
#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
--- /dev/null
+/*
+ * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
+ * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * Configuration settings for the HALE TT-01 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARM1136
+#define CONFIG_MX31
+#define CONFIG_MX31_HCLK_FREQ 26000000
+#define CONFIG_MX31_CLK32 32768
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */
+#define CONFIG_SYS_TEXT_BASE 0xA0000000
+
+
+/*
+ * Physical Memory Map:
+ * CS settings are defined by i.MX31:
+ * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000
+ * - CS0 and CS1 are 128MB each, at A0000000 and A8000000
+ * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6..
+ *
+ * HALE set-up of the bluetechnix board for now is:
+ * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface
+ * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0
+ * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM)
+ * the flash chip is a mirrorbit S29WS256N !
+ * - the PSRAM is hooked to CS5 (0xB6000000)
+ * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1
+ * - 64Mbit = 8MByte (will go away in the production set-up)
+ * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC:
+ * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks
+ * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface
+ *
+ * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM
+ * is not used right now. We should be able to reduce the SOM to NAND flash
+ * only and boot from there.
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
+
+/* default load address, 1MB up the road */
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000)
+
+/* The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/* Size of malloc() pool, make sure possible frame buffer fits */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024)
+
+/* memtest works on all but the last 1MB (u-boot) and malloc area */
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END \
+ (PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000))
+
+/* CFI FLASH driver setup */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
+#define CONFIG_FLASH_SPANSION_S29WS_N
+/*
+ * TODO: Bluetechnix (the supplier of the SOM) did define these values
+ * in their original version of u-boot (1.2 or so). This should be
+ * reviewed.
+ *
+ * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+ * #define CONFIG_SYS_FLASH_PROTECTION
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */
+
+/*
+ * FLASH and environment organization, only the Spansion chip is supported:
+ * - it has 254 * 128kB + 8 * 32kB blocks
+ * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF
+ * and 2 sectors with 128k as environment =
+ * A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF
+ * - this could be less, but this is only for developer versions of the board
+ * and no-one is going to use the NOR flash anyway.
+ *
+ * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is
+ * way to large, but it avoids ENV overwrite (when updating u-boot) in case
+ * size breaks the next boundary (as it has with 128k).
+ */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE (8 * 1024) /* smaller for faster access */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+
+/* Hardware drivers */
+
+/*
+ * on TT-01 UART1 pins are used by Audio, so we use UART2
+ * TT-01 implements a hardware that turns off components depending on
+ * the power level. In PL=1 the RS232 transceiver is usually off,
+ * make sure that the transceiver is enabled during PL=1 for testing!
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX31_UART2
+
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/* MC13783 connected to CSPI3 and SS0 */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_SPI
+#define CONFIG_PMIC_FSL
+
+#define CONFIG_FSL_PMIC_BUS 2
+#define CONFIG_FSL_PMIC_CS 0
+#define CONFIG_FSL_PMIC_CLK 1000000
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_BITLEN 32
+
+#define CONFIG_RTC_MC13XXX
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+/* console is UART2 on TT-01 */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/* ethernet setup for the onboard smc9118 */
+#define CONFIG_MII
+#define CONFIG_SMC911X
+/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */
+#define CONFIG_SMC911X_BASE (CS4_BASE+0x200000)
+#define CONFIG_SMC911X_16_BIT
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_NAND
+/*
+ * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support
+ * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports
+ * a software locking scheme.
+ */
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * currently a default setting for booting via script is implemented
+ * set user to login name and serverip to tftp host, define your
+ * boot behaviour in bootscript.loginname
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootcmd=dhcp bootscript.$(user); source\0"
+
+#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */
+#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */
+
+/* Miscellaneous configurable options */
+#define CONFIG_HUSH_PARSER
+#define CONFIG_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "TT01> "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_NAND_MXC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+
+/*
+ * actually this is nothing someone wants to configure!
+ * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init()
+ * is not used by the driver.
+ */
+#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
+#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
+#define CONFIG_MXC_NAND_HWECC
+
+/* the current u-boot driver does not use the nand flash setup! */
+#define CONFIG_SYS_NAND_LARGEPAGE
+/*
+ * it's not 16 bit:
+ * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ * the current u-boot mxc_nand.c tries to auto-detect, but this only
+ * reads the boot settings during reset (which might be wrong)
+ */
+
+#endif /* __CONFIG_H */
/* NAND BOOT is the only boot method */
#define CONFIG_NAND_U_BOOT
+#ifndef MACH_TYPE_TX25
+#define MACH_TYPE_TX25 2177
+#endif
+
+#define CONFIG_MACH_TYPE MACH_TYPE_TX25
+
#ifdef CONFIG_NAND_SPL
/* Start copying real U-boot from the second page */
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_BOARD_LATE_INIT
+#ifndef MACH_TYPE_TTC_VISION2
+#define MACH_TYPE_TTC_VISION2 2775
+#endif
#define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2
/*
#define CONFIG_FSL_PMIC_CLK 2500000
#define CONFIG_FSL_PMIC_MODE SPI_MODE_0
#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13783
+#define CONFIG_RTC_MC13XXX
/*
* MMC Configs
+++ /dev/null
-#
-# (C) Copyright 2006-2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# (C) Copyright 2011
-# Chander Kashyap, Samsung Electronics, <k.chander@samsung.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-CONFIG_MMC_SPL = y
-
-include $(TOPDIR)/config.mk
-
-LDSCRIPT= $(TOPDIR)/mmc_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS = -Bstatic -T $(mmcobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
-AFLAGS += -DCONFIG_MMC_SPL
-AFLAGS += -DCONFIG_SPL_BUILD
-CFLAGS += -DCONFIG_MMC_SPL
-CFLAGS += -DCONFIG_SPL_BUILD
-
-SOBJS = start.o mem_setup.o lowlevel_init.o
-COBJS = mmc_boot.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(OBJTREE)/mmc_spl/board/$(BOARDDIR)
-
-mmcobj := $(OBJTREE)/mmc_spl/
-
-
-MKV310_MMC_SPL_EXEC = mkv310_mmc_spl_exec
-MMC_SPL_BIN = u-boot-mmc-spl.bin
-
-ALL = $(mmcobj)u-boot-spl $(mmcobj)u-boot-spl.bin $(mmcobj)$(MMC_SPL_BIN)
-
-all: $(obj).depend $(ALL)
-
-$(mmcobj)$(MMC_SPL_BIN): $(mmcobj)u-boot-spl.bin tools/$(MKV310_MMC_SPL_EXEC)
- ./tools/$(MKV310_MMC_SPL_EXEC) $(mmcobj)u-boot-spl.bin $(mmcobj)$(MMC_SPL_BIN)
- rm -f tools/$(MKV310_MMC_SPL_EXEC)
-
-tools/$(MKV310_MMC_SPL_EXEC): tools/mkv310_image.c
- $(HOSTCC) tools/mkv310_image.c -o tools/$(MKV310_MMC_SPL_EXEC)
-
-$(mmcobj)u-boot-spl.bin: $(mmcobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(mmcobj)u-boot-spl: $(OBJS) $(mmcobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
- -Map $(mmcobj)u-boot-spl.map \
- -o $(mmcobj)u-boot-spl
-
-$(mmcobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-start.S:
- @rm -f $@
- @ln -s $(TOPDIR)/arch/arm/cpu/armv7/start.S $@
-
-# from board directory
-mem_setup.S:
- @rm -f $@
- @ln -s $(TOPDIR)/board/samsung/smdkv310/mem_setup.S $@
-
-lowlevel_init.S:
- @rm -f $@
- @ln -s $(TOPDIR)/board/samsung/smdkv310/lowlevel_init.S $@
-
-#########################################################################
-
-$(obj)%.o: %.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: %.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
const uchar *t;
const ushort *ss;
ushort type, tlen;
- uchar applid;
ushort vlan, nvlan;
/* minimum size? */
if (tlen < 3)
goto pkt_short;
- applid = t[0];
ss = (const ushort *)(t + 1);
#ifdef CONFIG_CDP_APPLIANCE_VLAN_TYPE
- if (applid == CONFIG_CDP_APPLIANCE_VLAN_TYPE)
+ if (t[0] == CONFIG_CDP_APPLIANCE_VLAN_TYPE)
vlan = *ss;
#else
/* XXX will this work; dunno */
LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o
LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o
+LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o
ifeq ($(SOC),omap3)
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
ifdef CONFIG_SAMSUNG
$(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin
- $(TOPDIR)/board/$(BOARDDIR)/tools/mk$(BOARD)spl.exe \
+ $(OBJTREE)/tools/mk$(BOARD)spl \
$(obj)u-boot-spl.bin $(obj)$(BOARD)-spl.bin
endif
#define UBL_IMAGE_SIZE (0x00003800u)
/* one NAND block */
-#define UBL_BLOCK_SIZE 512
+#define UBL_BLOCK_SIZE 2048
/* from sprufg5a.pdf Table 109 */
struct ubl_header {
projects / karo-tx-uboot.git / commitdiff