ARM: DRA72: DDR3: Add emif settings for 666MHz clock

On DRA72x, EMIF supports DDR3 upto 667MHz.
Adding the required settings for DDR3 at 666MHz and enabling it.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index ed89f85458dd86a6b9f06cbf7a1369ddeedfa4cd..025738302a2878a6bdd59476d67338a532ee2b5c 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -227,6 +227,16 @@ static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
        {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
 };
 
        {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
 };
 

+static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
+       {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 12 MHz   */
+       {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
+       {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
+       {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 19.2 MHz */
+       {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
+       {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
+       {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 38.4 MHz */
+};
+

 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
        {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 12 MHz   */
        {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
        {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 12 MHz   */
        {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */


@@ -286,6 +296,17 @@ struct dplls dra7xx_dplls = {
        .gmac = gmac_dpll_params_2000mhz,
 };
 
        .gmac = gmac_dpll_params_2000mhz,
 };
 

+struct dplls dra72x_dplls = {
+       .mpu = mpu_dpll_params_1ghz,
+       .core = core_dpll_params_2128mhz_dra7xx,
+       .per = per_dpll_params_768mhz_dra7xx,
+       .abe = abe_dpll_params_sysclk2_361267khz,
+       .iva = iva_dpll_params_2330mhz_dra7xx,
+       .usb = usb_dpll_params_1920mhz,
+       .ddr =  ddr_dpll_params_2664mhz,
+       .gmac = gmac_dpll_params_2000mhz,
+};
+

 struct pmic_data palmas = {
        .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
        .step = 10000, /* 10 mV represented in uV */
 struct pmic_data palmas = {
        .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
        .step = 10000, /* 10 mV represented in uV */


@@ -560,6 +581,18 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = {
        .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 };
 
        .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 };
 

+const struct ctrl_ioregs ioregs_dra72x_es1 = {
+       .ctrl_ddrch = 0x40404040,
+       .ctrl_lpddr2ch = 0x40404040,
+       .ctrl_ddr3ch = 0x60606080,
+       .ctrl_ddrio_0 = 0xA2084210,
+       .ctrl_ddrio_1 = 0x84210840,
+       .ctrl_ddrio_2 = 0x84210000,
+       .ctrl_emif_sdram_config_ext = 0x0001C1A7,
+       .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
+       .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
+};
+

 void hw_data_init(void)
 {
        u32 omap_rev = omap_revision();
 void hw_data_init(void)
 {
        u32 omap_rev = omap_revision();


@@ -592,7 +625,7 @@ void hw_data_init(void)
 
        case DRA722_ES1_0:
        *prcm = &dra7xx_prcm;
 
        case DRA722_ES1_0:
        *prcm = &dra7xx_prcm;

-       *dplls_data = &dra7xx_dplls;
+       *dplls_data = &dra72x_dplls;

        *omap_vcores = &dra722_volts;
        *ctrl = &dra7xx_ctrl;
        break;
        *omap_vcores = &dra722_volts;
        *ctrl = &dra7xx_ctrl;
        break;


@@ -619,9 +652,11 @@ void get_ioregs(const struct ctrl_ioregs **regs)
                break;
        case DRA752_ES1_0:
        case DRA752_ES1_1:
                break;
        case DRA752_ES1_0:
        case DRA752_ES1_1:

-       case DRA722_ES1_0:

                *regs = &ioregs_dra7xx_es1;
                break;
                *regs = &ioregs_dra7xx_es1;
                break;

+       case DRA722_ES1_0:
+               *regs = &ioregs_dra72x_es1;
+               break;

 
        default:
                printf("\n INVALID OMAP REVISION ");
 
        default:
                printf("\n INVALID OMAP REVISION ");

diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 9105121ff60a04347c4bfd3b271ad625c0e10e1c..065199be7671db9276e044906fc270b0038c4075 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -185,6 +185,30 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .emif_rd_wr_exec_thresh         = 0x00000305
 };
 
        .emif_rd_wr_exec_thresh         = 0x00000305
 };
 

+const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
+       .sdram_config_init              = 0x61851AB2,
+       .sdram_config                   = 0x61851AB2,
+       .sdram_config2                  = 0x08000000,
+       .ref_ctrl                       = 0x00001035,
+       .sdram_tim1                     = 0xCCCF36B3,
+       .sdram_tim2                     = 0x308F7FDA,
+       .sdram_tim3                     = 0x027F88A8,
+       .read_idle_ctrl                 = 0x00050000,
+       .zq_config                      = 0x0007190B,
+       .temp_alert_config              = 0x00000000,
+       .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
+       .emif_ddr_phy_ctlr_1            = 0x0024400A,
+       .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
+       .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
+       .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
+       .emif_rd_wr_lvl_rmp_win         = 0x00000000,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
+       .emif_rd_wr_lvl_ctl             = 0x00000000,
+       .emif_rd_wr_exec_thresh         = 0x00000305
+};
+

 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
        .dmm_lisa_map_0 = 0x0,
        .dmm_lisa_map_1 = 0x0,
 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
        .dmm_lisa_map_0 = 0x0,
        .dmm_lisa_map_1 = 0x0,


@@ -267,6 +291,8 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
                }
                break;
        case DRA722_ES1_0:
                }
                break;
        case DRA722_ES1_0:

+               *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
+               break;

        default:
                *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
        }
        default:
                *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
        }


@@ -450,6 +476,35 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
        0x0
 };
 
        0x0
 };
 

+const u32
+dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
+       0x00A400A4,
+       0x00390039,
+       0x00320032,
+       0x00320032,
+       0x00320032,
+       0x00440044,
+       0x00550055,
+       0x00550055,
+       0x00550055,
+       0x00550055,
+       0x007F007F,
+       0x004D004D,
+       0x00430043,
+       0x00560056,
+       0x00540054,
+       0x00600060,
+       0x0,
+       0x00600020,
+       0x40010080,
+       0x08102040,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0
+};
+

 const struct lpddr2_mr_regs mr_regs = {
        .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
        .mr2    = 0x6,
 const struct lpddr2_mr_regs mr_regs = {
        .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
        .mr2    = 0x6,


@@ -478,7 +533,6 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
                break;
        case DRA752_ES1_0:
        case DRA752_ES1_1:
                break;
        case DRA752_ES1_0:
        case DRA752_ES1_1:

-       case DRA722_ES1_0:

                if (emif_nr == 1) {
                        *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
                        *size =
                if (emif_nr == 1) {
                        *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
                        *size =


@@ -489,6 +543,10 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
                        ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
                }
                break;
                        ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
                }
                break;

+       case DRA722_ES1_0:
+               *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
+               *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
+               break;

        default:
                *regs = ddr3_ext_phy_ctrl_const_base_es2;
                *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
        default:
                *regs = ddr3_ext_phy_ctrl_const_base_es2;
                *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);