exynos5_set_usbhost_phy_ctrl(enable);
}
+static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
+{
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+
+ if (enable) {
+ /* Enabling USBDRD_PHY */
+ setbits_le32(&power->usbdrd_phy_control,
+ POWER_USB_DRD_PHY_CTRL_EN);
+ } else {
+ /* Disabling USBDRD_PHY */
+ clrbits_le32(&power->usbdrd_phy_control,
+ POWER_USB_DRD_PHY_CTRL_EN);
+ }
+}
+
+void set_usbdrd_phy_ctrl(unsigned int enable)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_usbdrd_phy_ctrl(enable);
+}
+
static void exynos5_dp_phy_control(unsigned int enable)
{
unsigned int cfg;
debug("MPU DPLL locked\n");
}
-#ifdef CONFIG_USB_EHCI_OMAP
+#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP)
static void setup_usb_dpll(void)
{
const struct dpll_params *params;
/* MPU dpll */
configure_mpu_dpll();
-#ifdef CONFIG_USB_EHCI_OMAP
+#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP)
setup_usb_dpll();
#endif
params = get_ddr_dpll_params(*dplls_data);
struct omap_sys_ctrl_regs const omap5_ctrl = {
.control_status = 0x4A002134,
.control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4,
+ .control_phy_power_usb = 0x4A002370,
.control_padconf_core_base = 0x4A002800,
.control_paconf_global = 0x4A002DA0,
.control_paconf_mode = 0x4A002DA4,
.cm_div_m2_dpll_unipro = 0x4a0081d0,
.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
+ .cm_coreaon_usb_phy_core_clkctrl = 0x4A008640,
.cm_coreaon_bandgap_clkctrl = 0x4a008648,
.cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
.cm_l3init_p1500_clkctrl = 0x4a009678,
.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
+ .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
+ .cm_l3init_usb_otg_ss_clkctrl = 0x4a0096f0,
/* prm irqstatus regs */
.prm_irqstatus_mpu_2 = 0x4ae06014,
.cm_clkmode_dpll_dsp = 0x4a005234,
.cm_shadow_freq_config1 = 0x4a005260,
.cm_clkmode_dpll_gmac = 0x4a0052a8,
+ .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
/* cm1.mpu */
.cm_mpu_mpu_clkctrl = 0x4a005320,
interrupts = <0 130 0>;
};
+ xhci@12000000 {
+ compatible = "samsung,exynos5250-xhci";
+ reg = <0x12000000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ phy {
+ compatible = "samsung,exynos5250-usb3-phy";
+ reg = <0x12100000 0x100>;
+ };
+ };
+
ehci@12110000 {
compatible = "samsung,exynos-ehci";
reg = <0x12110000 0x100>;
/* RTC base address */
#define RTC_BASE 0x44E3E000
+/* USB Clock Control */
+#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
+#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
+#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 2)
+#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
+
+#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
+#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
+#define USBPHYOCPSCP_MODULE_EN (1 << 2)
+
#endif /* __AM43XX_HARDWARE_AM43XX_H */
#define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4_USB3PHY_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS4X12 */
#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
#define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS5 Common*/
#define EXYNOS5_I2C_SPACING 0x10000
#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
#define EXYNOS5_GPIO_PART1_BASE 0x11400000
#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
+#define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000
+#define EXYNOS5_USB3PHY_BASE 0x12100000
#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000
#define EXYNOS5_USBPHY_BASE 0x12130000
#define EXYNOS5_USBOTG_BASE 0x12140000
SAMSUNG_BASE(timer, PWMTIMER_BASE)
SAMSUNG_BASE(uart, UART_BASE)
SAMSUNG_BASE(usb_phy, USBPHY_BASE)
+SAMSUNG_BASE(usb3_phy, USB3PHY_BASE)
SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
+SAMSUNG_BASE(usb_xhci, USB_HOST_XHCI_BASE)
SAMSUNG_BASE(usb_otg, USBOTG_BASE)
SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
SAMSUNG_BASE(power, POWER_BASE)
#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0)
#define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0)
+void set_usbdrd_phy_ctrl(unsigned int enable);
+
+#define POWER_USB_DRD_PHY_CTRL_EN (1 << 0)
+#define POWER_USB_DRD_PHY_CTRL_DISABLE (0 << 0)
+
void set_dp_phy_ctrl(unsigned int enable);
#define EXYNOS_DP_PHY_ENABLE (1 << 0)
--- /dev/null
+/* Copyright (c) 2012 Samsung Electronics Co. Ltd
+ *
+ * Exynos Phy register definitions
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_EXYNOS_H_
+#define _ASM_ARCH_XHCI_EXYNOS_H_
+
+/* Phy register MACRO definitions */
+
+#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
+#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
+#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
+
+#define PHYUTMI_OTGDISABLE (1 << 6)
+#define PHYUTMI_FORCESUSPEND (1 << 1)
+#define PHYUTMI_FORCESLEEP (1 << 0)
+
+#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
+#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
+
+#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
+#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
+
+#define PHYCLKRST_SSC_EN (0x1 << 20)
+#define PHYCLKRST_REF_SSP_EN (0x1 << 19)
+#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
+
+#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
+
+#define PHYCLKRST_FSEL_MASK (0x3f << 5)
+#define PHYCLKRST_FSEL(_x) ((_x) << 5)
+#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
+#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
+#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
+#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
+
+#define PHYCLKRST_RETENABLEN (0x1 << 4)
+
+#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
+#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
+#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
+
+#define PHYCLKRST_PORTRESET (0x1 << 1)
+#define PHYCLKRST_COMMONONN (0x1 << 0)
+
+#define PHYPARAM0_REF_USE_PAD (0x1 << 31)
+#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
+#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
+
+#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
+#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
+
+#define PHYTEST_POWERDOWN_SSP (0x1 << 3)
+#define PHYTEST_POWERDOWN_HSP (0x1 << 2)
+
+#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
+
+#define FSEL_CLKSEL_24M (0x5)
+
+/* XHCI PHY register structure */
+struct exynos_usb3_phy {
+ unsigned int reserve1;
+ unsigned int link_system;
+ unsigned int phy_utmi;
+ unsigned int phy_pipe;
+ unsigned int phy_clk_rst;
+ unsigned int phy_reg0;
+ unsigned int phy_reg1;
+ unsigned int phy_param0;
+ unsigned int phy_param1;
+ unsigned int phy_term;
+ unsigned int phy_test;
+ unsigned int phy_adp;
+ unsigned int phy_batchg;
+ unsigned int phy_resume;
+ unsigned int reserve2[3];
+ unsigned int link_port;
+};
+
+#endif /* _ASM_ARCH_XHCI_EXYNOS_H_ */
#define MX6_IOMUXC_GPR6 0x020e0018
#define MX6_IOMUXC_GPR7 0x020e001c
+/*
+ * IOMUXC_GPR1 bit fields
+ */
+#define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13)
+#define IOMUXC_GPR1_OTG_ID_GPIO1 (1<<13)
+#define IOMUXC_GPR1_OTG_ID_MASK (1<<13)
/*
* IOMUXC_GPR13 bit fields
*/
#define OPTFCLKEN_USB_CH1_CLK_ENABLE (1 << 9)
#define OPTFCLKEN_USB_CH2_CLK_ENABLE (1 << 10)
+/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
+#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8)
+
+/* CM_L3INIT_USB_OTG_SS_CLKCTRL */
+#define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0)
+#define OPTFCLKEN_REFCLK960M (1 << 8)
+
+/* CM_L3INIT_OCP2SCP1_CLKCTRL */
+#define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0)
+
/* CM_MPU_MPU_CLKCTRL */
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
/* PRM_VC_VAL_BYPASS */
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
+/* CTRL_CORE_SRCOMP_NORTH_SIDE */
+#define USB2PHY_DISCHGDET (1 << 29)
+#define USB2PHY_AUTORESUME_EN (1 << 30)
+
/* SMPS */
#define SMPS_I2C_SLAVE_ADDR 0x12
#define SMPS_REG_ADDR_12_MPU 0x23
/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
#define VBUS_VLD_STS (1 << 26)
-
/* Setup USB on the board */
-int board_usb_init(const void *blob);
+int usb_process_devicetree(const void *blob);
#endif /* _TEGRA_USB_H_ */
struct ehci_hccr;
struct ehci_hcor;
-int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor);
+int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor);
int omap_ehci_hcd_stop(void);
#endif /* _OMAP_COMMON_EHCI_H_ */
u32 cm_div_m2_dpll_unipro;
u32 cm_ssc_deltamstep_dpll_unipro;
u32 cm_ssc_modfreqdiv_dpll_unipro;
+ u32 cm_coreaon_usb_phy_core_clkctrl;
+ u32 cm_coreaon_usb_phy2_core_clkctrl;
/* cm2.core */
u32 cm_coreaon_bandgap_clkctrl;
u32 cm_l3init_p1500_clkctrl;
u32 cm_l3init_fsusb_clkctrl;
u32 cm_l3init_ocp2scp1_clkctrl;
+ u32 cm_l3init_ocp2scp3_clkctrl;
+ u32 cm_l3init_usb_otg_ss_clkctrl;
u32 prm_irqstatus_mpu_2;
u32 control_core_mac_id_1_lo;
u32 control_core_mac_id_1_hi;
u32 control_std_fuse_opp_vdd_mpu_2;
+ u32 control_phy_power_usb;
u32 control_core_mmr_lock1;
u32 control_core_mmr_lock2;
u32 control_core_mmr_lock3;
*/
static char ohci_inited = 0;
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
{
u32 pin_func;
u32 sys_freqctrl, sys_clksrc;
*/
static char ohci_inited = 0;
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
{
/* Set the USB Clock */
*/
static char ohci_inited = 0;
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
{
memset (&gohci, 0, sizeof (ohci_t));
memset (&urb_priv, 0, sizeof (urb_priv_t));
/* init uhci
*/
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
{
unsigned char temp;
ambapp_ahbdev ahbdev;
#include <asm/4xx_pcie.h>
#include <asm/ppc4xx-gpio.h>
#include <asm/errno.h>
+#include <usb.h>
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
}
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
-int usb_board_init(void)
+int board_usb_init(int index, enum usb_init_type init)
{
struct board_bcsr *bcsr_data =
(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
return 0;
}
-int usb_board_init_fail(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
{
return usb_board_stop();
}
#include <asm/io.h>
#include <spartan3.h>
#include <command.h>
+#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
}
#ifdef CONFIG_CMD_USB
-int usb_board_init(void)
+int board_usb_init(int index, enum usb_init_type init)
{
writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
return 0;
}
-void usb_board_init_fail(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
{
- return;
+ return 0;
}
void usb_board_stop(void)
#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
+#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
+static iomux_v3_cfg_t const misc_pads[] = {
+ MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
+ /* OTG Power enable */
+ MX6_PAD_EIM_D22__GPIO_3_22 | MUX_PAD_CTRL(OUTPUT_40OHM),
+};
+
/* wl1271 pads on nitrogen6x */
iomux_v3_cfg_t const wl12xx_pads[] = {
(MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK)
return 0;
}
+
+int board_ehci_power(int port, int on)
+{
+ if (port)
+ return 0;
+ gpio_set_value(GP_USB_OTG_PWR, on);
+ return 0;
+}
+
#endif
#ifdef CONFIG_FSL_ESDHC
free(bus);
}
#endif
+
+#ifdef CONFIG_MV_UDC
+ /* For otg ethernet*/
+ usb_eth_initialize(bis);
+#endif
return 0;
}
gpio_direction_input(WL12XX_WL_IRQ_GP);
gpio_direction_output(WL12XX_WL_ENABLE_GP, 0);
gpio_direction_output(WL12XX_BT_ENABLE_GP, 0);
+ gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
setup_buttons();
int board_init(void)
{
+ struct iomuxc_base_regs *const iomuxc_regs
+ = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+
+ clrsetbits_le32(&iomuxc_regs->gpr[1],
+ IOMUXC_GPR1_OTG_ID_MASK,
+ IOMUXC_GPR1_OTG_ID_GPIO1);
+
+ imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
+
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
};
#define SB_T35_USB_HUB_RESET_GPIO 167
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
u8 val;
int offset;
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0);
udelay(1);
- return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
}
int ehci_hcd_stop(void)
#include <mtd/cfi_flash.h>
#include <asm/4xx_pci.h>
#include <pci.h>
+#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
}
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
-int usb_board_init(void)
+int board_usb_init(int index, enum usb_init_type init)
{
return 0;
}
return 0;
}
-int usb_board_init_fail(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
{
- usb_board_stop();
- return 0;
+ return usb_board_stop();
}
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
#endif
#include <serial.h>
#include <asm/4xx_pci.h>
+#include <usb.h>
#include "fpga.h"
#include "pmc440.h"
}
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
-int usb_board_init(void)
+int board_usb_init(int index, enum usb_init_type init)
{
char *act = getenv("usbact");
int i;
return 0;
}
-int usb_board_init_fail(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
{
- usb_board_stop();
- return 0;
+ return usb_board_stop();
}
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
}
int ehci_hcd_stop(int index)
#include <netdev.h>
#include <serial.h>
#include <asm/io.h>
+#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
#ifdef CONFIG_CMD_USB
-int usb_board_init(void)
+int board_usb_init(int index, enum usb_init_type init)
{
writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
return 0;
}
-void usb_board_init_fail(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
{
- return;
+ return 0;
}
void usb_board_stop(void)
/* init uhci
*/
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
{
unsigned char temp;
int busdevfunc;
#ifdef CONFIG_USB_EHCI_TEGRA
#include <asm/arch-tegra/usb.h>
#include <asm/arch/usb.h>
+#include <usb.h>
#endif
#ifdef CONFIG_TEGRA_MMC
#include <asm/arch-tegra/tegra_mmc.h>
#ifdef CONFIG_USB_EHCI_TEGRA
pin_mux_usb();
- board_usb_init(gd->fdt_blob);
+ usb_process_devicetree(gd->fdt_blob);
#endif
+
#ifdef CONFIG_LCD
tegra_lcd_check_next_stage(gd->fdt_blob, 0);
#endif
LIB = $(obj)libsamsung.o
COBJS-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
+COBJS-$(CONFIG_THOR_FUNCTION) += thor.o
SRCS := $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
--- /dev/null
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/usb/ch9.h>
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+ if (!strcmp(name, "usb_dnl_thor")) {
+ put_unaligned(CONFIG_G_DNL_THOR_VENDOR_NUM, &dev->idVendor);
+ put_unaligned(CONFIG_G_DNL_THOR_PRODUCT_NUM, &dev->idProduct);
+ } else {
+ put_unaligned(CONFIG_G_DNL_VENDOR_NUM, &dev->idVendor);
+ put_unaligned(CONFIG_G_DNL_PRODUCT_NUM, &dev->idProduct);
+ }
+ return 0;
+}
mmc@12230000 {
status = "disabled";
};
+
+ ehci@12110000 {
+ samsung,vbus-gpio = <&gpio 0xbe 0>; /* X26 */
+ };
};
status = "disabled";
};
+ ehci@12110000 {
+ samsung,vbus-gpio = <&gpio 0xb1 0>; /* X11 */
+ };
+
+ xhci@12000000 {
+ samsung,vbus-gpio = <&gpio 0xbf 0>; /* X27 */
+ };
+
tmu@10060000 {
samsung,min-temp = <25>;
samsung,max-temp = <125>;
static struct local_info local;
-#ifdef CONFIG_USB_EHCI_EXYNOS
-int board_usb_vbus_init(void)
-{
- struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
- samsung_get_base_gpio_part1();
-
- /* Enable VBUS power switch */
- s5p_gpio_direction_output(&gpio1->x2, 6, 1);
-
- /* VBUS turn ON time */
- mdelay(3);
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_SOUND_MAX98095
static void board_enable_audio_codec(void)
{
if (board_init_cros_ec_devices(gd->fdt_blob))
return -1;
-#ifdef CONFIG_USB_EHCI_EXYNOS
- board_usb_vbus_init();
-#endif
#ifdef CONFIG_SOUND_MAX98095
board_enable_audio_codec();
#endif
#include <power/max8997_muic.h>
#include <power/battery.h>
#include <power/max17042_fg.h>
+#include <usb.h>
#include <usb_mass_storage.h>
#include "setup.h"
.usb_flags = PHY0_SLEEP,
};
-void board_usb_init(void)
+int board_usb_init(int index, enum usb_init_type init)
{
debug("USB_udc_probe\n");
- s3c_udc_probe(&s5pc210_otg_data);
+ return s3c_udc_probe(&s5pc210_otg_data);
}
#endif
return ret;
}
-int g_dnl_bind_fixup(struct usb_device_descriptor *dev)
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
{
put_unaligned(factory_dat.usb_vendor_id, &dev->idVendor);
put_unaligned(factory_dat.usb_product_id, &dev->idProduct);
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
}
int ehci_hcd_stop(int index)
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
}
int ehci_hcd_stop(int index)
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
};
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
}
int ehci_hcd_stop(int index)
#include "mux_data.h"
-#ifdef CONFIG_USB_EHCI
-#include <usb.h>
-#include <asm/arch/ehci.h>
-#include <asm/ehci-omap.h>
-#endif
-
#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
#endif
{GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
{GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
{GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
+ {USB2_DRVVBUS, (M0 | IEN | FSC) },
};
#endif /* _MUX_DATA_DRA7XX_H_ */
#include "mux_data.h"
-#ifdef CONFIG_USB_EHCI
+#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
#include <usb.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
return 0;
}
+#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
+static void enable_host_clocks(void)
+{
+ int auxclk;
+ int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
+ OPTFCLKEN_HSIC480M_P3_CLK |
+ OPTFCLKEN_HSIC60M_P2_CLK |
+ OPTFCLKEN_HSIC480M_P2_CLK |
+ OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
+
+ /* Enable port 2 and 3 clocks*/
+ setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
+
+ /* Enable port 2 and 3 usb host ports tll clocks*/
+ setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
+ (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
+#ifdef CONFIG_USB_XHCI_OMAP
+ /* Enable the USB OTG Super speed clocks */
+ setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
+ (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
+#endif
+
+ auxclk = readl((*prcm)->scrm_auxclk1);
+ /* Request auxilary clock */
+ auxclk |= AUXCLK_ENABLE_MASK;
+ writel(auxclk, (*prcm)->scrm_auxclk1);
+}
+#endif
+
/**
* @brief misc_init_r - Configure EVM board specific configurations
* such as power configurations, ethernet initialization as phase2 of
*/
int misc_init_r(void)
{
+ int reg;
+ uint8_t device_mac[6];
+
#ifdef CONFIG_PALMAS_POWER
palmas_init_settings();
#endif
+
+ if (!getenv("usbethaddr")) {
+ reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
+
+ /*
+ * create a fake MAC address from the processor ID code.
+ * first byte is 0x02 to signify locally administered.
+ */
+ device_mac[0] = 0x02;
+ device_mac[1] = readl(reg + 0x10) & 0xff;
+ device_mac[2] = readl(reg + 0xC) & 0xff;
+ device_mac[3] = readl(reg + 0x8) & 0xff;
+ device_mac[4] = readl(reg) & 0xff;
+ device_mac[5] = (readl(reg) >> 8) & 0xff;
+
+ eth_setenv_enetaddr("usbethaddr", device_mac);
+ }
+
return 0;
}
.port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
};
-static void enable_host_clocks(void)
-{
- int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
- OPTFCLKEN_HSIC480M_P3_CLK |
- OPTFCLKEN_HSIC60M_P2_CLK |
- OPTFCLKEN_HSIC480M_P2_CLK |
- OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
-
- /* Enable port 2 and 3 clocks*/
- setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
-
- /* Enable port 2 and 3 usb host ports tll clocks*/
- setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
- (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
-}
-
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
- int auxclk;
- int reg;
- uint8_t device_mac[6];
enable_host_clocks();
- if (!getenv("usbethaddr")) {
- reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
-
- /*
- * create a fake MAC address from the processor ID code.
- * first byte is 0x02 to signify locally administered.
- */
- device_mac[0] = 0x02;
- device_mac[1] = readl(reg + 0x10) & 0xff;
- device_mac[2] = readl(reg + 0xC) & 0xff;
- device_mac[3] = readl(reg + 0x8) & 0xff;
- device_mac[4] = readl(reg) & 0xff;
- device_mac[5] = (readl(reg) >> 8) & 0xff;
-
- eth_setenv_enetaddr("usbethaddr", device_mac);
- }
-
- auxclk = readl((*prcm)->scrm_auxclk1);
- /* Request auxilary clock */
- auxclk |= AUXCLK_ENABLE_MASK;
- writel(auxclk, (*prcm)->scrm_auxclk1);
-
- ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+ ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
if (ret < 0) {
puts("Failed to initialize ehci\n");
return ret;
}
}
#endif
+
+#ifdef CONFIG_USB_XHCI_OMAP
+/**
+ * @brief board_usb_init - Configure EVM board specific configurations
+ * for the LDO's and clocks for the USB blocks.
+ *
+ * @return 0
+ */
+int board_usb_init(int index, enum board_usb_init_type init)
+{
+ int ret;
+#ifdef CONFIG_PALMAS_USB_SS_PWR
+ ret = palmas_enable_ss_ldo();
+#endif
+
+ enable_host_clocks();
+
+ return 0;
+}
+#endif
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
unsigned int utmi_clk;
utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk);
- ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+ ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
if (ret < 0)
return ret;
#include <netdev.h>
#include <asm/io.h>
#include <serial.h>
+#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
}
#ifdef CONFIG_CMD_USB
-int usb_board_init(void)
+int board_usb_init(int index, enum usb_init_type init)
{
writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
return 0;
}
-void usb_board_init_fail(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
{
- return;
+ return 0;
}
void usb_board_stop(void)
#include <asm/arch/regs-mmc.h>
#include <netdev.h>
#include <asm/io.h>
+#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
* Miscelaneous platform dependent initialisations
*/
-int usb_board_init(void)
+int board_usb_init(int index, enum usb_init_type init)
{
writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
return 0;
}
-void usb_board_init_fail(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
{
- return;
+ return 0;
}
void usb_board_stop(void)
#include <netdev.h>
#include <serial.h>
#include <asm/io.h>
+#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
#ifdef CONFIG_CMD_USB
-int usb_board_init(void)
+int board_usb_init(int index, enum usb_init_type init)
{
writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
return 0;
}
-void usb_board_init_fail(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
{
- return;
+ return 0;
}
void usb_board_stop(void)
COBJS-$(CONFIG_USB_STORAGE) += usb_storage.o
endif
COBJS-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o
+COBJS-$(CONFIG_CMD_THOR_DOWNLOAD) += cmd_thordown.o
COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o
COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o
COBJS-$(CONFIG_CMD_SPL) += cmd_spl.o
#include <common.h>
#include <dfu.h>
#include <g_dnl.h>
+#include <usb.h>
static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+ if (argc < 4)
+ return CMD_RET_USAGE;
+
+ char *usb_controller = argv[1];
+ char *interface = argv[2];
+ char *devstring = argv[3];
+
char *s = "dfu";
int ret, i = 0;
- if (argc < 3)
- return CMD_RET_USAGE;
-
- ret = dfu_init_env_entities(argv[1], simple_strtoul(argv[2], NULL, 10));
+ ret = dfu_init_env_entities(interface, simple_strtoul(devstring,
+ NULL, 10));
if (ret)
return ret;
- if (argc > 3 && strcmp(argv[3], "list") == 0) {
+ if (argc > 4 && strcmp(argv[4], "list") == 0) {
dfu_show_entities();
goto done;
}
-#ifdef CONFIG_TRATS
- board_usb_init();
-#endif
+ int controller_index = simple_strtoul(usb_controller, NULL, 0);
+ board_usb_init(controller_index, USB_INIT_DEVICE);
g_dnl_register(s);
while (1) {
U_BOOT_CMD(dfu, CONFIG_SYS_MAXARGS, 1, do_dfu,
"Device Firmware Upgrade",
- "<interface> <dev> [list]\n"
- " - device firmware upgrade on a device <dev>\n"
- " attached to interface <interface>\n"
- " [list] - list available alt settings"
+ "<USB_controller> <interface> <dev> [list]\n"
+ " - device firmware upgrade via <USB_controller>\n"
+ " on device <dev>, attached to interface\n"
+ " <interface>\n"
+ " [list] - list available alt settings\n"
);
--- /dev/null
+/*
+ * cmd_thordown.c -- USB TIZEN "THOR" Downloader gadget
+ *
+ * Copyright (C) 2013 Lukasz Majewski <l.majewski@samsung.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <thor.h>
+#include <dfu.h>
+#include <g_dnl.h>
+#include <usb.h>
+
+int do_thor_down(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc < 4)
+ return CMD_RET_USAGE;
+
+ char *usb_controller = argv[1];
+ char *interface = argv[2];
+ char *devstring = argv[3];
+
+ const char *s = "thor";
+ int ret;
+
+ puts("TIZEN \"THOR\" Downloader\n");
+
+ ret = dfu_init_env_entities(interface, simple_strtoul(devstring,
+ NULL, 10));
+ if (ret)
+ return ret;
+
+ int controller_index = simple_strtoul(usb_controller, NULL, 0);
+ ret = board_usb_init(controller_index, USB_INIT_DEVICE);
+ if (ret) {
+ error("USB init failed: %d", ret);
+ ret = CMD_RET_FAILURE;
+ goto exit;
+ }
+
+ g_dnl_register(s);
+
+ ret = thor_init();
+ if (ret) {
+ error("THOR DOWNLOAD failed: %d", ret);
+ ret = CMD_RET_FAILURE;
+ goto exit;
+ }
+
+ ret = thor_handle();
+ if (ret) {
+ error("THOR failed: %d", ret);
+ ret = CMD_RET_FAILURE;
+ goto exit;
+ }
+
+exit:
+ g_dnl_unregister();
+ dfu_free_entities();
+
+ return ret;
+}
+
+U_BOOT_CMD(thordown, CONFIG_SYS_MAXARGS, 1, do_thor_down,
+ "TIZEN \"THOR\" downloader",
+ "<USB_controller> <interface> <dev>\n"
+ " - device software upgrade via LTHOR TIZEN dowload\n"
+ " program via <USB_controller> on device <dev>,\n"
+ " attached to interface <interface>\n"
+);
#include <common.h>
#include <command.h>
#include <g_dnl.h>
+#include <usb.h>
#include <usb_mass_storage.h>
int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
- char *ep;
- unsigned int dev_num = 0, offset = 0, part_size = 0;
- int rc;
+ if (argc < 3)
+ return CMD_RET_USAGE;
- struct ums_board_info *ums_info;
- static char *s = "ums";
-
- if (argc < 2) {
- printf("usage: ums <dev> - e.g. ums 0\n");
- return 0;
- }
-
- dev_num = (int)simple_strtoul(argv[1], &ep, 16);
+ const char *usb_controller = argv[1];
+ const char *mmc_devstring = argv[2];
+ unsigned int dev_num = (unsigned int)(simple_strtoul(mmc_devstring,
+ NULL, 0));
if (dev_num) {
- puts("\nSet eMMC device to 0! - e.g. ums 0\n");
+ error("Set eMMC device to 0! - e.g. ums 0");
goto fail;
}
- board_usb_init();
- ums_info = board_ums_init(dev_num, offset, part_size);
+ unsigned int controller_index = (unsigned int)(simple_strtoul(
+ usb_controller, NULL, 0));
+ if (board_usb_init(controller_index, USB_INIT_DEVICE)) {
+ error("Couldn't init USB controller.");
+ goto fail;
+ }
+ struct ums_board_info *ums_info = board_ums_init(dev_num, 0, 0);
if (!ums_info) {
- printf("MMC: %d -> NOT available\n", dev_num);
+ error("MMC: %d -> NOT available", dev_num);
goto fail;
}
- rc = fsg_init(ums_info);
+
+ int rc = fsg_init(ums_info);
if (rc) {
- printf("cmd ums: fsg_init failed\n");
+ error("fsg_init failed");
goto fail;
}
- g_dnl_register(s);
+ g_dnl_register("ums");
while (1) {
/* Handle control-c and timeouts */
if (ctrlc()) {
- printf("The remote end did not respond in time.\n");
+ error("The remote end did not respond in time.");
goto exit;
}
+
usb_gadget_handle_interrupts();
/* Check if USB cable has been detached */
if (fsg_main_thread(NULL) == EIO)
U_BOOT_CMD(ums, CONFIG_SYS_MAXARGS, 1, do_usb_mass_storage,
"Use the UMS [User Mass Storage]",
- "ums - User Mass Storage Gadget"
+ "<USB_controller> <mmc_dev>"
);
#include <linux/ctype.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
+#include <compiler.h>
#include <usb.h>
#ifdef CONFIG_4xx
for (i = 0; i < CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
/* init low_level USB */
printf("USB%d: ", i);
- if (usb_lowlevel_init(i, &ctrl)) {
+ if (usb_lowlevel_init(i, USB_INIT_HOST, &ctrl)) {
puts("lowlevel init failed\n");
continue;
}
usb_dev[dev_index].devnum = -1;
}
+/*
+ * XHCI issues Enable Slot command and thereafter
+ * allocates device contexts. Provide a weak alias
+ * function for the purpose, so that XHCI overrides it
+ * and EHCI/OHCI just work out of the box.
+ */
+__weak int usb_alloc_device(struct usb_device *udev)
+{
+ return 0;
+}
/*
* By the time we get here, the device has gotten a new device ID
* and is in the default state. We need to identify the thing and
int tmp;
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, tmpbuf, USB_BUFSIZ);
+ /*
+ * Allocate usb 3.0 device context.
+ * USB 3.0 (xHCI) protocol tries to allocate device slot
+ * and related data structures first. This call does that.
+ * Refer to sec 4.3.2 in xHCI spec rev1.0
+ */
+ if (usb_alloc_device(dev)) {
+ printf("Cannot allocate device context to get SLOT_ID\n");
+ return -1;
+ }
+
/* We still haven't set the Address yet */
addr = dev->devnum;
dev->devnum = 0;
* http://sourceforge.net/mailarchive/forum.php?
* thread_id=5729457&forum_id=5398
*/
- struct usb_device_descriptor *desc;
+ __maybe_unused struct usb_device_descriptor *desc;
int port = -1;
struct usb_device *parent = dev->parent;
unsigned short portstatus;
dev->epmaxpacketin[0] = 64;
dev->epmaxpacketout[0] = 64;
+ /*
+ * XHCI needs to issue a Address device command to setup
+ * proper device context structures, before it can interact
+ * with the device. So a get_descriptor will fail before any
+ * of that is done for XHCI unlike EHCI.
+ */
+#ifndef CONFIG_USB_XHCI
err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, 64);
if (err < 0) {
debug("usb_new_device: usb_get_descriptor() failed\n");
* to differentiate between HUB and DEVICE.
*/
dev->descriptor.bDeviceClass = desc->bDeviceClass;
+#endif
- /* find the port number we're at */
if (parent) {
int j;
+ /* find the port number we're at */
for (j = 0; j < parent->maxchild; j++) {
if (parent->children[j] == dev) {
port = j;
return 0;
}
+__weak
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return 0;
+}
/* EOF */
static unsigned char *dfu_buf;
static unsigned long dfu_buf_size = CONFIG_SYS_DFU_DATA_BUF_SIZE;
-static unsigned char *dfu_free_buf(void)
+unsigned char *dfu_free_buf(void)
{
free(dfu_buf);
dfu_buf = NULL;
return dfu_buf;
}
-static unsigned char *dfu_get_buf(void)
+unsigned char *dfu_get_buf(void)
{
char *s;
}
static int dfu_fill_entity(struct dfu_entity *dfu, char *s, int alt,
- char *interface, int num)
+ char *interface, int num)
{
char *st;
return NULL;
}
+
+int dfu_get_alt(char *name)
+{
+ struct dfu_entity *dfu;
+
+ list_for_each_entry(dfu, &dfu_list, list) {
+ if (!strncmp(dfu->name, name, strlen(dfu->name)))
+ return dfu->alt;
+ }
+
+ return -ENODEV;
+}
}
#endif
+#ifdef CONFIG_PALMAS_USB_SS_PWR
+/**
+ * @brief palmas_enable_ss_ldo - Configure EVM board specific configurations
+ * for the USB Super speed SMPS10 regulator.
+ *
+ * @return 0
+ */
+int palmas_enable_ss_ldo(void)
+{
+ /* Enable smps10 regulator */
+ return palmas_i2c_write_u8(TWL603X_CHIP_P1, SMPS10_CTRL,
+ SMPS10_MODE_ACTIVE_D);
+}
+#endif
+
/*
* Enable/disable back-up battery (or super cap) charging on TWL6035/37.
* Please use defined BB_xxx values.
#include <usb/mpc8xx_udc.h>
#elif defined(CONFIG_OMAP1510)
#include <usb/omap1510_udc.h>
-#elif defined(CONFIG_MUSB_UDC)
-#include <usb/musb_udc.h>
#elif defined(CONFIG_CPU_PXA27X)
#include <usb/pxa27x_udc.h>
#elif defined(CONFIG_DW_UDC)
#include <usb/mv_udc.h>
#endif
+#include <usb/udc.h>
#include <version.h>
/* If no VendorID/ProductID is defined in config.h, pretend to be Linux
/* SMSC LAN95xx based USB 2.0 Ethernet Devices */
+/* LED defines */
+#define LED_GPIO_CFG (0x24)
+#define LED_GPIO_CFG_SPD_LED (0x01000000)
+#define LED_GPIO_CFG_LNK_LED (0x00100000)
+#define LED_GPIO_CFG_FDX_LED (0x00010000)
+
/* Tx command words */
#define TX_CMD_A_FIRST_SEG_ 0x00002000
#define TX_CMD_A_LAST_SEG_ 0x00001000
return ret;
debug("ID_REV = 0x%08x\n", read_buf);
+ /* Configure GPIO pins as LED outputs */
+ write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
+ LED_GPIO_CFG_FDX_LED;
+ ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
+ if (ret < 0)
+ return ret;
+ debug("LED_GPIO_CFG set\n");
+
/* Init Tx */
write_buf = 0;
ret = smsc95xx_write_reg(dev, FLOW, write_buf);
COBJS-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o
COBJS-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o
COBJS-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
+COBJS-$(CONFIG_THOR_FUNCTION) += f_thor.o
COBJS-$(CONFIG_USBDOWNLOAD_GADGET) += g_dnl.o
COBJS-$(CONFIG_DFU_FUNCTION) += f_dfu.o
COBJS-$(CONFIG_USB_GADGET_MASS_STORAGE) += f_mass_storage.o
#include <usbdevice.h>
#include "ep0.h"
#include <usb/designware_udc.h>
+#include <usb/udc.h>
#include <asm/arch/hardware.h>
#define UDC_INIT_MDELAY 80 /* Device settle delay */
.bEndpointAddress = USB_DIR_IN,
.bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = __constant_cpu_to_le16(64),
};
static struct usb_endpoint_descriptor
.bEndpointAddress = USB_DIR_OUT,
.bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = __constant_cpu_to_le16(64),
};
static const struct usb_descriptor_header *fs_eth_function[11] = {
*/
debug("%s\n", __func__);
+ if (!req)
+ return -EINVAL;
size = (ETHER_HDR_SIZE + dev->mtu + RX_EXTRA);
size += dev->out_ep->maxpacket - 1;
--- /dev/null
+/*
+ * f_thor.c -- USB TIZEN THOR Downloader gadget function
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * Based on code from:
+ * git://review.tizen.org/kernel/u-boot
+ *
+ * Developed by:
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Sanghee Kim <sh0130.kim@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <errno.h>
+#include <common.h>
+#include <malloc.h>
+#include <version.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/composite.h>
+#include <linux/usb/cdc.h>
+#include <g_dnl.h>
+#include <dfu.h>
+
+#include "f_thor.h"
+
+static void thor_tx_data(unsigned char *data, int len);
+static void thor_set_dma(void *addr, int len);
+static int thor_rx_data(void);
+
+static struct f_thor *thor_func;
+static inline struct f_thor *func_to_thor(struct usb_function *f)
+{
+ return container_of(f, struct f_thor, usb_function);
+}
+
+DEFINE_CACHE_ALIGN_BUFFER(unsigned char, thor_tx_data_buf,
+ sizeof(struct rsp_box));
+DEFINE_CACHE_ALIGN_BUFFER(unsigned char, thor_rx_data_buf,
+ sizeof(struct rqt_box));
+
+/* ********************************************************** */
+/* THOR protocol - transmission handling */
+/* ********************************************************** */
+DEFINE_CACHE_ALIGN_BUFFER(char, f_name, F_NAME_BUF_SIZE);
+static unsigned long long int thor_file_size;
+static int alt_setting_num;
+
+static void send_rsp(const struct rsp_box *rsp)
+{
+ memcpy(thor_tx_data_buf, rsp, sizeof(struct rsp_box));
+ thor_tx_data(thor_tx_data_buf, sizeof(struct rsp_box));
+
+ debug("-RSP: %d, %d\n", rsp->rsp, rsp->rsp_data);
+}
+
+static void send_data_rsp(s32 ack, s32 count)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct data_rsp_box, rsp,
+ sizeof(struct data_rsp_box));
+
+ rsp->ack = ack;
+ rsp->count = count;
+
+ memcpy(thor_tx_data_buf, rsp, sizeof(struct data_rsp_box));
+ thor_tx_data(thor_tx_data_buf, sizeof(struct data_rsp_box));
+
+ debug("-DATA RSP: %d, %d\n", ack, count);
+}
+
+static int process_rqt_info(const struct rqt_box *rqt)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct rsp_box, rsp, sizeof(struct rsp_box));
+ memset(rsp, 0, sizeof(struct rsp_box));
+
+ rsp->rsp = rqt->rqt;
+ rsp->rsp_data = rqt->rqt_data;
+
+ switch (rqt->rqt_data) {
+ case RQT_INFO_VER_PROTOCOL:
+ rsp->int_data[0] = VER_PROTOCOL_MAJOR;
+ rsp->int_data[1] = VER_PROTOCOL_MINOR;
+ break;
+ case RQT_INIT_VER_HW:
+ snprintf(rsp->str_data[0], sizeof(rsp->str_data[0]),
+ "%x", checkboard());
+ break;
+ case RQT_INIT_VER_BOOT:
+ sprintf(rsp->str_data[0], "%s", U_BOOT_VERSION);
+ break;
+ case RQT_INIT_VER_KERNEL:
+ sprintf(rsp->str_data[0], "%s", "k unknown");
+ break;
+ case RQT_INIT_VER_PLATFORM:
+ sprintf(rsp->str_data[0], "%s", "p unknown");
+ break;
+ case RQT_INIT_VER_CSC:
+ sprintf(rsp->str_data[0], "%s", "c unknown");
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ send_rsp(rsp);
+ return true;
+}
+
+static int process_rqt_cmd(const struct rqt_box *rqt)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct rsp_box, rsp, sizeof(struct rsp_box));
+ memset(rsp, 0, sizeof(struct rsp_box));
+
+ rsp->rsp = rqt->rqt;
+ rsp->rsp_data = rqt->rqt_data;
+
+ switch (rqt->rqt_data) {
+ case RQT_CMD_REBOOT:
+ debug("TARGET RESET\n");
+ send_rsp(rsp);
+ g_dnl_unregister();
+ dfu_free_entities();
+ run_command("reset", 0);
+ break;
+ case RQT_CMD_POWEROFF:
+ case RQT_CMD_EFSCLEAR:
+ send_rsp(rsp);
+ default:
+ printf("Command not supported -> cmd: %d\n", rqt->rqt_data);
+ return -EINVAL;
+ }
+
+ return true;
+}
+
+static long long int download_head(unsigned long long total,
+ unsigned int packet_size,
+ long long int *left,
+ int *cnt)
+{
+ long long int rcv_cnt = 0, left_to_rcv, ret_rcv;
+ void *transfer_buffer = dfu_get_buf();
+ void *buf = transfer_buffer;
+ int usb_pkt_cnt = 0, ret;
+
+ /*
+ * Files smaller than THOR_STORE_UNIT_SIZE (now 32 MiB) are stored on
+ * the medium.
+ * The packet response is sent on the purpose after successful data
+ * chunk write. There is a room for improvement when asynchronous write
+ * is performed.
+ */
+ while (total - rcv_cnt >= packet_size) {
+ thor_set_dma(buf, packet_size);
+ buf += packet_size;
+ ret_rcv = thor_rx_data();
+ if (ret_rcv < 0)
+ return ret_rcv;
+ rcv_cnt += ret_rcv;
+ debug("%d: RCV data count: %llu cnt: %d\n", usb_pkt_cnt,
+ rcv_cnt, *cnt);
+
+ if ((rcv_cnt % THOR_STORE_UNIT_SIZE) == 0) {
+ ret = dfu_write(dfu_get_entity(alt_setting_num),
+ transfer_buffer, THOR_STORE_UNIT_SIZE,
+ (*cnt)++);
+ if (ret) {
+ error("DFU write failed [%d] cnt: %d",
+ ret, *cnt);
+ return ret;
+ }
+ buf = transfer_buffer;
+ }
+ send_data_rsp(0, ++usb_pkt_cnt);
+ }
+
+ /* Calculate the amount of data to arrive from PC (in bytes) */
+ left_to_rcv = total - rcv_cnt;
+
+ /*
+ * Calculate number of data already received. but not yet stored
+ * on the medium (they are smaller than THOR_STORE_UNIT_SIZE)
+ */
+ *left = left_to_rcv + buf - transfer_buffer;
+ debug("%s: left: %llu left_to_rcv: %llu buf: 0x%p\n", __func__,
+ *left, left_to_rcv, buf);
+
+ if (left_to_rcv) {
+ thor_set_dma(buf, packet_size);
+ ret_rcv = thor_rx_data();
+ if (ret_rcv < 0)
+ return ret_rcv;
+ rcv_cnt += ret_rcv;
+ send_data_rsp(0, ++usb_pkt_cnt);
+ }
+
+ debug("%s: %llu total: %llu cnt: %d\n", __func__, rcv_cnt, total, *cnt);
+
+ return rcv_cnt;
+}
+
+static int download_tail(long long int left, int cnt)
+{
+ void *transfer_buffer = dfu_get_buf();
+ int ret;
+
+ debug("%s: left: %llu cnt: %d\n", __func__, left, cnt);
+
+ if (left) {
+ ret = dfu_write(dfu_get_entity(alt_setting_num),
+ transfer_buffer, left, cnt++);
+ if (ret) {
+ error("DFU write failed [%d]: left: %llu", ret, left);
+ return ret;
+ }
+ }
+
+ /*
+ * To store last "packet" DFU storage backend requires dfu_write with
+ * size parameter equal to 0
+ *
+ * This also frees memory malloc'ed by dfu_get_buf(), so no explicit
+ * need fo call dfu_free_buf() is needed.
+ */
+ ret = dfu_write(dfu_get_entity(alt_setting_num),
+ transfer_buffer, 0, cnt);
+ if (ret)
+ error("DFU write failed [%d] cnt: %d", ret, cnt);
+
+ return ret;
+}
+
+static long long int process_rqt_download(const struct rqt_box *rqt)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct rsp_box, rsp, sizeof(struct rsp_box));
+ static long long int left, ret_head;
+ int file_type, ret = 0;
+ static int cnt;
+
+ memset(rsp, 0, sizeof(struct rsp_box));
+ rsp->rsp = rqt->rqt;
+ rsp->rsp_data = rqt->rqt_data;
+
+ switch (rqt->rqt_data) {
+ case RQT_DL_INIT:
+ thor_file_size = rqt->int_data[0];
+ debug("INIT: total %d bytes\n", rqt->int_data[0]);
+ break;
+ case RQT_DL_FILE_INFO:
+ file_type = rqt->int_data[0];
+ if (file_type == FILE_TYPE_PIT) {
+ puts("PIT table file - not supported\n");
+ rsp->ack = -ENOTSUPP;
+ ret = rsp->ack;
+ break;
+ }
+
+ thor_file_size = rqt->int_data[1];
+ memcpy(f_name, rqt->str_data[0], F_NAME_BUF_SIZE);
+
+ debug("INFO: name(%s, %d), size(%llu), type(%d)\n",
+ f_name, 0, thor_file_size, file_type);
+
+ rsp->int_data[0] = THOR_PACKET_SIZE;
+
+ alt_setting_num = dfu_get_alt(f_name);
+ if (alt_setting_num < 0) {
+ error("Alt setting [%d] to write not found!",
+ alt_setting_num);
+ rsp->ack = -ENODEV;
+ ret = rsp->ack;
+ }
+ break;
+ case RQT_DL_FILE_START:
+ send_rsp(rsp);
+ ret_head = download_head(thor_file_size, THOR_PACKET_SIZE,
+ &left, &cnt);
+ if (ret_head < 0) {
+ left = 0;
+ cnt = 0;
+ }
+ return ret_head;
+ case RQT_DL_FILE_END:
+ debug("DL FILE_END\n");
+ rsp->ack = download_tail(left, cnt);
+ ret = rsp->ack;
+ left = 0;
+ cnt = 0;
+ break;
+ case RQT_DL_EXIT:
+ debug("DL EXIT\n");
+ break;
+ default:
+ error("Operation not supported: %d", rqt->rqt_data);
+ ret = -ENOTSUPP;
+ }
+
+ send_rsp(rsp);
+ return ret;
+}
+
+static int process_data(void)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct rqt_box, rqt, sizeof(struct rqt_box));
+ int ret = -EINVAL;
+
+ memset(rqt, 0, sizeof(rqt));
+ memcpy(rqt, thor_rx_data_buf, sizeof(struct rqt_box));
+
+ debug("+RQT: %d, %d\n", rqt->rqt, rqt->rqt_data);
+
+ switch (rqt->rqt) {
+ case RQT_INFO:
+ ret = process_rqt_info(rqt);
+ break;
+ case RQT_CMD:
+ ret = process_rqt_cmd(rqt);
+ break;
+ case RQT_DL:
+ ret = (int) process_rqt_download(rqt);
+ break;
+ case RQT_UL:
+ puts("RQT: UPLOAD not supported!\n");
+ break;
+ default:
+ error("unknown request (%d)", rqt->rqt);
+ }
+
+ return ret;
+}
+
+/* ********************************************************** */
+/* THOR USB Function */
+/* ********************************************************** */
+
+static inline struct usb_endpoint_descriptor *
+ep_desc(struct usb_gadget *g, struct usb_endpoint_descriptor *hs,
+ struct usb_endpoint_descriptor *fs)
+{
+ if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH)
+ return hs;
+ return fs;
+}
+
+static struct usb_interface_descriptor thor_downloader_intf_data = {
+ .bLength = sizeof(thor_downloader_intf_data),
+ .bDescriptorType = USB_DT_INTERFACE,
+
+ .bNumEndpoints = 2,
+ .bInterfaceClass = USB_CLASS_CDC_DATA,
+};
+
+static struct usb_endpoint_descriptor fs_in_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+};
+
+static struct usb_endpoint_descriptor fs_out_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+
+ .bEndpointAddress = USB_DIR_OUT,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+};
+
+/* CDC configuration */
+static struct usb_interface_descriptor thor_downloader_intf_int = {
+ .bLength = sizeof(thor_downloader_intf_int),
+ .bDescriptorType = USB_DT_INTERFACE,
+
+ .bNumEndpoints = 1,
+ .bInterfaceClass = USB_CLASS_COMM,
+ /* 0x02 Abstract Line Control Model */
+ .bInterfaceSubClass = USB_CDC_SUBCLASS_ACM,
+ /* 0x01 Common AT commands */
+ .bInterfaceProtocol = USB_CDC_ACM_PROTO_AT_V25TER,
+};
+
+static struct usb_cdc_header_desc thor_downloader_cdc_header = {
+ .bLength = sizeof(thor_downloader_cdc_header),
+ .bDescriptorType = 0x24, /* CS_INTERFACE */
+ .bDescriptorSubType = 0x00,
+ .bcdCDC = 0x0110,
+};
+
+static struct usb_cdc_call_mgmt_descriptor thor_downloader_cdc_call = {
+ .bLength = sizeof(thor_downloader_cdc_call),
+ .bDescriptorType = 0x24, /* CS_INTERFACE */
+ .bDescriptorSubType = 0x01,
+ .bmCapabilities = 0x00,
+ .bDataInterface = 0x01,
+};
+
+static struct usb_cdc_acm_descriptor thor_downloader_cdc_abstract = {
+ .bLength = sizeof(thor_downloader_cdc_abstract),
+ .bDescriptorType = 0x24, /* CS_INTERFACE */
+ .bDescriptorSubType = 0x02,
+ .bmCapabilities = 0x00,
+};
+
+static struct usb_cdc_union_desc thor_downloader_cdc_union = {
+ .bLength = sizeof(thor_downloader_cdc_union),
+ .bDescriptorType = 0x24, /* CS_INTERFACE */
+ .bDescriptorSubType = USB_CDC_UNION_TYPE,
+};
+
+static struct usb_endpoint_descriptor fs_int_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+
+ .bEndpointAddress = 3 | USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_INT,
+ .wMaxPacketSize = __constant_cpu_to_le16(16),
+
+ .bInterval = 0x9,
+};
+
+static struct usb_interface_assoc_descriptor
+thor_iad_descriptor = {
+ .bLength = sizeof(thor_iad_descriptor),
+ .bDescriptorType = USB_DT_INTERFACE_ASSOCIATION,
+
+ .bFirstInterface = 0,
+ .bInterfaceCount = 2, /* control + data */
+ .bFunctionClass = USB_CLASS_COMM,
+ .bFunctionSubClass = USB_CDC_SUBCLASS_ACM,
+ .bFunctionProtocol = USB_CDC_PROTO_NONE,
+};
+
+static struct usb_endpoint_descriptor hs_in_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = __constant_cpu_to_le16(512),
+};
+
+static struct usb_endpoint_descriptor hs_out_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = __constant_cpu_to_le16(512),
+};
+
+static struct usb_endpoint_descriptor hs_int_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+
+ .bmAttributes = USB_ENDPOINT_XFER_INT,
+ .wMaxPacketSize = __constant_cpu_to_le16(16),
+
+ .bInterval = 0x9,
+};
+
+static struct usb_qualifier_descriptor dev_qualifier = {
+ .bLength = sizeof(dev_qualifier),
+ .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
+
+ .bcdUSB = __constant_cpu_to_le16(0x0200),
+ .bDeviceClass = USB_CLASS_VENDOR_SPEC,
+
+ .bNumConfigurations = 2,
+};
+
+/*
+ * This attribute vendor descriptor is necessary for correct operation with
+ * Windows version of THOR download program
+ *
+ * It prevents windows driver from sending zero lenght packet (ZLP) after
+ * each THOR_PACKET_SIZE. This assures consistent behaviour with libusb
+ */
+static struct usb_cdc_attribute_vendor_descriptor thor_downloader_cdc_av = {
+ .bLength = sizeof(thor_downloader_cdc_av),
+ .bDescriptorType = 0x24,
+ .bDescriptorSubType = 0x80,
+ .DAUType = 0x0002,
+ .DAULength = 0x0001,
+ .DAUValue = 0x00,
+};
+
+static const struct usb_descriptor_header *hs_thor_downloader_function[] = {
+ (struct usb_descriptor_header *)&thor_iad_descriptor,
+
+ (struct usb_descriptor_header *)&thor_downloader_intf_int,
+ (struct usb_descriptor_header *)&thor_downloader_cdc_header,
+ (struct usb_descriptor_header *)&thor_downloader_cdc_call,
+ (struct usb_descriptor_header *)&thor_downloader_cdc_abstract,
+ (struct usb_descriptor_header *)&thor_downloader_cdc_union,
+ (struct usb_descriptor_header *)&hs_int_desc,
+
+ (struct usb_descriptor_header *)&thor_downloader_intf_data,
+ (struct usb_descriptor_header *)&thor_downloader_cdc_av,
+ (struct usb_descriptor_header *)&hs_in_desc,
+ (struct usb_descriptor_header *)&hs_out_desc,
+ NULL,
+};
+
+/*-------------------------------------------------------------------------*/
+static struct usb_request *alloc_ep_req(struct usb_ep *ep, unsigned length)
+{
+ struct usb_request *req;
+
+ req = usb_ep_alloc_request(ep, 0);
+ if (!req)
+ return req;
+
+ req->length = length;
+ req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, length);
+ if (!req->buf) {
+ usb_ep_free_request(ep, req);
+ req = NULL;
+ }
+
+ return req;
+}
+
+static int thor_rx_data(void)
+{
+ struct thor_dev *dev = thor_func->dev;
+ int data_to_rx, tmp, status;
+
+ data_to_rx = dev->out_req->length;
+ tmp = data_to_rx;
+ do {
+ dev->out_req->length = data_to_rx;
+ debug("dev->out_req->length:%d dev->rxdata:%d\n",
+ dev->out_req->length, dev->rxdata);
+
+ status = usb_ep_queue(dev->out_ep, dev->out_req, 0);
+ if (status) {
+ error("kill %s: resubmit %d bytes --> %d",
+ dev->out_ep->name, dev->out_req->length, status);
+ usb_ep_set_halt(dev->out_ep);
+ return -EAGAIN;
+ }
+
+ while (!dev->rxdata) {
+ usb_gadget_handle_interrupts();
+ if (ctrlc())
+ return -1;
+ }
+ dev->rxdata = 0;
+ data_to_rx -= dev->out_req->actual;
+ } while (data_to_rx);
+
+ return tmp;
+}
+
+static void thor_tx_data(unsigned char *data, int len)
+{
+ struct thor_dev *dev = thor_func->dev;
+ unsigned char *ptr = dev->in_req->buf;
+ int status;
+
+ memset(ptr, 0, len);
+ memcpy(ptr, data, len);
+
+ dev->in_req->length = len;
+
+ debug("%s: dev->in_req->length:%d to_cpy:%d\n", __func__,
+ dev->in_req->length, sizeof(data));
+
+ status = usb_ep_queue(dev->in_ep, dev->in_req, 0);
+ if (status) {
+ error("kill %s: resubmit %d bytes --> %d",
+ dev->in_ep->name, dev->in_req->length, status);
+ usb_ep_set_halt(dev->in_ep);
+ }
+
+ /* Wait until tx interrupt received */
+ while (!dev->txdata)
+ usb_gadget_handle_interrupts();
+
+ dev->txdata = 0;
+}
+
+static void thor_rx_tx_complete(struct usb_ep *ep, struct usb_request *req)
+{
+ struct thor_dev *dev = thor_func->dev;
+ int status = req->status;
+
+ debug("%s: ep_ptr:%p, req_ptr:%p\n", __func__, ep, req);
+ switch (status) {
+ case 0:
+ if (ep == dev->out_ep)
+ dev->rxdata = 1;
+ else
+ dev->txdata = 1;
+
+ break;
+
+ /* this endpoint is normally active while we're configured */
+ case -ECONNABORTED: /* hardware forced ep reset */
+ case -ECONNRESET: /* request dequeued */
+ case -ESHUTDOWN: /* disconnect from host */
+ case -EREMOTEIO: /* short read */
+ case -EOVERFLOW:
+ error("ERROR:%d", status);
+ break;
+ }
+
+ debug("%s complete --> %d, %d/%d\n", ep->name,
+ status, req->actual, req->length);
+}
+
+static struct usb_request *thor_start_ep(struct usb_ep *ep)
+{
+ struct usb_request *req;
+
+ req = alloc_ep_req(ep, ep->maxpacket);
+ debug("%s: ep:%p req:%p\n", __func__, ep, req);
+
+ if (!req)
+ return NULL;
+
+ memset(req->buf, 0, req->length);
+ req->complete = thor_rx_tx_complete;
+
+ memset(req->buf, 0x55, req->length);
+
+ return req;
+}
+
+static void thor_setup_complete(struct usb_ep *ep, struct usb_request *req)
+{
+ if (req->status || req->actual != req->length)
+ debug("setup complete --> %d, %d/%d\n",
+ req->status, req->actual, req->length);
+}
+
+static int
+thor_func_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl)
+{
+ struct thor_dev *dev = thor_func->dev;
+ struct usb_request *req = dev->req;
+ struct usb_gadget *gadget = dev->gadget;
+ int value = 0;
+
+ u16 len = le16_to_cpu(ctrl->wLength);
+
+ debug("Req_Type: 0x%x Req: 0x%x wValue: 0x%x wIndex: 0x%x wLen: 0x%x\n",
+ ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, ctrl->wIndex,
+ ctrl->wLength);
+
+ switch (ctrl->bRequest) {
+ case USB_CDC_REQ_SET_CONTROL_LINE_STATE:
+ value = 0;
+ break;
+ case USB_CDC_REQ_SET_LINE_CODING:
+ value = len;
+ /* Line Coding set done = configuration done */
+ thor_func->dev->configuration_done = 1;
+ break;
+
+ default:
+ error("thor_setup: unknown request: %d", ctrl->bRequest);
+ }
+
+ if (value >= 0) {
+ req->length = value;
+ req->zero = value < len;
+ value = usb_ep_queue(gadget->ep0, req, 0);
+ if (value < 0) {
+ debug("%s: ep_queue: %d\n", __func__, value);
+ req->status = 0;
+ }
+ }
+
+ return value;
+}
+
+/* Specific to the THOR protocol */
+static void thor_set_dma(void *addr, int len)
+{
+ struct thor_dev *dev = thor_func->dev;
+
+ debug("in_req:%p, out_req:%p\n", dev->in_req, dev->out_req);
+ debug("addr:%p, len:%d\n", addr, len);
+
+ dev->out_req->buf = addr;
+ dev->out_req->length = len;
+}
+
+int thor_init(void)
+{
+ struct thor_dev *dev = thor_func->dev;
+
+ /* Wait for a device enumeration and configuration settings */
+ debug("THOR enumeration/configuration setting....\n");
+ while (!dev->configuration_done)
+ usb_gadget_handle_interrupts();
+
+ thor_set_dma(thor_rx_data_buf, strlen("THOR"));
+ /* detect the download request from Host PC */
+ if (thor_rx_data() < 0) {
+ printf("%s: Data not received!\n", __func__);
+ return -1;
+ }
+
+ if (!strncmp((char *)thor_rx_data_buf, "THOR", strlen("THOR"))) {
+ puts("Download request from the Host PC\n");
+ udelay(30 * 1000); /* 30 ms */
+
+ strcpy((char *)thor_tx_data_buf, "ROHT");
+ thor_tx_data(thor_tx_data_buf, strlen("ROHT"));
+ } else {
+ puts("Wrong reply information\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+int thor_handle(void)
+{
+ int ret;
+
+ /* receive the data from Host PC */
+ while (1) {
+ thor_set_dma(thor_rx_data_buf, sizeof(struct rqt_box));
+ ret = thor_rx_data();
+
+ if (ret > 0) {
+ ret = process_data();
+ if (ret < 0)
+ return ret;
+ } else {
+ printf("%s: No data received!\n", __func__);
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static int thor_func_bind(struct usb_configuration *c, struct usb_function *f)
+{
+ struct usb_gadget *gadget = c->cdev->gadget;
+ struct f_thor *f_thor = func_to_thor(f);
+ struct thor_dev *dev;
+ struct usb_ep *ep;
+ int status;
+
+ thor_func = f_thor;
+ dev = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*dev));
+ if (!dev)
+ return -ENOMEM;
+
+ memset(dev, 0, sizeof(*dev));
+ dev->gadget = gadget;
+ f_thor->dev = dev;
+
+ debug("%s: usb_configuration: 0x%p usb_function: 0x%p\n",
+ __func__, c, f);
+ debug("f_thor: 0x%p thor: 0x%p\n", f_thor, dev);
+
+ /* EP0 */
+ /* preallocate control response and buffer */
+ dev->req = usb_ep_alloc_request(gadget->ep0, 0);
+ if (!dev->req) {
+ status = -ENOMEM;
+ goto fail;
+ }
+ dev->req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
+ gadget->ep0->maxpacket);
+ if (!dev->req->buf) {
+ status = -ENOMEM;
+ goto fail;
+ }
+
+ dev->req->complete = thor_setup_complete;
+
+ /* DYNAMIC interface numbers assignments */
+ status = usb_interface_id(c, f);
+
+ if (status < 0)
+ goto fail;
+
+ thor_downloader_intf_int.bInterfaceNumber = status;
+ thor_downloader_cdc_union.bMasterInterface0 = status;
+
+ status = usb_interface_id(c, f);
+
+ if (status < 0)
+ goto fail;
+
+ thor_downloader_intf_data.bInterfaceNumber = status;
+ thor_downloader_cdc_union.bSlaveInterface0 = status;
+
+ /* allocate instance-specific endpoints */
+ ep = usb_ep_autoconfig(gadget, &fs_in_desc);
+ if (!ep) {
+ status = -ENODEV;
+ goto fail;
+ }
+
+ if (gadget_is_dualspeed(gadget)) {
+ hs_in_desc.bEndpointAddress =
+ fs_in_desc.bEndpointAddress;
+ }
+
+ dev->in_ep = ep; /* Store IN EP for enabling @ setup */
+
+ ep = usb_ep_autoconfig(gadget, &fs_out_desc);
+ if (!ep) {
+ status = -ENODEV;
+ goto fail;
+ }
+
+ if (gadget_is_dualspeed(gadget))
+ hs_out_desc.bEndpointAddress =
+ fs_out_desc.bEndpointAddress;
+
+ dev->out_ep = ep; /* Store OUT EP for enabling @ setup */
+
+ ep = usb_ep_autoconfig(gadget, &fs_int_desc);
+ if (!ep) {
+ status = -ENODEV;
+ goto fail;
+ }
+
+ dev->int_ep = ep;
+
+ if (gadget_is_dualspeed(gadget)) {
+ hs_int_desc.bEndpointAddress =
+ fs_int_desc.bEndpointAddress;
+
+ f->hs_descriptors = (struct usb_descriptor_header **)
+ &hs_thor_downloader_function;
+
+ if (!f->hs_descriptors)
+ goto fail;
+ }
+
+ debug("%s: out_ep:%p out_req:%p\n", __func__,
+ dev->out_ep, dev->out_req);
+
+ return 0;
+
+ fail:
+ free(dev);
+ return status;
+}
+
+static void free_ep_req(struct usb_ep *ep, struct usb_request *req)
+{
+ free(req->buf);
+ usb_ep_free_request(ep, req);
+}
+
+static void thor_unbind(struct usb_configuration *c, struct usb_function *f)
+{
+ struct f_thor *f_thor = func_to_thor(f);
+ struct thor_dev *dev = f_thor->dev;
+
+ free(dev);
+ memset(thor_func, 0, sizeof(*thor_func));
+ thor_func = NULL;
+}
+
+static void thor_func_disable(struct usb_function *f)
+{
+ struct f_thor *f_thor = func_to_thor(f);
+ struct thor_dev *dev = f_thor->dev;
+
+ debug("%s:\n", __func__);
+
+ /* Avoid freeing memory when ep is still claimed */
+ if (dev->in_ep->driver_data) {
+ free_ep_req(dev->in_ep, dev->in_req);
+ usb_ep_disable(dev->in_ep);
+ dev->in_ep->driver_data = NULL;
+ }
+
+ if (dev->out_ep->driver_data) {
+ dev->out_req->buf = NULL;
+ usb_ep_free_request(dev->out_ep, dev->out_req);
+ usb_ep_disable(dev->out_ep);
+ dev->out_ep->driver_data = NULL;
+ }
+
+ if (dev->int_ep->driver_data) {
+ usb_ep_disable(dev->int_ep);
+ dev->int_ep->driver_data = NULL;
+ }
+}
+
+static int thor_eps_setup(struct usb_function *f)
+{
+ struct usb_composite_dev *cdev = f->config->cdev;
+ struct usb_gadget *gadget = cdev->gadget;
+ struct thor_dev *dev = thor_func->dev;
+ struct usb_endpoint_descriptor *d;
+ struct usb_request *req;
+ struct usb_ep *ep;
+ int result;
+
+ ep = dev->in_ep;
+ d = ep_desc(gadget, &hs_in_desc, &fs_in_desc);
+ debug("(d)bEndpointAddress: 0x%x\n", d->bEndpointAddress);
+
+ result = usb_ep_enable(ep, d);
+ if (result)
+ goto exit;
+
+ ep->driver_data = cdev; /* claim */
+ req = thor_start_ep(ep);
+ if (!req) {
+ usb_ep_disable(ep);
+ result = -EIO;
+ goto exit;
+ }
+
+ dev->in_req = req;
+ ep = dev->out_ep;
+ d = ep_desc(gadget, &hs_out_desc, &fs_out_desc);
+ debug("(d)bEndpointAddress: 0x%x\n", d->bEndpointAddress);
+
+ result = usb_ep_enable(ep, d);
+ if (result)
+ goto exit;
+
+ ep->driver_data = cdev; /* claim */
+ req = thor_start_ep(ep);
+ if (!req) {
+ usb_ep_disable(ep);
+ result = -EIO;
+ goto exit;
+ }
+
+ dev->out_req = req;
+ /* ACM control EP */
+ ep = dev->int_ep;
+ ep->driver_data = cdev; /* claim */
+
+ exit:
+ return result;
+}
+
+static int thor_func_set_alt(struct usb_function *f,
+ unsigned intf, unsigned alt)
+{
+ struct thor_dev *dev = thor_func->dev;
+ int result;
+
+ debug("%s: func: %s intf: %d alt: %d\n",
+ __func__, f->name, intf, alt);
+
+ switch (intf) {
+ case 0:
+ debug("ACM INTR interface\n");
+ break;
+ case 1:
+ debug("Communication Data interface\n");
+ result = thor_eps_setup(f);
+ if (result)
+ error("%s: EPs setup failed!", __func__);
+ dev->configuration_done = 1;
+ break;
+ }
+
+ return 0;
+}
+
+static int thor_func_init(struct usb_configuration *c)
+{
+ struct f_thor *f_thor;
+ int status;
+
+ debug("%s: cdev: 0x%p\n", __func__, c->cdev);
+
+ f_thor = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*f_thor));
+ if (!f_thor)
+ return -ENOMEM;
+
+ memset(f_thor, 0, sizeof(*f_thor));
+
+ f_thor->usb_function.name = "f_thor";
+ f_thor->usb_function.bind = thor_func_bind;
+ f_thor->usb_function.unbind = thor_unbind;
+ f_thor->usb_function.setup = thor_func_setup;
+ f_thor->usb_function.set_alt = thor_func_set_alt;
+ f_thor->usb_function.disable = thor_func_disable;
+
+ status = usb_add_function(c, &f_thor->usb_function);
+ if (status)
+ free(f_thor);
+
+ return status;
+}
+
+int thor_add(struct usb_configuration *c)
+{
+ debug("%s:\n", __func__);
+ return thor_func_init(c);
+}
--- /dev/null
+/*
+ * f_thor.h - USB TIZEN THOR - internal gadget definitions
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _USB_THOR_H_
+#define _USB_THOR_H_
+
+#include <linux/compiler.h>
+#include <asm/sizes.h>
+
+/* THOR Composite Gadget */
+#define STRING_MANUFACTURER_IDX 0
+#define STRING_PRODUCT_IDX 1
+#define STRING_SERIAL_IDX 2
+
+/* ********************************************************** */
+/* THOR protocol definitions */
+/* ********************************************************** */
+
+/*
+ * Attribute Vendor descriptor - necessary to prevent ZLP transmission
+ * from Windows XP HOST PC
+ */
+struct usb_cdc_attribute_vendor_descriptor {
+ __u8 bLength;
+ __u8 bDescriptorType;
+ __u8 bDescriptorSubType;
+ __u16 DAUType;
+ __u16 DAULength;
+ __u8 DAUValue;
+} __packed;
+
+#define VER_PROTOCOL_MAJOR 4
+#define VER_PROTOCOL_MINOR 0
+
+enum rqt {
+ RQT_INFO = 200,
+ RQT_CMD,
+ RQT_DL,
+ RQT_UL,
+};
+
+enum rqt_data {
+ /* RQT_INFO */
+ RQT_INFO_VER_PROTOCOL = 1,
+ RQT_INIT_VER_HW,
+ RQT_INIT_VER_BOOT,
+ RQT_INIT_VER_KERNEL,
+ RQT_INIT_VER_PLATFORM,
+ RQT_INIT_VER_CSC,
+
+ /* RQT_CMD */
+ RQT_CMD_REBOOT = 1,
+ RQT_CMD_POWEROFF,
+ RQT_CMD_EFSCLEAR,
+
+ /* RQT_DL */
+ RQT_DL_INIT = 1,
+ RQT_DL_FILE_INFO,
+ RQT_DL_FILE_START,
+ RQT_DL_FILE_END,
+ RQT_DL_EXIT,
+
+ /* RQT_UL */
+ RQT_UL_INIT = 1,
+ RQT_UL_START,
+ RQT_UL_END,
+ RQT_UL_EXIT,
+};
+
+struct rqt_box { /* total: 256B */
+ s32 rqt; /* request id */
+ s32 rqt_data; /* request data id */
+ s32 int_data[14]; /* int data */
+ char str_data[5][32]; /* string data */
+ char md5[32]; /* md5 checksum */
+} __packed;
+
+struct rsp_box { /* total: 128B */
+ s32 rsp; /* response id (= request id) */
+ s32 rsp_data; /* response data id */
+ s32 ack; /* ack */
+ s32 int_data[5]; /* int data */
+ char str_data[3][32]; /* string data */
+} __packed;
+
+struct data_rsp_box { /* total: 8B */
+ s32 ack; /* response id (= request id) */
+ s32 count; /* response data id */
+} __packed;
+
+enum {
+ FILE_TYPE_NORMAL,
+ FILE_TYPE_PIT,
+};
+
+struct thor_dev {
+ struct usb_gadget *gadget;
+ struct usb_request *req; /* EP0 -> control responses */
+
+ /* IN/OUT EP's and correspoinding requests */
+ struct usb_ep *in_ep, *out_ep, *int_ep;
+ struct usb_request *in_req, *out_req;
+
+ /* Control flow variables */
+ unsigned char configuration_done;
+ unsigned char rxdata;
+ unsigned char txdata;
+};
+
+struct f_thor {
+ struct usb_function usb_function;
+ struct thor_dev *dev;
+};
+
+#define F_NAME_BUF_SIZE 32
+#define THOR_PACKET_SIZE SZ_1M /* 1 MiB */
+#define THOR_STORE_UNIT_SIZE SZ_32M /* 32 MiB */
+#endif /* _USB_THOR_H_ */
#include <g_dnl.h>
#include <usb_mass_storage.h>
#include <dfu.h>
+#include <thor.h>
#include "gadget_chips.h"
#include "composite.c"
{
struct usb_gadget *gadget = cdev->gadget;
+ free(cdev->config);
+ cdev->config = NULL;
debug("%s: calling usb_gadget_disconnect for "
"controller '%s'\n", shortname, gadget->name);
usb_gadget_disconnect(gadget);
ret = dfu_add(c);
else if (!strcmp(s, "usb_dnl_ums"))
ret = fsg_add(c);
+ else if (!strcmp(s, "usb_dnl_thor"))
+ ret = thor_add(c);
return ret;
}
static int g_dnl_config_register(struct usb_composite_dev *cdev)
{
- static struct usb_configuration config = {
- .label = "usb_dnload",
- .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,
- .bConfigurationValue = CONFIGURATION_NUMBER,
- .iConfiguration = STRING_USBDOWN,
+ struct usb_configuration *config;
+ const char *name = "usb_dnload";
- .bind = g_dnl_do_config,
- };
+ config = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*config));
+ if (!config)
+ return -ENOMEM;
- return usb_add_config(cdev, &config);
+ memset(config, 0, sizeof(*config));
+
+ config->label = name;
+ config->bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER;
+ config->bConfigurationValue = CONFIGURATION_NUMBER;
+ config->iConfiguration = STRING_USBDOWN;
+ config->bind = g_dnl_do_config;
+
+ return usb_add_config(cdev, config);
}
__weak
-int g_dnl_bind_fixup(struct usb_device_descriptor *dev)
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
{
return 0;
}
g_dnl_string_defs[1].id = id;
device_desc.iProduct = id;
- g_dnl_bind_fixup(&device_desc);
+ g_dnl_bind_fixup(&device_desc, cdev->driver->name);
ret = g_dnl_config_register(cdev);
if (ret)
goto error;
int g_dnl_register(const char *type)
{
- /* We only allow "dfu" atm, so 3 should be enough */
- static char name[sizeof(shortname) + 3];
+ /* The largest function name is 4 */
+ static char name[sizeof(shortname) + 4];
int ret;
if (!strcmp(type, "dfu")) {
} else if (!strcmp(type, "ums")) {
strcpy(name, shortname);
strcat(name, type);
+ } else if (!strcmp(type, "thor")) {
+ strcpy(name, shortname);
+ strcat(name, type);
} else {
printf("%s: unknown command: %s\n", __func__, type);
return -EINVAL;
#include <commproc.h>
#include <usbdevice.h>
#include <usb/mpc8xx_udc.h>
+#include <usb/udc.h>
#include "ep0.h"
#include <config.h>
#include <net.h>
#include <malloc.h>
+#include <asm/byteorder.h>
+#include <asm/errno.h>
#include <asm/io.h>
+#include <asm/unaligned.h>
#include <linux/types.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
#include <usb/mv_udc.h>
-
-#if CONFIG_USB_MAX_CONTROLLER_COUNT > 1
-#error This driver only supports one single controller.
-#endif
+#include "../host/ehci.h"
+#include "mv_udc.h"
/*
* Check if the system has too long cachelines. If the cachelines are
.gadget = {
.name = "mv_udc",
.ops = &mv_udc_ops,
+ .is_dualspeed = 1,
},
};
return;
}
-static void ep_enable(int num, int in)
+static void ep_enable(int num, int in, int maxpacket)
{
- struct ept_queue_head *head;
struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
unsigned n;
- head = mv_get_qh(num, in);
n = readl(&udc->epctrl[num]);
if (in)
n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK);
if (num != 0) {
- head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE) | CONFIG_ZLT;
+ struct ept_queue_head *head = mv_get_qh(num, in);
+
+ head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT;
mv_flush_qh(num);
}
writel(n, &udc->epctrl[num]);
int num, in;
num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
- ep_enable(num, in);
mv_ep->desc = desc;
+
+ if (num) {
+ int max = get_unaligned_le16(&desc->wMaxPacketSize);
+
+ if ((max > 64) && (controller.gadget.speed == USB_SPEED_FULL))
+ max = 64;
+ if (ep->maxpacket != max) {
+ DBG("%s: from %d to %d\n", __func__,
+ ep->maxpacket, max);
+ ep->maxpacket = max;
+ }
+ }
+ ep_enable(num, in, ep->maxpacket);
+ DBG("%s: num=%d maxpacket=%d\n", __func__, num, ep->maxpacket);
return 0;
}
static int mv_ep_disable(struct usb_ep *ep)
{
+ struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep);
+
+ mv_ep->desc = NULL;
return 0;
}
-static int mv_bounce(struct mv_ep *ep)
+static int mv_bounce(struct mv_ep *ep, int in)
{
uint32_t addr = (uint32_t)ep->req.buf;
uint32_t ba;
if (!ep->b_buf)
return -ENOMEM;
}
-
- memcpy(ep->b_buf, ep->req.buf, ep->req.length);
+ if (in)
+ memcpy(ep->b_buf, ep->req.buf, ep->req.length);
flush:
ba = (uint32_t)ep->b_buf;
return 0;
}
-static void mv_debounce(struct mv_ep *ep)
+static void mv_debounce(struct mv_ep *ep, int in)
{
uint32_t addr = (uint32_t)ep->req.buf;
uint32_t ba = (uint32_t)ep->b_buf;
+ if (in) {
+ if (addr == ba)
+ return; /* not a bounce */
+ goto free;
+ }
invalidate_dcache_range(ba, ba + ep->b_len);
- /* Input buffer address is not aligned. */
- if (addr & (ARCH_DMA_MINALIGN - 1))
- goto copy;
+ if (addr == ba)
+ return; /* not a bounce */
- /* Input buffer length is not aligned. */
- if (ep->req.length & (ARCH_DMA_MINALIGN - 1))
- goto copy;
-
- /* The buffer is well aligned, only invalidate cache. */
- return;
-
-copy:
memcpy(ep->req.buf, ep->b_buf, ep->req.length);
-
+free:
/* Large payloads use allocated buffer, free it. */
- if (ep->req.length > 64)
+ if (ep->b_buf != ep->b_fast)
free(ep->b_buf);
}
head = mv_get_qh(num, in);
len = req->length;
- ret = mv_bounce(mv_ep);
+ ret = mv_bounce(mv_ep, in);
if (ret)
return ret;
item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE;
item->page0 = (uint32_t)mv_ep->b_buf;
item->page1 = ((uint32_t)mv_ep->b_buf & 0xfffff000) + 0x1000;
+ mv_flush_qtd(num);
head->next = (unsigned) item;
head->info = 0;
DBG("ept%d %s queue len %x, buffer %p\n",
num, in ? "in" : "out", len, mv_ep->b_buf);
+ mv_flush_qh(num);
if (in)
bit = EPT_TX(num);
else
bit = EPT_RX(num);
- mv_flush_qh(num);
- mv_flush_qtd(num);
-
writel(bit, &udc->epprime);
return 0;
mv_invalidate_qtd(num);
if (item->info & 0xff)
- printf("EP%d/%s FAIL nfo=%x pg0=%x\n",
- num, in ? "in" : "out", item->info, item->page0);
+ printf("EP%d/%s FAIL info=%x pg0=%x\n",
+ num, in ? "in" : "out", item->info, item->page0);
len = (item->info >> 16) & 0x7fff;
-
- mv_debounce(ep);
-
ep->req.length -= len;
+ mv_debounce(ep, in);
+
DBG("ept%d %s complete %x\n",
num, in ? "in" : "out", len);
ep->req.complete(&ep->ep, &ep->req);
if ((r.wValue == 0) && (r.wLength == 0)) {
req->length = 0;
for (i = 0; i < NUM_ENDPOINTS; i++) {
- if (!controller.ep[i].desc)
+ struct mv_ep *ep = &controller.ep[i];
+
+ if (!ep->desc)
continue;
- num = controller.ep[i].desc->bEndpointAddress
+ num = ep->desc->bEndpointAddress
& USB_ENDPOINT_NUMBER_MASK;
- in = (controller.ep[i].desc->bEndpointAddress
+ in = (ep->desc->bEndpointAddress
& USB_DIR_IN) != 0;
if ((num == _num) && (in == _in)) {
- ep_enable(num, in);
+ ep_enable(num, in, ep->ep.maxpacket);
usb_ep_queue(controller.gadget.ep0,
req, 0);
break;
DBG("-- suspend --\n");
if (n & STS_PCI) {
- DBG("-- portchange --\n");
+ int max = 64;
+ int speed = USB_SPEED_FULL;
+
bit = (readl(&udc->portsc) >> 26) & 3;
+ DBG("-- portchange %x %s\n", bit, (bit == 2) ? "High" : "Full");
if (bit == 2) {
- controller.gadget.speed = USB_SPEED_HIGH;
- for (i = 1; i < NUM_ENDPOINTS && n; i++)
- if (controller.ep[i].desc)
- controller.ep[i].ep.maxpacket = 512;
- } else {
- controller.gadget.speed = USB_SPEED_FULL;
+ speed = USB_SPEED_HIGH;
+ max = 512;
+ }
+ controller.gadget.speed = speed;
+ for (i = 1; i < NUM_ENDPOINTS; i++) {
+ if (controller.ep[i].ep.maxpacket > max)
+ controller.ep[i].ep.maxpacket = max;
}
}
free(controller.epts);
return -ENOMEM;
}
+ memset(controller.items_mem, 0, ilist_sz);
for (i = 0; i < 2 * NUM_ENDPOINTS; i++) {
/*
if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH)
return -EINVAL;
- ret = usb_lowlevel_init(0, (void **)&controller.ctrl);
+ ret = usb_lowlevel_init(0, USB_INIT_DEVICE, (void **)&controller.ctrl);
if (ret)
return ret;
--- /dev/null
+/*
+ * Copyright 2011, Marvell Semiconductor Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __GADGET__MV_UDC_H__
+#define __GADGET__MV_UDC_H__
+
+#define NUM_ENDPOINTS 6
+
+struct mv_udc {
+#define MICRO_8FRAME 0x8
+#define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16)
+#define USBCMD_FS2 (1 << 15)
+#define USBCMD_RST (1 << 1)
+#define USBCMD_RUN (1)
+ u32 usbcmd; /* 0x140 */
+#define STS_SLI (1 << 8)
+#define STS_URI (1 << 6)
+#define STS_PCI (1 << 2)
+#define STS_UEI (1 << 1)
+#define STS_UI (1 << 0)
+ u32 usbsts; /* 0x144 */
+ u32 pad1[3];
+ u32 devaddr; /* 0x154 */
+ u32 epinitaddr; /* 0x158 */
+ u32 pad2[10];
+#define PTS_ENABLE 2
+#define PTS(x) (((x) & 0x3) << 30)
+#define PFSC (1 << 24)
+ u32 portsc; /* 0x184 */
+ u32 pad3[8];
+#define USBMODE_DEVICE 2
+ u32 usbmode; /* 0x1a8 */
+ u32 epstat; /* 0x1ac */
+#define EPT_TX(x) (1 << (((x) & 0xffff) + 16))
+#define EPT_RX(x) (1 << ((x) & 0xffff))
+ u32 epprime; /* 0x1b0 */
+ u32 epflush; /* 0x1b4 */
+ u32 pad4;
+ u32 epcomp; /* 0x1bc */
+#define CTRL_TXE (1 << 23)
+#define CTRL_TXR (1 << 22)
+#define CTRL_RXE (1 << 7)
+#define CTRL_RXR (1 << 6)
+#define CTRL_TXT_BULK (2 << 18)
+#define CTRL_RXT_BULK (2 << 2)
+ u32 epctrl[16]; /* 0x1c0 */
+};
+
+struct mv_ep {
+ struct usb_ep ep;
+ struct list_head queue;
+ const struct usb_endpoint_descriptor *desc;
+
+ struct usb_request req;
+ uint8_t *b_buf;
+ uint32_t b_len;
+ uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN);
+};
+
+struct mv_drv {
+ struct usb_gadget gadget;
+ struct usb_gadget_driver *driver;
+ struct ehci_ctrl *ctrl;
+ struct ept_queue_head *epts;
+ struct ept_queue_item *items[2 * NUM_ENDPOINTS];
+ uint8_t *items_mem;
+ struct mv_ep ep[NUM_ENDPOINTS];
+};
+
+struct ept_queue_head {
+ unsigned config;
+ unsigned current; /* read-only */
+
+ unsigned next;
+ unsigned info;
+ unsigned page0;
+ unsigned page1;
+ unsigned page2;
+ unsigned page3;
+ unsigned page4;
+ unsigned reserved_0;
+
+ unsigned char setup_data[8];
+
+ unsigned reserved_1;
+ unsigned reserved_2;
+ unsigned reserved_3;
+ unsigned reserved_4;
+};
+
+#define CONFIG_MAX_PKT(n) ((n) << 16)
+#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */
+#define CONFIG_IOS (1 << 15) /* IRQ on setup */
+
+struct ept_queue_item {
+ unsigned next;
+ unsigned info;
+ unsigned page0;
+ unsigned page1;
+ unsigned page2;
+ unsigned page3;
+ unsigned page4;
+ unsigned reserved;
+};
+
+#define TERMINATE 1
+#define INFO_BYTES(n) ((n) << 16)
+#define INFO_IOC (1 << 15)
+#define INFO_ACTIVE (1 << 7)
+#define INFO_HALTED (1 << 6)
+#define INFO_BUFFER_ERROR (1 << 5)
+#define INFO_TX_ERROR (1 << 3)
+#endif
#endif
#include <usbdevice.h>
#include <usb/omap1510_udc.h>
+#include <usb/udc.h>
#include "ep0.h"
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <usb/pxa27x_udc.h>
+#include <usb/udc.h>
#include "ep0.h"
invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_num],
(unsigned long) ep->dev->dma_buf[ep_num]
- + DMA_BUFFER_SIZE);
+ + ROUND(ep->ep.maxpacket,
+ CONFIG_SYS_CACHELINE_SIZE));
if (length == 0)
pktcnt = 1;
COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
+# xhci
+COBJS-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
+COBJS-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
+COBJS-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
+
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
/*
* EHCI host controller init
*/
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
if (utmi_init() < 0)
return -1;
*/
#define EN_UPLL_TIMEOUT 500UL
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
ulong start_time, tmp_time;
#include <asm/arch/ehci.h>
#include <asm/arch/system.h>
#include <asm/arch/power.h>
+#include <asm/gpio.h>
#include <asm-generic/errno.h>
#include <linux/compat.h>
#include "ehci.h"
struct exynos_ehci {
struct exynos_usb_phy *usb;
struct ehci_hccr *hcd;
+ struct fdt_gpio_state vbus_gpio;
};
static struct exynos_ehci exynos;
exynos->hcd = (struct ehci_hccr *)addr;
+ /* Vbus gpio */
+ fdtdec_decode_gpio(blob, node, "samsung,vbus-gpio", &exynos->vbus_gpio);
+
depth = 0;
node = fdtdec_next_compatible_subnode(blob, node,
COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct exynos_ehci *ctx = &exynos;
ctx->hcd = (struct ehci_hccr *)samsung_get_base_usb_ehci();
#endif
+#ifdef CONFIG_OF_CONTROL
+ /* setup the Vbus gpio here */
+ if (!fdtdec_setup_gpio(&ctx->vbus_gpio))
+ gpio_direction_output(ctx->vbus_gpio.gpio, 1);
+#endif
+
setup_usb_phy(ctx->usb);
*hccr = ctx->hcd;
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(int index, struct ehci_hccr **ret_hccr,
- struct ehci_hcor **ret_hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor)
{
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
*
* Excerpts from linux ehci fsl driver.
*/
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
const char *phy_type = NULL;
return ehci_hcd_stop(index);
}
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
{
uint32_t reg;
uint32_t cmd;
struct QH *qh_list;
struct QH *periodic;
int i;
+ int rc;
- if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
- return -1;
+ rc = ehci_hcd_init(index, init, &ehcic[index].hccr, &ehcic[index].hcor);
+ if (rc)
+ return rc;
+ if (init == USB_INIT_DEVICE)
+ goto done;
/* EHCI spec section 4.1 */
if (ehci_reset(index))
return -1;
#if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
- if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
- return -1;
+ rc = ehci_hcd_init(index, init, &ehcic[index].hccr, &ehcic[index].hcor);
+ if (rc)
+ return rc;
#endif
/* Set the high address word (aka segment) for 64-bit controller */
if (ehci_readl(&ehcic[index].hccr->cr_hccparams) & 1)
printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
ehcic[index].rootdev = 0;
-
+done:
*controller = &ehcic[index];
return 0;
}
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
*hccr = (struct ehci_hccr *)(0xcd000100);
*hcor = (struct ehci_hcor *)((uint32_t) *hccr
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
usb_brg_adrdec_setup();
* This code is derived from EHCI FSL USB Linux driver for MPC5121
*
*/
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
volatile struct usb_ehci *ehci;
{
}
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
#define USBPHY_CTRL_CLKGATE 0x40000000
#define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
#define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
+#define USBPHY_CTRL_OTG_ID 0x08000000
#define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
/* USBCMD */
-#define UH1_USBCMD_OFFSET 0x140
#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
#define UCMD_RESET (1 << 1) /* controller reset */
-static void usbh1_internal_phy_clock_gate(int on)
+static const unsigned phy_bases[] = {
+ USB_PHY0_BASE_ADDR,
+ USB_PHY1_BASE_ADDR,
+};
+
+static void usb_internal_phy_clock_gate(int index, int on)
{
- void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
+ void __iomem *phy_reg;
+
+ if (index >= ARRAY_SIZE(phy_bases))
+ return;
+ phy_reg = (void __iomem *)phy_bases[index];
phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
__raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
}
-static void usbh1_power_config(void)
+static void usb_power_config(int index)
{
struct anatop_regs __iomem *anatop =
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+ void __iomem *chrg_detect;
+ void __iomem *pll_480_ctrl_clr;
+ void __iomem *pll_480_ctrl_set;
+
+ switch (index) {
+ case 0:
+ chrg_detect = &anatop->usb1_chrg_detect;
+ pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
+ pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
+ break;
+ case 1:
+ chrg_detect = &anatop->usb2_chrg_detect;
+ pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
+ pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
+ break;
+ default:
+ return;
+ }
/*
- * Some phy and power's special controls for host1
+ * Some phy and power's special controls
* 1. The external charger detector needs to be disabled
* or the signal at DP will be poor
- * 2. The PLL's power and output to usb for host 1
+ * 2. The PLL's power and output to usb
* is totally controlled by IC, so the Software only needs
* to enable them at initializtion.
*/
__raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
- &anatop->usb2_chrg_detect);
+ chrg_detect);
__raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
- &anatop->usb2_pll_480_ctrl_clr);
+ pll_480_ctrl_clr);
__raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
ANADIG_USB2_PLL_480_CTRL_POWER |
ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
- &anatop->usb2_pll_480_ctrl_set);
+ pll_480_ctrl_set);
}
-static int usbh1_phy_enable(void)
+/* Return 0 : host node, <>0 : device mode */
+static int usb_phy_enable(int index, struct usb_ehci *ehci)
{
- void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
- void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
- void __iomem *usb_cmd = (void __iomem *)(USBOH3_USB_BASE_ADDR +
- USB_H1REGS_OFFSET +
- UH1_USBCMD_OFFSET);
+ void __iomem *phy_reg;
+ void __iomem *phy_ctrl;
+ void __iomem *usb_cmd;
u32 val;
+ if (index >= ARRAY_SIZE(phy_bases))
+ return 0;
+
+ phy_reg = (void __iomem *)phy_bases[index];
+ phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+ usb_cmd = (void __iomem *)&ehci->usbcmd;
+
/* Stop then Reset */
val = __raw_readl(usb_cmd);
val &= ~UCMD_RUN_STOP;
/* Power up the PHY */
__raw_writel(0, phy_reg + USBPHY_PWD);
/* enable FS/LS device */
- val = __raw_readl(phy_reg + USBPHY_CTRL);
+ val = __raw_readl(phy_ctrl);
val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
- __raw_writel(val, phy_reg + USBPHY_CTRL);
+ __raw_writel(val, phy_ctrl);
- return 0;
+ return val & USBPHY_CTRL_OTG_ID;
}
-static void usbh1_oc_config(void)
+/* Base address for this IP block is 0x02184800 */
+struct usbnc_regs {
+ u32 ctrl[4]; /* otg/host1-3 */
+ u32 uh2_hsic_ctrl;
+ u32 uh3_hsic_ctrl;
+ u32 otg_phy_ctrl_0;
+ u32 uh1_phy_ctrl_0;
+};
+
+static void usb_oc_config(int index)
{
- void __iomem *usb_base = (void __iomem *)USBOH3_USB_BASE_ADDR;
- void __iomem *usbother_base = usb_base + USB_OTHERREGS_OFFSET;
+ struct usbnc_regs *usbnc = (struct usbnc_regs *)(USBOH3_USB_BASE_ADDR +
+ USB_OTHERREGS_OFFSET);
+ void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
u32 val;
- val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
+ val = __raw_readl(ctrl);
#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
/* mx6qarm2 seems to required a different setting*/
val &= ~UCTRL_OVER_CUR_POL;
#else
val |= UCTRL_OVER_CUR_POL;
#endif
- __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
+ __raw_writel(val, ctrl);
- val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
+ val = __raw_readl(ctrl);
val |= UCTRL_OVER_CUR_DIS;
- __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
+ __raw_writel(val, ctrl);
}
int __weak board_ehci_hcd_init(int port)
return 0;
}
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int __weak board_ehci_power(int port, int on)
{
- struct usb_ehci *ehci;
+ return 0;
+}
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ enum usb_init_type type;
+ struct usb_ehci *ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
+ (0x200 * index));
+ if (index > 3)
+ return -EINVAL;
enable_usboh3_clk(1);
mdelay(1);
/* Do board specific initialization */
- board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
-
-#if CONFIG_MXC_USB_PORT == 1
- /* USB Host 1 */
- usbh1_power_config();
- usbh1_oc_config();
- usbh1_internal_phy_clock_gate(1);
- usbh1_phy_enable();
-#else
-#error "MXC USB port not yet supported"
-#endif
+ board_ehci_hcd_init(index);
+
+ usb_power_config(index);
+ usb_oc_config(index);
+ usb_internal_phy_clock_gate(index, 1);
+ type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
- ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
- (0x200 * CONFIG_MXC_USB_PORT));
*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
- setbits_le32(&ehci->usbmode, CM_HOST);
+ if ((type == init) || (type == USB_INIT_DEVICE))
+ board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
+ if (type != init)
+ return -ENODEV;
+ if (type == USB_INIT_DEVICE)
+ return 0;
+ setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
setbits_le32(&ehci->portsc, USB_EN);
return 0;
}
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
#ifdef CONFIG_MX31
return 0;
}
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
}
#endif
-inline int __board_usb_init(void)
-{
- return 0;
-}
-int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
-
#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
* Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
* See there for additional Copyrights.
*/
-int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
unsigned int i, reg = 0, rev = 0;
debug("Initializing OMAP EHCI\n");
- ret = board_usb_init();
+ ret = board_usb_init(index, USB_INIT_HOST);
if (ret < 0)
return ret;
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(int index, struct ehci_hccr **ret_hccr,
- struct ehci_hcor **ret_hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor)
{
pci_dev_t pdev;
uint32_t cmd;
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
*hccr = (struct ehci_hccr *)(CONFIG_SYS_PPC4XX_USB_ADDR);
*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
*hccr = (struct ehci_hccr *)(CONFIG_SYS_UHC0_EHCI_BASE + 0x100);
*hcor = (struct ehci_hcor *)((uint32_t)*hccr
return 0;
}
-int board_usb_init(const void *blob)
+int usb_process_devicetree(const void *blob)
{
int node_list[USB_PORTS_MAX];
int count, err = 0;
* @param hcor returns start address of EHCI HCOR registers
* @return 0 if ok, -1 on error (generally invalid port number)
*/
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct fdt_usb *config;
struct usb_ctlr *usbctlr;
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
u32 vct_hccr;
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
#endif
-/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
-#define DeviceRequest \
- ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define DeviceOutRequest \
- ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define InterfaceRequest \
- ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointRequest \
- ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointOutRequest \
- ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
/*
* Register Space.
*/
};
/* Low level init functions */
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor);
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor);
int ehci_hcd_stop(int index);
#endif /* USB_EHCI_H */
return 0;
}
-int usb_lowlevel_init(int index, void **controller))
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller))
{
struct isp116x *isp116x = &isp116x_dev;
*/
static char ohci_inited = 0;
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
{
#ifdef CONFIG_PCI_OHCI
pci_dev_t pdev;
#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
/* board dependant init */
- if (usb_board_init())
+ if (board_usb_init(index, USB_INIT_HOST))
return -1;
#endif
memset(&gohci, 0, sizeof(ohci_t));
err ("can't reset usb-%s", gohci.slot_name);
#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
/* board dependant cleanup */
- usb_board_init_fail();
+ board_usb_cleanup(index, USB_INIT_HOST);
#endif
#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
*/
static char ohci_inited = 0;
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
/* functions for doing board or CPU specific setup/cleanup */
-extern int usb_board_init(void);
-extern int usb_board_stop(void);
-extern int usb_board_init_fail(void);
-
-extern int usb_cpu_init(void);
-extern int usb_cpu_stop(void);
-extern int usb_cpu_init_fail(void);
+int usb_board_stop(void);
+int usb_cpu_init(void);
+int usb_cpu_stop(void);
+int usb_cpu_init_fail(void);
static int cc_to_error[16] = {
return 0;
}
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
{
struct r8a66597 *r8a66597 = &gr8a66597;
return 1;
}
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
{
root_hub_devnum = 0;
sl811_hc_reset();
--- /dev/null
+/*
+ * SAMSUNG EXYNOS5 USB HOST XHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * Vivek Gautam <gautam.vivek@samsung.com>
+ * Vikas Sajjan <vikas.sajjan@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * This file is a conglomeration for DWC3-init sequence and further
+ * exynos5 specific PHY-init sequence.
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>
+#include <usb.h>
+#include <watchdog.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/power.h>
+#include <asm/arch/xhci-exynos.h>
+#include <asm/gpio.h>
+#include <asm-generic/errno.h>
+#include <linux/compat.h>
+#include <linux/usb/dwc3.h>
+
+#include "xhci.h"
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * Contains pointers to register base addresses
+ * for the usb controller.
+ */
+struct exynos_xhci {
+ struct exynos_usb3_phy *usb3_phy;
+ struct xhci_hccr *hcd;
+ struct dwc3 *dwc3_reg;
+ struct fdt_gpio_state vbus_gpio;
+};
+
+static struct exynos_xhci exynos;
+
+#ifdef CONFIG_OF_CONTROL
+static int exynos_usb3_parse_dt(const void *blob, struct exynos_xhci *exynos)
+{
+ fdt_addr_t addr;
+ unsigned int node;
+ int depth;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_XHCI);
+ if (node <= 0) {
+ debug("XHCI: Can't get device node for xhci\n");
+ return -ENODEV;
+ }
+
+ /*
+ * Get the base address for XHCI controller from the device node
+ */
+ addr = fdtdec_get_addr(blob, node, "reg");
+ if (addr == FDT_ADDR_T_NONE) {
+ debug("Can't get the XHCI register base address\n");
+ return -ENXIO;
+ }
+ exynos->hcd = (struct xhci_hccr *)addr;
+
+ /* Vbus gpio */
+ fdtdec_decode_gpio(blob, node, "samsung,vbus-gpio", &exynos->vbus_gpio);
+
+ depth = 0;
+ node = fdtdec_next_compatible_subnode(blob, node,
+ COMPAT_SAMSUNG_EXYNOS5_USB3_PHY, &depth);
+ if (node <= 0) {
+ debug("XHCI: Can't get device node for usb3-phy controller\n");
+ return -ENODEV;
+ }
+
+ /*
+ * Get the base address for usbphy from the device node
+ */
+ exynos->usb3_phy = (struct exynos_usb3_phy *)fdtdec_get_addr(blob, node,
+ "reg");
+ if (exynos->usb3_phy == NULL) {
+ debug("Can't get the usbphy register address\n");
+ return -ENXIO;
+ }
+
+ return 0;
+}
+#endif
+
+static void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy)
+{
+ u32 reg;
+
+ /* enabling usb_drd phy */
+ set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN);
+
+ /* Reset USB 3.0 PHY */
+ writel(0x0, &phy->phy_reg0);
+
+ clrbits_le32(&phy->phy_param0,
+ /* Select PHY CLK source */
+ PHYPARAM0_REF_USE_PAD |
+ /* Set Loss-of-Signal Detector sensitivity */
+ PHYPARAM0_REF_LOSLEVEL_MASK);
+ setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);
+
+ writel(0x0, &phy->phy_resume);
+
+ /*
+ * Setting the Frame length Adj value[6:1] to default 0x20
+ * See xHCI 1.0 spec, 5.2.4
+ */
+ setbits_le32(&phy->link_system,
+ LINKSYSTEM_XHCI_VERSION_CONTROL |
+ LINKSYSTEM_FLADJ(0x20));
+
+ /* Set Tx De-Emphasis level */
+ clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);
+ setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);
+
+ setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);
+
+ /* PHYTEST POWERDOWN Control */
+ clrbits_le32(&phy->phy_test,
+ PHYTEST_POWERDOWN_SSP |
+ PHYTEST_POWERDOWN_HSP);
+
+ /* UTMI Power Control */
+ writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);
+
+ /* Use core clock from main PLL */
+ reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
+ /* Default 24Mhz crystal clock */
+ PHYCLKRST_FSEL(FSEL_CLKSEL_24M) |
+ PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x88) |
+ /* Force PortReset of PHY */
+ PHYCLKRST_PORTRESET |
+ /* Digital power supply in normal operating mode */
+ PHYCLKRST_RETENABLEN |
+ /* Enable ref clock for SS function */
+ PHYCLKRST_REF_SSP_EN |
+ /* Enable spread spectrum */
+ PHYCLKRST_SSC_EN |
+ /* Power down HS Bias and PLL blocks in suspend mode */
+ PHYCLKRST_COMMONONN;
+
+ writel(reg, &phy->phy_clk_rst);
+
+ /* giving time to Phy clock to settle before resetting */
+ udelay(10);
+
+ reg &= ~PHYCLKRST_PORTRESET;
+ writel(reg, &phy->phy_clk_rst);
+}
+
+static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy)
+{
+ setbits_le32(&phy->phy_utmi,
+ PHYUTMI_OTGDISABLE |
+ PHYUTMI_FORCESUSPEND |
+ PHYUTMI_FORCESLEEP);
+
+ clrbits_le32(&phy->phy_clk_rst,
+ PHYCLKRST_REF_SSP_EN |
+ PHYCLKRST_SSC_EN |
+ PHYCLKRST_COMMONONN);
+
+ /* PHYTEST POWERDOWN Control to remove leakage current */
+ setbits_le32(&phy->phy_test,
+ PHYTEST_POWERDOWN_SSP |
+ PHYTEST_POWERDOWN_HSP);
+
+ /* disabling usb_drd phy */
+ set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE);
+}
+
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
+{
+ clrsetbits_le32(&dwc3_reg->g_ctl,
+ DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
+ DWC3_GCTL_PRTCAPDIR(mode));
+}
+
+static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
+{
+ /* Before Resetting PHY, put Core in Reset */
+ setbits_le32(&dwc3_reg->g_ctl,
+ DWC3_GCTL_CORESOFTRESET);
+
+ /* Assert USB3 PHY reset */
+ setbits_le32(&dwc3_reg->g_usb3pipectl[0],
+ DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Assert USB2 PHY reset */
+ setbits_le32(&dwc3_reg->g_usb2phycfg,
+ DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ mdelay(100);
+
+ /* Clear USB3 PHY reset */
+ clrbits_le32(&dwc3_reg->g_usb3pipectl[0],
+ DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Clear USB2 PHY reset */
+ clrbits_le32(&dwc3_reg->g_usb2phycfg,
+ DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ /* After PHYs are stable we can take Core out of reset state */
+ clrbits_le32(&dwc3_reg->g_ctl,
+ DWC3_GCTL_CORESOFTRESET);
+}
+
+static int dwc3_core_init(struct dwc3 *dwc3_reg)
+{
+ u32 reg;
+ u32 revision;
+ unsigned int dwc3_hwparams1;
+
+ revision = readl(&dwc3_reg->g_snpsid);
+ /* This should read as U3 followed by revision number */
+ if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
+ puts("this is not a DesignWare USB3 DRD Core\n");
+ return -EINVAL;
+ }
+
+ dwc3_core_soft_reset(dwc3_reg);
+
+ dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
+
+ reg = readl(&dwc3_reg->g_ctl);
+ reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
+ reg &= ~DWC3_GCTL_DISSCRAMBLE;
+ switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
+ case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
+ reg &= ~DWC3_GCTL_DSBLCLKGTNG;
+ break;
+ default:
+ debug("No power optimization available\n");
+ }
+
+ /*
+ * WORKAROUND: DWC3 revisions <1.90a have a bug
+ * where the device can fail to connect at SuperSpeed
+ * and falls back to high-speed mode which causes
+ * the device to enter a Connect/Disconnect loop
+ */
+ if ((revision & DWC3_REVISION_MASK) < 0x190a)
+ reg |= DWC3_GCTL_U2RSTECN;
+
+ writel(reg, &dwc3_reg->g_ctl);
+
+ return 0;
+}
+
+static int exynos_xhci_core_init(struct exynos_xhci *exynos)
+{
+ int ret;
+
+ exynos5_usb3_phy_init(exynos->usb3_phy);
+
+ ret = dwc3_core_init(exynos->dwc3_reg);
+ if (ret) {
+ debug("failed to initialize core\n");
+ return -EINVAL;
+ }
+
+ /* We are hard-coding DWC3 core to Host Mode */
+ dwc3_set_mode(exynos->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+ return 0;
+}
+
+static void exynos_xhci_core_exit(struct exynos_xhci *exynos)
+{
+ exynos5_usb3_phy_exit(exynos->usb3_phy);
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+ struct exynos_xhci *ctx = &exynos;
+ int ret;
+
+#ifdef CONFIG_OF_CONTROL
+ exynos_usb3_parse_dt(gd->fdt_blob, ctx);
+#else
+ ctx->usb3_phy = (struct exynos_usb3_phy *)samsung_get_base_usb3_phy();
+ ctx->hcd = (struct xhci_hccr *)samsung_get_base_usb_xhci();
+#endif
+
+ ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
+
+#ifdef CONFIG_OF_CONTROL
+ /* setup the Vbus gpio here */
+ if (!fdtdec_setup_gpio(&ctx->vbus_gpio))
+ gpio_direction_output(ctx->vbus_gpio.gpio, 1);
+#endif
+
+ ret = exynos_xhci_core_init(ctx);
+ if (ret) {
+ puts("XHCI: failed to initialize controller\n");
+ return -EINVAL;
+ }
+
+ *hccr = (ctx->hcd);
+ *hcor = (struct xhci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+ debug("Exynos5-xhci: init hccr %x and hcor %x hc_length %d\n",
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+ return 0;
+}
+
+void xhci_hcd_stop(int index)
+{
+ struct exynos_xhci *ctx = &exynos;
+
+ exynos_xhci_core_exit(ctx);
+}
--- /dev/null
+/*
+ * USB HOST XHCI Controller stack
+ *
+ * Based on xHCI host controller driver in linux-kernel
+ * by Sarah Sharp.
+ *
+ * Copyright (C) 2008 Intel Corp.
+ * Author: Sarah Sharp
+ *
+ * Copyright (C) 2013 Samsung Electronics Co.Ltd
+ * Authors: Vivek Gautam <gautam.vivek@samsung.com>
+ * Vikas Sajjan <vikas.sajjan@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/byteorder.h>
+#include <usb.h>
+#include <malloc.h>
+#include <asm/cache.h>
+#include <asm-generic/errno.h>
+
+#include "xhci.h"
+
+#define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
+/**
+ * flushes the address passed till the length
+ *
+ * @param addr pointer to memory region to be flushed
+ * @param len the length of the cache line to be flushed
+ * @return none
+ */
+void xhci_flush_cache(uint32_t addr, u32 len)
+{
+ BUG_ON((void *)addr == NULL || len == 0);
+
+ flush_dcache_range(addr & ~(CACHELINE_SIZE - 1),
+ ALIGN(addr + len, CACHELINE_SIZE));
+}
+
+/**
+ * invalidates the address passed till the length
+ *
+ * @param addr pointer to memory region to be invalidates
+ * @param len the length of the cache line to be invalidated
+ * @return none
+ */
+void xhci_inval_cache(uint32_t addr, u32 len)
+{
+ BUG_ON((void *)addr == NULL || len == 0);
+
+ invalidate_dcache_range(addr & ~(CACHELINE_SIZE - 1),
+ ALIGN(addr + len, CACHELINE_SIZE));
+}
+
+
+/**
+ * frees the "segment" pointer passed
+ *
+ * @param ptr pointer to "segement" to be freed
+ * @return none
+ */
+static void xhci_segment_free(struct xhci_segment *seg)
+{
+ free(seg->trbs);
+ seg->trbs = NULL;
+
+ free(seg);
+}
+
+/**
+ * frees the "ring" pointer passed
+ *
+ * @param ptr pointer to "ring" to be freed
+ * @return none
+ */
+static void xhci_ring_free(struct xhci_ring *ring)
+{
+ struct xhci_segment *seg;
+ struct xhci_segment *first_seg;
+
+ BUG_ON(!ring);
+
+ first_seg = ring->first_seg;
+ seg = first_seg->next;
+ while (seg != first_seg) {
+ struct xhci_segment *next = seg->next;
+ xhci_segment_free(seg);
+ seg = next;
+ }
+ xhci_segment_free(first_seg);
+
+ free(ring);
+}
+
+/**
+ * frees the "xhci_container_ctx" pointer passed
+ *
+ * @param ptr pointer to "xhci_container_ctx" to be freed
+ * @return none
+ */
+static void xhci_free_container_ctx(struct xhci_container_ctx *ctx)
+{
+ free(ctx->bytes);
+ free(ctx);
+}
+
+/**
+ * frees the virtual devices for "xhci_ctrl" pointer passed
+ *
+ * @param ptr pointer to "xhci_ctrl" whose virtual devices are to be freed
+ * @return none
+ */
+static void xhci_free_virt_devices(struct xhci_ctrl *ctrl)
+{
+ int i;
+ int slot_id;
+ struct xhci_virt_device *virt_dev;
+
+ /*
+ * refactored here to loop through all virt_dev
+ * Slot ID 0 is reserved
+ */
+ for (slot_id = 0; slot_id < MAX_HC_SLOTS; slot_id++) {
+ virt_dev = ctrl->devs[slot_id];
+ if (!virt_dev)
+ continue;
+
+ ctrl->dcbaa->dev_context_ptrs[slot_id] = 0;
+
+ for (i = 0; i < 31; ++i)
+ if (virt_dev->eps[i].ring)
+ xhci_ring_free(virt_dev->eps[i].ring);
+
+ if (virt_dev->in_ctx)
+ xhci_free_container_ctx(virt_dev->in_ctx);
+ if (virt_dev->out_ctx)
+ xhci_free_container_ctx(virt_dev->out_ctx);
+
+ free(virt_dev);
+ /* make sure we are pointing to NULL */
+ ctrl->devs[slot_id] = NULL;
+ }
+}
+
+/**
+ * frees all the memory allocated
+ *
+ * @param ptr pointer to "xhci_ctrl" to be cleaned up
+ * @return none
+ */
+void xhci_cleanup(struct xhci_ctrl *ctrl)
+{
+ xhci_ring_free(ctrl->event_ring);
+ xhci_ring_free(ctrl->cmd_ring);
+ xhci_free_virt_devices(ctrl);
+ free(ctrl->erst.entries);
+ free(ctrl->dcbaa);
+ memset(ctrl, '\0', sizeof(struct xhci_ctrl));
+}
+
+/**
+ * Malloc the aligned memory
+ *
+ * @param size size of memory to be allocated
+ * @return allocates the memory and returns the aligned pointer
+ */
+static void *xhci_malloc(unsigned int size)
+{
+ void *ptr;
+ size_t cacheline_size = max(XHCI_ALIGNMENT, CACHELINE_SIZE);
+
+ ptr = memalign(cacheline_size, ALIGN(size, cacheline_size));
+ BUG_ON(!ptr);
+ memset(ptr, '\0', size);
+
+ xhci_flush_cache((uint32_t)ptr, size);
+
+ return ptr;
+}
+
+/**
+ * Make the prev segment point to the next segment.
+ * Change the last TRB in the prev segment to be a Link TRB which points to the
+ * address of the next segment. The caller needs to set any Link TRB
+ * related flags, such as End TRB, Toggle Cycle, and no snoop.
+ *
+ * @param prev pointer to the previous segment
+ * @param next pointer to the next segment
+ * @param link_trbs flag to indicate whether to link the trbs or NOT
+ * @return none
+ */
+static void xhci_link_segments(struct xhci_segment *prev,
+ struct xhci_segment *next, bool link_trbs)
+{
+ u32 val;
+ u64 val_64 = 0;
+
+ if (!prev || !next)
+ return;
+ prev->next = next;
+ if (link_trbs) {
+ val_64 = (uintptr_t)next->trbs;
+ prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = val_64;
+
+ /*
+ * Set the last TRB in the segment to
+ * have a TRB type ID of Link TRB
+ */
+ val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
+ val &= ~TRB_TYPE_BITMASK;
+ val |= (TRB_LINK << TRB_TYPE_SHIFT);
+
+ prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
+ }
+}
+
+/**
+ * Initialises the Ring's enqueue,dequeue,enq_seg pointers
+ *
+ * @param ring pointer to the RING to be intialised
+ * @return none
+ */
+static void xhci_initialize_ring_info(struct xhci_ring *ring)
+{
+ /*
+ * The ring is empty, so the enqueue pointer == dequeue pointer
+ */
+ ring->enqueue = ring->first_seg->trbs;
+ ring->enq_seg = ring->first_seg;
+ ring->dequeue = ring->enqueue;
+ ring->deq_seg = ring->first_seg;
+
+ /*
+ * The ring is initialized to 0. The producer must write 1 to the
+ * cycle bit to handover ownership of the TRB, so PCS = 1.
+ * The consumer must compare CCS to the cycle bit to
+ * check ownership, so CCS = 1.
+ */
+ ring->cycle_state = 1;
+}
+
+/**
+ * Allocates a generic ring segment from the ring pool, sets the dma address,
+ * initializes the segment to zero, and sets the private next pointer to NULL.
+ * Section 4.11.1.1:
+ * "All components of all Command and Transfer TRBs shall be initialized to '0'"
+ *
+ * @param none
+ * @return pointer to the newly allocated SEGMENT
+ */
+static struct xhci_segment *xhci_segment_alloc(void)
+{
+ struct xhci_segment *seg;
+
+ seg = (struct xhci_segment *)malloc(sizeof(struct xhci_segment));
+ BUG_ON(!seg);
+
+ seg->trbs = (union xhci_trb *)xhci_malloc(SEGMENT_SIZE);
+
+ seg->next = NULL;
+
+ return seg;
+}
+
+/**
+ * Create a new ring with zero or more segments.
+ * TODO: current code only uses one-time-allocated single-segment rings
+ * of 1KB anyway, so we might as well get rid of all the segment and
+ * linking code (and maybe increase the size a bit, e.g. 4KB).
+ *
+ *
+ * Link each segment together into a ring.
+ * Set the end flag and the cycle toggle bit on the last segment.
+ * See section 4.9.2 and figures 15 and 16 of XHCI spec rev1.0.
+ *
+ * @param num_segs number of segments in the ring
+ * @param link_trbs flag to indicate whether to link the trbs or NOT
+ * @return pointer to the newly created RING
+ */
+struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs)
+{
+ struct xhci_ring *ring;
+ struct xhci_segment *prev;
+
+ ring = (struct xhci_ring *)malloc(sizeof(struct xhci_ring));
+ BUG_ON(!ring);
+
+ if (num_segs == 0)
+ return ring;
+
+ ring->first_seg = xhci_segment_alloc();
+ BUG_ON(!ring->first_seg);
+
+ num_segs--;
+
+ prev = ring->first_seg;
+ while (num_segs > 0) {
+ struct xhci_segment *next;
+
+ next = xhci_segment_alloc();
+ BUG_ON(!next);
+
+ xhci_link_segments(prev, next, link_trbs);
+
+ prev = next;
+ num_segs--;
+ }
+ xhci_link_segments(prev, ring->first_seg, link_trbs);
+ if (link_trbs) {
+ /* See section 4.9.2.1 and 6.4.4.1 */
+ prev->trbs[TRBS_PER_SEGMENT-1].link.control |=
+ cpu_to_le32(LINK_TOGGLE);
+ }
+ xhci_initialize_ring_info(ring);
+
+ return ring;
+}
+
+/**
+ * Allocates the Container context
+ *
+ * @param ctrl Host controller data structure
+ * @param type type of XHCI Container Context
+ * @return NULL if failed else pointer to the context on success
+ */
+static struct xhci_container_ctx
+ *xhci_alloc_container_ctx(struct xhci_ctrl *ctrl, int type)
+{
+ struct xhci_container_ctx *ctx;
+
+ ctx = (struct xhci_container_ctx *)
+ malloc(sizeof(struct xhci_container_ctx));
+ BUG_ON(!ctx);
+
+ BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
+ ctx->type = type;
+ ctx->size = (MAX_EP_CTX_NUM + 1) *
+ CTX_SIZE(readl(&ctrl->hccr->cr_hccparams));
+ if (type == XHCI_CTX_TYPE_INPUT)
+ ctx->size += CTX_SIZE(readl(&ctrl->hccr->cr_hccparams));
+
+ ctx->bytes = (u8 *)xhci_malloc(ctx->size);
+
+ return ctx;
+}
+
+/**
+ * Allocating virtual device
+ *
+ * @param udev pointer to USB deivce structure
+ * @return 0 on success else -1 on failure
+ */
+int xhci_alloc_virt_device(struct usb_device *udev)
+{
+ u64 byte_64 = 0;
+ unsigned int slot_id = udev->slot_id;
+ struct xhci_virt_device *virt_dev;
+ struct xhci_ctrl *ctrl = udev->controller;
+
+ /* Slot ID 0 is reserved */
+ if (ctrl->devs[slot_id]) {
+ printf("Virt dev for slot[%d] already allocated\n", slot_id);
+ return -EEXIST;
+ }
+
+ ctrl->devs[slot_id] = (struct xhci_virt_device *)
+ malloc(sizeof(struct xhci_virt_device));
+
+ if (!ctrl->devs[slot_id]) {
+ puts("Failed to allocate virtual device\n");
+ return -ENOMEM;
+ }
+
+ memset(ctrl->devs[slot_id], 0, sizeof(struct xhci_virt_device));
+ virt_dev = ctrl->devs[slot_id];
+
+ /* Allocate the (output) device context that will be used in the HC. */
+ virt_dev->out_ctx = xhci_alloc_container_ctx(ctrl,
+ XHCI_CTX_TYPE_DEVICE);
+ if (!virt_dev->out_ctx) {
+ puts("Failed to allocate out context for virt dev\n");
+ return -ENOMEM;
+ }
+
+ /* Allocate the (input) device context for address device command */
+ virt_dev->in_ctx = xhci_alloc_container_ctx(ctrl,
+ XHCI_CTX_TYPE_INPUT);
+ if (!virt_dev->in_ctx) {
+ puts("Failed to allocate in context for virt dev\n");
+ return -ENOMEM;
+ }
+
+ /* Allocate endpoint 0 ring */
+ virt_dev->eps[0].ring = xhci_ring_alloc(1, true);
+
+ byte_64 = (uintptr_t)(virt_dev->out_ctx->bytes);
+
+ /* Point to output device context in dcbaa. */
+ ctrl->dcbaa->dev_context_ptrs[slot_id] = byte_64;
+
+ xhci_flush_cache((uint32_t)&ctrl->dcbaa->dev_context_ptrs[slot_id],
+ sizeof(__le64));
+ return 0;
+}
+
+/**
+ * Allocates the necessary data structures
+ * for XHCI host controller
+ *
+ * @param ctrl Host controller data structure
+ * @param hccr pointer to HOST Controller Control Registers
+ * @param hcor pointer to HOST Controller Operational Registers
+ * @return 0 if successful else -1 on failure
+ */
+int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr,
+ struct xhci_hcor *hcor)
+{
+ uint64_t val_64;
+ uint64_t trb_64;
+ uint32_t val;
+ unsigned long deq;
+ int i;
+ struct xhci_segment *seg;
+
+ /* DCBAA initialization */
+ ctrl->dcbaa = (struct xhci_device_context_array *)
+ xhci_malloc(sizeof(struct xhci_device_context_array));
+ if (ctrl->dcbaa == NULL) {
+ puts("unable to allocate DCBA\n");
+ return -ENOMEM;
+ }
+
+ val_64 = (uintptr_t)ctrl->dcbaa;
+ /* Set the pointer in DCBAA register */
+ xhci_writeq(&hcor->or_dcbaap, val_64);
+
+ /* Command ring control pointer register initialization */
+ ctrl->cmd_ring = xhci_ring_alloc(1, true);
+
+ /* Set the address in the Command Ring Control register */
+ trb_64 = (uintptr_t)ctrl->cmd_ring->first_seg->trbs;
+ val_64 = xhci_readq(&hcor->or_crcr);
+ val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
+ (trb_64 & (u64) ~CMD_RING_RSVD_BITS) |
+ ctrl->cmd_ring->cycle_state;
+ xhci_writeq(&hcor->or_crcr, val_64);
+
+ /* write the address of db register */
+ val = xhci_readl(&hccr->cr_dboff);
+ val &= DBOFF_MASK;
+ ctrl->dba = (struct xhci_doorbell_array *)((char *)hccr + val);
+
+ /* write the address of runtime register */
+ val = xhci_readl(&hccr->cr_rtsoff);
+ val &= RTSOFF_MASK;
+ ctrl->run_regs = (struct xhci_run_regs *)((char *)hccr + val);
+
+ /* writting the address of ir_set structure */
+ ctrl->ir_set = &ctrl->run_regs->ir_set[0];
+
+ /* Event ring does not maintain link TRB */
+ ctrl->event_ring = xhci_ring_alloc(ERST_NUM_SEGS, false);
+ ctrl->erst.entries = (struct xhci_erst_entry *)
+ xhci_malloc(sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS);
+
+ ctrl->erst.num_entries = ERST_NUM_SEGS;
+
+ for (val = 0, seg = ctrl->event_ring->first_seg;
+ val < ERST_NUM_SEGS;
+ val++) {
+ trb_64 = 0;
+ trb_64 = (uintptr_t)seg->trbs;
+ struct xhci_erst_entry *entry = &ctrl->erst.entries[val];
+ xhci_writeq(&entry->seg_addr, trb_64);
+ entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
+ entry->rsvd = 0;
+ seg = seg->next;
+ }
+ xhci_flush_cache((uint32_t)ctrl->erst.entries,
+ ERST_NUM_SEGS * sizeof(struct xhci_erst_entry));
+
+ deq = (unsigned long)ctrl->event_ring->dequeue;
+
+ /* Update HC event ring dequeue pointer */
+ xhci_writeq(&ctrl->ir_set->erst_dequeue,
+ (u64)deq & (u64)~ERST_PTR_MASK);
+
+ /* set ERST count with the number of entries in the segment table */
+ val = xhci_readl(&ctrl->ir_set->erst_size);
+ val &= ERST_SIZE_MASK;
+ val |= ERST_NUM_SEGS;
+ xhci_writel(&ctrl->ir_set->erst_size, val);
+
+ /* this is the event ring segment table pointer */
+ val_64 = xhci_readq(&ctrl->ir_set->erst_base);
+ val_64 &= ERST_PTR_MASK;
+ val_64 |= ((u32)(ctrl->erst.entries) & ~ERST_PTR_MASK);
+
+ xhci_writeq(&ctrl->ir_set->erst_base, val_64);
+
+ /* initializing the virtual devices to NULL */
+ for (i = 0; i < MAX_HC_SLOTS; ++i)
+ ctrl->devs[i] = NULL;
+
+ /*
+ * Just Zero'ing this register completely,
+ * or some spurious Device Notification Events
+ * might screw things here.
+ */
+ xhci_writel(&hcor->or_dnctrl, 0x0);
+
+ return 0;
+}
+
+/**
+ * Give the input control context for the passed container context
+ *
+ * @param ctx pointer to the context
+ * @return pointer to the Input control context data
+ */
+struct xhci_input_control_ctx
+ *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx)
+{
+ BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
+ return (struct xhci_input_control_ctx *)ctx->bytes;
+}
+
+/**
+ * Give the slot context for the passed container context
+ *
+ * @param ctrl Host controller data structure
+ * @param ctx pointer to the context
+ * @return pointer to the slot control context data
+ */
+struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl,
+ struct xhci_container_ctx *ctx)
+{
+ if (ctx->type == XHCI_CTX_TYPE_DEVICE)
+ return (struct xhci_slot_ctx *)ctx->bytes;
+
+ return (struct xhci_slot_ctx *)
+ (ctx->bytes + CTX_SIZE(readl(&ctrl->hccr->cr_hccparams)));
+}
+
+/**
+ * Gets the EP context from based on the ep_index
+ *
+ * @param ctrl Host controller data structure
+ * @param ctx context container
+ * @param ep_index index of the endpoint
+ * @return pointer to the End point context
+ */
+struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl,
+ struct xhci_container_ctx *ctx,
+ unsigned int ep_index)
+{
+ /* increment ep index by offset of start of ep ctx array */
+ ep_index++;
+ if (ctx->type == XHCI_CTX_TYPE_INPUT)
+ ep_index++;
+
+ return (struct xhci_ep_ctx *)
+ (ctx->bytes +
+ (ep_index * CTX_SIZE(readl(&ctrl->hccr->cr_hccparams))));
+}
+
+/**
+ * Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
+ * Useful when you want to change one particular aspect of the endpoint
+ * and then issue a configure endpoint command.
+ *
+ * @param ctrl Host controller data structure
+ * @param in_ctx contains the input context
+ * @param out_ctx contains the input context
+ * @param ep_index index of the end point
+ * @return none
+ */
+void xhci_endpoint_copy(struct xhci_ctrl *ctrl,
+ struct xhci_container_ctx *in_ctx,
+ struct xhci_container_ctx *out_ctx,
+ unsigned int ep_index)
+{
+ struct xhci_ep_ctx *out_ep_ctx;
+ struct xhci_ep_ctx *in_ep_ctx;
+
+ out_ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
+ in_ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
+
+ in_ep_ctx->ep_info = out_ep_ctx->ep_info;
+ in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
+ in_ep_ctx->deq = out_ep_ctx->deq;
+ in_ep_ctx->tx_info = out_ep_ctx->tx_info;
+}
+
+/**
+ * Copy output xhci_slot_ctx to the input xhci_slot_ctx.
+ * Useful when you want to change one particular aspect of the endpoint
+ * and then issue a configure endpoint command.
+ * Only the context entries field matters, but
+ * we'll copy the whole thing anyway.
+ *
+ * @param ctrl Host controller data structure
+ * @param in_ctx contains the inpout context
+ * @param out_ctx contains the inpout context
+ * @return none
+ */
+void xhci_slot_copy(struct xhci_ctrl *ctrl, struct xhci_container_ctx *in_ctx,
+ struct xhci_container_ctx *out_ctx)
+{
+ struct xhci_slot_ctx *in_slot_ctx;
+ struct xhci_slot_ctx *out_slot_ctx;
+
+ in_slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
+ out_slot_ctx = xhci_get_slot_ctx(ctrl, out_ctx);
+
+ in_slot_ctx->dev_info = out_slot_ctx->dev_info;
+ in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
+ in_slot_ctx->tt_info = out_slot_ctx->tt_info;
+ in_slot_ctx->dev_state = out_slot_ctx->dev_state;
+}
+
+/**
+ * Setup an xHCI virtual device for a Set Address command
+ *
+ * @param udev pointer to the Device Data Structure
+ * @return returns negative value on failure else 0 on success
+ */
+void xhci_setup_addressable_virt_dev(struct usb_device *udev)
+{
+ struct usb_device *hop = udev;
+ struct xhci_virt_device *virt_dev;
+ struct xhci_ep_ctx *ep0_ctx;
+ struct xhci_slot_ctx *slot_ctx;
+ u32 port_num = 0;
+ u64 trb_64 = 0;
+ struct xhci_ctrl *ctrl = udev->controller;
+
+ virt_dev = ctrl->devs[udev->slot_id];
+
+ BUG_ON(!virt_dev);
+
+ /* Extract the EP0 and Slot Ctrl */
+ ep0_ctx = xhci_get_ep_ctx(ctrl, virt_dev->in_ctx, 0);
+ slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->in_ctx);
+
+ /* Only the control endpoint is valid - one endpoint context */
+ slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | 0);
+
+ switch (udev->speed) {
+ case USB_SPEED_SUPER:
+ slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
+ break;
+ case USB_SPEED_HIGH:
+ slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
+ break;
+ case USB_SPEED_FULL:
+ slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
+ break;
+ case USB_SPEED_LOW:
+ slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
+ break;
+ default:
+ /* Speed was set earlier, this shouldn't happen. */
+ BUG();
+ }
+
+ /* Extract the root hub port number */
+ if (hop->parent)
+ while (hop->parent->parent)
+ hop = hop->parent;
+ port_num = hop->portnr;
+ debug("port_num = %d\n", port_num);
+
+ slot_ctx->dev_info2 |=
+ cpu_to_le32(((port_num & ROOT_HUB_PORT_MASK) <<
+ ROOT_HUB_PORT_SHIFT));
+
+ /* Step 4 - ring already allocated */
+ /* Step 5 */
+ ep0_ctx->ep_info2 = cpu_to_le32(CTRL_EP << EP_TYPE_SHIFT);
+ debug("SPEED = %d\n", udev->speed);
+
+ switch (udev->speed) {
+ case USB_SPEED_SUPER:
+ ep0_ctx->ep_info2 |= cpu_to_le32(((512 & MAX_PACKET_MASK) <<
+ MAX_PACKET_SHIFT));
+ debug("Setting Packet size = 512bytes\n");
+ break;
+ case USB_SPEED_HIGH:
+ /* USB core guesses at a 64-byte max packet first for FS devices */
+ case USB_SPEED_FULL:
+ ep0_ctx->ep_info2 |= cpu_to_le32(((64 & MAX_PACKET_MASK) <<
+ MAX_PACKET_SHIFT));
+ debug("Setting Packet size = 64bytes\n");
+ break;
+ case USB_SPEED_LOW:
+ ep0_ctx->ep_info2 |= cpu_to_le32(((8 & MAX_PACKET_MASK) <<
+ MAX_PACKET_SHIFT));
+ debug("Setting Packet size = 8bytes\n");
+ break;
+ default:
+ /* New speed? */
+ BUG();
+ }
+
+ /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
+ ep0_ctx->ep_info2 |=
+ cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) |
+ ((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT));
+
+ trb_64 = (uintptr_t)virt_dev->eps[0].ring->first_seg->trbs;
+ ep0_ctx->deq = cpu_to_le64(trb_64 | virt_dev->eps[0].ring->cycle_state);
+
+ /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
+
+ xhci_flush_cache((uint32_t)ep0_ctx, sizeof(struct xhci_ep_ctx));
+ xhci_flush_cache((uint32_t)slot_ctx, sizeof(struct xhci_slot_ctx));
+}
--- /dev/null
+/*
+ * OMAP USB HOST xHCI Controller
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm-generic/errno.h>
+#include <asm/omap_common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+
+#include <linux/compat.h>
+#include <linux/usb/dwc3.h>
+#include <linux/usb/xhci-omap.h>
+
+#include "xhci.h"
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct omap_xhci omap;
+
+inline int __board_usb_init(int index, enum board_usb_init_type init)
+{
+ return 0;
+}
+int board_usb_init(int index, enum board_usb_init_type init) \
+ __attribute__((weak, alias("__board_usb_init")));
+
+static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
+{
+ clrsetbits_le32(&dwc3_reg->g_ctl,
+ DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
+ DWC3_GCTL_PRTCAPDIR(mode));
+}
+
+static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
+{
+ /* Before Resetting PHY, put Core in Reset */
+ setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
+
+ omap_reset_usb_phy(dwc3_reg);
+
+ /* After PHYs are stable we can take Core out of reset state */
+ clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
+}
+
+static int dwc3_core_init(struct dwc3 *dwc3_reg)
+{
+ u32 reg;
+ u32 revision;
+ unsigned int dwc3_hwparams1;
+
+ revision = readl(&dwc3_reg->g_snpsid);
+ /* This should read as U3 followed by revision number */
+ if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
+ puts("this is not a DesignWare USB3 DRD Core\n");
+ return -1;
+ }
+
+ dwc3_core_soft_reset(dwc3_reg);
+
+ dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
+
+ reg = readl(&dwc3_reg->g_ctl);
+ reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
+ reg &= ~DWC3_GCTL_DISSCRAMBLE;
+ switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
+ case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
+ reg &= ~DWC3_GCTL_DSBLCLKGTNG;
+ break;
+ default:
+ debug("No power optimization available\n");
+ }
+
+ /*
+ * WORKAROUND: DWC3 revisions <1.90a have a bug
+ * where the device can fail to connect at SuperSpeed
+ * and falls back to high-speed mode which causes
+ * the device to enter a Connect/Disconnect loop
+ */
+ if ((revision & DWC3_REVISION_MASK) < 0x190a)
+ reg |= DWC3_GCTL_U2RSTECN;
+
+ writel(reg, &dwc3_reg->g_ctl);
+
+ return 0;
+}
+
+static int omap_xhci_core_init(struct omap_xhci *omap)
+{
+ int ret = 0;
+
+ omap_enable_phy(omap);
+
+ ret = dwc3_core_init(omap->dwc3_reg);
+ if (ret) {
+ debug("%s:failed to initialize core\n", __func__);
+ return ret;
+ }
+
+ /* We are hard-coding DWC3 core to Host Mode */
+ dwc3_set_mode(omap->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+ return ret;
+}
+
+static void omap_xhci_core_exit(struct omap_xhci *omap)
+{
+ usb_phy_power(0);
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+ struct omap_xhci *ctx = &omap;
+ int ret = 0;
+
+ ctx->hcd = (struct xhci_hccr *)OMAP_XHCI_BASE;
+ ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
+ ctx->usb3_phy = (struct omap_usb3_phy *)OMAP_OCP1_SCP_BASE;
+ ctx->otg_wrapper = (struct omap_dwc_wrapper *)OMAP_OTG_WRAPPER_BASE;
+
+ ret = board_usb_init(index, USB_INIT_HOST);
+ if (ret != 0) {
+ puts("Failed to initialize board for USB\n");
+ return ret;
+ }
+
+ ret = omap_xhci_core_init(ctx);
+ if (ret < 0) {
+ puts("Failed to initialize xhci\n");
+ return ret;
+ }
+
+ *hccr = (struct xhci_hccr *)(OMAP_XHCI_BASE);
+ *hcor = (struct xhci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+ debug("omap-xhci: init hccr %x and hcor %x hc_length %d\n",
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+ return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+ struct omap_xhci *ctx = &omap;
+
+ omap_xhci_core_exit(ctx);
+}
--- /dev/null
+/*
+ * USB HOST XHCI Controller stack
+ *
+ * Based on xHCI host controller driver in linux-kernel
+ * by Sarah Sharp.
+ *
+ * Copyright (C) 2008 Intel Corp.
+ * Author: Sarah Sharp
+ *
+ * Copyright (C) 2013 Samsung Electronics Co.Ltd
+ * Authors: Vivek Gautam <gautam.vivek@samsung.com>
+ * Vikas Sajjan <vikas.sajjan@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/byteorder.h>
+#include <usb.h>
+#include <asm/unaligned.h>
+#include <asm-generic/errno.h>
+
+#include "xhci.h"
+
+/**
+ * Is this TRB a link TRB or was the last TRB the last TRB in this event ring
+ * segment? I.e. would the updated event TRB pointer step off the end of the
+ * event seg ?
+ *
+ * @param ctrl Host controller data structure
+ * @param ring pointer to the ring
+ * @param seg poniter to the segment to which TRB belongs
+ * @param trb poniter to the ring trb
+ * @return 1 if this TRB a link TRB else 0
+ */
+static int last_trb(struct xhci_ctrl *ctrl, struct xhci_ring *ring,
+ struct xhci_segment *seg, union xhci_trb *trb)
+{
+ if (ring == ctrl->event_ring)
+ return trb == &seg->trbs[TRBS_PER_SEGMENT];
+ else
+ return TRB_TYPE_LINK_LE32(trb->link.control);
+}
+
+/**
+ * Does this link TRB point to the first segment in a ring,
+ * or was the previous TRB the last TRB on the last segment in the ERST?
+ *
+ * @param ctrl Host controller data structure
+ * @param ring pointer to the ring
+ * @param seg poniter to the segment to which TRB belongs
+ * @param trb poniter to the ring trb
+ * @return 1 if this TRB is the last TRB on the last segment else 0
+ */
+static bool last_trb_on_last_seg(struct xhci_ctrl *ctrl,
+ struct xhci_ring *ring,
+ struct xhci_segment *seg,
+ union xhci_trb *trb)
+{
+ if (ring == ctrl->event_ring)
+ return ((trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
+ (seg->next == ring->first_seg));
+ else
+ return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
+}
+
+/**
+ * See Cycle bit rules. SW is the consumer for the event ring only.
+ * Don't make a ring full of link TRBs. That would be dumb and this would loop.
+ *
+ * If we've just enqueued a TRB that is in the middle of a TD (meaning the
+ * chain bit is set), then set the chain bit in all the following link TRBs.
+ * If we've enqueued the last TRB in a TD, make sure the following link TRBs
+ * have their chain bit cleared (so that each Link TRB is a separate TD).
+ *
+ * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
+ * set, but other sections talk about dealing with the chain bit set. This was
+ * fixed in the 0.96 specification errata, but we have to assume that all 0.95
+ * xHCI hardware can't handle the chain bit being cleared on a link TRB.
+ *
+ * @param ctrl Host controller data structure
+ * @param ring pointer to the ring
+ * @param more_trbs_coming flag to indicate whether more trbs
+ * are expected or NOT.
+ * Will you enqueue more TRBs before calling
+ * prepare_ring()?
+ * @return none
+ */
+static void inc_enq(struct xhci_ctrl *ctrl, struct xhci_ring *ring,
+ bool more_trbs_coming)
+{
+ u32 chain;
+ union xhci_trb *next;
+
+ chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
+ next = ++(ring->enqueue);
+
+ /*
+ * Update the dequeue pointer further if that was a link TRB or we're at
+ * the end of an event ring segment (which doesn't have link TRBS)
+ */
+ while (last_trb(ctrl, ring, ring->enq_seg, next)) {
+ if (ring != ctrl->event_ring) {
+ /*
+ * If the caller doesn't plan on enqueueing more
+ * TDs before ringing the doorbell, then we
+ * don't want to give the link TRB to the
+ * hardware just yet. We'll give the link TRB
+ * back in prepare_ring() just before we enqueue
+ * the TD at the top of the ring.
+ */
+ if (!chain && !more_trbs_coming)
+ break;
+
+ /*
+ * If we're not dealing with 0.95 hardware or
+ * isoc rings on AMD 0.96 host,
+ * carry over the chain bit of the previous TRB
+ * (which may mean the chain bit is cleared).
+ */
+ next->link.control &= cpu_to_le32(~TRB_CHAIN);
+ next->link.control |= cpu_to_le32(chain);
+
+ next->link.control ^= cpu_to_le32(TRB_CYCLE);
+ xhci_flush_cache((uint32_t)next,
+ sizeof(union xhci_trb));
+ }
+ /* Toggle the cycle bit after the last ring segment. */
+ if (last_trb_on_last_seg(ctrl, ring,
+ ring->enq_seg, next))
+ ring->cycle_state = (ring->cycle_state ? 0 : 1);
+
+ ring->enq_seg = ring->enq_seg->next;
+ ring->enqueue = ring->enq_seg->trbs;
+ next = ring->enqueue;
+ }
+}
+
+/**
+ * See Cycle bit rules. SW is the consumer for the event ring only.
+ * Don't make a ring full of link TRBs. That would be dumb and this would loop.
+ *
+ * @param ctrl Host controller data structure
+ * @param ring Ring whose Dequeue TRB pointer needs to be incremented.
+ * return none
+ */
+static void inc_deq(struct xhci_ctrl *ctrl, struct xhci_ring *ring)
+{
+ do {
+ /*
+ * Update the dequeue pointer further if that was a link TRB or
+ * we're at the end of an event ring segment (which doesn't have
+ * link TRBS)
+ */
+ if (last_trb(ctrl, ring, ring->deq_seg, ring->dequeue)) {
+ if (ring == ctrl->event_ring &&
+ last_trb_on_last_seg(ctrl, ring,
+ ring->deq_seg, ring->dequeue)) {
+ ring->cycle_state = (ring->cycle_state ? 0 : 1);
+ }
+ ring->deq_seg = ring->deq_seg->next;
+ ring->dequeue = ring->deq_seg->trbs;
+ } else {
+ ring->dequeue++;
+ }
+ } while (last_trb(ctrl, ring, ring->deq_seg, ring->dequeue));
+}
+
+/**
+ * Generic function for queueing a TRB on a ring.
+ * The caller must have checked to make sure there's room on the ring.
+ *
+ * @param more_trbs_coming: Will you enqueue more TRBs before calling
+ * prepare_ring()?
+ * @param ctrl Host controller data structure
+ * @param ring pointer to the ring
+ * @param more_trbs_coming flag to indicate whether more trbs
+ * @param trb_fields pointer to trb field array containing TRB contents
+ * @return pointer to the enqueued trb
+ */
+static struct xhci_generic_trb *queue_trb(struct xhci_ctrl *ctrl,
+ struct xhci_ring *ring,
+ bool more_trbs_coming,
+ unsigned int *trb_fields)
+{
+ struct xhci_generic_trb *trb;
+ int i;
+
+ trb = &ring->enqueue->generic;
+
+ for (i = 0; i < 4; i++)
+ trb->field[i] = cpu_to_le32(trb_fields[i]);
+
+ xhci_flush_cache((uint32_t)trb, sizeof(struct xhci_generic_trb));
+
+ inc_enq(ctrl, ring, more_trbs_coming);
+
+ return trb;
+}
+
+/**
+ * Does various checks on the endpoint ring, and makes it ready
+ * to queue num_trbs.
+ *
+ * @param ctrl Host controller data structure
+ * @param ep_ring pointer to the EP Transfer Ring
+ * @param ep_state State of the End Point
+ * @return error code in case of invalid ep_state, 0 on success
+ */
+static int prepare_ring(struct xhci_ctrl *ctrl, struct xhci_ring *ep_ring,
+ u32 ep_state)
+{
+ union xhci_trb *next = ep_ring->enqueue;
+
+ /* Make sure the endpoint has been added to xHC schedule */
+ switch (ep_state) {
+ case EP_STATE_DISABLED:
+ /*
+ * USB core changed config/interfaces without notifying us,
+ * or hardware is reporting the wrong state.
+ */
+ puts("WARN urb submitted to disabled ep\n");
+ return -ENOENT;
+ case EP_STATE_ERROR:
+ puts("WARN waiting for error on ep to be cleared\n");
+ return -EINVAL;
+ case EP_STATE_HALTED:
+ puts("WARN halted endpoint, queueing URB anyway.\n");
+ case EP_STATE_STOPPED:
+ case EP_STATE_RUNNING:
+ debug("EP STATE RUNNING.\n");
+ break;
+ default:
+ puts("ERROR unknown endpoint state for ep\n");
+ return -EINVAL;
+ }
+
+ while (last_trb(ctrl, ep_ring, ep_ring->enq_seg, next)) {
+ /*
+ * If we're not dealing with 0.95 hardware or isoc rings
+ * on AMD 0.96 host, clear the chain bit.
+ */
+ next->link.control &= cpu_to_le32(~TRB_CHAIN);
+
+ next->link.control ^= cpu_to_le32(TRB_CYCLE);
+
+ xhci_flush_cache((uint32_t)next, sizeof(union xhci_trb));
+
+ /* Toggle the cycle bit after the last ring segment. */
+ if (last_trb_on_last_seg(ctrl, ep_ring,
+ ep_ring->enq_seg, next))
+ ep_ring->cycle_state = (ep_ring->cycle_state ? 0 : 1);
+ ep_ring->enq_seg = ep_ring->enq_seg->next;
+ ep_ring->enqueue = ep_ring->enq_seg->trbs;
+ next = ep_ring->enqueue;
+ }
+
+ return 0;
+}
+
+/**
+ * Generic function for queueing a command TRB on the command ring.
+ * Check to make sure there's room on the command ring for one command TRB.
+ *
+ * @param ctrl Host controller data structure
+ * @param ptr Pointer address to write in the first two fields (opt.)
+ * @param slot_id Slot ID to encode in the flags field (opt.)
+ * @param ep_index Endpoint index to encode in the flags field (opt.)
+ * @param cmd Command type to enqueue
+ * @return none
+ */
+void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr, u32 slot_id,
+ u32 ep_index, trb_type cmd)
+{
+ u32 fields[4];
+ u64 val_64 = (uintptr_t)ptr;
+
+ BUG_ON(prepare_ring(ctrl, ctrl->cmd_ring, EP_STATE_RUNNING));
+
+ fields[0] = lower_32_bits(val_64);
+ fields[1] = upper_32_bits(val_64);
+ fields[2] = 0;
+ fields[3] = TRB_TYPE(cmd) | EP_ID_FOR_TRB(ep_index) |
+ SLOT_ID_FOR_TRB(slot_id) | ctrl->cmd_ring->cycle_state;
+
+ queue_trb(ctrl, ctrl->cmd_ring, false, fields);
+
+ /* Ring the command ring doorbell */
+ xhci_writel(&ctrl->dba->doorbell[0], DB_VALUE_HOST);
+}
+
+/**
+ * The TD size is the number of bytes remaining in the TD (including this TRB),
+ * right shifted by 10.
+ * It must fit in bits 21:17, so it can't be bigger than 31.
+ *
+ * @param remainder remaining packets to be sent
+ * @return remainder if remainder is less than max else max
+ */
+static u32 xhci_td_remainder(unsigned int remainder)
+{
+ u32 max = (1 << (21 - 17 + 1)) - 1;
+
+ if ((remainder >> 10) >= max)
+ return max << 17;
+ else
+ return (remainder >> 10) << 17;
+}
+
+/**
+ * Finds out the remanining packets to be sent
+ *
+ * @param running_total total size sent so far
+ * @param trb_buff_len length of the TRB Buffer
+ * @param total_packet_count total packet count
+ * @param maxpacketsize max packet size of current pipe
+ * @param num_trbs_left number of TRBs left to be processed
+ * @return 0 if running_total or trb_buff_len is 0, else remainder
+ */
+static u32 xhci_v1_0_td_remainder(int running_total,
+ int trb_buff_len,
+ unsigned int total_packet_count,
+ int maxpacketsize,
+ unsigned int num_trbs_left)
+{
+ int packets_transferred;
+
+ /* One TRB with a zero-length data packet. */
+ if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
+ return 0;
+
+ /*
+ * All the TRB queueing functions don't count the current TRB in
+ * running_total.
+ */
+ packets_transferred = (running_total + trb_buff_len) / maxpacketsize;
+
+ if ((total_packet_count - packets_transferred) > 31)
+ return 31 << 17;
+ return (total_packet_count - packets_transferred) << 17;
+}
+
+/**
+ * Ring the doorbell of the End Point
+ *
+ * @param udev pointer to the USB device structure
+ * @param ep_index index of the endpoint
+ * @param start_cycle cycle flag of the first TRB
+ * @param start_trb pionter to the first TRB
+ * @return none
+ */
+static void giveback_first_trb(struct usb_device *udev, int ep_index,
+ int start_cycle,
+ struct xhci_generic_trb *start_trb)
+{
+ struct xhci_ctrl *ctrl = udev->controller;
+
+ /*
+ * Pass all the TRBs to the hardware at once and make sure this write
+ * isn't reordered.
+ */
+ if (start_cycle)
+ start_trb->field[3] |= cpu_to_le32(start_cycle);
+ else
+ start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
+
+ xhci_flush_cache((uint32_t)start_trb, sizeof(struct xhci_generic_trb));
+
+ /* Ringing EP doorbell here */
+ xhci_writel(&ctrl->dba->doorbell[udev->slot_id],
+ DB_VALUE(ep_index, 0));
+
+ return;
+}
+
+/**** POLLING mechanism for XHCI ****/
+
+/**
+ * Finalizes a handled event TRB by advancing our dequeue pointer and giving
+ * the TRB back to the hardware for recycling. Must call this exactly once at
+ * the end of each event handler, and not touch the TRB again afterwards.
+ *
+ * @param ctrl Host controller data structure
+ * @return none
+ */
+void xhci_acknowledge_event(struct xhci_ctrl *ctrl)
+{
+ /* Advance our dequeue pointer to the next event */
+ inc_deq(ctrl, ctrl->event_ring);
+
+ /* Inform the hardware */
+ xhci_writeq(&ctrl->ir_set->erst_dequeue,
+ (uintptr_t)ctrl->event_ring->dequeue | ERST_EHB);
+}
+
+/**
+ * Checks if there is a new event to handle on the event ring.
+ *
+ * @param ctrl Host controller data structure
+ * @return 0 if failure else 1 on success
+ */
+static int event_ready(struct xhci_ctrl *ctrl)
+{
+ union xhci_trb *event;
+
+ xhci_inval_cache((uint32_t)ctrl->event_ring->dequeue,
+ sizeof(union xhci_trb));
+
+ event = ctrl->event_ring->dequeue;
+
+ /* Does the HC or OS own the TRB? */
+ if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
+ ctrl->event_ring->cycle_state)
+ return 0;
+
+ return 1;
+}
+
+/**
+ * Waits for a specific type of event and returns it. Discards unexpected
+ * events. Caller *must* call xhci_acknowledge_event() after it is finished
+ * processing the event, and must not access the returned pointer afterwards.
+ *
+ * @param ctrl Host controller data structure
+ * @param expected TRB type expected from Event TRB
+ * @return pointer to event trb
+ */
+union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected)
+{
+ trb_type type;
+ unsigned long ts = get_timer(0);
+
+ do {
+ union xhci_trb *event = ctrl->event_ring->dequeue;
+
+ if (!event_ready(ctrl))
+ continue;
+
+ type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
+ if (type == expected)
+ return event;
+
+ if (type == TRB_PORT_STATUS)
+ /* TODO: remove this once enumeration has been reworked */
+ /*
+ * Port status change events always have a
+ * successful completion code
+ */
+ BUG_ON(GET_COMP_CODE(
+ le32_to_cpu(event->generic.field[2])) !=
+ COMP_SUCCESS);
+ else
+ printf("Unexpected XHCI event TRB, skipping... "
+ "(%08x %08x %08x %08x)\n",
+ le32_to_cpu(event->generic.field[0]),
+ le32_to_cpu(event->generic.field[1]),
+ le32_to_cpu(event->generic.field[2]),
+ le32_to_cpu(event->generic.field[3]));
+
+ xhci_acknowledge_event(ctrl);
+ } while (get_timer(ts) < XHCI_TIMEOUT);
+
+ if (expected == TRB_TRANSFER)
+ return NULL;
+
+ printf("XHCI timeout on event type %d... cannot recover.\n", expected);
+ BUG();
+}
+
+/*
+ * Stops transfer processing for an endpoint and throws away all unprocessed
+ * TRBs by setting the xHC's dequeue pointer to our enqueue pointer. The next
+ * xhci_bulk_tx/xhci_ctrl_tx on this enpoint will add new transfers there and
+ * ring the doorbell, causing this endpoint to start working again.
+ * (Careful: This will BUG() when there was no transfer in progress. Shouldn't
+ * happen in practice for current uses and is too complicated to fix right now.)
+ */
+static void abort_td(struct usb_device *udev, int ep_index)
+{
+ struct xhci_ctrl *ctrl = udev->controller;
+ struct xhci_ring *ring = ctrl->devs[udev->slot_id]->eps[ep_index].ring;
+ union xhci_trb *event;
+ u32 field;
+
+ xhci_queue_command(ctrl, NULL, udev->slot_id, ep_index, TRB_STOP_RING);
+
+ event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
+ field = le32_to_cpu(event->trans_event.flags);
+ BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
+ BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
+ BUG_ON(GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len
+ != COMP_STOP)));
+ xhci_acknowledge_event(ctrl);
+
+ event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
+ != udev->slot_id || GET_COMP_CODE(le32_to_cpu(
+ event->event_cmd.status)) != COMP_SUCCESS);
+ xhci_acknowledge_event(ctrl);
+
+ xhci_queue_command(ctrl, (void *)((uintptr_t)ring->enqueue |
+ ring->cycle_state), udev->slot_id, ep_index, TRB_SET_DEQ);
+ event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
+ != udev->slot_id || GET_COMP_CODE(le32_to_cpu(
+ event->event_cmd.status)) != COMP_SUCCESS);
+ xhci_acknowledge_event(ctrl);
+}
+
+static void record_transfer_result(struct usb_device *udev,
+ union xhci_trb *event, int length)
+{
+ udev->act_len = min(length, length -
+ EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len)));
+
+ switch (GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len))) {
+ case COMP_SUCCESS:
+ BUG_ON(udev->act_len != length);
+ /* fallthrough */
+ case COMP_SHORT_TX:
+ udev->status = 0;
+ break;
+ case COMP_STALL:
+ udev->status = USB_ST_STALLED;
+ break;
+ case COMP_DB_ERR:
+ case COMP_TRB_ERR:
+ udev->status = USB_ST_BUF_ERR;
+ break;
+ case COMP_BABBLE:
+ udev->status = USB_ST_BABBLE_DET;
+ break;
+ default:
+ udev->status = 0x80; /* USB_ST_TOO_LAZY_TO_MAKE_A_NEW_MACRO */
+ }
+}
+
+/**** Bulk and Control transfer methods ****/
+/**
+ * Queues up the BULK Request
+ *
+ * @param udev pointer to the USB device structure
+ * @param pipe contains the DIR_IN or OUT , devnum
+ * @param length length of the buffer
+ * @param buffer buffer to be read/written based on the request
+ * @return returns 0 if successful else -1 on failure
+ */
+int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe,
+ int length, void *buffer)
+{
+ int num_trbs = 0;
+ struct xhci_generic_trb *start_trb;
+ bool first_trb = 0;
+ int start_cycle;
+ u32 field = 0;
+ u32 length_field = 0;
+ struct xhci_ctrl *ctrl = udev->controller;
+ int slot_id = udev->slot_id;
+ int ep_index;
+ struct xhci_virt_device *virt_dev;
+ struct xhci_ep_ctx *ep_ctx;
+ struct xhci_ring *ring; /* EP transfer ring */
+ union xhci_trb *event;
+
+ int running_total, trb_buff_len;
+ unsigned int total_packet_count;
+ int maxpacketsize;
+ u64 addr;
+ int ret;
+ u32 trb_fields[4];
+ u64 val_64 = (uintptr_t)buffer;
+
+ debug("dev=%p, pipe=%lx, buffer=%p, length=%d\n",
+ udev, pipe, buffer, length);
+
+ ep_index = usb_pipe_ep_index(pipe);
+ virt_dev = ctrl->devs[slot_id];
+
+ xhci_inval_cache((uint32_t)virt_dev->out_ctx->bytes,
+ virt_dev->out_ctx->size);
+
+ ep_ctx = xhci_get_ep_ctx(ctrl, virt_dev->out_ctx, ep_index);
+
+ ring = virt_dev->eps[ep_index].ring;
+ /*
+ * How much data is (potentially) left before the 64KB boundary?
+ * XHCI Spec puts restriction( TABLE 49 and 6.4.1 section of XHCI Spec)
+ * that the buffer should not span 64KB boundary. if so
+ * we send request in more than 1 TRB by chaining them.
+ */
+ running_total = TRB_MAX_BUFF_SIZE -
+ (lower_32_bits(val_64) & (TRB_MAX_BUFF_SIZE - 1));
+ trb_buff_len = running_total;
+ running_total &= TRB_MAX_BUFF_SIZE - 1;
+
+ /*
+ * If there's some data on this 64KB chunk, or we have to send a
+ * zero-length transfer, we need at least one TRB
+ */
+ if (running_total != 0 || length == 0)
+ num_trbs++;
+
+ /* How many more 64KB chunks to transfer, how many more TRBs? */
+ while (running_total < length) {
+ num_trbs++;
+ running_total += TRB_MAX_BUFF_SIZE;
+ }
+
+ /*
+ * XXX: Calling routine prepare_ring() called in place of
+ * prepare_trasfer() as there in 'Linux' since we are not
+ * maintaining multiple TDs/transfer at the same time.
+ */
+ ret = prepare_ring(ctrl, ring,
+ le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * Don't give the first TRB to the hardware (by toggling the cycle bit)
+ * until we've finished creating all the other TRBs. The ring's cycle
+ * state may change as we enqueue the other TRBs, so save it too.
+ */
+ start_trb = &ring->enqueue->generic;
+ start_cycle = ring->cycle_state;
+
+ running_total = 0;
+ maxpacketsize = usb_maxpacket(udev, pipe);
+
+ total_packet_count = DIV_ROUND_UP(length, maxpacketsize);
+
+ /* How much data is in the first TRB? */
+ /*
+ * How much data is (potentially) left before the 64KB boundary?
+ * XHCI Spec puts restriction( TABLE 49 and 6.4.1 section of XHCI Spec)
+ * that the buffer should not span 64KB boundary. if so
+ * we send request in more than 1 TRB by chaining them.
+ */
+ addr = val_64;
+
+ if (trb_buff_len > length)
+ trb_buff_len = length;
+
+ first_trb = true;
+
+ /* flush the buffer before use */
+ xhci_flush_cache((uint32_t)buffer, length);
+
+ /* Queue the first TRB, even if it's zero-length */
+ do {
+ u32 remainder = 0;
+ field = 0;
+ /* Don't change the cycle bit of the first TRB until later */
+ if (first_trb) {
+ first_trb = false;
+ if (start_cycle == 0)
+ field |= TRB_CYCLE;
+ } else {
+ field |= ring->cycle_state;
+ }
+
+ /*
+ * Chain all the TRBs together; clear the chain bit in the last
+ * TRB to indicate it's the last TRB in the chain.
+ */
+ if (num_trbs > 1)
+ field |= TRB_CHAIN;
+ else
+ field |= TRB_IOC;
+
+ /* Only set interrupt on short packet for IN endpoints */
+ if (usb_pipein(pipe))
+ field |= TRB_ISP;
+
+ /* Set the TRB length, TD size, and interrupter fields. */
+ if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) < 0x100)
+ remainder = xhci_td_remainder(length - running_total);
+ else
+ remainder = xhci_v1_0_td_remainder(running_total,
+ trb_buff_len,
+ total_packet_count,
+ maxpacketsize,
+ num_trbs - 1);
+
+ length_field = ((trb_buff_len & TRB_LEN_MASK) |
+ remainder |
+ ((0 & TRB_INTR_TARGET_MASK) <<
+ TRB_INTR_TARGET_SHIFT));
+
+ trb_fields[0] = lower_32_bits(addr);
+ trb_fields[1] = upper_32_bits(addr);
+ trb_fields[2] = length_field;
+ trb_fields[3] = field | (TRB_NORMAL << TRB_TYPE_SHIFT);
+
+ queue_trb(ctrl, ring, (num_trbs > 1), trb_fields);
+
+ --num_trbs;
+
+ running_total += trb_buff_len;
+
+ /* Calculate length for next transfer */
+ addr += trb_buff_len;
+ trb_buff_len = min((length - running_total), TRB_MAX_BUFF_SIZE);
+ } while (running_total < length);
+
+ giveback_first_trb(udev, ep_index, start_cycle, start_trb);
+
+ event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
+ if (!event) {
+ debug("XHCI bulk transfer timed out, aborting...\n");
+ abort_td(udev, ep_index);
+ udev->status = USB_ST_NAK_REC; /* closest thing to a timeout */
+ udev->act_len = 0;
+ return -ETIMEDOUT;
+ }
+ field = le32_to_cpu(event->trans_event.flags);
+
+ BUG_ON(TRB_TO_SLOT_ID(field) != slot_id);
+ BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
+ BUG_ON(*(void **)(uintptr_t)le64_to_cpu(event->trans_event.buffer) -
+ buffer > (size_t)length);
+
+ record_transfer_result(udev, event, length);
+ xhci_acknowledge_event(ctrl);
+ xhci_inval_cache((uint32_t)buffer, length);
+
+ return (udev->status != USB_ST_NOT_PROC) ? 0 : -1;
+}
+
+/**
+ * Queues up the Control Transfer Request
+ *
+ * @param udev pointer to the USB device structure
+ * @param pipe contains the DIR_IN or OUT , devnum
+ * @param req request type
+ * @param length length of the buffer
+ * @param buffer buffer to be read/written based on the request
+ * @return returns 0 if successful else error code on failure
+ */
+int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe,
+ struct devrequest *req, int length,
+ void *buffer)
+{
+ int ret;
+ int start_cycle;
+ int num_trbs;
+ u32 field;
+ u32 length_field;
+ u64 buf_64 = 0;
+ struct xhci_generic_trb *start_trb;
+ struct xhci_ctrl *ctrl = udev->controller;
+ int slot_id = udev->slot_id;
+ int ep_index;
+ u32 trb_fields[4];
+ struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
+ struct xhci_ring *ep_ring;
+ union xhci_trb *event;
+
+ debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
+ req->request, req->request,
+ req->requesttype, req->requesttype,
+ le16_to_cpu(req->value), le16_to_cpu(req->value),
+ le16_to_cpu(req->index));
+
+ ep_index = usb_pipe_ep_index(pipe);
+
+ ep_ring = virt_dev->eps[ep_index].ring;
+
+ /*
+ * Check to see if the max packet size for the default control
+ * endpoint changed during FS device enumeration
+ */
+ if (udev->speed == USB_SPEED_FULL) {
+ ret = xhci_check_maxpacket(udev);
+ if (ret < 0)
+ return ret;
+ }
+
+ xhci_inval_cache((uint32_t)virt_dev->out_ctx->bytes,
+ virt_dev->out_ctx->size);
+
+ struct xhci_ep_ctx *ep_ctx = NULL;
+ ep_ctx = xhci_get_ep_ctx(ctrl, virt_dev->out_ctx, ep_index);
+
+ /* 1 TRB for setup, 1 for status */
+ num_trbs = 2;
+ /*
+ * Don't need to check if we need additional event data and normal TRBs,
+ * since data in control transfers will never get bigger than 16MB
+ * XXX: can we get a buffer that crosses 64KB boundaries?
+ */
+
+ if (length > 0)
+ num_trbs++;
+ /*
+ * XXX: Calling routine prepare_ring() called in place of
+ * prepare_trasfer() as there in 'Linux' since we are not
+ * maintaining multiple TDs/transfer at the same time.
+ */
+ ret = prepare_ring(ctrl, ep_ring,
+ le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK);
+
+ if (ret < 0)
+ return ret;
+
+ /*
+ * Don't give the first TRB to the hardware (by toggling the cycle bit)
+ * until we've finished creating all the other TRBs. The ring's cycle
+ * state may change as we enqueue the other TRBs, so save it too.
+ */
+ start_trb = &ep_ring->enqueue->generic;
+ start_cycle = ep_ring->cycle_state;
+
+ debug("start_trb %p, start_cycle %d\n", start_trb, start_cycle);
+
+ /* Queue setup TRB - see section 6.4.1.2.1 */
+ /* FIXME better way to translate setup_packet into two u32 fields? */
+ field = 0;
+ field |= TRB_IDT | (TRB_SETUP << TRB_TYPE_SHIFT);
+ if (start_cycle == 0)
+ field |= 0x1;
+
+ /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
+ if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) == 0x100) {
+ if (length > 0) {
+ if (req->requesttype & USB_DIR_IN)
+ field |= (TRB_DATA_IN << TRB_TX_TYPE_SHIFT);
+ else
+ field |= (TRB_DATA_OUT << TRB_TX_TYPE_SHIFT);
+ }
+ }
+
+ debug("req->requesttype = %d, req->request = %d,"
+ "le16_to_cpu(req->value) = %d,"
+ "le16_to_cpu(req->index) = %d,"
+ "le16_to_cpu(req->length) = %d\n",
+ req->requesttype, req->request, le16_to_cpu(req->value),
+ le16_to_cpu(req->index), le16_to_cpu(req->length));
+
+ trb_fields[0] = req->requesttype | req->request << 8 |
+ le16_to_cpu(req->value) << 16;
+ trb_fields[1] = le16_to_cpu(req->index) |
+ le16_to_cpu(req->length) << 16;
+ /* TRB_LEN | (TRB_INTR_TARGET) */
+ trb_fields[2] = (8 | ((0 & TRB_INTR_TARGET_MASK) <<
+ TRB_INTR_TARGET_SHIFT));
+ /* Immediate data in pointer */
+ trb_fields[3] = field;
+ queue_trb(ctrl, ep_ring, true, trb_fields);
+
+ /* Re-initializing field to zero */
+ field = 0;
+ /* If there's data, queue data TRBs */
+ /* Only set interrupt on short packet for IN endpoints */
+ if (usb_pipein(pipe))
+ field = TRB_ISP | (TRB_DATA << TRB_TYPE_SHIFT);
+ else
+ field = (TRB_DATA << TRB_TYPE_SHIFT);
+
+ length_field = (length & TRB_LEN_MASK) | xhci_td_remainder(length) |
+ ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT);
+ debug("length_field = %d, length = %d,"
+ "xhci_td_remainder(length) = %d , TRB_INTR_TARGET(0) = %d\n",
+ length_field, (length & TRB_LEN_MASK),
+ xhci_td_remainder(length), 0);
+
+ if (length > 0) {
+ if (req->requesttype & USB_DIR_IN)
+ field |= TRB_DIR_IN;
+ buf_64 = (uintptr_t)buffer;
+
+ trb_fields[0] = lower_32_bits(buf_64);
+ trb_fields[1] = upper_32_bits(buf_64);
+ trb_fields[2] = length_field;
+ trb_fields[3] = field | ep_ring->cycle_state;
+
+ xhci_flush_cache((uint32_t)buffer, length);
+ queue_trb(ctrl, ep_ring, true, trb_fields);
+ }
+
+ /*
+ * Queue status TRB -
+ * see Table 7 and sections 4.11.2.2 and 6.4.1.2.3
+ */
+
+ /* If the device sent data, the status stage is an OUT transfer */
+ field = 0;
+ if (length > 0 && req->requesttype & USB_DIR_IN)
+ field = 0;
+ else
+ field = TRB_DIR_IN;
+
+ trb_fields[0] = 0;
+ trb_fields[1] = 0;
+ trb_fields[2] = ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT);
+ /* Event on completion */
+ trb_fields[3] = field | TRB_IOC |
+ (TRB_STATUS << TRB_TYPE_SHIFT) |
+ ep_ring->cycle_state;
+
+ queue_trb(ctrl, ep_ring, false, trb_fields);
+
+ giveback_first_trb(udev, ep_index, start_cycle, start_trb);
+
+ event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
+ if (!event)
+ goto abort;
+ field = le32_to_cpu(event->trans_event.flags);
+
+ BUG_ON(TRB_TO_SLOT_ID(field) != slot_id);
+ BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
+
+ record_transfer_result(udev, event, length);
+ xhci_acknowledge_event(ctrl);
+
+ /* Invalidate buffer to make it available to usb-core */
+ if (length > 0)
+ xhci_inval_cache((uint32_t)buffer, length);
+
+ if (GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len))
+ == COMP_SHORT_TX) {
+ /* Short data stage, clear up additional status stage event */
+ event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
+ if (!event)
+ goto abort;
+ BUG_ON(TRB_TO_SLOT_ID(field) != slot_id);
+ BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
+ xhci_acknowledge_event(ctrl);
+ }
+
+ return (udev->status != USB_ST_NOT_PROC) ? 0 : -1;
+
+abort:
+ debug("XHCI control transfer timed out, aborting...\n");
+ abort_td(udev, ep_index);
+ udev->status = USB_ST_NAK_REC;
+ udev->act_len = 0;
+ return -ETIMEDOUT;
+}
--- /dev/null
+/*
+ * USB HOST XHCI Controller stack
+ *
+ * Based on xHCI host controller driver in linux-kernel
+ * by Sarah Sharp.
+ *
+ * Copyright (C) 2008 Intel Corp.
+ * Author: Sarah Sharp
+ *
+ * Copyright (C) 2013 Samsung Electronics Co.Ltd
+ * Authors: Vivek Gautam <gautam.vivek@samsung.com>
+ * Vikas Sajjan <vikas.sajjan@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/**
+ * This file gives the xhci stack for usb3.0 looking into
+ * xhci specification Rev1.0 (5/21/10).
+ * The quirk devices support hasn't been given yet.
+ */
+
+#include <common.h>
+#include <asm/byteorder.h>
+#include <usb.h>
+#include <malloc.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+#include <asm/unaligned.h>
+#include <asm-generic/errno.h>
+#include "xhci.h"
+
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
+static struct descriptor {
+ struct usb_hub_descriptor hub;
+ struct usb_device_descriptor device;
+ struct usb_config_descriptor config;
+ struct usb_interface_descriptor interface;
+ struct usb_endpoint_descriptor endpoint;
+ struct usb_ss_ep_comp_descriptor ep_companion;
+} __attribute__ ((packed)) descriptor = {
+ {
+ 0xc, /* bDescLength */
+ 0x2a, /* bDescriptorType: hub descriptor */
+ 2, /* bNrPorts -- runtime modified */
+ cpu_to_le16(0x8), /* wHubCharacteristics */
+ 10, /* bPwrOn2PwrGood */
+ 0, /* bHubCntrCurrent */
+ {}, /* Device removable */
+ {} /* at most 7 ports! XXX */
+ },
+ {
+ 0x12, /* bLength */
+ 1, /* bDescriptorType: UDESC_DEVICE */
+ cpu_to_le16(0x0300), /* bcdUSB: v3.0 */
+ 9, /* bDeviceClass: UDCLASS_HUB */
+ 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
+ 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */
+ 9, /* bMaxPacketSize: 512 bytes 2^9 */
+ 0x0000, /* idVendor */
+ 0x0000, /* idProduct */
+ cpu_to_le16(0x0100), /* bcdDevice */
+ 1, /* iManufacturer */
+ 2, /* iProduct */
+ 0, /* iSerialNumber */
+ 1 /* bNumConfigurations: 1 */
+ },
+ {
+ 0x9,
+ 2, /* bDescriptorType: UDESC_CONFIG */
+ cpu_to_le16(0x1f), /* includes SS endpoint descriptor */
+ 1, /* bNumInterface */
+ 1, /* bConfigurationValue */
+ 0, /* iConfiguration */
+ 0x40, /* bmAttributes: UC_SELF_POWER */
+ 0 /* bMaxPower */
+ },
+ {
+ 0x9, /* bLength */
+ 4, /* bDescriptorType: UDESC_INTERFACE */
+ 0, /* bInterfaceNumber */
+ 0, /* bAlternateSetting */
+ 1, /* bNumEndpoints */
+ 9, /* bInterfaceClass: UICLASS_HUB */
+ 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
+ 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
+ 0 /* iInterface */
+ },
+ {
+ 0x7, /* bLength */
+ 5, /* bDescriptorType: UDESC_ENDPOINT */
+ 0x81, /* bEndpointAddress: IN endpoint 1 */
+ 3, /* bmAttributes: UE_INTERRUPT */
+ 8, /* wMaxPacketSize */
+ 255 /* bInterval */
+ },
+ {
+ 0x06, /* ss_bLength */
+ 0x30, /* ss_bDescriptorType: SS EP Companion */
+ 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */
+ /* ss_bmAttributes: 1 packet per service interval */
+ 0x00,
+ /* ss_wBytesPerInterval: 15 bits for max 15 ports */
+ cpu_to_le16(0x02),
+ },
+};
+
+static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
+
+/**
+ * Waits for as per specified amount of time
+ * for the "result" to match with "done"
+ *
+ * @param ptr pointer to the register to be read
+ * @param mask mask for the value read
+ * @param done value to be campared with result
+ * @param usec time to wait till
+ * @return 0 if handshake is success else < 0 on failure
+ */
+static int handshake(uint32_t volatile *ptr, uint32_t mask,
+ uint32_t done, int usec)
+{
+ uint32_t result;
+
+ do {
+ result = xhci_readl(ptr);
+ if (result == ~(uint32_t)0)
+ return -ENODEV;
+ result &= mask;
+ if (result == done)
+ return 0;
+ usec--;
+ udelay(1);
+ } while (usec > 0);
+
+ return -ETIMEDOUT;
+}
+
+/**
+ * Set the run bit and wait for the host to be running.
+ *
+ * @param hcor pointer to host controller operation registers
+ * @return status of the Handshake
+ */
+static int xhci_start(struct xhci_hcor *hcor)
+{
+ u32 temp;
+ int ret;
+
+ puts("Starting the controller\n");
+ temp = xhci_readl(&hcor->or_usbcmd);
+ temp |= (CMD_RUN);
+ xhci_writel(&hcor->or_usbcmd, temp);
+
+ /*
+ * Wait for the HCHalted Status bit to be 0 to indicate the host is
+ * running.
+ */
+ ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC);
+ if (ret)
+ debug("Host took too long to start, "
+ "waited %u microseconds.\n",
+ XHCI_MAX_HALT_USEC);
+ return ret;
+}
+
+/**
+ * Resets the XHCI Controller
+ *
+ * @param hcor pointer to host controller operation registers
+ * @return -EBUSY if XHCI Controller is not halted else status of handshake
+ */
+int xhci_reset(struct xhci_hcor *hcor)
+{
+ u32 cmd;
+ u32 state;
+ int ret;
+
+ /* Halting the Host first */
+ debug("// Halt the HC\n");
+ state = xhci_readl(&hcor->or_usbsts) & STS_HALT;
+ if (!state) {
+ cmd = xhci_readl(&hcor->or_usbcmd);
+ cmd &= ~CMD_RUN;
+ xhci_writel(&hcor->or_usbcmd, cmd);
+ }
+
+ ret = handshake(&hcor->or_usbsts,
+ STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
+ if (ret) {
+ printf("Host not halted after %u microseconds.\n",
+ XHCI_MAX_HALT_USEC);
+ return -EBUSY;
+ }
+
+ debug("// Reset the HC\n");
+ cmd = xhci_readl(&hcor->or_usbcmd);
+ cmd |= CMD_RESET;
+ xhci_writel(&hcor->or_usbcmd, cmd);
+
+ ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC);
+ if (ret)
+ return ret;
+
+ /*
+ * xHCI cannot write to any doorbells or operational registers other
+ * than status until the "Controller Not Ready" flag is cleared.
+ */
+ return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC);
+}
+
+/**
+ * Used for passing endpoint bitmasks between the core and HCDs.
+ * Find the index for an endpoint given its descriptor.
+ * Use the return value to right shift 1 for the bitmask.
+ *
+ * Index = (epnum * 2) + direction - 1,
+ * where direction = 0 for OUT, 1 for IN.
+ * For control endpoints, the IN index is used (OUT index is unused), so
+ * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
+ *
+ * @param desc USB enpdoint Descriptor
+ * @return index of the Endpoint
+ */
+static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc)
+{
+ unsigned int index;
+
+ if (usb_endpoint_xfer_control(desc))
+ index = (unsigned int)(usb_endpoint_num(desc) * 2);
+ else
+ index = (unsigned int)((usb_endpoint_num(desc) * 2) -
+ (usb_endpoint_dir_in(desc) ? 0 : 1));
+
+ return index;
+}
+
+/**
+ * Issue a configure endpoint command or evaluate context command
+ * and wait for it to finish.
+ *
+ * @param udev pointer to the Device Data Structure
+ * @param ctx_change flag to indicate the Context has changed or NOT
+ * @return 0 on success, -1 on failure
+ */
+static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change)
+{
+ struct xhci_container_ctx *in_ctx;
+ struct xhci_virt_device *virt_dev;
+ struct xhci_ctrl *ctrl = udev->controller;
+ union xhci_trb *event;
+
+ virt_dev = ctrl->devs[udev->slot_id];
+ in_ctx = virt_dev->in_ctx;
+
+ xhci_flush_cache((uint32_t)in_ctx->bytes, in_ctx->size);
+ xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0,
+ ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
+ event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
+ != udev->slot_id);
+
+ switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
+ case COMP_SUCCESS:
+ debug("Successful %s command\n",
+ ctx_change ? "Evaluate Context" : "Configure Endpoint");
+ break;
+ default:
+ printf("ERROR: %s command returned completion code %d.\n",
+ ctx_change ? "Evaluate Context" : "Configure Endpoint",
+ GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
+ return -EINVAL;
+ }
+
+ xhci_acknowledge_event(ctrl);
+
+ return 0;
+}
+
+/**
+ * Configure the endpoint, programming the device contexts.
+ *
+ * @param udev pointer to the USB device structure
+ * @return returns the status of the xhci_configure_endpoints
+ */
+static int xhci_set_configuration(struct usb_device *udev)
+{
+ struct xhci_container_ctx *in_ctx;
+ struct xhci_container_ctx *out_ctx;
+ struct xhci_input_control_ctx *ctrl_ctx;
+ struct xhci_slot_ctx *slot_ctx;
+ struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM];
+ int cur_ep;
+ int max_ep_flag = 0;
+ int ep_index;
+ unsigned int dir;
+ unsigned int ep_type;
+ struct xhci_ctrl *ctrl = udev->controller;
+ int num_of_ep;
+ int ep_flag = 0;
+ u64 trb_64 = 0;
+ int slot_id = udev->slot_id;
+ struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
+ struct usb_interface *ifdesc;
+
+ out_ctx = virt_dev->out_ctx;
+ in_ctx = virt_dev->in_ctx;
+
+ num_of_ep = udev->config.if_desc[0].no_of_ep;
+ ifdesc = &udev->config.if_desc[0];
+
+ ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
+ /* Zero the input context control */
+ ctrl_ctx->add_flags = 0;
+ ctrl_ctx->drop_flags = 0;
+
+ /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
+ for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
+ ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]);
+ ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
+ if (max_ep_flag < ep_flag)
+ max_ep_flag = ep_flag;
+ }
+
+ xhci_inval_cache((uint32_t)out_ctx->bytes, out_ctx->size);
+
+ /* slot context */
+ xhci_slot_copy(ctrl, in_ctx, out_ctx);
+ slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
+ slot_ctx->dev_info &= ~(LAST_CTX_MASK);
+ slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0);
+
+ xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
+
+ /* filling up ep contexts */
+ for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
+ struct usb_endpoint_descriptor *endpt_desc = NULL;
+
+ endpt_desc = &ifdesc->ep_desc[cur_ep];
+ trb_64 = 0;
+
+ ep_index = xhci_get_ep_index(endpt_desc);
+ ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
+
+ /* Allocate the ep rings */
+ virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true);
+ if (!virt_dev->eps[ep_index].ring)
+ return -ENOMEM;
+
+ /*NOTE: ep_desc[0] actually represents EP1 and so on */
+ dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7);
+ ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2));
+ ep_ctx[ep_index]->ep_info2 =
+ cpu_to_le32(ep_type << EP_TYPE_SHIFT);
+ ep_ctx[ep_index]->ep_info2 |=
+ cpu_to_le32(MAX_PACKET
+ (get_unaligned(&endpt_desc->wMaxPacketSize)));
+
+ ep_ctx[ep_index]->ep_info2 |=
+ cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) |
+ ((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT));
+
+ trb_64 = (uintptr_t)
+ virt_dev->eps[ep_index].ring->enqueue;
+ ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 |
+ virt_dev->eps[ep_index].ring->cycle_state);
+ }
+
+ return xhci_configure_endpoints(udev, false);
+}
+
+/**
+ * Issue an Address Device command (which will issue a SetAddress request to
+ * the device).
+ *
+ * @param udev pointer to the Device Data Structure
+ * @return 0 if successful else error code on failure
+ */
+static int xhci_address_device(struct usb_device *udev)
+{
+ int ret = 0;
+ struct xhci_ctrl *ctrl = udev->controller;
+ struct xhci_slot_ctx *slot_ctx;
+ struct xhci_input_control_ctx *ctrl_ctx;
+ struct xhci_virt_device *virt_dev;
+ int slot_id = udev->slot_id;
+ union xhci_trb *event;
+
+ virt_dev = ctrl->devs[slot_id];
+
+ /*
+ * This is the first Set Address since device plug-in
+ * so setting up the slot context.
+ */
+ debug("Setting up addressable devices\n");
+ xhci_setup_addressable_virt_dev(udev);
+
+ ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
+ ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
+ ctrl_ctx->drop_flags = 0;
+
+ xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV);
+ event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
+
+ switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
+ case COMP_CTX_STATE:
+ case COMP_EBADSLT:
+ printf("Setup ERROR: address device command for slot %d.\n",
+ slot_id);
+ ret = -EINVAL;
+ break;
+ case COMP_TX_ERR:
+ puts("Device not responding to set address.\n");
+ ret = -EPROTO;
+ break;
+ case COMP_DEV_ERR:
+ puts("ERROR: Incompatible device"
+ "for address device command.\n");
+ ret = -ENODEV;
+ break;
+ case COMP_SUCCESS:
+ debug("Successful Address Device command\n");
+ udev->status = 0;
+ break;
+ default:
+ printf("ERROR: unexpected command completion code 0x%x.\n",
+ GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
+ ret = -EINVAL;
+ break;
+ }
+
+ xhci_acknowledge_event(ctrl);
+
+ if (ret < 0)
+ /*
+ * TODO: Unsuccessful Address Device command shall leave the
+ * slot in default state. So, issue Disable Slot command now.
+ */
+ return ret;
+
+ xhci_inval_cache((uint32_t)virt_dev->out_ctx->bytes,
+ virt_dev->out_ctx->size);
+ slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx);
+
+ debug("xHC internal address is: %d\n",
+ le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
+
+ return 0;
+}
+
+/**
+ * Issue Enable slot command to the controller to allocate
+ * device slot and assign the slot id. It fails if the xHC
+ * ran out of device slots, the Enable Slot command timed out,
+ * or allocating memory failed.
+ *
+ * @param udev pointer to the Device Data Structure
+ * @return Returns 0 on succes else return error code on failure
+ */
+int usb_alloc_device(struct usb_device *udev)
+{
+ union xhci_trb *event;
+ struct xhci_ctrl *ctrl = udev->controller;
+ int ret;
+
+ /*
+ * Root hub will be first device to be initailized.
+ * If this device is root-hub, don't do any xHC related
+ * stuff.
+ */
+ if (ctrl->rootdev == 0) {
+ udev->speed = USB_SPEED_SUPER;
+ return 0;
+ }
+
+ xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT);
+ event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
+ != COMP_SUCCESS);
+
+ udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags));
+
+ xhci_acknowledge_event(ctrl);
+
+ ret = xhci_alloc_virt_device(udev);
+ if (ret < 0) {
+ /*
+ * TODO: Unsuccessful Address Device command shall leave
+ * the slot in default. So, issue Disable Slot command now.
+ */
+ puts("Could not allocate xHCI USB device data structures\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+/*
+ * Full speed devices may have a max packet size greater than 8 bytes, but the
+ * USB core doesn't know that until it reads the first 8 bytes of the
+ * descriptor. If the usb_device's max packet size changes after that point,
+ * we need to issue an evaluate context command and wait on it.
+ *
+ * @param udev pointer to the Device Data Structure
+ * @return returns the status of the xhci_configure_endpoints
+ */
+int xhci_check_maxpacket(struct usb_device *udev)
+{
+ struct xhci_ctrl *ctrl = udev->controller;
+ unsigned int slot_id = udev->slot_id;
+ int ep_index = 0; /* control endpoint */
+ struct xhci_container_ctx *in_ctx;
+ struct xhci_container_ctx *out_ctx;
+ struct xhci_input_control_ctx *ctrl_ctx;
+ struct xhci_ep_ctx *ep_ctx;
+ int max_packet_size;
+ int hw_max_packet_size;
+ int ret = 0;
+ struct usb_interface *ifdesc;
+
+ ifdesc = &udev->config.if_desc[0];
+
+ out_ctx = ctrl->devs[slot_id]->out_ctx;
+ xhci_inval_cache((uint32_t)out_ctx->bytes, out_ctx->size);
+
+ ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
+ hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
+ max_packet_size = usb_endpoint_maxp(&ifdesc->ep_desc[0]);
+ if (hw_max_packet_size != max_packet_size) {
+ debug("Max Packet Size for ep 0 changed.\n");
+ debug("Max packet size in usb_device = %d\n", max_packet_size);
+ debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size);
+ debug("Issuing evaluate context command.\n");
+
+ /* Set up the modified control endpoint 0 */
+ xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx,
+ ctrl->devs[slot_id]->out_ctx, ep_index);
+ in_ctx = ctrl->devs[slot_id]->in_ctx;
+ ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
+ ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
+ ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
+
+ /*
+ * Set up the input context flags for the command
+ * FIXME: This won't work if a non-default control endpoint
+ * changes max packet sizes.
+ */
+ ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
+ ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
+ ctrl_ctx->drop_flags = 0;
+
+ ret = xhci_configure_endpoints(udev, true);
+ }
+ return ret;
+}
+
+/**
+ * Clears the Change bits of the Port Status Register
+ *
+ * @param wValue request value
+ * @param wIndex request index
+ * @param addr address of posrt status register
+ * @param port_status state of port status register
+ * @return none
+ */
+static void xhci_clear_port_change_bit(u16 wValue,
+ u16 wIndex, volatile uint32_t *addr, u32 port_status)
+{
+ char *port_change_bit;
+ u32 status;
+
+ switch (wValue) {
+ case USB_PORT_FEAT_C_RESET:
+ status = PORT_RC;
+ port_change_bit = "reset";
+ break;
+ case USB_PORT_FEAT_C_CONNECTION:
+ status = PORT_CSC;
+ port_change_bit = "connect";
+ break;
+ case USB_PORT_FEAT_C_OVER_CURRENT:
+ status = PORT_OCC;
+ port_change_bit = "over-current";
+ break;
+ case USB_PORT_FEAT_C_ENABLE:
+ status = PORT_PEC;
+ port_change_bit = "enable/disable";
+ break;
+ case USB_PORT_FEAT_C_SUSPEND:
+ status = PORT_PLC;
+ port_change_bit = "suspend/resume";
+ break;
+ default:
+ /* Should never happen */
+ return;
+ }
+
+ /* Change bits are all write 1 to clear */
+ xhci_writel(addr, port_status | status);
+
+ port_status = xhci_readl(addr);
+ debug("clear port %s change, actual port %d status = 0x%x\n",
+ port_change_bit, wIndex, port_status);
+}
+
+/**
+ * Save Read Only (RO) bits and save read/write bits where
+ * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
+ * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
+ *
+ * @param state state of the Port Status and Control Regsiter
+ * @return a value that would result in the port being in the
+ * same state, if the value was written to the port
+ * status control register.
+ */
+static u32 xhci_port_state_to_neutral(u32 state)
+{
+ /* Save read-only status and port state */
+ return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
+}
+
+/**
+ * Submits the Requests to the XHCI Host Controller
+ *
+ * @param udev pointer to the USB device structure
+ * @param pipe contains the DIR_IN or OUT , devnum
+ * @param buffer buffer to be read/written based on the request
+ * @return returns 0 if successful else -1 on failure
+ */
+static int xhci_submit_root(struct usb_device *udev, unsigned long pipe,
+ void *buffer, struct devrequest *req)
+{
+ uint8_t tmpbuf[4];
+ u16 typeReq;
+ void *srcptr = NULL;
+ int len, srclen;
+ uint32_t reg;
+ volatile uint32_t *status_reg;
+ struct xhci_ctrl *ctrl = udev->controller;
+ struct xhci_hcor *hcor = ctrl->hcor;
+
+ if (((req->requesttype & USB_RT_PORT) &&
+ le16_to_cpu(req->index)) > CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) {
+ printf("The request port(%d) is not configured\n",
+ le16_to_cpu(req->index) - 1);
+ return -EINVAL;
+ }
+
+ status_reg = (volatile uint32_t *)
+ (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc);
+ srclen = 0;
+
+ typeReq = req->request | req->requesttype << 8;
+
+ switch (typeReq) {
+ case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
+ switch (le16_to_cpu(req->value) >> 8) {
+ case USB_DT_DEVICE:
+ debug("USB_DT_DEVICE request\n");
+ srcptr = &descriptor.device;
+ srclen = 0x12;
+ break;
+ case USB_DT_CONFIG:
+ debug("USB_DT_CONFIG config\n");
+ srcptr = &descriptor.config;
+ srclen = 0x19;
+ break;
+ case USB_DT_STRING:
+ debug("USB_DT_STRING config\n");
+ switch (le16_to_cpu(req->value) & 0xff) {
+ case 0: /* Language */
+ srcptr = "\4\3\11\4";
+ srclen = 4;
+ break;
+ case 1: /* Vendor String */
+ srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
+ srclen = 14;
+ break;
+ case 2: /* Product Name */
+ srcptr = "\52\3X\0H\0C\0I\0 "
+ "\0H\0o\0s\0t\0 "
+ "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
+ srclen = 42;
+ break;
+ default:
+ printf("unknown value DT_STRING %x\n",
+ le16_to_cpu(req->value));
+ goto unknown;
+ }
+ break;
+ default:
+ printf("unknown value %x\n", le16_to_cpu(req->value));
+ goto unknown;
+ }
+ break;
+ case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
+ switch (le16_to_cpu(req->value) >> 8) {
+ case USB_DT_HUB:
+ debug("USB_DT_HUB config\n");
+ srcptr = &descriptor.hub;
+ srclen = 0x8;
+ break;
+ default:
+ printf("unknown value %x\n", le16_to_cpu(req->value));
+ goto unknown;
+ }
+ break;
+ case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
+ debug("USB_REQ_SET_ADDRESS\n");
+ ctrl->rootdev = le16_to_cpu(req->value);
+ break;
+ case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
+ /* Do nothing */
+ break;
+ case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
+ tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
+ tmpbuf[1] = 0;
+ srcptr = tmpbuf;
+ srclen = 2;
+ break;
+ case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
+ memset(tmpbuf, 0, 4);
+ reg = xhci_readl(status_reg);
+ if (reg & PORT_CONNECT) {
+ tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
+ switch (reg & DEV_SPEED_MASK) {
+ case XDEV_FS:
+ debug("SPEED = FULLSPEED\n");
+ break;
+ case XDEV_LS:
+ debug("SPEED = LOWSPEED\n");
+ tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
+ break;
+ case XDEV_HS:
+ debug("SPEED = HIGHSPEED\n");
+ tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
+ break;
+ case XDEV_SS:
+ debug("SPEED = SUPERSPEED\n");
+ tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8;
+ break;
+ }
+ }
+ if (reg & PORT_PE)
+ tmpbuf[0] |= USB_PORT_STAT_ENABLE;
+ if ((reg & PORT_PLS_MASK) == XDEV_U3)
+ tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
+ if (reg & PORT_OC)
+ tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
+ if (reg & PORT_RESET)
+ tmpbuf[0] |= USB_PORT_STAT_RESET;
+ if (reg & PORT_POWER)
+ /*
+ * XXX: This Port power bit (for USB 3.0 hub)
+ * we are faking in USB 2.0 hub port status;
+ * since there's a change in bit positions in
+ * two:
+ * USB 2.0 port status PP is at position[8]
+ * USB 3.0 port status PP is at position[9]
+ * So, we are still keeping it at position [8]
+ */
+ tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
+ if (reg & PORT_CSC)
+ tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
+ if (reg & PORT_PEC)
+ tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
+ if (reg & PORT_OCC)
+ tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
+ if (reg & PORT_RC)
+ tmpbuf[2] |= USB_PORT_STAT_C_RESET;
+
+ srcptr = tmpbuf;
+ srclen = 4;
+ break;
+ case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
+ reg = xhci_readl(status_reg);
+ reg = xhci_port_state_to_neutral(reg);
+ switch (le16_to_cpu(req->value)) {
+ case USB_PORT_FEAT_ENABLE:
+ reg |= PORT_PE;
+ xhci_writel(status_reg, reg);
+ break;
+ case USB_PORT_FEAT_POWER:
+ reg |= PORT_POWER;
+ xhci_writel(status_reg, reg);
+ break;
+ case USB_PORT_FEAT_RESET:
+ reg |= PORT_RESET;
+ xhci_writel(status_reg, reg);
+ break;
+ default:
+ printf("unknown feature %x\n", le16_to_cpu(req->value));
+ goto unknown;
+ }
+ break;
+ case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
+ reg = xhci_readl(status_reg);
+ reg = xhci_port_state_to_neutral(reg);
+ switch (le16_to_cpu(req->value)) {
+ case USB_PORT_FEAT_ENABLE:
+ reg &= ~PORT_PE;
+ break;
+ case USB_PORT_FEAT_POWER:
+ reg &= ~PORT_POWER;
+ break;
+ case USB_PORT_FEAT_C_RESET:
+ case USB_PORT_FEAT_C_CONNECTION:
+ case USB_PORT_FEAT_C_OVER_CURRENT:
+ case USB_PORT_FEAT_C_ENABLE:
+ xhci_clear_port_change_bit((le16_to_cpu(req->value)),
+ le16_to_cpu(req->index),
+ status_reg, reg);
+ break;
+ default:
+ printf("unknown feature %x\n", le16_to_cpu(req->value));
+ goto unknown;
+ }
+ xhci_writel(status_reg, reg);
+ break;
+ default:
+ puts("Unknown request\n");
+ goto unknown;
+ }
+
+ debug("scrlen = %d\n req->length = %d\n",
+ srclen, le16_to_cpu(req->length));
+
+ len = min(srclen, le16_to_cpu(req->length));
+
+ if (srcptr != NULL && len > 0)
+ memcpy(buffer, srcptr, len);
+ else
+ debug("Len is 0\n");
+
+ udev->act_len = len;
+ udev->status = 0;
+
+ return 0;
+
+unknown:
+ udev->act_len = 0;
+ udev->status = USB_ST_STALLED;
+
+ return -ENODEV;
+}
+
+/**
+ * Submits the INT request to XHCI Host cotroller
+ *
+ * @param udev pointer to the USB device
+ * @param pipe contains the DIR_IN or OUT , devnum
+ * @param buffer buffer to be read/written based on the request
+ * @param length length of the buffer
+ * @param interval interval of the interrupt
+ * @return 0
+ */
+int
+submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
+ int length, int interval)
+{
+ /*
+ * TODO: Not addressing any interrupt type transfer requests
+ * Add support for it later.
+ */
+ return -EINVAL;
+}
+
+/**
+ * submit the BULK type of request to the USB Device
+ *
+ * @param udev pointer to the USB device
+ * @param pipe contains the DIR_IN or OUT , devnum
+ * @param buffer buffer to be read/written based on the request
+ * @param length length of the buffer
+ * @return returns 0 if successful else -1 on failure
+ */
+int
+submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
+ int length)
+{
+ if (usb_pipetype(pipe) != PIPE_BULK) {
+ printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
+ return -EINVAL;
+ }
+
+ return xhci_bulk_tx(udev, pipe, length, buffer);
+}
+
+/**
+ * submit the control type of request to the Root hub/Device based on the devnum
+ *
+ * @param udev pointer to the USB device
+ * @param pipe contains the DIR_IN or OUT , devnum
+ * @param buffer buffer to be read/written based on the request
+ * @param length length of the buffer
+ * @param setup Request type
+ * @return returns 0 if successful else -1 on failure
+ */
+int
+submit_control_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
+ int length, struct devrequest *setup)
+{
+ struct xhci_ctrl *ctrl = udev->controller;
+ int ret = 0;
+
+ if (usb_pipetype(pipe) != PIPE_CONTROL) {
+ printf("non-control pipe (type=%lu)", usb_pipetype(pipe));
+ return -EINVAL;
+ }
+
+ if (usb_pipedevice(pipe) == ctrl->rootdev)
+ return xhci_submit_root(udev, pipe, buffer, setup);
+
+ if (setup->request == USB_REQ_SET_ADDRESS)
+ return xhci_address_device(udev);
+
+ if (setup->request == USB_REQ_SET_CONFIGURATION) {
+ ret = xhci_set_configuration(udev);
+ if (ret) {
+ puts("Failed to configure xHCI endpoint\n");
+ return ret;
+ }
+ }
+
+ return xhci_ctrl_tx(udev, pipe, setup, length, buffer);
+}
+
+/**
+ * Intialises the XHCI host controller
+ * and allocates the necessary data structures
+ *
+ * @param index index to the host controller data structure
+ * @return pointer to the intialised controller
+ */
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
+{
+ uint32_t val;
+ uint32_t val2;
+ uint32_t reg;
+ struct xhci_hccr *hccr;
+ struct xhci_hcor *hcor;
+ struct xhci_ctrl *ctrl;
+
+ if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0)
+ return -ENODEV;
+
+ if (xhci_reset(hcor) != 0)
+ return -ENODEV;
+
+ ctrl = &xhcic[index];
+
+ ctrl->hccr = hccr;
+ ctrl->hcor = hcor;
+
+ /*
+ * Program the Number of Device Slots Enabled field in the CONFIG
+ * register with the max value of slots the HC can handle.
+ */
+ val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK);
+ val2 = xhci_readl(&hcor->or_config);
+ val |= (val2 & ~HCS_SLOTS_MASK);
+ xhci_writel(&hcor->or_config, val);
+
+ /* initializing xhci data structures */
+ if (xhci_mem_init(ctrl, hccr, hcor) < 0)
+ return -ENOMEM;
+
+ reg = xhci_readl(&hccr->cr_hcsparams1);
+ descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >>
+ HCS_MAX_PORTS_SHIFT);
+ printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
+
+ /* Port Indicators */
+ reg = xhci_readl(&hccr->cr_hccparams);
+ if (HCS_INDICATOR(reg))
+ put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
+ | 0x80, &descriptor.hub.wHubCharacteristics);
+
+ /* Port Power Control */
+ if (HCC_PPC(reg))
+ put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
+ | 0x01, &descriptor.hub.wHubCharacteristics);
+
+ if (xhci_start(hcor)) {
+ xhci_reset(hcor);
+ return -ENODEV;
+ }
+
+ /* Zero'ing IRQ control register and IRQ pending register */
+ xhci_writel(&ctrl->ir_set->irq_control, 0x0);
+ xhci_writel(&ctrl->ir_set->irq_pending, 0x0);
+
+ reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
+ printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
+
+ *controller = &xhcic[index];
+
+ return 0;
+}
+
+/**
+ * Stops the XHCI host controller
+ * and cleans up all the related data structures
+ *
+ * @param index index to the host controller data structure
+ * @return none
+ */
+int usb_lowlevel_stop(int index)
+{
+ struct xhci_ctrl *ctrl = (xhcic + index);
+ u32 temp;
+
+ xhci_reset(ctrl->hcor);
+
+ debug("// Disabling event ring interrupts\n");
+ temp = xhci_readl(&ctrl->hcor->or_usbsts);
+ xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT);
+ temp = xhci_readl(&ctrl->ir_set->irq_pending);
+ xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp));
+
+ xhci_hcd_stop(index);
+
+ xhci_cleanup(ctrl);
+
+ return 0;
+}
--- /dev/null
+/*
+ * USB HOST XHCI Controller
+ *
+ * Based on xHCI host controller driver in linux-kernel
+ * by Sarah Sharp.
+ *
+ * Copyright (C) 2008 Intel Corp.
+ * Author: Sarah Sharp
+ *
+ * Copyright (C) 2013 Samsung Electronics Co.Ltd
+ * Authors: Vivek Gautam <gautam.vivek@samsung.com>
+ * Vikas Sajjan <vikas.sajjan@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef HOST_XHCI_H_
+#define HOST_XHCI_H_
+
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <linux/list.h>
+
+#define upper_32_bits(n) (u32)((n) >> 32)
+#define lower_32_bits(n) (u32)(n)
+
+#define MAX_EP_CTX_NUM 31
+#define XHCI_ALIGNMENT 64
+/* Generic timeout for XHCI events */
+#define XHCI_TIMEOUT 5000
+/* Max number of USB devices for any host controller - limit in section 6.1 */
+#define MAX_HC_SLOTS 256
+/* Section 5.3.3 - MaxPorts */
+#define MAX_HC_PORTS 127
+
+/* Up to 16 ms to halt an HC */
+#define XHCI_MAX_HALT_USEC (16*1000)
+
+#define XHCI_MAX_RESET_USEC (250*1000)
+
+/*
+ * These bits are Read Only (RO) and should be saved and written to the
+ * registers: 0, 3, 10:13, 30
+ * connect status, over-current status, port speed, and device removable.
+ * connect status and port speed are also sticky - meaning they're in
+ * the AUX well and they aren't changed by a hot, warm, or cold reset.
+ */
+#define XHCI_PORT_RO ((1 << 0) | (1 << 3) | (0xf << 10) | (1 << 30))
+/*
+ * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
+ * bits 5:8, 9, 14:15, 25:27
+ * link state, port power, port indicator state, "wake on" enable state
+ */
+#define XHCI_PORT_RWS ((0xf << 5) | (1 << 9) | (0x3 << 14) | (0x7 << 25))
+/*
+ * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
+ * bit 4 (port reset)
+ */
+#define XHCI_PORT_RW1S ((1 << 4))
+/*
+ * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
+ * bits 1, 17, 18, 19, 20, 21, 22, 23
+ * port enable/disable, and
+ * change bits: connect, PED,
+ * warm port reset changed (reserved zero for USB 2.0 ports),
+ * over-current, reset, link state, and L1 change
+ */
+#define XHCI_PORT_RW1CS ((1 << 1) | (0x7f << 17))
+/*
+ * Bit 16 is RW, and writing a '1' to it causes the link state control to be
+ * latched in
+ */
+#define XHCI_PORT_RW ((1 << 16))
+/*
+ * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
+ * bits 2, 24, 28:31
+ */
+#define XHCI_PORT_RZ ((1 << 2) | (1 << 24) | (0xf << 28))
+
+/*
+ * XHCI Register Space.
+ */
+struct xhci_hccr {
+ uint32_t cr_capbase;
+ uint32_t cr_hcsparams1;
+ uint32_t cr_hcsparams2;
+ uint32_t cr_hcsparams3;
+ uint32_t cr_hccparams;
+ uint32_t cr_dboff;
+ uint32_t cr_rtsoff;
+
+/* hc_capbase bitmasks */
+/* bits 7:0 - how long is the Capabilities register */
+#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
+/* bits 31:16 */
+#define HC_VERSION(p) (((p) >> 16) & 0xffff)
+
+/* HCSPARAMS1 - hcs_params1 - bitmasks */
+/* bits 0:7, Max Device Slots */
+#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
+#define HCS_SLOTS_MASK 0xff
+/* bits 8:18, Max Interrupters */
+#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
+/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
+#define HCS_MAX_PORTS_SHIFT 24
+#define HCS_MAX_PORTS_MASK (0x7f << HCS_MAX_PORTS_SHIFT)
+#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
+
+/* HCSPARAMS2 - hcs_params2 - bitmasks */
+/* bits 0:3, frames or uframes that SW needs to queue transactions
+ * ahead of the HW to meet periodic deadlines */
+#define HCS_IST(p) (((p) >> 0) & 0xf)
+/* bits 4:7, max number of Event Ring segments */
+#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
+/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
+/* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
+#define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
+
+/* HCSPARAMS3 - hcs_params3 - bitmasks */
+/* bits 0:7, Max U1 to U0 latency for the roothub ports */
+#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
+/* bits 16:31, Max U2 to U0 latency for the roothub ports */
+#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
+
+/* HCCPARAMS - hcc_params - bitmasks */
+/* true: HC can use 64-bit address pointers */
+#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
+/* true: HC can do bandwidth negotiation */
+#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
+/* true: HC uses 64-byte Device Context structures
+ * FIXME 64-byte context structures aren't supported yet.
+ */
+#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
+/* true: HC has port power switches */
+#define HCC_PPC(p) ((p) & (1 << 3))
+/* true: HC has port indicators */
+#define HCS_INDICATOR(p) ((p) & (1 << 4))
+/* true: HC has Light HC Reset Capability */
+#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
+/* true: HC supports latency tolerance messaging */
+#define HCC_LTC(p) ((p) & (1 << 6))
+/* true: no secondary Stream ID Support */
+#define HCC_NSS(p) ((p) & (1 << 7))
+/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
+#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
+/* Extended Capabilities pointer from PCI base - section 5.3.6 */
+#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
+
+/* db_off bitmask - bits 0:1 reserved */
+#define DBOFF_MASK (~0x3)
+
+/* run_regs_off bitmask - bits 0:4 reserved */
+#define RTSOFF_MASK (~0x1f)
+
+};
+
+struct xhci_hcor_port_regs {
+ volatile uint32_t or_portsc;
+ volatile uint32_t or_portpmsc;
+ volatile uint32_t or_portli;
+ volatile uint32_t reserved_3;
+};
+
+struct xhci_hcor {
+ volatile uint32_t or_usbcmd;
+ volatile uint32_t or_usbsts;
+ volatile uint32_t or_pagesize;
+ volatile uint32_t reserved_0[2];
+ volatile uint32_t or_dnctrl;
+ volatile uint64_t or_crcr;
+ volatile uint32_t reserved_1[4];
+ volatile uint64_t or_dcbaap;
+ volatile uint32_t or_config;
+ volatile uint32_t reserved_2[241];
+ struct xhci_hcor_port_regs portregs[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS];
+
+ uint32_t reserved_4[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS * 254];
+};
+
+/* USBCMD - USB command - command bitmasks */
+/* start/stop HC execution - do not write unless HC is halted*/
+#define CMD_RUN XHCI_CMD_RUN
+/* Reset HC - resets internal HC state machine and all registers (except
+ * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
+ * The xHCI driver must reinitialize the xHC after setting this bit.
+ */
+#define CMD_RESET (1 << 1)
+/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
+#define CMD_EIE XHCI_CMD_EIE
+/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
+#define CMD_HSEIE XHCI_CMD_HSEIE
+/* bits 4:6 are reserved (and should be preserved on writes). */
+/* light reset (port status stays unchanged) - reset completed when this is 0 */
+#define CMD_LRESET (1 << 7)
+/* host controller save/restore state. */
+#define CMD_CSS (1 << 8)
+#define CMD_CRS (1 << 9)
+/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
+#define CMD_EWE XHCI_CMD_EWE
+/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
+ * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
+ * '0' means the xHC can power it off if all ports are in the disconnect,
+ * disabled, or powered-off state.
+ */
+#define CMD_PM_INDEX (1 << 11)
+/* bits 12:31 are reserved (and should be preserved on writes). */
+
+/* USBSTS - USB status - status bitmasks */
+/* HC not running - set to 1 when run/stop bit is cleared. */
+#define STS_HALT XHCI_STS_HALT
+/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
+#define STS_FATAL (1 << 2)
+/* event interrupt - clear this prior to clearing any IP flags in IR set*/
+#define STS_EINT (1 << 3)
+/* port change detect */
+#define STS_PORT (1 << 4)
+/* bits 5:7 reserved and zeroed */
+/* save state status - '1' means xHC is saving state */
+#define STS_SAVE (1 << 8)
+/* restore state status - '1' means xHC is restoring state */
+#define STS_RESTORE (1 << 9)
+/* true: save or restore error */
+#define STS_SRE (1 << 10)
+/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
+#define STS_CNR XHCI_STS_CNR
+/* true: internal Host Controller Error - SW needs to reset and reinitialize */
+#define STS_HCE (1 << 12)
+/* bits 13:31 reserved and should be preserved */
+
+/*
+ * DNCTRL - Device Notification Control Register - dev_notification bitmasks
+ * Generate a device notification event when the HC sees a transaction with a
+ * notification type that matches a bit set in this bit field.
+ */
+#define DEV_NOTE_MASK (0xffff)
+#define ENABLE_DEV_NOTE(x) (1 << (x))
+/* Most of the device notification types should only be used for debug.
+ * SW does need to pay attention to function wake notifications.
+ */
+#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
+
+/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
+/* bit 0 is the command ring cycle state */
+/* stop ring operation after completion of the currently executing command */
+#define CMD_RING_PAUSE (1 << 1)
+/* stop ring immediately - abort the currently executing command */
+#define CMD_RING_ABORT (1 << 2)
+/* true: command ring is running */
+#define CMD_RING_RUNNING (1 << 3)
+/* bits 4:5 reserved and should be preserved */
+/* Command Ring pointer - bit mask for the lower 32 bits. */
+#define CMD_RING_RSVD_BITS (0x3f)
+
+/* CONFIG - Configure Register - config_reg bitmasks */
+/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
+#define MAX_DEVS(p) ((p) & 0xff)
+/* bits 8:31 - reserved and should be preserved */
+
+/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
+/* true: device connected */
+#define PORT_CONNECT (1 << 0)
+/* true: port enabled */
+#define PORT_PE (1 << 1)
+/* bit 2 reserved and zeroed */
+/* true: port has an over-current condition */
+#define PORT_OC (1 << 3)
+/* true: port reset signaling asserted */
+#define PORT_RESET (1 << 4)
+/* Port Link State - bits 5:8
+ * A read gives the current link PM state of the port,
+ * a write with Link State Write Strobe set sets the link state.
+ */
+#define PORT_PLS_MASK (0xf << 5)
+#define XDEV_U0 (0x0 << 5)
+#define XDEV_U2 (0x2 << 5)
+#define XDEV_U3 (0x3 << 5)
+#define XDEV_RESUME (0xf << 5)
+/* true: port has power (see HCC_PPC) */
+#define PORT_POWER (1 << 9)
+/* bits 10:13 indicate device speed:
+ * 0 - undefined speed - port hasn't be initialized by a reset yet
+ * 1 - full speed
+ * 2 - low speed
+ * 3 - high speed
+ * 4 - super speed
+ * 5-15 reserved
+ */
+#define DEV_SPEED_MASK (0xf << 10)
+#define XDEV_FS (0x1 << 10)
+#define XDEV_LS (0x2 << 10)
+#define XDEV_HS (0x3 << 10)
+#define XDEV_SS (0x4 << 10)
+#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
+#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
+#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
+#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
+#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
+/* Bits 20:23 in the Slot Context are the speed for the device */
+#define SLOT_SPEED_FS (XDEV_FS << 10)
+#define SLOT_SPEED_LS (XDEV_LS << 10)
+#define SLOT_SPEED_HS (XDEV_HS << 10)
+#define SLOT_SPEED_SS (XDEV_SS << 10)
+/* Port Indicator Control */
+#define PORT_LED_OFF (0 << 14)
+#define PORT_LED_AMBER (1 << 14)
+#define PORT_LED_GREEN (2 << 14)
+#define PORT_LED_MASK (3 << 14)
+/* Port Link State Write Strobe - set this when changing link state */
+#define PORT_LINK_STROBE (1 << 16)
+/* true: connect status change */
+#define PORT_CSC (1 << 17)
+/* true: port enable change */
+#define PORT_PEC (1 << 18)
+/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
+ * into an enabled state, and the device into the default state. A "warm" reset
+ * also resets the link, forcing the device through the link training sequence.
+ * SW can also look at the Port Reset register to see when warm reset is done.
+ */
+#define PORT_WRC (1 << 19)
+/* true: over-current change */
+#define PORT_OCC (1 << 20)
+/* true: reset change - 1 to 0 transition of PORT_RESET */
+#define PORT_RC (1 << 21)
+/* port link status change - set on some port link state transitions:
+ * Transition Reason
+ * --------------------------------------------------------------------------
+ * - U3 to Resume Wakeup signaling from a device
+ * - Resume to Recovery to U0 USB 3.0 device resume
+ * - Resume to U0 USB 2.0 device resume
+ * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
+ * - U3 to U0 Software resume of USB 2.0 device complete
+ * - U2 to U0 L1 resume of USB 2.1 device complete
+ * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
+ * - U0 to disabled L1 entry error with USB 2.1 device
+ * - Any state to inactive Error on USB 3.0 port
+ */
+#define PORT_PLC (1 << 22)
+/* port configure error change - port failed to configure its link partner */
+#define PORT_CEC (1 << 23)
+/* bit 24 reserved */
+/* wake on connect (enable) */
+#define PORT_WKCONN_E (1 << 25)
+/* wake on disconnect (enable) */
+#define PORT_WKDISC_E (1 << 26)
+/* wake on over-current (enable) */
+#define PORT_WKOC_E (1 << 27)
+/* bits 28:29 reserved */
+/* true: device is removable - for USB 3.0 roothub emulation */
+#define PORT_DEV_REMOVE (1 << 30)
+/* Initiate a warm port reset - complete when PORT_WRC is '1' */
+#define PORT_WR (1 << 31)
+
+/* We mark duplicate entries with -1 */
+#define DUPLICATE_ENTRY ((u8)(-1))
+
+/* Port Power Management Status and Control - port_power_base bitmasks */
+/* Inactivity timer value for transitions into U1, in microseconds.
+ * Timeout can be up to 127us. 0xFF means an infinite timeout.
+ */
+#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
+/* Inactivity timer value for transitions into U2 */
+#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
+/* Bits 24:31 for port testing */
+
+/* USB2 Protocol PORTSPMSC */
+#define PORT_L1S_MASK 7
+#define PORT_L1S_SUCCESS 1
+#define PORT_RWE (1 << 3)
+#define PORT_HIRD(p) (((p) & 0xf) << 4)
+#define PORT_HIRD_MASK (0xf << 4)
+#define PORT_L1DS(p) (((p) & 0xff) << 8)
+#define PORT_HLE (1 << 16)
+
+/**
+* struct xhci_intr_reg - Interrupt Register Set
+* @irq_pending: IMAN - Interrupt Management Register. Used to enable
+* interrupts and check for pending interrupts.
+* @irq_control: IMOD - Interrupt Moderation Register.
+* Used to throttle interrupts.
+* @erst_size: Number of segments in the
+ Event Ring Segment Table (ERST).
+* @erst_base: ERST base address.
+* @erst_dequeue: Event ring dequeue pointer.
+*
+* Each interrupter (defined by a MSI-X vector) has an event ring and an Event
+* Ring Segment Table (ERST) associated with it.
+* The event ring is comprised of multiple segments of the same size.
+* The HC places events on the ring and "updates the Cycle bit in the TRBs to
+* indicate to software the current position of the Enqueue Pointer."
+* The HCD (Linux) processes those events and updates the dequeue pointer.
+*/
+struct xhci_intr_reg {
+ volatile __le32 irq_pending;
+ volatile __le32 irq_control;
+ volatile __le32 erst_size;
+ volatile __le32 rsvd;
+ volatile __le64 erst_base;
+ volatile __le64 erst_dequeue;
+};
+
+/* irq_pending bitmasks */
+#define ER_IRQ_PENDING(p) ((p) & 0x1)
+/* bits 2:31 need to be preserved */
+/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
+#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
+#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
+#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
+
+/* irq_control bitmasks */
+/* Minimum interval between interrupts (in 250ns intervals). The interval
+ * between interrupts will be longer if there are no events on the event ring.
+ * Default is 4000 (1 ms).
+ */
+#define ER_IRQ_INTERVAL_MASK (0xffff)
+/* Counter used to count down the time to the next interrupt - HW use only */
+#define ER_IRQ_COUNTER_MASK (0xffff << 16)
+
+/* erst_size bitmasks */
+/* Preserve bits 16:31 of erst_size */
+#define ERST_SIZE_MASK (0xffff << 16)
+
+/* erst_dequeue bitmasks */
+/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
+ * where the current dequeue pointer lies. This is an optional HW hint.
+ */
+#define ERST_DESI_MASK (0x7)
+/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
+ * a work queue (or delayed service routine)?
+ */
+#define ERST_EHB (1 << 3)
+#define ERST_PTR_MASK (0xf)
+
+/**
+ * struct xhci_run_regs
+ * @microframe_index: MFINDEX - current microframe number
+ *
+ * Section 5.5 Host Controller Runtime Registers:
+ * "Software should read and write these registers using only Dword (32 bit)
+ * or larger accesses"
+ */
+struct xhci_run_regs {
+ __le32 microframe_index;
+ __le32 rsvd[7];
+ struct xhci_intr_reg ir_set[128];
+};
+
+/**
+ * struct doorbell_array
+ *
+ * Bits 0 - 7: Endpoint target
+ * Bits 8 - 15: RsvdZ
+ * Bits 16 - 31: Stream ID
+ *
+ * Section 5.6
+ */
+struct xhci_doorbell_array {
+ volatile __le32 doorbell[256];
+};
+
+#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
+#define DB_VALUE_HOST 0x00000000
+
+/**
+ * struct xhci_protocol_caps
+ * @revision: major revision, minor revision, capability ID,
+ * and next capability pointer.
+ * @name_string: Four ASCII characters to say which spec this xHC
+ * follows, typically "USB ".
+ * @port_info: Port offset, count, and protocol-defined information.
+ */
+struct xhci_protocol_caps {
+ u32 revision;
+ u32 name_string;
+ u32 port_info;
+};
+
+#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
+#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
+#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
+
+/**
+ * struct xhci_container_ctx
+ * @type: Type of context. Used to calculated offsets to contained contexts.
+ * @size: Size of the context data
+ * @bytes: The raw context data given to HW
+ * @dma: dma address of the bytes
+ *
+ * Represents either a Device or Input context. Holds a pointer to the raw
+ * memory used for the context (bytes) and dma address of it (dma).
+ */
+struct xhci_container_ctx {
+ unsigned type;
+#define XHCI_CTX_TYPE_DEVICE 0x1
+#define XHCI_CTX_TYPE_INPUT 0x2
+
+ int size;
+ u8 *bytes;
+};
+
+/**
+ * struct xhci_slot_ctx
+ * @dev_info: Route string, device speed, hub info, and last valid endpoint
+ * @dev_info2: Max exit latency for device number, root hub port number
+ * @tt_info: tt_info is used to construct split transaction tokens
+ * @dev_state: slot state and device address
+ *
+ * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
+ * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
+ * reserved at the end of the slot context for HC internal use.
+ */
+struct xhci_slot_ctx {
+ __le32 dev_info;
+ __le32 dev_info2;
+ __le32 tt_info;
+ __le32 dev_state;
+ /* offset 0x10 to 0x1f reserved for HC internal use */
+ __le32 reserved[4];
+};
+
+/* dev_info bitmasks */
+/* Route String - 0:19 */
+#define ROUTE_STRING_MASK (0xfffff)
+/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
+#define DEV_SPEED (0xf << 20)
+/* bit 24 reserved */
+/* Is this LS/FS device connected through a HS hub? - bit 25 */
+#define DEV_MTT (0x1 << 25)
+/* Set if the device is a hub - bit 26 */
+#define DEV_HUB (0x1 << 26)
+/* Index of the last valid endpoint context in this device context - 27:31 */
+#define LAST_CTX_MASK (0x1f << 27)
+#define LAST_CTX(p) ((p) << 27)
+#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
+#define SLOT_FLAG (1 << 0)
+#define EP0_FLAG (1 << 1)
+
+/* dev_info2 bitmasks */
+/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
+#define MAX_EXIT (0xffff)
+/* Root hub port number that is needed to access the USB device */
+#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
+#define ROOT_HUB_PORT_MASK (0xff)
+#define ROOT_HUB_PORT_SHIFT (16)
+#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
+/* Maximum number of ports under a hub device */
+#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
+
+/* tt_info bitmasks */
+/*
+ * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
+ * The Slot ID of the hub that isolates the high speed signaling from
+ * this low or full-speed device. '0' if attached to root hub port.
+ */
+#define TT_SLOT (0xff)
+/*
+ * The number of the downstream facing port of the high-speed hub
+ * '0' if the device is not low or full speed.
+ */
+#define TT_PORT (0xff << 8)
+#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
+
+/* dev_state bitmasks */
+/* USB device address - assigned by the HC */
+#define DEV_ADDR_MASK (0xff)
+/* bits 8:26 reserved */
+/* Slot state */
+#define SLOT_STATE (0x1f << 27)
+#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
+
+#define SLOT_STATE_DISABLED 0
+#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
+#define SLOT_STATE_DEFAULT 1
+#define SLOT_STATE_ADDRESSED 2
+#define SLOT_STATE_CONFIGURED 3
+
+/**
+ * struct xhci_ep_ctx
+ * @ep_info: endpoint state, streams, mult, and interval information.
+ * @ep_info2: information on endpoint type, max packet size, max burst size,
+ * error count, and whether the HC will force an event for all
+ * transactions.
+ * @deq: 64-bit ring dequeue pointer address. If the endpoint only
+ * defines one stream, this points to the endpoint transfer ring.
+ * Otherwise, it points to a stream context array, which has a
+ * ring pointer for each flow.
+ * @tx_info:
+ * Average TRB lengths for the endpoint ring and
+ * max payload within an Endpoint Service Interval Time (ESIT).
+ *
+ * Endpoint Context - section 6.2.1.2.This assumes the HC uses 32-byte context
+ * structures.If the HC uses 64-byte contexts, there is an additional 32 bytes
+ * reserved at the end of the endpoint context for HC internal use.
+ */
+struct xhci_ep_ctx {
+ __le32 ep_info;
+ __le32 ep_info2;
+ __le64 deq;
+ __le32 tx_info;
+ /* offset 0x14 - 0x1f reserved for HC internal use */
+ __le32 reserved[3];
+};
+
+/* ep_info bitmasks */
+/*
+ * Endpoint State - bits 0:2
+ * 0 - disabled
+ * 1 - running
+ * 2 - halted due to halt condition - ok to manipulate endpoint ring
+ * 3 - stopped
+ * 4 - TRB error
+ * 5-7 - reserved
+ */
+#define EP_STATE_MASK (0xf)
+#define EP_STATE_DISABLED 0
+#define EP_STATE_RUNNING 1
+#define EP_STATE_HALTED 2
+#define EP_STATE_STOPPED 3
+#define EP_STATE_ERROR 4
+/* Mult - Max number of burtst within an interval, in EP companion desc. */
+#define EP_MULT(p) (((p) & 0x3) << 8)
+#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
+/* bits 10:14 are Max Primary Streams */
+/* bit 15 is Linear Stream Array */
+/* Interval - period between requests to an endpoint - 125u increments. */
+#define EP_INTERVAL(p) (((p) & 0xff) << 16)
+#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
+#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
+#define EP_MAXPSTREAMS_MASK (0x1f << 10)
+#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
+/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
+#define EP_HAS_LSA (1 << 15)
+
+/* ep_info2 bitmasks */
+/*
+ * Force Event - generate transfer events for all TRBs for this endpoint
+ * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
+ */
+#define FORCE_EVENT (0x1)
+#define ERROR_COUNT(p) (((p) & 0x3) << 1)
+#define ERROR_COUNT_SHIFT (1)
+#define ERROR_COUNT_MASK (0x3)
+#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
+#define EP_TYPE(p) ((p) << 3)
+#define EP_TYPE_SHIFT (3)
+#define ISOC_OUT_EP 1
+#define BULK_OUT_EP 2
+#define INT_OUT_EP 3
+#define CTRL_EP 4
+#define ISOC_IN_EP 5
+#define BULK_IN_EP 6
+#define INT_IN_EP 7
+/* bit 6 reserved */
+/* bit 7 is Host Initiate Disable - for disabling stream selection */
+#define MAX_BURST(p) (((p)&0xff) << 8)
+#define MAX_BURST_MASK (0xff)
+#define MAX_BURST_SHIFT (8)
+#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
+#define MAX_PACKET(p) (((p)&0xffff) << 16)
+#define MAX_PACKET_MASK (0xffff)
+#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
+#define MAX_PACKET_SHIFT (16)
+
+/* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
+ * USB2.0 spec 9.6.6.
+ */
+#define GET_MAX_PACKET(p) ((p) & 0x7ff)
+
+/* tx_info bitmasks */
+#define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
+#define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
+#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
+
+/* deq bitmasks */
+#define EP_CTX_CYCLE_MASK (1 << 0)
+
+
+/**
+ * struct xhci_input_control_context
+ * Input control context; see section 6.2.5.
+ *
+ * @drop_context: set the bit of the endpoint context you want to disable
+ * @add_context: set the bit of the endpoint context you want to enable
+ */
+struct xhci_input_control_ctx {
+ volatile __le32 drop_flags;
+ volatile __le32 add_flags;
+ __le32 rsvd2[6];
+};
+
+
+/**
+ * struct xhci_device_context_array
+ * @dev_context_ptr array of 64-bit DMA addresses for device contexts
+ */
+struct xhci_device_context_array {
+ /* 64-bit device addresses; we only write 32-bit addresses */
+ __le64 dev_context_ptrs[MAX_HC_SLOTS];
+};
+/* TODO: write function to set the 64-bit device DMA address */
+/*
+ * TODO: change this to be dynamically sized at HC mem init time since the HC
+ * might not be able to handle the maximum number of devices possible.
+ */
+
+
+struct xhci_transfer_event {
+ /* 64-bit buffer address, or immediate data */
+ __le64 buffer;
+ __le32 transfer_len;
+ /* This field is interpreted differently based on the type of TRB */
+ volatile __le32 flags;
+};
+
+/* Transfer event TRB length bit mask */
+/* bits 0:23 */
+#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
+
+/** Transfer Event bit fields **/
+#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
+
+/* Completion Code - only applicable for some types of TRBs */
+#define COMP_CODE_MASK (0xff << 24)
+#define COMP_CODE_SHIFT (24)
+#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
+
+typedef enum {
+ COMP_SUCCESS = 1,
+ /* Data Buffer Error */
+ COMP_DB_ERR, /* 2 */
+ /* Babble Detected Error */
+ COMP_BABBLE, /* 3 */
+ /* USB Transaction Error */
+ COMP_TX_ERR, /* 4 */
+ /* TRB Error - some TRB field is invalid */
+ COMP_TRB_ERR, /* 5 */
+ /* Stall Error - USB device is stalled */
+ COMP_STALL, /* 6 */
+ /* Resource Error - HC doesn't have memory for that device configuration */
+ COMP_ENOMEM, /* 7 */
+ /* Bandwidth Error - not enough room in schedule for this dev config */
+ COMP_BW_ERR, /* 8 */
+ /* No Slots Available Error - HC ran out of device slots */
+ COMP_ENOSLOTS, /* 9 */
+ /* Invalid Stream Type Error */
+ COMP_STREAM_ERR, /* 10 */
+ /* Slot Not Enabled Error - doorbell rung for disabled device slot */
+ COMP_EBADSLT, /* 11 */
+ /* Endpoint Not Enabled Error */
+ COMP_EBADEP,/* 12 */
+ /* Short Packet */
+ COMP_SHORT_TX, /* 13 */
+ /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
+ COMP_UNDERRUN, /* 14 */
+ /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
+ COMP_OVERRUN, /* 15 */
+ /* Virtual Function Event Ring Full Error */
+ COMP_VF_FULL, /* 16 */
+ /* Parameter Error - Context parameter is invalid */
+ COMP_EINVAL, /* 17 */
+ /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
+ COMP_BW_OVER,/* 18 */
+ /* Context State Error - illegal context state transition requested */
+ COMP_CTX_STATE,/* 19 */
+ /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
+ COMP_PING_ERR,/* 20 */
+ /* Event Ring is full */
+ COMP_ER_FULL,/* 21 */
+ /* Incompatible Device Error */
+ COMP_DEV_ERR,/* 22 */
+ /* Missed Service Error - HC couldn't service an isoc ep within interval */
+ COMP_MISSED_INT,/* 23 */
+ /* Successfully stopped command ring */
+ COMP_CMD_STOP, /* 24 */
+ /* Successfully aborted current command and stopped command ring */
+ COMP_CMD_ABORT, /* 25 */
+ /* Stopped - transfer was terminated by a stop endpoint command */
+ COMP_STOP,/* 26 */
+ /* Same as COMP_EP_STOPPED, but the transferred length in the event
+ * is invalid */
+ COMP_STOP_INVAL, /* 27*/
+ /* Control Abort Error - Debug Capability - control pipe aborted */
+ COMP_DBG_ABORT, /* 28 */
+ /* Max Exit Latency Too Large Error */
+ COMP_MEL_ERR,/* 29 */
+ /* TRB type 30 reserved */
+ /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
+ COMP_BUFF_OVER = 31,
+ /* Event Lost Error - xHC has an "internal event overrun condition" */
+ COMP_ISSUES, /* 32 */
+ /* Undefined Error - reported when other error codes don't apply */
+ COMP_UNKNOWN, /* 33 */
+ /* Invalid Stream ID Error */
+ COMP_STRID_ERR, /* 34 */
+ /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
+ COMP_2ND_BW_ERR, /* 35 */
+ /* Split Transaction Error */
+ COMP_SPLIT_ERR /* 36 */
+
+} xhci_comp_code;
+
+struct xhci_link_trb {
+ /* 64-bit segment pointer*/
+ volatile __le64 segment_ptr;
+ volatile __le32 intr_target;
+ volatile __le32 control;
+};
+
+/* control bitfields */
+#define LINK_TOGGLE (0x1 << 1)
+
+/* Command completion event TRB */
+struct xhci_event_cmd {
+ /* Pointer to command TRB, or the value passed by the event data trb */
+ volatile __le64 cmd_trb;
+ volatile __le32 status;
+ volatile __le32 flags;
+};
+
+/* flags bitmasks */
+/* bits 16:23 are the virtual function ID */
+/* bits 24:31 are the slot ID */
+#define TRB_TO_SLOT_ID(p) (((p) & (0xff << 24)) >> 24)
+#define TRB_TO_SLOT_ID_SHIFT (24)
+#define TRB_TO_SLOT_ID_MASK (0xff << TRB_TO_SLOT_ID_SHIFT)
+#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
+#define SLOT_ID_FOR_TRB_MASK (0xff)
+#define SLOT_ID_FOR_TRB_SHIFT (24)
+
+/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
+#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
+#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
+
+#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
+#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
+#define LAST_EP_INDEX 30
+
+/* Set TR Dequeue Pointer command TRB fields */
+#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
+#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
+
+
+/* Port Status Change Event TRB fields */
+/* Port ID - bits 31:24 */
+#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
+#define PORT_ID_SHIFT (24)
+#define PORT_ID_MASK (0xff << PORT_ID_SHIFT)
+
+/* Normal TRB fields */
+/* transfer_len bitmasks - bits 0:16 */
+#define TRB_LEN(p) ((p) & 0x1ffff)
+#define TRB_LEN_MASK (0x1ffff)
+/* Interrupter Target - which MSI-X vector to target the completion event at */
+#define TRB_INTR_TARGET_SHIFT (22)
+#define TRB_INTR_TARGET_MASK (0x3ff)
+#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
+#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
+#define TRB_TBC(p) (((p) & 0x3) << 7)
+#define TRB_TLBPC(p) (((p) & 0xf) << 16)
+
+/* Cycle bit - indicates TRB ownership by HC or HCD */
+#define TRB_CYCLE (1<<0)
+/*
+ * Force next event data TRB to be evaluated before task switch.
+ * Used to pass OS data back after a TD completes.
+ */
+#define TRB_ENT (1<<1)
+/* Interrupt on short packet */
+#define TRB_ISP (1<<2)
+/* Set PCIe no snoop attribute */
+#define TRB_NO_SNOOP (1<<3)
+/* Chain multiple TRBs into a TD */
+#define TRB_CHAIN (1<<4)
+/* Interrupt on completion */
+#define TRB_IOC (1<<5)
+/* The buffer pointer contains immediate data */
+#define TRB_IDT (1<<6)
+
+/* Block Event Interrupt */
+#define TRB_BEI (1<<9)
+
+/* Control transfer TRB specific fields */
+#define TRB_DIR_IN (1<<16)
+#define TRB_TX_TYPE(p) ((p) << 16)
+#define TRB_TX_TYPE_SHIFT (16)
+#define TRB_DATA_OUT 2
+#define TRB_DATA_IN 3
+
+/* Isochronous TRB specific fields */
+#define TRB_SIA (1 << 31)
+
+struct xhci_generic_trb {
+ volatile __le32 field[4];
+};
+
+union xhci_trb {
+ struct xhci_link_trb link;
+ struct xhci_transfer_event trans_event;
+ struct xhci_event_cmd event_cmd;
+ struct xhci_generic_trb generic;
+};
+
+/* TRB bit mask */
+#define TRB_TYPE_BITMASK (0xfc00)
+#define TRB_TYPE(p) ((p) << 10)
+#define TRB_TYPE_SHIFT (10)
+#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
+
+/* TRB type IDs */
+typedef enum {
+ /* bulk, interrupt, isoc scatter/gather, and control data stage */
+ TRB_NORMAL = 1,
+ /* setup stage for control transfers */
+ TRB_SETUP, /* 2 */
+ /* data stage for control transfers */
+ TRB_DATA, /* 3 */
+ /* status stage for control transfers */
+ TRB_STATUS, /* 4 */
+ /* isoc transfers */
+ TRB_ISOC, /* 5 */
+ /* TRB for linking ring segments */
+ TRB_LINK, /* 6 */
+ /* TRB for EVENT DATA */
+ TRB_EVENT_DATA, /* 7 */
+ /* Transfer Ring No-op (not for the command ring) */
+ TRB_TR_NOOP, /* 8 */
+ /* Command TRBs */
+ /* Enable Slot Command */
+ TRB_ENABLE_SLOT, /* 9 */
+ /* Disable Slot Command */
+ TRB_DISABLE_SLOT, /* 10 */
+ /* Address Device Command */
+ TRB_ADDR_DEV, /* 11 */
+ /* Configure Endpoint Command */
+ TRB_CONFIG_EP, /* 12 */
+ /* Evaluate Context Command */
+ TRB_EVAL_CONTEXT, /* 13 */
+ /* Reset Endpoint Command */
+ TRB_RESET_EP, /* 14 */
+ /* Stop Transfer Ring Command */
+ TRB_STOP_RING, /* 15 */
+ /* Set Transfer Ring Dequeue Pointer Command */
+ TRB_SET_DEQ, /* 16 */
+ /* Reset Device Command */
+ TRB_RESET_DEV, /* 17 */
+ /* Force Event Command (opt) */
+ TRB_FORCE_EVENT, /* 18 */
+ /* Negotiate Bandwidth Command (opt) */
+ TRB_NEG_BANDWIDTH, /* 19 */
+ /* Set Latency Tolerance Value Command (opt) */
+ TRB_SET_LT, /* 20 */
+ /* Get port bandwidth Command */
+ TRB_GET_BW, /* 21 */
+ /* Force Header Command - generate a transaction or link management packet */
+ TRB_FORCE_HEADER, /* 22 */
+ /* No-op Command - not for transfer rings */
+ TRB_CMD_NOOP, /* 23 */
+ /* TRB IDs 24-31 reserved */
+ /* Event TRBS */
+ /* Transfer Event */
+ TRB_TRANSFER = 32,
+ /* Command Completion Event */
+ TRB_COMPLETION, /* 33 */
+ /* Port Status Change Event */
+ TRB_PORT_STATUS, /* 34 */
+ /* Bandwidth Request Event (opt) */
+ TRB_BANDWIDTH_EVENT, /* 35 */
+ /* Doorbell Event (opt) */
+ TRB_DOORBELL, /* 36 */
+ /* Host Controller Event */
+ TRB_HC_EVENT, /* 37 */
+ /* Device Notification Event - device sent function wake notification */
+ TRB_DEV_NOTE, /* 38 */
+ /* MFINDEX Wrap Event - microframe counter wrapped */
+ TRB_MFINDEX_WRAP, /* 39 */
+ /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
+ /* Nec vendor-specific command completion event. */
+ TRB_NEC_CMD_COMP = 48, /* 48 */
+ /* Get NEC firmware revision. */
+ TRB_NEC_GET_FW, /* 49 */
+} trb_type;
+
+#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
+/* Above, but for __le32 types -- can avoid work by swapping constants: */
+#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
+ cpu_to_le32(TRB_TYPE(TRB_LINK)))
+#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
+ cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
+
+/*
+ * TRBS_PER_SEGMENT must be a multiple of 4,
+ * since the command ring is 64-byte aligned.
+ * It must also be greater than 16.
+ */
+#define TRBS_PER_SEGMENT 64
+/* Allow two commands + a link TRB, along with any reserved command TRBs */
+#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
+#define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
+/* SEGMENT_SHIFT should be log2(SEGMENT_SIZE).
+ * Change this if you change TRBS_PER_SEGMENT!
+ */
+#define SEGMENT_SHIFT 10
+/* TRB buffer pointers can't cross 64KB boundaries */
+#define TRB_MAX_BUFF_SHIFT 16
+#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
+
+struct xhci_segment {
+ union xhci_trb *trbs;
+ /* private to HCD */
+ struct xhci_segment *next;
+};
+
+struct xhci_ring {
+ struct xhci_segment *first_seg;
+ union xhci_trb *enqueue;
+ struct xhci_segment *enq_seg;
+ union xhci_trb *dequeue;
+ struct xhci_segment *deq_seg;
+ /*
+ * Write the cycle state into the TRB cycle field to give ownership of
+ * the TRB to the host controller (if we are the producer), or to check
+ * if we own the TRB (if we are the consumer). See section 4.9.1.
+ */
+ volatile u32 cycle_state;
+ unsigned int num_segs;
+};
+
+struct xhci_erst_entry {
+ /* 64-bit event ring segment address */
+ __le64 seg_addr;
+ __le32 seg_size;
+ /* Set to zero */
+ __le32 rsvd;
+};
+
+struct xhci_erst {
+ struct xhci_erst_entry *entries;
+ unsigned int num_entries;
+ /* Num entries the ERST can contain */
+ unsigned int erst_size;
+};
+
+/*
+ * Each segment table entry is 4*32bits long. 1K seems like an ok size:
+ * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
+ * meaning 64 ring segments.
+ * Initial allocated size of the ERST, in number of entries */
+#define ERST_NUM_SEGS 3
+/* Initial number of event segment rings allocated */
+#define ERST_ENTRIES 3
+/* Initial allocated size of the ERST, in number of entries */
+#define ERST_SIZE 64
+/* Poll every 60 seconds */
+#define POLL_TIMEOUT 60
+/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
+#define XHCI_STOP_EP_CMD_TIMEOUT 5
+/* XXX: Make these module parameters */
+
+struct xhci_virt_ep {
+ struct xhci_ring *ring;
+ unsigned int ep_state;
+#define SET_DEQ_PENDING (1 << 0)
+#define EP_HALTED (1 << 1) /* For stall handling */
+#define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
+/* Transitioning the endpoint to using streams, don't enqueue URBs */
+#define EP_GETTING_STREAMS (1 << 3)
+#define EP_HAS_STREAMS (1 << 4)
+/* Transitioning the endpoint to not using streams, don't enqueue URBs */
+#define EP_GETTING_NO_STREAMS (1 << 5)
+};
+
+#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
+
+struct xhci_virt_device {
+ struct usb_device *udev;
+ /*
+ * Commands to the hardware are passed an "input context" that
+ * tells the hardware what to change in its data structures.
+ * The hardware will return changes in an "output context" that
+ * software must allocate for the hardware. We need to keep
+ * track of input and output contexts separately because
+ * these commands might fail and we don't trust the hardware.
+ */
+ struct xhci_container_ctx *out_ctx;
+ /* Used for addressing devices and configuration changes */
+ struct xhci_container_ctx *in_ctx;
+ /* Rings saved to ensure old alt settings can be re-instated */
+#define XHCI_MAX_RINGS_CACHED 31
+ struct xhci_virt_ep eps[31];
+};
+
+/* TODO: copied from ehci.h - can be refactored? */
+/* xHCI spec says all registers are little endian */
+static inline unsigned int xhci_readl(uint32_t volatile *regs)
+{
+ return readl(regs);
+}
+
+static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val)
+{
+ writel(val, regs);
+}
+
+/*
+ * Registers should always be accessed with double word or quad word accesses.
+ * Some xHCI implementations may support 64-bit address pointers. Registers
+ * with 64-bit address pointers should be written to with dword accesses by
+ * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
+ * xHCI implementations that do not support 64-bit address pointers will ignore
+ * the high dword, and write order is irrelevant.
+ */
+static inline u64 xhci_readq(__le64 volatile *regs)
+{
+ __u32 *ptr = (__u32 *)regs;
+ u64 val_lo = readl(ptr);
+ u64 val_hi = readl(ptr + 1);
+ return val_lo + (val_hi << 32);
+}
+
+static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
+{
+ __u32 *ptr = (__u32 *)regs;
+ u32 val_lo = lower_32_bits(val);
+ /* FIXME */
+ u32 val_hi = 0;
+ writel(val_lo, ptr);
+ writel(val_hi, ptr + 1);
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
+ struct xhci_hcor **ret_hcor);
+void xhci_hcd_stop(int index);
+
+
+/*************************************************************
+ EXTENDED CAPABILITY DEFINITIONS
+*************************************************************/
+/* Up to 16 ms to halt an HC */
+#define XHCI_MAX_HALT_USEC (16*1000)
+/* HC not running - set to 1 when run/stop bit is cleared. */
+#define XHCI_STS_HALT (1 << 0)
+
+/* HCCPARAMS offset from PCI base address */
+#define XHCI_HCC_PARAMS_OFFSET 0x10
+/* HCCPARAMS contains the first extended capability pointer */
+#define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff)
+
+/* Command and Status registers offset from the Operational Registers address */
+#define XHCI_CMD_OFFSET 0x00
+#define XHCI_STS_OFFSET 0x04
+
+#define XHCI_MAX_EXT_CAPS 50
+
+/* Capability Register */
+/* bits 7:0 - how long is the Capabilities register */
+#define XHCI_HC_LENGTH(p) (((p) >> 00) & 0x00ff)
+
+/* Extended capability register fields */
+#define XHCI_EXT_CAPS_ID(p) (((p) >> 0) & 0xff)
+#define XHCI_EXT_CAPS_NEXT(p) (((p) >> 8) & 0xff)
+#define XHCI_EXT_CAPS_VAL(p) ((p) >> 16)
+/* Extended capability IDs - ID 0 reserved */
+#define XHCI_EXT_CAPS_LEGACY 1
+#define XHCI_EXT_CAPS_PROTOCOL 2
+#define XHCI_EXT_CAPS_PM 3
+#define XHCI_EXT_CAPS_VIRT 4
+#define XHCI_EXT_CAPS_ROUTE 5
+/* IDs 6-9 reserved */
+#define XHCI_EXT_CAPS_DEBUG 10
+/* USB Legacy Support Capability - section 7.1.1 */
+#define XHCI_HC_BIOS_OWNED (1 << 16)
+#define XHCI_HC_OS_OWNED (1 << 24)
+
+/* USB Legacy Support Capability - section 7.1.1 */
+/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
+#define XHCI_LEGACY_SUPPORT_OFFSET (0x00)
+
+/* USB Legacy Support Control and Status Register - section 7.1.2 */
+/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
+#define XHCI_LEGACY_CONTROL_OFFSET (0x04)
+/* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
+#define XHCI_LEGACY_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17))
+
+/* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
+#define XHCI_L1C (1 << 16)
+
+/* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */
+#define XHCI_HLC (1 << 19)
+
+/* command register values to disable interrupts and halt the HC */
+/* start/stop HC execution - do not write unless HC is halted*/
+#define XHCI_CMD_RUN (1 << 0)
+/* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
+#define XHCI_CMD_EIE (1 << 2)
+/* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
+#define XHCI_CMD_HSEIE (1 << 3)
+/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
+#define XHCI_CMD_EWE (1 << 10)
+
+#define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE)
+
+/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
+#define XHCI_STS_CNR (1 << 11)
+
+struct xhci_ctrl {
+ struct xhci_hccr *hccr; /* R/O registers, not need for volatile */
+ struct xhci_hcor *hcor;
+ struct xhci_doorbell_array *dba;
+ struct xhci_run_regs *run_regs;
+ struct xhci_device_context_array *dcbaa \
+ __attribute__ ((aligned(ARCH_DMA_MINALIGN)));
+ struct xhci_ring *event_ring;
+ struct xhci_ring *cmd_ring;
+ struct xhci_ring *transfer_ring;
+ struct xhci_segment *seg;
+ struct xhci_intr_reg *ir_set;
+ struct xhci_erst erst;
+ struct xhci_erst_entry entry[ERST_NUM_SEGS];
+ struct xhci_virt_device *devs[MAX_HC_SLOTS];
+ int rootdev;
+};
+
+unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb);
+struct xhci_input_control_ctx
+ *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
+struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl,
+ struct xhci_container_ctx *ctx);
+struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl,
+ struct xhci_container_ctx *ctx,
+ unsigned int ep_index);
+void xhci_endpoint_copy(struct xhci_ctrl *ctrl,
+ struct xhci_container_ctx *in_ctx,
+ struct xhci_container_ctx *out_ctx,
+ unsigned int ep_index);
+void xhci_slot_copy(struct xhci_ctrl *ctrl,
+ struct xhci_container_ctx *in_ctx,
+ struct xhci_container_ctx *out_ctx);
+void xhci_setup_addressable_virt_dev(struct usb_device *udev);
+void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr,
+ u32 slot_id, u32 ep_index, trb_type cmd);
+void xhci_acknowledge_event(struct xhci_ctrl *ctrl);
+union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected);
+int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe,
+ int length, void *buffer);
+int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe,
+ struct devrequest *req, int length, void *buffer);
+int xhci_check_maxpacket(struct usb_device *udev);
+void xhci_flush_cache(uint32_t addr, u32 type_len);
+void xhci_inval_cache(uint32_t addr, u32 type_len);
+void xhci_cleanup(struct xhci_ctrl *ctrl);
+struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs);
+int xhci_alloc_virt_device(struct usb_device *udev);
+int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr,
+ struct xhci_hcor *hcor);
+
+#endif /* HOST_XHCI_H_ */
return submit_urb(&hcd, urb);
}
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
{
u8 power;
void *mbase;
/*
* This function initializes the usb controller module.
*/
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
{
u8 power;
u32 timeout;
*/
#include <common.h>
-#include <usb/musb_udc.h>
+#include <usbdevice.h>
+#include <usb/udc.h>
#include "../gadget/ep0.h"
#include "musb_core.h"
#if defined(CONFIG_USB_OMAP3)
LIB := $(obj)libusb_phy.o
COBJS-$(CONFIG_TWL4030_USB) += twl4030.o
+COBJS-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * OMAP USB PHY Support
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm-generic/errno.h>
+#include <asm/omap_common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+
+#include <linux/compat.h>
+#include <linux/usb/dwc3.h>
+#include <linux/usb/xhci-omap.h>
+
+#include "../host/xhci.h"
+
+#ifdef CONFIG_OMAP_USB3PHY1_HOST
+struct usb_dpll_params {
+ u16 m;
+ u8 n;
+ u8 freq:3;
+ u8 sd;
+ u32 mf;
+};
+
+#define NUM_USB_CLKS 6
+
+static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = {
+ {1250, 5, 4, 20, 0}, /* 12 MHz */
+ {3125, 20, 4, 20, 0}, /* 16.8 MHz */
+ {1172, 8, 4, 20, 65537}, /* 19.2 MHz */
+ {1250, 12, 4, 20, 0}, /* 26 MHz */
+ {3125, 47, 4, 20, 92843}, /* 38.4 MHz */
+ {1000, 7, 4, 10, 0}, /* 20 MHz */
+};
+
+static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
+{
+ u32 val;
+
+ writel(SET_PLL_GO, &phy_regs->pll_go);
+ do {
+ val = readl(&phy_regs->pll_status);
+ if (val & PLL_LOCK)
+ break;
+ } while (1);
+}
+
+static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
+{
+ u32 clk_index = get_sys_clk_index();
+ u32 val;
+
+ val = readl(&phy_regs->pll_config_1);
+ val &= ~PLL_REGN_MASK;
+ val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
+ writel(val, &phy_regs->pll_config_1);
+
+ val = readl(&phy_regs->pll_config_2);
+ val &= ~PLL_SELFREQDCO_MASK;
+ val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
+ writel(val, &phy_regs->pll_config_2);
+
+ val = readl(&phy_regs->pll_config_1);
+ val &= ~PLL_REGM_MASK;
+ val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
+ writel(val, &phy_regs->pll_config_1);
+
+ val = readl(&phy_regs->pll_config_4);
+ val &= ~PLL_REGM_F_MASK;
+ val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
+ writel(val, &phy_regs->pll_config_4);
+
+ val = readl(&phy_regs->pll_config_3);
+ val &= ~PLL_SD_MASK;
+ val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
+ writel(val, &phy_regs->pll_config_3);
+
+ omap_usb_dpll_relock(phy_regs);
+}
+
+static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
+{
+ u32 rate = get_sys_clk_freq()/1000000;
+ u32 val;
+
+ val = readl((*ctrl)->control_phy_power_usb);
+ val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK);
+ val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON);
+ val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT;
+
+ writel(val, (*ctrl)->control_phy_power_usb);
+}
+
+void usb_phy_power(int on)
+{
+ u32 val;
+
+ val = readl((*ctrl)->control_phy_power_usb);
+ if (on) {
+ val &= ~USB3_PWRCTL_CLK_CMD_MASK;
+ val |= USB3_PHY_TX_RX_POWERON;
+ } else {
+ val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON);
+ }
+
+ writel(val, (*ctrl)->control_phy_power_usb);
+}
+
+void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
+{
+ omap_usb_dpll_lock(phy_regs);
+
+ usb3_phy_partial_powerup(phy_regs);
+ /*
+ * Give enough time for the PHY to partially power-up before
+ * powering it up completely. delay value suggested by the HW
+ * team.
+ */
+ mdelay(100);
+ usb3_phy_power(1);
+}
+
+static void omap_enable_usb3_phy(struct omap_xhci *omap)
+{
+ u32 val;
+
+ /* Setting OCP2SCP1 register */
+ setbits_le32((*prcm)->cm_l3init_ocp2scp1_clkctrl,
+ OCP2SCP1_CLKCTRL_MODULEMODE_HW);
+
+ /* Turn on 32K AON clk */
+ setbits_le32((*prcm)->cm_coreaon_usb_phy_core_clkctrl,
+ USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+ /* Setting CM_L3INIT_CLKSTCTRL to 0x0 i.e NO sleep */
+ writel(0x0, (*prcm)->cm_l3init_clkstctrl);
+
+ val = (USBOTGSS_DMADISABLE |
+ USBOTGSS_STANDBYMODE_SMRT_WKUP |
+ USBOTGSS_IDLEMODE_NOIDLE);
+ writel(val, &omap->otg_wrapper->sysconfig);
+
+ /* Clear the utmi OTG status */
+ val = readl(&omap->otg_wrapper->utmi_otg_status);
+ writel(val, &omap->otg_wrapper->utmi_otg_status);
+
+ /* Enable interrupts */
+ writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0);
+ val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN |
+ USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN |
+ USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN |
+ USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN |
+ USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN |
+ USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN |
+ USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN |
+ USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN |
+ USBOTGSS_IRQ_SET_1_OEVT_EN);
+ writel(val, &omap->otg_wrapper->irqenable_set_1);
+
+ /* Clear the IRQ status */
+ val = readl(&omap->otg_wrapper->irqstatus_1);
+ writel(val, &omap->otg_wrapper->irqstatus_1);
+ val = readl(&omap->otg_wrapper->irqstatus_0);
+ writel(val, &omap->otg_wrapper->irqstatus_0);
+
+ /* Enable the USB OTG Super speed clocks */
+ val = (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW);
+ setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, val);
+
+};
+#endif /* CONFIG_OMAP_USB3PHY1_HOST */
+
+#ifdef CONFIG_OMAP_USB2PHY2_HOST
+static void omap_enable_usb2_phy2(struct omap_xhci *omap)
+{
+ u32 reg, val;
+
+ val = (~USB2PHY_AUTORESUME_EN & USB2PHY_DISCHGDET);
+ writel(val, (*ctrl)->control_srcomp_north_side);
+
+ setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
+ USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+ setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl,
+ (USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K |
+ OTG_SS_CLKCTRL_MODULEMODE_HW));
+
+ /* This is an undocumented Reserved register */
+ reg = 0x4a0086c0;
+ val = readl(reg);
+ val |= 0x100;
+ setbits_le32(reg, val);
+}
+
+void usb_phy_power(int on)
+{
+ return;
+}
+#endif /* CONFIG_OMAP_USB2PHY2_HOST */
+
+#ifdef CONFIG_AM437X_USB2PHY2_HOST
+static void am437x_enable_usb2_phy2(struct omap_xhci *omap)
+{
+ const u32 usb_otg_ss_clk_val = (USBOTGSSX_CLKCTRL_MODULE_EN |
+ USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
+
+ writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS0_CLKCTRL);
+ writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS1_CLKCTRL);
+
+ writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP0_CLKCTRL);
+ writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP1_CLKCTRL);
+}
+
+void usb_phy_power(int on)
+{
+ return;
+}
+#endif /* CONFIG_AM437X_USB2PHY2_HOST */
+
+void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
+{
+ /* Assert USB3 PHY reset */
+ setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Assert USB2 PHY reset */
+ setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ mdelay(100);
+
+ /* Clear USB3 PHY reset */
+ clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Clear USB2 PHY reset */
+ clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+}
+
+void omap_enable_phy(struct omap_xhci *omap)
+{
+#ifdef CONFIG_OMAP_USB2PHY2_HOST
+ omap_enable_usb2_phy2(omap);
+#endif
+
+#ifdef CONFIG_AM437X_USB2PHY2_HOST
+ am437x_enable_usb2_phy2(omap);
+#endif
+
+#ifdef CONFIG_OMAP_USB3PHY1_HOST
+ omap_enable_usb3_phy(omap);
+ omap_usb3_phy_init(omap->usb3_phy);
+#endif
+}
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT "U-Boot# "
#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
/* Unsupported features */
#undef CONFIG_USE_IRQ
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_AM437X_USB2PHY2_HOST
+
#endif /* __CONFIG_AM43XX_EVM_H */
#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+/* USB xHCI HOST */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_OMAP_USB2PHY2_HOST
+
#endif /* __CONFIG_DRA7XX_EVM_H */
/* Keep L2 Cache Disabled */
#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
/* Enable ACE acceleration for SHA1 and SHA256 */
#define CONFIG_EXYNOS_ACE_SHA
#define CONFIG_SHA_HW_ACCEL
/* USB */
#define CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_EXYNOS
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_EXYNOS
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
/* USB boot mode */
#define CONFIG_USB_STORAGE
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_MXC_USB_PORT 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
#define CONFIG_MXC_GPIO
+#define CONFIG_MV_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_CDC
+#define CONFIG_NETCONSOLE
#define CONFIG_CMD_FUSE
#ifdef CONFIG_CMD_FUSE
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_SMSC95XX
-#define CONFIG_MXC_USB_PORT 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define MACH_TYPE_TRATS 3928
#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
+#include <asm/sizes.h>
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (16 << 20))
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
/* select serial console configuration */
#define CONFIG_SERIAL2 /* use SERIAL 2 */
/* USB Composite download gadget - g_dnl */
#define CONFIG_USBDOWNLOAD_GADGET
+
+/* TIZEN THOR downloader support */
+#define CONFIG_CMD_THOR_DOWNLOAD
+#define CONFIG_THOR_FUNCTION
+
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
#define CONFIG_DFU_FUNCTION
#define CONFIG_DFU_MMC
/* USB Samsung's IDs */
#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
+#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
+#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
#define CONFIG_G_DNL_MANUFACTURER "Samsung"
#define CONFIG_BOOTDELAY 1
#define CONFIG_DFU_ALT \
"u-boot mmc 80 400;" \
"uImage ext4 0 2;" \
- "exynos4210-trats.dtb ext4 0 2\0"
+ "exynos4210-trats.dtb ext4 0 2;" \
+ ""PARTS_ROOT" part 0 5\0"
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
struct dfu_entity *dfu_get_entity(int alt);
char *dfu_extract_token(char** e, int *n);
void dfu_trigger_reset(void);
+int dfu_get_alt(char *name);
bool dfu_reset(void);
int dfu_init_env_entities(char *interface, int dev);
+unsigned char *dfu_get_buf(void);
+unsigned char *dfu_free_buf(void);
int dfu_read(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
int dfu_write(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
COMPAT_GOOGLE_CROS_EC, /* Google CROS_EC Protocol */
COMPAT_GOOGLE_CROS_EC_KEYB, /* Google CROS_EC Keyboard */
COMPAT_SAMSUNG_EXYNOS_EHCI, /* Exynos EHCI controller */
+ COMPAT_SAMSUNG_EXYNOS5_XHCI, /* Exynos5 XHCI controller */
COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */
+ COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */
COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */
COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */
COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
-int g_dnl_bind_fixup(struct usb_device_descriptor *);
+int g_dnl_bind_fixup(struct usb_device_descriptor *, const char *);
int g_dnl_register(const char *s);
void g_dnl_unregister(void);
-/* USB initialization declaration - board specific */
-void board_usb_init(void);
#endif /* __G_DOWNLOAD_H_ */
--- /dev/null
+/* include/linux/usb/dwc3.h
+ *
+ * Copyright (c) 2012 Samsung Electronics Co. Ltd
+ *
+ * Designware SuperSpeed USB 3.0 DRD Controller global and OTG registers
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DWC3_H_
+#define __DWC3_H_
+
+/* Global constants */
+#define DWC3_ENDPOINTS_NUM 32
+
+#define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE
+#define DWC3_EVENT_TYPE_MASK 0xfe
+
+#define DWC3_EVENT_TYPE_DEV 0
+#define DWC3_EVENT_TYPE_CARKIT 3
+#define DWC3_EVENT_TYPE_I2C 4
+
+#define DWC3_DEVICE_EVENT_DISCONNECT 0
+#define DWC3_DEVICE_EVENT_RESET 1
+#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
+#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
+#define DWC3_DEVICE_EVENT_WAKEUP 4
+#define DWC3_DEVICE_EVENT_EOPF 6
+#define DWC3_DEVICE_EVENT_SOF 7
+#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
+#define DWC3_DEVICE_EVENT_CMD_CMPL 10
+#define DWC3_DEVICE_EVENT_OVERFLOW 11
+
+#define DWC3_GEVNTCOUNT_MASK 0xfffc
+#define DWC3_GSNPSID_MASK 0xffff0000
+#define DWC3_GSNPSID_SHIFT 16
+#define DWC3_GSNPSREV_MASK 0xffff
+
+#define DWC3_REVISION_MASK 0xffff
+
+#define DWC3_REG_OFFSET 0xC100
+
+struct g_event_buffer {
+ u64 g_evntadr;
+ u32 g_evntsiz;
+ u32 g_evntcount;
+};
+
+struct d_physical_endpoint {
+ u32 d_depcmdpar2;
+ u32 d_depcmdpar1;
+ u32 d_depcmdpar0;
+ u32 d_depcmd;
+};
+
+struct dwc3 { /* offset: 0xC100 */
+ u32 g_sbuscfg0;
+ u32 g_sbuscfg1;
+ u32 g_txthrcfg;
+ u32 g_rxthrcfg;
+ u32 g_ctl;
+
+ u32 reserved1;
+
+ u32 g_sts;
+
+ u32 reserved2;
+
+ u32 g_snpsid;
+ u32 g_gpio;
+ u32 g_uid;
+ u32 g_uctl;
+ u64 g_buserraddr;
+ u64 g_prtbimap;
+
+ u32 g_hwparams0;
+ u32 g_hwparams1;
+ u32 g_hwparams2;
+ u32 g_hwparams3;
+ u32 g_hwparams4;
+ u32 g_hwparams5;
+ u32 g_hwparams6;
+ u32 g_hwparams7;
+
+ u32 g_dbgfifospace;
+ u32 g_dbgltssm;
+ u32 g_dbglnmcc;
+ u32 g_dbgbmu;
+ u32 g_dbglspmux;
+ u32 g_dbglsp;
+ u32 g_dbgepinfo0;
+ u32 g_dbgepinfo1;
+
+ u64 g_prtbimap_hs;
+ u64 g_prtbimap_fs;
+
+ u32 reserved3[28];
+
+ u32 g_usb2phycfg[16];
+ u32 g_usb2i2cctl[16];
+ u32 g_usb2phyacc[16];
+ u32 g_usb3pipectl[16];
+
+ u32 g_txfifosiz[32];
+ u32 g_rxfifosiz[32];
+
+ struct g_event_buffer g_evnt_buf[32];
+
+ u32 g_hwparams8;
+
+ u32 reserved4[63];
+
+ u32 d_cfg;
+ u32 d_ctl;
+ u32 d_evten;
+ u32 d_sts;
+ u32 d_gcmdpar;
+ u32 d_gcmd;
+
+ u32 reserved5[2];
+
+ u32 d_alepena;
+
+ u32 reserved6[55];
+
+ struct d_physical_endpoint d_phy_ep_cmd[32];
+
+ u32 reserved7[128];
+
+ u32 o_cfg;
+ u32 o_ctl;
+ u32 o_evt;
+ u32 o_evten;
+ u32 o_sts;
+
+ u32 reserved8[3];
+
+ u32 adp_cfg;
+ u32 adp_ctl;
+ u32 adp_evt;
+ u32 adp_evten;
+
+ u32 bc_cfg;
+
+ u32 reserved9;
+
+ u32 bc_evt;
+ u32 bc_evten;
+};
+
+/* Global Configuration Register */
+#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
+#define DWC3_GCTL_U2RSTECN (1 << 16)
+#define DWC3_GCTL_RAMCLKSEL(x) \
+ (((x) & DWC3_GCTL_CLK_MASK) << 6)
+#define DWC3_GCTL_CLK_BUS (0)
+#define DWC3_GCTL_CLK_PIPE (1)
+#define DWC3_GCTL_CLK_PIPEHALF (2)
+#define DWC3_GCTL_CLK_MASK (3)
+#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
+#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
+#define DWC3_GCTL_PRTCAP_HOST 1
+#define DWC3_GCTL_PRTCAP_DEVICE 2
+#define DWC3_GCTL_PRTCAP_OTG 3
+#define DWC3_GCTL_CORESOFTRESET (1 << 11)
+#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
+#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
+#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
+#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
+
+/* Global HWPARAMS1 Register */
+#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
+#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
+#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
+
+/* Global USB2 PHY Configuration Register */
+#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
+#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
+
+/* Global USB3 PIPE Control Register */
+#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
+#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
+
+/* Global TX Fifo Size Register */
+#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
+#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
+
+#endif /* __DWC3_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Inc, <www.ti.com>
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_OMAP_H_
+#define _ASM_ARCH_XHCI_OMAP_H_
+
+#ifdef CONFIG_DRA7XX
+#define OMAP_XHCI_BASE 0x488d0000
+#define OMAP_OCP1_SCP_BASE 0x4A081000
+#define OMAP_OTG_WRAPPER_BASE 0x488c0000
+#elif defined CONFIG_AM43XX
+#define OMAP_XHCI_BASE 0x483d0000
+#define OMAP_OCP1_SCP_BASE 0x483E8000
+#define OMAP_OTG_WRAPPER_BASE 0x483dc100
+#else
+/* Default to the OMAP5 XHCI defines */
+#define OMAP_XHCI_BASE 0x4a030000
+#define OMAP_OCP1_SCP_BASE 0x4a084c00
+#define OMAP_OTG_WRAPPER_BASE 0x4A020000
+#endif
+
+/* Phy register MACRO definitions */
+#define PLL_REGM_MASK 0x001FFE00
+#define PLL_REGM_SHIFT 0x9
+#define PLL_REGM_F_MASK 0x0003FFFF
+#define PLL_REGM_F_SHIFT 0x0
+#define PLL_REGN_MASK 0x000001FE
+#define PLL_REGN_SHIFT 0x1
+#define PLL_SELFREQDCO_MASK 0x0000000E
+#define PLL_SELFREQDCO_SHIFT 0x1
+#define PLL_SD_MASK 0x0003FC00
+#define PLL_SD_SHIFT 0x9
+#define SET_PLL_GO 0x1
+#define PLL_TICOPWDN 0x10000
+#define PLL_LOCK 0x2
+#define PLL_IDLE 0x1
+
+#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON (1 << 6)
+#define USB3_PHY_RX_POWERON (1 << 14)
+#define USB3_PHY_TX_POWERON (1 << 15)
+#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
+#define USB3_PWRCTL_CLK_CMD_SHIFT 14
+#define USB3_PWRCTL_CLK_FREQ_SHIFT 22
+
+/* USBOTGSS_WRAPPER definitions */
+#define USBOTGSS_WRAPRESET (1 << 17)
+#define USBOTGSS_DMADISABLE (1 << 16)
+#define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4)
+#define USBOTGSS_STANDBYMODE_SMRT (1 << 5)
+#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
+#define USBOTGSS_IDLEMODE_NOIDLE (1 << 2)
+#define USBOTGSS_IDLEMODE_SMRT (1 << 3)
+#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
+
+/* USBOTGSS_IRQENABLE_SET_0 bit */
+#define USBOTGSS_COREIRQ_EN (1 << 0)
+
+/* USBOTGSS_IRQENABLE_SET_1 bits */
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN (1 << 0)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN (1 << 3)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN (1 << 4)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN (1 << 5)
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN (1 << 8)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN (1 << 11)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN (1 << 12)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN (1 << 13)
+#define USBOTGSS_IRQ_SET_1_OEVT_EN (1 << 16)
+#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN (1 << 17)
+
+/*
+ * USBOTGSS_WRAPPER registers
+ */
+struct omap_dwc_wrapper {
+ u32 revision;
+
+ u32 reserve_1[3];
+
+ u32 sysconfig; /* offset of 0x10 */
+
+ u32 reserve_2[3];
+ u16 reserve_3;
+
+ u32 irqstatus_raw_0; /* offset of 0x24 */
+ u32 irqstatus_0;
+ u32 irqenable_set_0;
+ u32 irqenable_clr_0;
+
+ u32 irqstatus_raw_1; /* offset of 0x34 */
+ u32 irqstatus_1;
+ u32 irqenable_set_1;
+ u32 irqenable_clr_1;
+
+ u32 reserve_4[15];
+
+ u32 utmi_otg_ctrl; /* offset of 0x80 */
+ u32 utmi_otg_status;
+
+ u32 reserve_5[30];
+
+ u32 mram_offset; /* offset of 0x100 */
+ u32 fladj;
+ u32 dbg_config;
+ u32 dbg_data;
+ u32 dev_ebc_en;
+};
+
+/* XHCI PHY register structure */
+struct omap_usb3_phy {
+ u32 reserve1;
+ u32 pll_status;
+ u32 pll_go;
+ u32 pll_config_1;
+ u32 pll_config_2;
+ u32 pll_config_3;
+ u32 pll_ssc_config_1;
+ u32 pll_ssc_config_2;
+ u32 pll_config_4;
+};
+
+struct omap_xhci {
+ struct omap_dwc_wrapper *otg_wrapper;
+ struct omap_usb3_phy *usb3_phy;
+ struct xhci_hccr *hcd;
+ struct dwc3 *dwc3_reg;
+};
+
+/* USB PHY functions */
+void omap_enable_phy(struct omap_xhci *omap);
+void omap_reset_usb_phy(struct dwc3 *dwc3_reg);
+void usb_phy_power(int on);
+
+#endif /* _ASM_ARCH_XHCI_OMAP_H_ */
/* LDOUSB control/voltage */
#define LDOUSB_CTRL 0x64
#define LDOUSB_VOLTAGE 0x65
+#define LDO_CTRL 0x6a
/* Control of 32 kHz audio clock */
#define CLK32KGAUDIO_CTRL 0xd5
#define SMPS9_CTRL 0x38
#define SMPS9_VOLTAGE 0x3b
+/* SMPS10_CTRL */
+#define SMPS10_CTRL 0x3c
+#define SMPS10_MODE_ACTIVE_D 0x0d
+
/* Bit field definitions for SMPSx_CTRL */
#define SMPS_MODE_ACT_AUTO 1
#define SMPS_MODE_ACT_ECO 2
int twl603x_mmc1_set_ldo9(u8 vsel);
int twl603x_audio_power(u8 on);
int twl603x_enable_bb_charge(u8 bb_fields);
+int palmas_enable_ss_ldo(void);
#endif /* PALMAS_H */
--- /dev/null
+/*
+ * thor.h -- USB THOR Downloader protocol
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __THOR_H_
+#define __THOR_H_
+
+#include <linux/usb/composite.h>
+
+int thor_handle(void);
+int thor_init(void);
+
+#ifdef CONFIG_THOR_FUNCTION
+int thor_add(struct usb_configuration *c);
+#else
+int thor_add(struct usb_configuration *c)
+{
+ return 0;
+}
+#endif
+#endif /* __THOR_H_ */
struct usb_device *children[USB_MAXCHILDREN];
void *controller; /* hardware controller private data */
+ /* slot_id - for xHCI enabled devices */
+ unsigned int slot_id;
+};
+
+/*
+ * You can initialize platform's USB host or device
+ * ports by passing this enum as an argument to
+ * board_usb_init().
+ */
+enum usb_init_type {
+ USB_INIT_HOST,
+ USB_INIT_DEVICE
};
/**********************************************************************
defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \
defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X) || \
defined(CONFIG_USB_MUSB_DSPS) || defined(CONFIG_USB_MUSB_AM35X) || \
- defined(CONFIG_USB_MUSB_OMAP2PLUS)
+ defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_XHCI)
-int usb_lowlevel_init(int index, void **controller);
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller);
int usb_lowlevel_stop(int index);
int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
extern void udc_disconnect(void);
-#else
-#error USB Lowlevel not defined
#endif
+/*
+ * board-specific hardware initialization, called by
+ * usb drivers and u-boot commands
+ *
+ * @param index USB controller number
+ * @param init initializes controller as USB host or device
+ */
+int board_usb_init(int index, enum usb_init_type init);
+
+/*
+ * can be used to clean up after failed USB initialization attempt
+ * vide: board_usb_init()
+ *
+ * @param index USB controller number for selective cleanup
+ * @param init usb_init_type passed to board_usb_init()
+ */
+int board_usb_cleanup(int index, enum usb_init_type init);
+
#ifdef CONFIG_USB_STORAGE
#define USB_MAX_STOR_DEV 5
#define usb_pipecontrol(pipe) (usb_pipetype((pipe)) == PIPE_CONTROL)
#define usb_pipebulk(pipe) (usb_pipetype((pipe)) == PIPE_BULK)
+#define usb_pipe_ep_index(pipe) \
+ usb_pipecontrol(pipe) ? (usb_pipeendpoint(pipe) * 2) : \
+ ((usb_pipeendpoint(pipe) * 2) - \
+ (usb_pipein(pipe) ? 0 : 1))
/*************************************************************************
* Hub Stuff
int usb_new_device(struct usb_device *dev);
void usb_free_device(void);
+int usb_alloc_device(struct usb_device *dev);
#endif /*_USB_H_ */
u32 *fifo_p;
};
-/*
- * USBTTY definitions
- */
-#define EP0_MAX_PACKET_SIZE 64
-#define UDC_INT_ENDPOINT 1
-#define UDC_INT_PACKET_SIZE 64
-#define UDC_OUT_ENDPOINT 2
-#define UDC_BULK_PACKET_SIZE 64
-#define UDC_BULK_HS_PACKET_SIZE 512
-#define UDC_IN_ENDPOINT 3
-#define UDC_OUT_PACKET_SIZE 64
-#define UDC_IN_PACKET_SIZE 64
-
/*
* UDC endpoint definitions
*/
#define UDC_EP2 2
#define UDC_EP3 3
-/*
- * Function declarations
- */
-
-void udc_irq(void);
-
-void udc_set_nak(int epid);
-void udc_unset_nak(int epid);
-int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
-int udc_init(void);
-void udc_enable(struct usb_device_instance *device);
-void udc_disable(void);
-void udc_connect(void);
-void udc_disconnect(void);
-void udc_startup_events(struct usb_device_instance *device);
-void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
- struct usb_endpoint_instance *endpoint);
-
#endif /* __DW_UDC_H */
/* UDC device defines */
#define EP0_MAX_PACKET_SIZE EP_MAX_PKT
-#define UDC_OUT_ENDPOINT 0x02
+
#define UDC_OUT_PACKET_SIZE EP_MIN_PACKET_SIZE
-#define UDC_IN_ENDPOINT 0x03
#define UDC_IN_PACKET_SIZE EP_MIN_PACKET_SIZE
-#define UDC_INT_ENDPOINT 0x01
#define UDC_INT_PACKET_SIZE UDC_IN_PACKET_SIZE
#define UDC_BULK_PACKET_SIZE EP_MIN_PACKET_SIZE
STATE_READY,
}mpc8xx_udc_state_t;
-/* Declarations */
-int udc_init(void);
-void udc_irq(void);
-int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
-void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
- struct usb_endpoint_instance *endpoint);
-void udc_connect(void);
-void udc_disconnect(void);
-void udc_enable(struct usb_device_instance *device);
-void udc_disable(void);
-void udc_startup_events(struct usb_device_instance *device);
-
-/* Flow control */
-void udc_set_nak(int epid);
-void udc_unset_nak (int epid);
+++ /dev/null
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __MUSB_UDC_H__
-#define __MUSB_UDC_H__
-
-#include <usbdevice.h>
-
-/* UDC level routines */
-void udc_irq(void);
-void udc_set_nak(int ep_num);
-void udc_unset_nak(int ep_num);
-int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
-void udc_setup_ep(struct usb_device_instance *device, unsigned int id,
- struct usb_endpoint_instance *endpoint);
-void udc_connect(void);
-void udc_disconnect(void);
-void udc_enable(struct usb_device_instance *device);
-void udc_disable(void);
-void udc_startup_events(struct usb_device_instance *device);
-int udc_init(void);
-
-/* usbtty */
-#ifdef CONFIG_USB_TTY
-
-#define EP0_MAX_PACKET_SIZE 64 /* MUSB_EP0_FIFOSIZE */
-#define UDC_INT_ENDPOINT 1
-#define UDC_INT_PACKET_SIZE 64
-#define UDC_OUT_ENDPOINT 2
-#define UDC_OUT_PACKET_SIZE 64
-#define UDC_IN_ENDPOINT 3
-#define UDC_IN_PACKET_SIZE 64
-#define UDC_BULK_PACKET_SIZE 64
-
-#endif /* CONFIG_USB_TTY */
-
-#endif /* __MUSB_UDC_H__ */
#ifndef __MV_UDC_H__
#define __MV_UDC_H__
-#include <asm/byteorder.h>
-#include <asm/errno.h>
-#include <linux/usb/ch9.h>
-#include <linux/usb/gadget.h>
-
-#include "../../drivers/usb/host/ehci.h"
-
-#define NUM_ENDPOINTS 6
-
-/* Endpoint parameters */
-#define MAX_ENDPOINTS 4
-
#define EP_MAX_PACKET_SIZE 0x200
#define EP0_MAX_PACKET_SIZE 64
-
-struct mv_udc {
-#define MICRO_8FRAME 0x8
-#define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16)
-#define USBCMD_FS2 (1 << 15)
-#define USBCMD_RST (1 << 1)
-#define USBCMD_RUN (1)
- u32 usbcmd; /* 0x140 */
-#define STS_SLI (1 << 8)
-#define STS_URI (1 << 6)
-#define STS_PCI (1 << 2)
-#define STS_UEI (1 << 1)
-#define STS_UI (1 << 0)
- u32 usbsts; /* 0x144 */
- u32 pad1[3];
- u32 devaddr; /* 0x154 */
- u32 epinitaddr; /* 0x158 */
- u32 pad2[10];
-#define PTS_ENABLE 2
-#define PTS(x) (((x) & 0x3) << 30)
-#define PFSC (1 << 24)
- u32 portsc; /* 0x184 */
- u32 pad3[8];
-#define USBMODE_DEVICE 2
- u32 usbmode; /* 0x1a8 */
- u32 epstat; /* 0x1ac */
-#define EPT_TX(x) (1 << (((x) & 0xffff) + 16))
-#define EPT_RX(x) (1 << ((x) & 0xffff))
- u32 epprime; /* 0x1b0 */
- u32 epflush; /* 0x1b4 */
- u32 pad4;
- u32 epcomp; /* 0x1bc */
-#define CTRL_TXE (1 << 23)
-#define CTRL_TXR (1 << 22)
-#define CTRL_RXE (1 << 7)
-#define CTRL_RXR (1 << 6)
-#define CTRL_TXT_BULK (2 << 18)
-#define CTRL_RXT_BULK (2 << 2)
- u32 epctrl[16]; /* 0x1c0 */
-};
-
-struct mv_ep {
- struct usb_ep ep;
- struct list_head queue;
- const struct usb_endpoint_descriptor *desc;
-
- struct usb_request req;
- uint8_t *b_buf;
- uint32_t b_len;
- uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN);
-};
-
-struct mv_drv {
- struct usb_gadget gadget;
- struct usb_gadget_driver *driver;
- struct ehci_ctrl *ctrl;
- struct ept_queue_head *epts;
- struct ept_queue_item *items[2 * NUM_ENDPOINTS];
- uint8_t *items_mem;
- struct mv_ep ep[NUM_ENDPOINTS];
-};
-
-struct ept_queue_head {
- unsigned config;
- unsigned current; /* read-only */
-
- unsigned next;
- unsigned info;
- unsigned page0;
- unsigned page1;
- unsigned page2;
- unsigned page3;
- unsigned page4;
- unsigned reserved_0;
-
- unsigned char setup_data[8];
-
- unsigned reserved_1;
- unsigned reserved_2;
- unsigned reserved_3;
- unsigned reserved_4;
-};
-
-#define CONFIG_MAX_PKT(n) ((n) << 16)
-#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */
-#define CONFIG_IOS (1 << 15) /* IRQ on setup */
-
-struct ept_queue_item {
- unsigned next;
- unsigned info;
- unsigned page0;
- unsigned page1;
- unsigned page2;
- unsigned page3;
- unsigned page4;
- unsigned reserved;
-};
-
-#define TERMINATE 1
-#define INFO_BYTES(n) ((n) << 16)
-#define INFO_IOC (1 << 15)
-#define INFO_ACTIVE (1 << 7)
-#define INFO_HALTED (1 << 6)
-#define INFO_BUFFER_ERROR (1 << 5)
-#define INFO_TX_ERROR (1 << 3)
-
#endif /* __MV_UDC_H__ */
#define UDC_VBUS_MODE (1 << 18)
/* OMAP Endpoint parameters */
-#define EP0_MAX_PACKET_SIZE 64
-#define UDC_OUT_ENDPOINT 2
-#define UDC_OUT_PACKET_SIZE 64
-#define UDC_IN_ENDPOINT 1
-#define UDC_IN_PACKET_SIZE 64
-#define UDC_INT_ENDPOINT 5
+#define UDC_OUT_PACKET_SIZE 64
+#define UDC_IN_PACKET_SIZE 64
#define UDC_INT_PACKET_SIZE 16
-#define UDC_BULK_PACKET_SIZE 16
-
-void udc_irq (void);
-/* Flow control */
-void udc_set_nak(int epid);
-void udc_unset_nak (int epid);
-
-/* Higher level functions for abstracting away from specific device */
-int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
-
-int udc_init (void);
+#define UDC_BULK_PACKET_SIZE 16
-void udc_enable(struct usb_device_instance *device);
-void udc_disable(void);
-
-void udc_connect(void);
-void udc_disconnect(void);
-
-void udc_startup_events(struct usb_device_instance *device);
-void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, struct usb_endpoint_instance *endpoint);
+#define UDC_INT_ENDPOINT 5
+#define UDC_OUT_ENDPOINT 2
+#define UDC_IN_ENDPOINT 1
#endif
/* Endpoint parameters */
#define MAX_ENDPOINTS 4
-#define EP_MAX_PACKET_SIZE 64
#define EP0_MAX_PACKET_SIZE 16
+
#define UDC_OUT_ENDPOINT 0x02
-#define UDC_OUT_PACKET_SIZE EP_MAX_PACKET_SIZE
#define UDC_IN_ENDPOINT 0x01
-#define UDC_IN_PACKET_SIZE EP_MAX_PACKET_SIZE
#define UDC_INT_ENDPOINT 0x05
-#define UDC_INT_PACKET_SIZE EP_MAX_PACKET_SIZE
-#define UDC_BULK_PACKET_SIZE EP_MAX_PACKET_SIZE
-
-void udc_irq(void);
-/* Flow control */
-void udc_set_nak(int epid);
-void udc_unset_nak(int epid);
-
-/* Higher level functions for abstracting away from specific device */
-int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
-
-int udc_init(void);
-
-void udc_enable(struct usb_device_instance *device);
-void udc_disable(void);
-
-void udc_connect(void);
-void udc_disconnect(void);
-
-void udc_startup_events(struct usb_device_instance *device);
-void udc_setup_ep(struct usb_device_instance *device,
- unsigned int ep, struct usb_endpoint_instance *endpoint);
#endif
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef USB_UDC_H
+#define USB_UDC_H
+
+#ifndef EP0_MAX_PACKET_SIZE
+#define EP0_MAX_PACKET_SIZE 64
+#endif
+
+#ifndef EP_MAX_PACKET_SIZE
+#define EP_MAX_PACKET_SIZE 64
+#endif
+
+#if !defined(CONFIG_PPC) && !defined(CONFIG_OMAP1510)
+/* omap1510_udc.h and mpc8xx_udc.h will set these values */
+#define UDC_OUT_PACKET_SIZE EP_MAX_PACKET_SIZE
+#define UDC_IN_PACKET_SIZE EP_MAX_PACKET_SIZE
+#define UDC_INT_PACKET_SIZE EP_MAX_PACKET_SIZE
+#define UDC_BULK_PACKET_SIZE EP_MAX_PACKET_SIZE
+#endif
+
+#define UDC_BULK_HS_PACKET_SIZE 512
+
+#ifndef UDC_INT_ENDPOINT
+#define UDC_INT_ENDPOINT 1
+#endif
+
+#ifndef UDC_OUT_ENDPOINT
+#define UDC_OUT_ENDPOINT 2
+#endif
+
+#ifndef UDC_IN_ENDPOINT
+#define UDC_IN_ENDPOINT 3
+#endif
+
+/* function declarations */
+int udc_init(void);
+void udc_irq(void);
+int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
+void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
+ struct usb_endpoint_instance *endpoint);
+void udc_connect(void);
+void udc_disconnect(void);
+void udc_enable(struct usb_device_instance *device);
+void udc_disable(void);
+void udc_startup_events(struct usb_device_instance *device);
+
+/* Flow control */
+void udc_set_nak(int epid);
+void udc_unset_nak(int epid);
+
+#endif
#define USB_DIR_OUT 0
#define USB_DIR_IN 0x80
+/*
+ * bmRequestType: USB Device Requests, table 9.2 USB 2.0 spec.
+ * (shifted) direction/type/recipient.
+ */
+#define DeviceRequest \
+ ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define DeviceOutRequest \
+ ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define InterfaceRequest \
+ ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointRequest \
+ ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointOutRequest \
+ ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
/* Descriptor types */
#define USB_DT_DEVICE 0x01
#define USB_DT_CONFIG 0x02
struct ums_device ums_dev;
};
-extern void board_usb_init(void);
-
-extern int fsg_init(struct ums_board_info *);
-extern void fsg_cleanup(void);
-extern struct ums_board_info *board_ums_init(unsigned int,
- unsigned int, unsigned int);
-extern int usb_gadget_handle_interrupts(void);
-extern int fsg_main_thread(void *);
+int fsg_init(struct ums_board_info *);
+void fsg_cleanup(void);
+struct ums_board_info *board_ums_init(unsigned int, unsigned int,
+ unsigned int);
+int fsg_main_thread(void *);
#ifdef CONFIG_USB_GADGET_MASS_STORAGE
int fsg_add(struct usb_configuration *c);
COMPAT(GOOGLE_CROS_EC, "google,cros-ec"),
COMPAT(GOOGLE_CROS_EC_KEYB, "google,cros-ec-keyb"),
COMPAT(SAMSUNG_EXYNOS_EHCI, "samsung,exynos-ehci"),
+ COMPAT(SAMSUNG_EXYNOS5_XHCI, "samsung,exynos5250-xhci"),
COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),
+ COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),
COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"),
COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"),
COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
projects / karo-tx-uboot.git / commitdiff