powerpc/corenet_ds: Update DDR timing for single-rank DIMMs

Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed
800, 900, 1000, 1200, 1300MT/s.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 4a53b8d9337efc9ae96b062328427da0ff0f0faf..da284cde9556aa330acf85adcdf544e6614919fe 100644 (file)
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -139,8 +139,8 @@ static const struct board_specific_parameters udimm0[] = {
        {2,  1250,    4,     6,   0xff,    2,  0},
        {2,  1350,    5,     7,   0xff,    2,  0},
        {2,  1666,    5,     8,   0xff,    2,  0},
-       {1,   850,    4,     5,   0xff,    2,  0},
-       {1,   950,    4,     7,   0xff,    2,  0},
+       {1,  1250,    4,     6,   0xff,    2,  0},
+       {1,  1335,    4,     7,   0xff,    2,  0},
        {1,  1666,    4,     8,   0xff,    2,  0},
        {}
 };