]> git.kernelconcepts.de Git - karo-tx-uboot.git/commitdiff
am33xx: init OTG hardware and new musb gadget driver
authorIlya Yanok <ilya.yanok@cogentembedded.com>
Tue, 6 Nov 2012 13:48:23 +0000 (13:48 +0000)
committerMarek Vasut <marex@denx.de>
Mon, 19 Nov 2012 23:16:07 +0000 (00:16 +0100)
AM33xx has support for dual port MUSB OTG controller. This patch
adds initialization for the controller using new MUSB gadget
driver and ether gadget.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/am33xx/clock.c
arch/arm/include/asm/arch-am33xx/cpu.h
arch/arm/include/asm/arch-am33xx/hardware.h

index e4c123cd21d614f3b2bee6a3aabf6a9e5288be56..da5bc731852c428078fe76fa484240096f62c6a0 100644 (file)
 #include <i2c.h>
 #include <miiphy.h>
 #include <cpsw.h>
+#include <asm/errno.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/musb.h>
+#include <asm/omap_musb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -63,3 +68,83 @@ void setup_clocks_for_console(void)
        /* Not yet implemented */
        return;
 }
+
+/* AM33XX has two MUSB controllers which can be host or gadget */
+#if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
+       (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* USB 2.0 PHY Control */
+#define CM_PHY_PWRDN                   (1 << 0)
+#define CM_PHY_OTG_PWRDN               (1 << 1)
+#define OTGVDET_EN                     (1 << 19)
+#define OTGSESSENDEN                   (1 << 20)
+
+static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
+{
+       if (on) {
+               clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
+                               OTGVDET_EN | OTGSESSENDEN);
+       } else {
+               clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
+       }
+}
+
+static struct musb_hdrc_config musb_config = {
+       .multipoint     = 1,
+       .dyn_fifo       = 1,
+       .num_eps        = 16,
+       .ram_bits       = 12,
+};
+
+#ifdef CONFIG_AM335X_USB0
+static void am33xx_otg0_set_phy_power(u8 on)
+{
+       am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
+}
+
+struct omap_musb_board_data otg0_board_data = {
+       .set_phy_power = am33xx_otg0_set_phy_power,
+};
+
+static struct musb_hdrc_platform_data otg0_plat = {
+       .mode           = CONFIG_AM335X_USB0_MODE,
+       .config         = &musb_config,
+       .power          = 50,
+       .platform_ops   = &musb_dsps_ops,
+       .board_data     = &otg0_board_data,
+};
+#endif
+
+#ifdef CONFIG_AM335X_USB1
+static void am33xx_otg1_set_phy_power(u8 on)
+{
+       am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
+}
+
+struct omap_musb_board_data otg1_board_data = {
+       .set_phy_power = am33xx_otg1_set_phy_power,
+};
+
+static struct musb_hdrc_platform_data otg1_plat = {
+       .mode           = CONFIG_AM335X_USB1_MODE,
+       .config         = &musb_config,
+       .power          = 50,
+       .platform_ops   = &musb_dsps_ops,
+       .board_data     = &otg1_board_data,
+};
+#endif
+#endif
+
+int arch_misc_init(void)
+{
+#ifdef CONFIG_AM335X_USB0
+       musb_register(&otg0_plat, &otg0_board_data,
+               (void *)AM335X_USB0_OTG_BASE);
+#endif
+#ifdef CONFIG_AM335X_USB1
+       musb_register(&otg1_plat, &otg1_board_data,
+               (void *)AM335X_USB1_OTG_BASE);
+#endif
+       return 0;
+}
index bc2abb657cf3d54a6dcc5fc4b2a7dd67b0131b33..0b4cb4e529e6c5301c7809890355e41d68fd5ece 100644 (file)
@@ -40,6 +40,7 @@
 #define CLK_MODE_MASK          0xfffffff8
 #define CLK_DIV_SEL            0xFFFFFFE0
 #define CPGMAC0_IDLE           0x30000
+#define DPLL_CLKDCOLDO_GATE_CTRL        0x300
 
 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
@@ -194,6 +195,11 @@ static void enable_per_clocks(void)
        writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
        while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
                ;
+
+       /* MUSB */
+       writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
+       while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
+               ;
 }
 
 static void mpu_pll_config(void)
@@ -290,6 +296,8 @@ static void per_pll_config(void)
 
        while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
                ;
+
+       writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
 }
 
 void ddr_pll_config(unsigned int ddrpll_m)
index 819fd2f026900bf82491035b4e513fc9b84f8e46..d6c038e3aec225a46dd13af6ded8e59c1ed621e9 100644 (file)
@@ -82,7 +82,8 @@ struct cm_wkuppll {
        unsigned int clkseldpllcore;    /* offset 0x68 */
        unsigned int resv9[1];
        unsigned int idlestdpllper;     /* offset 0x70 */
-       unsigned int resv10[3];
+       unsigned int resv10[2];
+       unsigned int clkdcoldodpllper;  /* offset 0x7c */
        unsigned int divm4dpllcore;     /* offset 0x80 */
        unsigned int divm5dpllcore;     /* offset 0x84 */
        unsigned int clkmoddpllmpu;     /* offset 0x88 */
@@ -275,12 +276,16 @@ struct ctrl_stat {
 /* Control Device Register */
 struct ctrl_dev {
        unsigned int deviceid;          /* offset 0x00 */
-       unsigned int resv1[11];
+       unsigned int resv1[7];
+       unsigned int usb_ctrl0;         /* offset 0x20 */
+       unsigned int resv2;
+       unsigned int usb_ctrl1;         /* offset 0x28 */
+       unsigned int resv3;
        unsigned int macid0l;           /* offset 0x30 */
        unsigned int macid0h;           /* offset 0x34 */
        unsigned int macid1l;           /* offset 0x38 */
        unsigned int macid1h;           /* offset 0x3c */
-       unsigned int resv2[4];
+       unsigned int resv4[4];
        unsigned int miisel;            /* offset 0x50 */
 };
 #endif /* __ASSEMBLY__ */
index 5bd4bc8722016e04c86fe0e4b33daeafaa1d9454..24ab365ea31ebdfa6faeb4a07defd197e59a40f9 100644 (file)
@@ -87,4 +87,8 @@
 /* RTC base address */
 #define AM335X_RTC_BASE                        0x44E3E000
 
+/* OTG */
+#define AM335X_USB0_OTG_BASE           0x47401000
+#define AM335X_USB1_OTG_BASE           0x47401800
+
 #endif /* __AM33XX_HARDWARE_H */