{
u32 div;
u64 freq;
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
switch (pll) {
case PLL_528:
u32 reg = 0;
s32 timeout = 100000;
- struct anatop_regs __iomem *anatop =
- (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
-
if (freq < ENET_25MHZ || freq > ENET_125MHZ)
return -EINVAL;
#ifdef CONFIG_CMD_SATA
static void ungate_sata_clock(void)
{
- struct mxc_ccm_reg *const imx_ccm =
- (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
/* Enable SATA clock. */
setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
}
void disable_sata_clock(void)
{
- struct mxc_ccm_reg *const imx_ccm =
- (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
}
#endif
#ifdef CONFIG_PCIE_IMX
static void ungate_pcie_clock(void)
{
- struct mxc_ccm_reg *const imx_ccm =
- (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
/* Enable PCIe clock. */
setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
}
int enable_pcie_clock(void)
{
- struct anatop_regs *anatop_regs =
- (struct anatop_regs *)ANATOP_BASE_ADDR;
- struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
u32 lvds1_clk_sel;
/*
static void enable_pll3(void)
{
- struct anatop_regs __iomem *anatop =
- (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
-
/* make sure pll3 is enabled */
if ((readl(&anatop->usb1_pll_480_ctrl) &
BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
#ifndef CONFIG_SOC_MX6SX
void enable_ipu_clock(void)
{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- int reg;
- reg = readl(&mxc_ccm->CCGR3);
+ int reg = readl(&imx_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
- writel(reg, &mxc_ccm->CCGR3);
+ writel(reg, &imx_ccm->CCGR3);
if (is_mx6dqp()) {
- setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
- setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
+ setbits_le32(&imx_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
+ setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
}
}
#endif