powerpc: remove NX823 board support

Enough time has passed since this board was moved to Orphan. Remove.

 - Remove board/nx823/*
 - Remove include/configs/NX823.h
 - Clean-up ifdef(CONFIG_NX823)
 - Move the entry from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
index 3c2842057487dc0fc562577ff79bbebe214dfbd0..f4d4a6b30033327e74e6c12f5bc7656321e4d3e8 100644 (file)
--- a/arch/powerpc/include/asm/u-boot.h
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -106,9 +106,6 @@ typedef struct bd_info {
        unsigned int    bi_opbfreq;             /* OPB clock in Hz */
        int             bi_iic_fast[2];         /* Use fast i2c mode */
 #endif
        unsigned int    bi_opbfreq;             /* OPB clock in Hz */
        int             bi_iic_fast[2];         /* Use fast i2c mode */
 #endif

-#if defined(CONFIG_NX823)
-       unsigned char   bi_sernum[8];
-#endif

 #if defined(CONFIG_4xx)
 #if defined(CONFIG_440GX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #if defined(CONFIG_4xx)
 #if defined(CONFIG_440GX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)

diff --git a/board/nx823/Makefile b/board/nx823/Makefile
deleted file mode 100644 (file)
index a22be5c..0000000
--- a/board/nx823/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  = nx823.o flash.o

diff --git a/board/nx823/flash.c b/board/nx823/flash.c
deleted file mode 100644 (file)
index fbe17dd..0000000
--- a/board/nx823/flash.c
+++ /dev/null
@@ -1,449 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-flash_info_t   flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Protection Flags:
- */
-#define FLAG_PROTECT_SET       0x01
-#define FLAG_PROTECT_CLEAR     0x02
-
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH               ushort
-#define FLASH_PORT_WIDTHV              vu_short
-#else
-#define FLASH_PORT_WIDTH               ulong
-#define FLASH_PORT_WIDTHV              vu_long
-#endif
-
-#define FPW            FLASH_PORT_WIDTH
-#define FPWV   FLASH_PORT_WIDTHV
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (FPW *addr, flash_info_t *info);
-static int   write_data (flash_info_t *info, ulong dest, FPW data);
-static void  flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-       volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-       unsigned long size_b0;
-       int i;
-
-       /* Init: no FLASHes known */
-       for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-               flash_info[i].flash_id = FLASH_UNKNOWN;
-       }
-
-       /* Static FLASH Bank configuration here - FIXME XXX */
-       size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-       if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-               printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-                       size_b0, size_b0<<20);
-       }
-
-       /* Remap FLASH according to real size */
-       memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-       memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
-
-       /* Re-do sizing to get full correct info */
-       size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-       flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-       /* monitor protection ON by default */
-       (void)flash_protect(FLAG_PROTECT_SET,
-                           CONFIG_SYS_FLASH_BASE,
-                           CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
-                           &flash_info[0]);
-
-       flash_info[0].size = size_b0;
-
-       return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-       int i;
-
-       if (info->flash_id == FLASH_UNKNOWN) {
-               return;
-       }
-
-       if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-               for (i = 0; i < info->sector_count; i++) {
-                       info->start[i] = base + (i * 0x00020000);
-               }
-       }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-       int i;
-
-       if (info->flash_id == FLASH_UNKNOWN) {
-               printf ("missing or unknown FLASH type\n");
-               return;
-       }
-
-       switch (info->flash_id & FLASH_VENDMASK) {
-               case FLASH_MAN_INTEL:   printf ("INTEL ");              break;
-               default:                printf ("Unknown Vendor ");     break;
-       }
-
-       switch (info->flash_id & FLASH_TYPEMASK) {
-   case FLASH_28F320J3A:
-                               printf ("28F320J3A\n"); break;
-   case FLASH_28F640J3A:
-                               printf ("28F640J3A\n"); break;
-   case FLASH_28F128J3A:
-                               printf ("28F128J3A\n"); break;
-       default:                printf ("Unknown Chip Type\n"); break;
-       }
-
-       printf ("  Size: %ld MB in %d Sectors\n",
-               info->size >> 20, info->sector_count);
-
-       printf ("  Sector Start Addresses:");
-       for (i=0; i<info->sector_count; ++i) {
-               if ((i % 5) == 0)
-                       printf ("\n   ");
-               printf (" %08lX%s",
-                       info->start[i],
-                       info->protect[i] ? " (RO)" : "     "
-               );
-       }
-       printf ("\n");
-       return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (FPW *addr, flash_info_t *info)
-{
-       FPW value;
-
-       /* Write auto select command: read Manufacturer ID */
-       addr[0x5555] = (FPW)0x00AA00AA;
-       addr[0x2AAA] = (FPW)0x00550055;
-       addr[0x5555] = (FPW)0x00900090;
-
-       value = addr[0];
-
-   switch (value) {
-   case (FPW)INTEL_MANUFACT:
-      info->flash_id = FLASH_MAN_INTEL;
-      break;
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               info->sector_count = 0;
-               info->size = 0;
-               addr[0] = (FPW)0x00FF00FF;      /* restore read mode */
-               return (0);                     /* no or unknown flash  */
-       }
-
-       value = addr[1];                        /* device ID            */
-
-   switch (value) {
-   case (FPW)INTEL_ID_28F320J3A:
-      info->flash_id += FLASH_28F320J3A;
-      info->sector_count = 32;
-      info->size = 0x00400000;
-      break;            /* => 4 MB     */
-
-   case (FPW)INTEL_ID_28F640J3A:
-      info->flash_id += FLASH_28F640J3A;
-      info->sector_count = 64;
-      info->size = 0x00800000;
-      break;            /* => 8 MB     */
-
-   case (FPW)INTEL_ID_28F128J3A:
-      info->flash_id += FLASH_28F128J3A;
-      info->sector_count = 128;
-      info->size = 0x01000000;
-      break;            /* => 16 MB     */
-
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               break;
-       }
-
-       if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
-               printf ("** ERROR: sector count %d > max (%d) **\n",
-                       info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-               info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-       }
-
-       addr[0] = (FPW)0x00FF00FF;      /* restore read mode */
-
-       return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int    flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-       int flag, prot, sect;
-       ulong type, start, now, last;
-       int rcode = 0;
-
-       if ((s_first < 0) || (s_first > s_last)) {
-               if (info->flash_id == FLASH_UNKNOWN) {
-                       printf ("- missing\n");
-               } else {
-                       printf ("- no sectors to erase\n");
-               }
-               return 1;
-       }
-
-       type = (info->flash_id & FLASH_VENDMASK);
-       if ((type != FLASH_MAN_INTEL)) {
-               printf ("Can't erase unknown flash type %08lx - aborted\n",
-                       info->flash_id);
-               return 1;
-       }
-
-       prot = 0;
-       for (sect=s_first; sect<=s_last; ++sect) {
-               if (info->protect[sect]) {
-                       prot++;
-               }
-       }
-
-       if (prot) {
-               printf ("- Warning: %d protected sectors will not be erased!\n",
-                       prot);
-       } else {
-               printf ("\n");
-       }
-
-       start = get_timer (0);
-       last  = start;
-       /* Start erase on unprotected sectors */
-       for (sect = s_first; sect<=s_last; sect++) {
-               if (info->protect[sect] == 0) { /* not protected */
-                       FPWV *addr = (FPWV *)(info->start[sect]);
-                       FPW status;
-
-                       /* Disable interrupts which might cause a timeout here */
-                       flag = disable_interrupts();
-
-                       *addr = (FPW)0x00500050;        /* clear status register */
-                       *addr = (FPW)0x00200020;        /* erase setup */
-                       *addr = (FPW)0x00D000D0;        /* erase confirm */
-
-                       /* re-enable interrupts if necessary */
-                       if (flag)
-                               enable_interrupts();
-
-                       /* wait at least 80us - let's wait 1 ms */
-                       udelay (1000);
-
-                       while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
-                               if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-                                       printf ("Timeout\n");
-                                       *addr = (FPW)0x00B000B0; /* suspend erase         */
-                                       *addr = (FPW)0x00FF00FF; /* reset to read mode */
-                                       rcode = 1;
-                                       break;
-                               }
-
-                               /* show that we're waiting */
-                       if ((now - last) > 1000) {      /* every second */
-                                       putc ('.');
-                                       last = now;
-                               }
-                       }
-
-                       *addr = (FPW)0x00FF00FF;        /* reset to read mode */
-                       printf (" done\n");
-               }
-       }
-       return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-       ulong cp, wp;
-       FPW data;
-       int count, i, l, rc, port_width;
-
-       if (info->flash_id == FLASH_UNKNOWN) {
-               return 4;
-       }
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
-       wp = (addr & ~1);
-       port_width = 2;
-#else
-       wp = (addr & ~3);
-       port_width = 4;
-#endif
-
-       /* save sernum if needed */
-       if (addr >= CONFIG_SYS_FLASH_SN_SECTOR && addr < CONFIG_SYS_FLASH_SN_BASE)
-       {
-               u_long dest = CONFIG_SYS_FLASH_SN_BASE;
-               u_short *sn = (u_short *)gd->bd->bi_sernum;
-
-               printf("(saving sernum)");
-               for (i=0; i<4; i++)
-               {
-                       if ((rc = write_data(info, dest, sn[i])) != 0) {
-                               return (rc);
-                       }
-                       dest += port_width;
-               }
-       }
-
-       /*
-        * handle unaligned start bytes
-        */
-       if ((l = addr - wp) != 0) {
-               data = 0;
-               for (i=0, cp=wp; i<l; ++i, ++cp) {
-                       data = (data << 8) | (*(uchar *)cp);
-               }
-               for (; i<port_width && cnt>0; ++i) {
-                       data = (data << 8) | *src++;
-                       --cnt;
-                       ++cp;
-               }
-               for (; cnt==0 && i<port_width; ++i, ++cp) {
-                       data = (data << 8) | (*(uchar *)cp);
-               }
-
-               if ((rc = write_data(info, wp, data)) != 0) {
-                       return (rc);
-               }
-               wp += port_width;
-       }
-
-       /*
-        * handle word aligned part
-        */
-       count = 0;
-       while (cnt >= port_width) {
-               data = 0;
-               for (i=0; i<port_width; ++i) {
-                       data = (data << 8) | *src++;
-               }
-               if ((rc = write_data(info, wp, data)) != 0) {
-                       return (rc);
-               }
-               wp  += port_width;
-               cnt -= port_width;
-               if (count++ > 0x800)
-               {
-                       putc('.');
-                       count = 0;
-               }
-       }
-
-       if (cnt == 0) {
-               return (0);
-       }
-
-       /*
-        * handle unaligned tail bytes
-        */
-       data = 0;
-       for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) {
-               data = (data << 8) | *src++;
-               --cnt;
-       }
-       for (; i<port_width; ++i, ++cp) {
-               data = (data << 8) | (*(uchar *)cp);
-       }
-
-       return (write_data(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, ulong dest, FPW data)
-{
-       FPWV *addr = (FPWV *)dest;
-       ulong status;
-       ulong start;
-       int flag;
-
-       /* Check if Flash is (sufficiently) erased */
-       if ((*addr & data) != data) {
-               printf("not erased at %08lx (%x)\n",(ulong)addr,*addr);
-               return (2);
-       }
-       /* Disable interrupts which might cause a timeout here */
-       flag = disable_interrupts();
-
-       *addr = (FPW)0x00400040;                /* write setup */
-       *addr = data;
-
-       /* re-enable interrupts if necessary */
-       if (flag)
-               enable_interrupts();
-
-       start = get_timer (0);
-
-       while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
-               if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-                       *addr = (FPW)0x00FF00FF;        /* restore read mode */
-                       return (1);
-               }
-       }
-
-       *addr = (FPW)0x00FF00FF;        /* restore read mode */
-
-       return (0);
-}

diff --git a/board/nx823/nx823.c b/board/nx823/nx823.c
deleted file mode 100644 (file)
index d49fa8c..0000000
--- a/board/nx823/nx823.c
+++ /dev/null
@@ -1,374 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001-2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <mpc8xx.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static long int dram_size (long int, long int *, long int);
-
-#define        _NOT_USED_      0xFFFFFFFF
-
-const uint sdram_table[] = {
-#if (MPC8XX_SPEED <= 50000000L)
-       /*
-        * Single Read. (Offset 0 in UPMA RAM)
-        */
-       0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07,
-       0xFFFFFFFF,
-
-       /*
-        * SDRAM Initialization (offset 5 in UPMA RAM)
-        *
-        * This is no UPM entry point. The following definition uses
-        * the remaining space to establish an initialization
-        * sequence, which is executed by a RUN command.
-        *
-        */
-       0x1FE7F434, 0xEFABE834, 0x1FA7D435,
-
-       /*
-        * Burst Read. (Offset 8 in UPMA RAM)
-        */
-       0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00,
-       0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF,
-       0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-       0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
-       /*
-        * Single Write. (Offset 18 in UPMA RAM)
-        */
-       0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF,
-       0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
-       /*
-        * Burst Write. (Offset 20 in UPMA RAM)
-        */
-       0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00,
-       0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-       0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-       0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
-       /*
-        * Refresh  (Offset 30 in UPMA RAM)
-        */
-       0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07,
-       0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-       0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
-       /*
-        * Exception. (Offset 3c in UPMA RAM)
-        */
-       0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
-#else
-
-       /*
-        * Single Read. (Offset 0 in UPMA RAM)
-        */
-       0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800,
-       0x1FF7F447,
-
-       /*
-        * SDRAM Initialization (offset 5 in UPMA RAM)
-        *
-        * This is no UPM entry point. The following definition uses
-        * the remaining space to establish an initialization
-        * sequence, which is executed by a RUN command.
-        *
-        */
-       0x1FF7F434, 0xEFEBE834, 0x1FB7D435,
-
-       /*
-        * Burst Read. (Offset 8 in UPMA RAM)
-        */
-       0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00,
-       0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /*
-        * Single Write. (Offset 18 in UPMA RAM)
-        */
-       0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /*
-        * Burst Write. (Offset 20 in UPMA RAM)
-        */
-       0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00,
-       0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /*
-        * Refresh  (Offset 30 in UPMA RAM)
-        */
-       0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-       0xFFFFFC84, 0xFFFFFC07,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /*
-        * Exception. (Offset 3c in UPMA RAM)
-        */
-       0x7FFFFC07,             /* last */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-#endif
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- */
-
-int checkboard (void)
-{
-       printf ("Board: Nexus NX823");
-       return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-       long int size_b0, size_b1, size8, size9;
-
-       upmconfig (UPMA, (uint *) sdram_table,
-                  sizeof (sdram_table) / sizeof (uint));
-
-       /*
-        * Up to 2 Banks of 64Mbit x 2 devices
-        * Initial builds only have 1
-        */
-       memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
-       memctl->memc_mar = 0x00000088;
-
-       /*
-        * Map controller SDRAM bank 0
-        */
-       memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
-       memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
-       memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));      /* no refresh yet */
-       udelay (200);
-
-       /*
-        * Map controller SDRAM bank 1
-        */
-       memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
-       memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-
-       /*
-        * Perform SDRAM initializsation sequence
-        */
-       memctl->memc_mcr = 0x80002105;  /* SDRAM bank 0 */
-       udelay (1);
-       memctl->memc_mcr = 0x80002230;  /* SDRAM bank 0 - execute twice */
-       udelay (1);
-
-       memctl->memc_mcr = 0x80004105;  /* SDRAM bank 1 */
-       udelay (1);
-       memctl->memc_mcr = 0x80004230;  /* SDRAM bank 1 - execute twice */
-       udelay (1);
-
-       memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-       udelay (1000);
-
-       /*
-        * Preliminary prescaler for refresh (depends on number of
-        * banks): This value is selected for four cycles every 62.4 us
-        * with two SDRAM banks or four cycles every 31.2 us with one
-        * bank. It will be adjusted after memory sizing.
-        */
-       memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
-
-       memctl->memc_mar = 0x00000088;
-
-
-       /*
-        * Check Bank 0 Memory Size for re-configuration
-        *
-        * try 8 column mode
-        */
-       size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM,
-                          SDRAM_MAX_SIZE);
-
-       udelay (1000);
-
-       /*
-        * try 9 column mode
-        */
-       size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM,
-                          SDRAM_MAX_SIZE);
-
-       if (size8 < size9) {    /* leave configuration at 9 columns     */
-               size_b0 = size9;
-/*     debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);  */
-       } else {                /* back to 8 columns                    */
-               size_b0 = size8;
-               memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
-               udelay (500);
-/*     debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);  */
-       }
-
-       /*
-        * Check Bank 1 Memory Size
-        * use current column settings
-        * [9 column SDRAM may also be used in 8 column mode,
-        *  but then only half the real size will be used.]
-        */
-       size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM,
-                            SDRAM_MAX_SIZE);
-/*     debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20);  */
-
-       udelay (1000);
-
-       /*
-        * Adjust refresh rate depending on SDRAM type, both banks
-        * For types > 128 MBit leave it at the current (fast) rate
-        */
-       if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
-               /* reduce to 15.6 us (62.4 us / quad) */
-               memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
-               udelay (1000);
-       }
-
-       /*
-        * Final mapping: map bigger bank first
-        */
-       if (size_b1 > size_b0) {        /* SDRAM Bank 1 is bigger - map first   */
-
-               memctl->memc_or2 =
-                       ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-               memctl->memc_br2 =
-                       (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
-               if (size_b0 > 0) {
-                       /*
-                        * Position Bank 0 immediately above Bank 1
-                        */
-                       memctl->memc_or1 =
-                               ((-size_b0) & 0xFFFF0000) |
-                               CONFIG_SYS_OR_TIMING_SDRAM;
-                       memctl->memc_br1 =
-                               ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
-                                BR_V)
-                               + size_b1;
-               } else {
-                       unsigned long reg;
-
-                       /*
-                        * No bank 0
-                        *
-                        * invalidate bank
-                        */
-                       memctl->memc_br1 = 0;
-
-                       /* adjust refresh rate depending on SDRAM type, one bank */
-                       reg = memctl->memc_mptpr;
-                       reg >>= 1;      /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
-                       memctl->memc_mptpr = reg;
-               }
-
-       } else {                /* SDRAM Bank 0 is bigger - map first   */
-
-               memctl->memc_or1 =
-                       ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-               memctl->memc_br1 =
-                       (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
-               if (size_b1 > 0) {
-                       /*
-                        * Position Bank 1 immediately above Bank 0
-                        */
-                       memctl->memc_or2 =
-                               ((-size_b1) & 0xFFFF0000) |
-                               CONFIG_SYS_OR_TIMING_SDRAM;
-                       memctl->memc_br2 =
-                               ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
-                                BR_V)
-                               + size_b0;
-               } else {
-                       unsigned long reg;
-
-                       /*
-                        * No bank 1
-                        *
-                        * invalidate bank
-                        */
-                       memctl->memc_br2 = 0;
-
-                       /* adjust refresh rate depending on SDRAM type, one bank */
-                       reg = memctl->memc_mptpr;
-                       reg >>= 1;      /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
-                       memctl->memc_mptpr = reg;
-               }
-       }
-
-       udelay (10000);
-
-       return (size_b0 + size_b1);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
-                          long int maxsize)
-{
-       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-       memctl->memc_mamr = mamr_value;
-
-       return (get_ram_size (base, maxsize));
-}
-
-int misc_init_r (void)
-{
-       int i;
-       char tmp[50];
-       uchar ethaddr[6];
-       bd_t *bd = gd->bd;
-       ulong *my_sernum = (unsigned long *)&bd->bi_sernum;
-
-       /* load unique serial number */
-       for (i = 0; i < 8; ++i)
-               bd->bi_sernum[i] = *(u_char *) (CONFIG_SYS_FLASH_SN_BASE + i);
-
-       /* save env variables according to sernum */
-       sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]);
-       setenv ("serial#", tmp);
-
-       if (!eth_getenv_enetaddr("ethaddr", ethaddr)) {
-               ethaddr[0] = 0x10;
-               ethaddr[1] = 0x20;
-               ethaddr[2] = 0x30;
-               ethaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2];
-               ethaddr[4] = bd->bi_sernum[5];
-               ethaddr[5] = bd->bi_sernum[6];
-       }
-
-       return 0;
-}

diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds
deleted file mode 100644 (file)
index 7ae91ff..0000000
--- a/board/nx823/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2001-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    arch/powerpc/cpu/mpc8xx/start.o    (.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o    (.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-       KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}

diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug
deleted file mode 100644 (file)
index b0091db..0000000
--- a/board/nx823/u-boot.lds.debug
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)          }
-  .dynsym        : { *(.dynsym)                }
-  .dynstr        : { *(.dynstr)                }
-  .rel.text      : { *(.rel.text)              }
-  .rela.text     : { *(.rela.text)     }
-  .rel.data      : { *(.rel.data)              }
-  .rela.data     : { *(.rela.data)     }
-  .rel.rodata    : { *(.rel.rodata)    }
-  .rela.rodata   : { *(.rela.rodata)   }
-  .rel.got       : { *(.rel.got)               }
-  .rela.got      : { *(.rela.got)              }
-  .rel.ctors     : { *(.rel.ctors)     }
-  .rela.ctors    : { *(.rela.ctors)    }
-  .rel.dtors     : { *(.rel.dtors)     }
-  .rela.dtors    : { *(.rela.dtors)    }
-  .rel.bss       : { *(.rel.bss)               }
-  .rela.bss      : { *(.rela.bss)              }
-  .rel.plt       : { *(.rel.plt)               }
-  .rela.plt      : { *(.rela.plt)              }
-  .init          : { *(.init)  }
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within */
-    /* the sector layout of our flash chips!   XXX FIXME XXX   */
-
-    arch/powerpc/cpu/mpc8xx/start.o    (.text)
-    common/dlmalloc.o  (.text)
-    lib/vsprintf.o     (.text)
-    lib/crc32.o                (.text)
-
-    . = env_offset;
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = ALIGN(4);
-  .u_boot_list : {
-       KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}

diff --git a/boards.cfg b/boards.cfg
index 2b9b0c09700d7232c9906d792d085509dd93d97a..26e784b01c4b8d710f414a26e7c86dd2999a57bc 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -1255,4 +1255,3 @@ Orphan  powerpc     mpc8xx         -           -               fads
 Orphan  powerpc     mpc8xx         -           -               genietv             GENIETV                              -                                                                                                                                 -
 Orphan  powerpc     mpc8xx         -           -               mbx8xx              MBX                                  -                                                                                                                                 -
 Orphan  powerpc     mpc8xx         -           -               mbx8xx              MBX860T                              -                                                                                                                                 -
 Orphan  powerpc     mpc8xx         -           -               genietv             GENIETV                              -                                                                                                                                 -
 Orphan  powerpc     mpc8xx         -           -               mbx8xx              MBX                                  -                                                                                                                                 -
 Orphan  powerpc     mpc8xx         -           -               mbx8xx              MBX860T                              -                                                                                                                                 -

-Orphan  powerpc     mpc8xx         -           -               nx823               NX823                                -                                                                                                                                 -

diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 0a6c6b56178573fa48f52b8e25950c00d723231c..7f519916fd3a9a42299bcc5ce2f876e8044df13a 100644 (file)
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -11,8 +11,9 @@ easily if here is something they might want to dig for...
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================

-idmr             m68k        mcf52x2        -           2014-01-28
-M5271EVB         m68k        mcf52x2        -           2014-01-28
+nx823            powerpc     mpc8xx         -           2014-04-04
+idmr             m68k        mcf52x2        ba650e9b    2014-01-28
+M5271EVB         m68k        mcf52x2        ba650e9b    2014-01-28

 dvl_host         arm         ixp            e317de6b    2014-01-28  Michael Schwingen <michael@schwingen.org>
 actux4           arm         ixp            6ff7aafa    2014-01-28  Michael Schwingen <michael@schwingen.org>
 actux3           arm         ixp            38da33f3    2014-01-28  Michael Schwingen <michael@schwingen.org>
 dvl_host         arm         ixp            e317de6b    2014-01-28  Michael Schwingen <michael@schwingen.org>
 actux4           arm         ixp            6ff7aafa    2014-01-28  Michael Schwingen <michael@schwingen.org>
 actux3           arm         ixp            38da33f3    2014-01-28  Michael Schwingen <michael@schwingen.org>

diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index e78196797bdd133db62cf978e27bab5ae36cf1d6..c18e4ca27a3750da9a2c1e73d73c1269940bc09b 100644 (file)
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -108,9 +108,6 @@ typedef struct bd_info {
        unsigned int    bi_opbfreq;             /* OPB clock in Hz */
        int             bi_iic_fast[2];         /* Use fast i2c mode */
 #endif
        unsigned int    bi_opbfreq;             /* OPB clock in Hz */
        int             bi_iic_fast[2];         /* Use fast i2c mode */
 #endif

-#if defined(CONFIG_NX823)
-       unsigned char   bi_sernum[8];
-#endif

 #if defined(CONFIG_4xx)
 #if defined(CONFIG_440GX) || \
                defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #if defined(CONFIG_4xx)
 #if defined(CONFIG_440GX) || \
                defined(CONFIG_460EX) || defined(CONFIG_460GT)

diff --git a/include/commproc.h b/include/commproc.h
index c10a79c83930bde4c8e4d451b4a879fd6c0c41f9..12b94210607c612b8b95191c2211ae2d90cd1f4c 100644 (file)
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -888,33 +888,6 @@ typedef struct scc_enet {
 #define SICR_ENET_CLKRT        ((uint)0x00003E00)
 #endif /* CONFIG_LWMON */
 
 #define SICR_ENET_CLKRT        ((uint)0x00003E00)
 #endif /* CONFIG_LWMON */
 

-/***  NX823  ***********************************************/
-
-#if defined(CONFIG_NX823)
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- */
-#define PROFF_ENET     PROFF_SCC2
-#define CPM_CR_ENET    CPM_CR_CH_SCC2
-#define SCC_ENET       1
-#define PA_ENET_RXD    ((ushort)0x0004)  /* PA 13 */
-#define PA_ENET_TXD    ((ushort)0x0008)  /* PA 12 */
-#define PA_ENET_RCLK   ((ushort)0x0200)  /* PA  6 */
-#define PA_ENET_TCLK   ((ushort)0x0800)  /* PA  4 */
-
-#define PB_ENET_TENA   ((uint)0x00002000)   /* PB 18 */
-
-#define PC_ENET_CLSN   ((ushort)0x0040)  /* PC  9 */
-#define PC_ENET_RENA   ((ushort)0x0080)  /* PC  8 */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
- * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT        ((uint)0x00002f00)
-
-#endif   /* CONFIG_NX823 */
-

 /***  MBX  ************************************************************/
 
 #ifdef CONFIG_MBX
 /***  MBX  ************************************************************/
 
 #ifdef CONFIG_MBX

diff --git a/include/configs/NX823.h b/include/configs/NX823.h
deleted file mode 100644 (file)
index 6d468df..0000000
--- a/include/configs/NX823.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823          1       /* This is a MPC823 CPU     */
-#define CONFIG_NX823           1       /* ...on a NEXUS 823  module    */
-
-#define        CONFIG_SYS_TEXT_BASE    0x40000000
-
-/*#define  CONFIG_VIDEO                1 */
-
-#define CONFIG_8xx_GCLK_FREQ   MPC8XX_SPEED
-#define CONFIG_8xx_CONS_SMC1   1       /* Console is on SMC1       */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 57600  /* console baudrate = 115kbps   */
-#define CONFIG_BOOTDELAY       2       /* autoboot after 2 seconds */
-#define CONFIG_BOOTARGS                "ramdisk_size=8000 "\
-                               "root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\
-                               "nfsaddrs=10.77.77.20:10.77.77.250"
-#define CONFIG_BOOTCOMMAND     "bootm 400e0000"
-
-#define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
-#undef CONFIG_WATCHDOG                 /* watchdog disabled, for now       */
-#define CONFIG_SOURCE
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_SOURCE
-
-
-/* call various generic functions */
-#define CONFIG_MISC_INIT_R
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP                    /* undef to save memory     */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE              1024    /* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE              256     /* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)     /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS             16      /* max number of command args   */
-#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START       0x0400000       /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
-
-#define CONFIG_SYS_LOAD_ADDR           0x100000        /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR                0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE       0x2F00  /* Size of used area in DPRAM   */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE          0x00000000
-#define CONFIG_SYS_FLASH_BASE          0x40000000
-#define CONFIG_SYS_MONITOR_LEN         (128 << 10)     /* Reserve 128 kB for Monitor   */
-#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max number of memory banks       */
-#define CONFIG_SYS_MAX_FLASH_SECT      128     /* max number of sectors on one chip    */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)  */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define xEMBED
-#ifdef EMBED
-#define CONFIG_ENV_SIZE                0x200   /* FIXME How big when embedded?? */
-#define CONFIG_ENV_ADDR                CONFIG_SYS_MONITOR_BASE
-#else
-#define CONFIG_ENV_ADDR                0x40020000      /* absolute address for now   */
-#define CONFIG_ENV_SIZE                0x20000 /* 8K ouch, this may later be */
-#endif
-
-#define CONFIG_SYS_FLASH_SN_BASE       0x4001fff0      /* programmer automagically puts    */
-#define CONFIG_SYS_FLASH_SN_SECTOR     0x40000000      /* a serial number here             */
-#define CONFIG_SYS_FLASH_SN_BYTES      8
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE      16      /* For all MPC8xx CPUs          */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT     4       /* log base 2 of the above value    */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                           11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-                        SYPCR_SWE  | SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                           12-30
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control                                12-16
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register         12-18
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control               12-23
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR       (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register         5-7
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- */
-#define MPC8XX_SPEED   66666666L
-#define MPC8XX_XIN     32768   /* 32.768 kHz crystal */
-#define MPC8XX_FACT            (MPC8XX_SPEED/MPC8XX_XIN)
-#define CONFIG_SYS_PLPRCR_MF  ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
-#define CONFIG_SYS_PLPRCR              (CONFIG_SYS_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register              5-3
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK      SCCR_EBDF11
-#define CONFIG_SYS_SCCR        (SCCR_TBS     | \
-                        SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-                        SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-                        SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER         0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM     0x40000000      /* FLASH bank #0    */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM         0x80000000      /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
-
-/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0       */
-#define CONFIG_SYS_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_ACS_DIV1 | OR_BI | \
-                                OR_SCY_8_CLK )
-
-#define CONFIG_SYS_OR0_REMAP   (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM  (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-/*
- * BR1/2 and OR1/2 (SDRAM)
- */
-#define SDRAM_BASE1_PRELIM     0x00000000      /* SDRAM bank #0    */
-#define SDRAM_BASE2_PRELIM     0x20000000      /* SDRAM bank #1    */
-#define SDRAM_MAX_SIZE         0x04000000      /* max 64 MB per bank   */
-
-/* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */
-#define CONFIG_SYS_OR_TIMING_SDRAM     (OR_G5LS | OR_CSNT_SAM)
-
-#define CONFIG_SYS_OR1_PRELIM  (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR1_PRELIM  ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_OR1_PRELIM
-#define CONFIG_SYS_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/* IO and memory mapped stuff */
-#define NX823_IO_OR_AM         0xFFFF0000      /* mask for IO addresses */
-#define NX823_IO_BASE          0xFF000000      /* start of IO  */
-#define GPOUT_OFFSET           (3<<16)
-#define QUART_OFFSET           (4<<16)
-#define VIDAC_OFFSET           (5<<16)
-#define CPLD_OFFSET            (6<<16)
-#define SED1386_OFFSET         (7<<16)
-
-/*
- * BR3 and OR3 (general purpose output latches)
- */
-#define GPOUT_BASE     (NX823_IO_BASE + GPOUT_OFFSET)
-#define GPOUT_TIMING   (OR_CSNT_SAM | OR_TRLX | OR_BI)
-#define CONFIG_SYS_OR3_PRELIM  (NX823_IO_OR_AM | GPOUT_TIMING)
-#define CONFIG_SYS_BR3_PRELIM  (GPOUT_BASE | BR_V)
-
-/*
- * BR4 and OR4 (QUART)
- */
-#define QUART_BASE     (NX823_IO_BASE + QUART_OFFSET)
-#define QUART_TIMING   (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX)
-#define CONFIG_SYS_OR4_PRELIM  (NX823_IO_OR_AM | QUART_TIMING | OR_BI)
-#define CONFIG_SYS_BR4_PRELIM  (QUART_BASE | BR_PS_8 | BR_V)
-
-/*
- * BR5 and OR5 (Video DAC)
- */
-#define VIDAC_BASE     (NX823_IO_BASE + VIDAC_OFFSET)
-#define VIDAC_TIMING   (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
-#define CONFIG_SYS_OR5_PRELIM  (NX823_IO_OR_AM | VIDAC_TIMING | OR_BI)
-#define CONFIG_SYS_BR5_PRELIM  (VIDAC_BASE | BR_PS_8 | BR_V)
-
-/*
- * BR6 and OR6 (CPLD)
- * FIXME timing not verified for CPLD
- */
-#define CPLD_BASE      (NX823_IO_BASE + CPLD_OFFSET)
-#define CPLD_TIMING    (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
-#define CONFIG_SYS_OR6_PRELIM  (NX823_IO_OR_AM | CPLD_TIMING | OR_BI)
-#define CONFIG_SYS_BR6_PRELIM  (CPLD_BASE | BR_PS_8 | BR_V )
-
-/*
- * BR7 and OR7 (SED1386)
- * FIXME timing not verified for SED controller
- */
-#define SED1386_BASE   0xF7000000
-#define CONFIG_SYS_OR7_PRELIM  (0xFF000000 | OR_BI | OR_SETA)
-#define CONFIG_SYS_BR7_PRELIM  (SED1386_BASE | BR_PS_16 | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA    97              /* start with divider for 100 MHz   */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit    */
-#define CONFIG_SYS_MPTPR_2BK_4K        MPTPR_PTP_DIV16 /* setting for 2 banks  */
-#define CONFIG_SYS_MPTPR_1BK_4K        MPTPR_PTP_DIV32 /* setting for 1 bank   */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit                */
-#define CONFIG_SYS_MPTPR_2BK_8K        MPTPR_PTP_DIV8  /* setting for 2 banks  */
-#define CONFIG_SYS_MPTPR_1BK_8K        MPTPR_PTP_DIV16 /* setting for 1 bank   */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
-                        MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
-                        MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
-                        MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
-                        MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-
-#define CONFIG_ENV_OVERWRITE   /* allow changes to ethaddr (for now)   */
-#define CONFIG_ETHADDR         00:10:20:30:40:50
-#define CONFIG_IPADDR          10.77.77.20
-#define CONFIG_SERVERIP                10.77.77.250
-
-#endif /* __CONFIG_H */