]> git.kernelconcepts.de Git - karo-tx-uboot.git/commitdiff
x86: crownbay: Add SPI flash support
authorBin Meng <bmeng.cn@gmail.com>
Wed, 17 Dec 2014 07:50:44 +0000 (15:50 +0800)
committerSimon Glass <sjg@chromium.org>
Fri, 19 Dec 2014 00:26:07 +0000 (17:26 -0700)
The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
arch/x86/cpu/queensbay/tnc.c
arch/x86/include/asm/arch-queensbay/tnc.h [new file with mode: 0644]
include/configs/crownbay.h

index 8b9815fa00574f10cac1d017a322529610b335c4..8637cdca2dd4679f99bb3c56cec784cf03e7bfd1 100644 (file)
@@ -6,18 +6,42 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/pci.h>
 #include <asm/post.h>
+#include <asm/arch/tnc.h>
 #include <asm/arch/fsp/fsp_support.h>
 #include <asm/processor.h>
 
+static void unprotect_spi_flash(void)
+{
+       u32 bc;
+
+       bc = pci_read_config32(PCH_LPC_DEV, 0xd8);
+       bc |= 0x1;      /* unprotect the flash */
+       pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
+}
+
 int arch_cpu_init(void)
 {
+       struct pci_controller *hose;
+       int ret;
+
        post_code(POST_CPU_INIT);
 #ifdef CONFIG_SYS_X86_TSC_TIMER
        timer_set_base(rdtsc());
 #endif
 
-       return x86_cpu_init_f();
+       ret = x86_cpu_init_f();
+       if (ret)
+               return ret;
+
+       ret = pci_early_init_hose(&hose);
+       if (ret)
+               return ret;
+
+       unprotect_spi_flash();
+
+       return 0;
 }
 
 int print_cpuinfo(void)
diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h
new file mode 100644 (file)
index 0000000..67c5e05
--- /dev/null
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_TNC_H_
+#define _X86_ARCH_TNC_H_
+
+#include <pci.h>
+
+/* PCI Configuration Space (D31:F0): LPC */
+#define PCH_LPC_DEV    PCI_BDF(0, 0x1f, 0)
+
+#endif /* _X86_ARCH_TNC_H_ */
index 2314e62a876d552643cd1a75c0e64bda7e3076d6..a051b1149b5e9aee43335d3322f66586368a11d2 100644 (file)
@@ -45,6 +45,8 @@
 #define CONFIG_SCSI_DEV_LIST            \
        {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
 
+#define CONFIG_SPI_FLASH_SST
+
 /* Video is not supported */
 #undef CONFIG_VIDEO
 #undef CONFIG_CFB_CONSOLE