ARM: keystone2: configs: Move SP to end of u-boot section
authorLokesh Vutla <lokeshvutla@ti.com>
Mon, 17 Aug 2015 14:24:48 +0000 (19:54 +0530)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 09:29:49 +0000 (11:29 +0200)
Currently u-boot stack is defined at the beginning of MSMC RAM.
This is a problem for uart boot mode as ROM downloads directly to
starting of MSMC RAM.
Fixing it by moving stack to the end of u-boot section and shifting
SYS_TEXT_BASE to the start of MSMC RAM.
Updated division of MSMC RAM is shown below:
-----------------------------------------
| | | |
| U-Boot text |U-Boot | SPL text |
| download | Stack | Download + |
| | | SPL_BSS + |
| | | SPL_STACK |
-----------------------------------------
[1] [2] [3] [4]

[1] SYS_TEXT_BASE (Start of MSMC RAM)
[2] SPL_TEXT_BASE - GBL_DATA_SIZE
[3] SPL_TEXT_BASE
[4] END of SPL

[1] + [2] is at least 1M on all platforms, so no chance of overlap.

Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
include/configs/ti_armv7_keystone2.h

index 2fdc103..d8163b6 100644 (file)
@@ -19,7 +19,7 @@
 /* SoC Configuration */
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_SYS_ARCH_TIMER
-#define CONFIG_SYS_TEXT_BASE           0x0c001000
+#define CONFIG_SYS_TEXT_BASE           0x0c000000
 #define CONFIG_SPL_TARGET              "u-boot-spi.gph"
 #define CONFIG_SYS_DCACHE_OFF
 
@@ -28,7 +28,7 @@
 #define CONFIG_SYS_LPAE_SDRAM_BASE     0x800000000
 #define CONFIG_MAX_RAM_BANK_SIZE       (2 << 30)       /* 2GB */
 #define CONFIG_STACKSIZE               (512 << 10)     /* 512 KiB */
-#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_TEXT_BASE - \
+#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SPL_TEXT_BASE - \
                                        GENERATED_GBL_DATA_SIZE)
 
 /* SPL SPI Loader Configuration */