Stefano Babic <sbabic@denx.de>
ea20 davinci
+ mx35pdk i.MX35
+ mx51evk i.MX51
polaris xscale
trizepsiv xscale
- mx51evk i.MX51
vision2 i.MX51
+Jason Liu <r64343@freescale.com>
+
+ mx53evk i.MX53
+
Enric Balletbo i Serra <eballetbo@iseebcn.com>
igep0020 ARM ARMV7 (OMAP3xx SoC)
Minkyu Kang <mk7.kang@samsung.com>
- s5p_goni ARM ARMV7 (S5PC110 SoC)
- SMDKC100 ARM ARMV7 (S5PC100 SoC)
+ SMDKC100 ARM ARMV7 (S5PC100 SoC)
+ s5p_goni ARM ARMV7 (S5PC110 SoC)
+ s5pc210_universal ARM ARMV7 (S5PC210 SoC)
Frederik Kriewitz <frederik@kriewitz.eu>
at91sam9263ek ARM926EJS (AT91SAM9263 SoC)
at91sam9rlek ARM926EJS (AT91SAM9RL SoC)
+Mike Rapoport <mike@compulab.co.il>
+
+ cm_t35 ARM ARMV7 (OMAP3xx SoC)
+
Tom Rix <Tom.Rix@windriver.com>
omap3_zoom2 ARM ARMV7 (OMAP3xx SoC)
palmtc xscale
vpac270 xscale
zipitz2 xscale
+ efikamx i.MX51
Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
# needed for relocation
ifndef CONFIG_NAND_SPL
-PLATFORM_LDFLAGS += -pie
+LDFLAGS_u-boot += -pie
endif
#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
-static ulong timestamp;
-static ulong lastinc;
+DECLARE_GLOBAL_DATA_PTR;
/* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */
#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
void reset_timer_masked (void)
{
/* reset time */
- lastinc = GPTCNT; /* capture current incrementer value time */
- timestamp = 0; /* start "advancing" time stamp from 0 */
+ gd->lastinc = GPTCNT; /* capture current incrementer value time */
+ gd->tbl = 0; /* start "advancing" time stamp from 0 */
}
void reset_timer(void)
{
ulong now = GPTCNT; /* current tick value */
- if (now >= lastinc) /* normal mode (non roll) */
+ if (now >= gd->lastinc) /* normal mode (non roll) */
/* move stamp forward with absolut diff ticks */
- timestamp += (now - lastinc);
+ gd->tbl += (now - gd->lastinc);
else /* we have rollover of incrementer */
- timestamp += (0xFFFFFFFF - lastinc) + now;
- lastinc = now;
- return timestamp;
+ gd->tbl += (0xFFFFFFFF - gd->lastinc) + now;
+ gd->lastinc = now;
+ return gd->tbl;
}
ulong get_timer_masked (void)
void set_timer (ulong t)
{
- timestamp = time_to_tick(t);
+ gd->tbl = time_to_tick(t);
}
/* delay x useconds AND preserve advance timestamp value */
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS += generic.o
+COBJS += timer.o
+COBJS += iomux.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h
+
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+
+$(TOPDIR)/include/asm/arch/asm-offsets.h: $(TOPDIR)/include/autoconf.mk.dep \
+ ./asm-offsets.s
+ @echo Generating $@
+ $(TOPDIR)/tools/scripts/make-asm-offsets ./asm-offsets.s $@
+
+asm-offsets.s: $(TOPDIR)/include/autoconf.mk.dep \
+ ./asm-offsets.c
+ $(CC) -DDO_DEPS_ONLY \
+ $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
+ -o $@ ./asm-offsets.c -c -S
--- /dev/null
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+
+ /* Round up to make sure size gives nice stack alignment */
+ DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
+ DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
+ DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
+ DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
+ DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
+ DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
+ DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
+ DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
+ DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
+ DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
+ DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
+ DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
+ DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
+ DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+
+#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
+#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
+#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF)
+#define CLK_CODE_PATH(c) ((c) & 0xFF)
+
+#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
+
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+static int g_clk_mux_auto[8] = {
+ CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
+ CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
+};
+
+static int g_clk_mux_consumer[16] = {
+ CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
+ -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
+ CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
+ -1, -1, CLK_CODE(4, 2, 0), -1,
+};
+
+static int hsp_div_table[3][16] = {
+ {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
+ {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
+ {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
+};
+
+u32 get_cpu_rev(void)
+{
+ int reg;
+ struct iim_regs *iim =
+ (struct iim_regs *)IIM_BASE_ADDR;
+ reg = readl(&iim->iim_srev);
+ if (!reg) {
+ reg = readw(ROMPATCH_REV);
+ reg <<= 4;
+ } else {
+ reg += CHIP_REV_1_0;
+ }
+
+ return 0x35000 + (reg & 0xFF);
+}
+
+static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
+{
+ int *pclk_mux;
+ if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
+ pclk_mux = g_clk_mux_consumer +
+ ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
+ MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
+ } else {
+ pclk_mux = g_clk_mux_auto +
+ ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
+ MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
+ }
+
+ if ((*pclk_mux) == -1)
+ return -1;
+
+ if (fi && fd) {
+ if (!CLK_CODE_PATH(*pclk_mux)) {
+ *fi = *fd = 1;
+ return CLK_CODE_ARM(*pclk_mux);
+ }
+ if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
+ *fi = 3;
+ *fd = 4;
+ } else {
+ *fi = 2;
+ *fd = 3;
+ }
+ }
+ return CLK_CODE_ARM(*pclk_mux);
+}
+
+static int get_ahb_div(u32 pdr0)
+{
+ int *pclk_mux;
+
+ pclk_mux = g_clk_mux_consumer +
+ ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
+ MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
+
+ if ((*pclk_mux) == -1)
+ return -1;
+
+ return CLK_CODE_AHB(*pclk_mux);
+}
+
+static u32 decode_pll(u32 reg, u32 infreq)
+{
+ u32 mfi = (reg >> 10) & 0xf;
+ u32 mfn = reg & 0x3f;
+ u32 mfd = (reg >> 16) & 0x3f;
+ u32 pd = (reg >> 26) & 0xf;
+
+ mfi = mfi <= 5 ? 5 : mfi;
+ mfd += 1;
+ pd += 1;
+
+ return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
+}
+
+static u32 get_mcu_main_clk(void)
+{
+ u32 arm_div = 0, fi = 0, fd = 0;
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+ arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
+ fi *=
+ decode_pll(readl(&ccm->mpctl),
+ CONFIG_MX35_HCLK_FREQ);
+ return fi / (arm_div * fd);
+}
+
+static u32 get_ipg_clk(void)
+{
+ u32 freq = get_mcu_main_clk();
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+ u32 pdr0 = readl(&ccm->pdr0);
+
+ return freq / (get_ahb_div(pdr0) * 2);
+}
+
+static u32 get_ipg_per_clk(void)
+{
+ u32 freq = get_mcu_main_clk();
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+ u32 pdr0 = readl(&ccm->pdr0);
+ u32 pdr4 = readl(&ccm->pdr4);
+ u32 div;
+ if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
+ div = (CCM_GET_DIVIDER(pdr4,
+ MXC_CCM_PDR4_PER0_PRDF_MASK,
+ MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) *
+ (CCM_GET_DIVIDER(pdr4,
+ MXC_CCM_PDR4_PER0_PODF_MASK,
+ MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
+ } else {
+ div = CCM_GET_DIVIDER(pdr0,
+ MXC_CCM_PDR0_PER_PODF_MASK,
+ MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
+ freq /= get_ahb_div(pdr0);
+ }
+ return freq / div;
+}
+
+u32 imx_get_uartclk(void)
+{
+ u32 freq;
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+ u32 pdr4 = readl(&ccm->pdr4);
+
+ if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) {
+ freq = get_mcu_main_clk();
+ } else {
+ freq = decode_pll(readl(&ccm->ppctl),
+ CONFIG_MX35_HCLK_FREQ);
+ }
+ freq /= ((CCM_GET_DIVIDER(pdr4,
+ MXC_CCM_PDR4_UART_PRDF_MASK,
+ MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) *
+ (CCM_GET_DIVIDER(pdr4,
+ MXC_CCM_PDR4_UART_PODF_MASK,
+ MXC_CCM_PDR4_UART_PODF_OFFSET) + 1));
+ return freq;
+}
+
+unsigned int mxc_get_main_clock(enum mxc_main_clocks clk)
+{
+ u32 nfc_pdf, hsp_podf;
+ u32 pll, ret_val = 0, usb_prdf, usb_podf;
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ u32 reg = readl(&ccm->pdr0);
+ u32 reg4 = readl(&ccm->pdr4);
+
+ reg |= 0x1;
+
+ switch (clk) {
+ case CPU_CLK:
+ ret_val = get_mcu_main_clk();
+ break;
+ case AHB_CLK:
+ ret_val = get_mcu_main_clk();
+ break;
+ case HSP_CLK:
+ if (reg & CLKMODE_CONSUMER) {
+ hsp_podf = (reg >> 20) & 0x3;
+ pll = get_mcu_main_clk();
+ hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
+ if (hsp_podf > 0) {
+ ret_val = pll / hsp_podf;
+ } else {
+ puts("mismatch HSP with ARM clock setting\n");
+ ret_val = 0;
+ }
+ } else {
+ ret_val = get_mcu_main_clk();
+ }
+ break;
+ case IPG_CLK:
+ ret_val = get_ipg_clk();;
+ break;
+ case IPG_PER_CLK:
+ ret_val = get_ipg_per_clk();
+ break;
+ case NFC_CLK:
+ nfc_pdf = (reg4 >> 28) & 0xF;
+ pll = get_mcu_main_clk();
+ /* AHB/nfc_pdf */
+ ret_val = pll / (nfc_pdf + 1);
+ break;
+ case USB_CLK:
+ usb_prdf = (reg4 >> 25) & 0x7;
+ usb_podf = (reg4 >> 22) & 0x7;
+ if (reg4 & 0x200) {
+ pll = get_mcu_main_clk();
+ } else {
+ pll = decode_pll(readl(&ccm->ppctl),
+ CONFIG_MX35_HCLK_FREQ);
+ }
+
+ ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
+ break;
+ default:
+ printf("Unknown clock: %d\n", clk);
+ break;
+ }
+
+ return ret_val;
+}
+unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk)
+{
+ u32 ret_val = 0, pdf, pre_pdf, clk_sel;
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+ u32 mpdr2 = readl(&ccm->pdr2);
+ u32 mpdr3 = readl(&ccm->pdr3);
+ u32 mpdr4 = readl(&ccm->pdr4);
+
+ switch (clk) {
+ case UART1_BAUD:
+ case UART2_BAUD:
+ case UART3_BAUD:
+ clk_sel = mpdr3 & (1 << 14);
+ pre_pdf = (mpdr4 >> 13) & 0x7;
+ pdf = (mpdr4 >> 10) & 0x7;
+ ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+ decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+ ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case SSI1_BAUD:
+ pre_pdf = (mpdr2 >> 24) & 0x7;
+ pdf = mpdr2 & 0x3F;
+ clk_sel = mpdr2 & (1 << 6);
+ ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+ decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+ ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case SSI2_BAUD:
+ pre_pdf = (mpdr2 >> 27) & 0x7;
+ pdf = (mpdr2 >> 8) & 0x3F;
+ clk_sel = mpdr2 & (1 << 6);
+ ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+ decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+ ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case CSI_BAUD:
+ clk_sel = mpdr2 & (1 << 7);
+ pre_pdf = (mpdr2 >> 16) & 0x7;
+ pdf = (mpdr2 >> 19) & 0x7;
+ ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+ decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+ ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case MSHC_CLK:
+ pre_pdf = readl(&ccm->pdr1);
+ clk_sel = (pre_pdf & 0x80);
+ pdf = (pre_pdf >> 22) & 0x3F;
+ pre_pdf = (pre_pdf >> 28) & 0x7;
+ ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+ decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+ ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case ESDHC1_CLK:
+ clk_sel = mpdr3 & 0x40;
+ pre_pdf = mpdr3 & 0x7;
+ pdf = (mpdr3>>3) & 0x7;
+ ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+ decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+ ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case ESDHC2_CLK:
+ clk_sel = mpdr3 & 0x40;
+ pre_pdf = (mpdr3 >> 8) & 0x7;
+ pdf = (mpdr3 >> 11) & 0x7;
+ ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+ decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+ ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case ESDHC3_CLK:
+ clk_sel = mpdr3 & 0x40;
+ pre_pdf = (mpdr3 >> 16) & 0x7;
+ pdf = (mpdr3 >> 19) & 0x7;
+ ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+ decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+ ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case SPDIF_CLK:
+ clk_sel = mpdr3 & 0x400000;
+ pre_pdf = (mpdr3 >> 29) & 0x7;
+ pdf = (mpdr3 >> 23) & 0x3F;
+ ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+ decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+ ((pre_pdf + 1) * (pdf + 1));
+ break;
+ default:
+ printf("%s(): This clock: %d not supported yet\n",
+ __func__, clk);
+ break;
+ }
+
+ return ret_val;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return get_mcu_main_clk();
+ case MXC_AHB_CLK:
+ break;
+ case MXC_IPG_CLK:
+ return get_ipg_clk();
+ case MXC_IPG_PERCLK:
+ return get_ipg_per_clk();
+ case MXC_UART_CLK:
+ return imx_get_uartclk();
+ case MXC_ESDHC_CLK:
+ return mxc_get_peri_clock(ESDHC1_CLK);
+ case MXC_USB_CLK:
+ return mxc_get_main_clock(USB_CLK);
+ case MXC_FEC_CLK:
+ return get_ipg_clk();
+ case MXC_CSPI_CLK:
+ return get_ipg_clk();
+ }
+ return -1;
+}
+
+#ifdef CONFIG_FEC_MXC
+/*
+ * The MX35 has no fuse for MAC, return a NULL MAC
+ */
+void imx_get_mac_from_fuse(unsigned char *mac)
+{
+ memset(mac, 0, 6);
+}
+
+u32 imx_get_fecclk(void)
+{
+ return mxc_get_clock(MXC_IPG_CLK);
+}
+#endif
+
+int do_mx35_showclocks(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ u32 cpufreq = get_mcu_main_clk();
+ printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
+ printf("ipg clock : %dHz\n", get_ipg_clk());
+ printf("ipg per clock : %dHz\n", get_ipg_per_clk());
+ printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
+ "display clocks\n",
+ ""
+);
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ printf("CPU: Freescale i.MX35 at %d MHz\n",
+ get_mcu_main_clk() / 1000000);
+ /* mxc_dump_clocks(); */
+ return 0;
+}
+#endif
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+
+int cpu_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+ rc = fecmxc_initialize(bis);
+#endif
+
+ return rc;
+}
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
+ writew(4, &wdog->wcr);
+}
--- /dev/null
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+
+/*
+ * IOMUX register (base) addresses
+ */
+enum iomux_reg_addr {
+ IOMUXGPR = IOMUXC_BASE_ADDR, /* General purpose */
+ IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4, /* MUX control */
+ IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324, /* last MUX control */
+ IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328, /* Pad control */
+ IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794, /* last Pad control */
+ IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC, /* input select */
+ IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4, /* last input select */
+};
+
+#define MUX_PIN_NUM_MAX \
+ (((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1)
+#define MUX_INPUT_NUM_MUX \
+ (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1)
+
+#define PIN_TO_IOMUX_INDEX(pin) ((PIN_TO_IOMUX_PAD(pin) - 0x328) >> 2)
+
+/*
+ * Request ownership for an IO pin. This function has to be the first one
+ * being called before that pin is used.
+ */
+void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
+{
+ u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
+
+ if (mux_reg != NON_MUX_I) {
+ mux_reg += IOMUXGPR;
+ writel(cfg, mux_reg);
+ }
+}
+
+/*
+ * Release ownership for an IO pin
+ */
+void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
+{
+}
+
+/*
+ * This function configures the pad value for a IOMUX pin.
+ *
+ * @param pin a pin number as defined in iomux_pin_name_t
+ * @param config the ORed value of elements defined in iomux_pad_config_t
+ */
+void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
+{
+ u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin);
+
+ writel(config, pad_reg);
+}
+
+/*
+ * This function enables/disables the general purpose function for a particular
+ * signal.
+ *
+ * @param gp one signal as defined in iomux_gp_func_t
+ * @param en enable/disable
+ */
+void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en)
+{
+ u32 l;
+
+ l = readl(IOMUXGPR);
+ if (en)
+ l |= gp;
+ else
+ l &= ~gp;
+
+ writel(l, IOMUXGPR);
+}
+
+/*
+ * This function configures input path.
+ *
+ * @param input index of input select register as defined in
+ * iomux_input_select_t
+ * @param config the binary value of elements defined in
+ * iomux_input_config_t
+ */
+void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
+{
+ u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
+
+ writel(config, reg);
+}
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR (1<<15) /* Software reset */
+#define GPTCR_FRR (1<<9) /* Freerun / restart */
+#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */
+#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */
+#define GPTCR_TEN (1) /* Timer enable */
+#define GPTPR_VAL (66)
+
+int timer_init(void)
+{
+ int i;
+ struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
+
+ /* setup GP Timer 1 */
+ writel(GPTCR_SWR, &gpt->ctrl);
+ for (i = 0; i < 100; i++)
+ writel(0, &gpt->ctrl); /* We have no udelay by now */
+
+ writel(GPTPR_VAL, &gpt->pre);
+ /* Freerun Mode, PERCLK1 input */
+ writel(readl(&gpt->ctrl) |
+ GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
+ &gpt->ctrl);
+
+ return 0;
+}
+
+void reset_timer_masked(void)
+{
+ struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
+
+ writel(0, &gpt->ctrl);
+ /* Freerun Mode, PERCLK1 input */
+ writel(GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
+ &gpt->ctrl);
+}
+
+inline ulong get_timer_masked(void)
+{
+
+ struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
+ ulong val = readl(&gpt->counter);
+
+ return val;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ ulong tmp;
+
+ tmp = get_timer_masked();
+
+ if (tmp <= (base * 1000)) {
+ /* Overflow */
+ tmp += (0xffffffff - base);
+ }
+
+ return (tmp / 1000) - base;
+}
+
+void set_timer(ulong t)
+{
+}
+
+/*
+ * delay x useconds AND preserve advance timstamp value
+ * GPTCNT is now supposed to tick 1 by 1 us.
+ */
+void __udelay(unsigned long usec)
+{
+ ulong tmp;
+
+ tmp = get_timer_masked(); /* get current timestamp */
+
+ /* if setting this forward will roll time stamp */
+ if ((usec + tmp + 1) < tmp) {
+ /* reset "advancing" timestamp to 0, set lastinc value */
+ reset_timer_masked();
+ } else {
+ /* else, set advancing stamp wake up time */
+ tmp += usec;
+ }
+
+ while (get_timer_masked() < tmp) /* loop till event */
+ /*NOP*/;
+}
/* macro to read the 32 bit timer */
#define READ_TIMER (*((volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR)))
-static ulong timestamp;
-static ulong lastinc;
+DECLARE_GLOBAL_DATA_PTR;
int timer_init (void)
{
void set_timer (ulong t)
{
- timestamp = t;
+ gd->tbl = t;
}
/* delay x useconds AND preserve advance timestamp value */
void reset_timer_masked (void)
{
/* reset time */
- lastinc = READ_TIMER; /* capture current incrementer value time */
- timestamp = 0; /* start "advancing" time stamp from 0 */
+ gd->lastinc = READ_TIMER; /* capture current incrementer value time */
+ gd->tbl = 0; /* start "advancing" time stamp from 0 */
}
ulong get_timer_masked (void)
{
ulong now = READ_TIMER; /* current tick value */
- if (now >= lastinc) /* normal mode (non roll) */
- timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */
+ if (now >= gd->lastinc) /* normal mode (non roll) */
+ gd->tbl += (now - gd->lastinc); /* move stamp fordward with absoulte diff ticks */
else /* we have rollover of incrementer */
- timestamp += (0xFFFFFFFF - lastinc) + now;
- lastinc = now;
- return timestamp;
+ gd->tbl += (0xFFFFFFFF - gd->lastinc) + now;
+ gd->lastinc = now;
+ return gd->tbl;
}
/* waits specified delay value and resets timestamp */
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
orr r0, r0, #0xd3
msr cpsr, r0
- bl coloured_LED_init
- bl red_LED_on
-
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
/*
* relocate exception table
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
COBJS-$(CONFIG_SOC_DM365) += dm365.o
COBJS-$(CONFIG_SOC_DM644X) += dm644x.o
COBJS-$(CONFIG_SOC_DM646X) += dm646x.o
-COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o
+COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o
SOBJS = reset.o
#define DDR_PLLDIV PLLC_PLLDIV2
#endif
-#ifdef CONFIG_SOC_DM6447
-#define ARM_PLLDIV PLLC_PLLDIV2
+#ifdef CONFIG_SOC_DM646X
#define DSP_PLLDIV PLLC_PLLDIV1
+#define ARM_PLLDIV PLLC_PLLDIV2
#define DDR_PLLDIV PLLC_PLLDIV1
#endif
static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
{
volatile void *pllbase = (volatile void *) pll_addr;
+#ifdef CONFIG_SOC_DM646X
+ unsigned base = CFG_REFCLK_FREQ / 1000;
+#else
unsigned base = CONFIG_SYS_HZ_CLOCK / 1000;
+#endif
/* the PLL might be bypassed */
if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
return 0;
}
+#ifdef DAVINCI_DM6467EVM
+unsigned int davinci_arm_clk_get()
+{
+ return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
+}
+#endif
#endif
/*
--- /dev/null
+/*
+ * LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <miiphy.h>
+#include <asm/arch/emac_defs.h>
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+#ifdef CONFIG_CMD_NET
+
+/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */
+
+#define MII_PHY_CONFIG_REG 22
+
+/* PHY Config bits */
+#define PHY_SYS_CLK_EN (1 << 4)
+
+int et1011c_get_link_speed(int phy_addr)
+{
+ u_int16_t data;
+
+ if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
+ davinci_eth_phy_read(EMAC_MDIO_PHY_NUM,
+ MII_PHY_CONFIG_REG, &data);
+ /* Enable 125MHz clock sourced from PHY */
+ davinci_eth_phy_write(EMAC_MDIO_PHY_NUM,
+ MII_PHY_CONFIG_REG,
+ data | PHY_SYS_CLK_EN);
+ return (1);
+ }
+ return (0);
+}
+
+#endif /* CONFIG_CMD_NET */
+
+#endif /* CONFIG_DRIVER_ETHER */
#define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \
(CONFIG_SYS_TCLK / 1000))
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
void reset_timer_masked(void)
{
#define TIMER_LOAD_VAL 0xffffffff
#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256)
-static unsigned long long timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
static inline unsigned long long tick_to_time(unsigned long long tick)
{
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-static ulong timestamp;
-static ulong lastinc;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastinc gd->lastinc
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
#define GPTCR_CLKSOURCE_32 (4 << 1) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
-static ulong timestamp;
-static ulong lastinc;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastinc gd->lastinc
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
/* macro to read the 32 bit timer */
#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8))
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
int timer_init (void)
{
/ (CONFIG_SYS_TCLK / 1000);
}
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
void reset_timer_masked(void)
{
static struct misc_regs *const misc_regs_p =
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
int timer_init(void)
{
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy loop */
- ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
/* macro to read the 32 bit timer */
#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
#define TIMER_ENABLE (1 << 7)
#define TIMER_MODE_MSK (1 << 6)
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
- IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR,
+ IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START,
};
#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
{
u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
+#if defined(CONFIG_MX51)
if (is_soc_rev(CHIP_REV_2_0) < 0) {
/*
* Fixup register address:
- * i.MX51 TO1 has offset with the register
- * which is define as TO2.
+ * i.MX51 TO1 has offset with the register
+ * which is define as TO2.
*/
if ((pin == MX51_PIN_NANDF_RB5) ||
(pin == MX51_PIN_NANDF_RB6) ||
else if (mux_reg >= 0x130)
mux_reg += 0xC;
}
+#endif
mux_reg += IOMUXSW_MUX_CTL;
return mux_reg;
}
{
u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
+#if defined(CONFIG_MX51)
if (is_soc_rev(CHIP_REV_2_0) < 0) {
/*
* Fixup register address:
- * i.MX51 TO1 has offset with the register
- * which is define as TO2.
+ * i.MX51 TO1 has offset with the register
+ * which is define as TO2.
*/
if ((pin == MX51_PIN_NANDF_RB5) ||
(pin == MX51_PIN_NANDF_RB6) ||
else
pad_reg += 8;
}
+#endif
pad_reg += IOMUXSW_PAD_CTL;
return pad_reg;
}
/* Get the last iomux register address */
static inline u32 get_mux_end(void)
{
+#if defined(CONFIG_MX51)
if (is_soc_rev(CHIP_REV_2_0) < 0)
return IOMUXC_BASE_ADDR + (0x3F8 - 4);
else
return IOMUXC_BASE_ADDR + (0x3F0 - 4);
+#endif
+ return IOMUXSW_MUX_END;
}
/*
u32 pad_reg = get_pad_reg(pin);
return readl(pad_reg);
}
+
+/*
+ * This function configures daisy-chain
+ *
+ * @param input index of input select register
+ * @param config the binary value of elements
+ */
+void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
+{
+ u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
+
+ writel(config, reg);
+}
/* M4IF setup */
.macro init_m4if
+#ifdef CONFIG_MX51
/* VPU and IPU given higher priority (0x4)
* IPU accesses with ID=0x1 given highest priority (=0xA)
*/
ldr r1, =0x001901A3
str r1, [r0, #0x48]
+#endif
.endm /* init_m4if */
.macro setup_pll pll, freq
- ldr r2, =\pll
+ ldr r0, =\pll
ldr r1, =0x00001232
- str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
mov r1, #0x2
- str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
- str r3, [r2, #PLL_DP_OP]
- str r3, [r2, #PLL_DP_HFS_OP]
+ ldr r1, W_DP_OP_\freq
+ str r1, [r0, #PLL_DP_OP]
+ str r1, [r0, #PLL_DP_HFS_OP]
- str r4, [r2, #PLL_DP_MFD]
- str r4, [r2, #PLL_DP_HFS_MFD]
+ ldr r1, W_DP_MFD_\freq
+ str r1, [r0, #PLL_DP_MFD]
+ str r1, [r0, #PLL_DP_HFS_MFD]
- str r5, [r2, #PLL_DP_MFN]
- str r5, [r2, #PLL_DP_HFS_MFN]
+ ldr r1, W_DP_MFN_\freq
+ str r1, [r0, #PLL_DP_MFN]
+ str r1, [r0, #PLL_DP_HFS_MFN]
ldr r1, =0x00001232
- str r1, [r2, #PLL_DP_CTL]
-1: ldr r1, [r2, #PLL_DP_CTL]
+ str r1, [r0, #PLL_DP_CTL]
+1: ldr r1, [r0, #PLL_DP_CTL]
ands r1, r1, #0x1
beq 1b
.endm
.macro init_clock
ldr r0, =CCM_BASE_ADDR
+#if defined(CONFIG_MX51)
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
+#endif
/* Switch ARM to step clock */
mov r1, #0x4
str r1, [r0, #CLKCTL_CCSR]
- mov r3, #DP_OP_800
- mov r4, #DP_MFD_800
- mov r5, #DP_MFN_800
- setup_pll PLL1_BASE_ADDR
- mov r3, #DP_OP_665
- mov r4, #DP_MFD_665
- mov r5, #DP_MFN_665
- setup_pll PLL3_BASE_ADDR
+ setup_pll PLL1_BASE_ADDR, 800
+
+#if defined(CONFIG_MX51)
+ setup_pll PLL3_BASE_ADDR, 665
/* Switch peripheral to PLL 3 */
ldr r0, =CCM_BASE_ADDR
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x13239145
str r1, [r0, #CLKCTL_CBCDR]
- mov r3, #DP_OP_665
- mov r4, #DP_MFD_665
- mov r5, #DP_MFN_665
- setup_pll PLL2_BASE_ADDR
+ setup_pll PLL2_BASE_ADDR, 665
/* Switch peripheral to PLL2 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x000020C0
orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
-
- mov r3, #DP_OP_216
- mov r4, #DP_MFD_216
- mov r5, #DP_MFN_216
- setup_pll PLL3_BASE_ADDR
-
+#endif
+ setup_pll PLL3_BASE_ADDR, 216
/* Set the platform clock dividers */
ldr r0, =ARM_BASE_ADDR
ldr r0, =CCM_BASE_ADDR
+#if defined(CONFIG_MX51)
/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
ldr r1, =0x0
ldr r3, [r1, #ROM_SI_REV]
cmp r3, #0x10
movls r1, #0x1
movhi r1, #0
- str r1, [r0, #CLKCTL_CACRR]
+#else
+ mov r1, #0
+#endif
+ str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1 */
mov r1, #0
str r1, [r0, #CLKCTL_CCSR]
+#if defined(CONFIG_MX51)
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
ldr r1, =0x000020C2
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
ldr r1, =CONFIG_SYS_CLKTL_CBCDR
str r1, [r0, #CLKCTL_CBCDR]
+#endif
/* Restore the default values in the Gate registers */
ldr r1, =0xFFFFFFFF
str r1, [r0, #CLKCTL_CCGR4]
str r1, [r0, #CLKCTL_CCGR5]
str r1, [r0, #CLKCTL_CCGR6]
+#if defined(CONFIG_MX53)
+ str r1, [r0, #CLKCTL_CCGR7]
+#endif
+#if defined(CONFIG_MX51)
/* Use PLL 2 for UART's, get 66.5MHz from it */
ldr r1, =0xA5A2A020
str r1, [r0, #CLKCTL_CSCMR1]
ldr r1, =0x00C30321
str r1, [r0, #CLKCTL_CSCDR1]
-
+#elif defined(CONFIG_MX53)
+ ldr r1, [r0, #CLKCTL_CSCDR1]
+ orr r1, r1, #0x3f
+ eor r1, r1, #0x3f
+ orr r1, r1, #0x21
+ str r1, [r0, #CLKCTL_CSCDR1]
+#endif
/* make sure divider effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
.globl lowlevel_init
lowlevel_init:
+#if defined(CONFIG_MX51)
ldr r0, =GPIO1_BASE_ADDR
ldr r1, [r0, #0x0]
orr r1, r1, #(1 << 23)
ldr r1, [r0, #0x4]
orr r1, r1, #(1 << 23)
str r1, [r0, #0x4]
+#endif
init_l2cc
mov pc,lr
/* Board level setting value */
-DDR_PERCHARGE_CMD: .word 0x04008008
-DDR_REFRESH_CMD: .word 0x00008010
-DDR_LMR1_W: .word 0x00338018
-DDR_LMR_CMD: .word 0xB2220000
-DDR_TIMING_W: .word 0xB02567A9
-DDR_MISC_W: .word 0x000A0104
+W_DP_OP_800: .word DP_OP_800
+W_DP_MFD_800: .word DP_MFD_800
+W_DP_MFN_800: .word DP_MFN_800
+W_DP_OP_665: .word DP_OP_665
+W_DP_MFD_665: .word DP_MFD_665
+W_DP_MFN_665: .word DP_MFN_665
+W_DP_OP_216: .word DP_OP_216
+W_DP_MFD_216: .word DP_MFD_216
+W_DP_MFN_216: .word DP_MFN_216
#include <fsl_esdhc.h>
#endif
-#if defined(CONFIG_MX51)
-#define CPU_TYPE 0x51000
-#else
+#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
#error "CPU_TYPE not defined"
#endif
u32 get_cpu_rev(void)
{
- int system_rev = CPU_TYPE;
+#ifdef CONFIG_MX51
+ int system_rev = 0x51000;
+#else
+ int system_rev = 0x53000;
+#endif
int reg = __raw_readl(ROM_SI_REV);
+#if defined(CONFIG_MX51)
switch (reg) {
case 0x02:
system_rev |= CHIP_REV_1_1;
case 0x20:
system_rev |= CHIP_REV_3_0;
break;
- return system_rev;
default:
system_rev |= CHIP_REV_1_0;
break;
}
+#else
+ switch (reg) {
+ case 0x20:
+ system_rev |= CHIP_REV_2_0;
+ break;
+ default:
+ system_rev |= CHIP_REV_1_0;
+ break;
+ }
+#endif
return system_rev;
}
#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
#define GPTCR_TEN (1) /* Timer enable */
-static ulong timestamp;
-static ulong lastinc;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp (gd->tbl)
+#define lastinc (gd->lastinc)
int timer_init(void)
{
{
s5p_set_cpu_id();
- s5p_clock_init();
-
return 0;
}
#endif
#define CONFIG_SYS_CLK_FREQ_C110 24000000
#endif
-unsigned long (*get_uart_clk)(int dev_index);
-unsigned long (*get_pwm_clk)(void);
-unsigned long (*get_arm_clk)(void);
-unsigned long (*get_pll_clk)(int);
-
/* s5pc110: return pll clock frequency */
static unsigned long s5pc100_get_pll_clk(int pllreg)
{
return s5pc100_get_pclk();
}
-void s5p_clock_init(void)
+unsigned long get_pll_clk(int pllreg)
{
- if (cpu_is_s5pc110()) {
- get_pll_clk = s5pc110_get_pll_clk;
- get_arm_clk = s5pc110_get_arm_clk;
- } else {
- get_pll_clk = s5pc100_get_pll_clk;
- get_arm_clk = s5pc100_get_arm_clk;
- }
- get_uart_clk = s5pc1xx_get_uart_clk;
- get_pwm_clk = s5pc1xx_get_pwm_clk;
+ if (cpu_is_s5pc110())
+ return s5pc110_get_pll_clk(pllreg);
+ else
+ return s5pc100_get_pll_clk(pllreg);
+}
+
+unsigned long get_arm_clk(void)
+{
+ if (cpu_is_s5pc110())
+ return s5pc110_get_arm_clk();
+ else
+ return s5pc100_get_arm_clk();
+}
+
+unsigned long get_pwm_clk(void)
+{
+ return s5pc1xx_get_pwm_clk();
+}
+
+unsigned long get_uart_clk(int dev_index)
+{
+ return s5pc1xx_get_uart_clk(dev_index);
}
--- /dev/null
+#
+# Copyright (C) 2009 Samsung Electronics
+# Minkyu Kang <mk7.kang@samsung.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS += clock.o soc.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk.h>
+
+#ifndef CONFIG_SYS_CLK_FREQ_C210
+#define CONFIG_SYS_CLK_FREQ_C210 24000000
+#endif
+
+/* s5pc210: return pll clock frequency */
+static unsigned long s5pc210_get_pll_clk(int pllreg)
+{
+ struct s5pc210_clock *clk =
+ (struct s5pc210_clock *)samsung_get_base_clock();
+ unsigned long r, m, p, s, k = 0, mask, fout;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con0);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con0);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con0);
+ k = readl(&clk->epll_con1);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con0);
+ k = readl(&clk->vpll_con1);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ /*
+ * APLL_CON: MIDV [25:16]
+ * MPLL_CON: MIDV [25:16]
+ * EPLL_CON: MIDV [24:16]
+ * VPLL_CON: MIDV [24:16]
+ */
+ if (pllreg == APLL || pllreg == MPLL)
+ mask = 0x3ff;
+ else
+ mask = 0x1ff;
+
+ m = (r >> 16) & mask;
+
+ /* PDIV [13:8] */
+ p = (r >> 8) & 0x3f;
+ /* SDIV [2:0] */
+ s = r & 0x7;
+
+ freq = CONFIG_SYS_CLK_FREQ_C210;
+
+ if (pllreg == EPLL) {
+ k = k & 0xffff;
+ /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
+ fout = (m + k / 65536) * (freq / (p * (1 << s)));
+ } else if (pllreg == VPLL) {
+ k = k & 0xfff;
+ /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
+ fout = (m + k / 1024) * (freq / (p * (1 << s)));
+ } else {
+ if (s < 1)
+ s = 1;
+ /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
+ fout = m * (freq / (p * (1 << (s - 1))));
+ }
+
+ return fout;
+}
+
+/* s5pc210: return ARM clock frequency */
+static unsigned long s5pc210_get_arm_clk(void)
+{
+ struct s5pc210_clock *clk =
+ (struct s5pc210_clock *)samsung_get_base_clock();
+ unsigned long div;
+ unsigned long dout_apll;
+ unsigned int apll_ratio;
+
+ div = readl(&clk->div_cpu0);
+
+ /* APLL_RATIO: [26:24] */
+ apll_ratio = (div >> 24) & 0x7;
+
+ dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
+
+ return dout_apll;
+}
+
+/* s5pc210: return pwm clock frequency */
+static unsigned long s5pc210_get_pwm_clk(void)
+{
+ struct s5pc210_clock *clk =
+ (struct s5pc210_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+ * CLK_SRC_PERIL0
+ * PWM_SEL [27:24]
+ */
+ sel = readl(&clk->src_peril0);
+ sel = (sel >> 24) & 0xf;
+
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ /*
+ * CLK_DIV_PERIL3
+ * PWM_RATIO [3:0]
+ */
+ ratio = readl(&clk->div_peril3);
+ ratio = ratio & 0xf;
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
+/* s5pc210: return uart clock frequency */
+static unsigned long s5pc210_get_uart_clk(int dev_index)
+{
+ struct s5pc210_clock *clk =
+ (struct s5pc210_clock *)samsung_get_base_clock();
+ unsigned long uclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+ * CLK_SRC_PERIL0
+ * UART0_SEL [3:0]
+ * UART1_SEL [7:4]
+ * UART2_SEL [8:11]
+ * UART3_SEL [12:15]
+ * UART4_SEL [16:19]
+ * UART5_SEL [23:20]
+ */
+ sel = readl(&clk->src_peril0);
+ sel = (sel >> (dev_index << 2)) & 0xf;
+
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ /*
+ * CLK_DIV_PERIL0
+ * UART0_RATIO [3:0]
+ * UART1_RATIO [7:4]
+ * UART2_RATIO [8:11]
+ * UART3_RATIO [12:15]
+ * UART4_RATIO [16:19]
+ * UART5_RATIO [23:20]
+ */
+ ratio = readl(&clk->div_peril0);
+ ratio = (ratio >> (dev_index << 2)) & 0xf;
+
+ uclk = sclk / (ratio + 1);
+
+ return uclk;
+}
+
+unsigned long get_pll_clk(int pllreg)
+{
+ return s5pc210_get_pll_clk(pllreg);
+}
+
+unsigned long get_arm_clk(void)
+{
+ return s5pc210_get_arm_clk();
+}
+
+unsigned long get_pwm_clk(void)
+{
+ return s5pc210_get_pwm_clk();
+}
+
+unsigned long get_uart_clk(int dev_index)
+{
+ return s5pc210_get_uart_clk(dev_index);
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Samsung Electronics.
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+void reset_cpu(ulong addr)
+{
+ writel(0x1, samsung_get_base_swreset());
+}
beq clear_bss /* skip relocation */
#endif
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
clear_bss:
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
int dp83848_init_phy(int phy_addr);
int dp83848_auto_negotiate(int phy_addr);
+#define PHY_ET1011C (0x282f013)
+int et1011c_get_link_speed(int phy_addr);
+
#endif /* _DM644X_EMAC_H_ */
#define DAVINCI_DM646X_LPSC_EMAC 14
#define DAVINCI_DM646X_LPSC_UART0 26
#define DAVINCI_DM646X_LPSC_I2C 31
+#define DAVINCI_DM646X_LPSC_TIMER0 34
#else /* CONFIG_SOC_DA8XX */
--- /dev/null
+/*
+ * Davinci MMC Controller Defines - Based on Linux davinci_mmc.c
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _SDMMC_DEFS_H_
+#define _SDMMC_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+/* MMC Control Reg fields */
+#define MMCCTL_DATRST (1 << 0)
+#define MMCCTL_CMDRST (1 << 1)
+#define MMCCTL_WIDTH_4_BIT (1 << 2)
+#define MMCCTL_DATEG_DISABLED (0 << 6)
+#define MMCCTL_DATEG_RISING (1 << 6)
+#define MMCCTL_DATEG_FALLING (2 << 6)
+#define MMCCTL_DATEG_BOTH (3 << 6)
+#define MMCCTL_PERMDR_LE (0 << 9)
+#define MMCCTL_PERMDR_BE (1 << 9)
+#define MMCCTL_PERMDX_LE (0 << 10)
+#define MMCCTL_PERMDX_BE (1 << 10)
+
+/* MMC Clock Control Reg fields */
+#define MMCCLK_CLKEN (1 << 8)
+#define MMCCLK_CLKRT_MASK (0xFF << 0)
+
+/* MMC Status Reg0 fields */
+#define MMCST0_DATDNE (1 << 0)
+#define MMCST0_BSYDNE (1 << 1)
+#define MMCST0_RSPDNE (1 << 2)
+#define MMCST0_TOUTRD (1 << 3)
+#define MMCST0_TOUTRS (1 << 4)
+#define MMCST0_CRCWR (1 << 5)
+#define MMCST0_CRCRD (1 << 6)
+#define MMCST0_CRCRS (1 << 7)
+#define MMCST0_DXRDY (1 << 9)
+#define MMCST0_DRRDY (1 << 10)
+#define MMCST0_DATED (1 << 11)
+#define MMCST0_TRNDNE (1 << 12)
+
+#define MMCST0_ERR_MASK (0x00F8)
+
+/* MMC Status Reg1 fields */
+#define MMCST1_BUSY (1 << 0)
+#define MMCST1_CLKSTP (1 << 1)
+#define MMCST1_DXEMP (1 << 2)
+#define MMCST1_DRFUL (1 << 3)
+#define MMCST1_DAT3ST (1 << 4)
+#define MMCST1_FIFOEMP (1 << 5)
+#define MMCST1_FIFOFUL (1 << 6)
+
+/* MMC INT Mask Reg fields */
+#define MMCIM_EDATDNE (1 << 0)
+#define MMCIM_EBSYDNE (1 << 1)
+#define MMCIM_ERSPDNE (1 << 2)
+#define MMCIM_ETOUTRD (1 << 3)
+#define MMCIM_ETOUTRS (1 << 4)
+#define MMCIM_ECRCWR (1 << 5)
+#define MMCIM_ECRCRD (1 << 6)
+#define MMCIM_ECRCRS (1 << 7)
+#define MMCIM_EDXRDY (1 << 9)
+#define MMCIM_EDRRDY (1 << 10)
+#define MMCIM_EDATED (1 << 11)
+#define MMCIM_ETRNDNE (1 << 12)
+
+#define MMCIM_MASKALL (0xFFFFFFFF)
+
+/* MMC Resp Tout Reg fields */
+#define MMCTOR_TOR_MASK (0xFF) /* dont write to reg, | it */
+#define MMCTOR_TOD_20_16_SHIFT (8)
+
+/* MMC Data Read Tout Reg fields */
+#define MMCTOD_TOD_0_15_MASK (0xFFFF)
+
+/* MMC Block len Reg fields */
+#define MMCBLEN_BLEN_MASK (0xFFF)
+
+/* MMC Num Blocks Reg fields */
+#define MMCNBLK_NBLK_MASK (0xFFFF)
+#define MMCNBLK_NBLK_MAX (0xFFFF)
+
+/* MMC Num Blocks Counter Reg fields */
+#define MMCNBLC_NBLC_MASK (0xFFFF)
+
+/* MMC Cmd Reg fields */
+#define MMCCMD_CMD_MASK (0x3F)
+#define MMCCMD_PPLEN (1 << 7)
+#define MMCCMD_BSYEXP (1 << 8)
+#define MMCCMD_RSPFMT_NONE (0 << 9)
+#define MMCCMD_RSPFMT_R1567 (1 << 9)
+#define MMCCMD_RSPFMT_R2 (2 << 9)
+#define MMCCMD_RSPFMT_R3 (3 << 9)
+#define MMCCMD_DTRW (1 << 11)
+#define MMCCMD_STRMTP (1 << 12)
+#define MMCCMD_WDATX (1 << 13)
+#define MMCCMD_INITCK (1 << 14)
+#define MMCCMD_DCLR (1 << 15)
+#define MMCCMD_DMATRIG (1 << 16)
+
+/* FIFO control Reg fields */
+#define MMCFIFOCTL_FIFORST (1 << 0)
+#define MMCFIFOCTL_FIFODIR (1 << 1)
+#define MMCFIFOCTL_FIFOLEV (1 << 2)
+#define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
+#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
+#define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
+#define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
+
+/* Davinci MMC Register definitions */
+struct davinci_mmc_regs {
+ dv_reg mmcctl;
+ dv_reg mmcclk;
+ dv_reg mmcst0;
+ dv_reg mmcst1;
+ dv_reg mmcim;
+ dv_reg mmctor;
+ dv_reg mmctod;
+ dv_reg mmcblen;
+ dv_reg mmcnblk;
+ dv_reg mmcnblc;
+ dv_reg mmcdrr;
+ dv_reg mmcdxr;
+ dv_reg mmccmd;
+ dv_reg mmcarghl;
+ dv_reg mmcrsp01;
+ dv_reg mmcrsp23;
+ dv_reg mmcrsp45;
+ dv_reg mmcrsp67;
+ dv_reg mmcdrsp;
+ dv_reg mmcetok;
+ dv_reg mmccidx;
+ dv_reg mmcckc;
+ dv_reg mmctorc;
+ dv_reg mmctodc;
+ dv_reg mmcblnc;
+ dv_reg sdioctl;
+ dv_reg sdiost0;
+ dv_reg sdioien;
+ dv_reg sdioist;
+ dv_reg mmcfifoctl;
+};
+
+/* Davinci MMC board definitions */
+struct davinci_mmc {
+ struct davinci_mmc_regs *reg_base; /* Register base address */
+ uint input_clk; /* Input clock to MMC controller */
+ uint host_caps; /* Host capabilities */
+ uint voltages; /* Host supported voltages */
+ uint version; /* MMC Controller version */
+};
+
+enum {
+ MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
+ MMC_CTLR_VERSION_2, /* DA830 */
+};
+
+int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);
+
+#endif /* _SDMMC_DEFS_H */
u32 gpio_psr;
};
+struct cspi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 ctrl;
+ u32 intr;
+ u32 dma;
+ u32 stat;
+ u32 period;
+ u32 test;
+};
+
#define IOMUX_PADNUM_MASK 0x1ff
#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_AHB_CLK,
+ MXC_IPG_CLK,
+ MXC_IPG_PERCLK,
+ MXC_UART_CLK,
+ MXC_ESDHC_CLK,
+ MXC_USB_CLK,
+ MXC_CSPI_CLK,
+ MXC_FEC_CLK,
+};
+
+unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
+
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_CLOCK_H */
--- /dev/null
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__
+#define __CPU_ARM1136_MX35_CRM_REGS_H__
+
+/* Register bit definitions */
+#define MXC_CCM_CCMR_WFI (1 << 30)
+#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29)
+#define MXC_CCM_CCMR_VSTBY (1 << 28)
+#define MXC_CCM_CCMR_WBEN (1 << 27)
+#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20
+#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20)
+#define MXC_CCM_CCMR_ROMW_OFFSET 18
+#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18)
+#define MXC_CCM_CCMR_RAMW_OFFSET 21
+#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21)
+#define MXC_CCM_CCMR_LPM_OFFSET 14
+#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
+#define MXC_CCM_CCMR_UPE (1 << 9)
+#define MXC_CCM_CCMR_MPE (1 << 3)
+
+#define MXC_CCM_PDR0_PER_SEL (1 << 26)
+#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23)
+#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20
+#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20)
+#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16
+#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16)
+#define MXC_CCM_PDR0_CKIL_SEL (1 << 15)
+#define MXC_CCM_PDR0_PER_PODF_OFFSET 12
+#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12)
+#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9
+#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9)
+#define MXC_CCM_PDR0_AUTO_CON 0x1
+
+#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28
+#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28)
+#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22
+#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22)
+#define MXC_CCM_PDR1_MSHC_M_U (1 << 7)
+
+#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27
+#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27)
+#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24
+#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24)
+#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19
+#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19)
+#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16
+#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16)
+#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8
+#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8)
+#define MXC_CCM_PDR2_CSI_M_U (1 << 7)
+#define MXC_CCM_PDR2_SSI_M_U (1 << 6)
+#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0
+#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F)
+
+#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29
+#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29)
+#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23
+#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23)
+#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22)
+#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19
+#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19)
+#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16
+#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16)
+#define MXC_CCM_PDR3_UART_M_U (1 << 15)
+#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11
+#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11)
+#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8
+#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8)
+#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6)
+#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3
+#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3)
+#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0
+#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7)
+
+#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28
+#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28)
+#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25
+#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25)
+#define MXC_CCM_PDR4_USB_PODF_OFFSET 22
+#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22)
+#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19
+#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19)
+#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16
+#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16)
+#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13
+#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13)
+#define MXC_CCM_PDR4_UART_PODF_OFFSET 10
+#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10)
+#define MXC_CCM_PDR4_USB_M_U (1 << 9)
+
+/* Bit definitions for RCSR */
+#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29)
+#define MXC_CCM_RCSR_BUS_16BIT (1 << 29)
+#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27)
+#define MXC_CCM_RCSR_PAGE_512 (0 << 27)
+#define MXC_CCM_RCSR_PAGE_2K (1 << 27)
+#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27)
+#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27)
+#define MXC_CCM_RCSR_SOFT_RESET (1 << 15)
+#define MXC_CCM_RCSR_NF16B (1 << 14)
+#define MXC_CCM_RCSR_NFC_4K (1 << 9)
+#define MXC_CCM_RCSR_NFC_FMS (1 << 8)
+
+/* Bit definitions for both MCU, PERIPHERAL PLL control registers */
+#define MXC_CCM_PCTL_BRM 0x80000000
+#define MXC_CCM_PCTL_PD_OFFSET 26
+#define MXC_CCM_PCTL_PD_MASK (0xF << 26)
+#define MXC_CCM_PCTL_MFD_OFFSET 16
+#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16)
+#define MXC_CCM_PCTL_MFI_OFFSET 10
+#define MXC_CCM_PCTL_MFI_MASK (0xF << 10)
+#define MXC_CCM_PCTL_MFN_OFFSET 0
+#define MXC_CCM_PCTL_MFN_MASK 0x3FF
+
+/* Bit definitions for Audio clock mux register*/
+#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12
+#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12)
+#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8
+#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8)
+#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4
+#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4)
+#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0
+#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0)
+
+/* Bit definitions for Clock gating Register*/
+#define MXC_CCM_CGR0_ASRC_OFFSET 0
+#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0)
+#define MXC_CCM_CGR0_ATA_OFFSET 2
+#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2)
+#define MXC_CCM_CGR0_CAN1_OFFSET 6
+#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6)
+#define MXC_CCM_CGR0_CAN2_OFFSET 8
+#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8)
+#define MXC_CCM_CGR0_CSPI1_OFFSET 10
+#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10)
+#define MXC_CCM_CGR0_CSPI2_OFFSET 12
+#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12)
+#define MXC_CCM_CGR0_ECT_OFFSET 14
+#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14)
+#define MXC_CCM_CGR0_EDI0_OFFSET 16
+#define MXC_CCM_CGR0_EDI0_MASK (0x3 << 16)
+#define MXC_CCM_CGR0_EMI_OFFSET 18
+#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18)
+#define MXC_CCM_CGR0_EPIT1_OFFSET 20
+#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20)
+#define MXC_CCM_CGR0_EPIT2_OFFSET 22
+#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22)
+#define MXC_CCM_CGR0_ESAI_OFFSET 24
+#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24)
+#define MXC_CCM_CGR0_ESDHC1_OFFSET 26
+#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26)
+#define MXC_CCM_CGR0_ESDHC2_OFFSET 28
+#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28)
+#define MXC_CCM_CGR0_ESDHC3_OFFSET 30
+#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30)
+
+#define MXC_CCM_CGR1_FEC_OFFSET 0
+#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0)
+#define MXC_CCM_CGR1_GPIO1_OFFSET 2
+#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2)
+#define MXC_CCM_CGR1_GPIO2_OFFSET 4
+#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4)
+#define MXC_CCM_CGR1_GPIO3_OFFSET 6
+#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6)
+#define MXC_CCM_CGR1_GPT_OFFSET 8
+#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8)
+#define MXC_CCM_CGR1_I2C1_OFFSET 10
+#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10)
+#define MXC_CCM_CGR1_I2C2_OFFSET 12
+#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12)
+#define MXC_CCM_CGR1_I2C3_OFFSET 14
+#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14)
+#define MXC_CCM_CGR1_IOMUXC_OFFSET 16
+#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16)
+#define MXC_CCM_CGR1_IPU_OFFSET 18
+#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18)
+#define MXC_CCM_CGR1_KPP_OFFSET 20
+#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20)
+#define MXC_CCM_CGR1_MLB_OFFSET 22
+#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22)
+#define MXC_CCM_CGR1_MSHC_OFFSET 24
+#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24)
+#define MXC_CCM_CGR1_OWIRE_OFFSET 26
+#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26)
+#define MXC_CCM_CGR1_PWM_OFFSET 28
+#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28)
+#define MXC_CCM_CGR1_RNGC_OFFSET 30
+#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30)
+
+#define MXC_CCM_CGR2_RTC_OFFSET 0
+#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0)
+#define MXC_CCM_CGR2_RTIC_OFFSET 2
+#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2)
+#define MXC_CCM_CGR2_SCC_OFFSET 4
+#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4)
+#define MXC_CCM_CGR2_SDMA_OFFSET 6
+#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6)
+#define MXC_CCM_CGR2_SPBA_OFFSET 8
+#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8)
+#define MXC_CCM_CGR2_SPDIF_OFFSET 10
+#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10)
+#define MXC_CCM_CGR2_SSI1_OFFSET 12
+#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12)
+#define MXC_CCM_CGR2_SSI2_OFFSET 14
+#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14)
+#define MXC_CCM_CGR2_UART1_OFFSET 16
+#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16)
+#define MXC_CCM_CGR2_UART2_OFFSET 18
+#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18)
+#define MXC_CCM_CGR2_UART3_OFFSET 20
+#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20)
+#define MXC_CCM_CGR2_USBOTG_OFFSET 22
+#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22)
+#define MXC_CCM_CGR2_WDOG_OFFSET 24
+#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24)
+#define MXC_CCM_CGR2_MAX_OFFSET 26
+#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26)
+#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26)
+#define MXC_CCM_CGR2_AUDMUX_OFFSET 30
+#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30)
+
+#define MXC_CCM_CGR3_CSI_OFFSET 0
+#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0)
+#define MXC_CCM_CGR3_IIM_OFFSET 2
+#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2)
+#define MXC_CCM_CGR3_GPU2D_OFFSET 4
+#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4)
+
+#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F
+#define MXC_CCM_COSR_CLKOSEL_OFFSET 0
+#define MXC_CCM_COSR_CLKOEN (1 << 5)
+#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6)
+#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 10)
+#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 10
+#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 13)
+#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 13
+#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16)
+#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16
+#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18)
+#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18
+#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20)
+#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20
+#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22)
+#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22
+#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24)
+#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26)
+#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26
+
+#endif
--- /dev/null
+/*
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MX35_H
+#define __ASM_ARCH_MX35_H
+
+/*
+ * IRAM
+ */
+#define IRAM_BASE_ADDR 0x10000000 /* internal ram */
+#define IRAM_SIZE 0x00020000 /* 128 KB */
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR 0x43F00000
+#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
+#define MAX_BASE_ADDR 0x43F04000
+#define EVTMON_BASE_ADDR 0x43F08000
+#define CLKCTL_BASE_ADDR 0x43F0C000
+#define I2C_BASE_ADDR 0x43F80000
+#define I2C3_BASE_ADDR 0x43F84000
+#define ATA_BASE_ADDR 0x43F8C000
+#define UART1_BASE_ADDR 0x43F90000
+#define UART2_BASE_ADDR 0x43F94000
+#define I2C2_BASE_ADDR 0x43F98000
+#define CSPI1_BASE_ADDR 0x43FA4000
+#define IOMUXC_BASE_ADDR 0x43FAC000
+
+/*
+ * SPBA
+ */
+#define SPBA_BASE_ADDR 0x50000000
+#define UART3_BASE_ADDR 0x5000C000
+#define CSPI2_BASE_ADDR 0x50010000
+#define ATA_DMA_BASE_ADDR 0x50020000
+#define FEC_BASE_ADDR 0x50038000
+#define SPBA_CTRL_BASE_ADDR 0x5003C000
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR 0x53F00000
+#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
+#define CCM_BASE_ADDR 0x53F80000
+#define GPT1_BASE_ADDR 0x53F90000
+#define EPIT1_BASE_ADDR 0x53F94000
+#define EPIT2_BASE_ADDR 0x53F98000
+#define GPIO3_BASE_ADDR 0x53FA4000
+#define MMC_SDHC1_BASE_ADDR 0x53FB4000
+#define MMC_SDHC2_BASE_ADDR 0x53FB8000
+#define MMC_SDHC3_BASE_ADDR 0x53FBC000
+#define IPU_CTRL_BASE_ADDR 0x53FC0000
+#define GPIO3_BASE_ADDR 0x53FA4000
+#define GPIO1_BASE_ADDR 0x53FCC000
+#define GPIO2_BASE_ADDR 0x53FD0000
+#define SDMA_BASE_ADDR 0x53FD4000
+#define RTC_BASE_ADDR 0x53FD8000
+#define WDOG_BASE_ADDR 0x53FDC000
+#define PWM_BASE_ADDR 0x53FE0000
+#define RTIC_BASE_ADDR 0x53FEC000
+#define IIM_BASE_ADDR 0x53FF0000
+
+#define IMX_CCM_BASE CCM_BASE_ADDR
+
+/*
+ * ROMPATCH and AVIC
+ */
+#define ROMPATCH_BASE_ADDR 0x60000000
+#define AVIC_BASE_ADDR 0x68000000
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define EXT_MEM_CTRL_BASE 0xB8000000
+#define ESDCTL_BASE_ADDR 0xB8001000
+#define WEIM_BASE_ADDR 0xB8002000
+#define WEIM_CTRL_CS0 WEIM_BASE_ADDR
+#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
+#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
+#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
+#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
+#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50)
+#define M3IF_BASE_ADDR 0xB8003000
+#define EMI_BASE_ADDR 0xB8004000
+
+#define NFC_BASE_ADDR 0xBB000000
+
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE_ADDR 0x70000000
+#define CSD0_BASE_ADDR 0x80000000
+#define CSD1_BASE_ADDR 0x90000000
+#define CS0_BASE_ADDR 0xA0000000
+#define CS1_BASE_ADDR 0xA8000000
+#define CS2_BASE_ADDR 0xB0000000
+#define CS3_BASE_ADDR 0xB2000000
+#define CS4_BASE_ADDR 0xB4000000
+#define CS5_BASE_ADDR 0xB6000000
+
+/*
+ * IRQ Controller Register Definitions.
+ */
+#define AVIC_NIMASK 0x04
+#define AVIC_INTTYPEH 0x18
+#define AVIC_INTTYPEL 0x1C
+
+/* L210 */
+#define L2CC_BASE_ADDR 0x30000000
+#define L2_CACHE_LINE_SIZE 32
+#define L2_CACHE_CTL_REG 0x100
+#define L2_CACHE_AUX_CTL_REG 0x104
+#define L2_CACHE_SYNC_REG 0x730
+#define L2_CACHE_INV_LINE_REG 0x770
+#define L2_CACHE_INV_WAY_REG 0x77C
+#define L2_CACHE_CLEAN_LINE_REG 0x7B0
+#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
+#define L2_CACHE_DBG_CTL_REG 0xF40
+
+#define CLKMODE_AUTO 0
+#define CLKMODE_CONSUMER 1
+
+#define PLL_PD(x) (((x) & 0xf) << 26)
+#define PLL_MFD(x) (((x) & 0x3ff) << 16)
+#define PLL_MFI(x) (((x) & 0xf) << 10)
+#define PLL_MFN(x) (((x) & 0x3ff) << 0)
+
+#define CSCR_U(x) (WEIM_CTRL_CS#x + 0)
+#define CSCR_L(x) (WEIM_CTRL_CS#x + 4)
+#define CSCR_A(x) (WEIM_CTRL_CS#x + 8)
+
+#define IIM_SREV 0x24
+#define ROMPATCH_REV 0x40
+
+#define IPU_CONF IPU_CTRL_BASE_ADDR
+
+#define IPU_CONF_PXL_ENDIAN (1<<8)
+#define IPU_CONF_DU_EN (1<<7)
+#define IPU_CONF_DI_EN (1<<6)
+#define IPU_CONF_ADC_EN (1<<5)
+#define IPU_CONF_SDC_EN (1<<4)
+#define IPU_CONF_PF_EN (1<<3)
+#define IPU_CONF_ROT_EN (1<<2)
+#define IPU_CONF_IC_EN (1<<1)
+#define IPU_CONF_SCI_EN (1<<0)
+
+#define GPIO_PORT_NUM 3
+#define GPIO_NUM_PIN 32
+
+#define CHIP_REV_1_0 0x10
+#define CHIP_REV_2_0 0x20
+
+#define BOARD_REV_1_0 0x0
+#define BOARD_REV_2_0 0x1
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+extern void imx_get_mac_from_fuse(unsigned char *mac);
+
+enum mxc_main_clocks {
+ CPU_CLK,
+ AHB_CLK,
+ IPG_CLK,
+ IPG_PER_CLK,
+ NFC_CLK,
+ USB_CLK,
+ HSP_CLK,
+};
+
+enum mxc_peri_clocks {
+ UART1_BAUD,
+ UART2_BAUD,
+ UART3_BAUD,
+ SSI1_BAUD,
+ SSI2_BAUD,
+ CSI_BAUD,
+ MSHC_CLK,
+ ESDHC1_CLK,
+ ESDHC2_CLK,
+ ESDHC3_CLK,
+ SPDIF_CLK,
+ SPI1_CLK,
+ SPI2_CLK,
+};
+
+/* Clock Control Module (CCM) registers */
+struct ccm_regs {
+ u32 ccmr; /* Control */
+ u32 pdr0; /* Post divider 0 */
+ u32 pdr1; /* Post divider 1 */
+ u32 pdr2; /* Post divider 2 */
+ u32 pdr3; /* Post divider 3 */
+ u32 pdr4; /* Post divider 4 */
+ u32 rcsr; /* CCM Status */
+ u32 mpctl; /* Core PLL Control */
+ u32 ppctl; /* Peripheral PLL Control */
+ u32 acmr; /* Audio clock mux */
+ u32 cosr; /* Clock out source */
+ u32 cgr0; /* Clock Gating Control 0 */
+ u32 cgr1; /* Clock Gating Control 1 */
+ u32 cgr2; /* Clock Gating Control 2 */
+ u32 cgr3; /* Clock Gating Control 3 */
+ u32 reserved;
+ u32 dcvr0; /* DPTC Comparator 0 */
+ u32 dcvr1; /* DPTC Comparator 0 */
+ u32 dcvr2; /* DPTC Comparator 0 */
+ u32 dcvr3; /* DPTC Comparator 0 */
+ u32 ltr0; /* Load Tracking 0 */
+ u32 ltr1; /* Load Tracking 1 */
+ u32 ltr2; /* Load Tracking 2 */
+ u32 ltr3; /* Load Tracking 3 */
+ u32 ltbr0; /* Load Tracking Buffer 0 */
+};
+
+/* IIM control registers */
+struct iim_regs {
+ u32 iim_stat;
+ u32 iim_statm;
+ u32 iim_err;
+ u32 iim_emask;
+ u32 iim_fctl;
+ u32 iim_ua;
+ u32 iim_la;
+ u32 iim_sdat;
+ u32 iim_prev;
+ u32 iim_srev;
+ u32 iim_prog_p;
+ u32 iim_scs0;
+ u32 iim_scs1;
+ u32 iim_scs2;
+ u32 iim_scs3;
+};
+
+/* General Purpose Timer (GPT) registers */
+struct gpt_regs {
+ u32 ctrl; /* control */
+ u32 pre; /* prescaler */
+ u32 stat; /* status */
+ u32 intr; /* interrupt */
+ u32 cmp[3]; /* output compare 1-3 */
+ u32 capt[2]; /* input capture 1-2 */
+ u32 counter; /* counter */
+};
+
+/* CSPI registers */
+struct cspi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 ctrl;
+ u32 intr;
+ u32 dma;
+ u32 stat;
+ u32 period;
+ u32 test;
+};
+
+/* Watchdog Timer (WDOG) registers */
+struct wdog_regs {
+ u16 wcr; /* Control */
+ u16 wsr; /* Service */
+ u16 wrsr; /* Reset Status */
+ u16 wicr; /* Interrupt Control */
+ u16 wmcr; /* Misc Control */
+};
+
+/*
+ * NFMS bit in RCSR register for pagesize of nandflash
+ */
+#define NFMS_BIT 8
+#define NFMS_NF_DWIDTH 14
+#define NFMS_NF_PG_SZ 8
+
+#define CCM_RCSR_NF_16BIT_SEL (1 << 14)
+
+extern unsigned int get_board_rev(void);
+extern int is_soc_rev(int rev);
+extern int sdhc_init(void);
+
+#endif
+#endif /* __ASM_ARCH_MX35_H */
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MACH_MX35_IOMUX_H__
+#define __MACH_MX35_IOMUX_H__
+
+#include <asm/arch/imx-regs.h>
+
+/*
+ * various IOMUX functions
+ */
+typedef enum iomux_pin_config {
+ MUX_CONFIG_FUNC = 0, /* used as function */
+ MUX_CONFIG_ALT1, /* used as alternate function 1 */
+ MUX_CONFIG_ALT2, /* used as alternate function 2 */
+ MUX_CONFIG_ALT3, /* used as alternate function 3 */
+ MUX_CONFIG_ALT4, /* used as alternate function 4 */
+ MUX_CONFIG_ALT5, /* used as alternate function 5 */
+ MUX_CONFIG_ALT6, /* used as alternate function 6 */
+ MUX_CONFIG_ALT7, /* used as alternate function 7 */
+ MUX_CONFIG_SION = 0x1 << 4, /* used as LOOPBACK:MUX SION bit */
+ MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /* used as GPIO */
+} iomux_pin_cfg_t;
+
+/*
+ * various IOMUX pad functions
+ */
+typedef enum iomux_pad_config {
+ PAD_CTL_DRV_3_3V = 0x0 << 13,
+ PAD_CTL_DRV_1_8V = 0x1 << 13,
+ PAD_CTL_HYS_CMOS = 0x0 << 8,
+ PAD_CTL_HYS_SCHMITZ = 0x1 << 8,
+ PAD_CTL_PKE_NONE = 0x0 << 7,
+ PAD_CTL_PKE_ENABLE = 0x1 << 7,
+ PAD_CTL_PUE_KEEPER = 0x0 << 6,
+ PAD_CTL_PUE_PUD = 0x1 << 6,
+ PAD_CTL_100K_PD = 0x0 << 4,
+ PAD_CTL_47K_PU = 0x1 << 4,
+ PAD_CTL_100K_PU = 0x2 << 4,
+ PAD_CTL_22K_PU = 0x3 << 4,
+ PAD_CTL_ODE_CMOS = 0x0 << 3,
+ PAD_CTL_ODE_OpenDrain = 0x1 << 3,
+ PAD_CTL_DRV_NORMAL = 0x0 << 1,
+ PAD_CTL_DRV_HIGH = 0x1 << 1,
+ PAD_CTL_DRV_MAX = 0x2 << 1,
+ PAD_CTL_SRE_SLOW = 0x0 << 0,
+ PAD_CTL_SRE_FAST = 0x1 << 0
+} iomux_pad_config_t;
+
+/*
+ * various IOMUX general purpose functions
+ */
+typedef enum iomux_gp_func {
+ MUX_SDCTL_CSD0_SEL = 0x1 << 0,
+ MUX_SDCTL_CSD1_SEL = 0x1 << 1,
+ MUX_TAMPER_DETECT_EN = 0x1 << 2,
+} iomux_gp_func_t;
+
+/*
+ * various IOMUX input select register index
+ */
+typedef enum iomux_input_select {
+ MUX_IN_AMX_P5_RXCLK = 0,
+ MUX_IN_AMX_P5_RXFS,
+ MUX_IN_AMX_P6_DA,
+ MUX_IN_AMX_P6_DB,
+ MUX_IN_AMX_P6_RXCLK,
+ MUX_IN_AMX_P6_RXFS,
+ MUX_IN_AMX_P6_TXCLK,
+ MUX_IN_AMX_P6_TXFS,
+ MUX_IN_CAN1_CANRX,
+ MUX_IN_CAN2_CANRX,
+ MUX_IN_CCM_32K_MUXED,
+ MUX_IN_CCM_PMIC_RDY,
+ MUX_IN_CSPI1_SS2_B,
+ MUX_IN_CSPI1_SS3_B,
+ MUX_IN_CSPI2_CLK_IN,
+ MUX_IN_CSPI2_DATAREADY_B,
+ MUX_IN_CSPI2_MISO,
+ MUX_IN_CSPI2_MOSI,
+ MUX_IN_CSPI2_SS0_B,
+ MUX_IN_CSPI2_SS1_B,
+ MUX_IN_CSPI2_SS2_B,
+ MUX_IN_CSPI2_SS3_B,
+ MUX_IN_EMI_WEIM_DTACK_B,
+ MUX_IN_ESDHC1_DAT4_IN,
+ MUX_IN_ESDHC1_DAT5_IN,
+ MUX_IN_ESDHC1_DAT6_IN,
+ MUX_IN_ESDHC1_DAT7_IN,
+ MUX_IN_ESDHC3_CARD_CLK_IN,
+ MUX_IN_ESDHC3_CMD_IN,
+ MUX_IN_ESDHC3_DAT0,
+ MUX_IN_ESDHC3_DAT1,
+ MUX_IN_ESDHC3_DAT2,
+ MUX_IN_ESDHC3_DAT3,
+ MUX_IN_GPIO1_IN_0,
+ MUX_IN_GPIO1_IN_10,
+ MUX_IN_GPIO1_IN_11,
+ MUX_IN_GPIO1_IN_1,
+ MUX_IN_GPIO1_IN_20,
+ MUX_IN_GPIO1_IN_21,
+ MUX_IN_GPIO1_IN_22,
+ MUX_IN_GPIO1_IN_2,
+ MUX_IN_GPIO1_IN_3,
+ MUX_IN_GPIO1_IN_4,
+ MUX_IN_GPIO1_IN_5,
+ MUX_IN_GPIO1_IN_6,
+ MUX_IN_GPIO1_IN_7,
+ MUX_IN_GPIO1_IN_8,
+ MUX_IN_GPIO1_IN_9,
+ MUX_IN_GPIO2_IN_0,
+ MUX_IN_GPIO2_IN_10,
+ MUX_IN_GPIO2_IN_11,
+ MUX_IN_GPIO2_IN_12,
+ MUX_IN_GPIO2_IN_13,
+ MUX_IN_GPIO2_IN_14,
+ MUX_IN_GPIO2_IN_15,
+ MUX_IN_GPIO2_IN_16,
+ MUX_IN_GPIO2_IN_17,
+ MUX_IN_GPIO2_IN_18,
+ MUX_IN_GPIO2_IN_19,
+ MUX_IN_GPIO2_IN_20,
+ MUX_IN_GPIO2_IN_21,
+ MUX_IN_GPIO2_IN_22,
+ MUX_IN_GPIO2_IN_23,
+ MUX_IN_GPIO2_IN_24,
+ MUX_IN_GPIO2_IN_25,
+ MUX_IN_GPIO2_IN_26,
+ MUX_IN_GPIO2_IN_27,
+ MUX_IN_GPIO2_IN_28,
+ MUX_IN_GPIO2_IN_29,
+ MUX_IN_GPIO2_IN_2,
+ MUX_IN_GPIO2_IN_30,
+ MUX_IN_GPIO2_IN_31,
+ MUX_IN_GPIO2_IN_3,
+ MUX_IN_GPIO2_IN_4,
+ MUX_IN_GPIO2_IN_5,
+ MUX_IN_GPIO2_IN_6,
+ MUX_IN_GPIO2_IN_7,
+ MUX_IN_GPIO2_IN_8,
+ MUX_IN_GPIO2_IN_9,
+ MUX_IN_GPIO3_IN_0,
+ MUX_IN_GPIO3_IN_10,
+ MUX_IN_GPIO3_IN_11,
+ MUX_IN_GPIO3_IN_12,
+ MUX_IN_GPIO3_IN_13,
+ MUX_IN_GPIO3_IN_14,
+ MUX_IN_GPIO3_IN_15,
+ MUX_IN_GPIO3_IN_4,
+ MUX_IN_GPIO3_IN_5,
+ MUX_IN_GPIO3_IN_6,
+ MUX_IN_GPIO3_IN_7,
+ MUX_IN_GPIO3_IN_8,
+ MUX_IN_GPIO3_IN_9,
+ MUX_IN_I2C3_SCL_IN,
+ MUX_IN_I2C3_SDA_IN,
+ MUX_IN_IPU_DISPB_D0_VSYNC,
+ MUX_IN_IPU_DISPB_D12_VSYNC,
+ MUX_IN_IPU_DISPB_SD_D,
+ MUX_IN_IPU_SENSB_DATA_0,
+ MUX_IN_IPU_SENSB_DATA_1,
+ MUX_IN_IPU_SENSB_DATA_2,
+ MUX_IN_IPU_SENSB_DATA_3,
+ MUX_IN_IPU_SENSB_DATA_4,
+ MUX_IN_IPU_SENSB_DATA_5,
+ MUX_IN_IPU_SENSB_DATA_6,
+ MUX_IN_IPU_SENSB_DATA_7,
+ MUX_IN_KPP_COL_0,
+ MUX_IN_KPP_COL_1,
+ MUX_IN_KPP_COL_2,
+ MUX_IN_KPP_COL_3,
+ MUX_IN_KPP_COL_4,
+ MUX_IN_KPP_COL_5,
+ MUX_IN_KPP_COL_6,
+ MUX_IN_KPP_COL_7,
+ MUX_IN_KPP_ROW_0,
+ MUX_IN_KPP_ROW_1,
+ MUX_IN_KPP_ROW_2,
+ MUX_IN_KPP_ROW_3,
+ MUX_IN_KPP_ROW_4,
+ MUX_IN_KPP_ROW_5,
+ MUX_IN_KPP_ROW_6,
+ MUX_IN_KPP_ROW_7,
+ MUX_IN_OWIRE_BATTERY_LINE,
+ MUX_IN_SPDIF_HCKT_CLK2,
+ MUX_IN_SPDIF_SPDIF_IN1,
+ MUX_IN_UART3_UART_RTS_B,
+ MUX_IN_UART3_UART_RXD_MUX,
+ MUX_IN_USB_OTG_DATA_0,
+ MUX_IN_USB_OTG_DATA_1,
+ MUX_IN_USB_OTG_DATA_2,
+ MUX_IN_USB_OTG_DATA_3,
+ MUX_IN_USB_OTG_DATA_4,
+ MUX_IN_USB_OTG_DATA_5,
+ MUX_IN_USB_OTG_DATA_6,
+ MUX_IN_USB_OTG_DATA_7,
+ MUX_IN_USB_OTG_DIR,
+ MUX_IN_USB_OTG_NXT,
+ MUX_IN_USB_UH2_DATA_0,
+ MUX_IN_USB_UH2_DATA_1,
+ MUX_IN_USB_UH2_DATA_2,
+ MUX_IN_USB_UH2_DATA_3,
+ MUX_IN_USB_UH2_DATA_4,
+ MUX_IN_USB_UH2_DATA_5,
+ MUX_IN_USB_UH2_DATA_6,
+ MUX_IN_USB_UH2_DATA_7,
+ MUX_IN_USB_UH2_DIR,
+ MUX_IN_USB_UH2_NXT,
+ MUX_IN_USB_UH2_USB_OC,
+} iomux_input_select_t;
+
+/*
+ * various IOMUX input functions
+ */
+typedef enum iomux_input_config {
+ INPUT_CTL_PATH0 = 0x0,
+ INPUT_CTL_PATH1,
+ INPUT_CTL_PATH2,
+ INPUT_CTL_PATH3,
+ INPUT_CTL_PATH4,
+ INPUT_CTL_PATH5,
+ INPUT_CTL_PATH6,
+ INPUT_CTL_PATH7,
+} iomux_input_cfg_t;
+
+/*
+ * Request ownership for an IO pin. This function has to be the first one
+ * being called before that pin is used. The caller has to check the
+ * return value to make sure it returns 0.
+ *
+ * @param pin a name defined by iomux_pin_name_t
+ * @param cfg an input function as defined in iomux_pin_cfg_t
+ *
+ * @return 0 if successful; Non-zero otherwise
+ */
+void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
+
+/*
+ * Release ownership for an IO pin
+ *
+ * @param pin a name defined by iomux_pin_name_t
+ * @param cfg an input function as defined in iomux_pin_cfg_t
+ */
+void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
+
+/*
+ * This function enables/disables the general purpose function for a particular
+ * signal.
+ *
+ * @param gp one signal as defined in iomux_gp_func_t
+ * @param en 1 to enable; 0 to disable
+ */
+void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en);
+
+/*
+ * This function configures the pad value for a IOMUX pin.
+ *
+ * @param pin a pin number as defined in iomux_pin_name_t
+ * @param config the ORed value of elements defined in
+ * iomux_pad_config_t
+ */
+void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
+
+/*
+ * This function configures input path.
+ *
+ * @param input index of input select register as defined in
+ * iomux_input_select_t
+ * @param config the binary value of elements defined in
+ * iomux_input_cfg_t
+ */
+void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MXC_MX35_PINS_H__
+#define __ASM_ARCH_MXC_MX35_PINS_H__
+
+/*!
+ * @file arch-mxc/mx35_pins.h
+ *
+ * @brief MX35 I/O Pin List
+ *
+ * @ingroup GPIO_MX35
+ */
+
+#ifndef __ASSEMBLY__
+
+/*!
+ * @name IOMUX/PAD Bit field definitions
+ */
+
+/*! @{ */
+
+/*!
+ * In order to identify pins more effectively, each mux-controlled pin's
+ * enumerated value is constructed in the following way:
+ *
+ * -------------------------------------------------------------------
+ * 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0
+ * -------------------------------------------------------------------
+ * IO_P | IO_I | RSVD | PAD_I | MUX_I
+ * -------------------------------------------------------------------
+ *
+ * Bit 0 to 7 contains MUX_I used to identify the register
+ * offset (base is IOMUX_module_base ) defined in the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The similar field
+ * definitions are used for the pad control register.the MX35_PIN_A0 is
+ * defined in the enumeration: ( 0x28 << MUX_I) |( 0x368 << PAD_I)
+ * So the absolute address is: IOMUX_module_base + 0x28.
+ * The pad control register offset is: 0x368.
+ */
+
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * MUX control register offset
+ */
+#define MUX_I 0
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * PAD control register offset
+ */
+#define PAD_I 10
+
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * reserved filed
+ */
+#define RSVD_I 21
+
+#define MUX_IO_P 29
+#define MUX_IO_I 24
+#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
+ GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
+ ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
+#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
+#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
+#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
+
+#define NON_GPIO_I 0x7
+#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1)
+#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1)
+#define NON_MUX_I PIN_TO_MUX_MASK
+
+#define _MXC_BUILD_PIN(gp, gi, mi, pi) \
+ (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
+ ((mi) << MUX_I) | ((pi) << PAD_I))
+
+#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \
+ _MXC_BUILD_PIN(gp, gi, mi, pi)
+
+#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
+ _MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi)
+
+#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
+#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
+
+/*! @} End IOMUX/PAD Bit field definitions */
+
+/*!
+ * This enumeration is constructed based on the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the MX35 IC Spec. Each enumerated
+ * value is constructed based on the rules described above.
+ */
+typedef enum iomux_pins {
+ MX35_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 4, 0x4, 0x328),
+ MX35_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 5, 0x8, 0x32C),
+ MX35_PIN_WATCHDOG_RST = _MXC_BUILD_GPIO_PIN(0, 6, 0xC, 0x330),
+ MX35_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 0x10, 0x334),
+ MX35_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 0x14, 0x338),
+ MX35_PIN_GPIO2_0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x18, 0x33C),
+ MX35_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1C, 0x340),
+ MX35_PIN_CLKO = _MXC_BUILD_GPIO_PIN(0, 8, 0x20, 0x34C),
+
+ MX35_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x360),
+ MX35_PIN_VSTBY = _MXC_BUILD_GPIO_PIN(0, 7, 0x24, 0x364),
+ MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368),
+ MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C),
+ MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370),
+ MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374),
+ MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378),
+ MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C),
+ MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380),
+ MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384),
+ MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388),
+ MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C),
+ MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390),
+ MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394),
+ MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398),
+ MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C),
+ MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0),
+ MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4),
+ MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8),
+ MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC),
+ MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0),
+ MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4),
+ MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8),
+ MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC),
+ MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0),
+ MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4),
+ MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8),
+ MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC),
+ MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0),
+
+ MX35_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x46C),
+ MX35_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x470),
+ MX35_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x474),
+ MX35_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x478),
+ MX35_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x47C),
+ MX35_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x480),
+ MX35_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x484),
+ MX35_PIN_CS4 = _MXC_BUILD_GPIO_PIN(0, 20, 0xB0, 0x488),
+ MX35_PIN_CS5 = _MXC_BUILD_GPIO_PIN(0, 21, 0xB4, 0x48C),
+ MX35_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xB8, 0x490),
+
+ MX35_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(0xBC, 0x498),
+ MX35_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(0xC0, 0x49C),
+ MX35_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(0xC4, 0x4A0),
+
+ MX35_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(0, 18, 0xC8, 0x4CC),
+ MX35_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(0, 19, 0xCC, 0x4D0),
+ MX35_PIN_NFALE = _MXC_BUILD_GPIO_PIN(0, 20, 0xD0, 0x4D4),
+ MX35_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(0, 21, 0xD4, 0x4D8),
+ MX35_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xD8, 0x4DC),
+ MX35_PIN_NFRB = _MXC_BUILD_GPIO_PIN(0, 23, 0xDC, 0x4E0),
+
+ MX35_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E4),
+ MX35_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E8),
+ MX35_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4EC),
+ MX35_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F0),
+ MX35_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F4),
+ MX35_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F8),
+ MX35_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4FC),
+ MX35_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x500),
+ MX35_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x504),
+ MX35_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x508),
+ MX35_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x50C),
+ MX35_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x510),
+ MX35_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x514),
+ MX35_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x518),
+ MX35_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x51C),
+ MX35_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x520),
+
+ MX35_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 20, 0xE0, 0x524),
+ MX35_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(0, 21, 0xE4, 0x528),
+ MX35_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(0, 22, 0xE8, 0x52C),
+ MX35_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(0, 23, 0xEC, 0x530),
+ MX35_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(0, 24, 0xF0, 0x534),
+ MX35_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(0, 25, 0xF4, 0x538),
+ MX35_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(0, 26, 0xF8, 0x53C),
+ MX35_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(0, 27, 0xFC, 0x540),
+ MX35_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 28, 0x100, 0x544),
+ MX35_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 29, 0x104, 0x548),
+ MX35_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 30, 0x108, 0x54C),
+ MX35_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 31, 0x10C, 0x550),
+
+ MX35_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x110, 0x554),
+ MX35_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(1, 25, 0x114, 0x558),
+ MX35_PIN_I2C2_CLK = _MXC_BUILD_GPIO_PIN(1, 26, 0x118, 0x55C),
+ MX35_PIN_I2C2_DAT = _MXC_BUILD_GPIO_PIN(1, 27, 0x11C, 0x560),
+
+ MX35_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(1, 28, 0x120, 0x564),
+ MX35_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(1, 29, 0x124, 0x568),
+ MX35_PIN_SCK4 = _MXC_BUILD_GPIO_PIN(1, 30, 0x128, 0x56C),
+ MX35_PIN_STXFS4 = _MXC_BUILD_GPIO_PIN(1, 31, 0x12C, 0x570),
+ MX35_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 0, 0x130, 0x574),
+ MX35_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 1, 0x134, 0x578),
+ MX35_PIN_SCK5 = _MXC_BUILD_GPIO_PIN(0, 2, 0x138, 0x57C),
+ MX35_PIN_STXFS5 = _MXC_BUILD_GPIO_PIN(0, 3, 0x13C, 0x580),
+
+ MX35_PIN_SCKR = _MXC_BUILD_GPIO_PIN(0, 4, 0x140, 0x584),
+ MX35_PIN_FSR = _MXC_BUILD_GPIO_PIN(0, 5, 0x144, 0x588),
+ MX35_PIN_HCKR = _MXC_BUILD_GPIO_PIN(0, 6, 0x148, 0x58C),
+ MX35_PIN_SCKT = _MXC_BUILD_GPIO_PIN(0, 7, 0x14C, 0x590),
+ MX35_PIN_FST = _MXC_BUILD_GPIO_PIN(0, 8, 0x150, 0x594),
+ MX35_PIN_HCKT = _MXC_BUILD_GPIO_PIN(0, 9, 0x154, 0x598),
+ MX35_PIN_TX5_RX0 = _MXC_BUILD_GPIO_PIN(0, 10, 0x158, 0x59C),
+ MX35_PIN_TX4_RX1 = _MXC_BUILD_GPIO_PIN(0, 11, 0x15C, 0x5A0),
+ MX35_PIN_TX3_RX2 = _MXC_BUILD_GPIO_PIN(0, 12, 0x160, 0x5A4),
+ MX35_PIN_TX2_RX3 = _MXC_BUILD_GPIO_PIN(0, 13, 0x164, 0x5A8),
+ MX35_PIN_TX1 = _MXC_BUILD_GPIO_PIN(0, 14, 0x168, 0x5AC),
+ MX35_PIN_TX0 = _MXC_BUILD_GPIO_PIN(0, 15, 0x16C, 0x5B0),
+
+ MX35_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 16, 0x170, 0x5B4),
+ MX35_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 17, 0x174, 0x5B8),
+ MX35_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 18, 0x178, 0x5BC),
+ MX35_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 19, 0x17C, 0x5C0),
+ MX35_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(2, 4, 0x180, 0x5C4),
+ MX35_PIN_CSPI1_SPI_RDY = _MXC_BUILD_GPIO_PIN(2, 5, 0x184, 0x5C8),
+
+ MX35_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(2, 6, 0x188, 0x5CC),
+ MX35_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(2, 7, 0x18C, 0x5D0),
+ MX35_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x190, 0x5D4),
+ MX35_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(2, 9, 0x194, 0x5D8),
+ MX35_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(2, 10, 0x198, 0x5DC),
+ MX35_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(1, 11, 0x19C, 0x5E0),
+ MX35_PIN_RTS2 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1A0, 0x5E4),
+ MX35_PIN_CTS2 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1A4, 0x5E8),
+
+ MX35_PIN_USBOTG_PWR = _MXC_BUILD_GPIO_PIN(2, 14, 0x1A8, 0x60C),
+ MX35_PIN_USBOTG_OC = _MXC_BUILD_GPIO_PIN(2, 15, 0x1AC, 0x610),
+
+ MX35_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x1B0, 0x614),
+ MX35_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 1, 0x1B4, 0x618),
+ MX35_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 2, 0x1B8, 0x61C),
+ MX35_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1BC, 0x620),
+ MX35_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 4, 0x1C0, 0x624),
+ MX35_PIN_LD5 = _MXC_BUILD_GPIO_PIN(1, 5, 0x1C4, 0x628),
+ MX35_PIN_LD6 = _MXC_BUILD_GPIO_PIN(1, 6, 0x1C8, 0x62C),
+ MX35_PIN_LD7 = _MXC_BUILD_GPIO_PIN(1, 7, 0x1CC, 0x630),
+ MX35_PIN_LD8 = _MXC_BUILD_GPIO_PIN(1, 8, 0x1D0, 0x634),
+ MX35_PIN_LD9 = _MXC_BUILD_GPIO_PIN(1, 9, 0x1D4, 0x638),
+ MX35_PIN_LD10 = _MXC_BUILD_GPIO_PIN(1, 10, 0x1D8, 0x63C),
+ MX35_PIN_LD11 = _MXC_BUILD_GPIO_PIN(1, 11, 0x1DC, 0x640),
+ MX35_PIN_LD12 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1E0, 0x644),
+ MX35_PIN_LD13 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1E4, 0x648),
+ MX35_PIN_LD14 = _MXC_BUILD_GPIO_PIN(1, 14, 0x1E8, 0x64C),
+ MX35_PIN_LD15 = _MXC_BUILD_GPIO_PIN(1, 15, 0x1EC, 0x650),
+ MX35_PIN_LD16 = _MXC_BUILD_GPIO_PIN(1, 16, 0x1F0, 0x654),
+ MX35_PIN_LD17 = _MXC_BUILD_GPIO_PIN(1, 17, 0x1F4, 0x658),
+ MX35_PIN_LD18 = _MXC_BUILD_GPIO_PIN(2, 24, 0x1F8, 0x65C),
+ MX35_PIN_LD19 = _MXC_BUILD_GPIO_PIN(2, 25, 0x1FC, 0x660),
+ MX35_PIN_LD20 = _MXC_BUILD_GPIO_PIN(2, 26, 0x200, 0x664),
+ MX35_PIN_LD21 = _MXC_BUILD_GPIO_PIN(2, 27, 0x204, 0x668),
+ MX35_PIN_LD22 = _MXC_BUILD_GPIO_PIN(2, 28, 0x208, 0x66C),
+ MX35_PIN_LD23 = _MXC_BUILD_GPIO_PIN(2, 29, 0x20C, 0x670),
+
+ MX35_PIN_D3_HSYNC = _MXC_BUILD_GPIO_PIN(2, 30, 0x210, 0x674),
+ MX35_PIN_D3_FPSHIFT = _MXC_BUILD_GPIO_PIN(2, 31, 0x214, 0x678),
+ MX35_PIN_D3_DRDY = _MXC_BUILD_GPIO_PIN(0, 0, 0x218, 0x67C),
+ MX35_PIN_CONTRAST = _MXC_BUILD_GPIO_PIN(0, 1, 0x21C, 0x680),
+ MX35_PIN_D3_VSYNC = _MXC_BUILD_GPIO_PIN(0, 2, 0x220, 0x684),
+ MX35_PIN_D3_REV = _MXC_BUILD_GPIO_PIN(0, 3, 0x224, 0x688),
+ MX35_PIN_D3_CLS = _MXC_BUILD_GPIO_PIN(0, 4, 0x228, 0x68C),
+ MX35_PIN_D3_SPL = _MXC_BUILD_GPIO_PIN(0, 5, 0x22C, 0x690),
+
+ MX35_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 6, 0x230, 0x694),
+ MX35_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 7, 0x234, 0x698),
+ MX35_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 8, 0x238, 0x69C),
+ MX35_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 9, 0x23C, 0x6A0),
+ MX35_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 10, 0x240, 0x6A4),
+ MX35_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 11, 0x244, 0x6A8),
+ MX35_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(1, 0, 0x248, 0x6AC),
+ MX35_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(1, 1, 0x24C, 0x6B0),
+ MX35_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(1, 2, 0x250, 0x6B4),
+ MX35_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(1, 3, 0x254, 0x6B8),
+ MX35_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(1, 4, 0x258, 0x6BC),
+ MX35_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(1, 5, 0x25C, 0x6C0),
+
+ MX35_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(1, 6, 0x260, 0x6C4),
+ MX35_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(1, 7, 0x264, 0x6C8),
+ MX35_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(1, 8, 0x268, 0x6CC),
+ MX35_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(1, 9, 0x26C, 0x6D0),
+ MX35_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(1, 10, 0x270, 0x6D4),
+ MX35_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(1, 11, 0x274, 0x6D8),
+ MX35_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(1, 12, 0x278, 0x6DC),
+ MX35_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 13, 0x27C, 0x6E0),
+ MX35_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 14, 0x280, 0x6E4),
+ MX35_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 15, 0x284, 0x6E8),
+ MX35_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 16, 0x288, 0x6EC),
+ MX35_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 17, 0x28C, 0x6F0),
+ MX35_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 18, 0x290, 0x6F4),
+ MX35_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 19, 0x294, 0x6F8),
+ MX35_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 20, 0x298, 0x6FC),
+ MX35_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 21, 0x29C, 0x700),
+ MX35_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 22, 0x2A0, 0x704),
+ MX35_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 23, 0x2A4, 0x708),
+ MX35_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 24, 0x2A8, 0x70C),
+ MX35_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 25, 0x2AC, 0x710),
+ MX35_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 26, 0x2B0, 0x714),
+ MX35_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 27, 0x2B4, 0x718),
+ MX35_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 28, 0x2B8, 0x71C),
+ MX35_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(1, 29, 0x2BC, 0x720),
+ MX35_PIN_ATA_BUFF_EN = _MXC_BUILD_GPIO_PIN(1, 30, 0x2C0, 0x724),
+ MX35_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(1, 31, 0x2C4, 0x728),
+ MX35_PIN_ATA_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 0x2C8, 0x72C),
+ MX35_PIN_ATA_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 0x2CC, 0x730),
+ MX35_PIN_ATA_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 0x2D0, 0x734),
+
+ MX35_PIN_MLB_CLK = _MXC_BUILD_GPIO_PIN(2, 3, 0x2D4, 0x738),
+ MX35_PIN_MLB_DAT = _MXC_BUILD_GPIO_PIN(2, 4, 0x2D8, 0x73C),
+ MX35_PIN_MLB_SIG = _MXC_BUILD_GPIO_PIN(2, 5, 0x2DC, 0x740),
+
+ MX35_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 6, 0x2E0, 0x744),
+ MX35_PIN_FEC_RX_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 0x2E4, 0x748),
+ MX35_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 8, 0x2E8, 0x74C),
+ MX35_PIN_FEC_COL = _MXC_BUILD_GPIO_PIN(2, 9, 0x2EC, 0x750),
+ MX35_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x2F0, 0x754),
+ MX35_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 11, 0x2F4, 0x758),
+ MX35_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 12, 0x2F8, 0x75C),
+ MX35_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 13, 0x2FC, 0x760),
+ MX35_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 14, 0x300, 0x764),
+ MX35_PIN_FEC_TX_ERR = _MXC_BUILD_GPIO_PIN(2, 15, 0x304, 0x768),
+ MX35_PIN_FEC_RX_ERR = _MXC_BUILD_GPIO_PIN(2, 16, 0x308, 0x76C),
+ MX35_PIN_FEC_CRS = _MXC_BUILD_GPIO_PIN(2, 17, 0x30C, 0x770),
+ MX35_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 18, 0x310, 0x774),
+ MX35_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 19, 0x314, 0x778),
+ MX35_PIN_FEC_RDATA2 = _MXC_BUILD_GPIO_PIN(2, 20, 0x318, 0x77C),
+ MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780),
+ MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784),
+ MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788),
+} iomux_pin_name_t;
+
+#endif
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+u32 get_cpu_rev(void);
+#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
+void sdelay(unsigned long);
+
+#endif
#define CLKCTL_CCGR4 0x78
#define CLKCTL_CCGR5 0x7C
#define CLKCTL_CCGR6 0x80
+#if defined(CONFIG_MX53)
+#define CLKCTL_CCGR7 0x84
+#define CLKCTL_CMEOR 0x88
+#elif defined(CONFIG_MX51)
#define CLKCTL_CMEOR 0x84
+#endif
/* DPLL */
#define PLL_DP_CTL 0x00
* MA 02111-1307 USA
*/
-#ifndef __ASM_ARCH_MXC_MX51_H__
-#define __ASM_ARCH_MXC_MX51_H__
+#ifndef __ASM_ARCH_MX5_IMX_REGS_H__
+#define __ASM_ARCH_MX5_IMX_REGS_H__
-/*
- * IRAM
- */
+#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
-#define IRAM_SIZE 0x00020000 /* 128 KB */
-/*
- * Graphics Memory of GPU
- */
-#define GPU_BASE_ADDR 0x20000000
-#define GPU_CTRL_BASE_ADDR 0x30000000
#define IPU_CTRL_BASE_ADDR 0x40000000
-/*
- * Debug
- */
-#define DEBUG_BASE_ADDR 0x60000000
-#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
-#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
-#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
-#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
-#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
-#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
-#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
-#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
+#define SPBA0_BASE_ADDR 0x70000000
+#define AIPS1_BASE_ADDR 0x73F00000
+#define AIPS2_BASE_ADDR 0x83F00000
+#define CSD0_BASE_ADDR 0x90000000
+#define CSD1_BASE_ADDR 0xA0000000
+#define NFC_BASE_ADDR_AXI 0xCFFF0000
+#elif defined(CONFIG_MX53)
+#define IPU_CTRL_BASE_ADDR 0x18000000
+#define SPBA0_BASE_ADDR 0x50000000
+#define AIPS1_BASE_ADDR 0x53F00000
+#define AIPS2_BASE_ADDR 0x63F00000
+#define CSD0_BASE_ADDR 0x70000000
+#define CSD1_BASE_ADDR 0xB0000000
+#define NFC_BASE_ADDR_AXI 0xF7FF0000
+#define IRAM_BASE_ADDR 0xF8000000
+#else
+#error "CPU_TYPE not defined"
+#endif
+
+#define IRAM_SIZE 0x00020000 /* 128 KB */
/*
* SPBA global module enabled #0
*/
-#define SPBA0_BASE_ADDR 0x70000000
-
#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
/*
* AIPS 1
*/
-#define AIPS1_BASE_ADDR 0x73F00000
-
#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
+#if defined(CONFIG_MX53)
+#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
+#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
+#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
+#endif
/*
* AIPS 2
*/
-#define AIPS2_BASE_ADDR 0x83F00000
-
#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
-#define TZIC_BASE_ADDR 0x8FFFC000
-
-/*
- * Memory regions and CS
- */
-#define CSD0_BASE_ADDR 0x90000000
-#define CSD1_BASE_ADDR 0xA0000000
-#define CS0_BASE_ADDR 0xB0000000
-#define CS1_BASE_ADDR 0xB8000000
-#define CS2_BASE_ADDR 0xC0000000
-#define CS3_BASE_ADDR 0xC8000000
-#define CS4_BASE_ADDR 0xCC000000
-#define CS5_BASE_ADDR 0xCE000000
-
/*
- * NFC
- */
-#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */
-
-/*!
- * Number of GPIO port as defined in the IC Spec
- */
-#define GPIO_PORT_NUM 4
-/*!
* Number of GPIO pins per port
*/
#define GPIO_NUM_PIN 32
u32 simr;
};
+/* CSPI registers */
+struct cspi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 ctrl;
+ u32 cfg;
+ u32 intr;
+ u32 dma;
+ u32 stat;
+ u32 period;
+};
+
struct iim_regs {
u32 stat;
u32 statm;
#endif /* __ASSEMBLER__*/
-#endif /* __ASM_ARCH_MXC_MX51_H__ */
+#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */
PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */
} iomux_pad_config_t;
-/* various IOMUX input select register index */
-typedef enum iomux_input_select {
- MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
- MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
- MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
- MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
- MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT,
- /* TO2 */
- MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
- MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
- MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
- MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
- MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
- /* TO2 */
- MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
- MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
- MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
- MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
- MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
- MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
- MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
- MUX_IN_FEC_FEC_COL_SELECT_INPUT,
- MUX_IN_FEC_FEC_CRS_SELECT_INPUT,
- MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT,
- MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
- MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
- MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
- MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
- /* TO2 */
- MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
- MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
- MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
- /* TO2 */
- MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
- /* TO2 */
- MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
- MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
- MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
- MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
- MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
- MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
-
- MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
-
- MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
-
- MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
- MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
- MUX_INPUT_NUM_MUX,
-} iomux_input_select_t;
-
/* various IOMUX input functions */
typedef enum iomux_input_config {
INPUT_CTL_PATH0 = 0x0,
#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
-#define NON_MUX_I PIN_TO_MUX_MASK
+#define NON_MUX_I PIN_TO_MUX_MASK
+#define NON_PAD_I PIN_TO_PAD_MASK
+
+#if defined(CONFIG_MX51)
#define MUX_I_START 0x001C
#define PAD_I_START 0x3F0
#define INPUT_CTL_START 0x8C4
-#define INPUT_CTL_START_TO1 0x928
#define MUX_I_END (PAD_I_START - 4)
+#elif defined(CONFIG_MX53)
+#define MUX_I_START 0x0020
+#define PAD_I_START 0x348
+#define INPUT_CTL_START 0x730
+#define MUX_I_END (PAD_I_START - 4)
+#else
+#error "CPU_TYPE not defined"
+#endif
#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
* "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
* value is constructed based on the rules described above.
*/
-enum iomux_pins {
+enum {
MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
};
+enum {
+ MX53_PIN_GPIO_19 = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348),
+ MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C),
+ MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350),
+ MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354),
+ MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358),
+ MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C),
+ MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360),
+ MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364),
+ MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368),
+ MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C),
+ MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370),
+ MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374),
+ MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378),
+ MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C),
+ MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380),
+ MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384),
+ MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388),
+ MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C),
+ MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390),
+ MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394),
+ MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398),
+ MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C),
+ MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0),
+ MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4),
+ MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8),
+ MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC),
+ MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0),
+ MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4),
+ MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8),
+ MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC),
+ MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0),
+ MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4),
+ MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8),
+ MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC),
+ MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0),
+ MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4),
+ MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8),
+ MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC),
+ MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0),
+ MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4),
+ MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8),
+ MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC),
+ MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0),
+ MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4),
+ MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8),
+ MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC),
+ MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400),
+ MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404),
+ MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408),
+ MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C),
+ MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410),
+ MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414),
+ MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418),
+ MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C),
+ MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420),
+ MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424),
+ MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428),
+ MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C),
+ MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430),
+ MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434),
+ MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438),
+ MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C),
+ MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440),
+ MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444),
+ MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448),
+ MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C),
+ MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450),
+ MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454),
+ MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458),
+ MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C),
+ MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460),
+ MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464),
+ MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468),
+ MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C),
+ MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470),
+ MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474),
+ MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478),
+ MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C),
+ MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480),
+ MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484),
+ MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488),
+ MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C),
+ MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490),
+ MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494),
+ MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498),
+ MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C),
+ MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0),
+ MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4),
+ MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8),
+ MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC),
+ MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0),
+ MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4),
+ MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8),
+ MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC),
+ MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0),
+ MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4),
+ MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8),
+ MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC),
+ MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0),
+ MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4),
+ MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8),
+ MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC),
+ MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0),
+ MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4),
+ MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8),
+ MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC),
+ MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0),
+ MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4),
+ MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8),
+ MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC),
+ MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500),
+ MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504),
+ MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508),
+ MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C),
+ MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510),
+ MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514),
+ MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518),
+ MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C),
+ MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520),
+ MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524),
+ MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528),
+ MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C),
+ MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530),
+ MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534),
+ MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538),
+ MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C),
+ MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I),
+ MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I),
+ MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I),
+ MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I),
+ MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I),
+ MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I),
+ MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I),
+ MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I),
+ MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I),
+ MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I),
+ MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540),
+ MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544),
+ MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548),
+ MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C),
+ MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550),
+ MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554),
+ MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558),
+ MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C),
+ MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560),
+ MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564),
+ MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568),
+ MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C),
+ MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570),
+ MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574),
+ MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578),
+ MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C),
+ MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580),
+ MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584),
+ MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588),
+ MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C),
+ MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590),
+ MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594),
+ MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598),
+ MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C),
+ MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0),
+ MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4),
+ MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8),
+ MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC),
+ MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0),
+ MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4),
+ MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8),
+ MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC),
+ MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0),
+ MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4),
+ MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8),
+ MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC),
+ MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0),
+ MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4),
+ MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8),
+ MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC),
+ MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0),
+ MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4),
+ MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8),
+ MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC),
+ MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0),
+ MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4),
+ MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8),
+ MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC),
+ MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600),
+ MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604),
+ MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608),
+ MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C),
+ MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610),
+ MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614),
+ MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618),
+ MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C),
+ MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620),
+ MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624),
+ MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628),
+ MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C),
+ MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630),
+ MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634),
+ MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638),
+ MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C),
+ MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640),
+ MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644),
+ MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648),
+ MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C),
+ MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650),
+ MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654),
+ MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658),
+ MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C),
+ MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660),
+ MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664),
+ MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668),
+ MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C),
+ MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670),
+ MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674),
+ MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678),
+ MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C),
+ MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680),
+ MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684),
+ MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688),
+ MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C),
+ MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690),
+ MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694),
+ MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698),
+ MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C),
+ MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0),
+ MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4),
+ MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8),
+ MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC),
+ MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0),
+ MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4),
+ MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8),
+ MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC),
+ MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0),
+ MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4),
+ MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8),
+ MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC),
+ MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0),
+ MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4),
+ MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8),
+ MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC),
+ MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0),
+ MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4),
+ MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8),
+ MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC),
+ MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0),
+ MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4),
+ MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC),
+ MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708),
+ MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C),
+ MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710),
+ MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714),
+ MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718),
+ MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C),
+ MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720),
+ MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724),
+ MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728),
+ MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C),
+};
+/* various IOMUX input select register index */
+typedef enum iomux_input_select {
+ MX51_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
+ MX51_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
+ MX51_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
+ MX51_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
+ MX51_CCM_IPP_DI_CLK_SELECT_INPUT,
+ /* TO2 */
+ MX51_CCM_IPP_DI1_CLK_SELECT_INPUT,
+ MX51_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
+ MX51_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
+ MX51_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
+ MX51_CSPI_IPP_IND_MISO_SELECT_INPUT,
+ MX51_CSPI_IPP_IND_MOSI_SELECT_INPUT,
+ MX51_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
+ MX51_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
+ MX51_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
+ MX51_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
+ /* TO2 */
+ MX51_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
+ MX51_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
+ MX51_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
+ MX51_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
+ MX51_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
+ MX51_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
+ MX51_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
+ MX51_FEC_FEC_COL_SELECT_INPUT,
+ MX51_FEC_FEC_CRS_SELECT_INPUT,
+ MX51_FEC_FEC_MDI_SELECT_INPUT,
+ MX51_FEC_FEC_RDATA_0_SELECT_INPUT,
+ MX51_FEC_FEC_RDATA_1_SELECT_INPUT,
+ MX51_FEC_FEC_RDATA_2_SELECT_INPUT,
+ MX51_FEC_FEC_RDATA_3_SELECT_INPUT,
+ MX51_FEC_FEC_RX_CLK_SELECT_INPUT,
+ MX51_FEC_FEC_RX_DV_SELECT_INPUT,
+ MX51_FEC_FEC_RX_ER_SELECT_INPUT,
+ MX51_FEC_FEC_TX_CLK_SELECT_INPUT,
+ MX51_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
+ MX51_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
+ MX51_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
+ MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
+ MX51_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
+ MX51_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
+ MX51_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
+ MX51_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
+ /* TO2 */
+ MX51_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
+ MX51_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
+ MX51_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
+ /* TO2 */
+ MX51_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
+ /* TO2 */
+ MX51_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
+ MX51_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
+ MX51_I2C1_IPP_SCL_IN_SELECT_INPUT,
+ MX51_I2C1_IPP_SDA_IN_SELECT_INPUT,
+ MX51_I2C2_IPP_SCL_IN_SELECT_INPUT,
+ MX51_I2C2_IPP_SDA_IN_SELECT_INPUT,
+ MX51_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
+ MX51_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
+ MX51_KPP_IPP_IND_COL_6_SELECT_INPUT,
+ MX51_KPP_IPP_IND_COL_7_SELECT_INPUT,
+ MX51_KPP_IPP_IND_ROW_4_SELECT_INPUT,
+ MX51_KPP_IPP_IND_ROW_5_SELECT_INPUT,
+ MX51_KPP_IPP_IND_ROW_6_SELECT_INPUT,
+ MX51_KPP_IPP_IND_ROW_7_SELECT_INPUT,
+ MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
+ MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MX51_UART2_IPP_UART_RTS_B_SELECT_INPUT,
+ MX51_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MX51_UART3_IPP_UART_RTS_B_SELECT_INPUT,
+ MX51_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
+ MX51PUT_NUM_MUX,
+ /* MX53 */
+ MX53_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
+ MX53_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
+ MX53_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MX53_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
+ MX53_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MX53_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
+ MX53_AUDMUX_P5_INPUT_DA_AMX_SELECT_I,
+ MX53_AUDMUX_P5_INPUT_DB_AMX_SELECT_I,
+ MX53_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MX53_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT,
+ MX53_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MX53_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
+ MX53_CAN1_IPP_IND_CANRX_SELECT_INPUT,
+ MX53_CAN2_IPP_IND_CANRX_SELECT_INPUT,
+ MX53_CCM_IPP_ASRC_EXT_SELECT_INPUT,
+ MX53_CCM_IPP_DI1_CLK_SELECT_INPUT,
+ MX53_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
+ MX53_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
+ MX53_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
+ MX53_CCM_PLL4_BYPASS_CLK_SELECT_INPUT,
+ MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
+ MX53_CSPI_IPP_IND_MISO_SELECT_INPUT,
+ MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT,
+ MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
+ MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
+ MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
+ MX53_CSPI_IPP_IND_SS_B_4_SELECT_INPUT,
+ MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
+ MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
+ MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
+ MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
+ MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
+ MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT,
+ MX53_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT,
+ MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
+ MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
+ MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
+ MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
+ MX53_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_FST_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_SCKT_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
+ MX53_ESDHC1_IPP_WP_ON_SELECT_INPUT,
+ MX53_FEC_FEC_COL_SELECT_INPUT,
+ MX53_FEC_FEC_MDI_SELECT_INPUT,
+ MX53_FEC_FEC_RX_CLK_SELECT_INPUT,
+ MX53_FIRI_IPP_IND_RXD_SELECT_INPUT,
+ MX53_GPC_PMIC_RDY_SELECT_INPUT,
+ MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
+ MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
+ MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
+ MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
+ MX53_I2C3_IPP_SCL_IN_SELECT_INPUT,
+ MX53_I2C3_IPP_SDA_IN_SELECT_INPUT,
+ MX53_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
+ MX53_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
+ MX53_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
+ MX53_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT,
+ MX53_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT,
+ MX53_KPP_IPP_IND_COL_5_SELECT_INPUT,
+ MX53_KPP_IPP_IND_COL_6_SELECT_INPUT,
+ MX53_KPP_IPP_IND_COL_7_SELECT_INPUT,
+ MX53_KPP_IPP_IND_ROW_5_SELECT_INPUT,
+ MX53_KPP_IPP_IND_ROW_6_SELECT_INPUT,
+ MX53_KPP_IPP_IND_ROW_7_SELECT_INPUT,
+ MX53_MLB_MLBCLK_IN_SELECT_INPUT,
+ MX53_MLB_MLBDAT_IN_SELECT_INPUT,
+ MX53_MLB_MLBSIG_IN_SELECT_INPUT,
+ MX53_OWIRE_BATTERY_LINE_IN_SELECT_INPUT,
+ MX53_SDMA_EVENTS_14_SELECT_INPUT,
+ MX53_SDMA_EVENTS_15_SELECT_INPUT,
+ MX53_SPDIF_SPDIF_IN1_SELECT_INPUT,
+ MX53_UART1_IPP_UART_RTS_B_SELECT_INPUT,
+ MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MX53_UART2_IPP_UART_RTS_B_SELECT_INPUT,
+ MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MX53_UART3_IPP_UART_RTS_B_SELECT_INPUT,
+ MX53_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MX53_UART4_IPP_UART_RTS_B_SELECT_INPUT,
+ MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MX53_UART5_IPP_UART_RTS_B_SELECT_INPUT,
+ MX53_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT,
+ MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT,
+ MX53_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT,
+} iomux_input_select_t;
+
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */
#define HPLL 3
#define VPLL 4
-void s5p_clock_init(void);
-
-extern unsigned long (*get_pll_clk)(int pllreg);
-extern unsigned long (*get_arm_clk)(void);
-extern unsigned long (*get_pwm_clk)(void);
-extern unsigned long (*get_uart_clk)(int dev_index);
+unsigned long get_pll_clk(int pllreg);
+unsigned long get_arm_clk(void);
+unsigned long get_pwm_clk(void);
+unsigned long get_uart_clk(int dev_index);
#endif
unsigned char res3[0x3d0];
};
-static int use_divslot = 1;
+static inline int s5p_uart_divslot(void)
+{
+ return 1;
+}
#endif /* __ASSEMBLY__ */
--- /dev/null
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * MyungJoo Ham <myungjoo.ham@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_ADC_H_
+#define __ASM_ARM_ARCH_ADC_H_
+
+#ifndef __ASSEMBLY__
+struct s5p_adc {
+ unsigned int adccon;
+ unsigned int adctsc;
+ unsigned int adcdly;
+ unsigned int adcdat0;
+ unsigned int adcdat1;
+ unsigned int adcupdn;
+ unsigned int adcclrint;
+ unsigned int adcmux;
+ unsigned int adcclrintpndnup;
+};
+#endif
+
+#endif /* __ASM_ARM_ARCH_ADC_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_CLK_H_
+#define __ASM_ARM_ARCH_CLK_H_
+
+#define APLL 0
+#define MPLL 1
+#define EPLL 2
+#define HPLL 3
+#define VPLL 4
+
+unsigned long get_pll_clk(int pllreg);
+unsigned long get_arm_clk(void);
+unsigned long get_pwm_clk(void);
+unsigned long get_uart_clk(int dev_index);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_CLOCK_H_
+#define __ASM_ARM_ARCH_CLOCK_H_
+
+#ifndef __ASSEMBLY__
+struct s5pc210_clock {
+ unsigned char res1[0x4200];
+ unsigned int src_leftbus;
+ unsigned char res2[0x1fc];
+ unsigned int mux_stat_leftbus;
+ unsigned char res4[0xfc];
+ unsigned int div_leftbus;
+ unsigned char res5[0xfc];
+ unsigned int div_stat_leftbus;
+ unsigned char res6[0x1fc];
+ unsigned int gate_ip_leftbus;
+ unsigned char res7[0x1fc];
+ unsigned int clkout_leftbus;
+ unsigned int clkout_leftbus_div_stat;
+ unsigned char res8[0x37f8];
+ unsigned int src_rightbus;
+ unsigned char res9[0x1fc];
+ unsigned int mux_stat_rightbus;
+ unsigned char res10[0xfc];
+ unsigned int div_rightbus;
+ unsigned char res11[0xfc];
+ unsigned int div_stat_rightbus;
+ unsigned char res12[0x1fc];
+ unsigned int gate_ip_rightbus;
+ unsigned char res13[0x1fc];
+ unsigned int clkout_rightbus;
+ unsigned int clkout_rightbus_div_stat;
+ unsigned char res14[0x3608];
+ unsigned int epll_lock;
+ unsigned char res15[0xc];
+ unsigned int vpll_lock;
+ unsigned char res16[0xec];
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned char res17[0x8];
+ unsigned int vpll_con0;
+ unsigned int vpll_con1;
+ unsigned char res18[0xe8];
+ unsigned int src_top0;
+ unsigned int src_top1;
+ unsigned char res19[0x8];
+ unsigned int src_cam;
+ unsigned int src_tv;
+ unsigned int src_mfc;
+ unsigned int src_g3d;
+ unsigned int src_image;
+ unsigned int src_lcd0;
+ unsigned int src_lcd1;
+ unsigned int src_maudio;
+ unsigned int src_fsys;
+ unsigned char res20[0xc];
+ unsigned int src_peril0;
+ unsigned int src_peril1;
+ unsigned char res21[0xb8];
+ unsigned int src_mask_top;
+ unsigned char res22[0xc];
+ unsigned int src_mask_cam;
+ unsigned int src_mask_tv;
+ unsigned char res23[0xc];
+ unsigned int src_mask_lcd0;
+ unsigned int src_mask_lcd1;
+ unsigned int src_mask_maudio;
+ unsigned int src_mask_fsys;
+ unsigned char res24[0xc];
+ unsigned int src_mask_peril0;
+ unsigned int src_mask_peril1;
+ unsigned char res25[0xb8];
+ unsigned int mux_stat_top;
+ unsigned char res26[0x14];
+ unsigned int mux_stat_mfc;
+ unsigned int mux_stat_g3d;
+ unsigned int mux_stat_image;
+ unsigned char res27[0xdc];
+ unsigned int div_top;
+ unsigned char res28[0xc];
+ unsigned int div_cam;
+ unsigned int div_tv;
+ unsigned int div_mfc;
+ unsigned int div_g3d;
+ unsigned int div_image;
+ unsigned int div_lcd0;
+ unsigned int div_lcd1;
+ unsigned int div_maudio;
+ unsigned int div_fsys0;
+ unsigned int div_fsys1;
+ unsigned int div_fsys2;
+ unsigned int div_fsys3;
+ unsigned int div_peril0;
+ unsigned int div_peril1;
+ unsigned int div_peril2;
+ unsigned int div_peril3;
+ unsigned int div_peril4;
+ unsigned int div_peril5;
+ unsigned char res29[0x18];
+ unsigned int div2_ratio;
+ unsigned char res30[0x8c];
+ unsigned int div_stat_top;
+ unsigned char res31[0xc];
+ unsigned int div_stat_cam;
+ unsigned int div_stat_tv;
+ unsigned int div_stat_mfc;
+ unsigned int div_stat_g3d;
+ unsigned int div_stat_image;
+ unsigned int div_stat_lcd0;
+ unsigned int div_stat_lcd1;
+ unsigned int div_stat_maudio;
+ unsigned int div_stat_fsys0;
+ unsigned int div_stat_fsys1;
+ unsigned int div_stat_fsys2;
+ unsigned int div_stat_fsys3;
+ unsigned int div_stat_peril0;
+ unsigned int div_stat_peril1;
+ unsigned int div_stat_peril2;
+ unsigned int div_stat_peril3;
+ unsigned int div_stat_peril4;
+ unsigned int div_stat_peril5;
+ unsigned char res32[0x18];
+ unsigned int div2_stat;
+ unsigned char res33[0x29c];
+ unsigned int gate_ip_cam;
+ unsigned int gate_ip_tv;
+ unsigned int gate_ip_mfc;
+ unsigned int gate_ip_g3d;
+ unsigned int gate_ip_image;
+ unsigned int gate_ip_lcd0;
+ unsigned int gate_ip_lcd1;
+ unsigned char res34[0x4];
+ unsigned int gate_ip_fsys;
+ unsigned char res35[0x8];
+ unsigned int gate_ip_gps;
+ unsigned int gate_ip_peril;
+ unsigned char res36[0xc];
+ unsigned int gate_ip_perir;
+ unsigned char res37[0xc];
+ unsigned int gate_block;
+ unsigned char res38[0x8c];
+ unsigned int clkout_cmu_top;
+ unsigned int clkout_cmu_top_div_stat;
+ unsigned char res39[0x37f8];
+ unsigned int src_dmc;
+ unsigned char res40[0xfc];
+ unsigned int src_mask_dmc;
+ unsigned char res41[0xfc];
+ unsigned int mux_stat_dmc;
+ unsigned char res42[0xfc];
+ unsigned int div_dmc0;
+ unsigned int div_dmc1;
+ unsigned char res43[0xf8];
+ unsigned int div_stat_dmc0;
+ unsigned int div_stat_dmc1;
+ unsigned char res44[0x2f8];
+ unsigned int gate_ip_dmc;
+ unsigned char res45[0xfc];
+ unsigned int clkout_cmu_dmc;
+ unsigned int clkout_cmu_dmc_div_stat;
+ unsigned char res46[0x5f8];
+ unsigned int dcgidx_map0;
+ unsigned int dcgidx_map1;
+ unsigned int dcgidx_map2;
+ unsigned char res47[0x14];
+ unsigned int dcgperf_map0;
+ unsigned int dcgperf_map1;
+ unsigned char res48[0x18];
+ unsigned int dvcidx_map;
+ unsigned char res49[0x1c];
+ unsigned int freq_cpu;
+ unsigned int freq_dpm;
+ unsigned char res50[0x18];
+ unsigned int dvsemclk_en;
+ unsigned int maxperf;
+ unsigned char res51[0x2f78];
+ unsigned int apll_lock;
+ unsigned char res52[0x4];
+ unsigned int mpll_lock;
+ unsigned char res53[0xf4];
+ unsigned int apll_con0;
+ unsigned int apll_con1;
+ unsigned int mpll_con0;
+ unsigned int mpll_con1;
+ unsigned char res54[0xf0];
+ unsigned int src_cpu;
+ unsigned char res55[0x1fc];
+ unsigned int mux_stat_cpu;
+ unsigned char res56[0xfc];
+ unsigned int div_cpu0;
+ unsigned int div_cpu1;
+ unsigned char res57[0xf8];
+ unsigned int div_stat_cpu0;
+ unsigned int div_stat_cpu1;
+ unsigned char res58[0x3f8];
+ unsigned int clkout_cmu_cpu;
+ unsigned int clkout_cmu_cpu_div_stat;
+ unsigned char res59[0x5f8];
+ unsigned int armclk_stopctrl;
+ unsigned int atclk_stopctrl;
+ unsigned char res60[0x8];
+ unsigned int parityfail_status;
+ unsigned int parityfail_clear;
+ unsigned char res61[0xe8];
+ unsigned int apll_con0_l8;
+ unsigned int apll_con0_l7;
+ unsigned int apll_con0_l6;
+ unsigned int apll_con0_l5;
+ unsigned int apll_con0_l4;
+ unsigned int apll_con0_l3;
+ unsigned int apll_con0_l2;
+ unsigned int apll_con0_l1;
+ unsigned int iem_control;
+ unsigned char res62[0xdc];
+ unsigned int apll_con1_l8;
+ unsigned int apll_con1_l7;
+ unsigned int apll_con1_l6;
+ unsigned int apll_con1_l5;
+ unsigned int apll_con1_l4;
+ unsigned int apll_con1_l3;
+ unsigned int apll_con1_l2;
+ unsigned int apll_con1_l1;
+ unsigned char res63[0xe0];
+ unsigned int div_iem_l8;
+ unsigned int div_iem_l7;
+ unsigned int div_iem_l6;
+ unsigned int div_iem_l5;
+ unsigned int div_iem_l4;
+ unsigned int div_iem_l3;
+ unsigned int div_iem_l2;
+ unsigned int div_iem_l1;
+};
+#endif
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _S5PC2XX_CPU_H
+#define _S5PC2XX_CPU_H
+
+#define S5PC2XX_ADDR_BASE 0x10000000
+
+/* S5PC210 */
+#define S5PC210_GPIO_PART3_BASE 0x03860000
+#define S5PC210_PRO_ID 0x10000000
+#define S5PC210_POWER_BASE 0x10020000
+#define S5PC210_SWRESET 0x10020400
+#define S5PC210_CLOCK_BASE 0x10030000
+#define S5PC210_SYSTIMER_BASE 0x10050000
+#define S5PC210_WATCHDOG_BASE 0x10060000
+#define S5PC210_MIU_BASE 0x10600000
+#define S5PC210_DMC0_BASE 0x10400000
+#define S5PC210_DMC1_BASE 0x10410000
+#define S5PC210_GPIO_PART2_BASE 0x11000000
+#define S5PC210_GPIO_PART1_BASE 0x11400000
+#define S5PC210_FIMD_BASE 0x11C00000
+#define S5PC210_USBOTG_BASE 0x12480000
+#define S5PC210_MMC_BASE 0x12510000
+#define S5PC210_SROMC_BASE 0x12570000
+#define S5PC210_USBPHY_BASE 0x125B0000
+#define S5PC210_UART_BASE 0x13800000
+#define S5PC210_ADC_BASE 0x13910000
+#define S5PC210_PWMTIMER_BASE 0x139D0000
+#define S5PC210_MODEM_BASE 0x13A00000
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+/* CPU detection macros */
+extern unsigned int s5p_cpu_id;
+
+static inline void s5p_set_cpu_id(void)
+{
+ s5p_cpu_id = readl(S5PC210_PRO_ID);
+ s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
+
+ /*
+ * 0xC200: S5PC210 EVT0
+ * 0xC210: S5PC210 EVT1
+ */
+ if (s5p_cpu_id == 0xC200)
+ s5p_cpu_id |= 0x10;
+}
+
+#define IS_SAMSUNG_TYPE(type, id) \
+static inline int cpu_is_##type(void) \
+{ \
+ return s5p_cpu_id == id ? 1 : 0; \
+}
+
+IS_SAMSUNG_TYPE(s5pc210, 0xc210)
+
+#define SAMSUNG_BASE(device, base) \
+static inline unsigned int samsung_get_base_##device(void) \
+{ \
+ if (cpu_is_s5pc210()) \
+ return S5PC210_##base; \
+ else \
+ return 0; \
+}
+
+SAMSUNG_BASE(adc, ADC_BASE)
+SAMSUNG_BASE(clock, CLOCK_BASE)
+SAMSUNG_BASE(fimd, FIMD_BASE)
+SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
+SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
+SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
+SAMSUNG_BASE(pro_id, PRO_ID)
+SAMSUNG_BASE(mmc, MMC_BASE)
+SAMSUNG_BASE(modem, MODEM_BASE)
+SAMSUNG_BASE(sromc, SROMC_BASE)
+SAMSUNG_BASE(swreset, SWRESET)
+SAMSUNG_BASE(timer, PWMTIMER_BASE)
+SAMSUNG_BASE(uart, UART_BASE)
+SAMSUNG_BASE(usb_phy, USBPHY_BASE)
+SAMSUNG_BASE(usb_otg, USBOTG_BASE)
+SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
+#endif
+
+#endif /* _S5PC2XX_CPU_H */
--- /dev/null
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#ifndef __ASSEMBLY__
+struct s5p_gpio_bank {
+ unsigned int con;
+ unsigned int dat;
+ unsigned int pull;
+ unsigned int drv;
+ unsigned int pdn_con;
+ unsigned int pdn_pull;
+ unsigned char res1[8];
+};
+
+struct s5pc210_gpio_part1 {
+ struct s5p_gpio_bank a0;
+ struct s5p_gpio_bank a1;
+ struct s5p_gpio_bank b;
+ struct s5p_gpio_bank c0;
+ struct s5p_gpio_bank c1;
+ struct s5p_gpio_bank d0;
+ struct s5p_gpio_bank d1;
+ struct s5p_gpio_bank e0;
+ struct s5p_gpio_bank e1;
+ struct s5p_gpio_bank e2;
+ struct s5p_gpio_bank e3;
+ struct s5p_gpio_bank e4;
+ struct s5p_gpio_bank f0;
+ struct s5p_gpio_bank f1;
+ struct s5p_gpio_bank f2;
+ struct s5p_gpio_bank f3;
+};
+
+struct s5pc210_gpio_part2 {
+ struct s5p_gpio_bank j0;
+ struct s5p_gpio_bank j1;
+ struct s5p_gpio_bank k0;
+ struct s5p_gpio_bank k1;
+ struct s5p_gpio_bank k2;
+ struct s5p_gpio_bank k3;
+ struct s5p_gpio_bank l0;
+ struct s5p_gpio_bank l1;
+ struct s5p_gpio_bank l2;
+ struct s5p_gpio_bank y0;
+ struct s5p_gpio_bank y1;
+ struct s5p_gpio_bank y2;
+ struct s5p_gpio_bank y3;
+ struct s5p_gpio_bank y4;
+ struct s5p_gpio_bank y5;
+ struct s5p_gpio_bank y6;
+ struct s5p_gpio_bank res1[80];
+ struct s5p_gpio_bank x0;
+ struct s5p_gpio_bank x1;
+ struct s5p_gpio_bank x2;
+ struct s5p_gpio_bank x3;
+};
+
+struct s5pc210_gpio_part3 {
+ struct s5p_gpio_bank z;
+};
+
+/* functions */
+void gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
+void gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
+void gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
+void gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
+unsigned int gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
+void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
+void gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
+void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
+#endif
+
+/* Pin configurations */
+#define GPIO_INPUT 0x0
+#define GPIO_OUTPUT 0x1
+#define GPIO_IRQ 0xf
+#define GPIO_FUNC(x) (x)
+
+/* Pull mode */
+#define GPIO_PULL_NONE 0x0
+#define GPIO_PULL_DOWN 0x1
+#define GPIO_PULL_UP 0x2
+
+/* Drive Strength level */
+#define GPIO_DRV_1X 0x0
+#define GPIO_DRV_2X 0x1
+#define GPIO_DRV_3X 0x2
+#define GPIO_DRV_4X 0x3
+#define GPIO_DRV_FAST 0x0
+#define GPIO_DRV_SLOW 0x1
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_MMC_H_
+#define __ASM_ARCH_MMC_H_
+
+#ifndef __ASSEMBLY__
+struct s5p_mmc {
+ unsigned int sysad;
+ unsigned short blksize;
+ unsigned short blkcnt;
+ unsigned int argument;
+ unsigned short trnmod;
+ unsigned short cmdreg;
+ unsigned int rspreg0;
+ unsigned int rspreg1;
+ unsigned int rspreg2;
+ unsigned int rspreg3;
+ unsigned int bdata;
+ unsigned int prnsts;
+ unsigned char hostctl;
+ unsigned char pwrcon;
+ unsigned char blkgap;
+ unsigned char wakcon;
+ unsigned short clkcon;
+ unsigned char timeoutcon;
+ unsigned char swrst;
+ unsigned int norintsts; /* errintsts */
+ unsigned int norintstsen; /* errintstsen */
+ unsigned int norintsigen; /* errintsigen */
+ unsigned short acmd12errsts;
+ unsigned char res1[2];
+ unsigned int capareg;
+ unsigned char res2[4];
+ unsigned int maxcurr;
+ unsigned char res3[0x34];
+ unsigned int control2;
+ unsigned int control3;
+ unsigned int control4;
+ unsigned char res4[0x6e];
+ unsigned short hcver;
+ unsigned char res5[0xFF02];
+};
+
+struct mmc_host {
+ struct s5p_mmc *reg;
+ unsigned int version; /* SDHCI spec. version */
+ unsigned int clock; /* Current clock (MHz) */
+};
+
+int s5p_mmc_init(int dev_index, int bus_width);
+
+#endif /* __ASSEMBLY__ */
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_PWM_H_
+#define __ASM_ARM_ARCH_PWM_H_
+
+/* Interval mode(Auto Reload) of PWM Timer 4 */
+#define TCON4_AUTO_RELOAD (1 << 22)
+/* Update TCNTB4 */
+#define TCON4_UPDATE (1 << 21)
+/* start bit of PWM Timer 4 */
+#define TCON4_START (1 << 20)
+
+#ifndef __ASSEMBLY__
+struct s5p_timer {
+ unsigned int tcfg0;
+ unsigned int tcfg1;
+ unsigned int tcon;
+ unsigned int tcntb0;
+ unsigned int tcmpb0;
+ unsigned int tcnto0;
+ unsigned int tcntb1;
+ unsigned int tcmpb1;
+ unsigned int tcnto1;
+ unsigned int tcntb2;
+ unsigned int tcmpb2;
+ unsigned int tcnto2;
+ unsigned int tcntb3;
+ unsigned int res1;
+ unsigned int tcnto3;
+ unsigned int tcntb4;
+ unsigned int tcnto4;
+ unsigned int tintcstat;
+};
+#endif /* __ASSEMBLY__ */
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2010 Samsung Electrnoics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+u32 get_device_type(void);
+void invalidate_dcache(u32);
+void l2_cache_disable(void);
+void l2_cache_enable(void);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_UART_H_
+#define __ASM_ARCH_UART_H_
+
+#ifndef __ASSEMBLY__
+/* baudrate rest value */
+union br_rest {
+ unsigned short slot; /* udivslot */
+ unsigned char value; /* ufracval */
+};
+
+struct s5p_uart {
+ unsigned int ulcon;
+ unsigned int ucon;
+ unsigned int ufcon;
+ unsigned int umcon;
+ unsigned int utrstat;
+ unsigned int uerstat;
+ unsigned int ufstat;
+ unsigned int umstat;
+ unsigned char utxh;
+ unsigned char res1[3];
+ unsigned char urxh;
+ unsigned char res2[3];
+ unsigned int ubrdiv;
+ union br_rest rest;
+ unsigned char res3[0xffd0];
+};
+
+static inline int s5p_uart_divslot(void)
+{
+ return 0;
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif
*buf++ = __arch_getl(addr);
}
-#define __raw_writeb(v,a) __arch_putb(v,a)
-#define __raw_writew(v,a) __arch_putw(v,a)
-#define __raw_writel(v,a) __arch_putl(v,a)
+#define __raw_writeb(v,a) __arch_putb(v,a)
+#define __raw_writew(v,a) __arch_putw(v,a)
+#define __raw_writel(v,a) __arch_putl(v,a)
-#define __raw_readb(a) __arch_getb(a)
-#define __raw_readw(a) __arch_getw(a)
-#define __raw_readl(a) __arch_getl(a)
+#define __raw_readb(a) __arch_getb(a)
+#define __raw_readw(a) __arch_getw(a)
+#define __raw_readl(a) __arch_getl(a)
-#define writeb(v,a) __arch_putb(v,a)
-#define writew(v,a) __arch_putw(v,a)
-#define writel(v,a) __arch_putl(v,a)
+/*
+ * TODO: The kernel offers some more advanced versions of barriers, it might
+ * have some advantages to use them instead of the simple one here.
+ */
+#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#define __iormb() dmb()
+#define __iowmb() dmb()
+
+#define writeb(v,c) ({ __iowmb(); __arch_putb(v,c); v; })
+#define writew(v,c) ({ __iowmb(); __arch_putw(v,c); v; })
+#define writel(v,c) ({ __iowmb(); __arch_putl(v,c); v; })
-#define readb(a) __arch_getb(a)
-#define readw(a) __arch_getw(a)
-#define readl(a) __arch_getl(a)
+#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; })
+#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; })
+#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
/*
* The compiler seems to be incapable of optimising constants
#define MACH_TYPE_U380 2333
#define MACH_TYPE_HUALU_BOARD 2334
#define MACH_TYPE_NPCMX50 2335
-#define MACH_TYPE_MX51_LANGE51 2336
+#define MACH_TYPE_MX51_EFIKAMX 2336
#define MACH_TYPE_MX51_LANGE52 2337
#define MACH_TYPE_RIOM 2338
#define MACH_TYPE_COMCAS 2339
#define MACH_TYPE_CSB732 2367
#define MACH_TYPE_U8500 2368
#define MACH_TYPE_HUQIU 2369
-#define MACH_TYPE_MX51_KUNLUN 2370
+#define MACH_TYPE_MX51_EFIKASB 2370
#define MACH_TYPE_PMT1G 2371
#define MACH_TYPE_HTCELF 2372
#define MACH_TYPE_ARMADILLO420 2373
#define MACH_TYPE_WASABI 2986
#define MACH_TYPE_VIVOW 2987
#define MACH_TYPE_MX50_RDP 2988
-#define MACH_TYPE_UNIVERSAL 2989
+#define MACH_TYPE_UNIVERSAL_C210 2989
#define MACH_TYPE_REAL6410 2990
#define MACH_TYPE_SPX_SAKURA 2991
#define MACH_TYPE_IJ3K_2440 2992
#define MACH_TYPE_MSM8X60_QRDC 3060
#define MACH_TYPE_SPEAR900 3061
#define MACH_TYPE_PCONTROL_G20 3062
+#define MACH_TYPE_RDSTOR 3063
+#define MACH_TYPE_USDLOADER 3064
+#define MACH_TYPE_TSOPLOADER 3065
+#define MACH_TYPE_KRONOS 3066
+#define MACH_TYPE_FFCORE 3067
+#define MACH_TYPE_MONE 3068
+#define MACH_TYPE_UNIT2S 3069
+#define MACH_TYPE_ACER_A5 3070
+#define MACH_TYPE_ETHERPRO_ISP 3071
+#define MACH_TYPE_STRETCHS7000 3072
+#define MACH_TYPE_P87_SMARTSIM 3073
+#define MACH_TYPE_TULIP 3074
+#define MACH_TYPE_SUNFLOWER 3075
+#define MACH_TYPE_RIB 3076
+#define MACH_TYPE_CLOD 3077
+#define MACH_TYPE_RUMP 3078
+#define MACH_TYPE_TENDERLOIN 3079
+#define MACH_TYPE_SHORTLOIN 3080
+#define MACH_TYPE_CRESPO 3081
+#define MACH_TYPE_ANTARES 3082
+#define MACH_TYPE_WB40N 3083
+#define MACH_TYPE_HERRING 3084
+#define MACH_TYPE_NAXY400 3085
+#define MACH_TYPE_NAXY1200 3086
+#define MACH_TYPE_VPR200 3087
+#define MACH_TYPE_BUG20 3088
+#define MACH_TYPE_GOFLEXNET 3089
+#define MACH_TYPE_TORBRECK 3090
+#define MACH_TYPE_SAARB_MG1 3091
+#define MACH_TYPE_CALLISTO 3092
+#define MACH_TYPE_MULTHSU 3093
+#define MACH_TYPE_SALUDA 3094
+#define MACH_TYPE_PEMP_OMAP3_APOLLO 3095
+#define MACH_TYPE_VC0718 3096
+#define MACH_TYPE_MVBLX 3097
+#define MACH_TYPE_INHAND_APEIRON 3098
+#define MACH_TYPE_INHAND_FURY 3099
+#define MACH_TYPE_INHAND_SIREN 3100
+#define MACH_TYPE_HDNVP 3101
+#define MACH_TYPE_SOFTWINNER 3102
+#define MACH_TYPE_PRIMA2_EVB 3103
+#define MACH_TYPE_NAS6210 3104
+#define MACH_TYPE_UNISDEV 3105
+#define MACH_TYPE_SBCA11 3106
+#define MACH_TYPE_SAGA 3107
+#define MACH_TYPE_NS_K330 3108
+#define MACH_TYPE_TANNA 3109
+#define MACH_TYPE_IMATE8502 3110
+#define MACH_TYPE_ASPEN 3111
+#define MACH_TYPE_DAINTREE_CWAC 3112
+#define MACH_TYPE_ZMX25 3113
+#define MACH_TYPE_MAPLE1 3114
+#define MACH_TYPE_QSD8X72_SURF 3115
+#define MACH_TYPE_QSD8X72_FFA 3116
+#define MACH_TYPE_ABILENE 3117
+#define MACH_TYPE_EIGEN_TTR 3118
+#define MACH_TYPE_IOMEGA_IX2_200 3119
+#define MACH_TYPE_CORETEC_VCX7400 3120
+#define MACH_TYPE_SANTIAGO 3121
+#define MACH_TYPE_MX257SOL 3122
+#define MACH_TYPE_STRASBOURG 3123
+#define MACH_TYPE_MSM8X60_FLUID 3124
+#define MACH_TYPE_SMARTQV5 3125
+#define MACH_TYPE_SMARTQV3 3126
+#define MACH_TYPE_SMARTQV7 3127
+#define MACH_TYPE_PAZ00 3128
+#define MACH_TYPE_ACMENETUSFOXG20 3129
+#define MACH_TYPE_HTCWILLOW 3130
+#define MACH_TYPE_FWBD_0404 3131
+#define MACH_TYPE_HDGU 3132
+#define MACH_TYPE_PYRAMID 3133
+#define MACH_TYPE_EPIPHAN 3134
+#define MACH_TYPE_OMAP_BENDER 3135
+#define MACH_TYPE_GURNARD 3136
+#define MACH_TYPE_GTL_IT5100 3137
+#define MACH_TYPE_BCM2708 3138
+#define MACH_TYPE_MX51_GGC 3139
+#define MACH_TYPE_SHARESPACE 3140
+#define MACH_TYPE_HABA_KNX_EXPLORER 3141
+#define MACH_TYPE_SIMTEC_KIRKMOD 3142
+#define MACH_TYPE_CRUX 3143
+#define MACH_TYPE_MX51_BRAVO 3144
+#define MACH_TYPE_CHARON 3145
+#define MACH_TYPE_PICOCOM3 3146
+#define MACH_TYPE_PICOCOM4 3147
+#define MACH_TYPE_SERRANO 3148
+#define MACH_TYPE_DOUBLESHOT 3149
+#define MACH_TYPE_EVSY 3150
+#define MACH_TYPE_HUASHAN 3151
+#define MACH_TYPE_LAUSANNE 3152
+#define MACH_TYPE_EMERALD 3153
+#define MACH_TYPE_TQMA35 3154
+#define MACH_TYPE_MARVEL 3155
+#define MACH_TYPE_MANUAE 3156
+#define MACH_TYPE_CHACHA 3157
+#define MACH_TYPE_LEMON 3158
+#define MACH_TYPE_CSC 3159
+#define MACH_TYPE_GIRA_KNXIP_ROUTER 3160
+#define MACH_TYPE_T20 3161
+#define MACH_TYPE_HDMINI 3162
+#define MACH_TYPE_SCIPHONE_G2 3163
+#define MACH_TYPE_EXPRESS 3164
+#define MACH_TYPE_EXPRESS_KT 3165
+#define MACH_TYPE_MAXIMASP 3166
+#define MACH_TYPE_NITROGEN_IMX51 3167
+#define MACH_TYPE_NITROGEN_IMX53 3168
+#define MACH_TYPE_SUNFIRE 3169
+#define MACH_TYPE_AROWANA 3170
+#define MACH_TYPE_TEGRA_DAYTONA 3171
+#define MACH_TYPE_TEGRA_SWORDFISH 3172
+#define MACH_TYPE_EDISON 3173
+#define MACH_TYPE_SVP8500V1 3174
+#define MACH_TYPE_SVP8500V2 3175
+#define MACH_TYPE_SVP5500 3176
+#define MACH_TYPE_B5500 3177
+#define MACH_TYPE_S5500 3178
+#define MACH_TYPE_ICON 3179
+#define MACH_TYPE_ELEPHANT 3180
+#define MACH_TYPE_MSM8X60_FUSION 3181
+#define MACH_TYPE_SHOOTER 3182
+#define MACH_TYPE_SPADE_LTE 3183
+#define MACH_TYPE_PHILHWANI 3184
+#define MACH_TYPE_GSNCOMM 3185
+#define MACH_TYPE_STRASBOURG_A2 3186
+#define MACH_TYPE_MMM 3187
+#define MACH_TYPE_DAVINCI_DM365_BV 3188
+#define MACH_TYPE_AG5EVM 3189
+#define MACH_TYPE_SC575PLC 3190
+#define MACH_TYPE_SC575IPC 3191
+#define MACH_TYPE_OMAP3_TDM3730 3192
+#define MACH_TYPE_G7 3193
+#define MACH_TYPE_TOP9000_EVAL 3194
+#define MACH_TYPE_TOP9000_SU 3195
+#define MACH_TYPE_UTM300 3196
+#define MACH_TYPE_TSUNAGI 3197
+#define MACH_TYPE_TS75XX 3198
+#define MACH_TYPE_MSM8X60_FUSN_FFA 3199
+#define MACH_TYPE_TS47XX 3200
+#define MACH_TYPE_DA850_K5 3201
+#define MACH_TYPE_AX502 3202
+#define MACH_TYPE_IGEP0032 3203
+#define MACH_TYPE_ANTERO 3204
+#define MACH_TYPE_SYNERGY 3205
+#define MACH_TYPE_ICS_IF_VOIP 3206
+#define MACH_TYPE_WLF_CRAGG_6410 3207
+#define MACH_TYPE_PUNICA 3208
+#define MACH_TYPE_SBC_NT250 3209
+#define MACH_TYPE_MX27_WMULTRA 3210
+#define MACH_TYPE_MACKEREL 3211
+#define MACH_TYPE_FA9X27 3213
+#define MACH_TYPE_NS2816TB 3214
+#define MACH_TYPE_NS2816_NTPAD 3215
+#define MACH_TYPE_NS2816_NTNB 3216
+#define MACH_TYPE_KAEN 3217
+#define MACH_TYPE_NV1000 3218
+#define MACH_TYPE_NUC950TS 3219
+#define MACH_TYPE_NOKIA_RM680 3220
+#define MACH_TYPE_AST2200 3221
+#define MACH_TYPE_LEAD 3222
+#define MACH_TYPE_UNINO1 3223
+#define MACH_TYPE_GREECO 3224
+#define MACH_TYPE_VERDI 3225
+#define MACH_TYPE_DM6446_ADBOX 3226
+#define MACH_TYPE_QUAD_SALSA 3227
+#define MACH_TYPE_ABB_GMA_1_1 3228
+#define MACH_TYPE_SVCID 3229
+#define MACH_TYPE_MSM8960_SIM 3230
+#define MACH_TYPE_MSM8960_RUMI3 3231
+#define MACH_TYPE_ICON_G 3232
+#define MACH_TYPE_MB3 3233
+#define MACH_TYPE_GSIA18S 3234
+#define MACH_TYPE_PIVICC 3235
+#define MACH_TYPE_PCM048 3236
+#define MACH_TYPE_DDS 3237
+#define MACH_TYPE_CHALTEN_XA1 3238
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
# define machine_is_npcmx50() (0)
#endif
-#ifdef CONFIG_MACH_MX51_LANGE51
+#ifdef CONFIG_MACH_MX51_EFIKAMX
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_MX51_LANGE51
+# define machine_arch_type MACH_TYPE_MX51_EFIKAMX
# endif
-# define machine_is_mx51_lange51() (machine_arch_type == MACH_TYPE_MX51_LANGE51)
+# define machine_is_mx51_efikamx() (machine_arch_type == MACH_TYPE_MX51_EFIKAMX)
#else
-# define machine_is_mx51_lange51() (0)
+# define machine_is_mx51_efikamx() (0)
#endif
#ifdef CONFIG_MACH_MX51_LANGE52
# define machine_is_huqiu() (0)
#endif
-#ifdef CONFIG_MACH_MX51_KUNLUN
+#ifdef CONFIG_MACH_MX51_EFIKASB
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_MX51_KUNLUN
+# define machine_arch_type MACH_TYPE_MX51_EFIKASB
# endif
-# define machine_is_mx51_kunlun() (machine_arch_type == MACH_TYPE_MX51_KUNLUN)
+# define machine_is_mx51_efikasb() (machine_arch_type == MACH_TYPE_MX51_EFIKASB)
#else
-# define machine_is_mx51_kunlun() (0)
+# define machine_is_mx51_efikasb() (0)
#endif
#ifdef CONFIG_MACH_PMT1G
# define machine_is_mx50_rdp() (0)
#endif
-#ifdef CONFIG_MACH_UNIVERSAL
+#ifdef CONFIG_MACH_UNIVERSAL_C210
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_UNIVERSAL
+# define machine_arch_type MACH_TYPE_UNIVERSAL_C210
# endif
-# define machine_is_universal() (machine_arch_type == MACH_TYPE_UNIVERSAL)
+# define machine_is_universal_c210() (machine_arch_type == MACH_TYPE_UNIVERSAL_C210)
#else
-# define machine_is_universal() (0)
+# define machine_is_universal_c210() (0)
#endif
#ifdef CONFIG_MACH_REAL6410
# define machine_is_pcontrol_g20() (0)
#endif
+#ifdef CONFIG_MACH_RDSTOR
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_RDSTOR
+# endif
+# define machine_is_rdstor() (machine_arch_type == MACH_TYPE_RDSTOR)
+#else
+# define machine_is_rdstor() (0)
+#endif
+
+#ifdef CONFIG_MACH_USDLOADER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_USDLOADER
+# endif
+# define machine_is_usdloader() (machine_arch_type == MACH_TYPE_USDLOADER)
+#else
+# define machine_is_usdloader() (0)
+#endif
+
+#ifdef CONFIG_MACH_TSOPLOADER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TSOPLOADER
+# endif
+# define machine_is_tsoploader() (machine_arch_type == MACH_TYPE_TSOPLOADER)
+#else
+# define machine_is_tsoploader() (0)
+#endif
+
+#ifdef CONFIG_MACH_KRONOS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KRONOS
+# endif
+# define machine_is_kronos() (machine_arch_type == MACH_TYPE_KRONOS)
+#else
+# define machine_is_kronos() (0)
+#endif
+
+#ifdef CONFIG_MACH_FFCORE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_FFCORE
+# endif
+# define machine_is_ffcore() (machine_arch_type == MACH_TYPE_FFCORE)
+#else
+# define machine_is_ffcore() (0)
+#endif
+
+#ifdef CONFIG_MACH_MONE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MONE
+# endif
+# define machine_is_mone() (machine_arch_type == MACH_TYPE_MONE)
+#else
+# define machine_is_mone() (0)
+#endif
+
+#ifdef CONFIG_MACH_UNIT2S
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_UNIT2S
+# endif
+# define machine_is_unit2s() (machine_arch_type == MACH_TYPE_UNIT2S)
+#else
+# define machine_is_unit2s() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_A5
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_A5
+# endif
+# define machine_is_acer_a5() (machine_arch_type == MACH_TYPE_ACER_A5)
+#else
+# define machine_is_acer_a5() (0)
+#endif
+
+#ifdef CONFIG_MACH_ETHERPRO_ISP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ETHERPRO_ISP
+# endif
+# define machine_is_etherpro_isp() (machine_arch_type == MACH_TYPE_ETHERPRO_ISP)
+#else
+# define machine_is_etherpro_isp() (0)
+#endif
+
+#ifdef CONFIG_MACH_STRETCHS7000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_STRETCHS7000
+# endif
+# define machine_is_stretchs7000() (machine_arch_type == MACH_TYPE_STRETCHS7000)
+#else
+# define machine_is_stretchs7000() (0)
+#endif
+
+#ifdef CONFIG_MACH_P87_SMARTSIM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_P87_SMARTSIM
+# endif
+# define machine_is_p87_smartsim() (machine_arch_type == MACH_TYPE_P87_SMARTSIM)
+#else
+# define machine_is_p87_smartsim() (0)
+#endif
+
+#ifdef CONFIG_MACH_TULIP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TULIP
+# endif
+# define machine_is_tulip() (machine_arch_type == MACH_TYPE_TULIP)
+#else
+# define machine_is_tulip() (0)
+#endif
+
+#ifdef CONFIG_MACH_SUNFLOWER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SUNFLOWER
+# endif
+# define machine_is_sunflower() (machine_arch_type == MACH_TYPE_SUNFLOWER)
+#else
+# define machine_is_sunflower() (0)
+#endif
+
+#ifdef CONFIG_MACH_RIB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_RIB
+# endif
+# define machine_is_rib() (machine_arch_type == MACH_TYPE_RIB)
+#else
+# define machine_is_rib() (0)
+#endif
+
+#ifdef CONFIG_MACH_CLOD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CLOD
+# endif
+# define machine_is_clod() (machine_arch_type == MACH_TYPE_CLOD)
+#else
+# define machine_is_clod() (0)
+#endif
+
+#ifdef CONFIG_MACH_RUMP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_RUMP
+# endif
+# define machine_is_rump() (machine_arch_type == MACH_TYPE_RUMP)
+#else
+# define machine_is_rump() (0)
+#endif
+
+#ifdef CONFIG_MACH_TENDERLOIN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TENDERLOIN
+# endif
+# define machine_is_tenderloin() (machine_arch_type == MACH_TYPE_TENDERLOIN)
+#else
+# define machine_is_tenderloin() (0)
+#endif
+
+#ifdef CONFIG_MACH_SHORTLOIN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SHORTLOIN
+# endif
+# define machine_is_shortloin() (machine_arch_type == MACH_TYPE_SHORTLOIN)
+#else
+# define machine_is_shortloin() (0)
+#endif
+
+#ifdef CONFIG_MACH_CRESPO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CRESPO
+# endif
+# define machine_is_crespo() (machine_arch_type == MACH_TYPE_CRESPO)
+#else
+# define machine_is_crespo() (0)
+#endif
+
+#ifdef CONFIG_MACH_ANTARES
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ANTARES
+# endif
+# define machine_is_antares() (machine_arch_type == MACH_TYPE_ANTARES)
+#else
+# define machine_is_antares() (0)
+#endif
+
+#ifdef CONFIG_MACH_WB40N
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WB40N
+# endif
+# define machine_is_wb40n() (machine_arch_type == MACH_TYPE_WB40N)
+#else
+# define machine_is_wb40n() (0)
+#endif
+
+#ifdef CONFIG_MACH_HERRING
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HERRING
+# endif
+# define machine_is_herring() (machine_arch_type == MACH_TYPE_HERRING)
+#else
+# define machine_is_herring() (0)
+#endif
+
+#ifdef CONFIG_MACH_NAXY400
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NAXY400
+# endif
+# define machine_is_naxy400() (machine_arch_type == MACH_TYPE_NAXY400)
+#else
+# define machine_is_naxy400() (0)
+#endif
+
+#ifdef CONFIG_MACH_NAXY1200
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NAXY1200
+# endif
+# define machine_is_naxy1200() (machine_arch_type == MACH_TYPE_NAXY1200)
+#else
+# define machine_is_naxy1200() (0)
+#endif
+
+#ifdef CONFIG_MACH_VPR200
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VPR200
+# endif
+# define machine_is_vpr200() (machine_arch_type == MACH_TYPE_VPR200)
+#else
+# define machine_is_vpr200() (0)
+#endif
+
+#ifdef CONFIG_MACH_BUG20
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BUG20
+# endif
+# define machine_is_bug20() (machine_arch_type == MACH_TYPE_BUG20)
+#else
+# define machine_is_bug20() (0)
+#endif
+
+#ifdef CONFIG_MACH_GOFLEXNET
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GOFLEXNET
+# endif
+# define machine_is_goflexnet() (machine_arch_type == MACH_TYPE_GOFLEXNET)
+#else
+# define machine_is_goflexnet() (0)
+#endif
+
+#ifdef CONFIG_MACH_TORBRECK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TORBRECK
+# endif
+# define machine_is_torbreck() (machine_arch_type == MACH_TYPE_TORBRECK)
+#else
+# define machine_is_torbreck() (0)
+#endif
+
+#ifdef CONFIG_MACH_SAARB_MG1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SAARB_MG1
+# endif
+# define machine_is_saarb_mg1() (machine_arch_type == MACH_TYPE_SAARB_MG1)
+#else
+# define machine_is_saarb_mg1() (0)
+#endif
+
+#ifdef CONFIG_MACH_CALLISTO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CALLISTO
+# endif
+# define machine_is_callisto() (machine_arch_type == MACH_TYPE_CALLISTO)
+#else
+# define machine_is_callisto() (0)
+#endif
+
+#ifdef CONFIG_MACH_MULTHSU
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MULTHSU
+# endif
+# define machine_is_multhsu() (machine_arch_type == MACH_TYPE_MULTHSU)
+#else
+# define machine_is_multhsu() (0)
+#endif
+
+#ifdef CONFIG_MACH_SALUDA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SALUDA
+# endif
+# define machine_is_saluda() (machine_arch_type == MACH_TYPE_SALUDA)
+#else
+# define machine_is_saluda() (0)
+#endif
+
+#ifdef CONFIG_MACH_PEMP_OMAP3_APOLLO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PEMP_OMAP3_APOLLO
+# endif
+# define machine_is_pemp_omap3_apollo() (machine_arch_type == MACH_TYPE_PEMP_OMAP3_APOLLO)
+#else
+# define machine_is_pemp_omap3_apollo() (0)
+#endif
+
+#ifdef CONFIG_MACH_VC0718
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VC0718
+# endif
+# define machine_is_vc0718() (machine_arch_type == MACH_TYPE_VC0718)
+#else
+# define machine_is_vc0718() (0)
+#endif
+
+#ifdef CONFIG_MACH_MVBLX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MVBLX
+# endif
+# define machine_is_mvblx() (machine_arch_type == MACH_TYPE_MVBLX)
+#else
+# define machine_is_mvblx() (0)
+#endif
+
+#ifdef CONFIG_MACH_INHAND_APEIRON
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_INHAND_APEIRON
+# endif
+# define machine_is_inhand_apeiron() (machine_arch_type == MACH_TYPE_INHAND_APEIRON)
+#else
+# define machine_is_inhand_apeiron() (0)
+#endif
+
+#ifdef CONFIG_MACH_INHAND_FURY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_INHAND_FURY
+# endif
+# define machine_is_inhand_fury() (machine_arch_type == MACH_TYPE_INHAND_FURY)
+#else
+# define machine_is_inhand_fury() (0)
+#endif
+
+#ifdef CONFIG_MACH_INHAND_SIREN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_INHAND_SIREN
+# endif
+# define machine_is_inhand_siren() (machine_arch_type == MACH_TYPE_INHAND_SIREN)
+#else
+# define machine_is_inhand_siren() (0)
+#endif
+
+#ifdef CONFIG_MACH_HDNVP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HDNVP
+# endif
+# define machine_is_hdnvp() (machine_arch_type == MACH_TYPE_HDNVP)
+#else
+# define machine_is_hdnvp() (0)
+#endif
+
+#ifdef CONFIG_MACH_SOFTWINNER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SOFTWINNER
+# endif
+# define machine_is_softwinner() (machine_arch_type == MACH_TYPE_SOFTWINNER)
+#else
+# define machine_is_softwinner() (0)
+#endif
+
+#ifdef CONFIG_MACH_PRIMA2_EVB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PRIMA2_EVB
+# endif
+# define machine_is_prima2_evb() (machine_arch_type == MACH_TYPE_PRIMA2_EVB)
+#else
+# define machine_is_prima2_evb() (0)
+#endif
+
+#ifdef CONFIG_MACH_NAS6210
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NAS6210
+# endif
+# define machine_is_nas6210() (machine_arch_type == MACH_TYPE_NAS6210)
+#else
+# define machine_is_nas6210() (0)
+#endif
+
+#ifdef CONFIG_MACH_UNISDEV
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_UNISDEV
+# endif
+# define machine_is_unisdev() (machine_arch_type == MACH_TYPE_UNISDEV)
+#else
+# define machine_is_unisdev() (0)
+#endif
+
+#ifdef CONFIG_MACH_SBCA11
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SBCA11
+# endif
+# define machine_is_sbca11() (machine_arch_type == MACH_TYPE_SBCA11)
+#else
+# define machine_is_sbca11() (0)
+#endif
+
+#ifdef CONFIG_MACH_SAGA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SAGA
+# endif
+# define machine_is_saga() (machine_arch_type == MACH_TYPE_SAGA)
+#else
+# define machine_is_saga() (0)
+#endif
+
+#ifdef CONFIG_MACH_NS_K330
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NS_K330
+# endif
+# define machine_is_ns_k330() (machine_arch_type == MACH_TYPE_NS_K330)
+#else
+# define machine_is_ns_k330() (0)
+#endif
+
+#ifdef CONFIG_MACH_TANNA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TANNA
+# endif
+# define machine_is_tanna() (machine_arch_type == MACH_TYPE_TANNA)
+#else
+# define machine_is_tanna() (0)
+#endif
+
+#ifdef CONFIG_MACH_IMATE8502
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IMATE8502
+# endif
+# define machine_is_imate8502() (machine_arch_type == MACH_TYPE_IMATE8502)
+#else
+# define machine_is_imate8502() (0)
+#endif
+
+#ifdef CONFIG_MACH_ASPEN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ASPEN
+# endif
+# define machine_is_aspen() (machine_arch_type == MACH_TYPE_ASPEN)
+#else
+# define machine_is_aspen() (0)
+#endif
+
+#ifdef CONFIG_MACH_DAINTREE_CWAC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DAINTREE_CWAC
+# endif
+# define machine_is_daintree_cwac() (machine_arch_type == MACH_TYPE_DAINTREE_CWAC)
+#else
+# define machine_is_daintree_cwac() (0)
+#endif
+
+#ifdef CONFIG_MACH_ZMX25
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ZMX25
+# endif
+# define machine_is_zmx25() (machine_arch_type == MACH_TYPE_ZMX25)
+#else
+# define machine_is_zmx25() (0)
+#endif
+
+#ifdef CONFIG_MACH_MAPLE1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MAPLE1
+# endif
+# define machine_is_maple1() (machine_arch_type == MACH_TYPE_MAPLE1)
+#else
+# define machine_is_maple1() (0)
+#endif
+
+#ifdef CONFIG_MACH_QSD8X72_SURF
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_QSD8X72_SURF
+# endif
+# define machine_is_qsd8x72_surf() (machine_arch_type == MACH_TYPE_QSD8X72_SURF)
+#else
+# define machine_is_qsd8x72_surf() (0)
+#endif
+
+#ifdef CONFIG_MACH_QSD8X72_FFA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_QSD8X72_FFA
+# endif
+# define machine_is_qsd8x72_ffa() (machine_arch_type == MACH_TYPE_QSD8X72_FFA)
+#else
+# define machine_is_qsd8x72_ffa() (0)
+#endif
+
+#ifdef CONFIG_MACH_ABILENE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ABILENE
+# endif
+# define machine_is_abilene() (machine_arch_type == MACH_TYPE_ABILENE)
+#else
+# define machine_is_abilene() (0)
+#endif
+
+#ifdef CONFIG_MACH_EIGEN_TTR
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EIGEN_TTR
+# endif
+# define machine_is_eigen_ttr() (machine_arch_type == MACH_TYPE_EIGEN_TTR)
+#else
+# define machine_is_eigen_ttr() (0)
+#endif
+
+#ifdef CONFIG_MACH_IOMEGA_IX2_200
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IOMEGA_IX2_200
+# endif
+# define machine_is_iomega_ix2_200() (machine_arch_type == MACH_TYPE_IOMEGA_IX2_200)
+#else
+# define machine_is_iomega_ix2_200() (0)
+#endif
+
+#ifdef CONFIG_MACH_CORETEC_VCX7400
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CORETEC_VCX7400
+# endif
+# define machine_is_coretec_vcx7400() (machine_arch_type == MACH_TYPE_CORETEC_VCX7400)
+#else
+# define machine_is_coretec_vcx7400() (0)
+#endif
+
+#ifdef CONFIG_MACH_SANTIAGO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SANTIAGO
+# endif
+# define machine_is_santiago() (machine_arch_type == MACH_TYPE_SANTIAGO)
+#else
+# define machine_is_santiago() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX257SOL
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX257SOL
+# endif
+# define machine_is_mx257sol() (machine_arch_type == MACH_TYPE_MX257SOL)
+#else
+# define machine_is_mx257sol() (0)
+#endif
+
+#ifdef CONFIG_MACH_STRASBOURG
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_STRASBOURG
+# endif
+# define machine_is_strasbourg() (machine_arch_type == MACH_TYPE_STRASBOURG)
+#else
+# define machine_is_strasbourg() (0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X60_FLUID
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MSM8X60_FLUID
+# endif
+# define machine_is_msm8x60_fluid() (machine_arch_type == MACH_TYPE_MSM8X60_FLUID)
+#else
+# define machine_is_msm8x60_fluid() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTQV5
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMARTQV5
+# endif
+# define machine_is_smartqv5() (machine_arch_type == MACH_TYPE_SMARTQV5)
+#else
+# define machine_is_smartqv5() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTQV3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMARTQV3
+# endif
+# define machine_is_smartqv3() (machine_arch_type == MACH_TYPE_SMARTQV3)
+#else
+# define machine_is_smartqv3() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTQV7
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMARTQV7
+# endif
+# define machine_is_smartqv7() (machine_arch_type == MACH_TYPE_SMARTQV7)
+#else
+# define machine_is_smartqv7() (0)
+#endif
+
+#ifdef CONFIG_MACH_PAZ00
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PAZ00
+# endif
+# define machine_is_paz00() (machine_arch_type == MACH_TYPE_PAZ00)
+#else
+# define machine_is_paz00() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACMENETUSFOXG20
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACMENETUSFOXG20
+# endif
+# define machine_is_acmenetusfoxg20() (machine_arch_type == MACH_TYPE_ACMENETUSFOXG20)
+#else
+# define machine_is_acmenetusfoxg20() (0)
+#endif
+
+#ifdef CONFIG_MACH_HTCWILLOW
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HTCWILLOW
+# endif
+# define machine_is_htcwillow() (machine_arch_type == MACH_TYPE_HTCWILLOW)
+#else
+# define machine_is_htcwillow() (0)
+#endif
+
+#ifdef CONFIG_MACH_FWBD_0404
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_FWBD_0404
+# endif
+# define machine_is_fwbd_0404() (machine_arch_type == MACH_TYPE_FWBD_0404)
+#else
+# define machine_is_fwbd_0404() (0)
+#endif
+
+#ifdef CONFIG_MACH_HDGU
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HDGU
+# endif
+# define machine_is_hdgu() (machine_arch_type == MACH_TYPE_HDGU)
+#else
+# define machine_is_hdgu() (0)
+#endif
+
+#ifdef CONFIG_MACH_PYRAMID
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PYRAMID
+# endif
+# define machine_is_pyramid() (machine_arch_type == MACH_TYPE_PYRAMID)
+#else
+# define machine_is_pyramid() (0)
+#endif
+
+#ifdef CONFIG_MACH_EPIPHAN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EPIPHAN
+# endif
+# define machine_is_epiphan() (machine_arch_type == MACH_TYPE_EPIPHAN)
+#else
+# define machine_is_epiphan() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_BENDER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP_BENDER
+# endif
+# define machine_is_omap_bender() (machine_arch_type == MACH_TYPE_OMAP_BENDER)
+#else
+# define machine_is_omap_bender() (0)
+#endif
+
+#ifdef CONFIG_MACH_GURNARD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GURNARD
+# endif
+# define machine_is_gurnard() (machine_arch_type == MACH_TYPE_GURNARD)
+#else
+# define machine_is_gurnard() (0)
+#endif
+
+#ifdef CONFIG_MACH_GTL_IT5100
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GTL_IT5100
+# endif
+# define machine_is_gtl_it5100() (machine_arch_type == MACH_TYPE_GTL_IT5100)
+#else
+# define machine_is_gtl_it5100() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCM2708
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCM2708
+# endif
+# define machine_is_bcm2708() (machine_arch_type == MACH_TYPE_BCM2708)
+#else
+# define machine_is_bcm2708() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_GGC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX51_GGC
+# endif
+# define machine_is_mx51_ggc() (machine_arch_type == MACH_TYPE_MX51_GGC)
+#else
+# define machine_is_mx51_ggc() (0)
+#endif
+
+#ifdef CONFIG_MACH_SHARESPACE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SHARESPACE
+# endif
+# define machine_is_sharespace() (machine_arch_type == MACH_TYPE_SHARESPACE)
+#else
+# define machine_is_sharespace() (0)
+#endif
+
+#ifdef CONFIG_MACH_HABA_KNX_EXPLORER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HABA_KNX_EXPLORER
+# endif
+# define machine_is_haba_knx_explorer() (machine_arch_type == MACH_TYPE_HABA_KNX_EXPLORER)
+#else
+# define machine_is_haba_knx_explorer() (0)
+#endif
+
+#ifdef CONFIG_MACH_SIMTEC_KIRKMOD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SIMTEC_KIRKMOD
+# endif
+# define machine_is_simtec_kirkmod() (machine_arch_type == MACH_TYPE_SIMTEC_KIRKMOD)
+#else
+# define machine_is_simtec_kirkmod() (0)
+#endif
+
+#ifdef CONFIG_MACH_CRUX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CRUX
+# endif
+# define machine_is_crux() (machine_arch_type == MACH_TYPE_CRUX)
+#else
+# define machine_is_crux() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_BRAVO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX51_BRAVO
+# endif
+# define machine_is_mx51_bravo() (machine_arch_type == MACH_TYPE_MX51_BRAVO)
+#else
+# define machine_is_mx51_bravo() (0)
+#endif
+
+#ifdef CONFIG_MACH_CHARON
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CHARON
+# endif
+# define machine_is_charon() (machine_arch_type == MACH_TYPE_CHARON)
+#else
+# define machine_is_charon() (0)
+#endif
+
+#ifdef CONFIG_MACH_PICOCOM3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PICOCOM3
+# endif
+# define machine_is_picocom3() (machine_arch_type == MACH_TYPE_PICOCOM3)
+#else
+# define machine_is_picocom3() (0)
+#endif
+
+#ifdef CONFIG_MACH_PICOCOM4
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PICOCOM4
+# endif
+# define machine_is_picocom4() (machine_arch_type == MACH_TYPE_PICOCOM4)
+#else
+# define machine_is_picocom4() (0)
+#endif
+
+#ifdef CONFIG_MACH_SERRANO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SERRANO
+# endif
+# define machine_is_serrano() (machine_arch_type == MACH_TYPE_SERRANO)
+#else
+# define machine_is_serrano() (0)
+#endif
+
+#ifdef CONFIG_MACH_DOUBLESHOT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DOUBLESHOT
+# endif
+# define machine_is_doubleshot() (machine_arch_type == MACH_TYPE_DOUBLESHOT)
+#else
+# define machine_is_doubleshot() (0)
+#endif
+
+#ifdef CONFIG_MACH_EVSY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EVSY
+# endif
+# define machine_is_evsy() (machine_arch_type == MACH_TYPE_EVSY)
+#else
+# define machine_is_evsy() (0)
+#endif
+
+#ifdef CONFIG_MACH_HUASHAN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HUASHAN
+# endif
+# define machine_is_huashan() (machine_arch_type == MACH_TYPE_HUASHAN)
+#else
+# define machine_is_huashan() (0)
+#endif
+
+#ifdef CONFIG_MACH_LAUSANNE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LAUSANNE
+# endif
+# define machine_is_lausanne() (machine_arch_type == MACH_TYPE_LAUSANNE)
+#else
+# define machine_is_lausanne() (0)
+#endif
+
+#ifdef CONFIG_MACH_EMERALD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EMERALD
+# endif
+# define machine_is_emerald() (machine_arch_type == MACH_TYPE_EMERALD)
+#else
+# define machine_is_emerald() (0)
+#endif
+
+#ifdef CONFIG_MACH_TQMA35
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TQMA35
+# endif
+# define machine_is_tqma35() (machine_arch_type == MACH_TYPE_TQMA35)
+#else
+# define machine_is_tqma35() (0)
+#endif
+
+#ifdef CONFIG_MACH_MARVEL
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MARVEL
+# endif
+# define machine_is_marvel() (machine_arch_type == MACH_TYPE_MARVEL)
+#else
+# define machine_is_marvel() (0)
+#endif
+
+#ifdef CONFIG_MACH_MANUAE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MANUAE
+# endif
+# define machine_is_manuae() (machine_arch_type == MACH_TYPE_MANUAE)
+#else
+# define machine_is_manuae() (0)
+#endif
+
+#ifdef CONFIG_MACH_CHACHA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CHACHA
+# endif
+# define machine_is_chacha() (machine_arch_type == MACH_TYPE_CHACHA)
+#else
+# define machine_is_chacha() (0)
+#endif
+
+#ifdef CONFIG_MACH_LEMON
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LEMON
+# endif
+# define machine_is_lemon() (machine_arch_type == MACH_TYPE_LEMON)
+#else
+# define machine_is_lemon() (0)
+#endif
+
+#ifdef CONFIG_MACH_CSC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CSC
+# endif
+# define machine_is_csc() (machine_arch_type == MACH_TYPE_CSC)
+#else
+# define machine_is_csc() (0)
+#endif
+
+#ifdef CONFIG_MACH_GIRA_KNXIP_ROUTER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GIRA_KNXIP_ROUTER
+# endif
+# define machine_is_gira_knxip_router() (machine_arch_type == MACH_TYPE_GIRA_KNXIP_ROUTER)
+#else
+# define machine_is_gira_knxip_router() (0)
+#endif
+
+#ifdef CONFIG_MACH_T20
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_T20
+# endif
+# define machine_is_t20() (machine_arch_type == MACH_TYPE_T20)
+#else
+# define machine_is_t20() (0)
+#endif
+
+#ifdef CONFIG_MACH_HDMINI
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HDMINI
+# endif
+# define machine_is_hdmini() (machine_arch_type == MACH_TYPE_HDMINI)
+#else
+# define machine_is_hdmini() (0)
+#endif
+
+#ifdef CONFIG_MACH_SCIPHONE_G2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SCIPHONE_G2
+# endif
+# define machine_is_sciphone_g2() (machine_arch_type == MACH_TYPE_SCIPHONE_G2)
+#else
+# define machine_is_sciphone_g2() (0)
+#endif
+
+#ifdef CONFIG_MACH_EXPRESS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EXPRESS
+# endif
+# define machine_is_express() (machine_arch_type == MACH_TYPE_EXPRESS)
+#else
+# define machine_is_express() (0)
+#endif
+
+#ifdef CONFIG_MACH_EXPRESS_KT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EXPRESS_KT
+# endif
+# define machine_is_express_kt() (machine_arch_type == MACH_TYPE_EXPRESS_KT)
+#else
+# define machine_is_express_kt() (0)
+#endif
+
+#ifdef CONFIG_MACH_MAXIMASP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MAXIMASP
+# endif
+# define machine_is_maximasp() (machine_arch_type == MACH_TYPE_MAXIMASP)
+#else
+# define machine_is_maximasp() (0)
+#endif
+
+#ifdef CONFIG_MACH_NITROGEN_IMX51
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NITROGEN_IMX51
+# endif
+# define machine_is_nitrogen_imx51() (machine_arch_type == MACH_TYPE_NITROGEN_IMX51)
+#else
+# define machine_is_nitrogen_imx51() (0)
+#endif
+
+#ifdef CONFIG_MACH_NITROGEN_IMX53
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NITROGEN_IMX53
+# endif
+# define machine_is_nitrogen_imx53() (machine_arch_type == MACH_TYPE_NITROGEN_IMX53)
+#else
+# define machine_is_nitrogen_imx53() (0)
+#endif
+
+#ifdef CONFIG_MACH_SUNFIRE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SUNFIRE
+# endif
+# define machine_is_sunfire() (machine_arch_type == MACH_TYPE_SUNFIRE)
+#else
+# define machine_is_sunfire() (0)
+#endif
+
+#ifdef CONFIG_MACH_AROWANA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AROWANA
+# endif
+# define machine_is_arowana() (machine_arch_type == MACH_TYPE_AROWANA)
+#else
+# define machine_is_arowana() (0)
+#endif
+
+#ifdef CONFIG_MACH_TEGRA_DAYTONA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TEGRA_DAYTONA
+# endif
+# define machine_is_tegra_daytona() (machine_arch_type == MACH_TYPE_TEGRA_DAYTONA)
+#else
+# define machine_is_tegra_daytona() (0)
+#endif
+
+#ifdef CONFIG_MACH_TEGRA_SWORDFISH
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TEGRA_SWORDFISH
+# endif
+# define machine_is_tegra_swordfish() (machine_arch_type == MACH_TYPE_TEGRA_SWORDFISH)
+#else
+# define machine_is_tegra_swordfish() (0)
+#endif
+
+#ifdef CONFIG_MACH_EDISON
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EDISON
+# endif
+# define machine_is_edison() (machine_arch_type == MACH_TYPE_EDISON)
+#else
+# define machine_is_edison() (0)
+#endif
+
+#ifdef CONFIG_MACH_SVP8500V1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SVP8500V1
+# endif
+# define machine_is_svp8500v1() (machine_arch_type == MACH_TYPE_SVP8500V1)
+#else
+# define machine_is_svp8500v1() (0)
+#endif
+
+#ifdef CONFIG_MACH_SVP8500V2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SVP8500V2
+# endif
+# define machine_is_svp8500v2() (machine_arch_type == MACH_TYPE_SVP8500V2)
+#else
+# define machine_is_svp8500v2() (0)
+#endif
+
+#ifdef CONFIG_MACH_SVP5500
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SVP5500
+# endif
+# define machine_is_svp5500() (machine_arch_type == MACH_TYPE_SVP5500)
+#else
+# define machine_is_svp5500() (0)
+#endif
+
+#ifdef CONFIG_MACH_B5500
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_B5500
+# endif
+# define machine_is_b5500() (machine_arch_type == MACH_TYPE_B5500)
+#else
+# define machine_is_b5500() (0)
+#endif
+
+#ifdef CONFIG_MACH_S5500
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_S5500
+# endif
+# define machine_is_s5500() (machine_arch_type == MACH_TYPE_S5500)
+#else
+# define machine_is_s5500() (0)
+#endif
+
+#ifdef CONFIG_MACH_ICON
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ICON
+# endif
+# define machine_is_icon() (machine_arch_type == MACH_TYPE_ICON)
+#else
+# define machine_is_icon() (0)
+#endif
+
+#ifdef CONFIG_MACH_ELEPHANT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ELEPHANT
+# endif
+# define machine_is_elephant() (machine_arch_type == MACH_TYPE_ELEPHANT)
+#else
+# define machine_is_elephant() (0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X60_FUSION
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MSM8X60_FUSION
+# endif
+# define machine_is_msm8x60_fusion() (machine_arch_type == MACH_TYPE_MSM8X60_FUSION)
+#else
+# define machine_is_msm8x60_fusion() (0)
+#endif
+
+#ifdef CONFIG_MACH_SHOOTER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SHOOTER
+# endif
+# define machine_is_shooter() (machine_arch_type == MACH_TYPE_SHOOTER)
+#else
+# define machine_is_shooter() (0)
+#endif
+
+#ifdef CONFIG_MACH_SPADE_LTE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SPADE_LTE
+# endif
+# define machine_is_spade_lte() (machine_arch_type == MACH_TYPE_SPADE_LTE)
+#else
+# define machine_is_spade_lte() (0)
+#endif
+
+#ifdef CONFIG_MACH_PHILHWANI
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PHILHWANI
+# endif
+# define machine_is_philhwani() (machine_arch_type == MACH_TYPE_PHILHWANI)
+#else
+# define machine_is_philhwani() (0)
+#endif
+
+#ifdef CONFIG_MACH_GSNCOMM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GSNCOMM
+# endif
+# define machine_is_gsncomm() (machine_arch_type == MACH_TYPE_GSNCOMM)
+#else
+# define machine_is_gsncomm() (0)
+#endif
+
+#ifdef CONFIG_MACH_STRASBOURG_A2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_STRASBOURG_A2
+# endif
+# define machine_is_strasbourg_a2() (machine_arch_type == MACH_TYPE_STRASBOURG_A2)
+#else
+# define machine_is_strasbourg_a2() (0)
+#endif
+
+#ifdef CONFIG_MACH_MMM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MMM
+# endif
+# define machine_is_mmm() (machine_arch_type == MACH_TYPE_MMM)
+#else
+# define machine_is_mmm() (0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DM365_BV
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DAVINCI_DM365_BV
+# endif
+# define machine_is_davinci_dm365_bv() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_BV)
+#else
+# define machine_is_davinci_dm365_bv() (0)
+#endif
+
+#ifdef CONFIG_MACH_AG5EVM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AG5EVM
+# endif
+# define machine_is_ag5evm() (machine_arch_type == MACH_TYPE_AG5EVM)
+#else
+# define machine_is_ag5evm() (0)
+#endif
+
+#ifdef CONFIG_MACH_SC575PLC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SC575PLC
+# endif
+# define machine_is_sc575plc() (machine_arch_type == MACH_TYPE_SC575PLC)
+#else
+# define machine_is_sc575plc() (0)
+#endif
+
+#ifdef CONFIG_MACH_SC575IPC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SC575IPC
+# endif
+# define machine_is_sc575hmi() (machine_arch_type == MACH_TYPE_SC575IPC)
+#else
+# define machine_is_sc575hmi() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_TDM3730
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3_TDM3730
+# endif
+# define machine_is_omap3_tdm3730() (machine_arch_type == MACH_TYPE_OMAP3_TDM3730)
+#else
+# define machine_is_omap3_tdm3730() (0)
+#endif
+
+#ifdef CONFIG_MACH_G7
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_G7
+# endif
+# define machine_is_g7() (machine_arch_type == MACH_TYPE_G7)
+#else
+# define machine_is_g7() (0)
+#endif
+
+#ifdef CONFIG_MACH_TOP9000_EVAL
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TOP9000_EVAL
+# endif
+# define machine_is_top9000_eval() (machine_arch_type == MACH_TYPE_TOP9000_EVAL)
+#else
+# define machine_is_top9000_eval() (0)
+#endif
+
+#ifdef CONFIG_MACH_TOP9000_SU
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TOP9000_SU
+# endif
+# define machine_is_top9000_su() (machine_arch_type == MACH_TYPE_TOP9000_SU)
+#else
+# define machine_is_top9000_su() (0)
+#endif
+
+#ifdef CONFIG_MACH_UTM300
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_UTM300
+# endif
+# define machine_is_utm300() (machine_arch_type == MACH_TYPE_UTM300)
+#else
+# define machine_is_utm300() (0)
+#endif
+
+#ifdef CONFIG_MACH_TSUNAGI
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TSUNAGI
+# endif
+# define machine_is_tsunagi() (machine_arch_type == MACH_TYPE_TSUNAGI)
+#else
+# define machine_is_tsunagi() (0)
+#endif
+
+#ifdef CONFIG_MACH_TS75XX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TS75XX
+# endif
+# define machine_is_ts75xx() (machine_arch_type == MACH_TYPE_TS75XX)
+#else
+# define machine_is_ts75xx() (0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X60_FUSN_FFA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MSM8X60_FUSN_FFA
+# endif
+# define machine_is_msm8x60_fusn_ffa() (machine_arch_type == MACH_TYPE_MSM8X60_FUSN_FFA)
+#else
+# define machine_is_msm8x60_fusn_ffa() (0)
+#endif
+
+#ifdef CONFIG_MACH_TS47XX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TS47XX
+# endif
+# define machine_is_ts47xx() (machine_arch_type == MACH_TYPE_TS47XX)
+#else
+# define machine_is_ts47xx() (0)
+#endif
+
+#ifdef CONFIG_MACH_DA850_K5
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DA850_K5
+# endif
+# define machine_is_da850_k5() (machine_arch_type == MACH_TYPE_DA850_K5)
+#else
+# define machine_is_da850_k5() (0)
+#endif
+
+#ifdef CONFIG_MACH_AX502
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AX502
+# endif
+# define machine_is_ax502() (machine_arch_type == MACH_TYPE_AX502)
+#else
+# define machine_is_ax502() (0)
+#endif
+
+#ifdef CONFIG_MACH_IGEP0032
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IGEP0032
+# endif
+# define machine_is_igep0032() (machine_arch_type == MACH_TYPE_IGEP0032)
+#else
+# define machine_is_igep0032() (0)
+#endif
+
+#ifdef CONFIG_MACH_ANTERO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ANTERO
+# endif
+# define machine_is_antero() (machine_arch_type == MACH_TYPE_ANTERO)
+#else
+# define machine_is_antero() (0)
+#endif
+
+#ifdef CONFIG_MACH_SYNERGY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SYNERGY
+# endif
+# define machine_is_synergy() (machine_arch_type == MACH_TYPE_SYNERGY)
+#else
+# define machine_is_synergy() (0)
+#endif
+
+#ifdef CONFIG_MACH_ICS_IF_VOIP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ICS_IF_VOIP
+# endif
+# define machine_is_ics_if_voip() (machine_arch_type == MACH_TYPE_ICS_IF_VOIP)
+#else
+# define machine_is_ics_if_voip() (0)
+#endif
+
+#ifdef CONFIG_MACH_WLF_CRAGG_6410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WLF_CRAGG_6410
+# endif
+# define machine_is_wlf_cragg_6410() (machine_arch_type == MACH_TYPE_WLF_CRAGG_6410)
+#else
+# define machine_is_wlf_cragg_6410() (0)
+#endif
+
+#ifdef CONFIG_MACH_PUNICA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PUNICA
+# endif
+# define machine_is_punica() (machine_arch_type == MACH_TYPE_PUNICA)
+#else
+# define machine_is_punica() (0)
+#endif
+
+#ifdef CONFIG_MACH_SBC_NT250
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SBC_NT250
+# endif
+# define machine_is_sbc_nt250() (machine_arch_type == MACH_TYPE_SBC_NT250)
+#else
+# define machine_is_sbc_nt250() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX27_WMULTRA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX27_WMULTRA
+# endif
+# define machine_is_mx27_wmultra() (machine_arch_type == MACH_TYPE_MX27_WMULTRA)
+#else
+# define machine_is_mx27_wmultra() (0)
+#endif
+
+#ifdef CONFIG_MACH_MACKEREL
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MACKEREL
+# endif
+# define machine_is_mackerel() (machine_arch_type == MACH_TYPE_MACKEREL)
+#else
+# define machine_is_mackerel() (0)
+#endif
+
+#ifdef CONFIG_MACH_FA9X27
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_FA9X27
+# endif
+# define machine_is_fa9x27() (machine_arch_type == MACH_TYPE_FA9X27)
+#else
+# define machine_is_fa9x27() (0)
+#endif
+
+#ifdef CONFIG_MACH_NS2816TB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NS2816TB
+# endif
+# define machine_is_ns2816tb() (machine_arch_type == MACH_TYPE_NS2816TB)
+#else
+# define machine_is_ns2816tb() (0)
+#endif
+
+#ifdef CONFIG_MACH_NS2816_NTPAD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NS2816_NTPAD
+# endif
+# define machine_is_ns2816_ntpad() (machine_arch_type == MACH_TYPE_NS2816_NTPAD)
+#else
+# define machine_is_ns2816_ntpad() (0)
+#endif
+
+#ifdef CONFIG_MACH_NS2816_NTNB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NS2816_NTNB
+# endif
+# define machine_is_ns2816_ntnb() (machine_arch_type == MACH_TYPE_NS2816_NTNB)
+#else
+# define machine_is_ns2816_ntnb() (0)
+#endif
+
+#ifdef CONFIG_MACH_KAEN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KAEN
+# endif
+# define machine_is_kaen() (machine_arch_type == MACH_TYPE_KAEN)
+#else
+# define machine_is_kaen() (0)
+#endif
+
+#ifdef CONFIG_MACH_NV1000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NV1000
+# endif
+# define machine_is_nv1000() (machine_arch_type == MACH_TYPE_NV1000)
+#else
+# define machine_is_nv1000() (0)
+#endif
+
+#ifdef CONFIG_MACH_NUC950TS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NUC950TS
+# endif
+# define machine_is_nuc950ts() (machine_arch_type == MACH_TYPE_NUC950TS)
+#else
+# define machine_is_nuc950ts() (0)
+#endif
+
+#ifdef CONFIG_MACH_NOKIA_RM680
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NOKIA_RM680
+# endif
+# define machine_is_nokia_rm680() (machine_arch_type == MACH_TYPE_NOKIA_RM680)
+#else
+# define machine_is_nokia_rm680() (0)
+#endif
+
+#ifdef CONFIG_MACH_AST2200
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AST2200
+# endif
+# define machine_is_ast2200() (machine_arch_type == MACH_TYPE_AST2200)
+#else
+# define machine_is_ast2200() (0)
+#endif
+
+#ifdef CONFIG_MACH_LEAD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LEAD
+# endif
+# define machine_is_lead() (machine_arch_type == MACH_TYPE_LEAD)
+#else
+# define machine_is_lead() (0)
+#endif
+
+#ifdef CONFIG_MACH_UNINO1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_UNINO1
+# endif
+# define machine_is_unino1() (machine_arch_type == MACH_TYPE_UNINO1)
+#else
+# define machine_is_unino1() (0)
+#endif
+
+#ifdef CONFIG_MACH_GREECO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GREECO
+# endif
+# define machine_is_greeco() (machine_arch_type == MACH_TYPE_GREECO)
+#else
+# define machine_is_greeco() (0)
+#endif
+
+#ifdef CONFIG_MACH_VERDI
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VERDI
+# endif
+# define machine_is_verdi() (machine_arch_type == MACH_TYPE_VERDI)
+#else
+# define machine_is_verdi() (0)
+#endif
+
+#ifdef CONFIG_MACH_DM6446_ADBOX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DM6446_ADBOX
+# endif
+# define machine_is_dm6446_adbox() (machine_arch_type == MACH_TYPE_DM6446_ADBOX)
+#else
+# define machine_is_dm6446_adbox() (0)
+#endif
+
+#ifdef CONFIG_MACH_QUAD_SALSA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_QUAD_SALSA
+# endif
+# define machine_is_quad_salsa() (machine_arch_type == MACH_TYPE_QUAD_SALSA)
+#else
+# define machine_is_quad_salsa() (0)
+#endif
+
+#ifdef CONFIG_MACH_ABB_GMA_1_1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ABB_GMA_1_1
+# endif
+# define machine_is_abb_gma_1_1() (machine_arch_type == MACH_TYPE_ABB_GMA_1_1)
+#else
+# define machine_is_abb_gma_1_1() (0)
+#endif
+
+#ifdef CONFIG_MACH_SVCID
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SVCID
+# endif
+# define machine_is_svcid() (machine_arch_type == MACH_TYPE_SVCID)
+#else
+# define machine_is_svcid() (0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8960_SIM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MSM8960_SIM
+# endif
+# define machine_is_msm8960_sim() (machine_arch_type == MACH_TYPE_MSM8960_SIM)
+#else
+# define machine_is_msm8960_sim() (0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8960_RUMI3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MSM8960_RUMI3
+# endif
+# define machine_is_msm8960_rumi3() (machine_arch_type == MACH_TYPE_MSM8960_RUMI3)
+#else
+# define machine_is_msm8960_rumi3() (0)
+#endif
+
+#ifdef CONFIG_MACH_ICON_G
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ICON_G
+# endif
+# define machine_is_icon_g() (machine_arch_type == MACH_TYPE_ICON_G)
+#else
+# define machine_is_icon_g() (0)
+#endif
+
+#ifdef CONFIG_MACH_MB3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MB3
+# endif
+# define machine_is_mb3() (machine_arch_type == MACH_TYPE_MB3)
+#else
+# define machine_is_mb3() (0)
+#endif
+
+#ifdef CONFIG_MACH_GSIA18S
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GSIA18S
+# endif
+# define machine_is_gsia18s() (machine_arch_type == MACH_TYPE_GSIA18S)
+#else
+# define machine_is_gsia18s() (0)
+#endif
+
+#ifdef CONFIG_MACH_PIVICC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PIVICC
+# endif
+# define machine_is_pivicc() (machine_arch_type == MACH_TYPE_PIVICC)
+#else
+# define machine_is_pivicc() (0)
+#endif
+
+#ifdef CONFIG_MACH_PCM048
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PCM048
+# endif
+# define machine_is_pcm048() (machine_arch_type == MACH_TYPE_PCM048)
+#else
+# define machine_is_pcm048() (0)
+#endif
+
+#ifdef CONFIG_MACH_DDS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DDS
+# endif
+# define machine_is_dds() (machine_arch_type == MACH_TYPE_DDS)
+#else
+# define machine_is_dds() (0)
+#endif
+
+#ifdef CONFIG_MACH_CHALTEN_XA1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CHALTEN_XA1
+# endif
+# define machine_is_chalten_xa1() (machine_arch_type == MACH_TYPE_CHALTEN_XA1)
+#else
+# define machine_is_chalten_xa1() (0)
+#endif
+
/*
* These have not yet been registered
*/
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := cm_t35.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Author: Mike Rapoport <mike@compulab.co.il>
+ *
+ * Derived from omap3evm and Beagle Board by
+ * Manikandan Pillai <mani.pillai@ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <net.h>
+#include <i2c.h>
+#include <twl4030.h>
+
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "CM-T35 board",
+ "NAND",
+};
+
+static u32 gpmc_net_config[GPMC_MAX_REG] = {
+ NET_GPMC_CONFIG1,
+ NET_GPMC_CONFIG2,
+ NET_GPMC_CONFIG3,
+ NET_GPMC_CONFIG4,
+ NET_GPMC_CONFIG5,
+ NET_GPMC_CONFIG6,
+ 0
+};
+
+static u32 gpmc_nand_config[GPMC_MAX_REG] = {
+ SMNAND_GPMC_CONFIG1,
+ SMNAND_GPMC_CONFIG2,
+ SMNAND_GPMC_CONFIG3,
+ SMNAND_GPMC_CONFIG4,
+ SMNAND_GPMC_CONFIG5,
+ SMNAND_GPMC_CONFIG6,
+ 0,
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+ enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
+ CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
+
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Init I2C and display die ID
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ /* SDRC */
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
+
+ /* GPMC */
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
+
+ /* SB-T35 Ethernet */
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
+
+ /* CM-T35 Ethernet */
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
+ MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/
+ MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/
+
+ /* DSS */
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
+
+ /* serial interface */
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/
+
+ /* mUSB */
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
+
+ /* I2C1 */
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
+
+ /* control and debug */
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M4)); /*green LED*/
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0);
+}
+#endif
+
+/*
+ * Routine: setup_net_chip_gmpc
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip_gmpc(void)
+{
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
+ CM_T35_SMC911X_BASE, GPMC_SIZE_16M);
+ enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
+ SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+}
+
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+/*
+ * Routine: reset_net_chip
+ * Description: reset the Ethernet controller via TPS65930 GPIO
+ */
+static void reset_net_chip(void)
+{
+ /* Set GPIO1 of TPS65930 as output */
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
+ TWL4030_BASEADD_GPIO+0x03);
+ /* Send a pulse on the GPIO pin */
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
+ TWL4030_BASEADD_GPIO+0x0C);
+ udelay(1);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
+ TWL4030_BASEADD_GPIO+0x09);
+ udelay(1);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
+ TWL4030_BASEADD_GPIO+0x0C);
+}
+#else
+static inline void reset_net_chip(void) {}
+#endif
+
+/*
+ * Routine: handle_mac_address
+ * Description: prepare MAC address for on-board Ethernet.
+ */
+static int handle_mac_address(void)
+{
+ unsigned char enetaddr[6];
+ int rc;
+
+ rc = eth_getenv_enetaddr("ethaddr", enetaddr);
+ if (rc)
+ return 0;
+
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ rc = i2c_read(0x50, 0, 1, enetaddr, 6);
+ if (rc)
+ return rc;
+#endif
+
+ if (!is_valid_ether_addr(enetaddr))
+ return -1;
+
+ return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
+
+/*
+ * Routine: board_eth_init
+ * Description: initialize module and base-board Ethernet chips
+ */
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0, rc1 = 0;
+
+#ifdef CONFIG_SMC911X
+ setup_net_chip_gmpc();
+ reset_net_chip();
+
+ rc1 = handle_mac_address();
+ if (rc1)
+ printf("CM-T35: No MAC address found\n");
+
+ rc1 = smc911x_initialize(0, CM_T35_SMC911X_BASE);
+ if (rc1 > 0)
+ rc++;
+
+ rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
+ if (rc1 > 0)
+ rc++;
+#endif
+
+ return rc;
+}
/*
* Set the mii mode as MII or RMII
*/
-#if defined(CONFIG_DRIVER_TI_EMAC)
+#if defined(CONFIG_SOC_DA8XX)
void davinci_emac_mii_mode_sel(int mode_sel)
{
int val;
#include <asm/arch/davinci_misc.h>
#include <net.h>
#include <netdev.h>
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
}
#endif
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .input_clk = 108000000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_1,
+};
+
+#ifdef CONFIG_DAVINCI_MMC_SD1
+static struct davinci_mmc mmc_sd1 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
+ .input_clk = 108000000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_1,
+};
+#endif
+
+int board_mmc_init(bd_t *bis)
+{
+ int err;
+
+ /* Add slot-0 to mmc subsystem */
+ err = davinci_mmc_init(bis, &mmc_sd0);
+ if (err)
+ return err;
+
+#ifdef CONFIG_DAVINCI_MMC_SD1
+ /* Add slot-1 to mmc subsystem */
+ err = davinci_mmc_init(bis, &mmc_sd1);
+#endif
+
+ return err;
+}
+#endif
#include <asm/arch/gpio_defs.h>
#include <netdev.h>
#include <asm/arch/davinci_misc.h>
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
#endif
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .input_clk = 121500000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+
+#ifdef CONFIG_DAVINCI_MMC_SD1
+static struct davinci_mmc mmc_sd1 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
+ .input_clk = 121500000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+#endif
+
+int board_mmc_init(bd_t *bis)
+{
+ int err;
+
+ /* Add slot-0 to mmc subsystem */
+ err = davinci_mmc_init(bis, &mmc_sd0);
+ if (err)
+ return err;
+
+#ifdef CONFIG_DAVINCI_MMC_SD1
+#define PUPDCTL1 0x01c4007c
+ /* PINMUX(4)-DAT0-3/CMD; PINMUX(0)-CLK */
+ writel((readl(PINMUX4) | 0x55400000), PINMUX4);
+ writel((readl(PINMUX0) | 0x00010000), PINMUX0);
+
+ /* Configure MMC/SD pins as pullup */
+ writel((readl(PUPDCTL1) & ~0x07c0), PUPDCTL1);
+
+ /* Add slot-1 to mmc subsystem */
+ err = davinci_mmc_init(bis, &mmc_sd1);
+#endif
+
+ return err;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/arch/nand_defs.h>
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+ lpsc_on(DAVINCI_DM646X_LPSC_TIMER0);
+ lpsc_on(DAVINCI_DM646X_LPSC_UART0);
+ lpsc_on(DAVINCI_DM646X_LPSC_I2C);
+ lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
+
+ /* Enable GIO3.3V cells used for EMAC */
+ REG(VDD3P3V_PWDN) = 0x80000c0;
+
+ /* Select UART function on UART0 */
+ REG(PINMUX0) &= ~(0x0000003f << 18);
+ REG(PINMUX1) &= ~(0x00000003);
+
+ return 0;
+}
+
+#if defined(CONFIG_DRIVER_TI_EMAC)
+
+int board_eth_init(bd_t *bis)
+{
+ if (!davinci_emac_initialize()) {
+ printf("Error: Ethernet init failed!\n");
+ return -1;
+ }
+
return 0;
}
+#endif /* CONFIG_DRIVER_TI_EMAC */
#ifdef CONFIG_NAND_DAVINCI
int board_nand_init(struct nand_chip *nand)
--- /dev/null
+#
+# Copyright (C) 2010, Marek Vasut <marek.vasut@gmail.com>
+#
+# BASED ON: imx51evk
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := efikamx.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
#
-# (C) Copyright 2009 Faraday Technology
-# Po-Yu Chuang <ratbert@faraday-tech.com>
+# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# MA 02111-1307 USA
#
-# Faraday A320 board with FA526/FA626TE/ARM926EJ-S cpus
-#
-# see http://www.faraday-tech.com/ for more information
-
-# A320 has 1 bank of 64 MB DRAM
-#
-# 1000'0000 to 1400'0000
-#
-# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
-#
-# we load ourself to 13f8'0000
-#
-# download area is 1200'0000
-
-CONFIG_SYS_TEXT_BASE = 0x13f80000
+CONFIG_SYS_TEXT_BASE = 0x97800000
+IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
+ALL += $(obj)u-boot.imx
--- /dev/null
+/*
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
+#include <mxc_gpio.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Compile-time error checking
+ */
+#ifndef CONFIG_MXC_SPI
+#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
+#endif
+
+/*
+ * Shared variables / local defines
+ */
+/* LED */
+#define EFIKAMX_LED_BLUE 0x1
+#define EFIKAMX_LED_GREEN 0x2
+#define EFIKAMX_LED_RED 0x4
+
+void efikamx_toggle_led(uint32_t mask);
+
+/* Board revisions */
+#define EFIKAMX_BOARD_REV_11 0x1
+#define EFIKAMX_BOARD_REV_12 0x2
+#define EFIKAMX_BOARD_REV_13 0x3
+#define EFIKAMX_BOARD_REV_14 0x4
+
+/*
+ * Board identification
+ */
+u32 get_efika_rev(void)
+{
+ u32 rev = 0;
+ /*
+ * Retrieve board ID:
+ * rev1.1: 1,1,1
+ * rev1.2: 1,1,0
+ * rev1.3: 1,0,1
+ * rev1.4: 1,0,0
+ */
+ mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0),
+ MXC_GPIO_DIRECTION_OUT);
+ /* set to 1 in order to get correct value on board rev1.1 */
+ mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
+
+ mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0),
+ MXC_GPIO_DIRECTION_IN);
+ rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0;
+
+ mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1),
+ MXC_GPIO_DIRECTION_IN);
+ rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1;
+
+ mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3),
+ MXC_GPIO_DIRECTION_IN);
+ rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2;
+
+ return (~rev & 0x7) + 1;
+}
+
+u32 get_board_rev(void)
+{
+ return get_cpu_rev() | (get_efika_rev() << 8);
+}
+
+/*
+ * DRAM initialization
+ */
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+/*
+ * UART configuration
+ */
+static void setup_iomux_uart(void)
+{
+ unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
+
+ mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
+ mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
+ mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
+ mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
+}
+
+/*
+ * SPI configuration
+ */
+#ifdef CONFIG_MXC_SPI
+static void setup_iomux_spi(void)
+{
+ /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
+ mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+
+ /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
+ mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+
+ /* Configure SS0 as a GPIO */
+ mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0),
+ MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
+
+ /* Configure SS1 as a GPIO */
+ mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1),
+ MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
+
+ /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
+ mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+ /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
+ mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+}
+#else
+static inline void setup_iomux_spi(void) { }
+#endif
+
+/*
+ * PMIC configuration
+ */
+#ifdef CONFIG_MXC_SPI
+static void power_init(void)
+{
+ unsigned int val;
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+
+ /* Write needed to Power Gate 2 register */
+ val = pmic_reg_read(REG_POWER_MISC);
+ val &= ~PWGT2SPIEN;
+ pmic_reg_write(REG_POWER_MISC, val);
+
+ /* Externally powered */
+ val = pmic_reg_read(REG_CHARGE);
+ val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
+ pmic_reg_write(REG_CHARGE, val);
+
+ /* power up the system first */
+ pmic_reg_write(REG_POWER_MISC, PWUP);
+
+ /* Set core voltage to 1.1V */
+ val = pmic_reg_read(REG_SW_0);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
+ pmic_reg_write(REG_SW_0, val);
+
+ /* Setup VCC (SW2) to 1.25 */
+ val = pmic_reg_read(REG_SW_1);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+ pmic_reg_write(REG_SW_1, val);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.25 */
+ val = pmic_reg_read(REG_SW_2);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+ pmic_reg_write(REG_SW_2, val);
+ udelay(50);
+
+ /* Raise the core frequency to 800MHz */
+ writel(0x0, &mxc_ccm->cacrr);
+
+ /* Set switchers in Auto in NORMAL mode & STANDBY mode */
+ /* Setup the switcher mode for SW1 & SW2*/
+ val = pmic_reg_read(REG_SW_4);
+ val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+ (SWMODE_MASK << SWMODE2_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+ pmic_reg_write(REG_SW_4, val);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ val = pmic_reg_read(REG_SW_5);
+ val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
+ (SWMODE_MASK << SWMODE4_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
+ pmic_reg_write(REG_SW_5, val);
+
+ /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
+ val = pmic_reg_read(REG_SETTING_0);
+ val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
+ val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
+ pmic_reg_write(REG_SETTING_0, val);
+
+ /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
+ val = pmic_reg_read(REG_SETTING_1);
+ val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
+ val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
+ pmic_reg_write(REG_SETTING_1, val);
+
+ /* Configure VGEN3 and VCAM regulators to use external PNP */
+ val = VGEN3CONFIG | VCAMCONFIG;
+ pmic_reg_write(REG_MODE_1, val);
+ udelay(200);
+
+ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
+ VVIDEOEN | VAUDIOEN | VSDEN;
+ pmic_reg_write(REG_MODE_1, val);
+
+ val = pmic_reg_read(REG_POWER_CTL2);
+ val |= WDIRESET;
+ pmic_reg_write(REG_POWER_CTL2, val);
+
+ udelay(2500);
+}
+#else
+static inline void power_init(void) { }
+#endif
+
+/*
+ * MMC configuration
+ */
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {MMC_SDHC1_BASE_ADDR, 1},
+ {MMC_SDHC2_BASE_ADDR, 1},
+};
+
+int board_mmc_getcd(u8 *absent, struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+ *absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0));
+ else
+ *absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
+
+ return 0;
+}
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ /* SDHC1 is used on all revisions, setup control pins first */
+ mxc_request_iomux(MX51_PIN_GPIO1_0,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
+ PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
+ PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_request_iomux(MX51_PIN_GPIO1_1,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
+ PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_SRE_FAST);
+
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0),
+ MXC_GPIO_DIRECTION_IN);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1),
+ MXC_GPIO_DIRECTION_IN);
+
+ /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
+ if (get_efika_rev() < EFIKAMX_BOARD_REV_12) {
+ /* SDHC1 IOMUX */
+ mxc_request_iomux(MX51_PIN_SD1_CMD,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
+ PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_CLK,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
+ PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
+ PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
+ PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
+ PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
+ PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
+
+ /* SDHC2 IOMUX */
+ mxc_request_iomux(MX51_PIN_SD2_CMD,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD2_CLK,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ /* SDHC2 Control lines IOMUX */
+ mxc_request_iomux(MX51_PIN_GPIO1_7,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_GPIO1_7,
+ PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
+ PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_request_iomux(MX51_PIN_GPIO1_8,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_GPIO1_8,
+ PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_SRE_FAST);
+
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8),
+ MXC_GPIO_DIRECTION_IN);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7),
+ MXC_GPIO_DIRECTION_IN);
+
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+ if (!ret)
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
+ } else { /* New boards use only SDHC1 */
+ /* SDHC1 IOMUX */
+ mxc_request_iomux(MX51_PIN_SD1_CMD,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_CLK,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
+ PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+ }
+ return ret;
+}
+#endif
+
+/*
+ * ATA
+ */
+#ifdef CONFIG_MX51_PATA
+#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH)
+void setup_iomux_ata(void)
+{
+ mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG);
+ mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG);
+}
+#else
+static inline void setup_iomux_ata(void) { }
+#endif
+
+/*
+ * LED configuration
+ */
+void setup_iomux_led(void)
+{
+ /* Blue LED */
+ mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
+ MXC_GPIO_DIRECTION_OUT);
+ /* Green LED */
+ mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
+ MXC_GPIO_DIRECTION_OUT);
+ /* Red LED */
+ mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3);
+ mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
+ MXC_GPIO_DIRECTION_OUT);
+}
+
+void efikamx_toggle_led(uint32_t mask)
+{
+ mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
+ mask & EFIKAMX_LED_BLUE);
+ mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
+ mask & EFIKAMX_LED_GREEN);
+ mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
+ mask & EFIKAMX_LED_RED);
+}
+
+/*
+ * Board initialization
+ */
+static void init_drive_strength(void)
+{
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
+
+ /* Setting pad options */
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+}
+
+int board_early_init_f(void)
+{
+ init_drive_strength();
+
+ setup_iomux_uart();
+ setup_iomux_spi();
+ setup_iomux_led();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_MX51_LANGE51;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setup_iomux_spi();
+
+ power_init();
+
+ setup_iomux_led();
+ setup_iomux_ata();
+
+ efikamx_toggle_led(EFIKAMX_LED_BLUE);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ u32 system_rev = get_cpu_rev();
+ u32 cause;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+ puts("Board: Efika MX ");
+
+ switch (system_rev & 0xff) {
+ case CHIP_REV_3_0:
+ puts("3.0 [");
+ break;
+ case CHIP_REV_2_5:
+ puts("2.5 [");
+ break;
+ case CHIP_REV_2_0:
+ puts("2.0 [");
+ break;
+ case CHIP_REV_1_1:
+ puts("1.1 [");
+ break;
+ case CHIP_REV_1_0:
+ default:
+ puts("1.0 [");
+ break;
+ }
+
+ cause = src_regs->srsr;
+ switch (cause) {
+ case 0x0001:
+ puts("POR");
+ break;
+ case 0x0009:
+ puts("RST");
+ break;
+ case 0x0010:
+ case 0x0011:
+ puts("WDOG");
+ break;
+ default:
+ printf("unknown 0x%x", cause);
+ }
+ puts("]\n");
+
+ return 0;
+}
--- /dev/null
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# BASED ON: imx51evk
+#
+# (C) Copyright 2009
+# Stefano Babic DENX Software Engineering sbabic@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
+BOOT_FROM spi
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type Address Value
+#
+# where:
+# Addr-type register length (1,2 or 4 bytes)
+# Address absolute address of the register
+# value value to be stored in the register
+
+# Setting IOMUXC
+DATA 4 0x73fa88a0 0x000
+DATA 4 0x73fa850c 0x20c5
+DATA 4 0x73fa8510 0x20c5
+DATA 4 0x73fa883c 0x5
+DATA 4 0x73fa8848 0x5
+DATA 4 0x73fa84b8 0xe7
+DATA 4 0x73fa84bc 0x45
+DATA 4 0x73fa84c0 0x45
+DATA 4 0x73fa84c4 0x45
+DATA 4 0x73fa84c8 0x45
+DATA 4 0x73fa8820 0x0
+DATA 4 0x73fa84a4 0x5
+DATA 4 0x73fa84a8 0x5
+DATA 4 0x73fa84ac 0xe5
+DATA 4 0x73fa84b0 0xe5
+DATA 4 0x73fa84b4 0xe5
+DATA 4 0x73fa84cc 0xe5
+DATA 4 0x73fa84d0 0xe4
+
+DATA 4 0x73fa882c 0x4
+DATA 4 0x73fa88a4 0x4
+DATA 4 0x73fa88ac 0x4
+DATA 4 0x73fa88b8 0x4
+
+# Setting DDR for micron
+# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+# CAS=3 BL=4
+# ESDCTL_ESDCTL0
+DATA 4 0x83fd9000 0x82a20000
+# ESDCTL_ESDCTL1
+DATA 4 0x83fd9008 0x82a20000
+# ESDCTL_ESDMISC
+DATA 4 0x83fd9010 0xcaaaf6d0
+# ESDCTL_ESDCFG0
+DATA 4 0x83fd9004 0x3f3574aa
+# ESDCTL_ESDCFG1
+DATA 4 0x83fd900c 0x3f3574aa
+
+# Init DRAM on CS0
+# ESDCTL_ESDSCR
+DATA 4 0x83fd9014 0x04008008
+DATA 4 0x83fd9014 0x0000801a
+DATA 4 0x83fd9014 0x0000801b
+DATA 4 0x83fd9014 0x00448019
+DATA 4 0x83fd9014 0x07328018
+DATA 4 0x83fd9014 0x04008008
+DATA 4 0x83fd9014 0x00008010
+DATA 4 0x83fd9014 0x00008010
+DATA 4 0x83fd9014 0x06328018
+DATA 4 0x83fd9014 0x03808019
+DATA 4 0x83fd9014 0x00408019
+DATA 4 0x83fd9014 0x00008000
+
+# Init DRAM on CS1
+DATA 4 0x83fd9014 0x0400800c
+DATA 4 0x83fd9014 0x0000801e
+DATA 4 0x83fd9014 0x0000801f
+DATA 4 0x83fd9014 0x0000801d
+DATA 4 0x83fd9014 0x0732801c
+DATA 4 0x83fd9014 0x0400800c
+DATA 4 0x83fd9014 0x00008014
+DATA 4 0x83fd9014 0x00008014
+DATA 4 0x83fd9014 0x0632801c
+DATA 4 0x83fd9014 0x0380801d
+DATA 4 0x83fd9014 0x0040801d
+DATA 4 0x83fd9014 0x00008004
+
+# Write to CTL0
+DATA 4 0x83fd9000 0xb2a20000
+# Write to CTL1
+DATA 4 0x83fd9008 0xb2a20000
+# ESDMISC
+DATA 4 0x83fd9010 0x000ad6d0
+#ESDCTL_ESDCDLYGD
+DATA 4 0x83fd9034 0x90000000
+DATA 4 0x83fd9014 0x00000000
actual_size = get_ram_size((void *)sdram_base, expected_size);
- gd->bd->bi_dram[0].start = sdram_base;
- gd->bd->bi_dram[0].size = actual_size;
+ gd->ram_size = actual_size;
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
--- /dev/null
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := mx35pdk.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/asm-offsets.h>
+#include "mx35pdk.h"
+
+/*
+ * return soc version
+ * 0x10: TO1
+ * 0x20: TO2
+ * 0x30: TO3
+ */
+.macro check_soc_version ret, tmp
+ ldr \tmp, =IIM_BASE_ADDR
+ ldr \ret, [\tmp, #IIM_SREV]
+ cmp \ret, #0x00
+ moveq \tmp, #ROMPATCH_REV
+ ldreq \ret, [\tmp]
+ moveq \ret, \ret, lsl #4
+ addne \ret, \ret, #0x10
+.endm
+
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.
+ */
+.macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, =AIPS1_BASE_ADDR
+ ldr r1, =AIPS_MPR_CONFIG
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, =AIPS2_BASE_ADDR
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+
+ /*
+ * Clear the on and off peripheral modules Supervisor Protect bit
+ * for SDMA to access them. Did not change the AIPS control registers
+ * (offset 0x20) access type
+ */
+ ldr r0, =AIPS1_BASE_ADDR
+ ldr r1, =AIPS_OPACR_CONFIG
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ str r1, [r0, #0x50]
+ ldr r0, =AIPS2_BASE_ADDR
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ str r1, [r0, #0x50]
+.endm
+
+/* MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+ ldr r0, =MAX_BASE_ADDR
+ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+ ldr r1, =MAX_MPR_CONFIG
+ str r1, [r0, #0x000] /* for S0 */
+ str r1, [r0, #0x100] /* for S1 */
+ str r1, [r0, #0x200] /* for S2 */
+ str r1, [r0, #0x300] /* for S3 */
+ str r1, [r0, #0x400] /* for S4 */
+ /* SGPCR - always park on last master */
+ ldr r1, =MAX_SGPCR_CONFIG
+ str r1, [r0, #0x010] /* for S0 */
+ str r1, [r0, #0x110] /* for S1 */
+ str r1, [r0, #0x210] /* for S2 */
+ str r1, [r0, #0x310] /* for S3 */
+ str r1, [r0, #0x410] /* for S4 */
+ /* MGPCR - restore default values */
+ ldr r1, =MAX_MGPCR_CONFIG
+ str r1, [r0, #0x800] /* for M0 */
+ str r1, [r0, #0x900] /* for M1 */
+ str r1, [r0, #0xA00] /* for M2 */
+ str r1, [r0, #0xB00] /* for M3 */
+ str r1, [r0, #0xC00] /* for M4 */
+ str r1, [r0, #0xD00] /* for M5 */
+.endm
+
+/* M3IF setup */
+.macro init_m3if
+ /* Configure M3IF registers */
+ ldr r1, =M3IF_BASE_ADDR
+ /*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+ ldr r0, =M3IF_CONFIG
+ str r0, [r1] /* M3IF control reg */
+.endm
+
+/* CPLD on CS5 setup */
+.macro init_debug_board
+ ldr r0, =DBG_BASE_ADDR
+ ldr r1, =DBG_CSCR_U_CONFIG
+ str r1, [r0, #0x00]
+ ldr r1, =DBG_CSCR_L_CONFIG
+ str r1, [r0, #0x04]
+ ldr r1, =DBG_CSCR_A_CONFIG
+ str r1, [r0, #0x08]
+.endm
+
+/* clock setup */
+.macro init_clock
+ ldr r0, =CCM_BASE_ADDR
+
+ /* default CLKO to 1/32 of the ARM core*/
+ ldr r1, [r0, #CLKCTL_COSR]
+ bic r1, r1, #0x00000FF00
+ bic r1, r1, #0x0000000FF
+ mov r2, #0x00006C00
+ add r2, r2, #0x67
+ orr r1, r1, r2
+ str r1, [r0, #CLKCTL_COSR]
+
+ ldr r2, =CCM_CCMR_CONFIG
+ str r2, [r0, #CLKCTL_CCMR]
+
+ check_soc_version r1, r2
+ cmp r1, #CHIP_REV_2_0
+ ldrhs r3, =CCM_MPLL_532_HZ
+ bhs 1f
+ ldr r2, [r0, #CLKCTL_PDR0]
+ tst r2, #CLKMODE_CONSUMER
+ ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
+ ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
+1:
+ str r3, [r0, #CLKCTL_MPCTL]
+
+ ldr r1, =CCM_PPLL_300_HZ
+ str r1, [r0, #CLKCTL_PPCTL]
+
+ ldr r1, =CCM_PDR0_CONFIG
+ bic r1, r1, #0x800000
+ str r1, [r0, #CLKCTL_PDR0]
+
+ ldr r1, [r0, #CLKCTL_CGR0]
+ orr r1, r1, #0x0C300000
+ str r1, [r0, #CLKCTL_CGR0]
+
+ ldr r1, [r0, #CLKCTL_CGR1]
+ orr r1, r1, #0x00000C00
+ orr r1, r1, #0x00000003
+ str r1, [r0, #CLKCTL_CGR1]
+.endm
+
+.macro setup_sdram
+ ldr r0, =ESDCTL_BASE_ADDR
+ mov r3, #0x2000
+ str r3, [r0, #0x0]
+ str r3, [r0, #0x8]
+
+ /*ip(r12) has used to save lr register in upper calling*/
+ mov fp, lr
+
+ mov r5, #0x00
+ mov r2, #0x00
+ mov r1, #CSD0_BASE_ADDR
+ bl setup_sdram_bank
+ cmp r3, #0x0
+ orreq r5, r5, #1
+ eorne r2, r2, #0x1
+ blne setup_sdram_bank
+
+ mov lr, fp
+
+1:
+ ldr r3, =ESDCTL_DELAY_LINE5
+ str r3, [r0, #0x30]
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+ mov r10, lr
+
+ mrc 15, 0, r1, c1, c0, 0
+
+ mrc 15, 0, r0, c1, c0, 1
+ orr r0, r0, #7
+ mcr 15, 0, r0, c1, c0, 1
+ orr r1, r1, #(1<<11)
+
+ /* Set unaligned access enable */
+ orr r1, r1, #(1<<22)
+
+ /* Set low int latency enable */
+ orr r1, r1, #(1<<21)
+
+ mcr 15, 0, r1, c1, c0, 0
+
+ mov r0, #0
+
+ /* Set branch prediction enable */
+ mcr 15, 0, r0, c15, c2, 4
+
+ mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
+ mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
+
+ /*
+ * initializes very early AIPS
+ * Then it also initializes Multi-Layer AHB Crossbar Switch,
+ * M3IF
+ * Also setup the Peripheral Port Remap register inside the core
+ */
+ ldr r0, =0x40000015 /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ init_clock
+ init_debug_board
+
+ cmp pc, #PHYS_SDRAM_1
+ blo init_sdram_start
+ cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
+ blo skip_sdram_setup
+
+init_sdram_start:
+ /*init_sdram*/
+ setup_sdram
+
+skip_sdram_setup:
+ mov lr, r10
+ mov pc, lr
+
+
+/*
+ * r0: ESDCTL control base, r1: sdram slot base
+ * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
+ */
+setup_sdram_bank:
+ mov r3, #0xE
+ tst r2, #0x1
+ orreq r3, r3, #0x300 /*DDR2*/
+ str r3, [r0, #0x10]
+ bic r3, r3, #0x00A
+ str r3, [r0, #0x10]
+ beq 2f
+
+ mov r3, #0x20000
+1: subs r3, r3, #1
+ bne 1b
+
+2: tst r2, #0x1
+ ldreq r3, =ESDCTL_DDR2_CONFIG
+ ldrne r3, =ESDCTL_MDDR_CONFIG
+ cmp r1, #CSD1_BASE_ADDR
+ strlo r3, [r0, #0x4]
+ strhs r3, [r0, #0xC]
+
+ ldr r3, =ESDCTL_0x92220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ ldr r4, =ESDCTL_PRECHARGE
+ strb r3, [r1, r4]
+
+ tst r2, #0x1
+ bne skip_set_mode
+
+ cmp r1, #CSD1_BASE_ADDR
+ ldr r3, =ESDCTL_0xB2220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ ldr r4, =ESDCTL_DDR2_EMR2
+ strb r3, [r1, r4]
+ ldr r4, =ESDCTL_DDR2_EMR3
+ strb r3, [r1, r4]
+ ldr r4, =ESDCTL_DDR2_EN_DLL
+ strb r3, [r1, r4]
+ ldr r4, =ESDCTL_DDR2_RESET_DLL
+ strb r3, [r1, r4]
+
+ ldr r3, =ESDCTL_0x92220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ ldr r4, =ESDCTL_PRECHARGE
+ strb r3, [r1, r4]
+
+skip_set_mode:
+ cmp r1, #CSD1_BASE_ADDR
+ ldr r3, =ESDCTL_0xA2220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ strb r3, [r1]
+ strb r3, [r1]
+
+ ldr r3, =ESDCTL_0xB2220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ tst r2, #0x1
+ ldreq r4, =ESDCTL_DDR2_MR
+ ldrne r4, =ESDCTL_MDDR_MR
+ mov r3, #0xDA
+ strb r3, [r1, r4]
+ ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
+ streqb r3, [r1, r4]
+ ldreq r4, =ESDCTL_DDR2_EN_DLL
+ ldrne r4, =ESDCTL_MDDR_EMR
+ strb r3, [r1, r4]
+
+ cmp r1, #CSD1_BASE_ADDR
+ ldr r3, =ESDCTL_0x82228080
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+
+ tst r2, #0x1
+ moveq r4, #0x20000
+ movne r4, #0x200
+1: subs r4, r4, #1
+ bne 1b
+
+ str r3, [r1, #0x100]
+ ldr r4, [r1, #0x100]
+ cmp r3, r4
+ movne r3, #1
+ moveq r3, #0
+
+ mov pc, lr
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <fsl_pmic.h>
+#include <mc9sdz60.h>
+#include <mc13892.h>
+#include <linux/types.h>
+#include <mxc_gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+
+#ifndef BOARD_LATE_INIT
+#error "BOARD_LATE_INIT must be set for this board"
+#endif
+
+#ifndef CONFIG_BOARD_EARLY_INIT_F
+#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
+#endif
+
+#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+static void setup_iomux_i2c(void)
+{
+ int pad;
+
+ /* setup pins for I2C1 */
+ mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
+
+ pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
+ | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
+
+ mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
+ mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+}
+
+
+static void setup_iomux_spi(void)
+{
+ mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+}
+
+static void setup_iomux_fec(void)
+{
+ int pad;
+
+ /* setup pins for FEC */
+ mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+
+ pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \
+ PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW);
+
+ mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \
+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+}
+
+int board_early_init_f(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ /* enable clocks */
+ writel(readl(&ccm->cgr0) |
+ MXC_CCM_CGR0_EMI_MASK |
+ MXC_CCM_CGR0_EDI0_MASK |
+ MXC_CCM_CGR0_EPIT1_MASK,
+ &ccm->cgr0);
+
+ writel(readl(&ccm->cgr1) |
+ MXC_CCM_CGR1_FEC_MASK |
+ MXC_CCM_CGR1_GPIO1_MASK |
+ MXC_CCM_CGR1_GPIO2_MASK |
+ MXC_CCM_CGR1_GPIO3_MASK |
+ MXC_CCM_CGR1_I2C1_MASK |
+ MXC_CCM_CGR1_I2C2_MASK |
+ MXC_CCM_CGR1_IPU_MASK,
+ &ccm->cgr1);
+
+ /* Setup NAND */
+ __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+ setup_iomux_i2c();
+ setup_iomux_fec();
+ setup_iomux_spi();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+static inline int pmic_detect(void)
+{
+ int id;
+
+ id = pmic_reg_read(REG_IDENTIFICATION);
+
+ id = (id >> 6) & 0x7;
+ if (id == 0x7)
+ return 1;
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ int rev;
+
+ rev = pmic_detect();
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+int board_late_init(void)
+{
+ u8 val;
+ u32 pmic_val;
+
+ if (pmic_detect()) {
+ mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
+ MUX_CONFIG_ALT1);
+
+ pmic_val = pmic_reg_read(REG_SETTING_0);
+ pmic_reg_write(REG_SETTING_0, pmic_val | VO_1_30V | VO_1_50V);
+ pmic_val = pmic_reg_read(REG_MODE_0);
+ pmic_reg_write(REG_MODE_0, pmic_val | VGEN3EN);
+
+ mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
+ mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
+
+ mxc_gpio_direction(37, MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_set(37, 1);
+ }
+
+ val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
+ mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
+ mdelay(200);
+
+ val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
+ mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
+ mdelay(200);
+
+ val |= 0x80;
+ mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+ u32 cpu_rev = get_cpu_rev();
+
+ /*
+ * Be sure that I2C is initialized to check
+ * the board revision
+ */
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ /* Print board revision */
+ printf("Board: MX35 PDK %d.0 ", ((get_board_rev() >> 8) + 1) & 0x0F);
+
+ /* Print CPU revision */
+ printf("i.MX35 %d.%d [", (cpu_rev & 0xF0) >> 4, cpu_rev & 0x0F);
+
+ switch (readl(&ccm->rcsr) & 0x0F) {
+ case 0x0000:
+ puts("POR");
+ break;
+ case 0x0002:
+ puts("JTAG");
+ break;
+ case 0x0004:
+ puts("RST");
+ break;
+ case 0x0008:
+ puts("WDT");
+ break;
+ default:
+ puts("unknown");
+ }
+ puts("]\n");
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+#if defined(CONFIG_SMC911X)
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+
+ cpu_eth_init(bis);
+
+ return rc;
+}
--- /dev/null
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BOARD_MX35_3STACK_H
+#define __BOARD_MX35_3STACK_H
+
+#define AIPS_MPR_CONFIG 0x77777777
+#define AIPS_OPACR_CONFIG 0x00000000
+
+/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_MPR_CONFIG 0x00302154
+/* SGPCR - always park on last master */
+#define MAX_SGPCR_CONFIG 0x00000010
+/* MGPCR - restore default values */
+#define MAX_MGPCR_CONFIG 0x00000000
+
+/*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+#define M3IF_CONFIG 0x00000040
+
+#define DBG_BASE_ADDR WEIM_CTRL_CS5
+#define DBG_CSCR_U_CONFIG 0x0000D843
+#define DBG_CSCR_L_CONFIG 0x22252521
+#define DBG_CSCR_A_CONFIG 0x22220A00
+
+#define CCM_CCMR_CONFIG 0x003F4208
+#define CCM_PDR0_CONFIG 0x00801000
+
+#define PLL_BRM_OFFSET 31
+#define PLL_PD_OFFSET 26
+#define PLL_MFD_OFFSET 16
+#define PLL_MFI_OFFSET 10
+
+#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET)
+#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET)
+#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET)
+#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET)
+#define _PLL_MFN(x) (x)
+#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
+ (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
+ _PLL_MFN(mfn))
+
+#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1)
+#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
+#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
+
+/* MEMORY SETTING */
+#define ESDCTL_0x92220000 0x92220000
+#define ESDCTL_0xA2220000 0xA2220000
+#define ESDCTL_0xB2220000 0xB2220000
+#define ESDCTL_0x82228080 0x82228080
+
+#define ESDCTL_PRECHARGE 0x00000400
+
+#define ESDCTL_MDDR_CONFIG 0x007FFC3F
+#define ESDCTL_MDDR_MR 0x00000033
+#define ESDCTL_MDDR_EMR 0x02000000
+
+#define ESDCTL_DDR2_CONFIG 0x007FFC3F
+#define ESDCTL_DDR2_EMR2 0x04000000
+#define ESDCTL_DDR2_EMR3 0x06000000
+#define ESDCTL_DDR2_EN_DLL 0x02000400
+#define ESDCTL_DDR2_RESET_DLL 0x00000333
+#define ESDCTL_DDR2_MR 0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+
+#define ESDCTL_DELAY_LINE5 0x00F49F00
+#endif /* __BOARD_MX35_3STACK_H */
/* Set core voltage to 1.1V */
val = pmic_reg_read(REG_SW_0);
- val = (val & (~0x1F)) | 0x14;
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
pmic_reg_write(REG_SW_0, val);
/* Setup VCC (SW2) to 1.25 */
val = pmic_reg_read(REG_SW_1);
- val = (val & (~0x1F)) | 0x1A;
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
pmic_reg_write(REG_SW_1, val);
/* Setup 1V2_DIG1 (SW3) to 1.25 */
val = pmic_reg_read(REG_SW_2);
- val = (val & (~0x1F)) | 0x1A;
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
pmic_reg_write(REG_SW_2, val);
udelay(50);
}
#endif
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_fec();
+
+ return 0;
+}
+
int board_init(void)
{
system_rev = get_cpu_rev();
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- setup_iomux_uart();
- setup_iomux_fec();
-
return 0;
}
--- /dev/null
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := mx53evk.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
+ALL += $(obj)u-boot.imx
--- /dev/null
+#
+# (C Copyright 2009
+# Stefano Babic DENX Software Engineering sbabic@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# image version
+
+IMAGE_VERSION 2
+
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
+
+BOOT_FROM sd
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type Address Value
+#
+# where:
+# Addr-type register length (1,2 or 4 bytes)
+# Address absolute address of the register
+# value value to be stored in the register
+
+# Setting IOMUXC
+DATA 4 0x53fa8554 0x00200000
+DATA 4 0x53fa8560 0x00200000
+DATA 4 0x53fa8594 0x00200000
+DATA 4 0x53fa8584 0x00200000
+DATA 4 0x53fa8558 0x00200040
+DATA 4 0x53fa8568 0x00200040
+DATA 4 0x53fa8590 0x00200040
+DATA 4 0x53fa857c 0x00200040
+DATA 4 0x53fa8564 0x00200040
+DATA 4 0x53fa8580 0x00200040
+DATA 4 0x53fa8570 0x00200000
+DATA 4 0x53fa8578 0x00200000
+DATA 4 0x53fa872c 0x00200000
+DATA 4 0x53fa8728 0x00200000
+DATA 4 0x53fa871c 0x00200000
+DATA 4 0x53fa8718 0x00200000
+DATA 4 0x53fa8574 0x00280000
+DATA 4 0x53fa8588 0x00280000
+DATA 4 0x53fa86f0 0x00280000
+DATA 4 0x53fa8720 0x00280000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa86f4 0x00000200
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8724 0x06000000
+DATA 4 0x63fd9088 0x34333936
+DATA 4 0x63fd9090 0x49434942
+DATA 4 0x63fd90F8 0x00000800
+DATA 4 0x63fd907c 0x01350138
+DATA 4 0x63fd9080 0x01380139
+DATA 4 0x63fd9018 0x00001710
+DATA 4 0x63fd9000 0xc4110000
+DATA 4 0x63fd900C 0x4d5122d2
+DATA 4 0x63fd9010 0x92d18a22
+DATA 4 0x63fd9014 0x00c70092
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f000e
+DATA 4 0x63fd9008 0x12272000
+DATA 4 0x63fd9004 0x00030012
+DATA 4 0x63fd901c 0x04008010
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00008031
+DATA 4 0x63fd901c 0x0b5280b0
+DATA 4 0x63fd901c 0x04008010
+DATA 4 0x63fd901c 0x00008020
+DATA 4 0x63fd901c 0x00008020
+DATA 4 0x63fd901c 0x0a528030
+DATA 4 0x63fd901c 0x03c68031
+DATA 4 0x63fd901c 0x00448031
+DATA 4 0x63fd901c 0x04008018
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00008039
+DATA 4 0x63fd901c 0x0b528138
+DATA 4 0x63fd901c 0x04008018
+DATA 4 0x63fd901c 0x00008028
+DATA 4 0x63fd901c 0x00008028
+DATA 4 0x63fd901c 0x0a528038
+DATA 4 0x63fd901c 0x03c68039
+DATA 4 0x63fd901c 0x00448039
+DATA 4 0x63fd9020 0x00005800
+DATA 4 0x63fd9058 0x00033335
+DATA 4 0x63fd901c 0x00000000
+DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x53fa8004 0x00194005
--- /dev/null
+/*
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/errno.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <fsl_pmic.h>
+#include <mxc_gpio.h>
+#include <mc13892.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+ /* UART1 RXD */
+ mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
+
+ /* UART1 TXD */
+ mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE);
+}
+
+static void setup_i2c(unsigned int port_number)
+{
+ switch (port_number) {
+ case 0:
+ /* i2c1 SDA */
+ mxc_request_iomux(MX53_PIN_CSI0_D8,
+ IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+ mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
+ PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+ PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ /* i2c1 SCL */
+ mxc_request_iomux(MX53_PIN_CSI0_D9,
+ IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+ mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
+ PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+ PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ break;
+ case 1:
+ /* i2c2 SDA */
+ mxc_request_iomux(MX53_PIN_KEY_ROW3,
+ IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+ mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
+ PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+ PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE);
+
+ /* i2c2 SCL */
+ mxc_request_iomux(MX53_PIN_KEY_COL3,
+ IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+ mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
+ PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+ PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ break;
+ default:
+ printf("Warning: Wrong I2C port number\n");
+ break;
+ }
+}
+
+void power_init(void)
+{
+ unsigned int val;
+
+ /* Set VDDA to 1.25V */
+ val = pmic_reg_read(REG_SW_2);
+ val &= ~SWX_OUT_MASK;
+ val |= SWX_OUT_1_25;
+ pmic_reg_write(REG_SW_2, val);
+
+ /*
+ * Need increase VCC and VDDA to 1.3V
+ * according to MX53 IC TO2 datasheet.
+ */
+ if (is_soc_rev(CHIP_REV_2_0) == 0) {
+ /* Set VCC to 1.3V for TO2 */
+ val = pmic_reg_read(REG_SW_1);
+ val &= ~SWX_OUT_MASK;
+ val |= SWX_OUT_1_30;
+ pmic_reg_write(REG_SW_1, val);
+
+ /* Set VDDA to 1.3V for TO2 */
+ val = pmic_reg_read(REG_SW_2);
+ val &= ~SWX_OUT_MASK;
+ val |= SWX_OUT_1_30;
+ pmic_reg_write(REG_SW_2, val);
+ }
+}
+
+static void setup_iomux_fec(void)
+{
+ /*FEC_MDIO*/
+ mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
+
+ /*FEC_MDC*/
+ mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
+
+ /* FEC RXD1 */
+ mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+ /* FEC RXD0 */
+ mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+ /* FEC TXD1 */
+ mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
+
+ /* FEC TXD0 */
+ mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
+
+ /* FEC TX_EN */
+ mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
+
+ /* FEC TX_CLK */
+ mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+ /* FEC RX_ER */
+ mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+ /* FEC CRS */
+ mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {MMC_SDHC1_BASE_ADDR, 1},
+ {MMC_SDHC3_BASE_ADDR, 1},
+};
+
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+ *cd = mxc_gpio_get(77); /*GPIO3_13*/
+ else
+ *cd = mxc_gpio_get(75); /*GPIO3_11*/
+
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ u32 index;
+ s32 status = 0;
+
+ for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
+ switch (index) {
+ case 0:
+ mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_DATA0,
+ IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_DATA1,
+ IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_DATA2,
+ IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_DATA3,
+ IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_EIM_DA13,
+ IOMUX_CONFIG_ALT1);
+
+ mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+ PAD_CTL_DRV_HIGH);
+ mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ break;
+ case 1:
+ mxc_request_iomux(MX53_PIN_ATA_RESET_B,
+ IOMUX_CONFIG_ALT2);
+ mxc_request_iomux(MX53_PIN_ATA_IORDY,
+ IOMUX_CONFIG_ALT2);
+ mxc_request_iomux(MX53_PIN_ATA_DATA8,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA9,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA10,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA11,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA0,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA1,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA2,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA3,
+ IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_EIM_DA11,
+ IOMUX_CONFIG_ALT1);
+
+ mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+ PAD_CTL_DRV_HIGH);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+
+ break;
+ default:
+ printf("Warning: you configured more ESDHC controller"
+ "(%d) as supported by the board(2)\n",
+ CONFIG_SYS_FSL_ESDHC_NUM);
+ return status;
+ }
+ status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ }
+
+ return status;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_fec();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK;
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setup_i2c(1);
+ power_init();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ u32 cause;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+ puts("Board: MX53EVK [");
+
+ cause = src_regs->srsr;
+ switch (cause) {
+ case 0x0001:
+ printf("POR");
+ break;
+ case 0x0009:
+ printf("RST");
+ break;
+ case 0x0010:
+ case 0x0011:
+ printf("WDOG");
+ break;
+ default:
+ printf("unknown");
+ }
+ printf("]\n");
+ return 0;
+}
--- /dev/null
+#
+# Copyright (C) 2010 Samsung Electronics
+# Minkyu Kang <mk7.kang@samsung.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y := universal.o onenand.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(SOBJS) $(OBJS)
+ $(call cmd_link_o_target, $(SOBJS) $(OBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Lowlevel setup for universal board based on S5PC210
+ *
+ * Copyright (C) 2010 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ * r7 has GPIO part1 base 0x11400000
+ * r6 has GPIO part2 base 0x11000000
+ */
+
+ .globl lowlevel_init
+lowlevel_init:
+ mov r11, lr
+
+ /* r5 has always zero */
+ mov r5, #0
+
+ ldr r7, =S5PC210_GPIO_PART1_BASE
+ ldr r6, =S5PC210_GPIO_PART2_BASE
+
+ /* System Timer */
+ ldr r0, =S5PC210_SYSTIMER_BASE
+ ldr r1, =0x5000
+ str r1, [r0, #0x0]
+ ldr r1, =0xffffffff
+ str r1, [r0, #0x8]
+ ldr r1, =0x49
+ str r1, [r0, #0x4]
+
+ /* PMIC manual reset */
+ /* nPOWER: XEINT_23: GPX2[7] */
+ add r0, r6, #0xC40 @ S5PC210_GPIO_X2_OFFSET
+ ldr r1, [r0, #0x0]
+ bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
+ orr r1, r1, #(0x1 << 28) @ Output
+ str r1, [r0, #0x0]
+
+ ldr r1, [r0, #0x4]
+ orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
+ str r1, [r0, #0x4]
+
+ /* init system clock */
+ bl system_clock_init
+
+ /* Disable Watchdog */
+ ldr r0, =S5PC210_WATCHDOG_BASE @0x10060000
+ str r5, [r0]
+
+ /* UART */
+ bl uart_asm_init
+
+ /* PMU init */
+ bl system_power_init
+
+ bl tzpc_init
+
+ mov lr, r11
+ mov pc, lr
+ nop
+ nop
+ nop
+
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+ /*
+ * setup UART0-UART4 GPIOs (part1)
+ * GPA1CON[3] = I2C_3_SCL (3)
+ * GPA1CON[2] = I2C_3_SDA (3)
+ */
+ mov r0, r7
+ ldr r1, =0x22222222
+ str r1, [r0, #0x00] @ S5PC210_GPIO_A0_OFFSET
+ ldr r1, =0x00223322
+ str r1, [r0, #0x20] @ S5PC210_GPIO_A1_OFFSET
+
+ /* UART_SEL GPY4[7] (part2) at S5PC210 */
+ add r0, r6, #0x1A0 @ S5PC210_GPIO_Y4_OFFSET
+ ldr r1, [r0, #0x0]
+ bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
+ orr r1, r1, #(0x1 << 28)
+ str r1, [r0, #0x0]
+
+ ldr r1, [r0, #0x8]
+ bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
+ orr r1, r1, #(0x3 << 14) @ Pull-up enabled
+ str r1, [r0, #0x8]
+
+ ldr r1, [r0, #0x4]
+ orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
+ str r1, [r0, #0x4]
+
+ mov pc, lr
+ nop
+ nop
+ nop
+
+system_clock_init:
+ ldr r0, =S5PC210_CLOCK_BASE
+
+ /* APLL(1), MPLL(1), CORE(0), HPM(0) */
+ ldr r1, =0x0101
+ ldr r2, =0x14200 @ CLK_SRC_CPU
+ str r1, [r0, r2]
+
+ /* wait ?us */
+ mov r1, #0x10000
+1: subs r1, r1, #1
+ bne 1b
+
+ /*
+ * CLK_SRC_TOP0
+ * MUX_ONENAND_SEL[28] 0: DOUT133, 1: DOUT166
+ * MUX_VPLL_SEL[8] 0: FINPLL, 1: FOUTVPLL
+ * MUX_EPLL_SEL[4] 0: FINPLL, 1: FOUTEPLL
+ */
+ ldr r1, =0x10000110
+ ldr r2, =0x0C210 @ CLK_SRC_TOP
+ str r1, [r0, r2]
+
+ /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
+ ldr r1, =0x0066666
+ ldr r2, =0x0C240 @ CLK_SRC_FSYS
+ str r1, [r0, r2]
+ /* UART[0:5], PWM: SCLKMPLL(6) */
+ ldr r1, =0x6666666
+ ldr r2, =0x0C250 @ CLK_SRC_PERIL0_OFFSET
+ str r1, [r0, r2]
+
+ /* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */
+ ldr r1, =0x0133730
+ ldr r2, =0x14500 @ CLK_DIV_CPU0
+ str r1, [r0, r2]
+ /* CPU1: COPY, HPM */
+ ldr r1, =0x03
+ ldr r2, =0x14504 @ CLK_DIV_CPU1
+ str r1, [r0, r2]
+ /* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */
+ ldr r1, =0x13111113
+ ldr r2, =0x10500 @ CLK_DIV_DMC0
+ str r1, [r0, r2]
+ /* DMC1: PWI, DVSEM, DPM */
+ ldr r1, =0x01010100
+ ldr r2, =0x10504 @ CLK_DIV_DMC1
+ str r1, [r0, r2]
+ /* LEFTBUS: GDL, GPL */
+ ldr r1, =0x13
+ ldr r2, =0x04500 @ CLK_DIV_LEFTBUS
+ str r1, [r0, r2]
+ /* RIGHHTBUS: GDR, GPR */
+ ldr r1, =0x13
+ ldr r2, =0x08500 @ CLK_DIV_RIGHTBUS
+ str r1, [r0, r2]
+ /*
+ * CLK_DIV_TOP
+ * ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1)
+ * ACLK_200, ACLK_100, ACLK_160, ACLK_133,
+ */
+ ldr r1, =0x00005473
+ ldr r2, =0x0C510 @ CLK_DIV_TOP
+ str r1, [r0, r2]
+ /* MMC[0:1] */
+ ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
+ ldr r2, =0x0C544 @ CLK_DIV_FSYS1
+ str r1, [r0, r2]
+ /* MMC[2:3] */
+ ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
+ ldr r2, =0x0C548 @ CLK_DIV_FSYS2
+ str r1, [r0, r2]
+ /* MMC4 */
+ ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */
+ ldr r2, =0x0C54C @ CLK_DIV_FSYS3
+ str r1, [r0, r2]
+ /* UART[0:5] */
+ ldr r1, =0x774777
+ ldr r2, =0x0C550 @ CLK_DIV_PERIL0
+ str r1, [r0, r2]
+ /* SLIMBUS: ???, PWM */
+ ldr r1, =0x8
+ ldr r2, =0x0C55C @ CLK_DIV_PERIL3
+ str r1, [r0, r2]
+
+ /* PLL Setting */
+ ldr r1, =0x1C20
+ ldr r2, =0x14000 @ APLL_LOCK
+ str r1, [r0, r2]
+ ldr r2, =0x14008 @ MPLL_LOCK
+ str r1, [r0, r2]
+ ldr r2, =0x0C010 @ EPLL_LOCK
+ str r1, [r0, r2]
+ ldr r2, =0x0C020 @ VPLL_LOCK
+ str r1, [r0, r2]
+
+ /* APLL */
+ ldr r1, =0x8000001c
+ ldr r2, =0x14104 @ APLL_CON1
+ str r1, [r0, r2]
+ ldr r1, =0x80c80601 @ 800MHz
+ ldr r2, =0x14100 @ APLL_CON0
+ str r1, [r0, r2]
+ /* MPLL */
+ ldr r1, =0x8000001C
+ ldr r2, =0x1410C @ MPLL_CON1
+ str r1, [r0, r2]
+ ldr r1, =0x80c80601 @ 800MHz
+ ldr r2, =0x14108 @ MPLL_CON0
+ str r1, [r0, r2]
+ /* EPLL */
+ ldr r1, =0x0
+ ldr r2, =0x0C114 @ EPLL_CON1
+ str r1, [r0, r2]
+ ldr r1, =0x80300302 @ 96MHz
+ ldr r2, =0x0C110 @ EPLL_CON0
+ str r1, [r0, r2]
+ /* VPLL */
+ ldr r1, =0x11000400
+ ldr r2, =0x0C124 @ VPLL_CON1
+ str r1, [r0, r2]
+ ldr r1, =0x80350302 @ 108MHz
+ ldr r2, =0x0C120 @ VPLL_CON0
+ str r1, [r0, r2]
+
+ /*
+ * SMMUJPEG[11], JPEG[6], CSIS1[5] : 0111 1001
+ * Turn off all
+ */
+ ldr r1, =0xFFF80000
+ ldr r2, =0x0C920 @ CLK_GATE_IP_CAM
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFFC0
+ ldr r2, =0x0C924 @ CLK_GATE_IP_VP
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFFE0
+ ldr r2, =0x0C928 @ CLK_GATE_IP_MFC
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFFFC
+ ldr r2, =0x0C92C @ CLK_GATE_IP_G3D
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFC00
+ ldr r2, =0x0C930 @ CLK_GATE_IP_IMAGE
+ str r1, [r0, r2]
+
+ /* DSIM0[3], MDNIE0[2], MIE0[1] : 0001 */
+ ldr r1, =0xFFFFFFF1
+ ldr r2, =0x0C934 @ CLK_GATE_IP_LCD0
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFFC0
+ ldr r2, =0x0C938 @ CLK_GATE_IP_LCD1
+ str r1, [r0, r2]
+
+ /*
+ * SMMUPCIE[18], NFCON[16] : 1111 1010
+ * PCIE[14], SATA[10], SDMMC43[9:8] : 1011 1000
+ * SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2] : 1010 0011
+ */
+ ldr r1, =0xFFFAB8A3
+ ldr r2, =0x0C940 @ CLK_GATE_IP_FSYS
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFFFC
+ ldr r2, =0x0C94C @ CLK_GATE_IP_GPS
+ str r1, [r0, r2]
+
+ /*
+ * AC97[27], SPDIF[26], SLIMBUS[25] : 1111 0001
+ * I2C2[8] : 1111 1110
+ */
+ ldr r1, =0xF1FFFEFF
+ ldr r2, =0x0C950 @ CLK_GATE_IP_PERIL
+ str r1, [r0, r2]
+
+ /*
+ * KEYIF[16] : 1111 1110
+ */
+ ldr r1, =0xFFFEFFFF
+ ldr r2, =0x0C960 @ CLK_GATE_IP_PERIR
+ str r1, [r0, r2]
+
+ /* LCD1[5], G3D[3], MFC[2], TV[1] : 1101 0001 */
+ ldr r1, =0xFFFFFFD1
+ ldr r2, =0x0C970 @ CLK_GATE_BLOCK
+ str r1, [r0, r2]
+ mov pc, lr
+ nop
+ nop
+ nop
+
+system_power_init:
+ ldr r0, =S5PC210_POWER_BASE @ 0x10020000
+
+ ldr r2, =0x330C @ PS_HOLD_CONTROL
+ ldr r1, [r0, r2]
+ orr r1, r1, #(0x3 << 8) @ Data High, Output En
+ str r1, [r0, r2]
+
+ /* Power Down */
+ add r2, r0, #0x3000
+ str r5, [r2, #0xC20] @ TV_CONFIGURATION
+ str r5, [r2, #0xC40] @ MFC_CONFIGURATION
+ str r5, [r2, #0xC60] @ G3D_CONFIGURATION
+ str r5, [r2, #0xCA0] @ LCD1_CONFIGURATION
+ str r5, [r2, #0xCE0] @ GPS_CONFIGURATION
+
+ mov pc, lr
+ nop
+ nop
+ nop
+
+tzpc_init:
+ ldr r0, =0x10110000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x0804]
+ str r1, [r0, #0x0810]
+ str r1, [r0, #0x081C]
+ str r1, [r0, #0x0828]
+
+ ldr r0, =0x10120000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x0804]
+ str r1, [r0, #0x0810]
+ str r1, [r0, #0x081C]
+ str r1, [r0, #0x0828]
+
+ ldr r0, =0x10130000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x0804]
+ str r1, [r0, #0x0810]
+ str r1, [r0, #0x081C]
+ str r1, [r0, #0x0828]
+
+ ldr r0, =0x10140000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x0804]
+ str r1, [r0, #0x0810]
+ str r1, [r0, #0x081C]
+ str r1, [r0, #0x0828]
+
+ ldr r0, =0x10150000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x0804]
+ str r1, [r0, #0x0810]
+ str r1, [r0, #0x081C]
+ str r1, [r0, #0x0828]
+
+ mov pc, lr
--- /dev/null
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+
+ this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+ this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
+}
--- /dev/null
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/adc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct s5pc210_gpio_part1 *gpio1;
+struct s5pc210_gpio_part2 *gpio2;
+unsigned int board_rev;
+
+u32 get_board_rev(void)
+{
+ return board_rev;
+}
+
+static int get_hwrev(void)
+{
+ return board_rev & 0xFF;
+}
+
+static void check_hw_revision(void);
+
+int board_init(void)
+{
+ gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
+ gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+
+ gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ check_hw_revision();
+ printf("HW Revision:\t0x%x\n", board_rev);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
+static unsigned short get_adc_value(int channel)
+{
+ struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc();
+ unsigned short ret = 0;
+ unsigned int reg;
+ unsigned int loop = 0;
+
+ writel(channel & 0xF, &adc->adcmux);
+ writel((1 << 14) | (49 << 6), &adc->adccon);
+ writel(1000 & 0xffff, &adc->adcdly);
+ writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */
+ udelay(10);
+ writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */
+ udelay(10);
+
+ do {
+ udelay(1);
+ reg = readl(&adc->adccon);
+ } while (!(reg & (1 << 15)) && (loop++ < 1000));
+
+ ret = readl(&adc->adcdat0) & 0xFFF;
+
+ return ret;
+}
+
+static unsigned int get_hw_revision(void)
+{
+ int hwrev, mode0, mode1;
+
+ mode0 = get_adc_value(1); /* HWREV_MODE0 */
+ mode1 = get_adc_value(2); /* HWREV_MODE1 */
+
+ /*
+ * XXX Always set the default hwrev as the latest board
+ * ADC = (voltage) / 3.3 * 4096
+ */
+ hwrev = 3;
+
+#define IS_RANGE(x, min, max) ((x) > (min) && (x) < (max))
+ if (IS_RANGE(mode0, 80, 200) && IS_RANGE(mode1, 80, 200))
+ hwrev = 0x0; /* 0.01V 0.01V */
+ if (IS_RANGE(mode0, 750, 1000) && IS_RANGE(mode1, 80, 200))
+ hwrev = 0x1; /* 610mV 0.01V */
+ if (IS_RANGE(mode0, 1300, 1700) && IS_RANGE(mode1, 80, 200))
+ hwrev = 0x2; /* 1.16V 0.01V */
+ if (IS_RANGE(mode0, 2000, 2400) && IS_RANGE(mode1, 80, 200))
+ hwrev = 0x3; /* 1.79V 0.01V */
+#undef IS_RANGE
+
+ debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev);
+
+ return hwrev;
+}
+
+static void check_hw_revision(void)
+{
+ int hwrev;
+
+ hwrev = get_hw_revision();
+
+ board_rev |= hwrev;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ puts("Board:\tUniversal C210\n");
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ int i, err;
+
+ switch (get_hwrev()) {
+ case 0:
+ /*
+ * Set the low to enable LDO_EN
+ * But when you use the test board for eMMC booting
+ * you should set it HIGH since it removes the inverter
+ */
+ /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
+ gpio_direction_output(&gpio1->e3, 6, 0);
+ break;
+ default:
+ /*
+ * Default reset state is High and there's no inverter
+ * But set it as HIGH to ensure
+ */
+ /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
+ gpio_direction_output(&gpio1->e1, 3, 1);
+ break;
+ }
+
+ /*
+ * eMMC GPIO:
+ * SDR 8-bit@48MHz at MMC0
+ * GPK0[0] SD_0_CLK(2)
+ * GPK0[1] SD_0_CMD(2)
+ * GPK0[2] SD_0_CDn -> Not used
+ * GPK0[3:6] SD_0_DATA[0:3](2)
+ * GPK1[3:6] SD_0_DATA[0:3](3)
+ *
+ * DDR 4-bit@26MHz at MMC4
+ * GPK0[0] SD_4_CLK(3)
+ * GPK0[1] SD_4_CMD(3)
+ * GPK0[2] SD_4_CDn -> Not used
+ * GPK0[3:6] SD_4_DATA[0:3](3)
+ * GPK1[3:6] SD_4_DATA[4:7](4)
+ */
+ for (i = 0; i < 7; i++) {
+ if (i == 2)
+ continue;
+ /* GPK0[0:6] special function 2 */
+ gpio_cfg_pin(&gpio2->k0, i, 0x2);
+ /* GPK0[0:6] pull disable */
+ gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE);
+ /* GPK0[0:6] drv 4x */
+ gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X);
+ }
+
+ for (i = 3; i < 7; i++) {
+ /* GPK1[3:6] special function 3 */
+ gpio_cfg_pin(&gpio2->k1, i, 0x3);
+ /* GPK1[3:6] pull disable */
+ gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE);
+ /* GPK1[3:6] drv 4x */
+ gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X);
+ }
+
+ /* T-flash detect */
+ gpio_cfg_pin(&gpio2->x3, 4, 0xf);
+ gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
+
+ /*
+ * MMC device init
+ * mmc0 : eMMC (8-bit buswidth)
+ * mmc2 : SD card (4-bit buswidth)
+ */
+ err = s5p_mmc_init(0, 8);
+
+ /*
+ * Check the T-flash detect pin
+ * GPX3[4] T-flash detect pin
+ */
+ if (!gpio_get_value(&gpio2->x3, 4)) {
+ /*
+ * SD card GPIO:
+ * GPK2[0] SD_2_CLK(2)
+ * GPK2[1] SD_2_CMD(2)
+ * GPK2[2] SD_2_CDn -> Not used
+ * GPK2[3:6] SD_2_DATA[0:3](2)
+ */
+ for (i = 0; i < 7; i++) {
+ if (i == 2)
+ continue;
+ /* GPK2[0:6] special function 2 */
+ gpio_cfg_pin(&gpio2->k2, i, 0x2);
+ /* GPK2[0:6] pull disable */
+ gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
+ /* GPK2[0:6] drv 4x */
+ gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
+ }
+ err = s5p_mmc_init(2, 4);
+ }
+
+ return err;
+
+}
+#endif
qong arm arm1136 - davedenx mx31
mx31ads arm arm1136 - freescale mx31
imx31_litekit arm arm1136 - logicpd mx31
+mx35pdk arm arm1136 - freescale mx35
omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
armadillo arm arm720t
omap5912osk arm arm926ejs - ti omap
edminiv2 arm arm926ejs - LaCie orion5x
ca9x4_ct_vxp arm armv7 vexpress armltd
+efikamx arm armv7 efikamx - mx5
mx51evk arm armv7 mx51evk freescale mx5
+mx53evk arm armv7 mx53evk freescale mx5
vision2 arm armv7 vision2 ttcontrol mx5
+cm_t35 arm armv7 cm_t35 - omap3
omap3_overo arm armv7 overo - omap3
omap3_pandora arm armv7 pandora - omap3
igep0020 arm armv7 igep0020 isee omap3
omap4_sdp4430 arm armv7 sdp4430 ti omap4
s5p_goni arm armv7 goni samsung s5pc1xx
smdkc100 arm armv7 smdkc100 samsung s5pc1xx
+s5pc210_universal arm armv7 universal_c210 samsung s5pc2xx
actux1 arm ixp
actux2 arm ixp
actux3 arm ixp
2. Following are the valid command strings and associated data strings:-
Command string data string
-------------- -----------
+ IMXIMAGE_VERSION 1/2
+ 1 is for mx25/mx35/mx51 compatible,
+ 2 is for mx53 compatible,
+ others is invalid and error is generated.
+ This command need appear the fist before
+ other valid commands in configuration file.
+
BOOT_FROM nand/spi/sd/onenand
Example:
BOOT_FROM spi
Example (write to IOMUXC):
DATA 4 0x73FA88a0 0x200
-The processor support up to 60 register programming commands. An error
-is generated if more commands are found in the configuration file.
+The processor support up to 60 register programming commands for IMXIMAGE_VERSION 1
+and 121 register programming commands for IMXIMAGE_VERSION 2.
+An error is generated if more commands are found in the configuration file.
3. All commands are optional to program.
--- /dev/null
+Overview
+--------------
+
+mx35pdk (known als as mx35_3stack) is a development board by Freescale.
+It consists of three pluggable board:
+ - CPU module, with CPU, RAM, flash
+ - Personality board, with most interfaces (USB, Network,..)
+ - Debug board with JTAG header.
+
+The board is usually delivered with redboot. This howto explains how to boot
+a linux kernel and how to replace the original bootloader with U-Boot.
+
+The board is delivered with Redboot on the NAND flash. It is possible to
+switch the boot device with the switches SW1-SW2 on the Personality board,
+and with SW5-SW10 on the Debug board.
+
+Delivered Redboot script to start the kernel
+---------------------------------------------------
+
+In redboot the following script is stored:
+
+fis load kernel
+exec -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock8 rw rootfstype=jffs2 ip=dhcp fec_mac=00:04:9F:00:E7:76"
+
+Kernel is taken from flash. The image is in zImage format.
+
+Booting from NET, rootfs on NFS:
+-----------------------------------
+
+To change the script in redboot:
+
+load -r -b 0x100000 <path_to_zImage>
+exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/armVFP rw ip=dhcp"
+
+If the ip address is not set, you can set it with :
+
+ip_address -l <board_ip/netmask> -h <server_ip>
+
+Linux partitions:
+---------------------------
+
+As default, the board is shipped with these partition tables for NAND
+and for NOR:
+
+Creating 5 MTD partitions on "NAND 2GiB 3,3V 8-bit":
+0x00000000-0x00100000 : "nand.bootloader"
+0x00100000-0x00600000 : "nand.kernel"
+0x00600000-0x06600000 : "nand.rootfs"
+0x06600000-0x06e00000 : "nand.configure"
+0x06e00000-0x80000000 : "nand.userfs"
+
+Creating 6 MTD partitions on "mxc_nor_flash.0":
+0x00000000-0x00080000 : "Bootloader"
+0x00080000-0x00480000 : "nor.Kernel"
+0x00480000-0x02280000 : "nor.userfs"
+0x02280000-0x03e80000 : "nor.rootfs"
+0x01fe0000-0x01fe3000 : "FIS directory"
+0x01fff000-0x04000000 : "Redboot config"
+
+NAND partitions can be recognized enabling in kernel CONFIG_MTD_REDBOOT_PARTS.
+For this board, CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK should be set to 2.
+
+However, the setup in redboot is not correct and does not use the whole flash.
+
+Better solution is to use the kernel parameter mtdparts.
+Here the resulting script to be defined in RedBoot with fconfig:
+
+load -r -b 0x100000 sbabic/mx35pdk/zImage.2.6.37
+exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/arm rw ip=dhcp mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"
+
+Flashing U-Boot
+--------------------------------
+
+There are two options: the original bootloader in NAND can be replaced with
+u-boot, or u-boot can be stored on the NOR flash without erasing
+the delivered bootloader.
+The boot storage can be select using the switches on the personality board
+(SW1-SW2) and on the DEBUG board (SW4-SW10).
+
+The second option is to be preferred if you have not a JTAG debugger.
+If something goes wrong flashing the bootloader, it is always possible to
+recover the board booting from the other device.
+
+Replacing the bootloader on the NAND
+--------------------------------------
+To replace RedBoot with U-Boot, the easy way is to do this in linux.
+Start the kernel with the suggested options. Make sure to have set the
+mtdparts exactly as described, because this matches the layout on the
+mx35pdk.
+
+You should see in your boot log the following entries for the NAND
+flash:
+
+5 cmdlinepart partitions found on MTD device mxc_nand
+Creating 5 MTD partitions on "mxc_nand":
+0x000000000000-0x000000100000 : "boot"
+0x000000100000-0x000000600000 : "linux"
+0x000000600000-0x000006600000 : "root"
+0x000006600000-0x000006e00000 : "cfg"
+0x000006e00000-0x000080000000 : "user"
+
+You can use the utilities flash_eraseall and nandwrite to put
+u-boot on the NAND. The bootloader is marked as "boot", and 1MB is
+reserved. If everything is correct, this partition is accessed as
+/dev/mtd4. However, check if it is correct with "cat /proc/mtd" and
+get the device node from the partition name:
+
+$ cat /proc/mtd | grep boot
+
+I suggest you try the utilities on a different partition to be sure
+if everything works correctly. If not, and you remove RedBoot, you have to
+reinstall it using the ATK tool as suggested by Freescale, or using a
+JTAG debugger.
+
+I report the versions of the utilities I used (they are provided with ELDK):
+
+-bash-3.2# nandwrite --version
+nandwrite $Revision: 1.32 $
+
+flash_eraseall --version
+flash_eraseall $Revision: 1.22 $
+
+nandwrite reports a warning if the file to be saved is not sector aligned.
+This should have no consequences, but I preferred to pad u-boot.bin
+to get no problem at all.
+$ dd if=/dev/zero of=zeros bs=1 count=74800
+$ cat u-boot.bin zeros > u-boot-padded.bin
+
+To erase the partition:
+$ flash_eraseall /dev/mtd4
+
+Writing u-boot:
+
+$ nandwrite /dev/mtd4 u-boot-padded.bin
+
+Now U-Boot is stored on the booting partition.
+
+To boot from NAND, you have to select the switches as follows:
+
+Personality board
+ SW2 1, 4, 5 on
+ 2, 3, 6, 7, 8 off
+ SW1 all off
+
+Debug Board:
+ SW5 0
+ SW6 0
+ SW7 0
+ SW8 1
+ SW9 1
+ SW10 0
+
+
+Saving U-Boot in the NOR flash
+---------------------------------
+
+The procedure to save in the NOR flash is quite the same as to write into the NAND.
+
+Check the partition for boot in the NOR flash. Setting the mtdparts as reported,
+the boot partition should be /dev/mtd0.
+
+Creating 6 MTD partitions on "mxc_nor_flash.0":
+0x00000000-0x00080000 : "Bootloader"
+0x00080000-0x00480000 : "nor.Kernel"
+0x00480000-0x02280000 : "nor.userfs"
+0x02280000-0x03e80000 : "nor.rootfs"
+0x01fe0000-0x01fe3000 : "FIS directory"
+0x01fff000-0x04000000 : "Redboot config"
+
+To erase the whole partition:
+$ flash_eraseall /dev/mtd0
+
+Writing u-boot:
+dd if=u-boot.bin of=/dev/mtd0
+
+To boot from NOR, you have to select the switches as follows:
+
+Personality board
+ SW2 all off
+ SW1 all off
+
+Debug Board:
+ SW5 0
+ SW6 0
+ SW7 0
+ SW8 1
+ SW9 1
+ SW10 0
* TI/Logic PD Zoom 2 [7]
+* CompuLab Ltd. CM-T35 [8]
+
Toolchain
=========
make omap3_zoom2_config
make
+* CM-T35:
+
+make cm_t35_config
+make
+
Custom commands
===============
Acknowledgements
================
-OMAP3 U-Boot is based on U-Boot tar ball [8] for BeagleBoard and EVM done by
+OMAP3 U-Boot is based on U-Boot tar ball [9] for BeagleBoard and EVM done by
several TI employees.
Links
[7] TI/Logic PD Zoom 2
http://www.logicpd.com/sites/default/files/1012659A_Zoom_OMAP34x-II_MDP_Brief.pdf
-[8] TI OMAP3 U-Boot:
+
+[8] CompuLab Ltd. CM-T35:
+
+http://www.compulab.co.il/t3530/html/t3530-cm-datasheet.htm
+
+[9] TI OMAP3 U-Boot:
http://beagleboard.googlecode.com/files/u-boot_beagle_revb.tar.gz
COBJS-$(CONFIG_LIBATA) += libata.o
COBJS-$(CONFIG_CMD_MG_DISK) += mg_disk.o
COBJS-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
+COBJS-$(CONFIG_MX51_PATA) += mxc_ata.o
COBJS-$(CONFIG_PATA_BFIN) += pata_bfin.o
COBJS-$(CONFIG_SATA_DWC) += sata_dwc.o
COBJS-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
--- /dev/null
+/*
+ * Freescale iMX51 ATA driver
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on code by:
+ * Mahesh Mahadevan <mahesh.mahadevan@freescale.com>
+ *
+ * Based on code from original FSL ATA driver, which is
+ * part of eCos, the Embedded Configurable Operating System.
+ * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <config.h>
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <ide.h>
+
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+/* MXC ATA register offsets */
+struct mxc_ata_config_regs {
+ u8 time_off; /* 0x00 */
+ u8 time_on;
+ u8 time_1;
+ u8 time_2w;
+ u8 time_2r;
+ u8 time_ax;
+ u8 time_pio_rdx;
+ u8 time_4;
+ u8 time_9;
+ u8 time_m;
+ u8 time_jn;
+ u8 time_d;
+ u8 time_k;
+ u8 time_ack;
+ u8 time_env;
+ u8 time_udma_rdx;
+ u8 time_zah; /* 0x10 */
+ u8 time_mlix;
+ u8 time_dvh;
+ u8 time_dzfs;
+ u8 time_dvs;
+ u8 time_cvh;
+ u8 time_ss;
+ u8 time_cyc;
+ u32 fifo_data_32; /* 0x18 */
+ u32 fifo_data_16;
+ u32 fifo_fill;
+ u32 ata_control;
+ u32 interrupt_pending;
+ u32 interrupt_enable;
+ u32 interrupt_clear;
+ u32 fifo_alarm;
+};
+
+struct mxc_data_hdd_regs {
+ u32 drive_data; /* 0xa0 */
+ u32 drive_features;
+ u32 drive_sector_count;
+ u32 drive_sector_num;
+ u32 drive_cyl_low;
+ u32 drive_cyl_high;
+ u32 drive_dev_head;
+ u32 command;
+ u32 status;
+ u32 alt_status;
+};
+
+/* PIO timing table */
+#define NR_PIO_SPECS 5
+static uint16_t pio_t1[NR_PIO_SPECS] = { 70, 50, 30, 30, 25 };
+static uint16_t pio_t2_8[NR_PIO_SPECS] = { 290, 290, 290, 80, 70 };
+static uint16_t pio_t4[NR_PIO_SPECS] = { 30, 20, 15, 10, 10 };
+static uint16_t pio_t9[NR_PIO_SPECS] = { 20, 15, 10, 10, 10 };
+static uint16_t pio_tA[NR_PIO_SPECS] = { 50, 50, 50, 50, 50 };
+
+#define REG2OFF(reg) ((((uint32_t)reg) & 0x3) * 8)
+static void set_ata_bus_timing(unsigned char mode)
+{
+ uint32_t val;
+ uint32_t T = 1000000000 / mxc_get_clock(MXC_IPG_CLK);
+
+ struct mxc_ata_config_regs *ata_regs;
+ ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR;
+
+ if (mode >= NR_PIO_SPECS)
+ return;
+
+ /* Write TIME_OFF/ON/1/2W */
+ val = (3 << REG2OFF(&ata_regs->time_off)) |
+ (3 << REG2OFF(&ata_regs->time_on)) |
+ (((pio_t1[mode] + T) / T) << REG2OFF(&ata_regs->time_1)) |
+ (((pio_t2_8[mode] + T) / T) << REG2OFF(&ata_regs->time_2w));
+ writel(val, &ata_regs->time_off);
+
+ /* Write TIME_2R/AX/RDX/4 */
+ val = (((pio_t2_8[mode] + T) / T) << REG2OFF(&ata_regs->time_2r)) |
+ (((pio_tA[mode] + T) / T + 2) << REG2OFF(&ata_regs->time_ax)) |
+ (1 << REG2OFF(&ata_regs->time_pio_rdx)) |
+ (((pio_t4[mode] + T) / T) << REG2OFF(&ata_regs->time_4));
+ writel(val, &ata_regs->time_2r);
+
+ /* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */
+ val = (((pio_t9[mode] + T) / T) << REG2OFF(&ata_regs->time_9));
+ writel(val, &ata_regs->time_9);
+}
+
+int ide_preinit(void)
+{
+ struct mxc_ata_config_regs *ata_regs;
+ ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR;
+
+ /* 46.3.3.4 @ FSL iMX51 manual */
+ /* FIFO normal op., drive reset */
+ writel(0x80, &ata_regs->ata_control);
+ /* FIFO normal op., drive not reset */
+ writel(0xc0, &ata_regs->ata_control);
+
+ /* Configure the PIO timing */
+ set_ata_bus_timing(CONFIG_MXC_ATA_PIO_MODE);
+
+ /* 46.3.3.4 @ FSL iMX51 manual */
+ /* Drive not reset, IORDY handshake */
+ writel(0x41, &ata_regs->ata_control);
+
+ return 0;
+}
#ifdef CONFIG_MX31
#include <asm/arch/mx31-regs.h>
#endif
-#ifdef CONFIG_MX51
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
#endif
#include <asm/io.h>
[0] = GPIO1_BASE_ADDR,
[1] = GPIO2_BASE_ADDR,
[2] = GPIO3_BASE_ADDR,
-#ifdef CONFIG_MX51
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
[3] = GPIO4_BASE_ADDR,
#endif
+#if defined(CONFIG_MX53)
+ [4] = GPIO5_BASE_ADDR,
+ [5] = GPIO6_BASE_ADDR,
+ [6] = GPIO7_BASE_ADDR,
+#endif
};
int mxc_gpio_direction(unsigned int gpio, enum mxc_gpio_direction direction)
*/
#include <common.h>
+#include <asm/io.h>
#if defined(CONFIG_HARD_I2C)
+#if defined(CONFIG_MX31)
#include <asm/arch/mx31.h>
#include <asm/arch/mx31-regs.h>
+#else
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#endif
#define IADR 0x00
#define IFDR 0x04
#define I2SR_IIF (1 << 1)
#define I2SR_RX_NO_AK (1 << 0)
-#ifdef CONFIG_SYS_I2C_MX31_PORT1
+#if defined(CONFIG_SYS_I2C_MX31_PORT1)
#define I2C_BASE 0x43f80000
#define I2C_CLK_OFFSET 26
#elif defined (CONFIG_SYS_I2C_MX31_PORT2)
#elif defined (CONFIG_SYS_I2C_MX31_PORT3)
#define I2C_BASE 0x43f84000
#define I2C_CLK_OFFSET 30
+#elif defined(CONFIG_SYS_I2C_MX53_PORT1)
+#define I2C_BASE I2C1_BASE_ADDR
+#elif defined(CONFIG_SYS_I2C_MX53_PORT2)
+#define I2C_BASE I2C2_BASE_ADDR
+#elif defined(CONFIG_SYS_I2C_MX35_PORT1)
+#define I2C_BASE I2C_BASE_ADDR
#else
-#error "define CONFIG_SYS_I2C_MX31_PORTx to use the mx31 I2C driver"
+#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
#endif
-#ifdef DEBUG
-#define DPRINTF(args...) printf(args)
-#else
-#define DPRINTF(args...)
-#endif
+#define I2C_MAX_TIMEOUT 10000
+#define I2C_MAX_RETRIES 3
static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144,
160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960,
1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840};
+static inline void i2c_reset(void)
+{
+ writew(0, I2C_BASE + I2CR); /* Reset module */
+ writew(0, I2C_BASE + I2SR);
+ writew(I2CR_IEN, I2C_BASE + I2CR);
+}
+
void i2c_init(int speed, int unused)
{
- int freq = mx31_get_ipg_clk();
+ int freq;
int i;
+#if defined(CONFIG_MX31)
+ struct clock_control_regs *sc_regs =
+ (struct clock_control_regs *)CCM_BASE;
+
+ freq = mx31_get_ipg_clk();
/* start the required I2C clock */
- __REG(CCM_CGR0) = __REG(CCM_CGR0) | (3 << I2C_CLK_OFFSET);
+ writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET),
+ &sc_regs->cgr0);
+#else
+ freq = mxc_get_clock(MXC_IPG_PERCLK);
+#endif
for (i = 0; i < 0x1f; i++)
if (freq / div[i] <= speed)
break;
- DPRINTF("%s: speed: %d\n",__FUNCTION__, speed);
+ debug("%s: speed: %d\n", __func__, speed);
- __REG16(I2C_BASE + I2CR) = 0; /* Reset module */
- __REG16(I2C_BASE + IFDR) = i;
- __REG16(I2C_BASE + I2CR) = I2CR_IEN;
- __REG16(I2C_BASE + I2SR) = 0;
+ writew(i, I2C_BASE + IFDR);
+ i2c_reset();
+}
+
+static int wait_idle(void)
+{
+ int timeout = I2C_MAX_TIMEOUT;
+
+ while ((readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout) {
+ writew(0, I2C_BASE + I2SR);
+ udelay(1);
+ }
+ return timeout ? timeout : (!(readw(I2C_BASE + I2SR) & I2SR_IBB));
}
static int wait_busy(void)
{
- int timeout = 10000;
+ int timeout = I2C_MAX_TIMEOUT;
- while (!(__REG16(I2C_BASE + I2SR) & I2SR_IIF) && --timeout)
+ while (!(readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout)
udelay(1);
- __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */
+ writew(0, I2C_BASE + I2SR); /* clear interrupt */
return timeout;
}
+static int wait_complete(void)
+{
+ int timeout = I2C_MAX_TIMEOUT;
+
+ while ((!(readw(I2C_BASE + I2SR) & I2SR_ICF)) && (--timeout)) {
+ writew(0, I2C_BASE + I2SR);
+ udelay(1);
+ }
+ udelay(200);
+
+ writew(0, I2C_BASE + I2SR); /* clear interrupt */
+
+ return timeout;
+}
+
+
static int tx_byte(u8 byte)
{
- __REG16(I2C_BASE + I2DR) = byte;
+ writew(byte, I2C_BASE + I2DR);
- if (!wait_busy() || __REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK)
+ if (!wait_complete() || readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)
return -1;
return 0;
}
-static int rx_byte(void)
+static int rx_byte(int last)
{
- if (!wait_busy())
+ if (!wait_complete())
return -1;
- return __REG16(I2C_BASE + I2DR);
+ if (last)
+ writew(I2CR_IEN, I2C_BASE + I2CR);
+
+ return readw(I2C_BASE + I2DR);
}
int i2c_probe(uchar chip)
{
int ret;
- __REG16(I2C_BASE + I2CR) = 0; /* Reset module */
- __REG16(I2C_BASE + I2CR) = I2CR_IEN;
+ writew(0, I2C_BASE + I2CR); /* Reset module */
+ writew(I2CR_IEN, I2C_BASE + I2CR);
- __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX;
+ writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR);
ret = tx_byte(chip << 1);
- __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MTX;
+ writew(I2CR_IEN | I2CR_MTX, I2C_BASE + I2CR);
return ret;
}
static int i2c_addr(uchar chip, uint addr, int alen)
{
- __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */
- __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX;
+ int i, retry = 0;
+ for (retry = 0; retry < 3; retry++) {
+ if (wait_idle())
+ break;
+ i2c_reset();
+ for (i = 0; i < I2C_MAX_TIMEOUT; i++)
+ udelay(1);
+ }
+ if (retry >= I2C_MAX_RETRIES) {
+ debug("%s:bus is busy(%x)\n",
+ __func__, readw(I2C_BASE + I2SR));
+ return -1;
+ }
+ writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR);
- if (tx_byte(chip << 1))
+ if (!wait_busy()) {
+ debug("%s:trigger start fail(%x)\n",
+ __func__, readw(I2C_BASE + I2SR));
return -1;
+ }
+ if (tx_byte(chip << 1) || (readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) {
+ debug("%s:chip address cycle fail(%x)\n",
+ __func__, readw(I2C_BASE + I2SR));
+ return -1;
+ }
while (alen--)
- if (tx_byte((addr >> (alen * 8)) & 0xff))
+ if (tx_byte((addr >> (alen * 8)) & 0xff) ||
+ (readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) {
+ debug("%s:device address cycle fail(%x)\n",
+ __func__, readw(I2C_BASE + I2SR));
return -1;
+ }
return 0;
}
int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
{
- int timeout = 10000;
+ int timeout = I2C_MAX_TIMEOUT;
int ret;
- DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len);
+ debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",
+ __func__, chip, addr, alen, len);
if (i2c_addr(chip, addr, alen)) {
printf("i2c_addr failed\n");
return -1;
}
- __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA;
+ writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA, I2C_BASE + I2CR);
if (tx_byte(chip << 1 | 1))
return -1;
- __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | ((len == 1) ? I2CR_TX_NO_AK : 0);
+ writew(I2CR_IEN | I2CR_MSTA |
+ ((len == 1) ? I2CR_TX_NO_AK : 0),
+ I2C_BASE + I2CR);
- ret = __REG16(I2C_BASE + I2DR);
+ ret = readw(I2C_BASE + I2DR);
while (len--) {
- if ((ret = rx_byte()) < 0)
+ ret = rx_byte(len == 0);
+ if (ret < 0)
return -1;
*buf++ = ret;
if (len <= 1)
- __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_TX_NO_AK;
+ writew(I2CR_IEN | I2CR_MSTA |
+ I2CR_TX_NO_AK,
+ I2C_BASE + I2CR);
}
- wait_busy();
-
- __REG16(I2C_BASE + I2CR) = I2CR_IEN;
+ writew(I2CR_IEN, I2C_BASE + I2CR);
- while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
+ while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
udelay(1);
return 0;
int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
{
- int timeout = 10000;
- DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len);
+ int timeout = I2C_MAX_TIMEOUT;
+ debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",
+ __func__, chip, addr, alen, len);
if (i2c_addr(chip, addr, alen))
return -1;
if (tx_byte(*buf++))
return -1;
- __REG16(I2C_BASE + I2CR) = I2CR_IEN;
+ writew(I2CR_IEN, I2C_BASE + I2CR);
- while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
+ while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
udelay(1);
return 0;
COBJS-$(CONFIG_ALI152X) += ali512x.o
COBJS-$(CONFIG_DS4510) += ds4510.o
COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
+COBJS-$(CONFIG_FSL_PMIC) += fsl_pmic.o
COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
+COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
COBJS-$(CONFIG_NS87308) += ns87308.o
+COBJS-$(CONFIG_PDSP188x) += pdsp188x.o
COBJS-$(CONFIG_STATUS_LED) += status_led.o
COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o
-COBJS-$(CONFIG_FSL_PMIC) += fsl_pmic.o
-COBJS-$(CONFIG_PDSP188x) += pdsp188x.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
#include <config.h>
#include <common.h>
-#include <spi.h>
#include <asm/errno.h>
#include <linux/types.h>
#include <fsl_pmic.h>
+static int check_param(u32 reg, u32 write)
+{
+ if (reg > 63 || write > 1) {
+ printf("<reg num> = %d is invalid. Should be less then 63\n",
+ reg);
+ return -1;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_FSL_PMIC_I2C
+#include <i2c.h>
+
+u32 pmic_reg(u32 reg, u32 val, u32 write)
+{
+ unsigned char buf[4] = { 0 };
+ u32 ret_val = 0;
+
+ if (check_param(reg, write))
+ return -1;
+
+ if (write) {
+ buf[0] = (val >> 16) & 0xff;
+ buf[1] = (val >> 8) & 0xff;
+ buf[2] = (val) & 0xff;
+ if (i2c_write(CONFIG_SYS_FSL_PMIC_I2C_ADDR, reg, 1, buf, 3))
+ return -1;
+ } else {
+ if (i2c_read(CONFIG_SYS_FSL_PMIC_I2C_ADDR, reg, 1, buf, 3))
+ return -1;
+ ret_val = buf[0] << 16 | buf[1] << 8 | buf[2];
+ }
+
+ return ret_val;
+}
+#else /* SPI interface */
+#include <spi.h>
static struct spi_slave *slave;
struct spi_slave *pmic_spi_probe(void)
return -1;
}
- if (reg > 63 || write > 1) {
- printf("<reg num> = %d is invalid. Should be less then 63\n",
- reg);
+ if (check_param(reg, write))
return -1;
- }
if (spi_claim_bus(slave))
return -1;
spi_release_bus(slave);
return cpu_to_be32(pmic_rx);
}
+#endif
void pmic_reg_write(u32 reg, u32 value)
{
--- /dev/null
+/*
+ * (C) Copyright 2010 Stefano Babic <sbabic@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <common.h>
+#include <asm/errno.h>
+#include <linux/types.h>
+#include <i2c.h>
+#include <mc9sdz60.h>
+
+#ifndef CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR
+#error "You have to configure I2C address for MC9SDZ60"
+#endif
+
+
+u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg)
+{
+ u8 val;
+
+ if (i2c_read(CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR, reg, 1, &val, 1)) {
+ puts("Error reading MC9SDZ60 register\n");
+ return -1;
+ }
+
+ return val;
+}
+
+void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val)
+{
+ i2c_write(CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR, reg, 1, &val, 1);
+}
COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
+COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
--- /dev/null
+/*
+ * Davinci MMC Controller Driver
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <mmc.h>
+#include <part.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/arch/sdmmc_defs.h>
+
+#define DAVINCI_MAX_BLOCKS (32)
+#define WATCHDOG_COUNT (100000)
+
+#define get_val(addr) REG(addr)
+#define set_val(addr, val) REG(addr) = (val)
+#define set_bit(addr, val) set_val((addr), (get_val(addr) | (val)))
+#define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val)))
+
+/* Set davinci clock prescalar value based on the required clock in HZ */
+static void dmmc_set_clock(struct mmc *mmc, uint clock)
+{
+ struct davinci_mmc *host = mmc->priv;
+ struct davinci_mmc_regs *regs = host->reg_base;
+ uint clkrt, sysclk2, act_clock;
+
+ if (clock < mmc->f_min)
+ clock = mmc->f_min;
+ if (clock > mmc->f_max)
+ clock = mmc->f_max;
+
+ set_val(®s->mmcclk, 0);
+ sysclk2 = host->input_clk;
+ clkrt = (sysclk2 / (2 * clock)) - 1;
+
+ /* Calculate the actual clock for the divider used */
+ act_clock = (sysclk2 / (2 * (clkrt + 1)));
+
+ /* Adjust divider if actual clock exceeds the required clock */
+ if (act_clock > clock)
+ clkrt++;
+
+ /* check clock divider boundary and correct it */
+ if (clkrt > 0xFF)
+ clkrt = 0xFF;
+
+ set_val(®s->mmcclk, (clkrt | MMCCLK_CLKEN));
+}
+
+/* Status bit wait loop for MMCST1 */
+static int
+dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status)
+{
+ uint mmcstatus1, wdog = WATCHDOG_COUNT;
+ mmcstatus1 = get_val(®s->mmcst1);
+ while (--wdog && ((get_val(®s->mmcst1) & status) != status))
+ udelay(10);
+
+ if (!(get_val(®s->mmcctl) & MMCCTL_WIDTH_4_BIT))
+ udelay(100);
+
+ if (wdog == 0)
+ return COMM_ERR;
+
+ return 0;
+}
+
+/* Busy bit wait loop for MMCST1 */
+static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs)
+{
+ uint mmcstatus1, wdog = WATCHDOG_COUNT;
+
+ mmcstatus1 = get_val(®s->mmcst1);
+ while (--wdog && (get_val(®s->mmcst1) & MMCST1_BUSY))
+ udelay(10);
+
+ if (wdog == 0)
+ return COMM_ERR;
+
+ return 0;
+}
+
+/* Status bit wait loop for MMCST0 - Checks for error bits as well */
+static int dmmc_check_status(volatile struct davinci_mmc_regs *regs,
+ uint *cur_st, uint st_ready, uint st_error)
+{
+ uint wdog = WATCHDOG_COUNT;
+ uint mmcstatus = *cur_st;
+
+ while (wdog--) {
+ if (mmcstatus & st_ready) {
+ *cur_st = mmcstatus;
+ mmcstatus = get_val(®s->mmcst1);
+ return 0;
+ } else if (mmcstatus & st_error) {
+ if (mmcstatus & MMCST0_TOUTRS)
+ return TIMEOUT;
+ printf("[ ST0 ERROR %x]\n", mmcstatus);
+ /*
+ * Ignore CRC errors as some MMC cards fail to
+ * initialize on DM365-EVM on the SD1 slot
+ */
+ if (mmcstatus & MMCST0_CRCRS)
+ return 0;
+ return COMM_ERR;
+ }
+ udelay(10);
+
+ mmcstatus = get_val(®s->mmcst0);
+ }
+
+ printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus,
+ get_val(®s->mmcst1));
+ return COMM_ERR;
+}
+
+/*
+ * Sends a command out on the bus. Takes the mmc pointer,
+ * a command pointer, and an optional data pointer.
+ */
+static int
+dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+{
+ struct davinci_mmc *host = mmc->priv;
+ volatile struct davinci_mmc_regs *regs = host->reg_base;
+ uint mmcstatus, status_rdy, status_err;
+ uint i, cmddata, bytes_left = 0;
+ int fifo_words, fifo_bytes, err;
+ char *data_buf = NULL;
+
+ /* Clear status registers */
+ mmcstatus = get_val(®s->mmcst0);
+ fifo_words = (host->version == MMC_CTLR_VERSION_2) ? 16 : 8;
+ fifo_bytes = fifo_words << 2;
+
+ /* Wait for any previous busy signal to be cleared */
+ dmmc_busy_wait(regs);
+
+ cmddata = cmd->cmdidx;
+ cmddata |= MMCCMD_PPLEN;
+
+ /* Send init clock for CMD0 */
+ if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE)
+ cmddata |= MMCCMD_INITCK;
+
+ switch (cmd->resp_type) {
+ case MMC_RSP_R1b:
+ cmddata |= MMCCMD_BSYEXP;
+ /* Fall-through */
+ case MMC_RSP_R1: /* R1, R1b, R5, R6, R7 */
+ cmddata |= MMCCMD_RSPFMT_R1567;
+ break;
+ case MMC_RSP_R2:
+ cmddata |= MMCCMD_RSPFMT_R2;
+ break;
+ case MMC_RSP_R3: /* R3, R4 */
+ cmddata |= MMCCMD_RSPFMT_R3;
+ break;
+ }
+
+ set_val(®s->mmcim, 0);
+
+ if (data) {
+ /* clear previous data transfer if any and set new one */
+ bytes_left = (data->blocksize * data->blocks);
+
+ /* Reset FIFO - Always use 32 byte fifo threshold */
+ set_val(®s->mmcfifoctl,
+ (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
+
+ if (host->version == MMC_CTLR_VERSION_2)
+ cmddata |= MMCCMD_DMATRIG;
+
+ cmddata |= MMCCMD_WDATX;
+ if (data->flags == MMC_DATA_READ) {
+ set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
+ } else if (data->flags == MMC_DATA_WRITE) {
+ set_val(®s->mmcfifoctl,
+ (MMCFIFOCTL_FIFOLEV |
+ MMCFIFOCTL_FIFODIR));
+ cmddata |= MMCCMD_DTRW;
+ }
+
+ set_val(®s->mmctod, 0xFFFF);
+ set_val(®s->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK));
+ set_val(®s->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK));
+
+ if (data->flags == MMC_DATA_WRITE) {
+ uint val;
+ data_buf = (char *)data->src;
+ /* For write, fill FIFO with data before issue of CMD */
+ for (i = 0; (i < fifo_words) && bytes_left; i++) {
+ memcpy((char *)&val, data_buf, 4);
+ set_val(®s->mmcdxr, val);
+ data_buf += 4;
+ bytes_left -= 4;
+ }
+ }
+ } else {
+ set_val(®s->mmcblen, 0);
+ set_val(®s->mmcnblk, 0);
+ }
+
+ set_val(®s->mmctor, 0x1FFF);
+
+ /* Send the command */
+ set_val(®s->mmcarghl, cmd->cmdarg);
+ set_val(®s->mmccmd, cmddata);
+
+ status_rdy = MMCST0_RSPDNE;
+ status_err = (MMCST0_TOUTRS | MMCST0_TOUTRD |
+ MMCST0_CRCWR | MMCST0_CRCRD);
+ if (cmd->resp_type & MMC_RSP_CRC)
+ status_err |= MMCST0_CRCRS;
+
+ mmcstatus = get_val(®s->mmcst0);
+ err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err);
+ if (err)
+ return err;
+
+ /* For R1b wait for busy done */
+ if (cmd->resp_type == MMC_RSP_R1b)
+ dmmc_busy_wait(regs);
+
+ /* Collect response from controller for specific commands */
+ if (mmcstatus & MMCST0_RSPDNE) {
+ /* Copy the response to the response buffer */
+ if (cmd->resp_type & MMC_RSP_136) {
+ cmd->response[0] = get_val(®s->mmcrsp67);
+ cmd->response[1] = get_val(®s->mmcrsp45);
+ cmd->response[2] = get_val(®s->mmcrsp23);
+ cmd->response[3] = get_val(®s->mmcrsp01);
+ } else if (cmd->resp_type & MMC_RSP_PRESENT) {
+ cmd->response[0] = get_val(®s->mmcrsp67);
+ }
+ }
+
+ if (data == NULL)
+ return 0;
+
+ if (data->flags == MMC_DATA_READ) {
+ /* check for DATDNE along with DRRDY as the controller might
+ * set the DATDNE without DRRDY for smaller transfers with
+ * less than FIFO threshold bytes
+ */
+ status_rdy = MMCST0_DRRDY | MMCST0_DATDNE;
+ status_err = MMCST0_TOUTRD | MMCST0_CRCRD;
+ data_buf = data->dest;
+ } else {
+ status_rdy = MMCST0_DXRDY | MMCST0_DATDNE;
+ status_err = MMCST0_CRCWR;
+ }
+
+ /* Wait until all of the blocks are transferred */
+ while (bytes_left) {
+ err = dmmc_check_status(regs, &mmcstatus, status_rdy,
+ status_err);
+ if (err)
+ return err;
+
+ if (data->flags == MMC_DATA_READ) {
+ /*
+ * MMC controller sets the Data receive ready bit
+ * (DRRDY) in MMCST0 even before the entire FIFO is
+ * full. This results in erratic behavior if we start
+ * reading the FIFO soon after DRRDY. Wait for the
+ * FIFO full bit in MMCST1 for proper FIFO clearing.
+ */
+ if (bytes_left > fifo_bytes)
+ dmmc_wait_fifo_status(regs, 0x4a);
+ else if (bytes_left == fifo_bytes)
+ dmmc_wait_fifo_status(regs, 0x40);
+
+ for (i = 0; bytes_left && (i < fifo_words); i++) {
+ cmddata = get_val(®s->mmcdrr);
+ memcpy(data_buf, (char *)&cmddata, 4);
+ data_buf += 4;
+ bytes_left -= 4;
+ }
+ } else {
+ /*
+ * MMC controller sets the Data transmit ready bit
+ * (DXRDY) in MMCST0 even before the entire FIFO is
+ * empty. This results in erratic behavior if we start
+ * writing the FIFO soon after DXRDY. Wait for the
+ * FIFO empty bit in MMCST1 for proper FIFO clearing.
+ */
+ dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP);
+ for (i = 0; bytes_left && (i < fifo_words); i++) {
+ memcpy((char *)&cmddata, data_buf, 4);
+ set_val(®s->mmcdxr, cmddata);
+ data_buf += 4;
+ bytes_left -= 4;
+ }
+ dmmc_busy_wait(regs);
+ }
+ }
+
+ err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+/* Initialize Davinci MMC controller */
+static int dmmc_init(struct mmc *mmc)
+{
+ struct davinci_mmc *host = mmc->priv;
+ struct davinci_mmc_regs *regs = host->reg_base;
+
+ /* Clear status registers explicitly - soft reset doesn't clear it
+ * If Uboot is invoked from UBL with SDMMC Support, the status
+ * registers can have uncleared bits
+ */
+ get_val(®s->mmcst0);
+ get_val(®s->mmcst1);
+
+ /* Hold software reset */
+ set_bit(®s->mmcctl, MMCCTL_DATRST);
+ set_bit(®s->mmcctl, MMCCTL_CMDRST);
+ udelay(10);
+
+ set_val(®s->mmcclk, 0x0);
+ set_val(®s->mmctor, 0x1FFF);
+ set_val(®s->mmctod, 0xFFFF);
+
+ /* Clear software reset */
+ clear_bit(®s->mmcctl, MMCCTL_DATRST);
+ clear_bit(®s->mmcctl, MMCCTL_CMDRST);
+
+ udelay(10);
+
+ /* Reset FIFO - Always use the maximum fifo threshold */
+ set_val(®s->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
+ set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
+
+ return 0;
+}
+
+/* Set buswidth or clock as indicated by the GENERIC_MMC framework */
+static void dmmc_set_ios(struct mmc *mmc)
+{
+ struct davinci_mmc *host = mmc->priv;
+ struct davinci_mmc_regs *regs = host->reg_base;
+
+ /* Set the bus width */
+ if (mmc->bus_width == 4)
+ set_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
+ else
+ clear_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
+
+ /* Set clock speed */
+ if (mmc->clock)
+ dmmc_set_clock(mmc, mmc->clock);
+}
+
+/* Called from board_mmc_init during startup. Can be called multiple times
+ * depending on the number of slots available on board and controller
+ */
+int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host)
+{
+ struct mmc *mmc;
+
+ mmc = malloc(sizeof(struct mmc));
+ memset(mmc, 0, sizeof(struct mmc));
+
+ sprintf(mmc->name, "davinci");
+ mmc->priv = host;
+ mmc->send_cmd = dmmc_send_cmd;
+ mmc->set_ios = dmmc_set_ios;
+ mmc->init = dmmc_init;
+
+ mmc->f_min = 200000;
+ mmc->f_max = 25000000;
+ mmc->voltages = host->voltages;
+ mmc->host_caps = host->host_caps;
+
+#ifdef CONFIG_MMC_MBLOCK
+ mmc->b_max = DAVINCI_MAX_BLOCKS;
+#endif
+ mmc_register(mmc);
+
+ return 0;
+}
+
#include <nand.h>
#include <linux/err.h>
#include <asm/io.h>
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35)
#include <asm/arch/imx-regs.h>
#endif
*/
#if defined(CONFIG_MX31) || defined(CONFIG_MX27)
#define MXC_NFC_V1
-#elif defined(CONFIG_MX25)
+#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
#define MXC_NFC_V1_1
#else
#warning "MXC NFC version not defined"
else
return 0;
}
-#elif defined(CONFIG_MX25)
+#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
static int is_16bit_nand(void)
{
struct ccm_regs *ccm =
* Check if link detected is giga-bit
* If Gigabit mode detected, enable gigbit in MAC
*/
- writel(EMAC_MACCONTROL_GIGFORCE |
- EMAC_MACCONTROL_GIGABIT_ENABLE,
- &adap_emac->MACCONTROL);
+ writel(readl(&adap_emac->MACCONTROL) |
+ EMAC_MACCONTROL_GIGFORCE |
+ EMAC_MACCONTROL_GIGABIT_ENABLE,
+ &adap_emac->MACCONTROL);
}
}
}
return -1;
memset(dev, 0, sizeof *dev);
+ sprintf(dev->name, "DaVinci-EMAC");
dev->iobase = 0;
dev->init = davinci_eth_open;
phy.get_link_speed = dp83848_get_link_speed;
phy.auto_negotiate = dp83848_auto_negotiate;
break;
+ case PHY_ET1011C:
+ sprintf(phy.name, "ET1011C @ 0x%02x", active_phy_addr);
+ phy.init = gen_init_phy;
+ phy.is_phy_connected = gen_is_phy_connected;
+ phy.get_link_speed = et1011c_get_link_speed;
+ phy.auto_negotiate = gen_auto_negotiate;
+ break;
default:
sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr);
phy.init = gen_init_phy;
*/
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
&fec->eth->ecntrl);
-#ifdef CONFIG_MX25
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
udelay(100);
/*
* setup the MII gasket for RMII mode
uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */
-#ifdef CONFIG_MX25
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */
uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */
uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */
#define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */
#define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */
-#ifdef CONFIG_MX25
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
/* defines for MIIGSK */
/* RMII frequency control: 0=50MHz, 1=5MHz */
#define MIIGSK_CFGR_FRCONT (1 << 6)
#define UART_PHYS 0x1001b000
#elif defined(CONFIG_SYS_MX27_UART6)
#define UART_PHYS 0x1001c000
-#elif defined(CONFIG_SYS_MX51_UART1)
+#elif defined(CONFIG_SYS_MX35_UART1) || defined(CONFIG_SYS_MX51_UART1) || \
+ defined(CONFIG_SYS_MX53_UART1)
#define UART_PHYS UART1_BASE_ADDR
-#elif defined(CONFIG_SYS_MX51_UART2)
+#elif defined(CONFIG_SYS_MX35_UART2) || defined(CONFIG_SYS_MX51_UART2) || \
+ defined(CONFIG_SYS_MX53_UART2)
#define UART_PHYS UART2_BASE_ADDR
-#elif defined(CONFIG_SYS_MX51_UART3)
+#elif defined(CONFIG_SYS_MX35_UART3) || defined(CONFIG_SYS_MX51_UART3) || \
+ defined(CONFIG_SYS_MX53_UART3)
#define UART_PHYS UART3_BASE_ADDR
#else
#error "define CONFIG_SYS_MXxx_UARTx to use the MXC UART driver"
writel(val / 16 - 1, &uart->ubrdiv);
- if (use_divslot)
+ if (s5p_uart_divslot())
writew(udivslot[val % 16], &uart->rest.slot);
else
writeb(val % 16, &uart->rest.value);
#include <asm/arch/mx31.h>
-#define MXC_CSPIRXDATA 0x00
-#define MXC_CSPITXDATA 0x04
-#define MXC_CSPICTRL 0x08
-#define MXC_CSPIINT 0x0C
-#define MXC_CSPIDMA 0x10
-#define MXC_CSPISTAT 0x14
-#define MXC_CSPIPERIOD 0x18
-#define MXC_CSPITEST 0x1C
-#define MXC_CSPIRESET 0x00
-
#define MXC_CSPICTRL_EN (1 << 0)
#define MXC_CSPICTRL_MODE (1 << 1)
#define MXC_CSPICTRL_XCH (1 << 2)
0x53f84000,
};
+#define mxc_get_clock(x) mx31_get_ipg_clk()
+
#elif defined(CONFIG_MX51)
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#define MXC_CSPIRXDATA 0x00
-#define MXC_CSPITXDATA 0x04
-#define MXC_CSPICTRL 0x08
-#define MXC_CSPICON 0x0C
-#define MXC_CSPIINT 0x10
-#define MXC_CSPIDMA 0x14
-#define MXC_CSPISTAT 0x18
-#define MXC_CSPIPERIOD 0x1C
-#define MXC_CSPIRESET 0x00
#define MXC_CSPICTRL_EN (1 << 0)
#define MXC_CSPICTRL_MODE (1 << 1)
#define MXC_CSPICTRL_XCH (1 << 2)
CSPI2_BASE_ADDR,
CSPI3_BASE_ADDR,
};
+
+#elif defined(CONFIG_MX35)
+
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+#define MXC_CSPICTRL_EN (1 << 0)
+#define MXC_CSPICTRL_MODE (1 << 1)
+#define MXC_CSPICTRL_XCH (1 << 2)
+#define MXC_CSPICTRL_SMC (1 << 3)
+#define MXC_CSPICTRL_POL (1 << 4)
+#define MXC_CSPICTRL_PHA (1 << 5)
+#define MXC_CSPICTRL_SSCTL (1 << 6)
+#define MXC_CSPICTRL_SSPOL (1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC (1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPICTRL_MAXBITS 0xfff
+
+#define MXC_CSPIPERIOD_32KHZ (1 << 15)
+#define MAX_SPI_BYTES 4
+
+static unsigned long spi_bases[] = {
+ 0x43fa4000,
+ 0x50010000,
+};
+
#else
#error "Unsupported architecture"
#endif
#define OUT MXC_GPIO_DIRECTION_OUT
+#define reg_read readl
+#define reg_write(a, v) writel(v, a)
+
struct mxc_spi_slave {
struct spi_slave slave;
unsigned long base;
return container_of(slave, struct mxc_spi_slave, slave);
}
-static inline u32 reg_read(unsigned long addr)
-{
- return *(volatile unsigned long*)addr;
-}
-
-static inline void reg_write(unsigned long addr, u32 val)
-{
- *(volatile unsigned long*)addr = val;
-}
-
void spi_cs_activate(struct spi_slave *slave)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
!(mxcs->ss_pol));
}
-#ifdef CONFIG_MX51
-static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs,
+u32 get_cspi_div(u32 div)
+{
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ if (div <= (4 << i))
+ return i;
+ }
+ return i;
+}
+
+#if defined(CONFIG_MX31) || defined(CONFIG_MX35)
+static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ unsigned int ctrl_reg;
+ u32 clk_src;
+ u32 div;
+
+ clk_src = mxc_get_clock(MXC_CSPI_CLK);
+
+ div = clk_src / max_hz;
+ div = get_cspi_div(div);
+
+ debug("clk %d Hz, div %d, real clk %d Hz\n",
+ max_hz, div, clk_src / (4 << div));
+
+ ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
+ MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
+ MXC_CSPICTRL_DATARATE(div) |
+ MXC_CSPICTRL_EN |
+#ifdef CONFIG_MX35
+ MXC_CSPICTRL_SSCTL |
+#endif
+ MXC_CSPICTRL_MODE;
+
+ if (mode & SPI_CPHA)
+ ctrl_reg |= MXC_CSPICTRL_PHA;
+ if (mode & SPI_CPOL)
+ ctrl_reg |= MXC_CSPICTRL_POL;
+ if (mode & SPI_CS_HIGH)
+ ctrl_reg |= MXC_CSPICTRL_SSPOL;
+ mxcs->ctrl_reg = ctrl_reg;
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_MX51)
+static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
+ struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
if (max_hz == 0) {
printf("Error: desired clock is 0\n");
return -1;
}
- reg_ctrl = reg_read(mxcs->base + MXC_CSPICTRL);
+ reg_ctrl = reg_read(®s->ctrl);
/* Reset spi */
- reg_write(mxcs->base + MXC_CSPICTRL, 0);
- reg_write(mxcs->base + MXC_CSPICTRL, (reg_ctrl | 0x1));
+ reg_write(®s->ctrl, 0);
+ reg_write(®s->ctrl, (reg_ctrl | 0x1));
/*
* The following computation is taken directly from Freescale's code.
if (mode & SPI_CPHA)
sclkpha = 1;
- reg_config = reg_read(mxcs->base + MXC_CSPICON);
+ reg_config = reg_read(®s->cfg);
/*
* Configuration register setup
- * The MX51 has support different setup for each SS
+ * The MX51 supports different setup for each SS
*/
reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
(ss_pol << (cs + MXC_CSPICON_SSPOL));
(sclkpha << (cs + MXC_CSPICON_PHA));
debug("reg_ctrl = 0x%x\n", reg_ctrl);
- reg_write(mxcs->base + MXC_CSPICTRL, reg_ctrl);
+ reg_write(®s->ctrl, reg_ctrl);
debug("reg_config = 0x%x\n", reg_config);
- reg_write(mxcs->base + MXC_CSPICON, reg_config);
+ reg_write(®s->cfg, reg_config);
/* save config register and control register */
mxcs->ctrl_reg = reg_ctrl;
mxcs->cfg_reg = reg_config;
/* clear interrupt reg */
- reg_write(mxcs->base + MXC_CSPIINT, 0);
- reg_write(mxcs->base + MXC_CSPISTAT,
- MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
+ reg_write(®s->intr, 0);
+ reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
return 0;
}
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
int nbytes = (bitlen + 7) / 8;
u32 data, cnt, i;
+ struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
debug("%s: bitlen %d dout 0x%x din 0x%x\n",
__func__, bitlen, (u32)dout, (u32)din);
~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
MXC_CSPICTRL_BITCOUNT(bitlen - 1);
- reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
+ reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
#ifdef CONFIG_MX51
- reg_write(mxcs->base + MXC_CSPICON, mxcs->cfg_reg);
+ reg_write(®s->cfg, mxcs->cfg_reg);
#endif
/* Clear interrupt register */
- reg_write(mxcs->base + MXC_CSPISTAT,
- MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
+ reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
/*
* The SPI controller works only with words,
}
debug("Sending SPI 0x%x\n", data);
- reg_write(mxcs->base + MXC_CSPITXDATA, data);
+ reg_write(®s->txdata, data);
nbytes -= cnt;
}
/* Buffer is not 32-bit aligned */
if ((unsigned long)dout & 0x03) {
data = 0;
- for (i = 0; i < 4; i++, data <<= 8) {
+ for (i = 0; i < 4; i++)
data = (data << 8) | (*dout++ & 0xFF);
- }
} else {
data = *(u32 *)dout;
data = cpu_to_be32(data);
dout += 4;
}
debug("Sending SPI 0x%x\n", data);
- reg_write(mxcs->base + MXC_CSPITXDATA, data);
+ reg_write(®s->txdata, data);
nbytes -= 4;
}
/* FIFO is written, now starts the transfer setting the XCH bit */
- reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg |
+ reg_write(®s->ctrl, mxcs->ctrl_reg |
MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
/* Wait until the TC (Transfer completed) bit is set */
- while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0)
+ while ((reg_read(®s->stat) & MXC_CSPICTRL_TC) == 0)
;
/* Transfer completed, clear any pending request */
- reg_write(mxcs->base + MXC_CSPISTAT,
- MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
+ reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
nbytes = (bitlen + 7) / 8;
cnt = nbytes % 32;
if (bitlen % 32) {
- data = reg_read(mxcs->base + MXC_CSPIRXDATA);
+ data = reg_read(®s->rxdata);
cnt = (bitlen % 32) / 8;
+ data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
debug("SPI Rx unaligned: 0x%x\n", data);
if (din) {
- for (i = 0; i < cnt; i++, data >>= 8) {
- *din++ = data & 0xFF;
- }
+ memcpy(din, &data, cnt);
+ din += cnt;
}
nbytes -= cnt;
}
while (nbytes > 0) {
u32 tmp;
- tmp = reg_read(mxcs->base + MXC_CSPIRXDATA);
+ tmp = reg_read(®s->rxdata);
data = cpu_to_be32(tmp);
debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
cnt = min(nbytes, sizeof(data));
}
-
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
spi_cs_activate(slave);
while (n_bytes > 0) {
-
if (n_bytes < MAX_SPI_BYTES)
blk_size = n_bytes;
else
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
- unsigned int ctrl_reg;
struct mxc_spi_slave *mxcs;
int ret;
mxcs->base = spi_bases[bus];
mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
-#ifdef CONFIG_MX51
- /* Can be used for i.MX31 too ? */
- ctrl_reg = 0;
- ret = spi_cfg(mxcs, cs, max_hz, mode);
+ ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
if (ret) {
printf("mxc_spi: cannot setup SPI controller\n");
free(mxcs);
return NULL;
}
-#else
- ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
- MXC_CSPICTRL_BITCOUNT(31) |
- MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
- MXC_CSPICTRL_EN |
- MXC_CSPICTRL_MODE;
-
- if (mode & SPI_CPHA)
- ctrl_reg |= MXC_CSPICTRL_PHA;
- if (mode & SPI_CPOL)
- ctrl_reg |= MXC_CSPICTRL_POL;
- if (mode & SPI_CS_HIGH)
- ctrl_reg |= MXC_CSPICTRL_SSPOL;
- mxcs->ctrl_reg = ctrl_reg;
-#endif
return &mxcs->slave;
}
int spi_claim_bus(struct spi_slave *slave)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
+ struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
- reg_write(mxcs->base + MXC_CSPIRESET, 1);
+ reg_write(®s->rxdata, 1);
udelay(1);
- reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
- reg_write(mxcs->base + MXC_CSPIPERIOD,
- MXC_CSPIPERIOD_32KHZ);
- reg_write(mxcs->base + MXC_CSPIINT, 0);
+ reg_write(®s->ctrl, mxcs->ctrl_reg);
+ reg_write(®s->period, MXC_CSPIPERIOD_32KHZ);
+ reg_write(®s->intr, 0);
return 0;
}
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+ GENERATED_GBL_DATA_SIZE)
+
/*
* Load address and memory test area should agree with
* board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
*/
-#define CONFIG_SYS_LOAD_ADDR 0x12000000
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x2000000)
/* memtest works on 63 MB in DRAM */
-#define CONFIG_SYS_MEMTEST_START 0x10000000
-#define CONFIG_SYS_MEMTEST_END 0x13F00000
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x3F00000)
+
+#define CONFIG_SYS_TEXT_BASE 0
/*-----------------------------------------------------------------------
* Static memory controller configuration
/* environments */
#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR 0x00060000
+#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
#define CONFIG_ENV_SIZE 0x20000
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * CompuLab, Ltd.
+ * Mike Rapoport <mike@compulab.co.il>
+ *
+ * Based on omap3_beagle.h
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the CompuLab CM-T35 board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_CM_T35 1 /* working with CM-T35 */
+
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT 1
+/*
+ * The early kernel mapping on ARM currently only maps from the base of DRAM
+ * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
+ * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
+ * so that leaves DRAM base to DRAM base + 0x4000 available.
+ */
+#define CONFIG_SYS_BOOTMAPSZ 0x4000
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+ /* initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3 /* UART3 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define MTDIDS_DEFAULT "nand0=nand"
+#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
+ "1920k(u-boot),128k(u-boot-env),"\
+ "4m(kernel),-(fs)"
+
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+#define CONFIG_TWL4030_LED 1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST 1
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
+ /* to access nand */
+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
+ /* to access nand at */
+ /* CS0 */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
+ /* devices */
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV "nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET 0x680000
+#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
+ /* partition */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY 10
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
+ "console=ttyS2,115200n8\0" \
+ "mpurate=500\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768MR-16@60\0" \
+ "defaultdisplay=dvi\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "nandroot=/dev/mtdblock4 rw\0" \
+ "nandrootfstype=jffs2\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${loadaddr} 280000 400000; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run nandboot; " \
+ "fi; " \
+ "fi; " \
+ "else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE 1
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "CM-T35 # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
+ /* works on */
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+ 0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
+ /* load address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE boot_flash_base
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND 1
+#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
+#define CONFIG_ENV_OFFSET boot_flash_off
+#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+
+#ifndef __ASSEMBLY__
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CM_T35_SMC911X_BASE 0x2C000000
+#define SB_T35_SMC911X_BASE (CM_T35_SMC911X_BASE + (16 << 20))
+#define CONFIG_SMC911X_BASE CM_T35_SMC911X_BASE
+#endif /* (CONFIG_CMD_NET) */
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 2
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#define CONFIG_DAVINCI_MMC_SD1
+#define CONFIG_MMC_MBLOCK
+
/* USB: OTG connector */
/* NYET -- #define CONFIG_USB_DAVINCI */
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
+#ifdef CONFIG_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#endif
+
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#undef CONFIG_ENV_IS_IN_FLASH
#endif
+#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_CMD_ENV
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
+#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
+#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOTCOMMAND \
"dhcp;bootm"
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 2
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#define CONFIG_DAVINCI_MMC_SD1
+#define CONFIG_MMC_MBLOCK
+
#define PINMUX4_USBDRVBUS_BITCLEAR 0x3000
#define PINMUX4_USBDRVBUS_BITSET 0x2000
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
+#ifdef CONFIG_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#endif
+
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#undef CONFIG_ENV_IS_IN_FLASH
#endif
+#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_CMD_ENV
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
+#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
+#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTCOMMAND \
"dhcp;bootm"
/* Spectrum Digital TMS320DM6467 EVM board */
#define DAVINCI_DM6467EVM
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_USE_NAND
+#define CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_SKIP_LOWLEVEL_INIT
/* SoC Configuration */
#define CONFIG_ARM926EJS /* arm926ejs CPU */
+
+/* Clock rates detection */
+#ifndef __ASSEMBLY__
+extern unsigned int davinci_arm_clk_get(void);
+#endif
+
+#define CFG_REFCLK_FREQ 27000000
+/* Arm Clock frequency */
+#define CONFIG_SYS_CLK_FREQ davinci_arm_clk_get()
+/* Timer Input clock freq */
+#define CONFIG_SYS_HZ_CLOCK (CONFIG_SYS_CLK_FREQ/2)
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK 27000000
#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM646X
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 10
+/* Network & Ethernet Configuration */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM 1
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#define CONFIG_CMD_NET
+
/* Flash & Environment */
#define CONFIG_SYS_NO_FLASH
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_CMD_MII
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
#define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */
#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*2)
+#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ
#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX51EVK Board
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <config_cmd_default.h>
+
+/*
+ * High Level Board Configuration Options
+ */
+/* An i.MX51 CPU */
+#define CONFIG_MX51
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_MX5_HCLK 24000000
+#define CONFIG_SYS_MX5_CLK32 32768
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_L2_OFF
+
+/*
+ * Bootloader Components Configuration
+ */
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#undef CONFIG_CMD_IMLS
+
+/*
+ * Environmental settings
+ */
+
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
+#define CONFIG_ENV_SIZE (4 * 1024)
+
+/*
+ * ATAG setup
+ */
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define BOARD_LATE_INIT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX51_UART1
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_MXC_GPIO
+
+/*
+ * SPI Interface
+ */
+#ifdef CONFIG_CMD_SPI
+
+#define CONFIG_HARD_SPI
+#define CONFIG_MXC_SPI
+#define CONFIG_DEFAULT_SPI_BUS 1
+#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
+
+/* SPI FLASH */
+#ifdef CONFIG_CMD_SF
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_CS (1 | 121 << 8)
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+#define CONFIG_SF_DEFAULT_SPEED 25000000
+
+#define CONFIG_ENV_SPI_CS (1 | 121 << 8)
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_MAX_HZ 25000000
+#define CONFIG_ENV_SPI_MODE (SPI_MODE_0)
+#define CONFIG_FSL_ENV_IN_SF
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_NO_FLASH
+
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+/* SPI PMIC */
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_BUS 0
+#define CONFIG_FSL_PMIC_CS (0 | 120 << 8)
+#define CONFIG_FSL_PMIC_CLK 25000000
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_RTC_MC13783
+#endif
+
+/*
+ * MMC Configs
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 2
+#endif
+
+/*
+ * ATA/IDE
+ */
+#ifdef CONFIG_CMD_IDE
+#define CONFIG_LBA48
+#undef CONFIG_IDE_LED
+#undef CONFIG_IDE_RESET
+
+#define CONFIG_MX51_PATA
+
+#define __io
+
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE 1
+
+#define CONFIG_SYS_ATA_BASE_ADDR 0x83fe0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
+
+#define CONFIG_SYS_ATA_DATA_OFFSET 0xa0
+#define CONFIG_SYS_ATA_REG_OFFSET 0xa0
+#define CONFIG_SYS_ATA_ALT_OFFSET 0xd8
+
+#define CONFIG_SYS_ATA_STRIDE 4
+
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MXC_ATA_PIO_MODE 4
+#endif
+
+/*
+ * Filesystems
+ */
+#ifdef CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#undef CONFIG_CMD_PING
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_DATE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_LOADADDR 0x90800000
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "Efika> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0x90000000
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_CMDLINE_EDITING
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_DDR_CLKSEL 0
+#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration for the MX35pdk Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX35
+#define CONFIG_MX35_HCLK_FREQ 24000000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Set TEXT at the beginning of the NOR flash */
+#define CONFIG_SYS_TEXT_BASE 0xA0000000
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define BOARD_LATE_INIT
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_MX35_PORT1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+#define CONFIG_MXC_SPI
+
+
+/*
+ * PMIC Configs
+ */
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_I2C
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
+
+/*
+ * MFD MC9SDZ60
+ */
+#define CONFIG_FSL_MC9SDZ60
+#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX35_UART1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
+
+/*
+ * Ethernet on the debug board (SMC911)
+ */
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT 1
+#define CONFIG_SMC911X_BASE CS5_BASE_ADDR
+
+#define CONFIG_HAS_ETH1
+#define CONFIG_NET_MULTI
+#define CONFIG_ETHPRIME
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x1F
+
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "MX35 U-Boot > "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:1m(boot),5m(linux)," \
+ "96m(root),8m(cfg),1938m(user);" \
+ "physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+ #define CONFIG_ENV_IS_IN_NAND
+ #define CONFIG_ENV_OFFSET (1024 * 1024)
+#endif
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_FLASH_SPANSION_S29WS_N
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
+#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_HOSTNAME "mx35pdk"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth1\0" \
+ "ethprime=smc911x\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=ttymxc0,${baudrate}\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "loadaddr=80800000\0" \
+ "kernel_addr_r=80800000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "update=protect off ${uboot_addr} +40000;" \
+ "erase ${uboot_addr} +40000;" \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
+ "upd=if run load;then echo Updating u-boot;if run update;" \
+ "then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "bootcmd=run net_nfs\0"
+
+#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/arch/imx-regs.h>
-
/* High Level Configuration Options */
#define CONFIG_MX51 /* in a mx51 */
#define CONFIG_L2_OFF
+#include <asm/arch/imx-regs.h>
/*
* Disabled for now due to build problems under Debian and a significant
* increase in the final file size: 144260 vs. 109536 Bytes.
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+#define CONFIG_BOARD_EARLY_INIT_F
+
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53-EVK Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MX53
+
+#define CONFIG_SYS_MX5_HCLK 24000000
+#define CONFIG_SYS_MX5_CLK32 32768
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_L2_OFF
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX53_UART1
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_MX53_PORT2 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+/* PMIC Configs */
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_I2C
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 2
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Eth Configs */
+#define CONFIG_HAS_ETH1
+#define CONFIG_NET_MULTI
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x1F
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
+#define CONFIG_SYS_TEXT_BASE 0x77800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "uimage=uImage\0" \
+ "mmcdev=0\0" \
+ "mmcpart=2\0" \
+ "mmcroot=/dev/mmcblk0p3 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm\0" \
+ "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "dhcp ${uimage}; bootm\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "MX53EVK U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0x70000000
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_CMDLINE_EDITING
+
+/* Stack sizes */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG Universal (s5pc100) board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
+#define CONFIG_S5P 1 /* which is in a S5P Family */
+#define CONFIG_S5PC210 1 /* which is in a S5PC210 */
+#define CONFIG_UNIVERSAL 1 /* working with Universal */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_L2_OFF 1
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_TEXT_BASE 0x44800000
+
+/* input clock of PLL: Universal has 24MHz input clock at S5PC210 */
+#define CONFIG_SYS_CLK_FREQ_C210 24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
+
+/* select serial console configuration */
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_SERIAL2 1 /* use SERIAL 2 */
+#define CONFIG_BAUDRATE 115200
+
+/* MMC */
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_S5P_MMC 1
+
+/* It should define before config_cmd_default.h */
+#define CONFIG_SYS_NO_FLASH 1
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_XIMG
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_ONENAND
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */
+#define MTDIDS_DEFAULT "onenand0=samsung-onenand"
+
+#define MTDPARTS_DEFAULT "mtdparts=samsung-onenand:"\
+ "128k(s-boot)"\
+ ",896k(bootloader)"\
+ ",256k(params)"\
+ ",2816k(config)"\
+ ",8m(csa)"\
+ ",7m(kernel)"\
+ ",1m(log)"\
+ ",12m(modem)"\
+ ",60m(qboot)"\
+ ",-(UBI)\0"
+
+#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
+
+#define MBRPARTS_DEFAULT "20M(permanent)"\
+ ",20M(boot)"\
+ ",1G(system)"\
+ ",100M(swap)"\
+ ",-(UMS)\0"
+
+#define CONFIG_BOOTARGS "Please use defined boot"
+#define CONFIG_BOOTCOMMAND "run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
+
+#define CONFIG_ENV_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7"
+#define CONFIG_BOOTBLOCK "10"
+#define CONFIG_UBIBLOCK "9"
+
+#define CONFIG_ENV_UBIFS_OPTION " rootflags=bulk_read,no_chk_data_crc "
+#define CONFIG_ENV_FLASHBOOT CONFIG_ENV_UBI_MTD CONFIG_ENV_UBIFS_OPTION \
+ "${mtdparts}"
+
+#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "updateb=" \
+ "onenand erase 0x0 0x100000;" \
+ "onenand write 0x42008000 0x0 0x100000\0" \
+ "updatek=" \
+ "onenand erase 0xc00000 0x500000;" \
+ "onenand write 0x41008000 0xc00000 0x500000\0" \
+ "bootk=" \
+ "run loaduimage; bootm 0x40007FC0\0" \
+ "updatemmc=" \
+ "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
+ "mmc boot 0 1 1 0\0" \
+ "updatebackup=" \
+ "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
+ "mmc boot 0 1 1 0\0" \
+ "updatebootb=" \
+ "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
+ "lpj=lpj=3981312\0" \
+ "ubifsboot=" \
+ "set bootargs root=ubi0!rootfs rootfstype=ubifs ${lpj} " \
+ CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \
+ CONFIG_ENV_COMMON_BOOT "; run bootk\0" \
+ "tftpboot=" \
+ "set bootargs root=ubi0!rootfs rootfstype=ubifs " \
+ CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \
+ CONFIG_ENV_COMMON_BOOT \
+ "; tftp 0x40007FC0 uImage; bootm 0x40007FC0\0" \
+ "nfsboot=" \
+ "set bootargs root=/dev/nfs rw " \
+ "nfsroot=${nfsroot},nolock,tcp " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
+ "; run bootk\0" \
+ "ramfsboot=" \
+ "set bootargs root=/dev/ram0 rw rootfstype=ext2 " \
+ "${console} ${meminfo} " \
+ "initrd=0x43000000,8M ramdisk=8192\0" \
+ "mmcboot=" \
+ "set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+ "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
+ "run loaduimage; bootm 0x40007FC0\0" \
+ "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
+ "boottrace=setenv opts initcall_debug; run bootcmd\0" \
+ "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
+ "verify=n\0" \
+ "rootfstype=ext4\0" \
+ "console=" CONFIG_DEFAULT_CONSOLE \
+ "mtdparts=" MTDPARTS_DEFAULT \
+ "mbrparts=" MBRPARTS_DEFAULT \
+ "meminfo=crashkernel=32M@0x50000000\0" \
+ "nfsroot=/nfsroot/arm\0" \
+ "bootblock=" CONFIG_BOOTBLOCK "\0" \
+ "ubiblock=" CONFIG_UBIBLOCK" \0" \
+ "ubi=enabled\0" \
+ "loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
+ "mmcdev=0\0" \
+ "mmcbootpart=2\0" \
+ "mmcrootpart=3\0" \
+ "opts=always_resume=1"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "Universal # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
+
+#define CONFIG_SYS_HZ 1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* Stack sizes */
+#define CONFIG_STACKSIZE (256 << 10) /* regular stack 256KB */
+
+/* Universal has 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
+#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */
+#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
+#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */
+
+#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_SYS_ONENAND_BASE 0x0C000000
+
+#define CONFIG_ENV_IS_IN_MMC 1
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 4096
+#define CONFIG_ENV_OFFSET ((32 - 4) << 10)/* 32KiB - 4KiB */
+
+#define CONFIG_DOS_PARTITION 1
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/arch/imx-regs.h>
#define CONFIG_MX51 /* in a mx51 */
#define CONFIG_L2_OFF
+#include <asm/arch/imx-regs.h>
+
#define CONFIG_SYS_MX5_HCLK 24000000
#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
/* Reg Power Control 2*/
#define WDIRESET (1 << 12)
+/* SWx Output Volts */
+#define SWX_OUT_MASK 0x1F
+#define SWX_OUT_1_25 0x1A
+#define SWX_OUT_1_30 0X1C
+
+/* Buck Switchers (SW1,2,3,4) Output Voltage */
+/*
+ * NOTE: These values are for SWxHI = 0,
+ * SWxHI = 1 adds 0.5V to the desired voltage
+ */
+#define SWx_0_600V 0
+#define SWx_0_625V 1
+#define SWx_0_650V 2
+#define SWx_0_675V 3
+#define SWx_0_700V 4
+#define SWx_0_725V 5
+#define SWx_0_750V 6
+#define SWx_0_775V 7
+#define SWx_0_800V 8
+#define SWx_0_825V 9
+#define SWx_0_850V 10
+#define SWx_0_875V 11
+#define SWx_0_900V 12
+#define SWx_0_925V 13
+#define SWx_0_950V 14
+#define SWx_0_975V 15
+#define SWx_1_000V 16
+#define SWx_1_025V 17
+#define SWx_1_050V 18
+#define SWx_1_075V 19
+#define SWx_1_100V 20
+#define SWx_1_125V 21
+#define SWx_1_150V 22
+#define SWx_1_175V 23
+#define SWx_1_200V 24
+#define SWx_1_225V 25
+#define SWx_1_250V 26
+#define SWx_1_275V 27
+#define SWx_1_300V 28
+#define SWx_1_325V 29
+#define SWx_1_350V 30
+#define SWx_1_375V 31
+#define SWx_VOLT_MASK 0x1F
+
#endif
--- /dev/null
+/*
+ * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de>
+ *
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_MC9SDZ60_H
+#define __ASM_ARCH_MC9SDZ60_H
+
+/**
+ * Register addresses for the MC9SDZ60
+ *
+ * @note: these match those in the kernel drivers/mxc/mcu_pmic/mc9s08dz60.h
+ * but not include/linux/mfd/mc9s08dz60/pmic.h
+ *
+ */
+enum mc9sdz60_reg {
+ MC9SDZ60_REG_VERSION = 0x00,
+ /* reserved 0x01 */
+ MC9SDZ60_REG_SECS = 0x02,
+ MC9SDZ60_REG_MINS = 0x03,
+ MC9SDZ60_REG_HRS = 0x04,
+ MC9SDZ60_REG_DAY = 0x05,
+ MC9SDZ60_REG_DATE = 0x06,
+ MC9SDZ60_REG_MONTH = 0x07,
+ MC9SDZ60_REG_YEAR = 0x08,
+ MC9SDZ60_REG_ALARM_SECS = 0x09,
+ MC9SDZ60_REG_ALARM_MINS = 0x0a,
+ MC9SDZ60_REG_ALARM_HRS = 0x0b,
+ /* reserved 0x0c */
+ /* reserved 0x0d */
+ MC9SDZ60_REG_TS_CONTROL = 0x0e,
+ MC9SDZ60_REG_X_LOW = 0x0f,
+ MC9SDZ60_REG_Y_LOW = 0x10,
+ MC9SDZ60_REG_XY_HIGH = 0x11,
+ MC9SDZ60_REG_X_LEFT_LOW = 0x12,
+ MC9SDZ60_REG_X_LEFT_HIGH = 0x13,
+ MC9SDZ60_REG_X_RIGHT = 0x14,
+ MC9SDZ60_REG_Y_TOP_LOW = 0x15,
+ MC9SDZ60_REG_Y_TOP_HIGH = 0x16,
+ MC9SDZ60_REG_Y_BOTTOM = 0x17,
+ /* reserved 0x18 */
+ /* reserved 0x19 */
+ MC9SDZ60_REG_RESET_1 = 0x1a,
+ MC9SDZ60_REG_RESET_2 = 0x1b,
+ MC9SDZ60_REG_POWER_CTL = 0x1c,
+ MC9SDZ60_REG_DELAY_CONFIG = 0x1d,
+ /* reserved 0x1e */
+ /* reserved 0x1f */
+ MC9SDZ60_REG_GPIO_1 = 0x20,
+ MC9SDZ60_REG_GPIO_2 = 0x21,
+ MC9SDZ60_REG_KPD_1 = 0x22,
+ MC9SDZ60_REG_KPD_2 = 0x23,
+ MC9SDZ60_REG_KPD_CONTROL = 0x24,
+ MC9SDZ60_REG_INT_ENABLE_1 = 0x25,
+ MC9SDZ60_REG_INT_ENABLE_2 = 0x26,
+ MC9SDZ60_REG_INT_FLAG_1 = 0x27,
+ MC9SDZ60_REG_INT_FLAG_2 = 0x28,
+ MC9SDZ60_REG_DES_FLAG = 0x29,
+};
+
+extern u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg);
+extern void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val);
+
+#endif /* __ASM_ARCH_MC9SDZ60_H */
struct mmc_cmd *cmd, struct mmc_data *data);
void (*set_ios)(struct mmc *mmc);
int (*init)(struct mmc *mmc);
+#ifdef CONFIG_MMC_MBLOCK
+ uint b_max;
+#endif
};
int mmc_register(struct mmc *mmc);
int xilinx_emaclite_initialize (bd_t *bis, int base_addr);
int sh_eth_initialize(bd_t *bis);
int dm9000_initialize(bd_t *bis);
+int fecmxc_initialize(bd_t *bis);
/* Boards with PCI network controllers can call this from their board_eth_init()
* function to initialize whatever's on board.
* Supported commands for configuration file
*/
static table_entry_t imximage_cmds[] = {
- {CMD_BOOT_FROM, "BOOT_FROM", "boot command", },
- {CMD_DATA, "DATA", "Reg Write Data", },
- {-1, "", "", },
+ {CMD_BOOT_FROM, "BOOT_FROM", "boot command", },
+ {CMD_DATA, "DATA", "Reg Write Data", },
+ {CMD_IMAGE_VERSION, "IMAGE_VERSION", "image version", },
+ {-1, "", "", },
};
/*
{-1, "", "Invalid", },
};
+/*
+ * IMXIMAGE version definition for i.MX chips
+ */
+static table_entry_t imximage_versions[] = {
+ {IMXIMAGE_V1, "", " (i.MX25/35/51 compatible)", },
+ {IMXIMAGE_V2, "", " (i.MX53 compatible)", },
+ {-1, "", " (Invalid)", },
+};
static struct imx_header imximage_header;
+static uint32_t imximage_version;
+
+static set_dcd_val_t set_dcd_val;
+static set_dcd_rst_t set_dcd_rst;
+static set_imx_hdr_t set_imx_hdr;
static uint32_t get_cfg_value(char *token, char *name, int linenr)
{
return value;
}
-static int imximage_check_image_types(uint8_t type)
+static uint32_t detect_imximage_version(struct imx_header *imx_hdr)
{
- if (type == IH_TYPE_IMXIMAGE)
- return EXIT_SUCCESS;
- else
- return EXIT_FAILURE;
+ imx_header_v1_t *hdr_v1 = &imx_hdr->header.hdr_v1;
+ imx_header_v2_t *hdr_v2 = &imx_hdr->header.hdr_v2;
+ flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
+ flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
+
+ /* Try to detect V1 */
+ if ((fhdr_v1->app_code_barker == APP_CODE_BARKER) &&
+ (hdr_v1->dcd_table.preamble.barker == DCD_BARKER))
+ return IMXIMAGE_V1;
+
+ /* Try to detect V2 */
+ if ((fhdr_v2->header.tag == IVT_HEADER_TAG) &&
+ (hdr_v2->dcd_table.header.tag == DCD_HEADER_TAG))
+ return IMXIMAGE_V2;
+
+ return IMXIMAGE_VER_INVALID;
}
-static int imximage_verify_header(unsigned char *ptr, int image_size,
- struct mkimage_params *params)
+static void err_imximage_version(int version)
{
+ fprintf(stderr,
+ "Error: Unsupported imximage version:%d\n", version);
- struct imx_header *imx_hdr = (struct imx_header *) ptr;
- flash_header_t *hdr = &imx_hdr->fhdr;
+ exit(EXIT_FAILURE);
+}
- /* Only a few checks can be done: search for magic numbers */
- if (hdr->app_code_barker != APP_CODE_BARKER)
- return -FDT_ERR_BADSTRUCTURE;
+static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
+ int fld, uint32_t value, uint32_t off)
+{
+ dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
+
+ switch (fld) {
+ case CFG_REG_SIZE:
+ /* Byte, halfword, word */
+ if ((value != 1) && (value != 2) && (value != 4)) {
+ fprintf(stderr, "Error: %s[%d] - "
+ "Invalid register size " "(%d)\n",
+ name, lineno, value);
+ exit(EXIT_FAILURE);
+ }
+ dcd_v1->addr_data[off].type = value;
+ break;
+ case CFG_REG_ADDRESS:
+ dcd_v1->addr_data[off].addr = value;
+ break;
+ case CFG_REG_VALUE:
+ dcd_v1->addr_data[off].value = value;
+ break;
+ default:
+ break;
- if (imx_hdr->dcd_table.preamble.barker != DCD_BARKER)
- return -FDT_ERR_BADSTRUCTURE;
+ }
+}
- return 0;
+static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
+ int fld, uint32_t value, uint32_t off)
+{
+ dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
+
+ switch (fld) {
+ case CFG_REG_ADDRESS:
+ dcd_v2->addr_data[off].addr = cpu_to_be32(value);
+ break;
+ case CFG_REG_VALUE:
+ dcd_v2->addr_data[off].value = cpu_to_be32(value);
+ break;
+ default:
+ break;
+
+ }
}
-static void imximage_print_header(const void *ptr)
+/*
+ * Complete setting up the rest field of DCD of V1
+ * such as barker code and DCD data length.
+ */
+static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
+ char *name, int lineno)
{
- struct imx_header *imx_hdr = (struct imx_header *) ptr;
- flash_header_t *hdr = &imx_hdr->fhdr;
- uint32_t size;
- uint32_t length;
- dcd_t *dcd = &imx_hdr->dcd_table;
+ dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
+
+ if (dcd_len > MAX_HW_CFG_SIZE_V1) {
+ fprintf(stderr, "Error: %s[%d] -"
+ "DCD table exceeds maximum size(%d)\n",
+ name, lineno, MAX_HW_CFG_SIZE_V1);
+ exit(EXIT_FAILURE);
+ }
+
+ dcd_v1->preamble.barker = DCD_BARKER;
+ dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
+}
+
+/*
+ * Complete setting up the reset field of DCD of V2
+ * such as DCD tag, version, length, etc.
+ */
+static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
+ char *name, int lineno)
+{
+ dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
+
+ if (dcd_len > MAX_HW_CFG_SIZE_V2) {
+ fprintf(stderr, "Error: %s[%d] -"
+ "DCD table exceeds maximum size(%d)\n",
+ name, lineno, MAX_HW_CFG_SIZE_V2);
+ exit(EXIT_FAILURE);
+ }
+
+ dcd_v2->header.tag = DCD_HEADER_TAG;
+ dcd_v2->header.length = cpu_to_be16(
+ dcd_len * sizeof(dcd_addr_data_t) + 8);
+ dcd_v2->header.version = DCD_VERSION;
+ dcd_v2->write_dcd_command.tag = DCD_COMMAND_TAG;
+ dcd_v2->write_dcd_command.length = cpu_to_be16(
+ dcd_len * sizeof(dcd_addr_data_t) + 4);
+ dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
+}
+
+static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
+ struct stat *sbuf,
+ struct mkimage_params *params)
+{
+ imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
+ flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
+ dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
+ uint32_t base_offset;
+
+ /* Set default offset */
+ imxhdr->flash_offset = FLASH_OFFSET_STANDARD;
+
+ /* Set magic number */
+ fhdr_v1->app_code_barker = APP_CODE_BARKER;
+
+ fhdr_v1->app_dest_ptr = params->addr;
+ fhdr_v1->app_dest_ptr = params->ep - imxhdr->flash_offset -
+ sizeof(struct imx_header);
+ fhdr_v1->app_code_jump_vector = params->ep;
+
+ base_offset = fhdr_v1->app_dest_ptr + imxhdr->flash_offset ;
+ fhdr_v1->dcd_ptr_ptr =
+ (uint32_t) (offsetof(flash_header_v1_t, dcd_ptr) -
+ offsetof(flash_header_v1_t, app_code_jump_vector) +
+ base_offset);
+
+ fhdr_v1->dcd_ptr = base_offset +
+ offsetof(imx_header_v1_t, dcd_table);
+
+ /* The external flash header must be at the end of the DCD table */
+ dcd_v1->addr_data[dcd_len].type = sbuf->st_size +
+ imxhdr->flash_offset +
+ sizeof(struct imx_header);
+
+ /* Security feature are not supported */
+ fhdr_v1->app_code_csf = 0;
+ fhdr_v1->super_root_key = 0;
+}
+
+static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
+ struct stat *sbuf,
+ struct mkimage_params *params)
+{
+ imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
+ flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
+
+ /* Set default offset */
+ imxhdr->flash_offset = FLASH_OFFSET_STANDARD;
+
+ /* Set magic number */
+ fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
+ fhdr_v2->header.length = cpu_to_be16(sizeof(flash_header_v2_t));
+ fhdr_v2->header.version = IVT_VERSION; /* 0x40 */
+
+ fhdr_v2->entry = params->ep;
+ fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
+ fhdr_v2->self = params->ep - sizeof(struct imx_header);
+
+ fhdr_v2->dcd_ptr = fhdr_v2->self +
+ offsetof(imx_header_v2_t, dcd_table);
+
+ fhdr_v2->boot_data_ptr = fhdr_v2->self +
+ offsetof(imx_header_v2_t, boot_data);
+
+ hdr_v2->boot_data.start = fhdr_v2->self - imxhdr->flash_offset;
+ hdr_v2->boot_data.size = sbuf->st_size +
+ imxhdr->flash_offset +
+ sizeof(struct imx_header);
+
+ /* Security feature are not supported */
+ fhdr_v2->csf = 0;
+}
+
+static void set_hdr_func(struct imx_header *imxhdr)
+{
+ switch (imximage_version) {
+ case IMXIMAGE_V1:
+ set_dcd_val = set_dcd_val_v1;
+ set_dcd_rst = set_dcd_rst_v1;
+ set_imx_hdr = set_imx_hdr_v1;
+ break;
+ case IMXIMAGE_V2:
+ set_dcd_val = set_dcd_val_v2;
+ set_dcd_rst = set_dcd_rst_v2;
+ set_imx_hdr = set_imx_hdr_v2;
+ break;
+ default:
+ err_imximage_version(imximage_version);
+ break;
+ }
+}
- size = imx_hdr->dcd_table.preamble.length;
- if (size > (MAX_HW_CFG_SIZE * sizeof(dcd_type_addr_data_t))) {
+static void print_hdr_v1(struct imx_header *imx_hdr)
+{
+ imx_header_v1_t *hdr_v1 = &imx_hdr->header.hdr_v1;
+ flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
+ dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
+ uint32_t size, length, ver;
+
+ size = dcd_v1->preamble.length;
+ if (size > (MAX_HW_CFG_SIZE_V1 * sizeof(dcd_type_addr_data_t))) {
fprintf(stderr,
"Error: Image corrupt DCD size %d exceed maximum %d\n",
(uint32_t)(size / sizeof(dcd_type_addr_data_t)),
- MAX_HW_CFG_SIZE);
+ MAX_HW_CFG_SIZE_V1);
+ exit(EXIT_FAILURE);
+ }
+
+ length = dcd_v1->preamble.length / sizeof(dcd_type_addr_data_t);
+ ver = detect_imximage_version(imx_hdr);
+
+ printf("Image Type: Freescale IMX Boot Image\n");
+ printf("Image Ver: %x", ver);
+ printf("%s\n", get_table_entry_name(imximage_versions, NULL, ver));
+ printf("Data Size: ");
+ genimg_print_size(dcd_v1->addr_data[length].type);
+ printf("Load Address: %08x\n", (uint32_t)fhdr_v1->app_dest_ptr);
+ printf("Entry Point: %08x\n", (uint32_t)fhdr_v1->app_code_jump_vector);
+}
+
+static void print_hdr_v2(struct imx_header *imx_hdr)
+{
+ imx_header_v2_t *hdr_v2 = &imx_hdr->header.hdr_v2;
+ flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
+ dcd_v2_t *dcd_v2 = &hdr_v2->dcd_table;
+ uint32_t size, version;
+
+ size = be16_to_cpu(dcd_v2->header.length) - 8;
+ if (size > (MAX_HW_CFG_SIZE_V2 * sizeof(dcd_addr_data_t))) {
+ fprintf(stderr,
+ "Error: Image corrupt DCD size %d exceed maximum %d\n",
+ (uint32_t)(size / sizeof(dcd_addr_data_t)),
+ MAX_HW_CFG_SIZE_V2);
exit(EXIT_FAILURE);
}
- length = dcd->preamble.length / sizeof(dcd_type_addr_data_t);
+ version = detect_imximage_version(imx_hdr);
printf("Image Type: Freescale IMX Boot Image\n");
+ printf("Image Ver: %x", version);
+ printf("%s\n", get_table_entry_name(imximage_versions, NULL, version));
printf("Data Size: ");
- genimg_print_size(dcd->addr_data[length].type);
- printf("Load Address: %08x\n", (unsigned int)hdr->app_dest_ptr);
- printf("Entry Point: %08x\n", (unsigned int)hdr->app_code_jump_vector);
+ genimg_print_size(hdr_v2->boot_data.size);
+ printf("Load Address: %08x\n", (uint32_t)fhdr_v2->boot_data_ptr);
+ printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
}
-static uint32_t imximage_parse_cfg_file(struct imx_header *imxhdr, char *name)
+static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
+ char *name, int lineno, int fld, int dcd_len)
+{
+ int value;
+ static int cmd_ver_first = ~0;
+
+ switch (cmd) {
+ case CMD_IMAGE_VERSION:
+ imximage_version = get_cfg_value(token, name, lineno);
+ if (cmd_ver_first == 0) {
+ fprintf(stderr, "Error: %s[%d] - IMAGE_VERSION "
+ "command need be the first before other "
+ "valid command in the file\n", name, lineno);
+ exit(EXIT_FAILURE);
+ }
+ cmd_ver_first = 1;
+ set_hdr_func(imxhdr);
+ break;
+ case CMD_BOOT_FROM:
+ imxhdr->flash_offset = get_table_entry_id(imximage_bootops,
+ "imximage boot option", token);
+ if (imxhdr->flash_offset == -1) {
+ fprintf(stderr, "Error: %s[%d] -Invalid boot device"
+ "(%s)\n", name, lineno, token);
+ exit(EXIT_FAILURE);
+ }
+ if (unlikely(cmd_ver_first != 1))
+ cmd_ver_first = 0;
+ break;
+ case CMD_DATA:
+ value = get_cfg_value(token, name, lineno);
+ (*set_dcd_val)(imxhdr, name, lineno, fld, value, dcd_len);
+ if (unlikely(cmd_ver_first != 1))
+ cmd_ver_first = 0;
+ break;
+ }
+}
+
+static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
+ char *token, char *name, int lineno, int fld, int *dcd_len)
+{
+ int value;
+
+ switch (fld) {
+ case CFG_COMMAND:
+ *cmd = get_table_entry_id(imximage_cmds,
+ "imximage commands", token);
+ if (*cmd < 0) {
+ fprintf(stderr, "Error: %s[%d] - Invalid command"
+ "(%s)\n", name, lineno, token);
+ exit(EXIT_FAILURE);
+ }
+ break;
+ case CFG_REG_SIZE:
+ parse_cfg_cmd(imxhdr, *cmd, token, name, lineno, fld, *dcd_len);
+ break;
+ case CFG_REG_ADDRESS:
+ case CFG_REG_VALUE:
+ if (*cmd != CMD_DATA)
+ return;
+
+ value = get_cfg_value(token, name, lineno);
+ (*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
+
+ if (fld == CFG_REG_VALUE)
+ (*dcd_len)++;
+ break;
+ default:
+ break;
+ }
+}
+static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
{
FILE *fd = NULL;
char *line = NULL;
char *token, *saveptr1, *saveptr2;
int lineno = 0;
- int fld, value;
+ int fld;
size_t len;
int dcd_len = 0;
- dcd_t *dcd = &imxhdr->dcd_table;
int32_t cmd;
fd = fopen(name, "r");
if (token[0] == '#')
break;
- /* parse all fields in a single line */
- switch (fld) {
- case CFG_COMMAND:
- cmd = get_table_entry_id(imximage_cmds,
- "imximage commands", token);
- if (cmd < 0) {
- fprintf(stderr,
- "Error: %s[%d] - "
- "Invalid command (%s)\n",
- name, lineno, token);
- exit(EXIT_FAILURE);
- }
- break;
- case CFG_REG_SIZE:
- switch (cmd) {
- case CMD_BOOT_FROM:
- /* Get flash header offset */
- imxhdr->flash_offset =
- get_table_entry_id(
- imximage_bootops,
- "imximage boot option",
- token);
- if (imxhdr->flash_offset == -1) {
- fprintf(stderr,
- "Error: %s[%d] -"
- "Invalid boot device"
- "(%s)\n",
- name, lineno, token);
- exit(EXIT_FAILURE);
- }
- break;
- case CMD_DATA:
- value = get_cfg_value(token,
- name, lineno);
-
- /* Byte, halfword, word */
- if ((value != 1) &&
- (value != 2) && (value != 4)) {
- fprintf(stderr,
- "Error: %s[%d] - "
- "Invalid register size "
- "(%d)\n",
- name, lineno, value);
- exit(EXIT_FAILURE);
- }
- dcd->addr_data[dcd_len].type = value;
- break;
- }
-
- case CFG_REG_ADDRESS:
- if (cmd == CMD_DATA)
- dcd->addr_data[dcd_len].addr =
- get_cfg_value(token,
- name, lineno);
- break;
- case CFG_REG_VALUE:
- if (cmd == CMD_DATA) {
- dcd->addr_data[dcd_len].value =
- get_cfg_value(token,
- name, lineno);
- dcd_len++;
- }
- break;
- }
+ parse_cfg_fld(imxhdr, &cmd, token, name,
+ lineno, fld, &dcd_len);
}
- if (dcd_len > MAX_HW_CFG_SIZE) {
- fprintf(stderr,
- "Error: %s[%d] -"
- "DCD table exceeds maximum size(%d)\n",
- name, lineno, MAX_HW_CFG_SIZE);
- }
}
- dcd->preamble.barker = DCD_BARKER;
- dcd->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
+
+ (*set_dcd_rst)(imxhdr, dcd_len, name, lineno);
fclose(fd);
return dcd_len;
}
-static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
- struct mkimage_params *params)
-{
- struct imx_header *hdr = (struct imx_header *)ptr;
- flash_header_t *fhdr = &hdr->fhdr;
- int dcd_len;
- dcd_t *dcd = &hdr->dcd_table;
- uint32_t base_offset;
- /* Set default offset */
- hdr->flash_offset = FLASH_OFFSET_STANDARD;
+static int imximage_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_IMXIMAGE)
+ return EXIT_SUCCESS;
+ else
+ return EXIT_FAILURE;
+}
- /* Set magic number */
- fhdr->app_code_barker = APP_CODE_BARKER;
+static int imximage_verify_header(unsigned char *ptr, int image_size,
+ struct mkimage_params *params)
+{
+ struct imx_header *imx_hdr = (struct imx_header *) ptr;
- /* Parse dcd configuration file */
- dcd_len = imximage_parse_cfg_file(hdr, params->imagename);
+ if (detect_imximage_version(imx_hdr) == IMXIMAGE_VER_INVALID)
+ return -FDT_ERR_BADSTRUCTURE;
- fhdr->app_dest_ptr = params->addr;
- fhdr->app_dest_ptr = params->ep - hdr->flash_offset -
- sizeof(struct imx_header);
- fhdr->app_code_jump_vector = params->ep;
+ return 0;
+}
- base_offset = fhdr->app_dest_ptr + hdr->flash_offset ;
- fhdr->dcd_ptr_ptr = (uint32_t) (offsetof(flash_header_t, dcd_ptr) -
- offsetof(flash_header_t, app_code_jump_vector) +
- base_offset);
+static void imximage_print_header(const void *ptr)
+{
+ struct imx_header *imx_hdr = (struct imx_header *) ptr;
+ uint32_t version = detect_imximage_version(imx_hdr);
+
+ switch (version) {
+ case IMXIMAGE_V1:
+ print_hdr_v1(imx_hdr);
+ break;
+ case IMXIMAGE_V2:
+ print_hdr_v2(imx_hdr);
+ break;
+ default:
+ err_imximage_version(version);
+ break;
+ }
+}
- fhdr->dcd_ptr = base_offset +
- offsetof(struct imx_header, dcd_table);
+static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
+ struct mkimage_params *params)
+{
+ struct imx_header *imxhdr = (struct imx_header *)ptr;
+ uint32_t dcd_len;
- /* The external flash header must be at the end of the DCD table */
- dcd->addr_data[dcd_len].type = sbuf->st_size +
- hdr->flash_offset +
- sizeof(struct imx_header);
+ /*
+ * In order to not change the old imx cfg file
+ * by adding VERSION command into it, here need
+ * set up function ptr group to V1 by default.
+ */
+ imximage_version = IMXIMAGE_V1;
+ set_hdr_func(imxhdr);
- /* Security feature are not supported */
- fhdr->app_code_csf = 0;
- fhdr->super_root_key = 0;
+ /* Parse dcd configuration file */
+ dcd_len = parse_cfg_file(imxhdr, params->imagename);
+ /* Set the imx header */
+ (*set_imx_hdr)(imxhdr, dcd_len, sbuf, params);
}
int imximage_check_params(struct mkimage_params *params)
* imximage parameters
*/
static struct image_type_params imximage_params = {
- .name = "Freescale i.MX 51 Boot Image support",
+ .name = "Freescale i.MX 5x Boot Image support",
.header_size = sizeof(struct imx_header),
.hdr = (void *)&imximage_header,
.check_image_type = imximage_check_image_types,
#ifndef _IMXIMAGE_H_
#define _IMXIMAGE_H_
-#define MAX_HW_CFG_SIZE 60 /* Max number of registers imx can set */
-#define MAX_EXP_SIZE 4
+#include <config.h>
+
+#define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */
+#define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
#define APP_CODE_BARKER 0xB1
#define DCD_BARKER 0xB17219E9
-#define HEADER_OFFSET 0x400
+#define HEADER_OFFSET 0x400
#define CMD_DATA_STR "DATA"
#define FLASH_OFFSET_STANDARD 0x400
#define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_ONENAND 0x100
+#define IVT_HEADER_TAG 0xD1
+#define IVT_VERSION 0x40
+#define DCD_HEADER_TAG 0xD2
+#define DCD_COMMAND_TAG 0xCC
+#define DCD_VERSION 0x40
+#define DCD_COMMAND_PARAM 0x4
+
enum imximage_cmd {
CMD_INVALID,
+ CMD_IMAGE_VERSION,
CMD_BOOT_FROM,
CMD_DATA
};
CFG_REG_VALUE
};
-typedef struct {
- uint8_t rsa_exponent[MAX_EXP_SIZE]; /* RSA public exponent */
- uint8_t *rsa_modulus; /* RSA modulus pointer */
- uint16_t exponent_size; /* Exponent size (bytes) */
- uint16_t modulus_size; /* Modulus size (bytes) */
- uint8_t init_flag; /* key initialized */
-} hab_rsa_public_key;
+enum imximage_version {
+ IMXIMAGE_VER_INVALID = -1,
+ IMXIMAGE_V1 = 1,
+ IMXIMAGE_V2
+};
typedef struct {
uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */
typedef struct {
dcd_preamble_t preamble;
- dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE];
-} dcd_t;
+ dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1];
+} dcd_v1_t;
typedef struct {
uint32_t app_code_jump_vector;
uint32_t super_root_key;
uint32_t dcd_ptr;
uint32_t app_dest_ptr;
-} flash_header_t;
+} flash_header_v1_t;
typedef struct {
uint32_t length; /* Length of data to be read from flash */
} flash_cfg_parms_t;
-struct imx_header {
- flash_header_t fhdr;
- dcd_t dcd_table;
+typedef struct {
+ flash_header_v1_t fhdr;
+ dcd_v1_t dcd_table;
flash_cfg_parms_t ext_header;
+} imx_header_v1_t;
+
+typedef struct {
+ uint32_t addr;
+ uint32_t value;
+} dcd_addr_data_t;
+
+typedef struct {
+ uint8_t tag;
+ uint16_t length;
+ uint8_t version;
+} __attribute__((packed)) ivt_header_t;
+
+typedef struct {
+ uint8_t tag;
+ uint16_t length;
+ uint8_t param;
+} __attribute__((packed)) write_dcd_command_t;
+
+typedef struct {
+ ivt_header_t header;
+ write_dcd_command_t write_dcd_command;
+ dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
+} dcd_v2_t;
+
+typedef struct {
+ uint32_t start;
+ uint32_t size;
+ uint32_t plugin;
+} boot_data_t;
+
+typedef struct {
+ ivt_header_t header;
+ uint32_t entry;
+ uint32_t reserved1;
+ uint32_t dcd_ptr;
+ uint32_t boot_data_ptr;
+ uint32_t self;
+ uint32_t csf;
+ uint32_t reserved2;
+} flash_header_v2_t;
+
+typedef struct {
+ flash_header_v2_t fhdr;
+ boot_data_t boot_data;
+ dcd_v2_t dcd_table;
+} imx_header_v2_t;
+
+struct imx_header {
+ union {
+ imx_header_v1_t hdr_v1;
+ imx_header_v2_t hdr_v2;
+ } header;
uint32_t flash_offset;
};
-struct reg_config {
- uint32_t raddr;
- uint32_t rdata;
-};
+typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
+ char *name, int lineno,
+ int fld, uint32_t value,
+ uint32_t off);
+
+typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
+ uint32_t dcd_len,
+ char *name, int lineno);
+
+typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr,
+ uint32_t dcd_len,
+ struct stat *sbuf,
+ struct mkimage_params *params);
#endif /* _IMXIMAGE_H_ */
projects / karo-tx-uboot.git / commitdiff