igep0020 ARM ARMV7 (OMAP3xx SoC)
igep0030 ARM ARMV7 (OMAP3xx SoC)
igep0032 ARM ARMV7 (OMAP3xx SoC)
+ igep0033 ARM ARMV7 (AM33xx Soc)
Eric Benard <eric@eukrea.com>
Igor Grinberg <grinberg@compulab.co.il>
- cm-t35 ARM ARMV7 (OMAP3xx Soc)
+ cm_t35 ARM ARMV7 (OMAP3xx Soc)
Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than
directly. You should not need to touch this setting.
+- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
+ This is set by OMAP boards for the max time that reset should
+ be asserted. See doc/README.omap-reset-time for details on how
+ the value can be calulated on a given board.
The following definitions that deal with the placement and management
of environment data (variable area); in general, we support the
#include <asm/arch/emif_defs.h>
#include <asm/arch/pll_defs.h>
+void davinci_enable_uart0(void)
+{
+ lpsc_on(DAVINCI_LPSC_UART0);
+
+ /* Bringup UART0 out of reset */
+ REG(UART0_PWREMU_MGMT) = 0x00006001;
+}
+
#if defined(CONFIG_SYS_DA850_PLL_INIT)
void da850_waitloop(unsigned long loopcnt)
{
#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0)
/* PRCM */
+#define ENET_CLKCTRL_CMPL 0x30000
+
#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500)
struct cm_def {
unsigned int resv5[2];
unsigned int gpmcclkctrl;
unsigned int ethernet0clkctrl;
- unsigned int resv6[1];
+ unsigned int ethernet1clkctrl;
unsigned int mpuclkctrl;
unsigned int debugssclkctrl;
unsigned int l3clkctrl;
unsigned int custefuseclkctrl;
};
+#define SATA_PLL_BASE (CTRL_BASE + 0x0720)
+
+struct sata_pll {
+ unsigned int pllcfg0;
+ unsigned int pllcfg1;
+ unsigned int pllcfg2;
+ unsigned int pllcfg3;
+ unsigned int pllcfg4;
+ unsigned int pllstatus;
+ unsigned int rxstatus;
+ unsigned int txstatus;
+ unsigned int testcfg;
+};
+
+#define SEL_IN_FREQ (0x1 << 31)
+#define DIGCLRZ (0x1 << 30)
+#define ENDIGLDO (0x1 << 4)
+#define APLL_CP_CURR (0x1 << 3)
+#define ENBGSC_REF (0x1 << 2)
+#define ENPLLLDO (0x1 << 1)
+#define ENPLL (0x1 << 0)
+
+#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
+#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
+#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
+#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
+ ENPLLLDO | ENPLL)
+
+#define PLL_LOCK (0x1 << 0)
+
+#define ENSATAMODE (0x1 << 31)
+#define PLLREFSEL (0x1 << 30)
+#define MDIVINT (0x4b << 18)
+#define EN_CLKAUX (0x1 << 5)
+#define EN_CLK125M (0x1 << 4)
+#define EN_CLK100M (0x1 << 3)
+#define EN_CLK50M (0x1 << 2)
+
+#define SATA_PLLCFG1 (ENSATAMODE | \
+ PLLREFSEL | \
+ MDIVINT | \
+ EN_CLKAUX | \
+ EN_CLK125M | \
+ EN_CLK100M | \
+ EN_CLK50M)
+
+#define DIGLDO_EN_CAPLESSMODE (0x1 << 22)
+#define PLLDO_EN_LDO_STABLE (0x1 << 11)
+#define PLLDO_EN_BUF_CUR (0x1 << 7)
+#define PLLDO_EN_LP (0x1 << 6)
+#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1)
+
+#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \
+ PLLDO_EN_LDO_STABLE | \
+ PLLDO_EN_BUF_CUR | \
+ PLLDO_EN_LP | \
+ PLLDO_CTRL_TRIM_1_4V)
const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
+const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
/*
* Enable the peripheral clock for required peripherals
writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
;
+
+ /* Ethernet */
+ writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
+ writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
+ while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
+ ;
+ writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
+ while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
+ ;
}
/*
pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
}
+void sata_pll_config(void)
+{
+ /*
+ * This sequence for configuring the SATA PLL
+ * resident in the control module is documented
+ * in TI8148 TRM section 21.3.1
+ */
+ writel(SATA_PLLCFG1, &spll->pllcfg1);
+ udelay(50);
+
+ writel(SATA_PLLCFG3, &spll->pllcfg3);
+ udelay(50);
+
+ writel(SATA_PLLCFG0_1, &spll->pllcfg0);
+ udelay(50);
+
+ writel(SATA_PLLCFG0_2, &spll->pllcfg0);
+ udelay(50);
+
+ writel(SATA_PLLCFG0_3, &spll->pllcfg0);
+ udelay(50);
+
+ writel(SATA_PLLCFG0_4, &spll->pllcfg0);
+ udelay(50);
+
+ while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
+ ;
+}
+
void enable_emif_clocks(void) {};
void enable_dmm_clocks(void)
/* Enable the control module */
writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
+ /* Configure PLLs */
mpu_pll_config();
-
l3_pll_config();
+ sata_pll_config();
/* Enable the required peripherals */
enable_per_clocks();
int print_cpuinfo(void)
{
char *cpu_s, *sec_s;
- int arm_freq, ddr_freq;
switch (get_cpu_type()) {
case AM335X:
sec_s = "?";
}
- printf("%s-%s rev %d\n",
- cpu_s, sec_s, get_cpu_rev());
-
- /* TODO: Print ARM and DDR frequencies */
+ printf("%s-%s rev %d\n", cpu_s, sec_s, get_cpu_rev());
return 0;
}
*/
ldr sp, =CONFIG_SYS_INIT_SP_ADDR
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
+#ifdef CONFIG_SPL_BUILD
+ ldr r8, =gdata
+#else
+ sub sp, #GD_SIZE
+ bic sp, sp, #7
+ mov r8, sp
+#endif
/*
* Save the old lr(passed in ip) and the current lr to stack
*/
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
-/*
- * This is used to verify if the configuration header
- * was executed by rom code prior to control of transfer
- * to the bootloader. SPL is responsible for saving and
- * passing the boot_params pointer to the u-boot.
- */
-struct omap_boot_parameters boot_params __attribute__ ((section(".data")));
+DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
-/*
- * We use static variables because global data is not ready yet.
- * Initialized data is available in SPL right from the beginning.
- * We would not typically need to save these parameters in regular
- * U-Boot. This is needed only in SPL at the moment.
- */
-u32 omap_bootmode = MMCSD_MODE_FAT;
-
u32 spl_boot_device(void)
{
- return (u32) (boot_params.omap_bootdevice);
+ return (u32) (gd->arch.omap_boot_params.omap_bootdevice);
}
u32 spl_boot_mode(void)
{
- return omap_bootmode;
+ return gd->arch.omap_boot_params.omap_bootmode;
}
void spl_board_init(void)
}
return 0;
}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+ typedef void __noreturn (*image_entry_noargs_t)(u32 *);
+ image_entry_noargs_t image_entry =
+ (image_entry_noargs_t) spl_image->entry_point;
+
+ debug("image entry point: 0x%X\n", spl_image->entry_point);
+ /* Pass the saved boot_params from rom code */
+ image_entry((u32 *)&gd->arch.omap_boot_params);
+}
#endif
setup_non_essential_dplls();
enable_non_essential_clocks();
#endif
+ setup_warmreset_time();
break;
default:
break;
else
ddr3_init(base, regs);
}
+ if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
+ set_lpmode_selfrefresh(base);
+ emif_reset_phy(base);
+ ddr3_leveling(base, regs);
+ }
/* Write to the shadow registers */
emif_update_timings(base, regs);
in_sdram = running_from_sdram();
debug("in_sdram = %d\n", in_sdram);
- if (!(in_sdram || warm_reset())) {
- if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
+ if (!in_sdram) {
+ if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
bypass_dpll((*prcm)->cm_clkmode_dpll_core);
- else
+ else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
}
}
#ifdef CONFIG_SPL_BUILD
-static void init_boot_params(void)
-{
- boot_params_ptr = (u32 *) &boot_params;
-}
-
void spl_display_print(void)
{
omap_rev_string();
{
}
+static void save_omap_boot_params(void)
+{
+ u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
+ u8 boot_device;
+ u32 dev_desc, dev_data;
+
+ if ((rom_params < NON_SECURE_SRAM_START) ||
+ (rom_params > NON_SECURE_SRAM_END))
+ return;
+
+ /*
+ * rom_params can be type casted to omap_boot_parameters and
+ * used. But it not correct to assume that romcode structure
+ * encoding would be same as u-boot. So use the defined offsets.
+ */
+ gd->arch.omap_boot_params.omap_bootdevice = boot_device =
+ *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
+
+ gd->arch.omap_boot_params.ch_flags =
+ *((u8 *)(rom_params + CH_FLAGS_OFFSET));
+
+ if ((boot_device >= MMC_BOOT_DEVICES_START) &&
+ (boot_device <= MMC_BOOT_DEVICES_END)) {
+ if ((omap_hw_init_context() ==
+ OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
+ gd->arch.omap_boot_params.omap_bootmode =
+ *((u8 *)(rom_params + BOOT_MODE_OFFSET));
+ } else {
+ dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET));
+ dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET));
+ gd->arch.omap_boot_params.omap_bootmode =
+ *((u32 *)(dev_data + BOOT_MODE_OFFSET));
+ }
+ }
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+/*
+ * SOC specific cpu init
+ */
+int arch_cpu_init(void)
+{
+ save_omap_boot_params();
+ return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
/*
* Routine: s_init
* Description: Does early system init of watchdog, muxing, andclocks
*/
void s_init(void)
{
+ /*
+ * Save the boot parameters passed from romcode.
+ * We cannot delay the saving further than this,
+ * to prevent overwrites.
+ */
+#ifdef CONFIG_SPL_BUILD
+ save_omap_boot_params();
+#endif
init_omap_revision();
hw_data_init();
/* For regular u-boot sdram_init() is called from dram_init() */
sdram_init();
- init_boot_params();
#endif
}
#include <config.h>
#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
#include <asm/arch/spl.h>
#include <linux/linkage.h>
ENTRY(save_boot_params)
- /*
- * See if the rom code passed pointer is valid:
- * It is not valid if it is not in non-secure SRAM
- * This may happen if you are booting with the help of
- * debugger
- */
- ldr r2, =NON_SECURE_SRAM_START
- cmp r2, r0
- bgt 1f
- ldr r2, =NON_SECURE_SRAM_END
- cmp r2, r0
- blt 1f
-
- /*
- * store the boot params passed from rom code or saved
- * and passed by SPL
- */
- cmp r0, #0
- beq 1f
- ldr r1, =boot_params
+ ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
str r0, [r1]
-#ifdef CONFIG_SPL_BUILD
- /* Store the boot device in spl_boot_device */
- ldrb r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device
- and r2, #BOOT_DEVICE_MASK
- ldr r3, =boot_params
- strb r2, [r3, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r1
-
- /*
- * boot mode is only valid for device that can be raw or FAT booted.
- * in other cases it may be fatal to look. While platforms differ
- * in the values used for each MMC slot, they are contiguous.
- */
- cmp r2, #MMC_BOOT_DEVICES_START
- blt 2f
- cmp r2, #MMC_BOOT_DEVICES_END
- bgt 2f
- /* Store the boot mode (raw/FAT) in omap_bootmode */
- ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr
- ldr r2, [r2, #DEV_DATA_PTR_OFFSET] @ get the pDeviceData ptr
- ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode
- ldr r3, =omap_bootmode
- str r2, [r3]
-#endif
-2:
- ldrb r2, [r0, #CH_FLAGS_OFFSET]
- ldr r3, =boot_params
- strb r2, [r3, #CH_FLAGS_OFFSET]
-1:
bx lr
ENDPROC(save_boot_params)
{
return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK);
}
+
+void __weak setup_warmreset_time(void)
+{
+}
#include <asm/utils.h>
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
-u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
+u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
+u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
#endif
#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
struct vcores_data const **omap_vcores =
(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
struct omap_sys_ctrl_regs const **ctrl =
- (struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL;
+ (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
/*
* The M & N values in the following tables are created using the
#include <asm/sizes.h>
#include <asm/emif.h>
#include <asm/arch/gpio.h>
+#include <asm/omap_common.h>
DECLARE_GLOBAL_DATA_PTR;
-u32 *const omap_si_rev = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
+u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
static const struct gpio_bank gpio_bank_44xx[6] = {
{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
-static u32 *const T_num = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_NUM;
-static u32 *const T_den = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_DEN;
+static u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
+static u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
#endif
#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
struct vcores_data const **omap_vcores =
(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
struct omap_sys_ctrl_regs const **ctrl =
- (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;
+ (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
/* OPP HIGH FREQUENCY for ES2.0 */
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
};
u32 const clk_modules_hw_auto_essential[] = {
+ (*prcm)->cm_l3init_hsusbtll_clkctrl,
0
};
(*prcm)->cm_l4per_i2c2_clkctrl,
(*prcm)->cm_l4per_i2c3_clkctrl,
(*prcm)->cm_l4per_i2c4_clkctrl,
- (*prcm)->cm_l3init_hsusbtll_clkctrl,
+ (*prcm)->cm_l4per_i2c5_clkctrl,
(*prcm)->cm_l3init_hsusbhost_clkctrl,
(*prcm)->cm_l3init_fsusb_clkctrl,
0
#include <asm/utils.h>
#include <asm/arch/gpio.h>
#include <asm/emif.h>
+#include <asm/omap_common.h>
DECLARE_GLOBAL_DATA_PTR;
-u32 *const omap_si_rev = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
+u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
static struct gpio_bank gpio_bank_54xx[6] = {
{ (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
{
return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
}
+
+void setup_warmreset_time(void)
+{
+ u32 rst_time, rst_val;
+
+#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
+ rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
+#else
+ rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
+#endif
+ rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
+
+ if (rst_time > RSTTIME1_MASK)
+ rst_time = RSTTIME1_MASK;
+
+ rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
+ rst_val |= rst_time;
+ writel(rst_val, (*prcm)->prm_rsttime);
+}
.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
.prm_rstctrl = 0x4ae07c00,
.prm_rstst = 0x4ae07c04,
+ .prm_rsttime = 0x4ae07c08,
.prm_vc_val_bypass = 0x4ae07ca0,
.prm_vc_cfg_i2c_mode = 0x4ae07cb4,
.prm_vc_cfg_i2c_clk = 0x4ae07cb8,
.cm_wkupaon_scrm_clkctrl = 0x4ae07890,
.prm_rstctrl = 0x4ae07d00,
.prm_rstst = 0x4ae07d04,
+ .prm_rsttime = 0x4ae07d08,
.prm_vc_val_bypass = 0x4ae07da0,
.prm_vc_cfg_i2c_mode = 0x4ae07db4,
.prm_vc_cfg_i2c_clk = 0x4ae07db8,
#define MT41J512M8RH125_PHY_WR_DATA 0x74
#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
+/* Samsung K4B2G1646E-BIH9 */
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x06
+#define K4B2G1646EBIH9_EMIF_TIM1 0x0888A39B
+#define K4B2G1646EBIH9_EMIF_TIM2 0x2A04011A
+#define K4B2G1646EBIH9_EMIF_TIM3 0x501F820F
+#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C24AB2
+#define K4B2G1646EBIH9_EMIF_SDREF 0x0000093B
+#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
+#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1
+#define K4B2G1646EBIH9_RATIO 0x40
+#define K4B2G1646EBIH9_INVERT_CLKOUT 0x1
+#define K4B2G1646EBIH9_RD_DQS 0x3B
+#define K4B2G1646EBIH9_WR_DQS 0x85
+#define K4B2G1646EBIH9_PHY_FIFO_WE 0x100
+#define K4B2G1646EBIH9_PHY_WR_DATA 0xC1
+#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
+
/**
* Configure DMM
*/
/* Control Module Base Address */
#define CTRL_BASE 0x48140000
+#define CTRL_DEVICE_BASE 0x48140600
/* PRCM Base Address */
#define PRCM_BASE 0x48180000
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000
#endif
-
-/* ROM code defines */
-/* Boot device */
-#define BOOT_DEVICE_MASK 0xFF
-#define BOOT_DEVICE_OFFSET 0x8
-#define DEV_DESC_PTR_OFFSET 0x4
-#define DEV_DATA_PTR_OFFSET 0x18
-#define BOOT_MODE_OFFSET 0x8
-#define RESET_REASON_OFFSET 0x9
-#define CH_FLAGS_OFFSET 0xA
-
-#define CH_FLAGS_CHSETTINGS (0x1 << 0)
-#define CH_FLAGS_CHRAM (0x1 << 1)
-#define CH_FLAGS_CHFLASH (0x1 << 2)
-#define CH_FLAGS_CHMMCSD (0x1 << 3)
-
-#ifndef __ASSEMBLY__
-struct omap_boot_parameters {
- char *boot_message;
- unsigned int mem_boot_descriptor;
- unsigned char omap_bootdevice;
- unsigned char reset_reason;
- unsigned char ch_flags;
-};
-#endif
#endif
#define PSC_PSC0_MODULE_ID_CNT 16
#define PSC_PSC1_MODULE_ID_CNT 32
+#define UART0_PWREMU_MGMT (0x01c42030)
+
struct davinci_psc_regs {
dv_reg revid;
dv_reg rsvd0[71];
#define MASK_ALE 0x08
#endif
+#ifdef CONFIG_SYS_NAND_MASK_CLE
+#undef MASK_CLE
+#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
+#endif
+#ifdef CONFIG_SYS_NAND_MASK_ALE
+#undef MASK_ALE
+#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
+#endif
+
#define NAND_READ_START 0x00
#define NAND_READ_END 0x30
#define NAND_STATUS 0x70
#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4030D000
-/* Temporary SRAM stack used while low level init is done */
-#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
-/* SRAM scratch space entries */
-#define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR
-#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
-#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
-#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
-#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
-#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
-#define OMAP4_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
-#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
-
-/* ROM code defines */
-/* Boot device */
-#define BOOT_DEVICE_MASK 0xFF
-#define BOOT_DEVICE_OFFSET 0x8
-#define DEV_DESC_PTR_OFFSET 0x4
-#define DEV_DATA_PTR_OFFSET 0x18
-#define BOOT_MODE_OFFSET 0x8
-#define RESET_REASON_OFFSET 0x9
-#define CH_FLAGS_OFFSET 0xA
-
-#define CH_FLAGS_CHSETTINGS (0x1 << 0)
-#define CH_FLAGS_CHRAM (0x1 << 1)
-#define CH_FLAGS_CHFLASH (0x1 << 2)
-#define CH_FLAGS_CHMMCSD (0x1 << 3)
-
-#ifndef __ASSEMBLY__
-struct omap_boot_parameters {
- char *boot_message;
- unsigned int mem_boot_descriptor;
- unsigned char omap_bootdevice;
- unsigned char reset_reason;
- unsigned char ch_flags;
-};
-#endif
#endif
#include <asm/omap_common.h>
#include <asm/arch/mux_omap4.h>
+DECLARE_GLOBAL_DATA_PTR;
+
struct omap_sysinfo {
char *board_string;
};
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
u32 warm_reset(void);
void force_emif_self_refresh(void);
-/*
- * This is used to verify if the configuration header
- * was executed by Romcode prior to control of transfer
- * to the bootloader. SPL is responsible for saving and
- * passing this to the u-boot.
- */
-extern struct omap_boot_parameters boot_params;
+void setup_warmreset_time(void);
static inline u32 running_from_sdram(void)
{
* variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
* mandatory section if CH is present.
*/
- if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
+ if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
return 0;
else
return running_from_sdram();
#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8
#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8)
+/* PRM_RSTTIME */
+#define RSTTIME1_SHIFT 0
+#define RSTTIME1_MASK (0x3ff << 0)
+
/* Clock frequencies */
#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
#define OMAP_SYS_CLK_IND_38_4_MHZ 6
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
+/*
+ * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
+ * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
+ * into microsec and passing the value.
+ */
+#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
#endif /* _CLOCKS_OMAP5_H_ */
#define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000)
#define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000)
#define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000)
+#define I2C_BASE4 (OMAP54XX_L4_PER_BASE + 0x7A000)
+#define I2C_BASE5 (OMAP54XX_L4_PER_BASE + 0x7C000)
/* MUSB base */
#define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000)
#ifndef _OMAP5_I2C_H_
#define _OMAP5_I2C_H_
-#define I2C_BUS_MAX 3
+#define I2C_BUS_MAX 5
#define I2C_DEFAULT_BASE I2C_BASE1
struct i2c {
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000
-#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
-/*
- * SRAM scratch space entries
- */
-#define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR
-#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
-#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
-#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
-#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
-#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
-#define OMAP5_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
-#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
-
/* Silicon revisions */
#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
#define OMAP4430_ES1_0 0x44300100
#define OMAP4460_ES1_0 0x44600100
#define OMAP4460_ES1_1 0x44600110
-/* ROM code defines */
-/* Boot device */
-#define BOOT_DEVICE_MASK 0xFF
-#define BOOT_DEVICE_OFFSET 0x8
-#define DEV_DESC_PTR_OFFSET 0x4
-#define DEV_DATA_PTR_OFFSET 0x18
-#define BOOT_MODE_OFFSET 0x8
-#define RESET_REASON_OFFSET 0x9
-#define CH_FLAGS_OFFSET 0xA
-
-#define CH_FLAGS_CHSETTINGS (0x1 << 0)
-#define CH_FLAGS_CHRAM (0x1 << 1)
-#define CH_FLAGS_CHFLASH (0x1 << 2)
-#define CH_FLAGS_CHMMCSD (0x1 << 3)
-
/* CONTROL_SRCOMP_XXX_SIDE */
#define OVERRIDE_XS_SHIFT 30
#define OVERRIDE_XS_MASK (1 << 30)
s8 multiply_factor;
};
-struct omap_boot_parameters {
- char *boot_message;
- unsigned int mem_boot_descriptor;
- unsigned char omap_bootdevice;
- unsigned char reset_reason;
- unsigned char ch_flags;
-};
-
struct ctrl_ioregs {
u32 ctrl_ddrch;
u32 ctrl_lpddr2ch;
#include <asm/omap_common.h>
#include <asm/arch/clocks.h>
+DECLARE_GLOBAL_DATA_PTR;
+
struct pad_conf_entry {
u32 offset;
u32 val;
void force_emif_self_refresh(void);
void get_ioregs(const struct ctrl_ioregs **regs);
void srcomp_enable(void);
-
-/*
- * This is used to verify if the configuration header
- * was executed by Romcode prior to control of transfer
- * to the bootloader. SPL is responsible for saving and
- * passing this to the u-boot.
- */
-extern struct omap_boot_parameters boot_params;
+void setup_warmreset_time(void);
static inline u32 running_from_sdram(void)
{
* variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
* mandatory section if CH is present.
*/
- if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
+ if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
return 0;
else
return running_from_sdram();
#endif
}
+static inline u32 div_round_up(u32 num, u32 den)
+{
+ return (num + den - 1)/den;
+}
+
+static inline u32 usec_to_32k(u32 usec)
+{
+ return div_round_up(32768 * usec, 1000000);
+}
#endif
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
+#ifdef CONFIG_OMAP
+#include <asm/omap_boot.h>
+#endif
+
/* Architecture-specific global data */
struct arch_global_data {
#if defined(CONFIG_FSL_ESDHC)
unsigned long tlb_addr;
unsigned long tlb_size;
#endif
+
+#ifdef CONFIG_OMAP
+ struct omap_boot_parameters omap_boot_params;
+#endif
};
#include <asm-generic/global_data.h>
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ROM code defines */
+/* Boot device */
+#define BOOT_DEVICE_MASK 0xFF
+#define BOOT_DEVICE_OFFSET 0x8
+#define DEV_DESC_PTR_OFFSET 0x4
+#define DEV_DATA_PTR_OFFSET 0x18
+#define BOOT_MODE_OFFSET 0x8
+#define RESET_REASON_OFFSET 0x9
+#define CH_FLAGS_OFFSET 0xA
+
+#define CH_FLAGS_CHSETTINGS (0x1 << 0)
+#define CH_FLAGS_CHRAM (0x1 << 1)
+#define CH_FLAGS_CHFLASH (0x1 << 2)
+#define CH_FLAGS_CHMMCSD (0x1 << 3)
+
+#ifndef __ASSEMBLY__
+struct omap_boot_parameters {
+ char *boot_message;
+ unsigned int mem_boot_descriptor;
+ unsigned char omap_bootdevice;
+ unsigned char reset_reason;
+ unsigned char ch_flags;
+ unsigned long omap_bootmode;
+};
+#endif
#ifndef _OMAP_COMMON_H_
#define _OMAP_COMMON_H_
+#ifndef __ASSEMBLY__
+
#include <common.h>
#define NUM_SYS_CLKS 8
u32 cm_wkupaon_io_srcomp_clkctrl;
u32 prm_rstctrl;
u32 prm_rstst;
+ u32 prm_rsttime;
u32 prm_vc_val_bypass;
u32 prm_vc_cfg_i2c_mode;
u32 prm_vc_cfg_i2c_clk;
extern u32 *const omap_si_rev;
return *omap_si_rev;
}
+#endif
/*
* silicon revisions.
/* DRA7XX */
#define DRA752_ES1_0 0x07520100
+
+/*
+ * SRAM scratch space entries
+ */
+#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
+#define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR
+#define OMAP_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
+#define OMAP_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
+#define OMAP_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
+#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
+#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
+#define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
+#define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24)
+#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+
#endif /* _OMAP_COMMON_H_ */
#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Authors: Nikita Kiryanov <nikita@compulab.co.il>
+# Igor Grinberg <grinberg@compulab.co.il>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
+# Foundation, Inc.
include $(TOPDIR)/config.mk
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
+
+#########################################################################
/*
- * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
+ * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
*
* Authors: Mike Rapoport <mike@compulab.co.il>
* Igor Grinberg <grinberg@compulab.co.il>
{
u8 val;
- if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, TWL4030_BASEADD_GPIO))
+ if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val))
return -1;
return !(val & 1);
static void reset_net_chip(void)
{
/* Set GPIO1 of TPS65930 as output */
- twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
- TWL4030_BASEADD_GPIO + 0x03);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03,
+ 0x02);
/* Send a pulse on the GPIO pin */
- twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
- TWL4030_BASEADD_GPIO + 0x0C);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
+ 0x02);
udelay(1);
- twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
- TWL4030_BASEADD_GPIO + 0x09);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09,
+ 0x02);
mdelay(40);
- twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
- TWL4030_BASEADD_GPIO + 0x0C);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
+ 0x02);
mdelay(1);
}
#else
udelay(1000);
offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
- twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, offset);
+ twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val);
/* Set GPIO6 and GPIO7 of TPS65930 as output */
val |= 0xC0;
- twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, val, offset);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val);
offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1;
/* Take both PHYs out of reset */
- twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0xC0, offset);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0);
udelay(1);
return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
/*
- * (C) Copyright 2012 CompuLab, Ltd. <www.compulab.co.il>
+ * (C) Copyright 2012 - 2013 CompuLab, Ltd. <www.compulab.co.il>
*
* Authors: Nikita Kiryanov <nikita@compulab.co.il>
*
/*
- * (C) Copyright 2011
- * CompuLab, Ltd. <www.compulab.co.il>
+ * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
*
* Author: Igor Grinberg <grinberg@compulab.co.il>
*
--- /dev/null
+#
+# Makefile
+#
+# Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS := mux.o
+endif
+
+COBJS += board.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Board functions for IGEP COM AQUILA/CYGNUS based boards
+ *
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+#ifdef CONFIG_SPL_BUILD
+static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+#endif
+
+/* MII mode defines */
+#define RMII_MODE_ENABLE 0x4D
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* UART Defines */
+#ifdef CONFIG_SPL_BUILD
+#define UART_RESET (0x1 << 1)
+#define UART_CLK_RUNNING_MASK 0x1
+#define UART_SMART_IDLE_EN (0x1 << 0x3)
+
+static void rtc32k_enable(void)
+{
+ struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+
+ /*
+ * Unlock the RTC's registers. For more details please see the
+ * RTC_SS section of the TRM. In order to unlock we need to
+ * write these specific values (keys) in this order.
+ */
+ writel(0x83e70b13, &rtc->kick0r);
+ writel(0x95a4f1e0, &rtc->kick1r);
+
+ /* Enable the RTC 32K OSC by setting bits 3 and 6. */
+ writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
+ .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
+ .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
+ .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = K4B2G1646EBIH9_RATIO,
+ .cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
+ .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+
+ .cmd1csratio = K4B2G1646EBIH9_RATIO,
+ .cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
+ .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+
+ .cmd2csratio = K4B2G1646EBIH9_RATIO,
+ .cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
+ .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
+ .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
+ .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
+ .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
+ .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
+ .zq_config = K4B2G1646EBIH9_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
+};
+#endif
+
+/*
+ * Early system init of muxing and clocks.
+ */
+void s_init(void)
+{
+ /* WDT1 is already running when the bootloader gets control
+ * Disable it to avoid "random" resets
+ */
+ writel(0xAAAA, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+ writel(0x5555, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+
+#ifdef CONFIG_SPL_BUILD
+ /* Setup the PLLs and the clocks for the peripherals */
+ pll_init();
+
+ /* Enable RTC32K clock */
+ rtc32k_enable();
+
+ /* UART softreset */
+ u32 regval;
+
+ enable_uart0_pin_mux();
+
+ regval = readl(&uart_base->uartsyscfg);
+ regval |= UART_RESET;
+ writel(regval, &uart_base->uartsyscfg);
+ while ((readl(&uart_base->uartsyssts) &
+ UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+ ;
+
+ /* Disable smart idle */
+ regval = readl(&uart_base->uartsyscfg);
+ regval |= UART_SMART_IDLE_EN;
+ writel(regval, &uart_base->uartsyscfg);
+
+ gd = &gdata;
+
+ preloader_console_init();
+
+ /* Configure board pin mux */
+ enable_board_pin_mux();
+
+ config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+#endif
+}
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+
+ gpmc_init();
+
+ return 0;
+}
+
+#if defined(CONFIG_DRIVER_TI_CPSW)
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_id = 0,
+ .phy_if = PHY_INTERFACE_MODE_RMII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int rv, ret = 0;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ writel(RMII_MODE_ENABLE, &cdev->miisel);
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ ret += rv;
+
+ return ret;
+}
+#endif
+
--- /dev/null
+/*
+ * IGEP COM AQUILA/CYGNUS boards information header
+ *
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We must be able to enable uart0, for initial output. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(mcasp0_aclkx), (MODE(4) | RXACTIVE)}, /* MMC0_CD */
+ {-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
+ {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
+ {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
+ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
+ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
+ {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
+ {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
+ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REF_CLK */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+/*
+ * Do board-specific muxes.
+ */
+void enable_board_pin_mux(void)
+{
+ /* NAND Flash */
+ configure_module_pin_mux(nand_pin_mux);
+ /* SD Card */
+ configure_module_pin_mux(mmc0_pin_mux);
+ /* Ethernet pinmux. */
+ configure_module_pin_mux(rmii1_pin_mux);
+}
+
static void twl4030_regulator_set_mode(u8 id, u8 mode)
{
u16 msg = MSG_SINGULAR(DEV_GRP_P1, id, mode);
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg >> 8,
- TWL4030_PM_MASTER_PB_WORD_MSB);
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg & 0xff,
- TWL4030_PM_MASTER_PB_WORD_LSB);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_PB_WORD_MSB, msg >> 8);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_PB_WORD_LSB, msg & 0xff);
}
static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
TWL4030_PM_RECEIVER_DEV_GRP_P1);
/* store I2C access state */
- twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &state,
- TWL4030_PM_MASTER_PB_CFG);
+ twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+ &state);
/* enable I2C access to powerbus (needed for twl4030 regulator) */
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x02,
- TWL4030_PM_MASTER_PB_CFG);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+ 0x02);
/* set VAUX3, VSIM and VMMC1 state to active - enable eMMC memory */
twl4030_regulator_set_mode(RES_VAUX3, RES_STATE_ACTIVE);
twl4030_regulator_set_mode(RES_VMMC1, RES_STATE_ACTIVE);
/* restore I2C access state */
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, state,
- TWL4030_PM_MASTER_PB_CFG);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+ state);
/* set env variable attkernaddr for relocated kernel */
sprintf(buf, "%#x", KERNEL_ADDRESS);
return;
/* read actual watchdog timeout */
- twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &timeout,
- TWL4030_PM_RECEIVER_WATCHDOG_CFG);
+ twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER,
+ TWL4030_PM_RECEIVER_WATCHDOG_CFG, &timeout);
/* timeout 0 means watchdog is disabled */
/* reset watchdog timeout to 31s (maximum) */
if (timeout != 0)
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 31,
- TWL4030_PM_RECEIVER_WATCHDOG_CFG);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+ TWL4030_PM_RECEIVER_WATCHDOG_CFG, 31);
/* store last watchdog reset time */
twl_wd_time = get_timer(0);
{
int ret = 0;
u8 ctrl;
- ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &ctrl,
- TWL4030_KEYPAD_KEYP_CTRL_REG);
+ ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_CTRL_REG, &ctrl);
if (ret)
return ret;
ctrl |= TWL4030_KEYPAD_CTRL_KBD_ON;
ctrl |= TWL4030_KEYPAD_CTRL_SOFT_NRST;
ctrl |= TWL4030_KEYPAD_CTRL_SOFTMODEN;
- ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, ctrl,
- TWL4030_KEYPAD_KEYP_CTRL_REG);
+ ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_CTRL_REG, ctrl);
/* enable key event status */
- ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0xfe,
- TWL4030_KEYPAD_KEYP_IMR1);
+ ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_IMR1, 0xfe);
/* enable interrupt generation on rising and falling */
/* this is a workaround for qemu twl4030 emulation */
- ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x57,
- TWL4030_KEYPAD_KEYP_EDR);
+ ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_EDR, 0x57);
/* enable ISR clear on read */
- ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x05,
- TWL4030_KEYPAD_KEYP_SIH_CTRL);
+ ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_SIH_CTRL, 0x05);
return 0;
}
for (i = 0; i < 2; i++) {
/* check interrupt register for events */
- twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &intr,
- TWL4030_KEYPAD_KEYP_ISR1+(2*i));
+ twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_ISR1 + (2 * i), &intr);
/* no event */
if (!(intr&1))
/* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+ TWL4030_PM_RECEIVER_BB_CFG,
TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV |
- TWL4030_BB_CFG_BBISEL_500UA, TWL4030_PM_RECEIVER_BB_CFG);
+ TWL4030_BB_CFG_BBISEL_500UA);
dieid_num_r();
/*
* Routine: get_board_revision
* Description: Detect if we are running on a Beagle revision Ax/Bx,
- * C1/2/3, C4 or xM. This can be done by reading
+ * C1/2/3, C4, xM Ax/Bx or xM Cx. This can be done by reading
* the level of GPIO173, GPIO172 and GPIO171. This should
* result in
* GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
* GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
* GPIO173, GPIO172, GPIO171: 1 0 1 => C4
- * GPIO173, GPIO172, GPIO171: 0 0 0 => xM
+ * GPIO173, GPIO172, GPIO171: 0 1 0 => xM Cx
+ * GPIO173, GPIO172, GPIO171: 0 0 0 => xM Ax/Bx
*/
static int get_board_revision(void)
{
* MA 02111-1307 USA
*/
#include <common.h>
-#include <twl6035.h>
+#include <palmas.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
* MA 02111-1307 USA
*/
#include <common.h>
-#include <twl6035.h>
+#include <palmas.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
*/
int misc_init_r(void)
{
-#ifdef CONFIG_TWL6035_POWER
- twl6035_init_settings();
+#ifdef CONFIG_PALMAS_POWER
+ palmas_init_settings();
#endif
return 0;
}
if (omap_revision() == OMAP4430_ES1_0)
return 0;
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ if (omap_revision() >= OMAP4460_ES1_0 ||
+ omap_revision() <= OMAP4460_ES1_1)
+ setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
+#endif
+
gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
*/
#include <common.h>
+#include <cpsw.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
#endif
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
/* UART Defines */
#ifdef CONFIG_SPL_BUILD
#define UART_RESET (0x1 << 1)
*/
wdt_disable();
+ /* Enable timer */
+ timer_init();
+
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* Set MMC pins */
enable_mmc1_pin_mux();
+ /* Set Ethernet pins */
+ enable_enet_pin_mux();
+
/* Enable UART */
uart_enable();
return 0;
}
#endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x50,
+ .sliver_reg_ofs = 0x700,
+ .phy_id = 1,
+ },
+ {
+ .slave_reg_ofs = 0x90,
+ .sliver_reg_ofs = 0x740,
+ .phy_id = 0,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x100,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0x600,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x28,
+ .hw_stats_reg_ofs = 0x400,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_1,
+};
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+ printf("<ethaddr> not set. Reading from E-fuse\n");
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ else
+ printf("Unable to read MAC address. Set <ethaddr>\n");
+ }
+
+ return cpsw_register(&cpsw_data);
+}
void enable_uart0_pin_mux(void);
void enable_mmc1_pin_mux(void);
+void enable_enet_pin_mux(void);
#endif /* _EVM_H */
{-1},
};
+static struct module_pin_mux enet_pin_mux[] = {
+ {OFFSET(pincntl232), MODE(0x01)}, /* EMAC_RMREFCLK */
+ {OFFSET(pincntl233), PULLUP_EN | MODE(0x01)}, /* MDCLK */
+ {OFFSET(pincntl234), PULLUP_EN | MODE(0x01)}, /* MDIO */
+ {OFFSET(pincntl235), MODE(0x01)}, /* EMAC[0]_MTCLK */
+ {OFFSET(pincntl236), MODE(0x01)}, /* EMAC[0]_MCOL */
+ {OFFSET(pincntl237), MODE(0x01)}, /* EMAC[0]_MCRS */
+ {OFFSET(pincntl238), MODE(0x01)}, /* EMAC[0]_MRXER */
+ {OFFSET(pincntl239), MODE(0x01)}, /* EMAC[0]_MRCLK */
+ {OFFSET(pincntl240), MODE(0x01)}, /* EMAC[0]_MRXD[0] */
+ {OFFSET(pincntl241), MODE(0x01)}, /* EMAC[0]_MRXD[1] */
+ {OFFSET(pincntl242), MODE(0x01)}, /* EMAC[0]_MRXD[2] */
+ {OFFSET(pincntl243), MODE(0x01)}, /* EMAC[0]_MRXD[3] */
+ {OFFSET(pincntl244), MODE(0x01)}, /* EMAC[0]_MRXD[4] */
+ {OFFSET(pincntl245), MODE(0x01)}, /* EMAC[0]_MRXD[5] */
+ {OFFSET(pincntl246), MODE(0x01)}, /* EMAC[0]_MRXD[6] */
+ {OFFSET(pincntl247), MODE(0x01)}, /* EMAC[0]_MRXD[7] */
+ {OFFSET(pincntl248), MODE(0x01)}, /* EMAC[0]_MRXDV */
+ {OFFSET(pincntl249), MODE(0x01)}, /* EMAC[0]_GMTCLK */
+ {OFFSET(pincntl250), MODE(0x01)}, /* EMAC[0]_MTXD[0] */
+ {OFFSET(pincntl251), MODE(0x01)}, /* EMAC[0]_MTXD[1] */
+ {OFFSET(pincntl252), MODE(0x01)}, /* EMAC[0]_MTXD[2] */
+ {OFFSET(pincntl253), MODE(0x01)}, /* EMAC[0]_MTXD[3] */
+ {OFFSET(pincntl254), MODE(0x01)}, /* EMAC[0]_MTXD[4] */
+ {OFFSET(pincntl255), MODE(0x01)}, /* EMAC[0]_MTXD[5] */
+ {OFFSET(pincntl256), MODE(0x01)}, /* EMAC[0]_MTXD[6] */
+ {OFFSET(pincntl257), MODE(0x01)}, /* EMAC[0]_MTXD[7] */
+ {OFFSET(pincntl258), MODE(0x01)}, /* EMAC[0]_MTXEN */
+};
+
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
{
configure_module_pin_mux(mmc1_pin_mux);
}
+
+void enable_enet_pin_mux(void)
+{
+ configure_module_pin_mux(enet_pin_mux);
+}
nitrogen6s1g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024
wandboard_dl arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
wandboard_solo arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512
-cm_t35 arm armv7 cm_t35 - omap3
omap3_overo arm armv7 overo - omap3
omap3_pandora arm armv7 pandora - omap3
dig297 arm armv7 dig297 comelit omap3
+cm_t35 arm armv7 cm_t35 compulab omap3
igep0020 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND
igep0020_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND
igep0030 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND
igep0030_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND
igep0032 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND
+igep0033 arm armv7 igep0033 isee am33xx
am3517_evm arm armv7 am3517evm logicpd omap3
mt_ventoux arm armv7 mt_ventoux teejet omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
- typedef void __noreturn (*image_entry_noargs_t)(u32 *);
+ typedef void __noreturn (*image_entry_noargs_t)(void);
+
image_entry_noargs_t image_entry =
(image_entry_noargs_t) spl_image->entry_point;
debug("image entry point: 0x%X\n", spl_image->entry_point);
- /* Pass the saved boot_params from rom code */
-#if defined(CONFIG_VIRTIO) || defined(CONFIG_ZEBU)
- image_entry = (image_entry_noargs_t)0x80100000;
-#endif
- u32 boot_params_ptr_addr = (u32)&boot_params_ptr;
- image_entry((u32 *)boot_params_ptr_addr);
+ image_entry();
}
#ifdef CONFIG_SPL_RAM_DEVICE
--- /dev/null
+README on how reset time on OMAPs should be calculated
+
+CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC:
+Most OMAPs' provide a way to specify the time for
+which the reset should be held low while the voltages
+and Oscillator outputs stabilize.
+
+This time is mostly board and PMIC dependent. Hence the
+boards are expected to specify a pre-computed time
+using the above option, (the details on how to compute
+the value are given below) without which a default time
+as specified by CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC
+is used.
+
+The value for CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
+can be computed using a summation of the below 3 parameters
+-1- Time taken by the Osciallator to stop and restart
+-2- PMIC OTP time
+-3- Voltage ramp time, which can be derived using the
+PMIC slew rate and value of voltage ramp needed.
if (ledon_mask & TWL4030_LED_LEDEN_LEDBON)
ledon_mask |= TWL4030_LED_LEDEN_LEDBPWM;
- twl4030_i2c_write_u8(TWL4030_CHIP_LED, ledon_mask,
- TWL4030_LED_LEDEN);
+ twl4030_i2c_write_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN,
+ ledon_mask);
}
#include <i2c.h>
#include <twl4030.h>
#include <twl6030.h>
-#include <twl6035.h>
+#include <palmas.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
}
#endif
-#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
+#if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
static void omap5_pbias_config(struct mmc *mmc)
{
u32 value = 0;
value |= SDCARD_BIAS_HIZ_MODE;
writel(value, (*ctrl)->control_pbias);
- twl6035_mmc1_poweron_ldo();
+ palmas_mmc1_poweron_ldo();
value = readl((*ctrl)->control_pbias);
value &= ~SDCARD_BIAS_HIZ_MODE;
if (mmc->block_dev.dev == 0)
omap4_vmmc_pbias_config(mmc);
#endif
-#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
+#if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
if (mmc->block_dev.dev == 0)
omap5_pbias_config(mmc);
#endif
u32 flow_thresh;
u32 port_vlan;
u32 tx_pri_map;
+#ifdef CONFIG_AM33XX
u32 gap_thresh;
+#elif defined(CONFIG_TI814X)
+ u32 ts_ctl;
+ u32 ts_seq_ltype;
+ u32 ts_vlan;
+#endif
u32 sa_lo;
u32 sa_hi;
};
COBJS-$(CONFIG_PHY_ATHEROS) += atheros.o
COBJS-$(CONFIG_PHY_BROADCOM) += broadcom.o
COBJS-$(CONFIG_PHY_DAVICOM) += davicom.o
+COBJS-$(CONFIG_PHY_ET1011C) += et1011c.o
COBJS-$(CONFIG_PHY_LXT) += lxt.o
COBJS-$(CONFIG_PHY_MARVELL) += marvell.o
COBJS-$(CONFIG_PHY_MICREL) += micrel.o
--- /dev/null
+/*
+ * ET1011C PHY driver
+ *
+ * Derived from Linux kernel driver by Chaithrika U S
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <config.h>
+#include <phy.h>
+
+#define ET1011C_CONFIG_REG (0x16)
+#define ET1011C_TX_FIFO_MASK (0x3 << 12)
+#define ET1011C_TX_FIFO_DEPTH_8 (0x0 << 12)
+#define ET1011C_TX_FIFO_DEPTH_16 (0x1 << 12)
+#define ET1011C_INTERFACE_MASK (0x7 << 0)
+#define ET1011C_GMII_INTERFACE (0x2 << 0)
+#define ET1011C_SYS_CLK_EN (0x1 << 4)
+#define ET1011C_TX_CLK_EN (0x1 << 5)
+
+#define ET1011C_STATUS_REG (0x1A)
+#define ET1011C_DUPLEX_STATUS (0x1 << 7)
+#define ET1011C_SPEED_MASK (0x3 << 8)
+#define ET1011C_SPEED_1000 (0x2 << 8)
+#define ET1011C_SPEED_100 (0x1 << 8)
+#define ET1011C_SPEED_10 (0x0 << 8)
+
+static int et1011c_config(struct phy_device *phydev)
+{
+ int ctl = 0;
+ ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
+ if (ctl < 0)
+ return ctl;
+ ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 |
+ BMCR_ANENABLE);
+ /* First clear the PHY */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET);
+
+ return genphy_config_aneg(phydev);
+}
+
+static int et1011c_parse_status(struct phy_device *phydev)
+{
+ int mii_reg;
+ int speed;
+
+ mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG);
+
+ if (mii_reg & ET1011C_DUPLEX_STATUS)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+
+ speed = mii_reg & ET1011C_SPEED_MASK;
+ switch (speed) {
+ case ET1011C_SPEED_1000:
+ phydev->speed = SPEED_1000;
+ mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG);
+ mii_reg &= ~ET1011C_TX_FIFO_MASK;
+ phy_write(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG,
+ mii_reg |
+ ET1011C_GMII_INTERFACE |
+ ET1011C_SYS_CLK_EN |
+#ifdef CONFIG_PHY_ET1011C_TX_CLK_FIX
+ ET1011C_TX_CLK_EN |
+#endif
+ ET1011C_TX_FIFO_DEPTH_16);
+ break;
+ case ET1011C_SPEED_100:
+ phydev->speed = SPEED_100;
+ break;
+ case ET1011C_SPEED_10:
+ phydev->speed = SPEED_10;
+ break;
+ }
+
+ return 0;
+}
+
+static int et1011c_startup(struct phy_device *phydev)
+{
+ genphy_update_link(phydev);
+ et1011c_parse_status(phydev);
+ return 0;
+}
+
+static struct phy_driver et1011c_driver = {
+ .name = "ET1011C",
+ .uid = 0x0282f014,
+ .mask = 0xfffffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &et1011c_config,
+ .startup = &et1011c_startup,
+};
+
+int phy_et1011c_init(void)
+{
+ phy_register(&et1011c_driver);
+
+ return 0;
+}
#ifdef CONFIG_PHY_DAVICOM
phy_davicom_init();
#endif
+#ifdef CONFIG_PHY_ET1011C
+ phy_et1011c_init();
+#endif
#ifdef CONFIG_PHY_LXT
phy_lxt_init();
#endif
COBJS-$(CONFIG_TPS6586X_POWER) += tps6586x.o
COBJS-$(CONFIG_TWL4030_POWER) += twl4030.o
COBJS-$(CONFIG_TWL6030_POWER) += twl6030.o
-COBJS-$(CONFIG_TWL6035_POWER) += twl6035.o
+COBJS-$(CONFIG_PALMAS_POWER) += palmas.o
COBJS-$(CONFIG_POWER) += power_core.o
COBJS-$(CONFIG_DIALOG_POWER) += power_dialog.o
/*
- * (C) Copyright 2012
+ * (C) Copyright 2012-2013
* Texas Instruments, <www.ti.com>
*
* See file CREDITS for list of people who contributed to this
* MA 02111-1307 USA
*/
#include <config.h>
-#include <twl6035.h>
+#include <palmas.h>
-/* Functions to read and write from TWL6030 */
-int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg)
-{
- return i2c_write(chip_no, reg, 1, &val, 1);
-}
-
-int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg)
-{
- return i2c_read(chip_no, reg, 1, val, 1);
-}
-
-/* To align with i2c mw/mr address, reg, val command syntax */
-static inline int palmas_write_u8(u8 chip_no, u8 reg, u8 val)
-{
- return i2c_write(chip_no, reg, 1, &val, 1);
-}
-
-static inline int palmas_read_u8(u8 chip_no, u8 reg, u8 *val)
-{
- return i2c_read(chip_no, reg, 1, val, 1);
-}
-
-void twl6035_init_settings(void)
+void palmas_init_settings(void)
{
return;
}
-int twl6035_mmc1_poweron_ldo(void)
+int palmas_mmc1_poweron_ldo(void)
{
u8 val = 0;
/* set LDO9 TWL6035 to 3V */
val = 0x2b; /* (3 -.9)*28 +1 */
- if (palmas_write_u8(0x48, LDO9_VOLTAGE, val)) {
+ if (palmas_i2c_write_u8(0x48, LDO9_VOLTAGE, val)) {
printf("twl6035: could not set LDO9 voltage.\n");
return 1;
}
/* TURN ON LDO9 */
val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
- if (palmas_write_u8(0x48, LDO9_CTRL, val)) {
+ if (palmas_i2c_write_u8(0x48, LDO9_CTRL, val)) {
printf("twl6035: could not turn on LDO9.\n");
return 1;
}
void twl4030_power_reset_init(void)
{
u8 val = 0;
- if (twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &val,
- TWL4030_PM_MASTER_P1_SW_EVENTS)) {
+ if (twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_P1_SW_EVENTS, &val)) {
printf("Error:TWL4030: failed to read the power register\n");
printf("Could not initialize hardware reset\n");
} else {
val |= TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON;
- if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, val,
- TWL4030_PM_MASTER_P1_SW_EVENTS)) {
+ if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_P1_SW_EVENTS, val)) {
printf("Error:TWL4030: failed to write the power register\n");
printf("Could not initialize hardware reset\n");
}
int ret;
/* Select the Voltage */
- ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val,
- vsel_reg);
+ ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_reg,
+ vsel_val);
if (ret != 0) {
printf("Could not write vsel to reg %02x (%d)\n",
vsel_reg, ret);
}
/* Select the Device Group (enable the supply if dev_grp_sel != 0) */
- ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel,
- dev_grp);
+ ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp,
+ dev_grp_sel);
if (ret != 0)
printf("Could not write grp_sel to reg %02x (%d)\n",
dev_grp, ret);
#include <twl6030.h>
-/* Functions to read and write from TWL6030 */
-static inline int twl6030_i2c_write_u8(u8 chip_no, u8 val, u8 reg)
-{
- return i2c_write(chip_no, reg, 1, &val, 1);
-}
-
-static inline int twl6030_i2c_read_u8(u8 chip_no, u8 *val, u8 reg)
-{
- return i2c_read(chip_no, reg, 1, val, 1);
-}
-
static int twl6030_gpadc_read_channel(u8 channel_no)
{
u8 lsb = 0;
u8 msb = 0;
int ret = 0;
- ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &lsb,
- GPCH0_LSB + channel_no * 2);
+ ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC,
+ GPCH0_LSB + channel_no * 2, &lsb);
if (ret)
return ret;
- ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &msb,
- GPCH0_MSB + channel_no * 2);
+ ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC,
+ GPCH0_MSB + channel_no * 2, &msb);
if (ret)
return ret;
u8 val;
int ret = 0;
- ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, CTRL_P2_SP2, CTRL_P2);
+ ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, CTRL_P2, CTRL_P2_SP2);
if (ret)
return ret;
val = CTRL_P2_BUSY;
while (!((val & CTRL_P2_EOCP2) && (!(val & CTRL_P2_BUSY)))) {
- ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &val, CTRL_P2);
+ ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, CTRL_P2, &val);
if (ret)
return ret;
udelay(1000);
void twl6030_stop_usb_charging(void)
{
- twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, 0, CONTROLLER_CTRL1);
+ twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CONTROLLER_CTRL1, 0);
return;
}
void twl6030_start_usb_charging(void)
{
- twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_VICHRG_1500,
- CHARGERUSB_VICHRG);
- twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CIN_LIMIT_NONE,
- CHARGERUSB_CINLIMIT);
- twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, MBAT_TEMP,
- CONTROLLER_INT_MASK);
- twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, MASK_MCHARGERUSB_THMREG,
- CHARGERUSB_INT_MASK);
- twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_VOREG_4P0,
- CHARGERUSB_VOREG);
- twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CTRL2_VITERM_400,
- CHARGERUSB_CTRL2);
- twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, TERM, CHARGERUSB_CTRL1);
+ twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
+ CHARGERUSB_VICHRG, CHARGERUSB_VICHRG_1500);
+ twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
+ CHARGERUSB_CINLIMIT, CHARGERUSB_CIN_LIMIT_NONE);
+ twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
+ CONTROLLER_INT_MASK, MBAT_TEMP);
+ twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
+ CHARGERUSB_INT_MASK, MASK_MCHARGERUSB_THMREG);
+ twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
+ CHARGERUSB_VOREG, CHARGERUSB_VOREG_4P0);
+ twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
+ CHARGERUSB_CTRL2, CHARGERUSB_CTRL2_VITERM_400);
+ twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CTRL1, TERM);
/* Enable USB charging */
- twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CONTROLLER_CTRL1_EN_CHARGER,
- CONTROLLER_CTRL1);
+ twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER,
+ CONTROLLER_CTRL1, CONTROLLER_CTRL1_EN_CHARGER);
return;
}
u8 msb = 0;
u8 lsb = 0;
- twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &msb, FG_REG_11);
- twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &lsb, FG_REG_10);
+ twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, FG_REG_11, &msb);
+ twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, FG_REG_10, &lsb);
battery_current = ((msb << 8) | lsb);
/* convert 10 bit signed number to 16 bit signed number */
int ret = 0;
/* Enable VBAT measurement */
- twl6030_i2c_write_u8(TWL6030_CHIP_PM, VBAT_MEAS, MISC1);
+ twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC1, VBAT_MEAS);
/* Enable GPADC module */
- ret = twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, FGS | GPADCS, TOGGLE1);
+ ret = twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, TOGGLE1, FGS | GPADCS);
if (ret) {
printf("Failed to enable GPADC\n");
return;
printf("Main battery voltage too low!\n");
/* Check for the presence of USB charger */
- twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &stat1, CONTROLLER_STAT1);
+ twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, CONTROLLER_STAT1, &stat1);
/* check for battery presence indirectly via Fuel gauge */
if ((stat1 & VBUS_DET) && (battery_volt < 3300))
void twl6030_power_mmc_init()
{
/* set voltage to 3.0 and turnon for APP */
- twl6030_i2c_write_u8(TWL6030_CHIP_PM, 0x15, VMMC_CFG_VOLTATE);
- twl6030_i2c_write_u8(TWL6030_CHIP_PM, 0x21, VMMC_CFG_STATE);
+ twl6030_i2c_write_u8(TWL6030_CHIP_PM, VMMC_CFG_VOLTATE, 0x15);
+ twl6030_i2c_write_u8(TWL6030_CHIP_PM, VMMC_CFG_STATE, 0x21);
}
void twl6030_usb_device_settings()
u8 data = 0;
/* Select APP Group and set state to ON */
- twl6030_i2c_write_u8(TWL6030_CHIP_PM, 0x21, VUSB_CFG_STATE);
+ twl6030_i2c_write_u8(TWL6030_CHIP_PM, VUSB_CFG_STATE, 0x21);
- twl6030_i2c_read_u8(TWL6030_CHIP_PM, &data, MISC2);
+ twl6030_i2c_read_u8(TWL6030_CHIP_PM, MISC2, &data);
data |= 0x10;
/* Select the input supply for VBUS regulator */
- twl6030_i2c_write_u8(TWL6030_CHIP_PM, data, MISC2);
+ twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC2, data);
}
#endif
{
int ret;
- ret = twl4030_i2c_write_u8(TWL4030_CHIP_USB, data, address);
+ ret = twl4030_i2c_write_u8(TWL4030_CHIP_USB, address, data);
if (ret != 0)
printf("TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
u8 data;
int ret;
- ret = twl4030_i2c_read_u8(TWL4030_CHIP_USB, &data, address);
+ ret = twl4030_i2c_read_u8(TWL4030_CHIP_USB, address, &data);
if (ret == 0)
ret = data;
else
static void twl4030_usb_ldo_init(void)
{
/* Enable writing to power configuration registers */
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0xC0,
- TWL4030_PM_MASTER_PROTECT_KEY);
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x0C,
- TWL4030_PM_MASTER_PROTECT_KEY);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_PROTECT_KEY, 0xC0);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_PROTECT_KEY, 0x0C);
/* put VUSB3V1 LDO in active state */
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00,
- TWL4030_PM_RECEIVER_VUSB_DEDICATED2);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+ TWL4030_PM_RECEIVER_VUSB_DEDICATED2, 0x00);
/* input to VUSB3V1 LDO is from VBAT, not VBUS */
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x14,
- TWL4030_PM_RECEIVER_VUSB_DEDICATED1);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+ TWL4030_PM_RECEIVER_VUSB_DEDICATED1, 0x14);
/* turn on 3.1V regulator */
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20,
- TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP);
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00,
- TWL4030_PM_RECEIVER_VUSB3V1_TYPE);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+ TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP, 0x20);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+ TWL4030_PM_RECEIVER_VUSB3V1_TYPE, 0x00);
/* turn on 1.5V regulator */
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20,
- TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP);
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00,
- TWL4030_PM_RECEIVER_VUSB1V5_TYPE);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+ TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP, 0x20);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+ TWL4030_PM_RECEIVER_VUSB1V5_TYPE, 0x00);
/* turn on 1.8V regulator */
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20,
- TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP);
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00,
- TWL4030_PM_RECEIVER_VUSB1V8_TYPE);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+ TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP, 0x20);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+ TWL4030_PM_RECEIVER_VUSB1V8_TYPE, 0x00);
/* disable access to power configuration registers */
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x00,
- TWL4030_PM_MASTER_PROTECT_KEY);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_PROTECT_KEY, 0x00);
}
static void twl4030_phy_power(void)
#define __CONFIG_AM335X_EVM_H
#define CONFIG_AM33XX
+#define CONFIG_OMAP
#include <asm/arch/omap.h>
+ (8 * 1024 * 1024))
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
-#define CONFIG_SYS_HZ 1000 /* 1ms clock */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
/* Platform/Board specific defs */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_HZ 1000 /* 1ms clock */
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000)
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ECCSTEPS 4
-#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
- CONFIG_SYS_NAND_ECCSTEPS)
-
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT "nand0=nand"
#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
- "1920k(u-boot),128k(u-boot-env),"\
+ "1920k(u-boot),256k(u-boot-env),"\
"4m(kernel),-(fs)"
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-#define CONFIG_JFFS2_NAND
-/* nand device jffs2 lives on */
-#define CONFIG_JFFS2_DEV "nand0"
-/* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_OFFSET 0x680000
-#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
- /* partition */
-
/* Environment information */
#define CONFIG_BOOTDELAY 10
#define CONFIG_ZERO_BOOTDELAY_CHECK
"defaultdisplay=dvi\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
"nandroot=/dev/mtdblock4 rw\0" \
- "nandrootfstype=jffs2\0" \
+ "nandrootfstype=ubifs\0" \
"mmcargs=setenv bootargs console=${console} " \
"mpurate=${mpurate} " \
"vram=${vram} " \
"bootm ${loadaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
- "nand read ${loadaddr} 280000 400000; " \
+ "nand read ${loadaddr} 2a0000 400000; " \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
#define CONFIG_SYS_NAND_CS 3
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_CLE_MASK 0x10
-#define CONFIG_SYS_ALE_MASK 0x8
+#define CONFIG_SYS_NAND_MASK_CLE 0x10
+#define CONFIG_SYS_NAND_MASK_ALE 0x8
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#endif
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_CS 3
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_CLE_MASK 0x10
-#define CONFIG_SYS_ALE_MASK 0x8
+#define CONFIG_SYS_NAND_MASK_CLE 0x10
+#define CONFIG_SYS_NAND_MASK_ALE 0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_CS 3
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_CLE_MASK 0x10
-#define CONFIG_SYS_ALE_MASK 0x8
+#define CONFIG_SYS_NAND_MASK_CLE 0x10
+#define CONFIG_SYS_NAND_MASK_ALE 0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
--- /dev/null
+/*
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_IGEP0033_H
+#define __CONFIG_IGEP0033_H
+
+#define CONFIG_AM33XX
+#define CONFIG_OMAP
+
+#include <asm/arch/omap.h>
+
+/* Mach type */
+#define MACH_TYPE_IGEP0033 4521 /* Until the next sync */
+#define CONFIG_MACH_TYPE MACH_TYPE_IGEP0033
+
+/* Clock defines */
+#define V_OSCK 24000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+/* DMA defines */
+#define CONFIG_DMA_COHERENT
+#define CONFIG_DMA_COHERENT_SIZE (1 << 20)
+
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT "U-Boot# "
+#define CONFIG_SYS_NO_FLASH
+
+/* Display cpuinfo */
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+/*
+ * Because the issues explained in doc/README.memory-test, the "mtest command
+ * is considered deprecated. It should not be enabled in most normal ports of
+ * U-Boot.
+ */
+#undef CONFIG_CMD_MEMTEST
+
+#define CONFIG_BOOTDELAY 1 /* negative for no autoboot */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x80200000\0" \
+ "rdaddr=0x81000000\0" \
+ "bootfile=/boot/uImage\0" \
+ "console=ttyO0,115200n8\0" \
+ "optargs=\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
+ "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+ "ramrootfstype=ext2\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "bootenv=uEnv.txt\0" \
+ "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "ramargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${ramroot} " \
+ "rootfstype=${ramrootfstype}\0" \
+ "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+ "loaduimagefat=load mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+ "loaduimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "ramboot=echo Booting from ramdisk ...; " \
+ "run ramargs; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loaduimage; then " \
+ "run mmcboot;" \
+ "fi;" \
+ "fi;" \
+
+/* Max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
+#define CONFIG_SYS_HZ 1000 /* 1ms clock */
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
+#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
+ GENERATED_GBL_DATA_SIZE)
+/* Platform/Board specific defs */
+#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK (48000000)
+#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
+
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* MMC support */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* GPIO support */
+#define CONFIG_OMAP_GPIO
+
+/* Ethernet support */
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR 0
+#define CONFIG_PHY_SMSC
+
+/* NAND support */
+#define CONFIG_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
+#define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_ONFI_DETECTION 1
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
+
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+#define MTDIDS_DEFAULT "nand0=nand"
+#define MTDPARTS_DEFAULT "mtdparts=nand:512k(SPL),"\
+ "1m(U-Boot),128k(U-Boot Env),"\
+ "5m(Kernel),-(File System)"
+
+/* Unsupported features */
+#undef CONFIG_USE_IRQ
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x402F0400
+#define CONFIG_SPL_MAX_SIZE (101 * 1024)
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+
+#define CONFIG_SYS_NAND_ECCSTEPS 4
+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
+ CONFIG_SYS_NAND_ECCSTEPS)
+
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x80800000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#endif /* ! __CONFIG_IGEP0033_H */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
+
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
/* I2C */
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
"if test $board_name = sdp4430; then " \
"setenv fdtfile omap4-sdp.dtb; fi; " \
"if test $board_name = panda; then " \
- "setenv fdtfile omap4-panda-es.dtb; fi\0" \
+ "setenv fdtfile omap4-panda.dtb; fi;" \
+ "if test $board_name = panda-es; then " \
+ "setenv fdtfile omap4-panda-es.dtb; fi; \0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
#define CONFIG_BOOTCOMMAND \
#define CONFIG_SYS_PROMPT "Panda # "
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
#endif /* __CONFIG_PANDA_H */
#define CONFIG_BAUDRATE 115200
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
/* I2C */
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
"usbtty=cdc_acm\0" \
"vram=16M\0" \
"partitions=" PARTS_DEFAULT "\0" \
+ "optargs=\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext4 rootwait\0" \
"mmcargs=setenv bootargs console=${console} " \
+ "${optargs} " \
"vram=${vram} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
/* TWL6035 */
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_TWL6035_POWER
+#define CONFIG_PALMAS_POWER
#endif
/* MMC ENV related defines */
#define CONFIG_SYS_PROMPT "OMAP5430 EVM # "
+#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296
#endif /* __CONFIG_OMAP5_EVM_H */
#define __CONFIG_PCM051_H
#define CONFIG_AM33XX
+#define CONFIG_OMAP
#include <asm/arch/omap.h>
+ (8 * 1024 * 1024))
#define CONFIG_SYS_LOAD_ADDR 0x80007fc0 /* Default load address */
-#define CONFIG_SYS_HZ 1000 /* 1ms clock */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
/* Platform/Board specific defs */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_HZ 1000 /* 1ms clock */
#define CONFIG_CONS_INDEX 1
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000)
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_TI81XX
#define CONFIG_TI814X
#define CONFIG_SYS_NO_FLASH
+#define CONFIG_OMAP
#include <asm/arch/omap.h>
#define CONFIG_BAUDRATE 115200
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* Unsupported features */
#undef CONFIG_USE_IRQ
+/* Ethernet */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR 1
+#define CONFIG_PHY_ET1011C
+#define CONFIG_PHY_ET1011C_TX_CLK_FIX
+
#endif /* ! __CONFIG_TI814X_EVM_H */
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BASE TNETV107X_ASYNC_EMIF_DATA_CE0_BASE
-#define CONFIG_SYS_CLE_MASK 0x10
-#define CONFIG_SYS_ALE_MASK 0x8
+#define CONFIG_SYS_NAND_MASK_CLE 0x10
+#define CONFIG_SYS_NAND_MASK_ALE 0x8
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
/*
- * (C) Copyright 2012
+ * (C) Copyright 2012-2013
* Texas Instruments, <www.ti.com>
*
* See file CREDITS for list of people who contributed to this
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+#ifndef PALMAS_H
+#define PALMAS_H
#include <common.h>
#include <i2c.h>
/* I2C chip addresses */
-#define TWL6035_CHIP_ADDR 0x48
+#define PALMAS_CHIP_ADDR 0x48
/* 0x1XY translates to page 1, register address 0xXY */
#define LDO9_CTRL 0x60
#define LDO_MODE_SLEEP (1 << 2)
#define LDO_MODE_ACTIVE (1 << 0)
-int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg);
-int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg);
-void twl6035_init_settings(void);
-int twl6035_mmc1_poweron_ldo(void);
+/*
+ * Functions to read and write from TPS659038/TWL6035/TWL6037
+ * or other Palmas family of TI PMICs
+ */
+static inline int palmas_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
+{
+ return i2c_write(chip_no, reg, 1, &val, 1);
+}
+
+static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
+{
+ return i2c_read(chip_no, reg, 1, val, 1);
+}
+
+void palmas_init_settings(void);
+int palmas_mmc1_poweron_ldo(void);
+
+#endif /* PALMAS_H */
int phy_atheros_init(void);
int phy_broadcom_init(void);
int phy_davicom_init(void);
+int phy_et1011c_init(void);
int phy_lxt_init(void);
int phy_marvell_init(void);
int phy_micrel_init(void);
#define SPL_COPY_PAYLOAD_ONLY 1
extern struct spl_image_info spl_image;
-extern u32 *boot_params_ptr;
/* SPL common functions */
void preloader_console_init(void);
* examples are TWL4030_PM_RECEIVER_VMMC1_DEV_GRP and
* TWL4030_LED_LEDEN.
*/
-static inline int twl4030_i2c_write_u8(u8 chip_no, u8 val, u8 reg)
+static inline int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
{
return i2c_write(chip_no, reg, 1, &val, 1);
}
-static inline int twl4030_i2c_read_u8(u8 chip_no, u8 *val, u8 reg)
+static inline int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
{
return i2c_read(chip_no, reg, 1, val, 1);
}
* MA 02111-1307 USA
*/
+#ifndef TWL6030_H
+#define TWL6030_H
+
#include <common.h>
#include <i2c.h>
#define GPCH0_LSB 0x57
#define GPCH0_MSB 0x58
+/* Functions to read and write from TWL6030 */
+static inline int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
+{
+ return i2c_write(chip_no, reg, 1, &val, 1);
+}
+
+static inline int twl6030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
+{
+ return i2c_read(chip_no, reg, 1, val, 1);
+}
+
void twl6030_init_battery_charging(void);
void twl6030_usb_device_settings(void);
void twl6030_start_usb_charging(void);
int twl6030_get_battery_voltage(void);
int twl6030_get_battery_current(void);
void twl6030_power_mmc_init(void);
+
+#endif /* TWL6030_H */
projects / karo-tx-uboot.git / commitdiff