]> git.kernelconcepts.de Git - karo-tx-uboot.git/commitdiff
OMAP3+: reset: Create a common reset layer.
authorSRICHARAN R <r.sricharan@ti.com>
Mon, 12 Mar 2012 19:49:32 +0000 (19:49 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Tue, 15 May 2012 06:31:25 +0000 (08:31 +0200)
The reset.S has the function to do a warm reset on OMAP
based socs. Moving this to a reset.c file so that this
acts a common layer to add any reset related functionality
for the future.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
arch/arm/cpu/armv7/omap-common/reset.c [moved from arch/arm/cpu/armv7/omap-common/reset.S with 70% similarity]
arch/arm/include/asm/arch-omap3/cpu.h
arch/arm/include/asm/arch-omap4/cpu.h
arch/arm/include/asm/arch-omap4/omap.h
arch/arm/include/asm/arch-omap5/cpu.h
arch/arm/include/asm/arch-omap5/omap.h

similarity index 70%
rename from arch/arm/cpu/armv7/omap-common/reset.S
rename to arch/arm/cpu/armv7/omap-common/reset.c
index 838b1221ee274761b0bca7c8c9af8a999c46e1c3..234e90a86831445d2dfb7e297cfd3c25d3cdca8e 100644 (file)
@@ -1,6 +1,11 @@
 /*
- * Copyright (c) 2009 Samsung Electronics.
- * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * Common layer for reset related functionality of OMAP based socs.
+ *
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-
 #include <config.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <linux/compiler.h>
 
-.global reset_cpu
-reset_cpu:
-       ldr     r1, rstctl                      @ get addr for global reset
-                                               @ reg
-       ldr     r3, rstbit                      @ sw reset bit
-       str     r3, [r1]                        @ force reset
-       mov     r0, r0
-_loop_forever:
-       b       _loop_forever
-rstctl:
-       .word   PRM_RSTCTRL
-rstbit:
-       .word   PRM_RSTCTRL_RESET
+void __weak reset_cpu(unsigned long ignored)
+{
+       writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
+}
index 84308e04b352b48e519c57ff47a1cdb1f535eed1..457f99d2c5056bc1408a93670b840d5344a43933 100644 (file)
@@ -474,12 +474,11 @@ struct prm {
        u8 res3[0x1c];
        u32 clksrc_ctrl;        /* 0x1270 */
 };
-#else /* __ASSEMBLY__ */
-#define PRM_RSTCTRL            0x48307250
-#define PRM_RSTCTRL_RESET      0x04
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 
+#define PRM_RSTCTRL            0x48307250
+#define PRM_RSTCTRL_RESET      0x04
 #define SYSCLKDIV_1            (0x1 << 6)
 #define SYSCLKDIV_2            (0x1 << 7)
 
index 08b9c993531bb38983121ba7414c479b3ec15b3f..feddb7de5141d8b7e21fc1a37095299a88df0e32 100644 (file)
@@ -168,4 +168,15 @@ struct watchdog {
 #define OMAP_GPIO_CLEARDATAOUT         0x0190
 #define OMAP_GPIO_SETDATAOUT           0x0194
 
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE               0x4A306000
+#define PRM_DEVICE_BASE                (PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL            PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET      0x01
+
 #endif /* _CPU_H */
index 3a39787298b9456473af61176d9c8f7289bd899b..47c5883025ce818b8865e92d9c577edb8a85d3fa 100644 (file)
 #define TCLR_AR                        (0x1 << 1)
 #define TCLR_PRE               (0x1 << 5)
 
-/*
- * PRCM
- */
-
-/* PRM */
-#define PRM_BASE               0x4A306000
-#define PRM_DEVICE_BASE                (PRM_BASE + 0x1B00)
-
-#define PRM_RSTCTRL            PRM_DEVICE_BASE
-#define PRM_RSTCTRL_RESET      0x01
-
 /* Control Module */
 #define LDOSRAM_ACTMODE_VSET_IN_MASK   (0x1F << 5)
 #define LDOSRAM_VOLT_CTRL_OVERRIDE     0x0401040f
index 0697a732de44ae043177cdf73e6981b8c7af3e5c..8ef17c9a146aab0368f914b133621445c0accd66 100644 (file)
@@ -172,4 +172,15 @@ struct watchdog {
 #define OMAP_GPIO_CLEARDATAOUT         0x0190
 #define OMAP_GPIO_SETDATAOUT           0x0194
 
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE               0x4AE06000
+#define PRM_DEVICE_BASE                (PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL            PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET      0x01
+
 #endif /* _CPU_H */
index d672b6f9d9fc2207fd01b74c35cbf629573ad90c..e3f55d20201316a19f850adb858379daf772cdf3 100644 (file)
 #define TCLR_AR                        (0x1 << 1)
 #define TCLR_PRE               (0x1 << 5)
 
-/*
- * PRCM
- */
-
-/* PRM */
-#define PRM_BASE               0x4AE06000
-#define PRM_DEVICE_BASE                (PRM_BASE + 0x1B00)
-
-#define PRM_RSTCTRL            PRM_DEVICE_BASE
-#define PRM_RSTCTRL_RESET      0x01
-
 /* Control Module */
 #define LDOSRAM_ACTMODE_VSET_IN_MASK   (0x1F << 5)
 #define LDOSRAM_VOLT_CTRL_OVERRIDE     0x0401040f