powerpc/mpc85xx:Fix Core cluster configuration loop

Different personalities/derivatives of SoC may have reduced cluster. But it is
not necessary for last valid DCFG_CCSR_TP_CLUSTER register to have
DCFG_CCSR_TP_CLUSTER[EOC] bit set to represent "End of Clusters".

EOC bit can still be set in last DCFG_CCSR_TP_CLUSTER register of orignal SoC
which may not be valid for the personality.
So add initiator type check to find valid cluster.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index d1155e81263e8d948144cb1d84a3098e3c41f161..cc0930002cf17c772e6b37abe96216fe0c9dd187 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -312,19 +312,33 @@ int enable_cluster_l2(void)
 
        /* Look through the remaining clusters, and set up their caches */
        do {
 
        /* Look through the remaining clusters, and set up their caches */
        do {

+               int j, cluster_valid = 0;
+

                l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
                l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);

+

                cluster = in_be32(&gur->tp_cluster[i].lower);
 
                cluster = in_be32(&gur->tp_cluster[i].lower);
 

-               /* set stash ID to (cluster) * 2 + 32 + 1 */
-               clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
+               /* check that at least one core/accel is enabled in cluster */
+               for (j = 0; j < 4; j++) {
+                       u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
+                       u32 type = in_be32(&gur->tp_ityp[idx]);

 
 

-               printf("enable l2 for cluster %d %p\n", i, l2cache);
+                       if (type & TP_ITYP_AV)
+                               cluster_valid = 1;
+               }

 
 

-               out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
-               while ((in_be32(&l2cache->l2csr0) &
-                       (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
-                       ;
-               out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+               if (cluster_valid) {
+                       /* set stash ID to (cluster) * 2 + 32 + 1 */
+                       clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
+
+                       printf("enable l2 for cluster %d %p\n", i, l2cache);
+
+                       out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
+                       while ((in_be32(&l2cache->l2csr0)
+                               & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
+                                       ;
+                       out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+               }

                i++;
        } while (!(cluster & TP_CLUSTER_EOC));
 
                i++;
        } while (!(cluster & TP_CLUSTER_EOC));