+commit f9476902b789b0481b9df49af88d6ca94fb16fa0
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Dec 15 12:10:47 2009 -0600
+
+ mpc85xx, mpc86xx: Fix gd->cpu pointer after relocation
+
+ The gd->cpu pointer is set to an address located in flash when the
+ probecpu() function is called while U-Boot is executing from flash.
+ This pointer needs to be updated to point to an address in RAM after
+ relocation has occurred otherwise Linux may not be able to boot due to
+ "fdt board" crashing if flash has been erased or changed.
+
+ This bug was introduced in commit
+ a0e2066f392782730f0398095e583c87812d97f2.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Reported-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+ Tested-by: Kumar Gala <galak@kernel.crashing.org>
+ Tested on MPC8527DS.
+ Tested by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit 3363a34b9eeda9783afcbbed5cdd738926d1f4bf
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Sun Dec 13 17:58:34 2009 -0600
+
+ MVBLUE: Remove CONFIG_CMD_IRQ
+
+ Neither the MVBLUE nor its underlying architecture implement the
+ do_irqinfo() function which is required when CONFIG_CMD_IRQ is defined.
+ This change fixes the following MVBLUE compiler error:
+
+ -> ./MAKEALL MVBLUE
+ Configuring for MVBLUE board...
+ common/libcommon.a(cmd_irq.o):(.u_boot_cmd+0x24): undefined reference to `do_irqinfo'
+ make: *** [u-boot] Error 1
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
+
+commit 18e8ad60ee87431c01cc2686985b60cc54f5dd3b
+Author: Detlev Zundel <dzu@denx.de>
+Date: Mon Dec 14 17:54:40 2009 +0100
+
+ imx27lite: Reenable MTD support on NOR flash.
+
+ The support for this was silently dropped by a configuration
+ split during the merge of the imx27lite board support in commit
+ 864aa034f3a0e10ce710e8bbda171df3cab59414 (cmd_mtdparts: Move to common
+ handling of FLASH devices via MTD layer).
+
+ Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit f4cfe42758192d09f8375e384cc000aa70d97029
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Dec 9 09:01:43 2009 +0100
+
+ nand: Fix access to last block in NAND devices
+
+ Currently, the last block of NAND devices can't be accessed. This patch
+ fixes this issue by correcting the boundary checking (off-by-one error).
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Scott Wood <scottwood@freescale.com>
+ Cc: Wolfgang Denk <wd@denx.de>
+
+commit 3b887ca8ce72cc12129183538f6e828db13f4867
+Author: Peter Korsgaard <jacmet@sunsite.dk>
+Date: Tue Dec 8 22:20:34 2009 +0100
+
+ mpc83xx: boot time regression, move LCRR setup back to cpu_init_f
+
+ Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR,
+ and LCRR bitfields) moved the LCRR assignment to after relocation
+ to RAM because of the potential problem with changing the local bus
+ clock while executing from flash.
+
+ This change unfortunately adversely affects the boot time, as running
+ all code up to cpu_init_r can cause significant slowdown.
+
+ E.G. on a 8347 board a bootup time increase of ~600ms has been observed:
+
+ 0.020 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
+ 0.168 RS: 232
+ 0.172 I2C: ready
+ 0.176 DRAM: 64 MB
+ 1.236 FLASH: 32 MB
+
+ Versus:
+
+ 0.016 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
+ 0.092 RS: 232
+ 0.092 I2C: ready
+ 0.096 DRAM: 64 MB
+ 0.644 FLASH: 32 MB
+
+ So far no boards have needed the late LCRR setup, so simply revert it
+ for now - If it is needed at a later time, those boards can either do
+ their own final LCRR setup in board code (E.G. in board_early_init_r),
+ or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do
+ the setup in cpu_init_r.
+
+ Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 386118a896554b13f14ad0f82356276988f7de82
+Author: Michal Simek <monstr@monstr.eu>
+Date: Tue Dec 8 09:12:49 2009 +0100
+
+ microblaze: Correct ffs regression for Microblaze
+
+ We are using generic implementation of ffs. This should
+ be part of Simon's commit 0413cfecea350000eab5e591a0965c3e3ee0ff00
+
+ Here is warning message which this patch removes.
+
+ In file included from /tmp/u-boot-microblaze/include/common.h:38,
+ from cmd_mtdparts.c:87:
+ /tmp/u-boot-microblaze/include/linux/bitops.h:123:1: warning: "ffs" redefined
+ In file included from /tmp/u-boot-microblaze/include/linux/bitops.h:110,
+ from /tmp/u-boot-microblaze/include/common.h:38,
+ from cmd_mtdparts.c:87:
+ /tmp/u-boot-microblaze/include/asm/bitops.h:269:1:
+ warning: this is the location of the previous definition
+
+ Signed-off-by: Michal Simek <monstr@monstr.eu>
+
+commit 8fe7b29f9811322931f0192a56431edcf819d6b9
+Author: Graeme Smecher <graeme.smecher@mail.mcgill.ca>
+Date: Mon Dec 7 08:09:57 2009 -0800
+
+ microblaze: Stop stack clobbering in microblaze-generic.
+
+ A typo caused the stack and malloc regions to overlap, which prevented
+ mem_malloc_init() from returning. This commit makes the memory layout match
+ the example described in include/configs/microblaze-generic.h
+
+ Signed-off-by: Graeme Smecher <graeme.smecher@mail.mcgill.ca>
+ Signed-off-by: Michal Simek <monstr@monstr.eu>
+
+commit 0fc52948bda0734431cb528ee4fd82f1dec8c7b5
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Dec 7 23:14:13 2009 +0100
+
+ Update CHANGELOG, prepare -rc2
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit f2352877cb2daac88115192fb09991a2397d0b27
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Sun Dec 6 23:58:28 2009 -0600
+
+ MAKEALL: Fix return value
+
+ Previously MAKEALL would always return a value of 0, even if 1 or more
+ boards did not compile. This change causes MAKEALL to return 0 if all
+ boards were able to build, otherwise 1.
+
+ This change also requires changing the script interpreter from sh to
+ bash to support bash's PIPESTATUS variable.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit fbc1c8f6f6c972524197829c56dd8f2f5da0200a
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Sun Dec 6 01:33:24 2009 -0600
+
+ tools/mkimage: Remove duplicate line of code
+
+ Recent commits 1a99de2cb4d08eb3bf9fb3f60a9d533150de8c0e and
+ 6a590c5f5fd12cdd27f3153522acfac3854590e7 both fixed the same bug in the
+ same manner. Unfortunately git was "smart" enough to merge both changes
+ which resulted in some duplicate code.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+ Reordered code and comment a bit.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit df002fa6b9cd475909ede35bf95b803c2289c6a4
+Author: Heiko Schocher <hs@denx.de>
+Date: Sat Dec 5 11:59:51 2009 +0100
+
+ i2c: fix dangling comment in do_i2c_mw()
+
+ commit bd3784df94bfeca43fbf34094df9cb1bd3ecca3b deleted some unused
+ code in do_i2c_mw(), but missed to also remove the respective
+ commment. This patch fixes this.
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit f8450829f921cf10667af98a8d08edfa3d998f04
+Author: Heiko Schocher <hs@denx.de>
+Date: Tue Dec 1 19:30:47 2009 +0100
+
+ 52xx, manroland: add fdt_fixup_memory() in ft_board_setup()
+
+ To update the real memory size in the memory node on the
+ uc101 and mucmc52 boards call fdt_fixup_memory() in
+ ft_board_setup().
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 0ec81db20294efdad2454a753e79f1fe244a43ca
+Author: Daniel Hobi <daniel.hobi@schmid-telecom.ch>
+Date: Tue Dec 1 14:05:55 2009 +0100
+
+ Fix computation in nand_util.c:get_len_incl_bad
+
+ Depending on offset, flash size and the number of bad blocks,
+ get_len_incl_bad may return a too small value which may lead to:
+
+ 1) If there are no bad blocks, nand_{read,write}_skip_bad chooses the
+ bad block aware read/write code. This may hurt performance, but does
+ not have any adverse effects.
+
+ 2) If there are bad blocks, the nand_{read,write}_skip_bad may choose
+ the bad block unaware read/write code (if len_incl_bad == *length)
+ which leads to corrupted data.
+
+ Signed-off-by: Daniel Hobi <daniel.hobi@schmid-telecom.ch>
+
+commit aabb8cb0818e285aeed0cfaf243635997e07554d
+Author: Evan Samanas <esamanas@xes-inc.com>
+Date: Mon Nov 9 20:08:36 2009 -0600
+
+ nfs: NfsTimeout() updates
+
+ - NfsTimeout() does not correctly update the NFS timeout value which
+ results in NfsTimeout() only being called once in certain situations.
+ This can result in the 'nfs' command hanging indefinetly. For
+ example, the command:
+
+ nfs 192.168.0.1:/home/user/file
+
+ will not exit until ctrl-c is pressed if 192.168.0.1 does not have an
+ NFS server running.
+
+ This issue is resolved by reinitializting the NFS timeout value inside
+ NfsTimeout() when a timeout occurs.
+
+ - Make the 'nfs' command print the 'T' character when a timeout occurs.
+ Previously there was no indication that timeouts were occuring.
+
+ - Mimic the 'tftpboot' command and when a download fails print "Retry
+ count exceeded; starting again", and restart the download taking the
+ 'netretry' environment variable into account.
+
+ Signed-off-by: Evan Samanas <esamanas@xes-inc.com>
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+ Tested on TQM8xxL.
+
+ Tested by: Wolfgang Denk <wd@denx.de>
+
+ Tested on MPC8527DS.
+
+ Tested by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit 224c90d1060bf1a83cbf33ca51d060b9d19e0294
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Wed Nov 18 19:08:59 2009 -0600
+
+ bootm: Fix help message's sub-command ordering
+
+ The help message for the 'bootm' command listed the 'cmdline' and 'bdt'
+ sub-commands in the wrong order which resulted in the error below when
+ following the 'help' command's instructions:
+
+ "Trying to execute a command out of order"
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit a93c92cddaedd5f0720e0da15c6664f7a688b582
+Author: Robert P. J. Day <rpjday@crashcourse.ca>
+Date: Tue Nov 17 07:30:23 2009 -0500
+
+ help: Correct syntax of nandecc help output.
+
+ "nandecc" help output should not reproduce the command name, nor have
+ a trailing newline.
+
+ Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
+
+commit c2fff331a32ceca837d76eb7827d6340da270d52
+Author: Mike Rapoport <mike@compulab.co.il>
+Date: Wed Nov 11 10:03:03 2009 +0200
+
+ smc911x: update SMC911X related configuration description
+
+ Since commit 736fead8fdbf8a8407048bebc373cd551d01ec98 "Convert SMC911X
+ Ethernet driver to CONFIG_NET_MULTI API" SMC911X configration options
+ are called CONFIG_SMC911X rather than CONFIG_DRIVER_SMC911X. Update
+ README to reflect that change.
+
+ Signed-off-by: Mike Rapoport <mike@compulab.co.il>
+
+commit 45b6b65c6bf06a589ef3123192af94b0381db27b
+Author: Mike Rapoport <mike@compulab.co.il>
+Date: Wed Nov 11 10:03:09 2009 +0200
+
+ smc911x: fix typo in smc911x_handle_mac_address name
+
+ Signed-off-by: Mike Rapoport <mike@compulab.co.il>
+
+commit f64ef9bb995687e24e0b61b52316f4eaa97c3bbc
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Thu Nov 19 02:47:28 2009 -0600
+
+ fix nfs symlink name corruption
+
+ An off by one error may cause nfs readlink lookup fail if
+ nfs_path_buff has non-zero data from a previous use.
+
+ Loading: *** ERROR: File lookup fail
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit e8fac25e83426fdf461c66aa8a2530ec28ec536e
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Dec 7 21:06:40 2009 +0100
+
+ at91sam9261ek.c: fix minor coding style issue.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 4713010adf5beda87410d637ebfc58db0db9a9db
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Dec 6 01:21:28 2009 +0100
+
+ trab: fix warning: implicit declaration of function 'disable_vfd'
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit a9f99ab44b473fb394169ba365f8b4380f981584
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Dec 6 00:53:18 2009 +0100
+
+ zlib.c: avoid build conflicts for cradle board
+
+ Commit dce3d79710 updated the zlib code to v0.95; this caused
+ conflicts when building for the "cradle" board, because the (pretty
+ generic) preprocessor variable "OFF" was used in multiple files.
+ Make sure to avoid further conflicts by #undef'ing it in zlib.c
+ before redefining it.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ cc: Giuseppe Condorelli <giuseppe.condorelli@st.com>
+ cc: Angelo Castello <angelo.castello@st.com>
+ cc: Alessandro Rubini <rubini-list@gnudd.com>
+
+commit 8cbf4e4f17121d732e78764f0ba317c9a1838ea6
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Dec 6 00:26:19 2009 +0100
+
+ Fix out-of-tree building of "apollon" board.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit f68ab43de67f59925542efb6bcec30f4a84fe695
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Fri Dec 4 05:35:15 2009 -0500
+
+ lzma: ignore unset filesizes
+
+ The Linux kernel build system changed how it compresses things with LZMA
+ such that the header no longer contains the filesize (it is instead set to
+ all F's). So if we get a LZMA image that has -1 for the 64bit field,
+ let's just assume that the decompressed size is unknown and continue on.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit cccfc2ab77877dbdd2abe26b28d4c1f467feb0c0
+Author: Detlev Zundel <dzu@denx.de>
+Date: Tue Dec 1 17:16:19 2009 +0100
+
+ README: Rearrange paragraphs to regain linear arrangement.
+
+ Two later additions to the Configuration Option section unfortunately
+ split the description of Show boot progress and the list of its call outs.
+
+ Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit c81296c16fd9d12422c9968cc0f1d9bf440a7d88
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Nov 24 16:42:10 2009 -0600
+
+ tools/mkimage: Print FIT image contents after creation
+
+ Previously, there was no indication to the user that a FIT image was
+ successfully created after executing mkimage. For example:
+
+ $ mkimage -f uImage.its uImage.itb
+ DTC: dts->dtb on file "uImage.its"
+
+ Adding some additional output after creating a FIT image lets the user
+ know exactly what is contained in their image, eg:
+
+ $ mkimage -f uImage.its uImage.itb
+ DTC: dts->dtb on file "uImage.its"
+ FIT description: Linux kernel 2.6.32-rc7-00201-g7550d6f-dirty
+ Created: Tue Nov 24 15:43:01 2009
+ Image 0 (kernel@1)
+ Description: Linux Kernel 2.6.32-rc7-00201-g7550d6f-dirty
+ Type: Kernel Image
+ Compression: gzip compressed
+ Data Size: 2707311 Bytes = 2643.86 kB = 2.58 MB
+ Architecture: PowerPC
+ OS: Linux
+ Load Address: 0x00000000
+ Entry Point: 0x00000000
+ Hash algo: crc32
+ Hash value: efe0798b
+ Hash algo: sha1
+ Hash value: ecafba8c95684f2c8fec67e33c41ec88df1534d7
+ Image 1 (fdt@1)
+ Description: Flattened Device Tree blob
+ Type: Flat Device Tree
+ Compression: uncompressed
+ Data Size: 12288 Bytes = 12.00 kB = 0.01 MB
+ Architecture: PowerPC
+ Hash algo: crc32
+ Hash value: a5cab676
+ Hash algo: sha1
+ Hash value: 168722b13e305283cfd6603dfe8248cc329adea6
+ Default Configuration: 'config@1'
+ Configuration 0 (config@1)
+ Description: Default Linux kernel
+ Kernel: kernel@1
+ FDT: fdt@1
+
+ This brings the behavior of creating a FIT image in line with creating a
+ standard uImage, which also prints out the uImage contents after
+ creation.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 8e1c89663cc8796b85588910046e03b388a7597c
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Nov 24 16:42:09 2009 -0600
+
+ tools/fit_image.c: Remove unused fit_set_header()
+
+ The FIT fit_set_header() function was copied from the standard uImage's
+ image_set_header() function during mkimage reorganization. However, the
+ fit_set_header() function is not used since FIT images use a standard
+ device tree blob header.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 1a99de2cb4d08eb3bf9fb3f60a9d533150de8c0e
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Nov 24 16:42:08 2009 -0600
+
+ tools/mkimage: Assume FDT image type for FIT images
+
+ When building a Flattened Image Tree (FIT) the image type needs to be
+ "flat_dt". Commit 89a4d6b12fd6394898b8a454cbabeaf1cd59bae5 introduced a
+ regression which caused the user to need to specify the "-T flat_dt"
+ parameter on the command line when building a FIT image. The "-T
+ flat_dt" parameter should not be needed and is at odds with the current
+ FIT image documentation.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 270737acca21f3939f814de5dcf350a1c3d80d83
+Author: Michael Brandt <Michael.Brandt@emsyso.de>
+Date: Sun Nov 22 14:13:27 2009 +0100
+
+ EXT2FS: fix inode size for ext2fs rev#0
+
+ extfs.c assumes that there is always a valid inode_size field in the
+ superblock. But this is not true for ext2fs rev 0. Such ext2fs images
+ are for instance generated by genext2fs. Symptoms on ARM machines are
+ messages like: "raise: Signal # 8 caught"; on PowerPC "ext2ls" will
+ print nothing.
+ This fix checks for rev 0 and uses then 128 bytes as inode size.
+
+ Signed-off-by: Michael Brandt <Michael.Brandt@emsyso.de>
+ Tested on: TQM5200S
+ Tested-by: Wolfgang Denk <wd@denx.de>
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit bcb324d68f7955c1136dafc944eb55db8ebaa601
+Author: Robert P. J. Day <rpjday@crashcourse.ca>
+Date: Thu Nov 19 11:00:28 2009 -0500
+
+ Remove superfluous preprocessor tests from some cmd_*.c files.
+
+ A small number of common/cmd_*.c files contain preprocessor tests that
+ are apparently superfluous since those same tests are used in the
+ Makefile to control the compilation of those files. Those tests are
+ clearly redundant as long as they surround the entirety of the source
+ in those files.
+
+ Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
+
+commit ad53226156fa64b6d04c0d1d6e91e09979cbea15
+Author: Robert P. J. Day <rpjday@crashcourse.ca>
+Date: Tue Nov 17 01:59:29 2009 -0500
+
+ README: Update the list of directories.
+
+ Bring the directory listing more into line with current content.
+
+ Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
+
+commit bd3784df94bfeca43fbf34094df9cb1bd3ecca3b
+Author: Pratap Chandu <pratap.rrke@gmail.com>
+Date: Thu Nov 12 19:28:25 2009 +0530
+
+ Removes dead code in the file common/cmd_i2c.c
+
+ There is some dead code enclosed by #if 0 .... #endif in the file
+ common/cmd_i2c.c
+ This patch removes the dead code.
+
+ Signed-off-by: Pratap Chandu <pratap.rrke@gmail.com>
+
+commit 64a480601a5614b441de692ae15a62c51e0bb381
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Nov 11 17:51:56 2009 -0500
+
+ smc91111_eeprom: drop CONFIG stub protection
+
+ Since the Makefile now controls the compilation of this, there is no need
+ for CONFIG checking nor the stub function.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit f3a7bddc06c927c36a1a99a97131299479ef207a
+Author: Magnus Lilja <lilja.magnus@gmail.com>
+Date: Wed Nov 11 19:56:58 2009 +0100
+
+ RTC: Fix return code in MC13783 RTC driver.
+
+ Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
+
+commit d52e3e0176a74c30549251e16c5c00a363c544d2
+Author: Magnus Lilja <lilja.magnus@gmail.com>
+Date: Wed Nov 11 19:56:36 2009 +0100
+
+ cmd_date: Fix spelling in error message.
+
+ Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
+
+commit c253122395753abb9e531d8906c5265dc8803fb1
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Wed Nov 11 10:36:28 2009 -0600
+
+ Move do_irqinfo() to common/cmd_irq.c
+
+ cmd_irq.c is a much better home and it is already conditionally
+ compiled based on CONFIG_CMD_IRQ.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit a5dd4dc64fe68e549c5ffcf6a048281b5ba94752
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Wed Nov 11 10:36:19 2009 -0600
+
+ cmd_license: Remove unneeded #ifdef CONFIG_CMD_LICENSE
+
+ cmd_license is already conditionally compiled at the Makefile-level.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 06015146a15adc7455440c491d543f6a8091551d
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Mon Nov 9 15:18:52 2009 -0600
+
+ m41t11: Remove unused functions
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 9ef78511cda39987e5fc10febf386fd19f58ecf7
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Mon Nov 9 15:17:50 2009 -0600
+
+ circbuf: Move to lib_generic and conditionally compile
+
+ circbuf could be used as a generic library and is only currently
+ needed when CONFIG_USB_TTY is defined.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 604f7ce55ad74694ef8743ad2e99933dc0265e46
+Author: Sanjeev Premi <premi@ti.com>
+Date: Mon Nov 9 22:43:00 2009 +0530
+
+ Fix build failure in examples/standalone
+
+ Some versions of 'make' do not handle trailing white-spaces
+ properly. Trailing spaces in ELF causes a 'fake' source to
+ be added to the variable COBJS; leading to build failure
+ (listed below). The problem was found with GNU Make 3.80.
+
+ Using text-function 'strip' as a workaround for the problem.
+
+ make[1]: Entering directory `/home/sanjeev/u-boot/examples/standalone'
+ arm-none-linux-gnueabi-gcc -g -Os -fno-common -ffixed-r8 -msoft-float
+ -D__KERNEL__ -DTEXT_BASE=0x80e80000 -I/home/sanjeev/u-boot/include
+ -fno-builtin -ffreestanding -nostdinc -isystem /opt/codesourcery/2009q1-
+ 203/bin/../lib/gcc/arm-none-linux-gnueabi/4.3.3/include -pipe -DCONFIG_
+ ARM -D__ARM__ -marm -mabi=aapcs-linux -mno-thumb-interwork -march=armv5
+ -Wall -Wstrict-prototypes -fno-stack-protector -g -Os -fno-common -ff
+ ixed-r8 -msoft-float -D__KERNEL__ -DTEXT_BASE=0x80e80000 -I/home/sanje
+ ev/u-boot/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/co
+ desourcery/2009q1-203/bin/../lib/gcc/arm-none-linux-gnueabi/4.3.3/includ
+ e -pipe -DCONFIG_ARM -D__ARM__ -marm -mabi=aapcs-linux -mno-thumb-inte
+ rwork -march=armv5 -I.. -Bstatic -T u-boot.lds -Ttext 0x80e80000 -o .c
+ arm-none-linux-gnueabi-gcc: no input files
+ make[1]: *** [.c] Error 1
+ make[1]: Leaving directory `/home/sanjeev/u-boot/examples/standalone'
+ make: *** [examples/standalone] Error 2
+ premi #
+
+ Signed-off-by: Sanjeev Premi <premi@ti.com>
+
+ Fixed typo (s/ElF/ELF/).
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit af860962b544ddf323c4ff68454f00d31e44df0a
+Author: Becky Bruce <beckyb@kernel.crashing.org>
+Date: Wed Nov 4 18:30:08 2009 -0600
+
+ 85xx: Remove unused CONFIG_ASSUME_AMD_FLASH from config files
+
+ A bunch of the 85xx boards have this cruft in them - it's not used
+ anywhere. Delete it.
+
+ Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
+
+commit deec1fbd4f704dded2e668bb9e368631981ea139
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Dec 2 22:26:30 2009 +0100
+
+ MAINTAINERS: update responsible for MPC85xx/86xx
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: Kumar Gala <galak@kernel.crashing.org>
+ Cc: Becky Bruce <beckyb@kernel.crashing.org>
+
+commit 824d82997fbcf28e49081d36fdd5d3be1b92b03d
+Author: Ira W. Snyder <iws@ovro.caltech.edu>
+Date: Wed Nov 4 13:37:59 2009 -0800
+
+ Fix example FIT image source files
+
+ The example FIT image source files do not compile with the latest dtc and
+ mkimage. The following error message is produced:
+
+ DTC: dts->dtb on file "kernel.its"
+ Error: kernel.its 7:0 - 1:0 syntax error
+ FATAL ERROR: Unable to parse input tree
+ ./mkimage: Can't read kernel.itb.tmp: Invalid argument
+
+ The FIT image source files are missing the "/dts-v1/;" directive at the
+ beginning of the file. Add the directive to the examples.
+
+ Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
+
+commit fd66066ee3ce15c2966feb9b2be0f0d51a95db48
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Nov 4 16:13:19 2009 -0500
+
+ img2srec: use standard types
+
+ The img2srec code creates a lot of typedefs with common names. These
+ easily clash with system headers that include these typedefs (like mingw).
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 8204e068110e8abe5db9c3b7df9971b58cda8f26
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Nov 4 16:03:25 2009 -0500
+
+ tools: gitignore *.exe binaries
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 425d3b666eee5c58fdb82fb894a535dd71782a05
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Nov 3 23:31:07 2009 -0600
+
+ ppc: Move conditional compilation of kgdb.c to Makefile
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit e06ab6546b332acc55ac4e7c31338662328b0fb3
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Tue Nov 3 11:36:39 2009 -0500
+
+ spi_flash.h: pull in linux/types.h for u## types
+
+commit 0008555f4d57c15ad86ee735861ca0d783042f61
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Tue Nov 3 11:36:26 2009 -0500
+
+ bootm: mark local boot_os[] table static
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit a8fa379d47f06c7d3ed75c8fb26ae43ee38e1fd7
+Author: Nishanth Menon <nm@ti.com>
+Date: Mon Nov 2 09:40:18 2009 -0600
+
+ mkconfig: deny messed up ARCH definition
+
+ Refuse to setup a platform if the command line ARCH= is not the same
+ as the one required for the board. This prevents any user with
+ prehistoric aliases from messing up their builds.
+
+ Reported in thread:
+ http://old.nabble.com/-U-Boot--Build-breaks-on-some-OMAP3-configs-to26132721.html
+
+ Inputs from: Mike Frysinger and Wolfgang Denk:
+ http://lists.denx.de/pipermail/u-boot/2009-November/063642.html
+
+ Cc: Wolfgang Denk <wd@denx.de>
+ Cc: Mike Frysinger <vapier@gentoo.org>
+ Cc: Anand Gadiyar <gadiyar@ti.com>
+ Cc: Dirk Behme <dirk.behme@googlemail.com>
+ Signed-off-by: Nishanth Menon <nm@ti.com>
+
+commit 67b96e87da1b84660fa1e5b78cc760246d116814
+Author: Remy Bohmer <linux@bohmer.net>
+Date: Wed Oct 28 22:13:39 2009 +0100
+
+ Repair the 'netretry=once' option.
+
+ 'netretry = once' does the same as 'netretry = yes', because it is not stored
+ when it was tried once.
+
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit b25e38fc36e13fa8037fa4d37fe909d1d6e6f372
+Author: Remy Bohmer <linux@bohmer.net>
+Date: Thu Oct 29 14:24:22 2009 +0100
+
+ Repair build fail in case CONFIG_PPC=n and CONFIG_FIT=y
+
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 01826abc02ce160501534788e63629ccbe31b05c
+Author: Grazvydas Ignotas <notasas@gmail.com>
+Date: Thu Nov 12 11:46:07 2009 +0200
+
+ OMAP3: pandora: fix booting without serial attached
+
+ When the board is booted without serial cable attached (which
+ is how most of them will be used) UART RX is left floating and
+ sometimes picks noise, which interrupts countdown and enters
+ U-Boot prompt instead of booting the kernel.
+
+ Fix this by setting up internal pullup on UART RX pin. This
+ does not prevent serial from working as the internal pullup
+ is weak.
+
+ Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
+
+commit 41dfd8a60324243dbe2dc313a607910824a68aa7
+Author: Remy Bohmer <linux@bohmer.net>
+Date: Wed Oct 28 22:13:37 2009 +0100
+
+ Add support for CS2 dataflash for Atmel-SPI.
+
+ The only missing chipselect line support is CS2, and I need it on
+ CS2...
+
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit faf36c1437c95e4a86835633d9801c5f6396a3c7
+Author: Remy Bohmer <linux@bohmer.net>
+Date: Wed Oct 28 22:13:36 2009 +0100
+
+ Fix mingw tools build
+
+ mkimage does not build due to missing strtok_r() and getline() implementation
+
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 6a590c5f5fd12cdd27f3153522acfac3854590e7
+Author: Remy Bohmer <linux@bohmer.net>
+Date: Wed Oct 28 22:13:35 2009 +0100
+
+ Building of FIT images does not work.
+
+ The type is not set for generation of the FIT images, resulting
+ in no images being created without printing or returning an error
+
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 0a7691e820e33b23f61c6ea0ef6fa72099d1a6ae
+Author: Renato Andreola <renato.andreola@imagos.it>
+Date: Mon Nov 23 16:45:14 2009 -0500
+
+ Nios2: do_boom_linux(): kernel gunzip input data integrity problem due to
+ missing cache flush.
+
+ Added instruction and data caches flush.
+
+ Signed-off-by: Scott McNutt <smcnutt@psyent.com>
+
+commit de03825386eaedb5e17261dd87cde86e9a764ba9
+Author: Scott McNutt <smcnutt@psyent.com>
+Date: Mon Nov 23 16:29:40 2009 -0500
+
+ Nios2: Fix compiler warnings in lib_nios2/board.c (unused variables)
+
+ Signed-off-by: Scott McNutt <smcnutt@psyent.com>
+
+commit 57baa379cf2f67df89a5c6052767fd25daff20bd
+Author: Scott McNutt <smcnutt@psyent.com>
+Date: Mon Nov 23 15:54:25 2009 -0500
+
+ Nios2/Nios: Remove unnecessary (residual) linker Nios command scripts from
+ the standalone examples.
+
+ Signed-off-by: Scott McNutt <smcnutt@psyent.com>
+
+commit fcffb680e77fcb48598d4a9944dbe2d4503170e0
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Wed Oct 14 19:28:03 2009 -0400
+
+ sf: fix stmicro offset setup while erasing
+
+ Reported-by: Peter Gombos <gombos@protecta.hu>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit d394a7795027d96ca55799df40bd5c4a13dbeebe
+Author: Jason McMullan <mcmullan@netapp.com>
+Date: Fri Oct 9 17:12:23 2009 -0400
+
+ sf: new driver for Winbond W25X16/32/64 devices
+
+ Signed-off-by: Jason McMullan <jason.mcmullan@gmail.com>
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit cada315100c88894b85972a91309a6f2413966b6
+Author: Marcel Ziswiler <marcel@ziswiler.com>
+Date: Thu Oct 1 23:55:17 2009 +0200
+
+ mpc8260: move FDT memory node fixup into common CPU code.
+
+ Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com>
+ Tested-by: Heiko Schocher <hs@denx.de>
+
+commit f2cea405f83da46b72098ea874fb3eefe185d312
+Author: Po-Yu Chuang <ratbert.chuang@gmail.com>
+Date: Wed Sep 23 15:52:35 2009 +0800
+
+ Add driver for FTRTC010 real time clock
+
+ Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
+
+ Edited commit message.
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit c0356a88011330646e960dfac8a2c909bede3304
+Author: Mark Jackson <mpfj-list@mimc.co.uk>
+Date: Mon Aug 17 16:42:52 2009 +0100
+
+ MIMC200: set default fbmem value
+
+ This patch adds a default bootargs "fbmem" value to the
+ CONFIG_BOOTARGS string for the MIMC200 board.
+
+ Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
+
+commit 3ffc0d61bad7d986e344ce7062b37c5c8f04fb0e
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Tue Oct 27 19:58:09 2009 +0100
+
+ ppc4xx: Initialize magnetic coupler on VOM405 boards
+
+ This patch fixes an ugly behavior of the IL712 magnetic coupler
+ as used on VOM405. These parts will remember their last state
+ over a power cycle which might cause unwanted behavior.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit be0db3e3141c6c6b4e232b51091f35a284cc54e5
+Author: Matthias Fuchs <matthias.fuchs@esd.eu>
+Date: Mon Oct 26 09:58:45 2009 +0100
+
+ ppc4xx: Initialize magnetic couplers in PLU405
+
+ This patch fixes an ugly behavior of the IL712 magnetic couplers
+ as used on PLU405. These parts will remember their last state
+ over a power cycle which might cause unwanted behavior.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 067f54c66acd469870ef6946e1591bfcc02de1b3
+Author: Matthias Fuchs <matthias.fuchs@esd.eu>
+Date: Mon Oct 26 09:55:40 2009 +0100
+
+ Add minimal SJA1000 header for basic CAN mode
+
+ This patch is in preparation for the upcoming PLU405 board fix.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit cdbdbe65f5f006cba208accee5a126c659d4b867
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Fri Nov 13 08:52:21 2009 -0600
+
+ ppc/85xx: Fix how we determine the number of CAM entries
+
+ We were incorrectly use the max CAM size as the number of entries in
+ the array for setting up the addrmap. We should be using the NENTRY
+ field which is the low 12-bits of TLB1CFG.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit fbd47b6753b08162436d9ccad1e63c8d43ede54c
+Author: Mike Rapoport <mike@compulab.co.il>
+Date: Thu Nov 12 15:35:08 2009 +0200
+
+ smc911x: make smc911x_initialize return correct value
+
+ Make smc911x_initialize return -1 on error and number of interfaces
+ detected otherwise.
+
+ Signed-off-by: Mike Rapoport <mike@compulab.co.il>
+ Acked-by: Mike Frysinger <vapier@gentoo.org>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit c44efcf97b335dcef7d014f65b7d3094e79adb13
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Nov 12 22:26:02 2009 -0500
+
+ smc911x_eeprom: fix building after smc911x overhaul
+
+ When the smc911x driver was converted to NET_MULTI, the smc911x eeprom was
+ missed. The config option needed updating as well as overhauling of the
+ rergister read/write functions.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Tested-by: Mike Rapoport <mike.rapoport@gmail.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 3ad95deb30ac73bd57e966d321215a17d3236f9f
+Author: Dave Liu <daveliu@freescale.com>
+Date: Thu Nov 12 07:26:37 2009 +0800
+
+ fsl-ddr: Fix the chip-select interleaving issue
+
+ commit 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3
+ introduced one new bug to chip-select interleaving.
+
+ Single DDR controller also can do the chip-select
+ interleaving if there is dual-rank or qual-rank DIMMs.
+
+ Signed-off-by: Dave Liu <daveliu@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 651ef90fa6ca824c8e581aeef9e04bbbe7f7e9ce
+Author: javier Martin <javier.martin@vista-silicon.com>
+Date: Thu Oct 29 08:22:43 2009 +0100
+
+ mxc_fec: avoid free() calls to already freed pointers.
+
+ Sometimes, inside NetLoop, eth_halt() is called before eth_init() has
+ been called. This is harmless except for free() calls to pointers
+ which have not been allocated yet.
+
+ This patch initializes those pointers to NULL and allocates them only
+ the first time. This way we can get rid of free calls in halt callback.
+
+ This has been tested in i.MX27 Litekit board and eldk-4.2 toolchains.
+
+ Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit e8f1546a88b4ade6a910c4a7958a774ee1b40023
+Author: javier Martin <javier.martin@vista-silicon.com>
+Date: Thu Oct 29 08:18:34 2009 +0100
+
+ mxc_fec: fix some erroneous PHY accesses.
+
+ This patch fixes erroneous access to the ethernet PHY which broke the driver.
+ 1. Selector field in the auto-negotiation register must be 0x00001 for
+ using 802.3, not 0x00000 which is reseved.
+ 2. Access to the PHY address specified by CONFIG_FEC_MXC_PHYADDR, not
+ 0x0 fixed address.
+
+ This has been tested in i.MX27 Litekit board and eldk-4.2 toolchains.
+
+ Now using proper defines for auto-negotiation register.
+
+ Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit f865fcbbb35851e75fee9c3a3fa8e0f71d9e6463
+Author: Ron Lee <ron@debian.org>
+Date: Wed Aug 5 20:14:01 2009 +0200
+
+ ARM Don't inline weak symbols
+
+ ------------------------------------------------------------------------
+
+ GCC 4.4 complains about this now.
+
+ Signed-off-by: Ron Lee <ron@debian.org>
+
+commit d14c7ec2b51fb92c4a5218b299b772c3d186510d
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date: Mon Nov 9 13:09:57 2009 -0800
+
+ Fix SMC91111 regression: lpd7a40x build failures
+
+ Both lpd7a400 and lpd7a404 failed to compile because they had
+ CONFIG_SMC_USE_IOFUNCS defined:
+
+ examples/standalone/smc91111_eeprom.c:388: undefined reference to `SMC_outw'
+
+ Also removed an orphaned paren in lpd7a404.h
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 1031ae960ce6ce8332190278a06e2d72c2b2793e
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date: Mon Nov 9 14:01:08 2009 -0800
+
+ SMC91111: Clean up SMC_inx macros on xsengine and xaeniax
+
+ This patch fixes the following warnings:
+
+ Configuring for xaeniax board...
+ smc91111_eeprom.c: In function 'print_macaddr':
+ smc91111_eeprom.c:278: warning: suggest parentheses around + or - in operand of &
+ smc91111_eeprom.c:281: warning: suggest parentheses around + or - in operand of &
+ ...
+ Configuring for xsengine board...
+ smc91111_eeprom.c: In function 'print_macaddr':
+ smc91111_eeprom.c:278: warning: suggest parentheses around + or - inside shift
+ smc91111_eeprom.c:281: warning: suggest parentheses around + or - inside shift
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 830c7b6722c6a9762411bf52a7bf2fae4dc71dab
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date: Mon Nov 9 11:43:18 2009 -0800
+
+ Fix CS8900 regression on impa7 board
+
+ The following error was seen on impa7 board, due to its use of a 32-bit bus
+ on CS8900.
+ cs8900.c:137:37: error: macro "get_reg_init_bus" passed 2 arguments, but takes just 1
+
+ This patch gives the macro the correct number of arguments
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit e5c5d9e0834bacf1c4787fa76cc4e369f2597cf5
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sun Nov 1 22:39:56 2009 -0500
+
+ clarify eth driver halt/recv steps
+
+ The dev->halt() func can be called at any time, and the dev->recv() func
+ does not need to use NetRxPackets[] when calling NetReceive().
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 497ab0eec5e1e2dfccc141a4485cd6b940e1424a
+Author: Hui.Tang <zetalabs@gmail.com>
+Date: Thu Nov 5 09:58:44 2009 +0800
+
+ Fix cs8900 dev->priv not init issue
+
+ Ensure all CS8900 data structures are assigned before accessing device
+
+ Signed-off-by: Hui.Tang <zetalabs@gmail.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 4fe5193d464ecdac26ddc71b1351be5b86bbff29
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Nov 3 14:34:45 2009 +0100
+
+ ppc4xx: 44x_spd_ddr2.c: Fix register macro ECCCR -> ECCES (SDRAM_ECCES)
+
+ This error only appears when DEBUG is enabled in this driver. That's why
+ it went unnoticed till now.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 916ed9444d3ab7b5cd6312557005f2a764a8baf7
+Author: Stefan Roese <sr@denx.de>
+Date: Thu Oct 29 18:37:45 2009 +0100
+
+ ppc4xx: Canyonlands: Change EBC bus config to drive always (no high-z)
+
+ This patch fixes a problem only seen very occasionally on Canyonlands.
+ The NOR flash interface (CFI driver) doesn't work reliably in all cases.
+ Erasing and/or programming sometimes doesn't work. Sometimes with
+ an error message, like "flash not erased" when trying to program an
+ area that should have just been erased. And sometimes without any error
+ messages. As mentioned above, this problem was only seen rarely and with
+ some PLL configuration (CPU speed, EBC speed).
+
+ Now I spotted this problem a few times, when running my Canyonlands with
+ the following setup (chip_config):
+
+ 1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100
+
+ Changing the EBC configuration to not release the bus into high
+ impedance state inbetween the transfers (ATC, DTC and CTC bits set to 1
+ in EBC0_CFG) seems to fix this problem. I haven't seen any failure
+ anymore with this patch applied.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: David Mitchell <dmitchell@amcc.com>
+ Cc: Jeff Mann <MannJ@embeddedplanet.com>
+
+commit 25793f76bf9a7be59c9415ef0f78d034e8d53dae
+Author: Remy Bohmer <linux@bohmer.net>
+Date: Thu Oct 29 12:29:37 2009 +0100
+
+ ARM: Use Linux version for unaligned access code
+
+ The asm-arm/unaligned.h includes linux/unaligned/access_ok.h
+ This file is unsafe to be used on ARM, since it does an unaligned memory
+ accesses which fails on ARM.
+
+ Lookin at Linux the basic difference seems to be the header
+ "include/asm-arm/unaligned.h". The Linux version of "unaligned.h"
+ does *not* include "access_ok.h" at all. It includes "le_byteshift.h"
+ and "be_byteshift.h" instead.
+
+ Signed-off-by: Remy Bohmer <linux@bohmer.net>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ --
+ include/asm-arm/unaligned.h | 3 -
+ include/linux/unaligned/be_byteshift.h | 70 +++++++++++++++++++++++++++++++++
+ include/linux/unaligned/le_byteshift.h | 70 +++++++++++++++++++++++++++++++++
+ 3 files changed, 142 insertions(+), 1 deletion(-)
+ create mode 100644 include/linux/unaligned/be_byteshift.h
+ create mode 100644 include/linux/unaligned/le_byteshift.h
+
+commit 6d6e7c53d5c75e5e24841c5506f4ed9d82adee09
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Wed Nov 4 18:02:10 2009 -0600
+
+ ppc/85xx: Fix inclusion of 83xx immap in 85xx builds
+
+ The nand_boot_fsl_elbc.c is shared between 83xx & 85xx however we should
+ not be including the immap_83xx.h when building 85xx. We can just get
+ this all from common.h
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 107b579c75256212d4bf8b99ee8d68e0078f3646
+Author: Becky Bruce <beckyb@kernel.crashing.org>
+Date: Wed Nov 4 17:34:04 2009 -0600
+
+ 86xx: Remove redundant code in initdram
+
+ The same code exists both inside an #ifdef and outside of it.
+ Remove the extra code for all the 86xx boards.
+
+ Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 715d8f7608f77c93f1807a032644893fd5b6d08b
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Mon Nov 2 09:05:49 2009 -0600
+
+ fsl_pci_init_port end-point initialization is broken
+
+ commit 70ed869e broke fsl pcie end-point initialization.
+ Returning 0 is not correct. The function must return the first free
+ bus number for the next controller.
+
+ fsl_pci_init() must still be called and a bus allocated even if the
+ controller is an end-point.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+ Acked-by: Vivek Mahajan <vivek.mahajan@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 01471d538fb163f472a769f21267d7676c91267c
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Wed Nov 4 01:29:04 2009 -0600
+
+ Revert "ppc/85xx/pci: fsl_pci_init: pcie agent mode support"
+
+ This reverts commit 70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc.
+
+ There isn't any need to modify the API for fsl_pci_init_port to pass the
+ status of host/agent(end-point) status. We can determine that
+ internally to fsl_pci_init_port. Revert the patch that makes the API
+ change.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit ff88229549e08fdd3f9127c1cc4db11a3576250f
+Author: Dave Liu <daveliu@freescale.com>
+Date: Sat Oct 31 07:59:55 2009 +0800
+
+ ppc/85xx: Fix misc L2 cache enabling bug
+
+ We need loop-check the flash clear lock and enable bit for L2 cache.
+
+ Signed-off-by: Dave Liu <daveliu@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 59434fe243962758742af5cb8e2ced976e17c302
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Fri Oct 30 10:16:27 2009 +0900
+
+ sh: Update lowlevel_init.S of espt-giga
+
+ There was the point that did not use write macro.
+ Change to write macro.
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit f1cae1969d9e971fb72827a5731ce7e752464aa2
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Fri Oct 30 10:01:25 2009 +0900
+
+ sh: Move some defs to convince 'pcrel too far'
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ Signed-off-by: Takashi Yoshii <yoshii.takashi@gmail.com>
+
+commit 0f9eaf4b323ea0ca95944b84c7465b81ba575514
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Thu Oct 15 13:36:34 2009 +0900
+
+ sh: Remove malloc_bin_reloc from lib_sh, lib_nios2 and lib_nios.
+
+ By "arm/microblaze/nios/nios2/sh: Remove relocation fixups"
+ (commit: 0630535e2d062dd73c1ceca5c6125c86d1127a49", doesn't need
+ malloc_bin_reloc function. This commit remove this.
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 0775437293a6963cb21244dfae6978cbf67c6bfe
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date: Wed Oct 21 21:53:39 2009 -0700
+
+ Fix DM9000 MAC address handling
+
+ Proper behavior is to pull MAC address from NVRAM in the initialization() an
+ stuff it in dev->address, then program the device from dev->address in
+ the init() function.
+
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 98d92d8c9f4021629a45261ad5ec3f3595f3a27a
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Oct 28 22:07:56 2009 +0100
+
+ sbc8349: fix incorrect comment
+
+ The comment for the BR0_PRELIM port size initialization incorrectly
+ stated 32 bit, while it's actually 16 bit. The code is correct.
+
+ Reported-by: Guenter Koellner <guenter.koellner@nsn.com>
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit a38f85e180a30b6225808828ded1017b1a5418c6
+Author: Sandeep Paulraj <s-paulraj@ti.com>
+Date: Wed Oct 28 11:05:03 2009 -0400
+
+ Fix Compliation warning for TNY-A9260 and TNY-A9G20
+
+ The patch fixes a compilation warning by defining
+ CONFIG_SYS_64BIT_VSPRINTF in the config file
+
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 264e42ee54f1d322805d9068168fd362b413fd09
+Author: Sandeep Paulraj <s-paulraj@ti.com>
+Date: Wed Oct 28 11:04:53 2009 -0400
+
+ Fix Compliation warning for SBC35-A9G20 board
+
+ The patch fixes a compilation warning by defining
+ CONFIG_SYS_64BIT_VSPRINTF in the config file
+
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 353462f6ff9769091fb644d44d8025f20a4192d9
+Author: Eric Millbrandt <emillbrandt@coldhaus.com>
+Date: Wed Oct 28 09:37:33 2009 -0500
+
+ galaxy5200: Add default environment variables
+
+ Extend bootdelay to 10 seconds. Set boot retry time to 120 seconds and use
+ reset to retry. Define default bootcommand and bootargs for production.
+
+ Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
+
+commit fa36ae790eb10ce70935f9a78f07703719dca422
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Oct 27 15:15:55 2009 +0100
+
+ cfi: Add weak default function for flash_cmd_reset()
+
+ Currently the CFI driver issues both AMD and Intel reset commands.
+ This is because the driver doesn't know yet which chips are connected.
+ This dual reset seems to cause problems with the M29W128G chips as
+ reported by Richard Retanubun. This patch now introduces a weak default
+ function for the CFI reset command, still with both resets. This can
+ be overridden by a board specific version if necessary.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Richard Retanubun <RichardRetanubun@ruggedcom.com>
+
+commit 4946775c6db52dba28f72ba3525764b54f1d4593
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Oct 28 00:49:47 2009 +0100
+
+ Coding Style cleanup; update CHANGELOG, prepare -rc1
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit 246c69225c7b962d5c93e92282b78ca9fc5fefee
Author: Peter Tyser <ptyser@xes-inc.com>
Date: Sun Oct 25 15:12:56 2009 -0500
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+commit 2c0c58b92dbb68007061bdc0edd23bdf142efebf
+Author: Sergey Mironov <ierton@gmail.com>
+Date: Wed Sep 23 16:47:38 2009 +0400
+
+ Fix bug in jumptable call stubs for SPARC.
+
+ Signed-off-by: Sergey Mironov <ierton@gmail.com>
+ Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
+
commit 3e303f748cf57fb23e8ec95ab7eac0074be50e2b
Author: Anton Vorontsov <avorontsov@ru.mvista.com>
Date: Thu Oct 15 17:47:04 2009 +0400
mecp5200 MPC5200
pf5200 MPC5200
+ caddy2 MPC8349
vme8349 MPC8349
CPCI750 PPC750FX/GX
Wolfgang Grandegger <wg@denx.de>
+ ipek01 MPC5200
+
CCM MPC855
PN62 MPC8240
ZUMA MPC7xx_74xx
-Jon Loeliger <jdl@freescale.com>
+Kumar Gala <kumar.gala@freescale.com>
MPC8540ADS MPC8540
MPC8560ADS MPC8560
AT91RM9200DK at91rm9200
+Po-Yu Chuang <ratbert@faraday-tech.com>
+
+ a320evb FA526 (ARM920T-like) (a320 SoC)
+
George G. Davis <gdavis@mvista.com>
assabet SA1100
B2 ARM7TDMI (S3C44B0X)
+Nick Thompson <nick.thompson@gefanuc.com>
+
+ da830evm ARM926EJS (DA830/OMAP-L137)
+
Albin Tonnerre <albin.tonnerre@free-electrons.com>
sbc35_a9g20 ARM926EJS (AT91SAM9G20 SoC)
-#!/bin/sh
+#!/bin/bash
# Print statistics when we exit
trap exit 1 2 3 15
ERR_CNT=0
ERR_LIST=""
TOTAL_CNT=0
+RC=0
#########################################################################
## MPC5xx Systems
icecube_5100 \
icecube_5200 \
inka4x0 \
+ ipek01 \
lite5200b \
mcc200 \
mecp5200 \
#########################################################################
LIST_83xx=" \
+ caddy2 \
kmeter1 \
MPC8313ERDB_33 \
MPC8313ERDB_NAND_66 \
MPC8315ERDB \
+ MPC8315ERDB_NAND \
MPC8323ERDB \
MPC832XEMDS \
MPC832XEMDS_ATM \
#########################################################################
LIST_ARM9=" \
+ a320evb \
ap920t \
ap922_XA10 \
ap926ejs \
cp926ejs \
cp946es \
cp966 \
+ da830evm \
imx27lite \
lpd7a400 \
mv88f6281gtw_ge \
${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \
| tee ${LOG_DIR}/$target.ERR
+
+ # Check for 'make' errors
+ if [ ${PIPESTATUS[0]} -ne 0 ] ; then
+ RC=1
+ fi
+
if [ -s ${LOG_DIR}/$target.ERR ] ; then
ERR_CNT=$((ERR_CNT + 1))
ERR_LIST="${ERR_LIST} $target"
echo "Boards with warnings or errors: ${ERR_CNT} (${ERR_LIST} )"
fi
echo "----------------------------------------------------------"
+
+ exit $RC
}
#-----------------------------------------------------------------------
VERSION = 2009
PATCHLEVEL = 11
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION =
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
LIBS += drivers/qe/qe.a
LIBS += cpu/mpc8xxx/ddr/libddr.a
LIBS += cpu/mpc8xxx/lib8xxx.a
-TAG_SUBDIRS += cpu/mpc8xxx
endif
ifeq ($(CPU),mpc86xx)
LIBS += cpu/mpc8xxx/ddr/libddr.a
LIBS += cpu/mpc8xxx/lib8xxx.a
-TAG_SUBDIRS += cpu/mpc8xxx
endif
LIBS += drivers/rtc/librtc.a
LIBS += drivers/serial/libserial.a
LIBS += drivers/usb/gadget/libusb_gadget.a
LIBS += drivers/usb/host/libusb_host.a
LIBS += drivers/usb/musb/libusb_musb.a
+LIBS += drivers/usb/phy/libusb_phy.a
LIBS += drivers/video/libvideo.a
LIBS += drivers/watchdog/libwatchdog.a
LIBS += common/libcommon.a
depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir _depend ; done
+TAG_SUBDIRS = $(SUBDIRS)
+TAG_SUBDIRS += $(dir $(__LIBS))
TAG_SUBDIRS += include
-TAG_SUBDIRS += lib_generic board/$(BOARDDIR)
-TAG_SUBDIRS += cpu/$(CPU)
-TAG_SUBDIRS += lib_$(ARCH)
-TAG_SUBDIRS += fs/cramfs
-TAG_SUBDIRS += fs/fat
-TAG_SUBDIRS += fs/fdos
-TAG_SUBDIRS += fs/jffs2
-TAG_SUBDIRS += fs/yaffs2
-TAG_SUBDIRS += net
-TAG_SUBDIRS += disk
-TAG_SUBDIRS += common
-TAG_SUBDIRS += drivers/bios_emulator
-TAG_SUBDIRS += drivers/block
-TAG_SUBDIRS += drivers/gpio
-TAG_SUBDIRS += drivers/hwmon
-TAG_SUBDIRS += drivers/i2c
-TAG_SUBDIRS += drivers/input
-TAG_SUBDIRS += drivers/misc
-TAG_SUBDIRS += drivers/mmc
-TAG_SUBDIRS += drivers/mtd
-TAG_SUBDIRS += drivers/mtd/nand
-TAG_SUBDIRS += drivers/mtd/onenand
-TAG_SUBDIRS += drivers/mtd/spi
-TAG_SUBDIRS += drivers/net
-TAG_SUBDIRS += drivers/net/sk98lin
-TAG_SUBDIRS += drivers/pci
-TAG_SUBDIRS += drivers/pcmcia
-TAG_SUBDIRS += drivers/qe
-TAG_SUBDIRS += drivers/rtc
-TAG_SUBDIRS += drivers/serial
-TAG_SUBDIRS += drivers/spi
-TAG_SUBDIRS += drivers/usb
-TAG_SUBDIRS += drivers/video
tags ctags:
- ctags -w -o $(obj)ctags `find $(SUBDIRS) $(TAG_SUBDIRS) \
- -name '*.[ch]' -print`
+ ctags -w -o $(obj)ctags `find $(TAG_SUBDIRS) \
+ -name '*.[chS]' -print`
etags:
- etags -a -o $(obj)etags `find $(SUBDIRS) $(TAG_SUBDIRS) \
- -name '*.[ch]' -print`
+ etags -a -o $(obj)etags `find $(TAG_SUBDIRS) \
+ -name '*.[chS]' -print`
cscope:
- find $(SUBDIRS) $(TAG_SUBDIRS) -name '*.[ch]' -print \
- > cscope.files
+ find $(TAG_SUBDIRS) -name '*.[chS]' -print > cscope.files
cscope -b -q -k
SYSTEM_MAP = \
inka4x0_config: unconfig
@$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0
+ipek01_config: unconfig
+ @$(MKCONFIG) -a ipek01 ppc mpc5xxx ipek01
+
lite5200b_config \
lite5200b_PM_config \
lite5200b_LOWBOOT_config: unconfig
echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \
fi ;
+MPC8315ERDB_NAND_config \
MPC8315ERDB_config: unconfig
- @$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
+ @if [ "$(findstring _NAND_,$@)" ] ; then \
+ ln -sf mpc8313erdb nand_spl/board/freescale/mpc8315erdb ; \
+ fi ;
+ @$(MKCONFIG) -t $(@:_config=) MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
MPC8323ERDB_config: unconfig
@$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale
TQM834x_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc
+caddy2_config \
vme8349_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc83xx vme8349 esd
+ @$(MKCONFIG) -t $(@:_config=) vme8349 ppc mpc83xx vme8349 esd
#########################################################################
## MPC85xx Systems
## ARM92xT Systems
#########################################################################
+a320evb_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm920t a320evb faraday a320
+
#########################################################################
## Atmel AT91RM9200 Systems
#########################################################################
cp1026_config: unconfig
@board/armltd/integrator/split_by_variant.sh cp $@
+da830evm_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs da830evm davinci davinci
+
davinci_dvevm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dvevm davinci davinci
#########################################################################
apollon_config : unconfig
+ @mkdir -p $(obj)include
@echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h
@$(MKCONFIG) $(@:_config=) arm arm1136 apollon NULL omap24xx
@echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
#
-# (C) Copyright 2000 - 2008
+# (C) Copyright 2000 - 2009
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
Directory Hierarchy:
====================
+- api Machine/arch independent API for external apps
- board Board dependent files
- common Misc architecture independent functions
- cpu CPU specific files
- disk Code for disk drive partition handling
- doc Documentation (don't expect too much)
- drivers Commonly used device drivers
-- dtt Digital Thermometer and Thermostat drivers
- examples Example code for standalone applications, etc.
+- fs Filesystem code (cramfs, ext2, jffs2, etc.)
- include Header Files
- lib_arm Files generic to ARM architecture
- lib_avr32 Files generic to AVR32 architecture
- lib_generic Files generic to all architectures
- lib_i386 Files generic to i386 architecture
- lib_m68k Files generic to m68k architecture
+- lib_microblaze Files generic to microblaze architecture
- lib_mips Files generic to MIPS architecture
- lib_nios Files generic to NIOS architecture
+- lib_nios2 Files generic to NIOS2 architecture
- lib_ppc Files generic to PowerPC architecture
+- lib_sh Files generic to SH architecture
- lib_sparc Files generic to SPARC architecture
- libfdt Library files to support flattened device trees
- net Networking code
CONFIG_LBA48
Set this to enable support for disks larger than 137GB
- Also look at CONFIG_SYS_64BIT_LBA ,CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
+ Also look at CONFIG_SYS_64BIT_LBA.
Whithout these , LBA48 support uses 32bit variables and will 'only'
support disks up to 2.1TB.
Define this to use i/o functions instead of macros
(some hardware wont work with macros)
- CONFIG_DRIVER_SMC911X
+ CONFIG_SMC911X
Support for SMSC's LAN911x and LAN921x chips
- CONFIG_DRIVER_SMC911X_BASE
+ CONFIG_SMC911X_BASE
Define this to hold the physical address
of the device (I/O space)
- CONFIG_DRIVER_SMC911X_32_BIT
+ CONFIG_SMC911X_32_BIT
Define this if data bus is 32 bits
- CONFIG_DRIVER_SMC911X_16_BIT
+ CONFIG_SMC911X_16_BIT
Define this if data bus is 16 bits. If your processor
automatically converts one 32 bit word to two 16 bit
- words you may also try CONFIG_DRIVER_SMC911X_32_BIT.
+ words you may also try CONFIG_SMC911X_32_BIT.
- USB Support:
At the moment only the UHCI host controller is
example, some LED's) on your board. At the moment,
the following checkpoints are implemented:
-- Automatic software updates via TFTP server
- CONFIG_UPDATE_TFTP
- CONFIG_UPDATE_TFTP_CNT_MAX
- CONFIG_UPDATE_TFTP_MSEC_MAX
-
- These options enable and control the auto-update feature;
- for a more detailed description refer to doc/README.update.
-
-- MTD Support (mtdparts command, UBI support)
- CONFIG_MTD_DEVICE
-
- Adds the MTD device infrastructure from the Linux kernel.
- Needed for mtdparts command support.
-
- CONFIG_MTD_PARTITIONS
-
- Adds the MTD partitioning infrastructure from the Linux
- kernel. Needed for UBI support.
-
Legacy uImage format:
Arg Where When
-150 common/cmd_nand.c Incorrect FIT image format
151 common/cmd_nand.c FIT image format OK
+- Automatic software updates via TFTP server
+ CONFIG_UPDATE_TFTP
+ CONFIG_UPDATE_TFTP_CNT_MAX
+ CONFIG_UPDATE_TFTP_MSEC_MAX
+
+ These options enable and control the auto-update feature;
+ for a more detailed description refer to doc/README.update.
+
+- MTD Support (mtdparts command, UBI support)
+ CONFIG_MTD_DEVICE
+
+ Adds the MTD device infrastructure from the Linux kernel.
+ Needed for mtdparts command support.
+
+ CONFIG_MTD_PARTITIONS
+
+ Adds the MTD partitioning infrastructure from the Linux
+ kernel. Needed for UBI support.
+
Modem Support:
--------------
- CONFIG_SYS_FAULT_MII_ADDR:
MII address of the PHY to check for the Ethernet link state.
-- CONFIG_SYS_64BIT_VSPRINTF:
- Makes vsprintf (and all *printf functions) support printing
- of 64bit values by using the L quantifier
-
-- CONFIG_SYS_64BIT_STRTOUL:
- Adds simple_strtoull that returns a 64bit value
-
- CONFIG_NS16550_MIN_FUNCTIONS:
Define this if you desire to only have use of the NS16550_init
and NS16550_putc functions for the serial driver located at
# bit12-11: TW2W
# bit31-13: zero required
-DATA 0xFFD01410 0x00000099 # DDR Address Control
-# bit1-0: 01, Cs0width=x16
-# bit3-2: 10, Cs0size=512Mb
-# bit5-4: 01, Cs1width=x16
-# bit7-6: 10, Cs1size=512Mb
+DATA 0xFFD01410 0x000000cc # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs1width=x8
+# bit7-6: 11, Cs1size=1Gb
# bit9-8: 00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
+
+ifdef CONFIG_NAND_U_BOOT
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+endif
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
#endif
}
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller *hose)
-{
- unsigned long addr;
-
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB3 devices to 0.
- | Set PLB3 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
- mfsdr(SD0_AMP1, addr);
- mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB3_ACR);
- mtdcr(PLB3_ACR, addr | 0x80000000);
-
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB4 devices to 0.
- +-------------------------------------------------------------------------*/
- mfsdr(SD0_AMP0, addr);
- mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
- mtdcr(PLB4_ACR, addr);
-
- /*-------------------------------------------------------------------------+
- | Set Nebula PLB4 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
- /* Segment0 */
- addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
- addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
- addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
- addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
- mtdcr(PLB0_ACR, addr);
-
- /* Segment1 */
- addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
- addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
- addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
- addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
- mtdcr(PLB1_ACR, addr);
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*--------------------------------------------------------------------------+
- * Set up Direct MMIO registers
- *--------------------------------------------------------------------------*/
- /*--------------------------------------------------------------------------+
- | PowerPC440 EP PCI Master configuration.
- | Map one 1Gig range of PLB/processor addresses to PCI memory space.
- | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
- | Use byte reversed out routines to handle endianess.
- | Make this region non-prefetchable.
- +--------------------------------------------------------------------------*/
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*--------------------------------------------------------------------------+
- * Set up Configuration registers
- *--------------------------------------------------------------------------*/
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*************************************************************************
- * pci_master_init
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
-void pci_master_init(struct pci_controller *hose)
-{
- unsigned short temp_short;
-
- /*--------------------------------------------------------------------------+
- | Write the PowerPC440 EP PCI Configuration regs.
- | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- | Enable PowerPC440 EP to act as a PCI memory target (PTM).
- +--------------------------------------------------------------------------*/
- pci_read_config_word(0, PCI_COMMAND, &temp_short);
- pci_write_config_word(0, PCI_COMMAND,
- temp_short | PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
-
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- /* Bamboo is always configured as host. */
- return (1);
-}
-#endif /* defined(CONFIG_PCI) */
-
/*----------------------------------------------------------------------------+
| is_powerpc440ep_pass1.
+----------------------------------------------------------------------------*/
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
+
+ifdef CONFIG_NAND_U_BOOT
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/amcc/bamboo/init.o (.text)
- board/amcc/bamboo/bamboo.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
}
#endif
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*
- * Disable everything
- */
- out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
- out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
- out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
- out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
-
- /*
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
- * strapping options to not support sizes such as 128/256 MB.
- */
- out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out_le32((void *)PCIL0_PIM0LAH, 0);
- out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
- out_le32((void *)PCIL0_BAR0, 0);
-
- /*
- * Program the board's subsystem id/vendor id
- */
- out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
- out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
#if defined(CONFIG_PCI)
-/*
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- */
-int is_pci_host(struct pci_controller *hose)
+int board_pcie_first(void)
{
- /* Board is always configured as host. */
- return (1);
-}
-
-static struct pci_controller pcie_hose[2] = {{0},{0}};
-
-void pcie_setup_hoses(int busno)
-{
- struct pci_controller *hose;
- int i, bus;
- int ret = 0;
- char *env;
- unsigned int delay;
- int start;
-
- /*
- * assume we're called after the PCIX hose is initialized, which takes
- * bus ID 0 and therefore start numbering PCIe's from 1.
- */
- bus = busno;
-
/*
* Canyonlands with SATA enabled has only one PCIe slot
* (2nd one).
*/
if (gd->board_type == BOARD_CANYONLANDS_SATA)
- start = 1;
- else
- start = 0;
-
- for (i = start; i <= 1; i++) {
+ return 1;
- if (is_end_point(i))
- ret = ppc4xx_init_pcie_endport(i);
- else
- ret = ppc4xx_init_pcie_rootport(i);
- if (ret == -ENODEV)
- continue;
- if (ret) {
- printf("PCIE%d: initialization as %s failed\n", i,
- is_end_point(i) ? "endpoint" : "root-complex");
- continue;
- }
-
- hose = &pcie_hose[i];
- hose->first_busno = bus;
- hose->last_busno = bus;
- hose->current_busno = bus;
-
- /* setup mem resource */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
- CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
- CONFIG_SYS_PCIE_MEMSIZE,
- PCI_REGION_MEM);
- hose->region_count = 1;
- pci_register_hose(hose);
-
- if (is_end_point(i)) {
- ppc4xx_setup_pcie_endpoint(hose, i);
- /*
- * Reson for no scanning is endpoint can not generate
- * upstream configuration accesses.
- */
- } else {
- ppc4xx_setup_pcie_rootpoint(hose, i);
- env = getenv ("pciscandelay");
- if (env != NULL) {
- delay = simple_strtoul(env, NULL, 10);
- if (delay > 5)
- printf("Warning, expect noticable delay before "
- "PCIe scan due to 'pciscandelay' value!\n");
- mdelay(delay * 1000);
- }
-
- /*
- * Config access can only go down stream
- */
- hose->last_busno = pci_hose_scan(hose);
- bus = hose->last_busno + 1;
- }
- }
+ return 0;
}
#endif /* CONFIG_PCI */
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
+
+ifdef CONFIG_NAND_U_BOOT
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+endif
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/amcc/canyonlands/init.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- _end = . ;
- PROVIDE (end = .);
-}
return (128 * 1024 * 1024); /* 128 MB */
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller *hose)
-{
- unsigned long strap;
-
- /*--------------------------------------------------------------------------+
- * The ebony board is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *--------------------------------------------------------------------------*/
- strap = mfdcr(CPC0_STRP1);
- if ((strap & 0x00100000) == 0) {
- printf("PCI: CPC0_STRP1[PAE] not set.\n");
- return 0;
- }
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r(PCIL0_PIM0SA, 0); /* disable */
- out32r(PCIL0_PIM1SA, 0); /* disable */
- out32r(PCIL0_PIM2SA, 0); /* disable */
- out32r(PCIL0_EROMBA, 0); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out32r(PCIL0_PIM0LAH, 0);
- out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
-
- out32r(PCIL0_BAR0, 0);
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
- out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- /* The ebony board is always configured as host. */
- return (1);
-}
-#endif /* defined(CONFIG_PCI) */
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/amcc/ebony/init.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o cmd_katmai.o
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
SOBJS = init.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+ {
+ "400-133","CPU: 400 PLB: 133 OPB: 66 EBC: 66",
+ { 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
+ },
+ {
+ "500-166","CPU: 500 PLB: 166 OPB: 83 EBC: 83",
+ { 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
+ },
+ {
+ "533-133","CPU: 533 PLB: 133 OPB: 66 EBC: 66",
+ { 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 }
+ },
+ {
+ "667-133","CPU: 667 PLB: 133 OPB: 66 EBC: 66",
+ { 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 }
+ },
+ {
+ "667-166","CPU: 667 PLB: 166 OPB: 83 EBC: 83",
+ { 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 }
+ },
+ {
+ "800-160","CPU: 800 PLB: 160 OPB: 53 EBC: 17",
+ { 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 }
+ },
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-#include <asm/byteorder.h>
-
-#define CONFIG_STRESS /* enable 667 MHz CPU freq selection */
-#define DEBUG
-
-static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- uchar chip;
- ulong data;
- int nbytes;
- extern char console_buffer[];
-
- char sysClock[4];
- char cpuClock[4];
- char plbClock[4];
- char pcixClock[4];
-
- if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
- }
-
- if (strcmp(argv[2], "prom0") == 0)
- chip = IIC0_BOOTPROM_ADDR;
- else
- chip = IIC0_ALT_BOOTPROM_ADDR;
-
- /* on Katmai SysClk is always 33MHz */
- strcpy(sysClock, "33");
-
- do {
-#ifdef CONFIG_STRESS
- printf("enter cpu clock frequency 400, 500, 533, 667 MHz or quit to abort\n");
-#else
- printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n");
-#endif
- nbytes = readline (" ? ");
-
- if (strcmp(console_buffer, "quit") == 0)
- return 0;
-
- if ((strcmp(console_buffer, "400") != 0) &&
- (strcmp(console_buffer, "500") != 0) &&
- (strcmp(console_buffer, "533") != 0)
-#ifdef CONFIG_STRESS
- && (strcmp(console_buffer, "667") != 0)
-#endif
- ) {
- nbytes = 0;
- }
-
- strcpy(cpuClock, console_buffer);
-
- } while (nbytes == 0);
-
- if (strcmp(cpuClock, "500") == 0)
- strcpy(plbClock, "166");
- else if (strcmp(cpuClock, "533") == 0)
- strcpy(plbClock, "133");
- else {
- do {
- if (strcmp(cpuClock, "400") == 0)
- printf("enter plb clock frequency 100, 133 MHz or quit to abort\n");
-
-#ifdef CONFIG_STRESS
- if (strcmp(cpuClock, "667") == 0)
- printf("enter plb clock frequency 133, 166 MHz or quit to abort\n");
-
-#endif
- nbytes = readline (" ? ");
-
- if (strcmp(console_buffer, "quit") == 0)
- return 0;
-
- if (strcmp(cpuClock, "400") == 0) {
- if ((strcmp(console_buffer, "100") != 0) &&
- (strcmp(console_buffer, "133") != 0))
- nbytes = 0;
- }
-#ifdef CONFIG_STRESS
- if (strcmp(cpuClock, "667") == 0) {
- if ((strcmp(console_buffer, "133") != 0) &&
- (strcmp(console_buffer, "166") != 0))
- nbytes = 0;
- }
-#endif
- strcpy(plbClock, console_buffer);
-
- } while (nbytes == 0);
- }
-
- do {
- printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n");
- nbytes = readline (" ? ");
-
- if (strcmp(console_buffer, "quit") == 0)
- return 0;
-
- if ((strcmp(console_buffer, "33") != 0) &&
- (strcmp(console_buffer, "66") != 0) &&
- (strcmp(console_buffer, "100") != 0) &&
- (strcmp(console_buffer, "133") != 0)) {
- nbytes = 0;
- }
- strcpy(pcixClock, console_buffer);
-
- } while (nbytes == 0);
-
- printf("\nsys clk = %s MHz\n", sysClock);
- printf("cpu clk = %s MHz\n", cpuClock);
- printf("plb clk = %s MHz\n", plbClock);
- printf("Pci-X clk = %s MHz\n", pcixClock);
-
- do {
- printf("\npress [y] to write I2C bootstrap \n");
- printf("or [n] to abort. \n");
- printf("Don't forget to set board switches \n");
- printf("according to your choice before re-starting \n");
- printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n");
-
- nbytes = readline (" ? ");
- if (strcmp(console_buffer, "n") == 0)
- return 0;
-
- } while (nbytes == 0);
-
- if (strcmp(sysClock, "33") == 0) {
- if ((strcmp(cpuClock, "400") == 0) &&
- (strcmp(plbClock, "100") == 0))
- data = 0x8678c206;
-
- if ((strcmp(cpuClock, "400") == 0) &&
- (strcmp(plbClock, "133") == 0))
- data = 0x8678c2c6;
-
- if ((strcmp(cpuClock, "500") == 0))
- data = 0x8778f2c6;
-
- if ((strcmp(cpuClock, "533") == 0))
- data = 0x87790252;
-#ifdef CONFIG_STRESS
- if ((strcmp(cpuClock, "667") == 0) &&
- (strcmp(plbClock, "133") == 0))
- data = 0x87794256;
-
- if ((strcmp(cpuClock, "667") == 0) &&
- (strcmp(plbClock, "166") == 0))
- data = 0x87794206;
-#endif
- }
-#ifdef DEBUG
- printf(" pin strap0 to write in i2c = %lx\n", data);
-#endif /* DEBUG */
-
- if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0)
- printf("Error writing strap0 in %s\n", argv[2]);
-
- if (strcmp(pcixClock, "33") == 0)
- data = 0x000007E1;
-
- if (strcmp(pcixClock, "66") == 0)
- data = 0x000006E1;
-
- if (strcmp(pcixClock, "100") == 0)
- data = 0x000005E1;
-
- if (strcmp(pcixClock, "133") == 0)
- data = 0x000004E1;
-
- if (strcmp(plbClock, "166") == 0)
-/* data |= 0x05950000; */ /* this set's DDR2 clock == PLB clock */
- data |= 0x05A50000; /* this set's DDR2 clock == 2 * PLB clock */
- else
- data |= 0x05A50000;
-
-#ifdef DEBUG
- printf(" pin strap1 to write in i2c = %lx\n", data);
-#endif /* DEBUG */
-
- udelay(1000);
- if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0)
- printf("Error writing strap1 in %s\n", argv[2]);
-
- return 0;
-}
-
-U_BOOT_CMD(
- bootstrap, 3, 1, do_bootstrap,
- "program the serial device strap",
- "wrclk [prom0|prom1] - program the serial device strap"
-);
/*
- * (C) Copyright 2007-2008
+ * (C) Copyright 2007-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
}
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller * hose )
-{
- unsigned long strap;
-
- /*-------------------------------------------------------------------+
- * The katmai board is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *-------------------------------------------------------------------*/
- mfsdr(SDR0_SDSTP1, strap);
- if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
- printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
- return 0;
- }
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*-------------------------------------------------------------------+
- * Disable everything
- *-------------------------------------------------------------------*/
- out32r( PCIL0_PIM0SA, 0 ); /* disable */
- out32r( PCIL0_PIM1SA, 0 ); /* disable */
- out32r( PCIL0_PIM2SA, 0 ); /* disable */
- out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
- /*-------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
- * strapping options to not support sizes such as 128/256 MB.
- *-------------------------------------------------------------------*/
- out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIL0_PIM0LAH, 0 );
- out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
- out32r( PCIL0_BAR0, 0 );
-
- /*-------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *-------------------------------------------------------------------*/
- out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
#if defined(CONFIG_PCI)
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- ************************************************************************/
-int is_pci_host(struct pci_controller *hose)
-{
- /* The katmai board is always configured as host. */
- return 1;
-}
-
-static int katmai_pcie_card_present(int port)
+int board_pcie_card_present(int port)
{
u32 val;
return 0;
}
}
-
-static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
-
-void pcie_setup_hoses(int busno)
-{
- struct pci_controller *hose;
- int i, bus;
- int ret = 0;
- char *env;
- unsigned int delay;
-
- /*
- * assume we're called after the PCIX hose is initialized, which takes
- * bus ID 0 and therefore start numbering PCIe's from 1.
- */
- bus = busno;
- for (i = 0; i <= 2; i++) {
- /* Check for katmai card presence */
- if (!katmai_pcie_card_present(i))
- continue;
-
- if (is_end_point(i))
- ret = ppc4xx_init_pcie_endport(i);
- else
- ret = ppc4xx_init_pcie_rootport(i);
- if (ret == -ENODEV)
- continue;
- if (ret) {
- printf("PCIE%d: initialization as %s failed\n", i,
- is_end_point(i) ? "endpoint" : "root-complex");
- continue;
- }
-
- hose = &pcie_hose[i];
- hose->first_busno = bus;
- hose->last_busno = bus;
- hose->current_busno = bus;
-
- /* setup mem resource */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
- CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
- CONFIG_SYS_PCIE_MEMSIZE,
- PCI_REGION_MEM);
- hose->region_count = 1;
- pci_register_hose(hose);
-
- if (is_end_point(i)) {
- ppc4xx_setup_pcie_endpoint(hose, i);
- /*
- * Reson for no scanning is endpoint can not generate
- * upstream configuration accesses.
- */
- } else {
- ppc4xx_setup_pcie_rootpoint(hose, i);
- env = getenv ("pciscandelay");
- if (env != NULL) {
- delay = simple_strtoul(env, NULL, 10);
- if (delay > 5)
- printf("Warning, expect noticable delay before "
- "PCIe scan due to 'pciscandelay' value!\n");
- mdelay(delay * 1000);
- }
-
- /*
- * Config access can only go down stream
- */
- hose->last_busno = pci_hose_scan(hose);
- bus = hose->last_busno + 1;
- }
- }
-}
#endif /* defined(CONFIG_PCI) */
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return (ctrlc());
-}
-#endif
-
int board_eth_init(bd_t *bis)
{
cpu_eth_init(bis);
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
- board/amcc/katmai/init.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
+
+ifdef CONFIG_NAND_U_BOOT
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+endif
return 2;
}
-static int board_pcie_count(void)
+/*
+ * Override the weak default implementation and return the
+ * last PCIe slot number (max number - 1).
+ */
+int board_pcie_last(void)
{
/*
* 405EXr only has one EMAC interface, 405EX has two
*/
if (is_405exr())
- return 1;
+ return 1 - 1;
else
- return 2;
+ return 2 - 1;
}
int checkboard (void)
return (0);
}
-
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller * hose )
-{
- return 0;
-}
-#endif /* defined(CONFIG_PCI) */
-
-#ifdef CONFIG_PCI
-static struct pci_controller pcie_hose[2] = {{0},{0}};
-
-void pcie_setup_hoses(int busno)
-{
- struct pci_controller *hose;
- int i, bus;
- int ret = 0;
- bus = busno;
- char *env;
- unsigned int delay;
-
- for (i = 0; i < board_pcie_count(); i++) {
-
- if (is_end_point(i))
- ret = ppc4xx_init_pcie_endport(i);
- else
- ret = ppc4xx_init_pcie_rootport(i);
- if (ret == -ENODEV)
- continue;
- if (ret) {
- printf("PCIE%d: initialization as %s failed\n", i,
- is_end_point(i) ? "endpoint" : "root-complex");
- continue;
- }
-
- hose = &pcie_hose[i];
- hose->first_busno = bus;
- hose->last_busno = bus;
- hose->current_busno = bus;
-
- /* setup mem resource */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
- CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
- CONFIG_SYS_PCIE_MEMSIZE,
- PCI_REGION_MEM);
- hose->region_count = 1;
- pci_register_hose(hose);
-
- if (is_end_point(i)) {
- ppc4xx_setup_pcie_endpoint(hose, i);
- /*
- * Reson for no scanning is endpoint can not generate
- * upstream configuration accesses.
- */
- } else {
- ppc4xx_setup_pcie_rootpoint(hose, i);
- env = getenv ("pciscandelay");
- if (env != NULL) {
- delay = simple_strtoul(env, NULL, 10);
- if (delay > 5)
- printf("Warning, expect noticable delay before "
- "PCIe scan due to 'pciscandelay' value!\n");
- mdelay(delay * 1000);
- }
-
- /*
- * Config access can only go down stream
- */
- hose->last_busno = pci_hose_scan(hose);
- bus = hose->last_busno + 1;
- }
- }
-}
-#endif
-
-#if defined(CONFIG_POST)
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return 0; /* No hotkeys supported */
-}
-#endif /* CONFIG_POST */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
-/* To compile successfully, uncomment the following section.
- * To go in ram, remove the section.
- * Added by SunHe.
- */
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
}
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init( struct pci_controller *hose )
-{
- unsigned long strap;
-
- /*--------------------------------------------------------------------------+
- * The luan board is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *--------------------------------------------------------------------------*/
- mfsdr(SDR0_SDSTP1, strap);
- if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
- printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
-
- return 0;
- }
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0SA, 0 ); /* disable */
- out32r( PCIL0_PIM1SA, 0 ); /* disable */
- out32r( PCIL0_PIM2SA, 0 ); /* disable */
- out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIL0_PIM0LAH, 0 );
- out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
- out32r( PCIL0_BAR0, 0 );
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-
/*************************************************************************
* hw_watchdog_reset
*
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
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- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
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- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/amcc/luan/init.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
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- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
return (0);
}
-
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller * hose )
-{
- return 0;
-}
-#endif /* defined(CONFIG_PCI) */
-
-#ifdef CONFIG_PCI
-static struct pci_controller pcie_hose[2] = {{0},{0}};
-
-void pcie_setup_hoses(int busno)
-{
- struct pci_controller *hose;
- int i, bus;
- int ret = 0;
- bus = busno;
- char *env;
- unsigned int delay;
-
- for (i = 0; i < 2; i++) {
-
- if (is_end_point(i))
- ret = ppc4xx_init_pcie_endport(i);
- else
- ret = ppc4xx_init_pcie_rootport(i);
- if (ret == -ENODEV)
- continue;
- if (ret) {
- printf("PCIE%d: initialization as %s failed\n", i,
- is_end_point(i) ? "endpoint" : "root-complex");
- continue;
- }
-
- hose = &pcie_hose[i];
- hose->first_busno = bus;
- hose->last_busno = bus;
- hose->current_busno = bus;
-
- /* setup mem resource */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
- CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
- CONFIG_SYS_PCIE_MEMSIZE,
- PCI_REGION_MEM);
- hose->region_count = 1;
- pci_register_hose(hose);
-
- if (is_end_point(i)) {
- ppc4xx_setup_pcie_endpoint(hose, i);
- /*
- * Reson for no scanning is endpoint can not generate
- * upstream configuration accesses.
- */
- } else {
- ppc4xx_setup_pcie_rootpoint(hose, i);
- env = getenv ("pciscandelay");
- if (env != NULL) {
- delay = simple_strtoul(env, NULL, 10);
- if (delay > 5)
- printf("Warning, expect noticable delay before "
- "PCIe scan due to 'pciscandelay' value!\n");
- mdelay(delay * 1000);
- }
-
- /*
- * Config access can only go down stream
- */
- hose->last_busno = pci_hose_scan(hose);
- bus = hose->last_busno + 1;
- }
- }
-}
-#endif
-
-#if defined(CONFIG_POST)
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return 0; /* No hotkeys supported */
-}
-#endif /* CONFIG_POST */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
-/* To compile successfully, uncomment the following section.
- * To go in ram, remove the section.
- * Added by SunHe.
- */
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller * hose )
-{
- unsigned long strap;
-
- /*--------------------------------------------------------------------------+
- * The ocotea board is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *--------------------------------------------------------------------------*/
- mfsdr(SDR0_SDSTP1, strap);
- if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
- printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
- return 0;
- }
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0SA, 0 ); /* disable */
- out32r( PCIL0_PIM1SA, 0 ); /* disable */
- out32r( PCIL0_PIM2SA, 0 ); /* disable */
- out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIL0_PIM0LAH, 0 );
- out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
- out32r( PCIL0_BAR0, 0 );
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- /* The ocotea board is always configured as host. */
- return(1);
-}
-#endif /* defined(CONFIG_PCI) */
-
-
void fpga_init(void)
{
unsigned long group;
return;
}
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
-
- return (ctrlc());
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/amcc/ocotea/init.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/amcc/redwood/init.o (.text)
-
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
+
+ifdef CONFIG_NAND_U_BOOT
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+endif
/*
* Assign interrupts to PCI devices.
*/
-void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
}
#endif
-/*
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- */
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller *hose)
-{
- unsigned long addr;
-
- /*
- * Set priority for all PLB3 devices to 0.
- * Set PLB3 arbiter to fair mode.
- */
- mfsdr(SD0_AMP1, addr);
- mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB3_ACR);
- mtdcr(PLB3_ACR, addr | 0x80000000);
-
- /*
- * Set priority for all PLB4 devices to 0.
- */
- mfsdr(SD0_AMP0, addr);
- mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
- mtdcr(PLB4_ACR, addr);
-
- /*
- * Set Nebula PLB4 arbiter to fair mode.
- */
- /* Segment0 */
- addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
- addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
- addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
- addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
- mtdcr(PLB0_ACR, addr);
-
- /* Segment1 */
- addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
- addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
- addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
- addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
- mtdcr(PLB1_ACR, addr);
-
-#ifdef CONFIG_PCI_PNP
- hose->fixup_irq = sequoia_pci_fixup_irq;
-#endif
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*
- * Set up Direct MMIO registers
- */
- /*
- * PowerPC440EPX PCI Master configuration.
- * Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0xA0000000-0xDFFFFFFF
- * ==> PCI address 0xA0000000-0xDFFFFFFF
- * Use byte reversed out routines to handle endianess.
- * Make this region non-prefetchable.
- */
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
- /* - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
- /* and enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
- /* - disabled b4 setting */
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
- /* and enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*
- * Set up Configuration registers
- */
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
-void pci_master_init(struct pci_controller *hose)
-{
- unsigned short temp_short;
-
- /*
- * Write the PowerPC440 EP PCI Configuration regs.
- * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- * Enable PowerPC440 EP to act as a PCI memory target (PTM).
- */
- pci_read_config_word(0, PCI_COMMAND, &temp_short);
- pci_write_config_word(0, PCI_COMMAND,
- temp_short | PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
-
-/*
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- */
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- /* Cactus is always configured as host. */
- return (1);
-}
-#endif /* defined(CONFIG_PCI) */
-
-#if defined(CONFIG_POST)
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return 0; /* No hotkeys supported */
-}
-#endif /* CONFIG_POST */
-
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
/*
* On NAND-booting sequoia, we need to patch the chips select numbers
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
-
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
return (0);
}
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller * hose )
-{
- unsigned long strap;
-
- /*--------------------------------------------------------------------------+
- * The ocotea board is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *--------------------------------------------------------------------------*/
- mfsdr(SDR0_SDSTP1, strap);
- if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
- printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
- return 0;
- }
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0SA, 0 ); /* disable */
- out32r( PCIL0_PIM1SA, 0 ); /* disable */
- out32r( PCIL0_PIM2SA, 0 ); /* disable */
- out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIL0_PIM0LAH, 0 );
- out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
- out32r( PCIL0_BAR0, 0 );
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- /* The ocotea board is always configured as host. */
- return(1);
-}
-#endif /* defined(CONFIG_PCI) */
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return (ctrlc());
-}
-#endif
-
int board_eth_init(bd_t *bis)
{
cpu_eth_init(bis);
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
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- .rela.bss : { *(.rela.bss) }
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- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/amcc/taishan/init.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/amcc/yosemite/init.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024); /* return bytes */
}
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller *hose)
-{
- unsigned long addr;
-
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB3 devices to 0.
- | Set PLB3 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
- mfsdr(SD0_AMP1, addr);
- mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB3_ACR);
- mtdcr(PLB3_ACR, addr | 0x80000000);
-
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB4 devices to 0.
- +-------------------------------------------------------------------------*/
- mfsdr(SD0_AMP0, addr);
- mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
- mtdcr(PLB4_ACR, addr);
-
- /*-------------------------------------------------------------------------+
- | Set Nebula PLB4 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
- /* Segment0 */
- addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
- addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
- addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
- addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
- mtdcr(PLB0_ACR, addr);
-
- /* Segment1 */
- addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
- addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
- addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
- addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
- mtdcr(PLB1_ACR, addr);
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*--------------------------------------------------------------------------+
- * Set up Direct MMIO registers
- *--------------------------------------------------------------------------*/
- /*--------------------------------------------------------------------------+
- | PowerPC440 EP PCI Master configuration.
- | Map one 1Gig range of PLB/processor addresses to PCI memory space.
- | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
- | Use byte reversed out routines to handle endianess.
- | Make this region non-prefetchable.
- +--------------------------------------------------------------------------*/
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*--------------------------------------------------------------------------+
- * Set up Configuration registers
- *--------------------------------------------------------------------------*/
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*************************************************************************
- * pci_master_init
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
-void pci_master_init(struct pci_controller *hose)
-{
- unsigned short temp_short;
-
- /*--------------------------------------------------------------------------+
- | Write the PowerPC440 EP PCI Configuration regs.
- | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- | Enable PowerPC440 EP to act as a PCI memory target (PTM).
- +--------------------------------------------------------------------------*/
- pci_read_config_word(0, PCI_COMMAND, &temp_short);
- pci_write_config_word(0, PCI_COMMAND,
- temp_short | PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
-
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- /* Bamboo is always configured as host. */
- return (1);
-}
-#endif /* defined(CONFIG_PCI) */
-
/*************************************************************************
* hw_watchdog_reset
*
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/amcc/yucca/init.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
return default_val;
}
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller * hose )
-{
- unsigned long strap;
-
- /*-------------------------------------------------------------------+
- * The yucca board is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *-------------------------------------------------------------------*/
- mfsdr(SDR0_SDSTP1, strap);
- if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
- printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
- return 0;
- }
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*-------------------------------------------------------------------+
- * Disable everything
- *-------------------------------------------------------------------*/
- out32r( PCIL0_PIM0SA, 0 ); /* disable */
- out32r( PCIL0_PIM1SA, 0 ); /* disable */
- out32r( PCIL0_PIM2SA, 0 ); /* disable */
- out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
- /*-------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
- * strapping options to not support sizes such as 128/256 MB.
- *-------------------------------------------------------------------*/
- out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIL0_PIM0LAH, 0 );
- out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
- out32r( PCIL0_BAR0, 0 );
-
- /*-------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *-------------------------------------------------------------------*/
- out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-#if defined(CONFIG_PCI)
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- ************************************************************************/
-int is_pci_host(struct pci_controller *hose)
-{
- /* The yucca board is always configured as host. */
- return 1;
-}
-
-static int yucca_pcie_card_present(int port)
+int board_pcie_card_present(int port)
{
u16 reg;
}
}
-/*
- * For the given slot, set rootpoint mode, send power to the slot,
- * turn on the green LED and turn off the yellow LED, enable the clock
- * and turn off reset.
- */
-void yucca_setup_pcie_fpga_rootpoint(int port)
-{
- u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
-
- switch(port) {
- case 0:
- rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
- endpoint = 0;
- power = FPGA_REG1A_PE0_PWRON;
- green_led = FPGA_REG1A_PE0_GLED;
- clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
- yellow_led = FPGA_REG1A_PE0_YLED;
- reset_off = FPGA_REG1C_PE0_PERST;
- break;
- case 1:
- rootpoint = 0;
- endpoint = FPGA_REG1C_PE1_ENDPOINT;
- power = FPGA_REG1A_PE1_PWRON;
- green_led = FPGA_REG1A_PE1_GLED;
- clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
- yellow_led = FPGA_REG1A_PE1_YLED;
- reset_off = FPGA_REG1C_PE1_PERST;
- break;
- case 2:
- rootpoint = 0;
- endpoint = FPGA_REG1C_PE2_ENDPOINT;
- power = FPGA_REG1A_PE2_PWRON;
- green_led = FPGA_REG1A_PE2_GLED;
- clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
- yellow_led = FPGA_REG1A_PE2_YLED;
- reset_off = FPGA_REG1C_PE2_PERST;
- break;
-
- default:
- return;
- }
-
- out_be16((u16 *)FPGA_REG1A,
- ~(power | clock | green_led) &
- (yellow_led | in_be16((u16 *)FPGA_REG1A)));
-
- out_be16((u16 *)FPGA_REG1C,
- ~(endpoint | reset_off) &
- (rootpoint | in_be16((u16 *)FPGA_REG1C)));
- /*
- * Leave device in reset for a while after powering on the
- * slot to give it a chance to initialize.
- */
- udelay(250 * 1000);
-
- out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C));
-}
/*
* For the given slot, set endpoint mode, send power to the slot,
- * turn on the green LED and turn off the yellow LED, enable the clock
- * .In end point mode reset bit is read only.
+ * turn on the green LED and turn off the yellow LED, enable the
+ * clock. In end point mode reset bit is read only.
*/
-void yucca_setup_pcie_fpga_endpoint(int port)
+void board_pcie_setup_port(int port, int rootpoint)
{
- u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
+ u16 power, clock, green_led, yellow_led,
+ reset_off, rp, ep;
- switch(port) {
+ switch (port) {
case 0:
- rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
- endpoint = 0;
- power = FPGA_REG1A_PE0_PWRON;
- green_led = FPGA_REG1A_PE0_GLED;
- clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
- yellow_led = FPGA_REG1A_PE0_YLED;
- reset_off = FPGA_REG1C_PE0_PERST;
+ rp = FPGA_REG1C_PE0_ROOTPOINT;
+ ep = 0;
break;
case 1:
- rootpoint = 0;
- endpoint = FPGA_REG1C_PE1_ENDPOINT;
- power = FPGA_REG1A_PE1_PWRON;
- green_led = FPGA_REG1A_PE1_GLED;
- clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
- yellow_led = FPGA_REG1A_PE1_YLED;
- reset_off = FPGA_REG1C_PE1_PERST;
+ rp = 0;
+ ep = FPGA_REG1C_PE1_ENDPOINT;
break;
case 2:
- rootpoint = 0;
- endpoint = FPGA_REG1C_PE2_ENDPOINT;
- power = FPGA_REG1A_PE2_PWRON;
- green_led = FPGA_REG1A_PE2_GLED;
- clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
- yellow_led = FPGA_REG1A_PE2_YLED;
- reset_off = FPGA_REG1C_PE2_PERST;
+ rp = 0;
+ ep = FPGA_REG1C_PE2_ENDPOINT;
break;
default:
return;
}
- out_be16((u16 *)FPGA_REG1A,
- ~(power | clock | green_led) &
- (yellow_led | in_be16((u16 *)FPGA_REG1A)));
-
- out_be16((u16 *)FPGA_REG1C,
- ~(rootpoint | reset_off) &
- (endpoint | in_be16((u16 *)FPGA_REG1C)));
-}
+ power = FPGA_REG1A_PWRON_ENCODE(port);
+ green_led = FPGA_REG1A_GLED_ENCODE(port);
+ clock = FPGA_REG1A_REFCLK_ENCODE(port);
+ yellow_led = FPGA_REG1A_YLED_ENCODE(port);
+ reset_off = FPGA_REG1C_PERST_ENCODE(port);
-static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
+ out_be16((u16 *)FPGA_REG1A, ~(power | clock | green_led) &
+ (yellow_led | in_be16((u16 *)FPGA_REG1A)));
-void pcie_setup_hoses(int busno)
-{
- struct pci_controller *hose;
- int i, bus;
- int ret = 0;
- char *env;
- unsigned int delay;
+ out_be16((u16 *)FPGA_REG1C, ~(ep | reset_off) &
+ (rp | in_be16((u16 *)FPGA_REG1C)));
- /*
- * assume we're called after the PCIX hose is initialized, which takes
- * bus ID 0 and therefore start numbering PCIe's from 1.
- */
- bus = busno;
- for (i = 0; i <= 2; i++) {
- /* Check for yucca card presence */
- if (!yucca_pcie_card_present(i))
- continue;
-
- if (is_end_point(i)) {
- yucca_setup_pcie_fpga_endpoint(i);
- ret = ppc4xx_init_pcie_endport(i);
- } else {
- yucca_setup_pcie_fpga_rootpoint(i);
- ret = ppc4xx_init_pcie_rootport(i);
- }
- if (ret == -ENODEV)
- continue;
- if (ret) {
- printf("PCIE%d: initialization as %s failed\n", i,
- is_end_point(i) ? "endpoint" : "root-complex");
- continue;
- }
-
- hose = &pcie_hose[i];
- hose->first_busno = bus;
- hose->last_busno = bus;
- hose->current_busno = bus;
-
- /* setup mem resource */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
- CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
- CONFIG_SYS_PCIE_MEMSIZE,
- PCI_REGION_MEM);
- hose->region_count = 1;
- pci_register_hose(hose);
-
- if (is_end_point(i)) {
- ppc4xx_setup_pcie_endpoint(hose, i);
- /*
- * Reson for no scanning is endpoint can not generate
- * upstream configuration accesses.
- */
- } else {
- ppc4xx_setup_pcie_rootpoint(hose, i);
- env = getenv("pciscandelay");
- if (env != NULL) {
- delay = simple_strtoul(env, NULL, 10);
- if (delay > 5)
- printf("Warning, expect noticable delay before "
- "PCIe scan due to 'pciscandelay' value!\n");
- mdelay(delay * 1000);
- }
+ if (rootpoint) {
+ /*
+ * Leave device in reset for a while after powering on the
+ * slot to give it a chance to initialize.
+ */
+ udelay(250 * 1000);
- /*
- * Config access can only go down stream
- */
- hose->last_busno = pci_hose_scan(hose);
- bus = hose->last_busno + 1;
- }
+ out_be16((u16 *)FPGA_REG1C,
+ reset_off | in_be16((u16 *)FPGA_REG1C));
}
}
#endif /* defined(CONFIG_PCI) */
return;
}
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return (ctrlc());
-}
-#endif
-
/*---------------------------------------------------------------------------+
| onboard_pci_arbiter_selected => from EPLD
+---------------------------------------------------------------------------*/
# like it's not in RAM. This is a bit of voodoo to allow it to be
# run from RAM instead of Flash.
TEXT_BASE = 0x08000000
+
+# Use board specific linker script
+LDSCRIPT := $(SRCTREE)/board/amirix/ap1000/u-boot.lds
* MA 02111-1307 USA
*/
#include <common.h>
+#include <netdev.h>
#include <asm/arch/omap2420.h>
#include <asm/io.h>
#include <asm/arch/bits.h>
********************************************************/
int misc_init_r(void)
{
- ether_init(); /* better done here so timers are init'ed */
return (0);
}
}
/*******************************************************************
- * Routine:ether_init
+ * Routine:board_eth_init
* Description: take the Ethernet controller out of reset and wait
* for the EEPROM load to complete.
******************************************************************/
-void ether_init(void)
+int board_eth_init(bd_t *bis)
{
-#ifdef CONFIG_DRIVER_LAN91C96
+ int rc = 0;
+#ifdef CONFIG_LAN91C96
int cnt = 20;
__raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */
mask_config_reg(ETH_CONTROL_REG, 0x01);
udelay(1000);
-
+ rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
eth_reset_err_out:
- return;
#endif
+ return rc;
}
/**********************************************
}
/* delay usec useconds */
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
ulong tmo, tmp;
*/
#include <common.h>
+#include <netdev.h>
#include <SA-1100.h>
DECLARE_GLOBAL_DATA_PTR;
return (0);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_LAN91C96
+ rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+ return rc;
+}
+#endif
}
#ifdef CONFIG_DRIVER_DM9000
- int board_eth_init(bd_t *bis)
- {
+int board_eth_init(bd_t *bis)
+{
return dm9000_initialize(bis);
- }
- #endif
+}
+#endif
+
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
static struct pci_controller pcie1_hose;
#endif
-int first_free_busno=0;
-
-void
-pci_init_board(void)
+void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct fsl_pci_info pci_info[3];
+ u32 devdisr, pordevsr, io_sel;
+ u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+ int first_free_busno = 0;
+ int num = 0;
+
+ int pcie_ep, pcie_configured;
- uint devdisr = gur->devdisr;
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ porpllsr = in_be32(&gur->porpllsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
- devdisr, io_sel, host_agent);
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
/* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
- gur->clkocr |= MPC85xx_ATUM_CLKOCR;
+ setbits_be32(&gur->clkocr, MPC85xx_ATUM_CLKOCR);
if (io_sel & 1) {
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
}
#ifdef CONFIG_PCIE1
- {
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- struct pci_controller *hose = &pcie1_hose;
- int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
- struct pci_region *r = hose->regions;
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE1 connected to slot as %s (base address %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
/* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BASE,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
-#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE2,
+ pci_set_region(&pcie1_hose.regions[0],
+ CONFIG_SYS_PCIE1_MEM_BUS2,
CONFIG_SYS_PCIE1_MEM_PHYS2,
CONFIG_SYS_PCIE1_MEM_SIZE2,
PCI_REGION_MEM);
-#endif
- hose->region_count = r - hose->regions;
- hose->first_busno=first_free_busno;
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno=hose->last_busno+1;
- printf(" PCIE1 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ pcie1_hose.region_count = 1;
+#endif
+ printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
} else {
printf (" PCIE1: disabled\n");
}
- }
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
#ifdef CONFIG_PCI1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- struct pci_controller *hose = &pci1_hose;
- struct pci_region *r = hose->regions;
-
- uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);
- uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
- uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
- uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
- uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
+ pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
+ pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
+ pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+ pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
- printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
+ SET_STD_PCI_INFO(pci_info[num], 1);
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+ printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333000) ? "33" :
(pci_speed == 66666000) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
pci_agent ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter",
- (uint)pci
- );
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
+ pci_info[num].regs);
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BASE,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
- hose->region_count = r - hose->regions;
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- first_free_busno=hose->last_busno+1;
- printf ("PCI1 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pci1_hose, first_free_busno);
} else {
- printf (" PCI1: disabled\n");
+ printf (" PCI: disabled\n");
}
-}
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
#ifdef CONFIG_PCI2
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
- struct pci_controller *hose = &pci2_hose;
- struct pci_region *r = hose->regions;
-
if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
- pci_set_region(r++,
- CONFIG_SYS_PCI2_MEM_BASE,
- CONFIG_SYS_PCI2_MEM_PHYS,
- CONFIG_SYS_PCI2_MEM_SIZE,
- PCI_REGION_MEM);
+ SET_STD_PCI_INFO(pci_info[num], 2);
+ pci_agent = fsl_setup_hose(&pci2_hose, pci_info[num].regs);
- pci_set_region(r++,
- CONFIG_SYS_PCI2_IO_BASE,
- CONFIG_SYS_PCI2_IO_PHYS,
- CONFIG_SYS_PCI2_IO_SIZE,
- PCI_REGION_IO);
- hose->region_count = r - hose->regions;
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- first_free_busno=hose->last_busno+1;
- printf ("PCI2 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ puts (" PCI2\n");
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pci1_hose, first_free_busno);
} else {
printf (" PCI2: disabled\n");
}
-}
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCI2;
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
#endif
}
#include <linux/types.h>
#include <stdio_dev.h>
-int gunzip(void *, int, unsigned char *, unsigned long *);
-
#define DMA_SIZE16 2
#include <asm/mach-common/bits/ppi.h>
#include <linux/types.h>
#include <stdio_dev.h>
-int gunzip(void *, int, unsigned char *, unsigned long *);
-
#define DMA_SIZE16 2
#include <asm/mach-common/bits/ppi.h>
#include <linux/types.h>
#include <stdio_dev.h>
-int gunzip(void *, int, unsigned char *, unsigned long *);
-
#define DMA_SIZE16 2
#include <asm/mach-common/bits/eppi.h>
#include <linux/types.h>
#include <stdio_dev.h>
-int gunzip(void *, int, unsigned char *, unsigned long *);
-
#ifdef CONFIG_VIDEO
#define DMA_SIZE16 2
if (ret < 0)
printf("ft_blob_update(): cannot set /model property err:%s\n",
fdt_strerror(ret));
-
- ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
-
- if (ret < 0) {
- printf("ft_blob_update(): cannot set /memory/reg "
- "property err:%s\n", fdt_strerror(ret));
- }
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
}
-#ifdef CONFIG_POST
-int post_hotkeys_pressed(void)
-{
- return 0;
-}
-#endif /* CONFIG_POST */
-
-
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
void post_word_store(ulong a)
{
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/cray/L1/init.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- drivers/net/4xx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/*. = env_offset;*/
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/csb272/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- drivers/net/4xx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
-
- lib_ppc/extable.o (.text)
- lib_ppc/board.o (.text)
- lib_generic/zlib.o (.text)
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/csb472/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- drivers/net/4xx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
-
- lib_ppc/extable.o (.text)
- lib_ppc/board.o (.text)
- lib_generic/zlib.o (.text)
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
*/
#include <common.h>
+#include <netdev.h>
#include <asm/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
return (0);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_LAN91C96
+ rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+ return rc;
+}
+#endif
/* ------------------------------------------------------------------------- */
-/* Prototypes */
-int gunzip(void *, int, unsigned char *, unsigned long *);
-
int board_early_init_f (void)
{
out32(GPIO0_OR, CONFIG_SYS_NAND0_CE); /* set initial outputs */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- drivers/net/4xx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
- . = 0xFFFF8000;
- .ppcenv :
- {
- common/env_embedded.o(.ppcenv);
- }
-
- _end = . ;
- PROVIDE (end = .);
-}
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
/*
* Miscelaneous DaVinci functions.
*
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
* Copyright (C) 2004 Texas Instruments.
#include <i2c.h>
#include <net.h>
#include <asm/arch/hardware.h>
-
+#include <asm/io.h>
+#include "misc.h"
DECLARE_GLOBAL_DATA_PTR;
}
#endif /* DAVINCI_EMAC */
+
+/*
+ * Change the setting of a pin multiplexer field.
+ *
+ * Takes an array of pinmux settings similar to:
+ *
+ * struct pinmux_config uart_pins[] = {
+ * { &davinci_syscfg_regs->pinmux[8], 2, 7 },
+ * { &davinci_syscfg_regs->pinmux[9], 2, 0 }
+ * };
+ *
+ * Stepping through the array, each pinmux[n] register has the given value
+ * set in the pin mux field specified.
+ *
+ * The number of pins in the array must be passed (ARRAY_SIZE can provide
+ * this value conveniently).
+ *
+ * Returns 0 if all field numbers and values are in the correct range,
+ * else returns -1.
+ */
+int davinci_configure_pin_mux(const struct pinmux_config *pins,
+ const int n_pins)
+{
+ int i;
+
+ /* check for invalid pinmux values */
+ for (i = 0; i < n_pins; i++) {
+ if (pins[i].field >= PIN_MUX_NUM_FIELDS ||
+ (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0)
+ return -1;
+ }
+
+ /* configure the pinmuxes */
+ for (i = 0; i < n_pins; i++) {
+ const int offset = pins[i].field * PIN_MUX_FIELD_SIZE;
+ const unsigned int value = pins[i].value << offset;
+ const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
+ const dv_reg *mux = pins[i].mux;
+
+ writel(value | (readl(mux) & (~mask)), mux);
+ }
+
+ return 0;
+}
+
+/*
+ * Configure multiple pinmux resources.
+ *
+ * Takes an pinmux_resource array of pinmux_config and pin counts:
+ *
+ * const struct pinmux_resource pinmuxes[] = {
+ * PINMUX_ITEM(uart_pins),
+ * PINMUX_ITEM(i2c_pins),
+ * };
+ *
+ * The number of items in the array must be passed (ARRAY_SIZE can provide
+ * this value conveniently).
+ *
+ * Each item entry is configured in the defined order. If configuration
+ * of any item fails, -1 is returned and none of the following items are
+ * configured. On success, 0 is returned.
+ */
+int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
+ const int n_items)
+{
+ int i;
+
+ for (i = 0; i < n_items; i++) {
+ if (davinci_configure_pin_mux(item[i].pins,
+ item[i].n_pins) != 0)
+ return -1;
+ }
+
+ return 0;
+}
#ifndef __MISC_H
#define __MISC_H
+/* pin muxer definitions */
+#define PIN_MUX_NUM_FIELDS 8 /* Per register */
+#define PIN_MUX_FIELD_SIZE 4 /* n in bits */
+#define PIN_MUX_FIELD_MASK ((1 << PIN_MUX_FIELD_SIZE) - 1)
+
+/* pin definition */
+struct pinmux_config {
+ dv_reg *mux; /* Address of mux register */
+ unsigned char value; /* Value to set in field */
+ unsigned char field; /* field number */
+};
+
+/* pin table definition */
+struct pinmux_resource {
+ const struct pinmux_config *pins;
+ const int n_pins;
+};
+
+#define PINMUX_ITEM(item) { \
+ .pins = item, \
+ .n_pins = ARRAY_SIZE(item) \
+ }
int dvevm_read_mac_address(uint8_t *buf);
void dv_configure_mac_address(uint8_t *rom_enetaddr);
+int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
+int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
+ int n_items);
#endif /* __MISC_H */
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := da830evm.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# Texas Instruments DA8xx EVM board (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# DA8xx EVM has 1 bank of 64 MB SDRAM (2 16Meg x16 chips).
+# Physical Address:
+# C000'0000 to C400'0000
+#
+# Linux-Kernel is expected to be at C000'8000, entry C000'8000
+# (mem base + reserved)
+#
+# we load ourself to C108 '0000
+
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+TEXT_BASE = 0xC1080000
--- /dev/null
+/*
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ *
+ * Base on code from TI. Original Notices follow:
+ *
+ * (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
+ *
+ * Modified for DA8xx EVM.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * -----------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include "../common/misc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define pinmux &davinci_syscfg_regs->pinmux
+
+#ifdef CONFIG_SPI_FLASH
+/* SPI0 pin muxer settings */
+const struct pinmux_config spi0_pins[] = {
+ { pinmux[7], 1, 3 },
+ { pinmux[7], 1, 4 },
+ { pinmux[7], 1, 5 },
+ { pinmux[7], 1, 6 },
+ { pinmux[7], 1, 7 }
+};
+#endif
+
+/* UART pin muxer settings */
+const struct pinmux_config uart_pins[] = {
+ { pinmux[8], 2, 7 },
+ { pinmux[9], 2, 0 }
+};
+
+/* I2C pin muxer settings */
+const struct pinmux_config i2c_pins[] = {
+ { pinmux[9], 2, 3 },
+ { pinmux[9], 2, 4 }
+};
+
+/* USB0_DRVVBUS pin muxer settings */
+const struct pinmux_config usb_pins[] = {
+ { pinmux[9], 1, 1 }
+};
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+ /*
+ * Mask all IRQs by clearing the global enable and setting
+ * the enable clear for all the 90 interrupts.
+ */
+
+ writel(0, &davinci_aintc_regs->ger);
+
+ writel(0, &davinci_aintc_regs->hier);
+
+ writel(0xffffffff, &davinci_aintc_regs->ecr1);
+ writel(0xffffffff, &davinci_aintc_regs->ecr2);
+ writel(0xffffffff, &davinci_aintc_regs->ecr3);
+#endif
+
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /*
+ * Power on required peripherals
+ * ARM does not have access by default to PSC0 and PSC1
+ * assuming here that the DSP bootloader has set the IOPU
+ * such that PSC access is available to ARM
+ */
+ lpsc_on(DAVINCI_LPSC_AEMIF); /* NAND, NOR */
+ lpsc_on(DAVINCI_LPSC_SPI0); /* Serial Flash */
+ lpsc_on(DAVINCI_LPSC_EMAC); /* image download */
+ lpsc_on(DAVINCI_LPSC_UART2); /* console */
+ lpsc_on(DAVINCI_LPSC_GPIO);
+
+ /* setup the SUSPSRC for ARM to control emulation suspend */
+ writel(readl(&davinci_syscfg_regs->suspsrc) &
+ ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+ DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+ DAVINCI_SYSCFG_SUSPSRC_UART2),
+ &davinci_syscfg_regs->suspsrc);
+
+#ifdef CONFIG_SPI_FLASH
+ if (davinci_configure_pin_mux(spi0_pins, ARRAY_SIZE(spi0_pins)) != 0)
+ return 1;
+#endif
+
+ if (davinci_configure_pin_mux(uart_pins, ARRAY_SIZE(uart_pins)) != 0)
+ return 1;
+
+ if (davinci_configure_pin_mux(i2c_pins, ARRAY_SIZE(i2c_pins)) != 0)
+ return 1;
+
+ if (davinci_configure_pin_mux(usb_pins, ARRAY_SIZE(usb_pins)) != 0)
+ return 1;
+
+ /* enable the console UART */
+ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+ DAVINCI_UART_PWREMU_MGMT_UTRST),
+ &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+ return(0);
+}
#include <common.h>
#include <asm/io.h>
+#include <nand.h>
+#include <asm/arch/nand_defs.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+#ifdef CONFIG_NAND_DAVINCI
+int board_nand_init(struct nand_chip *nand)
+{
+ davinci_nand_init(nand);
+
+ return 0;
+}
+#endif
#
TEXT_BASE = 0x38040000
+CFLAGS_dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing
+PLATFORM_RELFLAGS += -fvisibility=hidden
+PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
+PLATFORM_LDFLAGS += -pic --emit-relocs -Bsymbolic -Bsymbolic-functions
{
/* Set CPU Speed to 100MHz */
sc520_mmcr->cpuctl = 0x01;
- gd->cpu_clk = 100000000;
/* wait at least one millisecond */
asm("movl $0x2000,%%ecx\n"
/*
* Miscellaneous platform dependent initializations
*/
-int board_init(void)
+int board_early_init_f(void)
{
init_sc520_enet();
sc520_mmcr->sysarbctl = 0x06;
sc520_mmcr->sysarbmenb = 0x0003;
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ /* CPU Speed to 100MHz */
+ gd->cpu_clk = 100000000;
+
/* Crystal is 33.000MHz */
gd->bus_clk = 33000000;
.section .bios, "ax"
.code16
.globl realmode_reset
+.hidden realmode_reset
+.type realmode_reset, @function
realmode_reset:
/* Alias MMCR to 0xdf000 */
movw $0xfffc, %dx
SECTIONS
{
. = 0x38040000; /* Location of bootcode in flash */
+ _i386boot_text_start = .;
.text : { *(.text); }
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
_i386boot_text_size = SIZEOF(.text) + SIZEOF(.rodata);
+ . = ALIGN(4);
+
+ .data : { *(.data) }
+ . = ALIGN(4);
+
+ .interp : { *(.interp) }
+ . = ALIGN(4);
+
+ .dynsym : { *(.dynsym) }
+ . = ALIGN(4);
- . = 0x03FF0000; /* Ram data segment to use */
- _i386boot_romdata_dest = ABSOLUTE(.);
- .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) }
- _i386boot_romdata_start = LOADADDR(.data);
+ .dynstr : { *(.dynstr) }
+ . = ALIGN(4);
+
+ .hash : { *(.hash) }
+ . = ALIGN(4);
+ .got : { *(.got) }
. = ALIGN(4);
- .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) }
+ .got.plt : { *(.got.plt) }
. = ALIGN(4);
+
+ .dynamic (NOLOAD) : { *(.dynamic) }
+ . = ALIGN(4);
+
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
+ . = ALIGN(4);
__u_boot_cmd_end = .;
_i386boot_cmd_start = LOADADDR(.u_boot_cmd);
- _i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got) + SIZEOF(.u_boot_cmd);
+ _i386boot_rel_dyn_start = .;
+ .rel.dyn : { *(.rel.dyn) }
+ _i386boot_rel_dyn_end = .;
. = ALIGN(4);
_i386boot_bss_start = ABSOLUTE(.);
_i386boot_bss_size = SIZEOF(.bss);
/* 16bit realmode trampoline code */
- .realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) + SIZEOF(.u_boot_cmd)) { *(.realmode) }
+ .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { *(.realmode) }
_i386boot_realmode = LOADADDR(.realmode);
_i386boot_realmode_size = SIZEOF(.realmode);
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/eric/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- drivers/net/4xx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
*/
#include "../common/fpga.c"
-/* Prototypes */
-int gunzip(void *, int, unsigned char *, unsigned long *);
-
#ifdef CONFIG_LCD_USED
/* logo bitmap data - gzip compressed and generated by bin2c */
unsigned char logo_bmp[] =
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
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#include "../common/fpga.c"
-/* Prototypes */
-int gunzip(void *, int, unsigned char *, unsigned long *);
-
-
int board_early_init_f (void)
{
/*
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
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- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
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+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
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- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
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/* Prototypes */
int cpci405_version(void);
-int gunzip(void *, int, unsigned char *, unsigned long *);
void lxt971_no_sleep(void);
int board_early_init_f(void)
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
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- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
# MA 02111-1307 USA
#
TEXT_BASE = 0xFFFC0000
+
+# Use board specific linker script
+LDSCRIPT := $(SRCTREE)/board/esd/dasa_sim/u-boot.lds
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
return (0);
}
-/*
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- */
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller *hose)
-{
- unsigned long addr;
-
- /*
- * Set priority for all PLB3 devices to 0.
- * Set PLB3 arbiter to fair mode.
- */
- mfsdr(SD0_AMP1, addr);
- mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB3_ACR);
- mtdcr(PLB3_ACR, addr | 0x80000000);
-
- /*
- * Set priority for all PLB4 devices to 0.
- */
- mfsdr(SD0_AMP0, addr);
- mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
- mtdcr(PLB4_ACR, addr);
-
- /*
- * Set Nebula PLB4 arbiter to fair mode.
- */
- /* Segment0 */
- addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
- addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
- addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
- addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
- mtdcr(PLB0_ACR, addr);
-
- /* Segment1 */
- addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
- addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
- addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
- addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
- mtdcr(PLB1_ACR, addr);
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*
- * Set up Direct MMIO registers
- */
- /*
- * PowerPC440EPX PCI Master configuration.
- * Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0xA0000000-0xDFFFFFFF
- * ==> PCI address 0xA0000000-0xDFFFFFFF
- * Use byte reversed out routines to handle endianess.
- * Make this region non-prefetchable.
- */
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
- /* - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
- /* and enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
- /* - disabled b4 setting */
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
- /* and enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*
- * Set up Configuration registers
- */
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- PCI_VENDOR_ID_ESDGMBH);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, PCI_DEVICE_ID_DU440);
-
- pci_write_config_word(0, PCI_CLASS_SUB_CODE, PCI_CLASS_BRIDGE_HOST);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
-void pci_master_init(struct pci_controller *hose)
-{
- unsigned short temp_short;
-
- /*
- * Write the PowerPC440 EP PCI Configuration regs.
- * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- * Enable PowerPC440 EP to act as a PCI memory target (PTM).
- */
- pci_read_config_word(0, PCI_COMMAND, &temp_short);
- pci_write_config_word(0, PCI_COMMAND,
- temp_short | PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
-
-/*
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- */
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- /* always configured as host. */
- return (1);
-}
-#endif /* defined(CONFIG_PCI) */
-
int last_stage_init(void)
{
int e, i;
#define PWR_RDY 0x10
#define CPLD_IRQ (32+30)
-
-#define PCI_VENDOR_ID_ESDGMBH 0x12fe
-#define PCI_DEVICE_ID_DU440 0x0444
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
-
- _end = . ;
- PROVIDE (end = .);
-}
#include "../common/fpga.c"
-/* Prototypes */
-int gunzip(void *, int, unsigned char *, unsigned long *);
-
-
/* logo bitmap data - gzip compressed and generated by bin2c */
unsigned char logo_bmp_320[] =
{
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
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- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
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- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
DECLARE_GLOBAL_DATA_PTR;
/* Prototypes */
-int gunzip(void *, int, unsigned char *, unsigned long *);
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
unsigned long fpga_done_state(void);
unsigned long fpga_init_state(void);
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
COBJS = $(BOARD).o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
- ../common/auto_update.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
+#include <sja1000.h>
#undef FPGA_DEBUG
*/
#include "../common/fpga.c"
-/*
- * include common auto-update code (for esd boards)
- */
-#include "../common/auto_update.h"
-
-au_image_t au_image[] = {
- {"plu405/preinst.img", 0, -1, AU_SCRIPT},
- {"plu405/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
- {"plu405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
- {"plu405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
- {"plu405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
- {"plu405/postinst.img", 0, 0, AU_SCRIPT},
-};
-
-int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
-
-/* Prototypes */
-int gunzip(void *, int, unsigned char *, unsigned long *);
-
int board_early_init_f(void)
{
/*
out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
out_8((void *)DUART1_BA + 3, 0); /* write LCR */
+ /*
+ * Init magnetic couplers
+ */
+ if (!getenv("noinitcoupler")) {
+ init_coupler(CAN0_BA);
+ init_coupler(CAN1_BA);
+ }
return 0;
}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-#
-# AMCC 440EPx Reference Platform (Sequoia) board
-#
-
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
#include <miiphy.h>
#endif
#include <serial.h>
+#include <asm/4xx_pci.h>
+
#include "fpga.h"
#include "pmc440.h"
/*
* Assign interrupts to PCI devices. Some OSs rely on this.
*/
-void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
}
#endif
-/*
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- */
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller *hose)
-{
- unsigned long addr;
-
- /*
- * Set priority for all PLB3 devices to 0.
- * Set PLB3 arbiter to fair mode.
- */
- mfsdr(SD0_AMP1, addr);
- mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB3_ACR);
- mtdcr(PLB3_ACR, addr | 0x80000000);
-
- /*
- * Set priority for all PLB4 devices to 0.
- */
- mfsdr(SD0_AMP0, addr);
- mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
- mtdcr(PLB4_ACR, addr);
-
- /*
- * Set Nebula PLB4 arbiter to fair mode.
- */
- /* Segment0 */
- addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
- addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
- addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
- addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
- mtdcr(PLB0_ACR, addr);
-
- /* Segment1 */
- addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
- addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
- addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
- addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
- mtdcr(PLB1_ACR, addr);
-
-#ifdef CONFIG_PCI_PNP
- hose->fixup_irq = pmc440_pci_fixup_irq;
-#endif
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
/*
* pci_target_init
*
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*
- * pci_master_init
+ * Override weak default pci_master_init()
*/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
- unsigned short temp_short;
-
/*
- * Write the PowerPC440 EP PCI Configuration regs.
- * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- * Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ * Only configure the master in monach mode
*/
- if (is_monarch()) {
- pci_read_config_word(0, PCI_COMMAND, &temp_short);
- pci_write_config_word(0, PCI_COMMAND,
- temp_short | PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY);
- }
+ if (is_monarch())
+ __pci_master_init(hose);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
}
/*
- * is_pci_host
+ * Override weak is_pci_host()
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
}
#endif /* defined(CONFIG_PCI) */
-#if defined(CONFIG_POST)
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return 0; /* No hotkeys supported */
-}
-#endif /* CONFIG_POST */
-
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
-
- _end = . ;
- PROVIDE (end = .);
-}
/* Prototypes */
-int gunzip(void *, int, unsigned char *, unsigned long *);
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
* pci.c -- esd VME8349 PCI board support.
* Copyright (c) 2006 Wind River Systems, Inc.
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
*
* Based on MPC8349 PCI support but w/o PIB related code.
*
#include <pci.h>
#include <i2c.h>
#include <asm/fsl_i2c.h>
+#include "vme8349pin.h"
DECLARE_GLOBAL_DATA_PTR;
udelay(2000);
/*
- * Assert/deassert PCI reset
+ * Assert/deassert VME reset
*/
- setbits_be32(&immr->gpio[0].dat, 0x00800000);
- setbits_be32(&immr->gpio[0].dir, 0x00800000);
- setbits_be32(&immr->gpio[1].dir, 0x08800000);
+ clrsetbits_be32(&immr->gpio[1].dat,
+ GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
+ GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N);
+ setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
+ GPIO2_TSI_POWERUP_RESET_N |
+ GPIO2_VME_RESET_N |
+ GPIO2_L_RESET_EN_N);
+ clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
udelay(200);
- setbits_be32(&immr->gpio[1].dat, 0x08000000);
+ setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
udelay(200);
- setbits_be32(&immr->gpio[1].dat, 0x08800000);
+ setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
udelay(600000);
- clrbits_be32(&immr->gpio[1].dat, 0x00100000);
+ clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
/* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
udelay(2000);
- if (monarch == 0)
+ if (monarch == 0) {
mpc83xx_pci_init(1, reg, 0);
+ } else {
+ /*
+ * Release PCI RST Output signal
+ */
+ out_be32(&immr->pci_ctrl[0].gcr, 0);
+ udelay(2000);
+ out_be32(&immr->pci_ctrl[0].gcr, 1);
+ }
}
#endif
#include <asm/io.h>
#include <asm/mmu.h>
+#include <spd.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <netdev.h>
void ddr_enable_ecc(unsigned int dram_size);
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1);
- ddr_size = ddr_size>>1, ddr_size_log2++) {
- if (ddr_size & 1)
- return -1;
- }
-
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
- im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
- LAWAR_SIZE);
-
-#if (CONFIG_SYS_DDR_SIZE == 512)
- im->ddr.csbnds[0].csbnds = 0x0000001f;
-#else
-#warning Currently any DDR size other than 512MiB is not supported
-#endif
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG | 0x00330000;
-
- /* currently we use only one CS, so disable the other banks */
- im->ddr.csbnds[1].csbnds = 0x00000000;
- im->ddr.csbnds[2].csbnds = 0x00000000;
- im->ddr.csbnds[3].csbnds = 0x00000000;
- im->ddr.cs_config[1] = 0;
- im->ddr.cs_config[2] = 0;
- im->ddr.cs_config[3] = 0;
-
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- sync();
- udelay(200);
-
- /* enable DDR controller */
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
- return msize;
-}
-
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
- /* DDR SDRAM - Main SODIMM */
+ /* DDR SDRAM - Main memory */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
- msize = fixed_sdram();
+ msize = spd_sdram();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
int checkboard(void)
{
- puts("Board: esd VME8349\n");
+#ifdef VME_CADDY2
+ puts("Board: esd VME-CADDY/2\n");
+#else
+ puts("Board: esd VME-CPU/8349\n");
+#endif
return 0;
}
+#ifdef VME_CADDY2
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+#endif
+
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
#endif
+
+int misc_init_r()
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+ clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0);
+
+ return 0;
+}
+
+/*
+ * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
+ * and VME-CADDY/2) have different SDRAM configurations.
+ */
+#ifdef VME_CADDY2
+#define SMALL_RAM 0xff
+#define LARGE_RAM 0x00
+#else
+#define SMALL_RAM 0x00
+#define LARGE_RAM 0xff
+#endif
+
+#define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM))
+
+static spd_eeprom_t default_spd_eeprom = {
+ SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */
+ SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */
+ SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */
+ SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */
+ SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */
+ SPD_VAL(0x00, 0x00), /* 05 */
+ SPD_VAL(0x40, 0x40), /* 06 */
+ SPD_VAL(0x00, 0x00), /* 07 */
+ SPD_VAL(0x05, 0x05), /* 08 */
+ SPD_VAL(0x30, 0x30), /* 09 */
+ SPD_VAL(0x45, 0x45), /* 10 */
+ SPD_VAL(0x02, 0x02), /* 11 ecc used */
+ SPD_VAL(0x82, 0x82), /* 12 */
+ SPD_VAL(0x10, 0x10), /* 13 */
+ SPD_VAL(0x08, 0x08), /* 14 */
+ SPD_VAL(0x00, 0x00), /* 15 */
+ SPD_VAL(0x0c, 0x0c), /* 16 */
+ SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */
+ SPD_VAL(0x38, 0x38), /* 18 */
+ SPD_VAL(0x00, 0x00), /* 19 */
+ SPD_VAL(0x02, 0x02), /* 20 */
+ SPD_VAL(0x00, 0x00), /* 21 */
+ SPD_VAL(0x03, 0x03), /* 22 */
+ SPD_VAL(0x3d, 0x3d), /* 23 */
+ SPD_VAL(0x45, 0x45), /* 24 */
+ SPD_VAL(0x50, 0x50), /* 25 */
+ SPD_VAL(0x45, 0x45), /* 26 */
+ SPD_VAL(0x3c, 0x3c), /* 27 */
+ SPD_VAL(0x28, 0x28), /* 28 */
+ SPD_VAL(0x3c, 0x3c), /* 29 */
+ SPD_VAL(0x2d, 0x2d), /* 30 */
+ SPD_VAL(0x20, 0x80), /* 31 */
+ SPD_VAL(0x20, 0x20), /* 32 */
+ SPD_VAL(0x27, 0x27), /* 33 */
+ SPD_VAL(0x10, 0x10), /* 34 */
+ SPD_VAL(0x17, 0x17), /* 35 */
+ SPD_VAL(0x3c, 0x3c), /* 36 */
+ SPD_VAL(0x1e, 0x1e), /* 37 */
+ SPD_VAL(0x1e, 0x1e), /* 38 */
+ SPD_VAL(0x00, 0x00), /* 39 */
+ SPD_VAL(0x00, 0x06), /* 40 */
+ SPD_VAL(0x37, 0x37), /* 41 */
+ SPD_VAL(0x4b, 0x7f), /* 42 */
+ SPD_VAL(0x80, 0x80), /* 43 */
+ SPD_VAL(0x18, 0x18), /* 44 */
+ SPD_VAL(0x22, 0x22), /* 45 */
+ SPD_VAL(0x00, 0x00), /* 46 */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ SPD_VAL(0x10, 0x10), /* 62 */
+ SPD_VAL(0x7e, 0x1d), /* 63 */
+ { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
+ SPD_VAL(0x00, 0x00), /* 72 */
+#ifdef VME_CADDY2
+ { "vme-caddy/2 ram " }
+#else
+ { "vme-cpu/2 ram " }
+#endif
+};
+
+int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+ int old_bus = I2C_GET_BUS();
+ unsigned int l, sum;
+ int valid = 0;
+
+ I2C_SET_BUS(0);
+
+ if (i2c_read(chip, addr, alen, buffer, len) == 0)
+ if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
+ sum = 0;
+ for (l = 0; l < 63; l++)
+ sum = (sum + buffer[l]) & 0xff;
+ if (sum == buffer[63])
+ valid = 1;
+ else
+ printf("Invalid checksum in EEPROM %02x %02x\n",
+ sum, buffer[63]);
+ }
+
+ if (valid == 0) {
+ memcpy(buffer, (void *)&default_spd_eeprom, len);
+ sum = 0;
+ for (l = 0; l < 63; l++)
+ sum = (sum + buffer[l]) & 0xff;
+ if (sum != buffer[63])
+ printf("Invalid checksum in FLASH %02x %02x\n",
+ sum, buffer[63]);
+ buffer[63] = sum;
+ }
+
+ I2C_SET_BUS(old_bus);
+
+ return 0;
+}
--- /dev/null
+/*
+ * vme8349pin.h -- esd VME8349 MPC8349 I/O pin definition.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __VME8349PIN_H__
+#define __VME8349PIN_H__
+
+#define GPIO2_V_SCON 0x80000000 /* In: from tsi148 1: is syscon */
+#define GPIO2_VME_RESET_N 0x20000000 /* Out: to tsi148 */
+#define GPIO2_TSI_PLL_RESET_N 0x08000000 /* Out: to tsi148 */
+#define GPIO2_TSI_POWERUP_RESET_N 0x00800000 /* Out: to tsi148 */
+#define GPIO2_L_RESET_EN_N 0x00100000 /* Out: 0:vme can assert cpu lrst*/
+
+#endif /* of ifndef __VME8349PIN_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
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- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
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- *(.eh_frame)
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- }
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- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
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- *(.data)
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- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
#include "../common/fpga.c"
-/* Prototypes */
-int gunzip(void *, int, unsigned char *, unsigned long *);
-
-
/* logo bitmap data - gzip compressed and generated by bin2c */
unsigned char logo_bmp_320[] =
{
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
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- .init : { *(.init) }
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-
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- *(.got1)
- }
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- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
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- }
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- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
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- *(.dynbss)
- *(.bss)
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- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
+#include <sja1000.h>
DECLARE_GLOBAL_DATA_PTR;
extern void lxt971_no_sleep(void);
+/*
+ * generate a short spike on the CAN tx line
+ * to bring the couplers in sync
+ */
+void init_coupler(u32 addr)
+{
+ struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
+
+ /* reset */
+ out_8(&ctrl->cr, CR_RR);
+
+ /* dominant */
+ out_8(&ctrl->btr0, 0x00); /* btr setup is required */
+ out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
+ out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
+ OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
+ out_8(&ctrl->cr, 0x00);
+
+ /* delay */
+ in_8(&ctrl->cr);
+ in_8(&ctrl->cr);
+ in_8(&ctrl->cr);
+ in_8(&ctrl->cr);
+
+ /* reset */
+ out_8(&ctrl->cr, CR_RR);
+}
+
int board_early_init_f (void)
{
/*
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
+ /*
+ * Init magnetic coupler
+ */
+ if (!getenv("noinitcoupler"))
+ init_coupler(CAN_BA);
+
return (0);
}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
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- . = + SIZEOF_HEADERS;
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- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
#include "../common/fpga.c"
-/* Prototypes */
-int gunzip(void *, int, unsigned char *, unsigned long *);
-
-
int board_early_init_f (void)
{
/*
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
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- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/exbitgen/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- . = ALIGN(4);
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := a320evb.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <asm/arch/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_FARADAY;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ ftsmc020_init(); /* initialize Flash */
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_1;
+ unsigned long expected_size = PHYS_SDRAM_1_SIZE;
+ unsigned long actual_size;
+
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+ gd->bd->bi_dram[0].start = sdram_base;
+ gd->bd->bi_dram[0].size = actual_size;
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else
+ return 0;
+}
--- /dev/null
+#
+# (C) Copyright 2009 Faraday Technology
+# Po-Yu Chuang <ratbert@faraday-tech.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# Faraday A320 board with FA526/FA626TE/ARM926EJ-S cpus
+#
+# see http://www.faraday-tech.com/ for more information
+
+# A320 has 1 bank of 64 MB DRAM
+#
+# 1000'0000 to 1400'0000
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
+#
+# we load ourself to 13f8'0000
+#
+# download area is 1200'0000
+
+TEXT_BASE = 0x13f80000
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/macro.h>
+#include <asm/arch/ftsdmc020.h>
+
+/*
+ * parameters for the SDRAM controller
+ */
+#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
+#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
+#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
+#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
+#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
+
+#define TP0_D CONFIG_SYS_FTSDMC020_TP0
+#define TP1_D CONFIG_SYS_FTSDMC020_TP1
+#define CR_D1 FTSDMC020_CR_IPREC
+#define CR_D2 FTSDMC020_CR_ISMR
+#define CR_D3 FTSDMC020_CR_IREF
+
+#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \
+ FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
+#define ACR_D FTSDMC020_ACR_TOC(0x18)
+
+/*
+ * numeric 7 segment display
+ */
+.macro led, num
+ write32 CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+.macro wait_sdram
+ ldr r0, =CONFIG_FTSDMC020_BASE
+1:
+ ldr r1, [r0, #FTSDMC020_OFFSET_CR]
+ cmp r1, #0
+ bne 1b
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+ mov r11, lr
+
+ led 0x0
+
+ bl init_sdmc
+
+ led 0x1
+
+ /* everything is fine now */
+ mov lr, r11
+ mov pc, lr
+
+/*
+ * memory initialization
+ */
+init_sdmc:
+ led 0x10
+
+ /* set SDRAM register */
+
+ write32 TP0_A, TP0_D
+ led 0x11
+
+ write32 TP1_A, TP1_D
+ led 0x12
+
+ /* set to precharge */
+ write32 CR_A, CR_D1
+ led 0x13
+
+ wait_sdram
+ led 0x14
+
+ /* set mode register */
+ write32 CR_A, CR_D2
+ led 0x15
+
+ wait_sdram
+ led 0x16
+
+ /* set to refresh */
+ write32 CR_A, CR_D3
+ led 0x17
+
+ wait_sdram
+ led 0x18
+
+ write32 B0_BSR_A, B0_BSR_D
+ led 0x19
+
+ write32 ACR_A, ACR_D
+ led 0x1a
+
+ mov pc, lr
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_blob_update(void *blob, bd_t *bd)
-{
- int ret;
-
- ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
-
- if (ret < 0) {
- printf("ft_blob_update(): cannot set /memory/reg "
- "property err:%s\n", fdt_strerror(ret));
- }
-}
-
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
- ft_blob_update(blob, bd);
}
#endif
* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
* or the DDR2 controller may fail to initialize correctly.
*/
- udelay(50000);
+ __udelay(50000);
im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+ifndef NAND_SPL
+ifeq ($(CONFIG_MK_NAND), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+endif
+endif
+
+ifndef TEXT_BASE
TEXT_BASE = 0xFE000000
+endif
#include <mpc83xx.h>
#include <netdev.h>
#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+#ifndef CONFIG_NAND_SPL
+
static u8 read_board_info(void)
{
u8 val8;
cpu_eth_init(bis); /* Initialize TSECs first */
return pci_eth_init(bis);
}
+
+#else /* CONFIG_NAND_SPL */
+
+int checkboard(void)
+{
+ puts("Board: Freescale MPC8315ERDB\n");
+ return 0;
+}
+
+void board_init_f(ulong bootflag)
+{
+ board_early_init_f();
+ NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
+ CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+ puts("NAND boot... ");
+ init_timebase();
+ initdram(0);
+ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
+ CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (gd->flags & GD_FLG_SILENT)
+ return;
+
+ if (c == '\n')
+ NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
+
+ NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
+}
+
+#endif /* CONFIG_NAND_SPL */
* This is useful for faster booting in configs where the RAM is unlikely
* to be changed, or for things like NAND booting where space is tight.
*/
+#ifndef CONFIG_SYS_RAMBOOT
static long fixed_sdram(void)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
* or the DDR2 controller may fail to initialize correctly.
*/
- udelay(50000);
+ __udelay(50000);
im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
return msize;
}
+#else
+static long fixed_sdram(void)
+{
+ return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+}
+#endif /* CONFIG_SYS_RAMBOOT */
phys_size_t initdram(int board_type)
{
/*
- * Copyright 2008 Freescale Semiconductor.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
static struct pci_controller pcie3_hose;
#endif
-int first_free_busno=0;
-
-void
-pci_init_board(void)
+#ifdef CONFIG_PCI
+void pci_init_board(void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint devdisr = gur->devdisr;
- uint sdrs2_io_sel =
- (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct fsl_pci_info pci_info[4];
+ u32 devdisr, pordevsr, io_sel, sdrs2_io_sel;
+ u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+ int first_free_busno = 0;
+ int num = 0;
+
+ int pcie_ep, pcie_configured;
- debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\
- host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent);
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ porpllsr = in_be32(&gur->porpllsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ sdrs2_io_sel = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
+
+ debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x\n",
+ devdisr, sdrs2_io_sel, io_sel);
if (sdrs2_io_sel == 7)
printf(" Serdes2 disalbed\n");
} else if (sdrs2_io_sel == 6)
printf(" eTSEC1 is in sgmii mode.\n");
+ puts("\n");
#ifdef CONFIG_PCIE3
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
- struct pci_controller *hose = &pcie3_hose;
- int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
- struct pci_region *r = hose->regions;
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE3 connected to Slot3 as %s (base address %x)",
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
+ SET_STD_PCIE_INFO(pci_info[num], 3);
+ pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
+ printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_MEM_BUS,
- CONFIG_SYS_PCIE3_MEM_PHYS,
- CONFIG_SYS_PCIE3_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_IO_BUS,
- CONFIG_SYS_PCIE3_IO_PHYS,
- CONFIG_SYS_PCIE3_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno=hose->last_busno+1;
- printf (" PCIE3 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie3_hose, first_free_busno);
} else {
printf (" PCIE3: disabled\n");
}
-}
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
#endif
#ifdef CONFIG_PCIE1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- struct pci_controller *hose = &pcie1_hose;
- int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
- struct pci_region *r = hose->regions;
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE1 connected to Slot1 as %s (base address %x)",
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BUS,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BUS,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
-#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BUS2,
- CONFIG_SYS_PCIE1_MEM_PHYS2,
- CONFIG_SYS_PCIE1_MEM_SIZE2,
- PCI_REGION_MEM);
-#endif
- hose->region_count = r - hose->regions;
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno=hose->last_busno+1;
- printf(" PCIE1 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
-
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
} else {
printf (" PCIE1: disabled\n");
}
-}
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
#ifdef CONFIG_PCIE2
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- struct pci_controller *hose = &pcie2_hose;
- int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
- struct pci_region *r = hose->regions;
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)",
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+ printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BUS,
- CONFIG_SYS_PCIE2_MEM_PHYS,
- CONFIG_SYS_PCIE2_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BUS,
- CONFIG_SYS_PCIE2_IO_PHYS,
- CONFIG_SYS_PCIE2_IO_SIZE,
- PCI_REGION_IO);
-
-#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BUS2,
- CONFIG_SYS_PCIE2_MEM_PHYS2,
- CONFIG_SYS_PCIE2_MEM_SIZE2,
- PCI_REGION_MEM);
-#endif
- hose->region_count = r - hose->regions;
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- first_free_busno=hose->last_busno+1;
- printf (" PCIE2 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
-
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie2_hose, first_free_busno);
} else {
printf (" PCIE2: disabled\n");
}
-}
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
#endif
#ifdef CONFIG_PCI1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- struct pci_controller *hose = &pci1_hose;
- struct pci_region *r = hose->regions;
-
- uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI, host_agent);
- uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
- uint pci_32 = 1;
- uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
- uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
+ pci_speed = 66666000;
+ pci_32 = 1;
+ pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+ pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
- printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
+ SET_STD_PCI_INFO(pci_info[num], 1);
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+ printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333000) ? "33" :
(pci_speed == 66666000) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
pci_agent ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter",
- (uint)pci
- );
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BUS,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BUS,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
-#ifdef CONFIG_SYS_PCI1_MEM_BUS2
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BUS2,
- CONFIG_SYS_PCI1_MEM_PHYS2,
- CONFIG_SYS_PCI1_MEM_SIZE2,
- PCI_REGION_MEM);
-#endif
- hose->region_count = r - hose->regions;
- hose->first_busno=first_free_busno;
+ pci_info[num].regs);
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- first_free_busno=hose->last_busno+1;
- printf ("PCI on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pci1_hose, first_free_busno);
} else {
printf (" PCI: disabled\n");
}
-}
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
}
+#endif
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- const u8 flash_esel = 1;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
/*
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
static struct pci_controller pcie3_hose;
#endif
-int first_free_busno=0;
-
-void
-pci_init_board(void)
+void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint devdisr = gur->devdisr;
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+ struct fsl_pci_info pci_info[4];
+ u32 devdisr, pordevsr, io_sel;
+ u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+ int first_free_busno = 0;
+ int num = 0;
+
+ int pcie_ep, pcie_configured;
- debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
- devdisr, io_sel, host_agent);
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ porpllsr = in_be32(&gur->porpllsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
if (io_sel & 1) {
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
printf (" eTSEC3 is in sgmii mode.\n");
}
+ puts("\n");
#ifdef CONFIG_PCIE3
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
- struct pci_controller *hose = &pcie3_hose;
- int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
- struct pci_region *r = hose->regions;
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE3 connected to ULI as %s (base address %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_MEM_BUS,
- CONFIG_SYS_PCIE3_MEM_PHYS,
- CONFIG_SYS_PCIE3_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_IO_BUS,
- CONFIG_SYS_PCIE3_IO_PHYS,
- CONFIG_SYS_PCIE3_IO_SIZE,
- PCI_REGION_IO);
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
+ SET_STD_PCIE_INFO(pci_info[num], 3);
+ pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
/* outbound memory */
- pci_set_region(r++,
+ pci_set_region(&pcie3_hose.regions[0],
CONFIG_SYS_PCIE3_MEM_BUS2,
CONFIG_SYS_PCIE3_MEM_PHYS2,
CONFIG_SYS_PCIE3_MEM_SIZE2,
PCI_REGION_MEM);
-#endif
- hose->region_count = r - hose->regions;
- hose->first_busno=first_free_busno;
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno=hose->last_busno+1;
- printf (" PCIE3 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ pcie3_hose.region_count = 1;
+#endif
+ printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie3_hose, first_free_busno);
/*
* Activate ULI1575 legacy chip by performing a fake
} else {
printf (" PCIE3: disabled\n");
}
-
- }
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
#endif
#ifdef CONFIG_PCIE1
- {
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- struct pci_controller *hose = &pcie1_hose;
- int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
- struct pci_region *r = hose->regions;
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BUS,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BUS,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
/* outbound memory */
- pci_set_region(r++,
+ pci_set_region(&pcie1_hose.regions[0],
CONFIG_SYS_PCIE1_MEM_BUS2,
CONFIG_SYS_PCIE1_MEM_PHYS2,
CONFIG_SYS_PCIE1_MEM_SIZE2,
PCI_REGION_MEM);
-#endif
- hose->region_count = r - hose->regions;
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- first_free_busno=hose->last_busno+1;
- printf(" PCIE1 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ pcie1_hose.region_count = 1;
+#endif
+ printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
} else {
printf (" PCIE1: disabled\n");
}
- }
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
#ifdef CONFIG_PCIE2
- {
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- struct pci_controller *hose = &pcie2_hose;
- int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
- struct pci_region *r = hose->regions;
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BUS,
- CONFIG_SYS_PCIE2_MEM_PHYS,
- CONFIG_SYS_PCIE2_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BUS,
- CONFIG_SYS_PCIE2_IO_PHYS,
- CONFIG_SYS_PCIE2_IO_SIZE,
- PCI_REGION_IO);
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
/* outbound memory */
- pci_set_region(r++,
+ pci_set_region(&pcie2_hose.regions[0],
CONFIG_SYS_PCIE2_MEM_BUS2,
CONFIG_SYS_PCIE2_MEM_PHYS2,
CONFIG_SYS_PCIE2_MEM_SIZE2,
PCI_REGION_MEM);
-#endif
- hose->region_count = r - hose->regions;
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- first_free_busno=hose->last_busno+1;
- printf (" PCIE2 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ pcie2_hose.region_count = 1;
+#endif
+ printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie2_hose, first_free_busno);
} else {
printf (" PCIE2: disabled\n");
}
- }
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
#endif
-
#ifdef CONFIG_PCI1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- struct pci_controller *hose = &pci1_hose;
- struct pci_region *r = hose->regions;
-
- uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI, host_agent);
- uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
- uint pci_32 = 1;
- uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
- uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
-
+ pci_speed = 66666000;
+ pci_32 = 1;
+ pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+ pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
- printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
+ SET_STD_PCI_INFO(pci_info[num], 1);
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+ printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333000) ? "33" :
(pci_speed == 66666000) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
pci_agent ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter",
- (uint)pci
- );
+ pci_info[num].regs);
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BUS,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BUS,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
-#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_MEM_BUS2,
- CONFIG_SYS_PCIE3_MEM_PHYS2,
- CONFIG_SYS_PCIE3_MEM_SIZE2,
- PCI_REGION_MEM);
-#endif
- hose->region_count = r - hose->regions;
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- first_free_busno=hose->last_busno+1;
- printf ("PCI on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pci1_hose, first_free_busno);
} else {
printf (" PCI: disabled\n");
}
-}
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
}
/*
- * Copyright 2004, 2007 Freescale Semiconductor.
+ * Copyright 2004, 2007, 200 Freescale Semiconductor, Inc.
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
-int first_free_busno=0;
-
-void
-pci_init_board(void)
+void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
-
-
-#ifdef CONFIG_PCI1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- struct pci_controller *hose = &pci1_hose;
- struct pci_region *r = hose->regions;
+ struct fsl_pci_info pci_info[4];
+ u32 devdisr, pordevsr, io_sel;
+ u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+ int first_free_busno = 0;
+ int num = 0;
- uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
- uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
- uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
+ int pcie_ep, pcie_configured;
- uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ porpllsr = in_be32(&gur->porpllsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
- if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
- printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
+#ifdef CONFIG_PCI1
+ pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+ pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
+ pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+ pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info[num], 1);
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+ printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333000) ? "33" :
(pci_speed == 66666000) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
pci_agent ? "agent" : "host",
- pci_arb ? "arbiter" : "external-arbiter"
- );
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BUS,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BUS,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
- hose->region_count = r - hose->regions;
-
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- first_free_busno=hose->last_busno+1;
- printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+ pci_arb ? "arbiter" : "external-arbiter",
+ pci_info[num].regs);
+
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pci1_hose, first_free_busno);
+
#ifdef CONFIG_PCIX_CHECK
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
+ if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
/* PCI-X init */
if (CONFIG_SYS_CLK_FREQ < 66000000)
printf("PCI-X will only work at 66 MHz\n");
} else {
printf (" PCI: disabled\n");
}
-}
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
#ifdef CONFIG_PCI2
{
- uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
+ uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
if (pci_dual) {
printf (" PCI2: 32 bit, 66 MHz, %s\n",
}
}
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
#endif /* CONFIG_PCI2 */
#ifdef CONFIG_PCIE1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- struct pci_controller *hose = &pcie1_hose;
- int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
- struct pci_region *r = hose->regions;
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-
- if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE connected to slot as %s (base address %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
-
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BUS,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BUS,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
-
- first_free_busno=hose->last_busno+1;
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
} else {
- printf (" PCIE: disabled\n");
+ printf (" PCIE1: disabled\n");
}
- }
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
-
}
int last_stage_init(void)
/*
- * Copyright 2007 Freescale Semiconductor.
+ * Copyright 2007,2009 Freescale Semiconductor, Inc.
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
-int first_free_busno = 0;
-
/*
* pib_init() -- Initialize the PCA9555 IO expander on the PIB board
*/
}
#ifdef CONFIG_PCI
-void
-pci_init_board(void)
+void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
-
-#ifdef CONFIG_PCI1
-{
- pib_init();
-
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- struct pci_controller *hose = &pci1_hose;
- struct pci_region *r = hose->regions;
+ struct fsl_pci_info pci_info[2];
+ u32 devdisr, pordevsr, io_sel;
+ u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+ int first_free_busno = 0;
+ int num = 0;
- uint pci_32 = 1; /* PORDEVSR[15] */
- uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
- uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
+ int pcie_ep, pcie_configured;
- uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ porpllsr = in_be32(&gur->porpllsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint pci_speed = 66666000;
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
- if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
- printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
+#ifdef CONFIG_PCI1
+ pci_speed = 66666000;
+ pci_32 = 1;
+ pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+ pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info[num], 1);
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+ printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333000) ? "33" :
(pci_speed == 66666000) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
pci_agent ? "agent" : "host",
- pci_arb ? "arbiter" : "external-arbiter"
- );
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BUS,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BUS,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- first_free_busno = hose->last_busno+1;
- printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+ pci_arb ? "arbiter" : "external-arbiter",
+ pci_info[num].regs);
+
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pci1_hose, first_free_busno);
} else {
- printf (" PCI: disabled\n");
+ printf (" PCI: disabled\n");
}
-}
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
#ifdef CONFIG_PCIE1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- struct pci_controller *hose = &pcie1_hose;
- int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
- struct pci_region *r = hose->regions;
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-
- if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE connected to slot as %s (base address %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
-
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BUS,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BUS,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
-
- first_free_busno=hose->last_busno+1;
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
} else {
- printf (" PCIE: disabled\n");
+ printf (" PCIE1: disabled\n");
}
-}
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
}
#endif /* CONFIG_PCI */
console_assign(stdin, "eserial1");
printf("Switched to UART1 (initial log has been printed to "
"UART0).\n");
+
+ clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
+ PLPPAR1_ESDHC_4BITS_VAL);
+ clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
+ PLPDIR1_ESDHC_4BITS_VAL);
bcsr6 |= BCSR6_SD_CARD_4BITS;
} else {
printf("should be disabled.\n");
break;
}
}
+
+ if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
+ off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
+ if (off < 0) {
+ printf("WARNING: could not find esdhc node\n");
+ return;
+ }
+ fdt_delprop(blob, off, "sdhci,1-bit-only");
+ }
}
#else
static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
-int first_free_busno = 0;
-
#ifdef CONFIG_PCI
-void
-pci_init_board(void)
-{
- volatile ccsr_gur_t *gur;
- uint io_sel;
- uint host_agent;
-
- gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
-
-#ifdef CONFIG_PCIE1
+void pci_init_board(void)
{
- volatile ccsr_fsl_pci_t *pci;
- struct pci_controller *hose;
- int pcie_ep;
- struct pci_region *r;
- int pcie_configured;
-
- pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- hose = &pcie1_hose;
- pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
- r = hose->regions;
- pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-
- if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE connected to slot as %s (base address %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
-
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
- printf ("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BUS,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BUS,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct fsl_pci_info pci_info[1];
+ u32 devdisr, pordevsr, io_sel;
+ int first_free_busno = 0;
+ int num = 0;
- hose->region_count = r - hose->regions;
+ int pcie_ep, pcie_configured;
- hose->first_busno=first_free_busno;
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- printf ("PCIE on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
- first_free_busno=hose->last_busno+1;
+#ifdef CONFIG_PCIE1
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
} else {
- printf (" PCIE: disabled\n");
+ printf (" PCIE1: disabled\n");
}
-}
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
+
}
#endif /* CONFIG_PCI */
/*
- * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct fsl_pci_info pci_info[3];
- u32 devdisr, pordevsr, io_sel, host_agent, temp32;
+ u32 devdisr, pordevsr, io_sel, temp32;
int first_free_busno = 0;
int num = 0;
devdisr = in_be32(&gur->devdisr);
pordevsr = in_be32(&gur->pordevsr);
io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
- debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
- devdisr, io_sel, host_agent);
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
printf (" eTSEC1 is in sgmii mode.\n");
puts("\n");
#ifdef CONFIG_PCIE3
- pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
SET_STD_PCIE_INFO(pci_info[num], 3);
+ pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie3_hose, first_free_busno, pcie_ep);
+ &pcie3_hose, first_free_busno);
/*
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
#endif
#ifdef CONFIG_PCIE2
- pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
SET_STD_PCIE_INFO(pci_info[num], 2);
+ pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno, pcie_ep);
+ &pcie2_hose, first_free_busno);
} else {
printf (" PCIE2: disabled\n");
}
#endif
#ifdef CONFIG_PCIE1
- pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno, pcie_ep);
+ &pcie1_hose, first_free_busno);
} else {
printf (" PCIE1: disabled\n");
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- const u8 flash_esel = 2;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */
/*
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
dram_size = fixed_sdram();
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- puts(" DDR: ");
- return dram_size;
-#endif
-
puts(" DDR: ");
return dram_size;
}
static struct pci_controller pcie2_hose;
#endif
-int first_free_busno = 0;
-
void pci_init_board(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
- uint devdisr = gur->devdisr;
- uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
- >> MPC8610_PORDEVSR_IO_SEL_SHIFT;
- uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA)
- >> MPC8610_PORBMSR_HA_SHIFT;
+ struct fsl_pci_info pci_info[3];
+ u32 devdisr, pordevsr, io_sel;
+ int first_free_busno = 0;
+ int num = 0;
+
+ int pci_agent, pcie_ep, pcie_configured;
+
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ io_sel = (pordevsr & MPC8610_PORDEVSR_IO_SEL)
+ >> MPC8610_PORDEVSR_IO_SEL_SHIFT;
- printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
- devdisr, io_sel, host_agent);
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
#ifdef CONFIG_PCIE1
- {
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- struct pci_controller *hose = &pcie1_hose;
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
- int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
- struct pci_region *r = hose->regions;
-
- if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
- printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det)
- pci->pme_msg_det = 0xffffffff;
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BUS,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BUS,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno = hose->last_busno + 1;
- printf(" PCI-Express 1 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
-
- } else
- puts(" PCI-Express 1: Disabled\n");
- }
-#else
- puts("PCI-Express 1: Disabled\n");
-#endif /* CONFIG_PCIE1 */
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf (" PCIE1 connected to ULI as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
+ } else {
+ printf (" PCIE1: disabled\n");
+ }
+ puts("\n");
+#else
+ setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */
+#endif
#ifdef CONFIG_PCIE2
- {
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- struct pci_controller *hose = &pcie2_hose;
- struct pci_region *r = hose->regions;
-
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
- int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
-
- if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
- printf(" PCI-Express 2 connected to slot as %s" \
- " (base address %x)\n",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det)
- pci->pme_msg_det = 0xffffffff;
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BUS,
- CONFIG_SYS_PCIE2_MEM_PHYS,
- CONFIG_SYS_PCIE2_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BUS,
- CONFIG_SYS_PCIE2_IO_PHYS,
- CONFIG_SYS_PCIE2_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno = hose->last_busno + 1;
- printf(" PCI-Express 2 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
- } else
- puts(" PCI-Express 2: Disabled\n");
- }
-#else
- puts("PCI-Express 2: Disabled\n");
-#endif /* CONFIG_PCIE2 */
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+ printf (" PCIE2 connected to Slot as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie2_hose, first_free_busno);
+ } else {
+ printf (" PCIE2: disabled\n");
+ }
+ puts("\n");
+#else
+ setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */
+#endif
#ifdef CONFIG_PCI1
- {
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- struct pci_controller *hose = &pci1_hose;
- int pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);
- struct pci_region *r = hose->regions;
-
- if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
+ if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info[num], 1);
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
printf(" PCI connected to PCI slots as %s" \
- " (base address %x)\n",
+ " (base address %lx)\n",
pci_agent ? "Agent" : "Host",
- (uint)pci);
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BUS,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BUS,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno = hose->last_busno + 1;
- printf(" PCI on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
-
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pci1_hose, first_free_busno);
+ } else {
+ printf (" PCI: disabled\n");
+ }
- } else
- puts(" PCI: Disabled\n");
- }
-#endif /* CONFIG_PCI1 */
+ puts("\n");
+#else
+ setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
+#endif
}
#if defined(CONFIG_OF_BOARD_SETUP)
dram_size = fixed_sdram();
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- puts(" DDR: ");
- return dram_size;
-#endif
-
puts(" DDR: ");
return dram_size;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- const u8 flash_esel = 2;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct fsl_pci_info pci_info[2];
- u32 devdisr, pordevsr, io_sel, host_agent;
+ u32 devdisr, pordevsr, io_sel;
int first_free_busno = 0;
int num = 0;
devdisr = in_be32(&gur->devdisr);
pordevsr = in_be32(&gur->pordevsr);
io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
- debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
- devdisr, io_sel, host_agent);
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
printf (" eTSEC2 is in sgmii mode.\n");
puts("\n");
#ifdef CONFIG_PCIE2
- pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 2);
+ pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno, pcie_ep);
+ &pcie2_hose, first_free_busno);
} else {
printf (" PCIE2: disabled\n");
}
#endif
#ifdef CONFIG_PCIE1
- pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno, pcie_ep);
+ &pcie1_hose, first_free_busno);
} else {
printf (" PCIE1: disabled\n");
}
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct fsl_pci_info pci_info[3];
- u32 devdisr, pordevsr, io_sel, host_agent;
+ u32 devdisr, pordevsr, io_sel;
int first_free_busno = 0;
int num = 0;
devdisr = in_be32(&gur->devdisr);
pordevsr = in_be32(&gur->pordevsr);
io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
- debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
- devdisr, io_sel, host_agent);
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
printf(" eTSEC2 is in sgmii mode.\n");
puts("\n");
#ifdef CONFIG_PCIE2
- pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
SET_STD_PCIE_INFO(pci_info[num], 2);
+ pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
printf(" PCIE2 connected to ULI as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno, pcie_ep);
+ &pcie2_hose, first_free_busno);
/*
* The workaround doesn't work on p2020 because the location
#endif
#ifdef CONFIG_PCIE3
- pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
SET_STD_PCIE_INFO(pci_info[num], 3);
+ pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie3_hose, first_free_busno, pcie_ep);
+ &pcie3_hose, first_free_busno);
} else {
printf(" PCIE3: disabled\n");
}
#endif
#ifdef CONFIG_PCIE1
- pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno, pcie_ep);
+ &pcie1_hose, first_free_busno);
} else {
printf(" PCIE1: disabled\n");
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- const u8 flash_esel = 2;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
*/
#include <common.h>
+#include <netdev.h>
#include <SA-1100.h>
DECLARE_GLOBAL_DATA_PTR;
return (0);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_LAN91C96
+ rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+ return rc;
+}
+#endif
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
#include <ppc4xx.h>
#include <asm/processor.h>
#include <asm/io.h>
+#include <asm/4xx_pci.h>
DECLARE_GLOBAL_DATA_PTR;
}
/*
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
+ * Override weak pci_pre_init()
*/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
- unsigned long addr;
-
- /*
- * Set priority for all PLB3 devices to 0.
- * Set PLB3 arbiter to fair mode.
- */
- mfsdr(SD0_AMP1, addr);
- mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB3_ACR);
- mtdcr(PLB3_ACR, addr | 0x80000000);
-
- /*
- * Set priority for all PLB4 devices to 0.
- */
- mfsdr(SD0_AMP0, addr);
- mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
- mtdcr(PLB4_ACR, addr);
-
- /*
- * Set Nebula PLB4 arbiter to fair mode.
- */
- /* Segment0 */
- addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
- addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
- addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
- addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
- mtdcr(PLB0_ACR, addr);
-
- /* Segment1 */
- addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
- addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
- addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
- addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
- mtdcr(PLB1_ACR, addr);
+ /* First call common code */
+ __pci_pre_init(hose);
/* enable 66 MHz ext. Clock */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);
return 1;
}
#endif /* defined(CONFIG_PCI) */
-
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*
- * Set up Direct MMIO registers
- */
-
- /*
- * PowerPC440 EP PCI Master configuration.
- * Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0xA0000000-0xDFFFFFFF
- * ==> PCI address 0xA0000000-0xDFFFFFFF
- * Use byte reversed out routines to handle endianess.
- * Make this region non-prefetchable.
- */
- out32r(PCIL0_PMM0MA, 0x00000000); /* disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
- out32r(PCIL0_PMM0PCIHA, 0x00000000);
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* disabled b4 setting */
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
- out32r(PCIL0_PMM1PCIHA, 0x00000000);
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001);
- out32r(PCIL0_PTM1LA, 0);
- out32r(PCIL0_PTM2MS, 0);
- out32r(PCIL0_PTM2LA, 0);
-
- /*
- * Set up Configuration registers
- */
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*
- * pci_master_init
- *
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
-void pci_master_init(struct pci_controller *hose)
-{
- unsigned short temp_short;
-
- /*
- * Write the PowerPC440 EP PCI Configuration regs.
- * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- * Enable PowerPC440 EP to act as a PCI memory target (PTM).
- */
- pci_read_config_word(0, PCI_COMMAND, &temp_short);
- pci_write_config_word(0, PCI_COMMAND,
- temp_short | PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
-
-/*
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- */
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/gdsys/gdppc440etx/init.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
return 0;
}
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*
- * Disable everything
- */
- out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
- out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
- out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
- out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
-
- /*
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
- * strapping options to not support sizes such as 128/256 MB.
- */
- out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out_le32((void *)PCIL0_PIM0LAH, 0);
- out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
- out_le32((void *)PCIL0_BAR0, 0);
-
- /*
- * Program the board's subsystem id/vendor id
- */
- out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
- out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-#if defined(CONFIG_PCI)
-/*
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- */
-int is_pci_host(struct pci_controller *hose)
-{
- /* Board is always configured as host. */
- return 1;
-}
-#endif /* CONFIG_PCI */
-
int board_early_init_r(void)
{
/*
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/gdsys/intip/init.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
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- .rel.data : { *(.rel.data) }
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- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
puts ("### Please power off the board ###\n");
while (1);
}
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed (void)
-{
- return 0; /* No hotkeys supported */
-}
-#endif
#endif /* CONFIG_CMD_NAND */
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-/*
- * update "memory" property in the blob
- */
-void ft_blob_update(void *blob, bd_t *bd)
-{
- int ret;
-
- ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
-
- if (ret < 0) {
- printf("ft_blob_update(): cannot set /memory/reg "
- "property err:%s\n", fdt_strerror(ret));
- }
-}
-
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup( blob, bd);
- ft_blob_update(blob, bd);
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
--- /dev/null
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IPEK01 board
+#
+
+TEXT_BASE = 0xfc000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
--- /dev/null
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2006
+ * MicroSys GmbH
+ *
+ * (C) Copyright 2009
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <mb862xx.h>
+#include <video_fb.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_OF_LIBFDT
+#include <fdt_support.h>
+#endif /* CONFIG_OF_LIBFDT */
+
+/* mt46v16m16-75 */
+#ifdef CONFIG_MPC5200_DDR
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x714f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
+#else
+#error SDRAM is not supported on this board
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_start (int hi_addr)
+{
+ struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
+
+ /* precharge all banks */
+ out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
+
+ /* set mode register: extended mode */
+ out_be32 (&sdram->mode, SDRAM_EMODE);
+
+ /* set mode register: reset DLL */
+ out_be32 (&sdram->mode, SDRAM_MODE | 0x04000000);
+
+ /* precharge all banks */
+ out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
+
+ /* auto refresh */
+ out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
+
+ /* set mode register */
+ out_be32 (&sdram->mode, SDRAM_MODE);
+
+ /* normal operation */
+ out_be32 (&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
+ * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+ struct mpc5xxx_mmap_ctl *mmap_ctl =
+ (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+ struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+ struct mpc5xxx_cdm *cdm = (struct mpc5xxx_cdm *)MPC5XXX_CDM;
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ out_be32 (&mmap_ctl->sdram0, 0x0000001e); /* 2G at 0x0 */
+ out_be32 (&mmap_ctl->sdram1, 0x00000000); /* disabled */
+
+ /* setup config registers */
+ out_be32 (&sdram->config1, SDRAM_CONFIG1);
+ out_be32 (&sdram->config2, SDRAM_CONFIG2);
+
+ /* set tap delay */
+ out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start (0);
+ test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start (1);
+ test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start (0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0)
+ out_be32 (&mmap_ctl->sdram0,
+ 0x13 + __builtin_ffs (dramsize >> 20) - 1);
+ else
+ out_be32 (&mmap_ctl->sdram1, 0); /* disabled */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ out_be32 (&sdram->sdelay, 0x04);
+
+ return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+ puts ("Board: IPEK01 \n");
+ return 0;
+}
+
+void flash_preinit (void)
+{
+ struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
+
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ clrbits_be32 (&lpb->cs0_cfg, 0x1); /* clear RO */
+}
+
+void flash_afterinit (ulong start, ulong size)
+{
+ struct mpc5xxx_mmap_ctl *mmap_ctl =
+ (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+
+#if defined(CONFIG_BOOT_ROM)
+ /* adjust mapping */
+ out_be32 (&mmap_ctl->cs1_start, START_REG (start));
+ out_be32 (&mmap_ctl->cs1_stop, STOP_REG (start, size));
+#else
+ /* adjust mapping */
+ out_be32 (&mmap_ctl->boot_start, START_REG (start));
+ out_be32 (&mmap_ctl->cs0_start, START_REG (start));
+ out_be32 (&mmap_ctl->boot_stop, STOP_REG (start, size));
+ out_be32 (&mmap_ctl->cs0_stop, STOP_REG (start, size));
+#endif
+}
+
+extern flash_info_t flash_info[]; /* info for FLASH chips */
+
+int misc_init_r (void)
+{
+ /* adjust flash start */
+ gd->bd->bi_flashstart = flash_info[0].start[0];
+ return (0);
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init (struct pci_controller *);
+
+void pci_init_board (void)
+{
+ pci_mpc5xxx_init (&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup (void *blob, bd_t * bd)
+{
+ ft_cpu_setup (blob, bd);
+ fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in FEC comes first */
+ return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_VIDEO
+extern GraphicDevice mb862xx;
+
+static const gdc_regs init_regs[] = {
+ {0x0100, 0x00000900},
+ {0x0020, 0x80190257},
+ {0x0024, 0x00000000},
+ {0x0028, 0x00000000},
+ {0x002c, 0x00000000},
+ {0x0110, 0x00000000},
+ {0x0114, 0x00000000},
+ {0x0118, 0x02570320},
+ {0x0004, 0x041f0000},
+ {0x0008, 0x031f031f},
+ {0x000c, 0x067f0347},
+ {0x0010, 0x02780000},
+ {0x0014, 0x0257025c},
+ {0x0018, 0x00000000},
+ {0x001c, 0x02570320},
+ {0x0100, 0x80010900},
+ {0x0, 0x0}
+};
+
+const gdc_regs *board_get_regs (void)
+{
+ return init_regs;
+}
+
+/* Returns Lime base address */
+unsigned int board_video_init (void)
+{
+ if (mb862xx_probe (CONFIG_SYS_LIME_BASE) != MB862XX_TYPE_LIME)
+ return 0;
+
+ mb862xx.winSizeX = 800;
+ mb862xx.winSizeY = 600;
+ mb862xx.gdfIndex = GDF_15BIT_555RGB;
+ mb862xx.gdfBytesPP = 2;
+
+ return CONFIG_SYS_LIME_BASE;
+}
+
+#if defined(CONFIG_CONSOLE_EXTRA_INFO)
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+ if (line_number == 1)
+ strcpy (info, " Board: IPEK01");
+ else
+ info[0] = '\0';
+}
+#endif
+#endif /* CONFIG_VIDEO */
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text : {
- /* The start.o file includes the initial jump vector that
- must be located in the beginning. It is the basic run-
- time function that calls all other functions. */
- cpu/ppc4xx/start.o (.text)
-
- board/jse/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
-
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
/*
- * update "memory" property in the blob
+ * update "flash" property in the blob
*/
void ft_blob_update (void *blob, bd_t *bd)
{
- ulong memory_data[2] = {0};
ulong *flash_data = NULL;
ulong flash_reg[6] = {0};
flash_info_t *info;
int size;
int i = 0;
- memory_data[0] = cpu_to_be32 (bd->bi_memstart);
- memory_data[1] = cpu_to_be32 (bd->bi_memsize);
- fdt_set_node_and_value (blob, "/memory", "reg", memory_data,
- sizeof (memory_data));
-
len = fdt_get_node_and_value (blob, "/localbus", "ranges",
(void *)&flash_data);
#include <asm/io.h>
#include <asm/ppc4xx-uic.h>
#include <asm/processor.h>
+#include <asm/4xx_pci.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Assign interrupts to PCI devices.
*/
-void korat_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
}
#endif
-/*
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- */
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller *hose)
-{
- unsigned long addr;
-
- /*
- * Set priority for all PLB3 devices to 0.
- * Set PLB3 arbiter to fair mode.
- */
- mfsdr(SD0_AMP1, addr);
- mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB3_ACR);
- mtdcr(PLB3_ACR, addr | 0x80000000);
-
- /*
- * Set priority for all PLB4 devices to 0.
- */
- mfsdr(SD0_AMP0, addr);
- mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
- mtdcr(PLB4_ACR, addr);
-
- /*
- * Set Nebula PLB4 arbiter to fair mode.
- */
- /* Segment0 */
- addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
- addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
- addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
- addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
- mtdcr(PLB0_ACR, addr);
-
- /* Segment1 */
- addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
- addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
- addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
- addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
- mtdcr(PLB1_ACR, addr);
-
-#if defined(CONFIG_PCI_PNP)
- hose->fixup_irq = korat_pci_fixup_irq;
-#endif
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
/*
* pci_target_init
*
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
- /*
- * Set up Direct MMIO registers
- */
- /*
- * PowerPC440EPX PCI Master configuration.
- * Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0x80000000-0xBFFFFFFF
- * ==> PCI address 0x80000000-0xBFFFFFFF
- * Use byte reversed out routines to handle endianess.
- * Make this region non-prefetchable.
- */
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
- /* - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA,
- CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
- /* and enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
- /* - disabled b4 setting */
- out32r(PCIL0_PMM1LA,
- CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 Local Address */
- out32r(PCIL0_PMM1PCILA,
- CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
- /* and enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*
- * Set up Configuration registers
- */
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+ /* First do 440EP(x) common setup */
+ __pci_target_init(hose);
/*
* Set up Configuration registers for on-board NEC uPD720101 USB
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
-void pci_master_init(struct pci_controller *hose)
-{
- unsigned short temp_short;
-
- /*
- * Write the PowerPC440 EP PCI Configuration regs.
- * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- * Enable PowerPC440 EP to act as a PCI memory target (PTM).
- */
- pci_read_config_word(0, PCI_COMMAND, &temp_short);
- pci_write_config_word(0, PCI_COMMAND,
- temp_short | PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY);
-}
-#endif
-
-/*
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- */
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- /* Korat is always configured as host. */
- return (1);
-}
-#endif /* defined(CONFIG_PCI) */
-
-#if defined(CONFIG_POST)
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return 0; /* No hotkeys supported */
-}
-#endif /* CONFIG_POST */
-
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
-
- _end = . ;
- PROVIDE (end = .);
-}
else
setenv ("key1", "on");
}
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed (void)
-{
- return (0);
-}
-#endif
* MA 02111-1307 USA
*/
#include <common.h>
+#include <netdev.h>
#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mux.h>
int misc_init_r(void)
{
twl4030_power_init();
- twl4030_led_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
dieid_num_r();
/*
/* platform specific muxes */
MUX_ZOOM1_MDK();
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_LAN91C96
+ rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+ return rc;
+}
+#endif
* MA 02111-1307 USA
*/
#include <common.h>
+#include <netdev.h>
#ifdef CONFIG_STATUS_LED
#include <status_led.h>
#endif
{
zoom2_identify();
twl4030_power_init();
- twl4030_led_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
dieid_num_r();
/*
/* platform specific muxes */
MUX_ZOOM2 ();
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_LAN91C96
+ rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+ return rc;
+}
+#endif
quad_putc_dev (base, '\r');
NS16550_putc ((NS16550_t) base, c);
+ } else {
+ usbtty_putc(c);
}
}
if (zoom2_debug_board_connected ()) {
while ((s != NULL) && (*s != '\0'))
quad_putc_dev (base, *s++);
+ } else {
+ usbtty_puts(s);
}
}
{
if (zoom2_debug_board_connected ())
return NS16550_getc ((NS16550_t) base);
- else
- return 0;
+
+ return usbtty_getc();
}
int quad_tstc_dev (unsigned long base)
{
if (zoom2_debug_board_connected ())
return NS16550_tstc ((NS16550_t) base);
- else
- return 0;
+
+ return usbtty_tstc();
}
void quad_setbrg_dev (unsigned long base)
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_LAN91C96
+ rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+ return rc;
+}
+#endif
return (0);
}
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller *hose)
-{
- unsigned long addr;
-
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB3 devices to 0.
- | Set PLB3 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
- mfsdr(SD0_AMP1, addr);
- mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB3_ACR);
- mtdcr(PLB3_ACR, addr | 0x80000000);
-
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB4 devices to 0.
- +-------------------------------------------------------------------------*/
- mfsdr(SD0_AMP0, addr);
- mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
- mtdcr(PLB4_ACR, addr);
-
- /*-------------------------------------------------------------------------+
- | Set Nebula PLB4 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
- /* Segment0 */
- addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
- addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
- addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
- addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
- mtdcr(PLB0_ACR, addr);
-
- /* Segment1 */
- addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
- addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
- addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
- addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
- mtdcr(PLB1_ACR, addr);
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*--------------------------------------------------------------------------+
- * Set up Direct MMIO registers
- *--------------------------------------------------------------------------*/
- /*--------------------------------------------------------------------------+
- | PowerPC440EPX PCI Master configuration.
- | Map one 1Gig range of PLB/processor addresses to PCI memory space.
- | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
- | Use byte reversed out routines to handle endianess.
- | Make this region non-prefetchable.
- +--------------------------------------------------------------------------*/
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*--------------------------------------------------------------------------+
- * Set up Configuration registers
- *--------------------------------------------------------------------------*/
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*************************************************************************
- * pci_master_init
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
-void pci_master_init(struct pci_controller *hose)
-{
- unsigned short temp_short;
-
- /*--------------------------------------------------------------------------+
- | Write the PowerPC440 EP PCI Configuration regs.
- | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- | Enable PowerPC440 EP to act as a PCI memory target (PTM).
- +--------------------------------------------------------------------------*/
- pci_read_config_word(0, PCI_COMMAND, &temp_short);
- pci_write_config_word(0, PCI_COMMAND,
- temp_short | PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
-
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- /* Cactus is always configured as host. */
- return (1);
-}
-#endif /* defined(CONFIG_PCI) */
-
void hw_watchdog_reset(void)
{
int val;
udelay(500);
gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
- /* Lime memory clock adjusted to 100MHz */
- out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_LIME_CLOCK_100MHZ);
- /* Wait untill time expired. Because of requirements in lime manual */
- udelay(300);
- /* Write lime controller memory parameters */
- out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE);
-
mb862xx.winSizeX = 640;
mb862xx.winSizeY = 480;
mb862xx.gdfBytesPP = 2;
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
-
- _end = . ;
- PROVIDE (end = .);
-}
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
int board_eth_init(bd_t *bis)
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#TEXT_BASE = 0xFFFE0000
TEXT_BASE = 0x18000000
+
+# Use board specific linker script
+LDSCRIPT := $(SRCTREE)/board/ml2/u-boot.lds
#define FIRM_START 0xFFF00000
#endif
-extern int gunzip(void *, int, uchar *, unsigned long *);
extern int mem_test(ulong start, ulong ramsize, int quiet);
#define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
}
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return 0; /* No hotkeys supported */
-}
-#endif
-
extern int mk_date (char *, struct rtc_time *);
int last_stage_init (void)
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
- .bootpg 0xFFFFF000 :
- {
- board/mpl/mip405/init.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/mpl/mip405/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- drivers/net/4xx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/mpl/pip405/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
void ft_blob_update (void *blob, bd_t *bd)
{
int ret, nodeoffset = 0;
- ulong memory_data[2] = {0};
ulong flash_data[4] = {0};
ulong speed = 0;
- memory_data[0] = cpu_to_be32 (bd->bi_memstart);
- memory_data[1] = cpu_to_be32 (bd->bi_memsize);
-
- nodeoffset = fdt_path_offset (blob, "/memory");
- if (nodeoffset >= 0) {
- ret = fdt_setprop (blob, nodeoffset, "reg", memory_data,
- sizeof(memory_data));
- if (ret < 0)
- printf ("ft_blob_update): cannot set /memory/reg "
- "property err:%s\n", fdt_strerror (ret));
- } else {
- /* memory node is required in dts */
- printf ("ft_blob_update(): cannot find /memory node "
- "err:%s\n", fdt_strerror(nodeoffset));
- }
/* update Flash addr, size */
flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
flash_data[3] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE);
*/
#include <common.h>
+#include <fdt_support.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <malloc.h>
return dram_size;
}
-#if defined(CONFIG_POST)
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return 0; /* No hotkeys supported */
-}
-#endif /* CONFIG_POST */
-
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text : {
- /* The start.o file includes the initial jump vector that
- must be located in the beginning. It is the basic run-
- time function that calls all other functions. */
- cpu/ppc4xx/start.o (.text)
-
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
#include <asm/processor.h>
#include <ppc440.h>
#include <asm/io.h>
+#include <asm/4xx_pci.h>
+
#include "../common/nm.h"
DECLARE_GLOBAL_DATA_PTR;
}
/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- */
-void pci_target_init(struct pci_controller *hose)
-{
- if (!board_with_pci()) { return; }
- /*
- * Set up Direct MMIO registers
- *
- * PowerPC440EPX PCI Master configuration.
- * Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
- * 0xA0000000-0xDFFFFFFF
- * Use byte reversed out routines to handle endianess.
- * Make this region non-prefetchable.
- */
- /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM0MA, 0x00000000);
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- /* 512M + No prefetching, and enable region */
- out32r(PCIL0_PMM0MA, 0xE0000001);
-
- /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM1MA, 0x00000000);
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- /* 512M + No prefetching, and enable region */
- out32r(PCIL0_PMM1MA, 0xE0000001);
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*
- * Set up Configuration registers
- */
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-}
-
-/*
- * pci_master_init
- *
+ * Override weak default pci_master_init()
*/
void pci_master_init(struct pci_controller *hose)
{
- unsigned short temp_short;
- if (!board_with_pci()) { return; }
-
- /*---------------------------------------------------------------
- * Write the PowerPC440 EP PCI Configuration regs.
- * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- * Enable PowerPC440 EP to act as a PCI memory target (PTM).
- *--------------------------------------------------------------*/
- pci_read_config_word(0, PCI_COMMAND, &temp_short);
- pci_write_config_word(0, PCI_COMMAND,
- temp_short | PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY);
-}
+ if (!board_with_pci())
+ return;
-/*
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- */
-int is_pci_host(struct pci_controller *hose)
-{
- return 1;
+ __pci_master_init(hose);
}
#endif /* defined(CONFIG_PCI) */
-#if defined(CONFIG_POST)
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return 0; /* No hotkeys supported */
-}
-#endif /* CONFIG_POST */
-
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
-
- _end = . ;
- PROVIDE (end = .);
-}
return dram_size;
}
-#if defined(CONFIG_POST)
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return 0; /* No hotkeys supported */
-}
-#endif /* CONFIG_POST */
-
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text : {
- /* The start.o file includes the initial jump vector that
- must be located in the beginning. It is the basic run-
- time function that calls all other functions. */
- cpu/ppc4xx/start.o (.text)
-
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
#endif
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return 0; /* No hotkeys supported */
-}
-#endif
-
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
int misc_init_r(void)
{
twl4030_power_init();
- twl4030_led_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
#if defined(CONFIG_CMD_NET)
setup_net_chip();
struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
- twl4030_power_init();
- twl4030_led_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
/* Configure GPIOs to output */
writel(~(GPIO14 | GPIO15 | GPIO16 | GPIO23), &gpio1_base->oe);
MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)) /*GPIO_147,*/\
/*UART2_RX*/\
/*Serial Interface (Peripheral boot, Linux console, on AV connector)*/\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX*/\
+ /*RX pulled up to avoid noise when nothing is connected to serial port*/\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX*/\
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX*/\
/*LEDs (Controlled by OMAP)*/\
MUX_VAL(CP(MMC1_DAT6), (IDIS | PTD | DIS | M4)) /*GPIO_128*/\
return dram_size;
}
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller *hose)
-{
- unsigned long addr;
-
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB3 devices to 0.
- | Set PLB3 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
- mfsdr(SD0_AMP1, addr);
- mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB3_ACR);
- mtdcr(PLB3_ACR, addr | 0x80000000);
-
- /*-------------------------------------------------------------------------+
- | Set priority for all PLB4 devices to 0.
- +-------------------------------------------------------------------------*/
- mfsdr(SD0_AMP0, addr);
- mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
- mtdcr(PLB4_ACR, addr);
-
- /*-------------------------------------------------------------------------+
- | Set Nebula PLB4 arbiter to fair mode.
- +-------------------------------------------------------------------------*/
- /* Segment0 */
- addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
- addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
- addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
- addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
- mtdcr(PLB0_ACR, addr);
-
- /* Segment1 */
- addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
- addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
- addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
- addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
- mtdcr(PLB1_ACR, addr);
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*--------------------------------------------------------------------------+
- * Set up Direct MMIO registers
- *--------------------------------------------------------------------------*/
- /*--------------------------------------------------------------------------+
- | PowerPC440 EP PCI Master configuration.
- | Map one 1Gig range of PLB/processor addresses to PCI memory space.
- | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
- | Use byte reversed out routines to handle endianess.
- | Make this region non-prefetchable.
- +--------------------------------------------------------------------------*/
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*--------------------------------------------------------------------------+
- * Set up Configuration registers
- *--------------------------------------------------------------------------*/
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*************************************************************************
- * pci_master_init
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
-void pci_master_init(struct pci_controller *hose)
-{
- unsigned short temp_short;
-
- /*--------------------------------------------------------------------------+
- | Write the PowerPC440 EP PCI Configuration regs.
- | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- | Enable PowerPC440 EP to act as a PCI memory target (PTM).
- +--------------------------------------------------------------------------*/
- pci_read_config_word(0, PCI_COMMAND, &temp_short);
- pci_write_config_word(0, PCI_COMMAND,
- temp_short | PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
-
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- /* PCS440EP is always configured as host. */
- return (1);
-}
-#endif /* defined(CONFIG_PCI) */
-
/*************************************************************************
* hw_watchdog_reset
*
#include <ppc4xx_enet.h>
#include <miiphy.h>
#include <asm/processor.h>
+#include <asm/4xx_pci.h>
DECLARE_GLOBAL_DATA_PTR;
return (0);
}
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller * hose )
+/*
+ * Override weak pci_pre_init()
+ */
+int pci_pre_init(struct pci_controller *hose)
{
- unsigned long strap;
-
- /*--------------------------------------------------------------------------+
- * The ocotea board is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *--------------------------------------------------------------------------*/
- mfsdr(SDR0_SDSTP1, strap);
- if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
- printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+ if (__pci_pre_init(hose) == 0)
return 0;
- }
/* FPGA Init */
- alpr_fpga_init ();
+ alpr_fpga_init();
return 1;
}
-#endif /* defined(CONFIG_PCI) */
/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0SA, 0 ); /* disable */
- out32r( PCIL0_PIM1SA, 0 ); /* disable */
- out32r( PCIL0_PIM2SA, 0 ); /* disable */
- out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIL0_PIM0LAH, 0 );
- out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
- out32r( PCIL0_BAR0, 0 );
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*************************************************************************
- * is_pci_host
+ * Override weak is_pci_host()
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
*
*
************************************************************************/
-#if defined(CONFIG_PCI)
-
static void wait_for_pci_ready(void)
{
/*
out32r(PCIL0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
-
- return (ctrlc());
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/prodrive/alpr/init.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
}
/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller *hose)
-{
- unsigned long strap;
-
- /*--------------------------------------------------------------------------+
- * The P3P440 board is always configured as the host & requires the
- * PCI arbiter to be disabled because it's an PMC module.
- *--------------------------------------------------------------------------*/
- strap = mfdcr(CPC0_STRP1);
- if (strap & 0x00100000) {
- printf("PCI: CPC0_STRP1[PAE] set.\n");
- return 0;
- }
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r(PCIL0_PIM0SA, 0); /* disable */
- out32r(PCIL0_PIM1SA, 0); /* disable */
- out32r(PCIL0_PIM2SA, 0); /* disable */
- out32r(PCIL0_EROMBA, 0); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out32r(PCIL0_PIM0LAH, 0);
- out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
-
- out32r(PCIL0_BAR0, 0);
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
- out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*************************************************************************
- * is_pci_host
+ * Override weak is_pci_host()
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
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- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/prodrive/p3p440/init.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
DECLARE_GLOBAL_DATA_PTR;
/* Prototypes */
-int gunzip(void *, int, unsigned char *, unsigned long *);
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
/* predefine these here for FPGA programming (before including fpga.c) */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
#endif
#endif /* CONFIG_MISC_INIT_R */
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return 0; /* No hotkeys supported */
-}
-
-#endif
#include <i2c.h>
#include <command.h>
#include "ppc440gx_i2c.h"
+#include <asm-ppc/io.h>
#ifdef CONFIG_I2C_BUS1
static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
#endif
+static struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_REGISTERS_BUS1_BASE_ADDRESS;
+
static void _i2c_bus1_reset (void)
{
int i, status;
/* Reset status register */
/* write 1 in SCMP and IRQA to clear these fields */
- out8 (IIC_STS1, 0x0A);
+ out_8 (IIC_STS1, 0x0A);
/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
- out8 (IIC_EXTSTS1, 0x8F);
+ out_8 (IIC_EXTSTS1, 0x8F);
__asm__ volatile ("eieio");
/*
i = 10;
do {
/* Get status */
- status = in8 (IIC_STS1);
+ status = in_8 (IIC_STS1);
udelay (500); /* 500us */
i--;
} while ((status & IIC_STS_PT) && (i > 0));
/* Soft reset controller */
- status = in8 (IIC_XTCNTLSS1);
- out8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST));
+ status = in_8 (IIC_XTCNTLSS1);
+ out_8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST));
__asm__ volatile ("eieio");
/* make sure where in initial state, data hi, clock hi */
- out8 (IIC_DIRECTCNTL1, 0xC);
+ out_8 (IIC_DIRECTCNTL1, 0xC);
for (i = 0; i < 10; i++) {
- if ((in8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) {
+ if ((in_8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) {
/* clock until we get to known state */
- out8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */
+ out_8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */
udelay (100); /* 100us */
- out8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */
+ out_8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */
udelay (100); /* 100us */
} else {
break;
}
}
/* send start condition */
- out8 (IIC_DIRECTCNTL1, 0x4);
+ out_8 (IIC_DIRECTCNTL1, 0x4);
udelay (1000); /* 1ms */
/* send stop condition */
- out8 (IIC_DIRECTCNTL1, 0xC);
+ out_8 (IIC_DIRECTCNTL1, 0xC);
udelay (1000); /* 1ms */
/* Unreset controller */
- out8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST));
+ out_8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST));
udelay (1000); /* 1ms */
}
_i2c_bus1_reset ();
/* clear lo master address */
- out8 (IIC_LMADR1, 0);
+ out_8 (IIC_LMADR1, 0);
/* clear hi master address */
- out8 (IIC_HMADR1, 0);
+ out_8 (IIC_HMADR1, 0);
/* clear lo slave address */
- out8 (IIC_LSADR1, 0);
+ out_8 (IIC_LSADR1, 0);
/* clear hi slave address */
- out8 (IIC_HSADR1, 0);
+ out_8 (IIC_HSADR1, 0);
/* Clock divide Register */
/* get OPB frequency */
divisor = (freqOPB - 1) / 10000000;
if (divisor == 0)
divisor = 1;
- out8 (IIC_CLKDIV1, divisor);
+ out_8 (IIC_CLKDIV1, divisor);
/* no interrupts */
- out8 (IIC_INTRMSK1, 0);
+ out_8 (IIC_INTRMSK1, 0);
/* clear transfer count */
- out8 (IIC_XFRCNT1, 0);
+ out_8 (IIC_XFRCNT1, 0);
/* clear extended control & stat */
/* write 1 in SRC SRS SWC SWS to clear these fields */
- out8 (IIC_XTCNTLSS1, 0xF0);
+ out_8 (IIC_XTCNTLSS1, 0xF0);
/* Mode Control Register
Flush Slave/Master data buffer */
- out8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
+ out_8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
__asm__ volatile ("eieio");
- val = in8(IIC_MDCNTL1);
+ val = in_8(IIC_MDCNTL1);
__asm__ volatile ("eieio");
/* Ignore General Call, slave transfers are ignored,
if( speed >= 400000 ){
val |= IIC_MDCNTL_FSM;
}
- out8 (IIC_MDCNTL1, val);
+ out_8 (IIC_MDCNTL1, val);
/* clear control reg */
- out8 (IIC_CNTL1, 0x00);
+ out_8 (IIC_CNTL1, 0x00);
__asm__ volatile ("eieio");
}
/*
This code tries to use the features of the 405GP i2c
controller. It will transfer up to 4 bytes in one pass
- on the loop. It only does out8(lbz) to the buffer when it
+ on the loop. It only does out_8(lbz) to the buffer when it
is possible to do out16(lhz) transfers.
cmd_type is 0 for write 1 for read.
}
/*Clear Stop Complete Bit*/
- out8(IIC_STS1,IIC_STS_SCMP);
+ out_8(IIC_STS1,IIC_STS_SCMP);
/* Check init */
i=10;
do {
/* Get status */
- status = in8(IIC_STS1);
+ status = in_8(IIC_STS1);
__asm__ volatile("eieio");
i--;
} while ((status & IIC_STS_PT) && (i>0));
return(result);
}
/*flush the Master/Slave Databuffers*/
- out8(IIC_MDCNTL1, ((in8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
+ out_8(IIC_MDCNTL1, ((in_8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
/*need to wait 4 OPB clocks? code below should take that long*/
/* 7-bit adressing */
- out8(IIC_HMADR1,0);
- out8(IIC_LMADR1, chip);
+ out_8(IIC_HMADR1,0);
+ out_8(IIC_LMADR1, chip);
__asm__ volatile("eieio");
tran = 0;
else {
for(j=0; j<bc; j++) {
/* Set buffer */
- out8(IIC_MDBUF1,ptr[tran+j]);
+ out_8(IIC_MDBUF1,ptr[tran+j]);
__asm__ volatile("eieio");
}
}
- out8(IIC_CNTL1, creg );
+ out_8(IIC_CNTL1, creg );
__asm__ volatile("eieio");
/* Transfer is in progress
i=2*5*8;
do {
/* Get status */
- status = in8(IIC_STS1);
+ status = in_8(IIC_STS1);
__asm__ volatile("eieio");
udelay (10);
i--;
if (status & IIC_STS_ERR) {
result = IIC_NOK;
- status = in8 (IIC_EXTSTS1);
+ status = in_8 (IIC_EXTSTS1);
/* Lost arbitration? */
if (status & IIC_EXTSTS_LA)
result = IIC_NOK_LA;
*/
udelay (1);
for(j=0;j<bc;j++) {
- ptr[tran+j] = in8(IIC_MDBUF1);
+ ptr[tran+j] = in_8(IIC_MDBUF1);
__asm__ volatile("eieio");
}
} else
#define I2C_BUS1_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000500)
#define I2C_REGISTERS_BUS1_BASE_ADDRESS I2C_BUS1_BASE_ADDR
-#define IIC_MDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDBUF)
-#define IIC_SDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSDBUF)
-#define IIC_LMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLMADR)
-#define IIC_HMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHMADR)
-#define IIC_CNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCNTL)
-#define IIC_MDCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDCNTL)
-#define IIC_STS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSTS)
-#define IIC_EXTSTS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICEXTSTS)
-#define IIC_LSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLSADR)
-#define IIC_HSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHSADR)
-#define IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IIC0_CLKDIV)
-#define IIC_INTRMSK1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICINTRMSK)
-#define IIC_XFRCNT1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXFRCNT)
-#define IIC_XTCNTLSS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXTCNTLSS)
-#define IIC_DIRECTCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICDIRECTCNTL)
+#define IIC_MDBUF1 (&i2c->mdbuf)
+#define IIC_SDBUF1 (&i2c->sdbuf)
+#define IIC_LMADR1 (&i2c->lmadr)
+#define IIC_HMADR1 (&i2c->hmadr)
+#define IIC_CNTL1 (&i2c->cntl)
+#define IIC_MDCNTL1 (&i2c->mdcntl)
+#define IIC_STS1 (&i2c->sts)
+#define IIC_EXTSTS1 (&i2c->extsts)
+#define IIC_LSADR1 (&i2c->lsadr)
+#define IIC_HSADR1 (&i2c->hsadr)
+#define IIC_CLKDIV1 (&i2c->clkdiv)
+#define IIC_INTRMSK1 (&i2c->intrmsk)
+#define IIC_XFRCNT1 (&i2c->xfrcnt)
+#define IIC_XTCNTLSS1 (&i2c->xtcntlss)
+#define IIC_DIRECTCNTL1 (&i2c->directcntl)
void i2c1_init (int speed, int slaveadd);
int i2c_probe1 (uchar chip);
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller * hose )
-{
- unsigned long strap;
-
- /*--------------------------------------------------------------------------+
- * The metrobox is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *--------------------------------------------------------------------------*/
- mfsdr(SDR0_SDSTP1, strap);
- if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
- printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
- return 0;
- }
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0SA, 0 ); /* disable */
- out32r( PCIL0_PIM1SA, 0 ); /* disable */
- out32r( PCIL0_PIM2SA, 0 ); /* disable */
- out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIL0_PIM0LAH, 0 );
- out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
- out32r( PCIL0_BAR0, 0 );
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-
-/*************************************************************************
- * is_pci_host
- *
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- /* The metrobox is always configured as host. */
- return(1);
-}
-#endif /* defined(CONFIG_PCI) */
-
/*************************************************************************
* board_get_enetaddr
*
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/sandburst/karef/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- drivers/net/4xx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/sandburst/metrobox/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- drivers/net/4xx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- drivers/net/4xx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
SET_STD_PCI_INFO(pci_info[num], 1);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pci1_hose, first_free_busno, 0);
+ &pci1_hose, first_free_busno);
} else {
printf (" PCI: disabled\n");
}
SET_STD_PCIE_INFO(pci_info[num], 1);
printf (" PCIE at base address %lx\n", pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno, 0);
+ &pcie1_hose, first_free_busno);
} else {
printf (" PCIE: disabled\n");
}
dram_size = fixed_sdram ();
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- puts (" DDR: ");
- return dram_size;
-#endif
-
puts (" DDR: ");
return dram_size;
}
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-#define CONFIG_SYS_LIME_SRST ((CONFIG_SYS_LIME_BASE) + 0x01FC002C)
-#define CONFIG_SYS_LIME_CCF ((CONFIG_SYS_LIME_BASE) + 0x01FC0038)
-#define CONFIG_SYS_LIME_MMR ((CONFIG_SYS_LIME_BASE) + 0x01FCFFFC)
-/* Lime clock frequency */
-#define CONFIG_SYS_LIME_CLK_100MHZ 0x00000
-#define CONFIG_SYS_LIME_CLK_133MHZ 0x10000
-/* SDRAM parameter */
-#define CONFIG_SYS_LIME_MMR_VALUE 0x4157BA63
-
-#define DISPLAY_WIDTH 800
-#define DISPLAY_HEIGHT 480
#define DEFAULT_BRIGHTNESS 25
#define BACKLIGHT_ENABLE (1 << 31)
return init_regs;
}
-#define CONFIG_SYS_LIME_CID ((CONFIG_SYS_LIME_BASE) + 0x01FC00F0)
-#define CONFIG_SYS_LIME_REV ((CONFIG_SYS_LIME_BASE) + 0x01FF8084)
int lime_probe(void)
{
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
uint cfg_br2;
uint cfg_or2;
- uint reg;
+ int type;
cfg_br2 = memctl->br2;
cfg_or2 = memctl->or2;
memctl->or2 = 0xfc000410;
memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901;
- /* Try to access GDC ID/Revision registers */
- reg = in_be32((void *)CONFIG_SYS_LIME_CID);
- reg = in_be32((void *)CONFIG_SYS_LIME_CID);
- if (reg == 0x303) {
- reg = in_be32((void *)CONFIG_SYS_LIME_REV);
- reg = in_be32((void *)CONFIG_SYS_LIME_REV);
- reg = ((reg & ~0xff) == 0x20050100) ? 1 : 0;
- } else
- reg = 0;
+ /* Get controller type */
+ type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
/* Restore previous CS2 configuration */
memctl->br2 = 0;
memctl->or2 = cfg_or2;
memctl->br2 = cfg_br2;
- return reg;
+
+ return (type == MB862XX_TYPE_LIME) ? 1 : 0;
}
/* Returns Lime base address */
if (!lime_probe())
return 0;
- /*
- * Reset Lime controller
- */
- out_be32((void *)CONFIG_SYS_LIME_SRST, 0x1);
- udelay(200);
-
- /* Set Lime clock to 133MHz */
- out_be32((void *)CONFIG_SYS_LIME_CCF, CONFIG_SYS_LIME_CLK_133MHZ);
- /* Delay required */
- udelay(300);
- /* Set memory parameters */
- out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE);
-
- mb862xx.winSizeX = DISPLAY_WIDTH;
- mb862xx.winSizeY = DISPLAY_HEIGHT;
+ mb862xx.winSizeX = 800;
+ mb862xx.winSizeY = 480;
mb862xx.gdfIndex = GDF_15BIT_555RGB;
mb862xx.gdfBytesPP = 2;
#endif
-#if defined(CONFIG_POST)
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return 0; /* No hotkeys supported */
-}
-#endif /* CONFIG_POST */
-
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
twl4030_power_init();
- twl4030_led_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
/* Configure GPIOs to output */
writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_LAN91C96
+ rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#if defined(CONFIG_OMAP1610)
#include <./configs/omap1510.h>
#endif
*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_LAN91C96
+ rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+ return rc;
+}
+#endif
* MA 02111-1307 USA
*/
#include <common.h>
+#include <netdev.h>
#include <asm/arch/omap2420.h>
#include <asm/io.h>
#include <asm/arch/bits.h>
}
}
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_LAN91C96
+ rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#if defined(CONFIG_OMAP1610)
#include <./configs/omap1510.h>
#endif
return (0);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_LAN91C96
+ rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#if defined(CONFIG_OMAP730)
#include <./configs/omap730.h>
#endif
*MuxConfReg &= (0xFF1FFFFF);
*MuxConfReg &= (0xF1FFFFFF);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_LAN91C96
+ rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+ return rc;
+}
+#endif
* MA 02111-1307 USA
*/
#include <common.h>
+#include <netdev.h>
#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mux.h>
#define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b)
/**
- * @brief ether_init Take the Ethernet controller out of reset and wait
+ * @brief board_eth_init Take the Ethernet controller out of reset and wait
* for the EEPROM load to complete.
*/
-static void ether_init(void)
+int board_eth_init(bd_t *bis)
{
-#ifdef CONFIG_DRIVER_LAN91C96
+ int rc = 0;
+#ifdef CONFIG_LAN91C96
int cnt = 20;
writew(0x0, LAN_RESET_REGISTER);
writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG);
udelay(1000);
+ rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
reset_err_out:
- return;
#endif
+ return rc;
}
/**
* VSIM - off (init, variable) for MMC1.DAT[3..7], SIM
* VPLL2 - 1.8V
*/
- ether_init();
return 0;
}
twl4030_power_init();
#ifdef CONFIG_TWL4030_LED
- twl4030_led_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
#endif
#ifdef CONFIG_DRIVER_DM9000
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_PCI1
- uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR;
struct pci_controller *hose = &pci1_hose;
struct pci_region *r = hose->regions;
/* PORPLLSR[16] */
uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
- uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);
+ int pci_agent = fsl_setup_hose(hose, CONFIG_SYS_PCI1_ADDR);
uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_PCIE1
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR;
struct pci_controller *hose = &pcie1_hose;
- int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
+ int pcie_ep;
struct pci_region *r = hose->regions;
int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+ pcie_ep = fsl_setup_hose(hose, CONFIG_SYS_PCIE1_ADDR);
+
if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("PCIe: %s, base address %x",
pcie_ep ? "End point" : "Root complex", (uint)pci);
return 0;
}
-
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed (void)
-{
- return 0; /* No hotkeys supported */
-}
-#endif
*/
#include <common.h>
+#include <fdt_support.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <malloc.h>
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
- board/w7o/init.o (.text)
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/xes/xpedite1000/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
}
/*
+ * Override weak pci_pre_init()
+ *
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*/
-
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose)
{
}
#endif /* defined(CONFIG_PCI) */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-/*
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-void pci_target_init(struct pci_controller * hose)
-{
- /* Disable everything */
- out32r(PCIL0_PIM0SA, 0);
- out32r(PCIL0_PIM1SA, 0);
- out32r(PCIL0_PIM2SA, 0);
- out32r(PCIL0_EROMBA, 0); /* disable expansion rom */
-
- /*
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- */
- out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out32r(PCIL0_PIM0LAH, 0);
- out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
-
- out32r(PCIL0_BAR0, 0);
-
- /* Program the board's subsystem id/vendor id */
- out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
- out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
#if defined(CONFIG_PCI)
/*
+ * Override weak is_pci_host()
+ *
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
#TEXT_BASE = 0xFFFE0000
TEXT_BASE = 0x04000000
+
+# Use board specific linker script
+LDSCRIPT := $(SRCTREE)/board/xilinx/ml300/u-boot.lds
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
# core
COBJS-y += main.o
-COBJS-y += circbuf.o
COBJS-y += console.o
COBJS-y += command.o
COBJS-y += dlmalloc.o
# core command
COBJS-y += cmd_boot.o
COBJS-y += cmd_bootm.o
+COBJS-y += cmd_help.o
COBJS-y += cmd_nvedit.o
+COBJS-y += cmd_version.o
# environment
COBJS-y += env_common.o
endif
COBJS-$(CONFIG_CMD_DISPLAY) += cmd_display.o
COBJS-$(CONFIG_CMD_DTT) += cmd_dtt.o
+COBJS-$(CONFIG_CMD_ECHO) += cmd_echo.o
COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += cmd_eeprom.o
COBJS-$(CONFIG_CMD_EEPROM) += cmd_eeprom.o
COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o
+COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o
COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o
COBJS-$(CONFIG_CMD_FAT) += cmd_fat.o
COBJS-$(CONFIG_CMD_FDC)$(CONFIG_CMD_FDOS) += cmd_fdc.o
COBJS-$(CONFIG_CMD_MMC) += cmd_mmc.o
COBJS-$(CONFIG_MP) += cmd_mp.o
COBJS-$(CONFIG_CMD_MTDPARTS) += cmd_mtdparts.o
-COBJS-y += cmd_nand.o
+COBJS-$(CONFIG_CMD_NAND) += cmd_nand.o
COBJS-$(CONFIG_CMD_NET) += cmd_net.o
COBJS-$(CONFIG_CMD_ONENAND) += cmd_onenand.o
COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o
COBJS-$(CONFIG_CMD_SPIBOOTLDR) += cmd_spibootldr.o
COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o
COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
+COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_test.o
COBJS-$(CONFIG_CMD_TSI148) += cmd_tsi148.o
COBJS-$(CONFIG_CMD_UBI) += cmd_ubi.o
COBJS-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o
static int bmp_info (ulong addr);
static int bmp_display (ulong addr, int x, int y);
-int gunzip(void *, int, unsigned char *, unsigned long *);
-
/*
* Allocate and decompress a BMP image using gunzip().
*
#include <lzma/LzmaTools.h>
#endif /* CONFIG_LZMA */
+#ifdef CONFIG_LZO
+#include <linux/lzo.h>
+#endif /* CONFIG_LZO */
+
DECLARE_GLOBAL_DATA_PTR;
-extern int gunzip (void *dst, int dstlen, unsigned char *src, unsigned long *lenp);
#ifndef CONFIG_SYS_BOOTM_LEN
#define CONFIG_SYS_BOOTM_LEN 0x800000 /* use 8MByte as default max gunzip size */
#endif
static boot_os_fn do_bootm_integrity;
#endif
-boot_os_fn * boot_os[] = {
+static boot_os_fn *boot_os[] = {
#ifdef CONFIG_BOOTM_LINUX
[IH_OS_LINUX] = do_bootm_linux,
#endif
*load_end = load + unc_len;
break;
#endif /* CONFIG_LZMA */
+#ifdef CONFIG_LZO
+ case IH_COMP_LZO:
+ printf (" Uncompressing %s ... ", type_name);
+
+ int ret = lzop_decompress((const unsigned char *)image_start,
+ image_len, (unsigned char *)load,
+ &unc_len);
+ if (ret != LZO_E_OK) {
+ printf ("LZO: uncompress or overwrite error %d "
+ "- must RESET board to recover\n", ret);
+ if (boot_progress)
+ show_boot_progress (-6);
+ return BOOTM_ERR_RESET;
+ }
+
+ *load_end = load + unc_len;
+ break;
+#endif /* CONFIG_LZO */
default:
printf ("Unimplemented compression type %d\n", comp);
return BOOTM_ERR_UNIMPLEMENTED;
#ifdef CONFIG_OF_LIBFDT
U_BOOT_CMD_MKENT(fdt, 0, 1, (void *)BOOTM_STATE_FDT, "", ""),
#endif
- U_BOOT_CMD_MKENT(bdt, 0, 1, (void *)BOOTM_STATE_OS_BD_T, "", ""),
U_BOOT_CMD_MKENT(cmdline, 0, 1, (void *)BOOTM_STATE_OS_CMDLINE, "", ""),
+ U_BOOT_CMD_MKENT(bdt, 0, 1, (void *)BOOTM_STATE_OS_BD_T, "", ""),
U_BOOT_CMD_MKENT(prep, 0, 1, (void *)BOOTM_STATE_OS_PREP, "", ""),
U_BOOT_CMD_MKENT(go, 0, 1, (void *)BOOTM_STATE_OS_GO, "", ""),
};
}
break;
#endif
-#ifdef CONFIG_OF_LIBFDT
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_SYS_BOOTMAPSZ)
case BOOTM_STATE_FDT:
{
ulong bootmap_base = getenv_bootm_low();
#if defined(CONFIG_OF_LIBFDT)
"\tfdt - relocate flat device tree\n"
#endif
- "\tbdt - OS specific bd_t processing\n"
"\tcmdline - OS specific command line processing/setup\n"
+ "\tbdt - OS specific bd_t processing\n"
"\tprep - OS specific prep before relocation or go\n"
"\tgo - start OS"
);
#include <common.h>
#include <command.h>
-#if defined(CONFIG_CMD_CACHE)
-
static int on_off (const char *);
int do_icache ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
"[on, off]\n"
" - enable or disable data (writethrough) cache"
);
-
-#endif
/* and write to RTC */
rcode = rtc_set (&tm);
if(rcode)
- puts("## Set date failled\n");
+ puts("## Set date failed\n");
} else {
- puts("## Get date failled\n");
+ puts("## Get date failed\n");
}
}
/* FALL TROUGH */
rcode = rtc_get (&tm);
if (rcode) {
- puts("## Get date failled\n");
+ puts("## Get date failed\n");
break;
}
--- /dev/null
+/*
+ * Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+int do_echo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int i;
+ int putnl = 1;
+
+ for (i = 1; i < argc; i++) {
+ char *p = argv[i], c;
+
+ if (i > 1)
+ putc(' ');
+ while ((c = *p++) != '\0') {
+ if (c == '\\' && *p == 'c') {
+ putnl = 0;
+ p++;
+ } else {
+ putc(c);
+ }
+ }
+ }
+
+ if (putnl)
+ putc('\n');
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ echo, CONFIG_SYS_MAXARGS, 1, do_echo,
+ "echo args to console",
+ "[args..]\n"
+ " - echo args to console; \\c suppresses newline"
+);
/*
- * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
+ * Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
+#include <common.h>
+#include <command.h>
-OUTPUT_FORMAT("elf32-nios")
-OUTPUT_ARCH(nios)
-ENTRY(_start)
-
-SECTIONS
+int do_exit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- .text :
- {
- *(.text)
- }
- __text_end = .;
-
- . = ALIGN(4);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- __rodata_end = .;
+ int r;
- . = ALIGN(4);
- .data :
- {
- *(.data)
- }
- . = ALIGN(4);
- __data_end = .;
+ r = 0;
+ if (argc > 1)
+ r = simple_strtoul(argv[1], NULL, 10);
- __bss_start = .;
- . = ALIGN(4);
- .bss (NOLOAD) :
- {
- *(.bss)
- }
- . = ALIGN(4);
- __bss_end = .;
- _end = .;
+ return -r - 2;
}
+
+U_BOOT_CMD(
+ exit, 2, 1, do_exit,
+ "exit script",
+ ""
+);
} else if (strncmp(argv[1], "me", 2) == 0) {
uint64_t addr, size;
int err;
-#ifdef CONFIG_SYS_64BIT_STRTOUL
- addr = simple_strtoull(argv[2], NULL, 16);
- size = simple_strtoull(argv[3], NULL, 16);
-#else
- addr = simple_strtoul(argv[2], NULL, 16);
- size = simple_strtoul(argv[3], NULL, 16);
-#endif
+ addr = simple_strtoull(argv[2], NULL, 16);
+ size = simple_strtoull(argv[3], NULL, 16);
err = fdt_fixup_memory(working_fdt, addr, size);
if (err < 0)
return err;
} else if (argv[2][0] == 'a') {
uint64_t addr, size;
int err;
-#ifdef CONFIG_SYS_64BIT_STRTOUL
addr = simple_strtoull(argv[3], NULL, 16);
size = simple_strtoull(argv[4], NULL, 16);
-#else
- addr = simple_strtoul(argv[3], NULL, 16);
- size = simple_strtoul(argv[4], NULL, 16);
-#endif
err = fdt_add_mem_rsv(working_fdt, addr, size);
if (err < 0) {
--- /dev/null
+/*
+ * Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+int do_help(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ return _do_help(&__u_boot_cmd_start,
+ &__u_boot_cmd_end - &__u_boot_cmd_start,
+ cmdtp, flag, argc, argv);
+}
+
+U_BOOT_CMD(
+ help, CONFIG_SYS_MAXARGS, 1, do_help,
+ "print command description/usage",
+ "\n"
+ " - print brief description of all commands\n"
+ "help command ...\n"
+ " - print detailed usage of 'command'"
+);
+
+/* This does not use the U_BOOT_CMD macro as ? can't be used in symbol names */
+cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = {
+ "?", CONFIG_SYS_MAXARGS, 1, do_help,
+ "alias for 'help'",
+#ifdef CONFIG_SYS_LONGHELP
+ ""
+#endif /* CONFIG_SYS_LONGHELP */
+};
/*
* Wait for the write to complete. The write can take
* up to 10mSec (we allow a little more time).
- *
- * On some chips, while the write is in progress, the
- * chip doesn't respond. This apparently isn't a
- * universal feature so we don't take advantage of it.
*/
/*
* No write delay with FRAM devices.
#if !defined(CONFIG_SYS_I2C_FRAM)
udelay(11000);
#endif
-
-#if 0
- for (timeout = 0; timeout < 10; timeout++) {
- udelay(2000);
- if (i2c_probe(chip) == 0)
- break;
- }
-#endif
}
return (0);
}
if ((c&(ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR)) != ATA_STAT_DRQ) {
-#if defined(CONFIG_SYS_64BIT_LBA) && defined(CONFIG_SYS_64BIT_VSPRINTF)
+#if defined(CONFIG_SYS_64BIT_LBA)
printf ("Error (no IRQ) dev %d blk %Ld: status 0x%02x\n",
device, blknr, c);
#else
c = ide_wait (device, IDE_TIME_OUT); /* can't take over 500 ms */
if ((c&(ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR)) != ATA_STAT_DRQ) {
-#if defined(CONFIG_SYS_64BIT_LBA) && defined(CONFIG_SYS_64BIT_VSPRINTF)
+#if defined(CONFIG_SYS_64BIT_LBA)
printf ("Error (no IRQ) dev %d blk %Ld: status 0x%02x\n",
device, blknr, c);
#else
"enable or disable interrupts",
"[on, off]"
);
+
+/* Implemented in $(CPU)/interrupts.c */
+int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+U_BOOT_CMD(
+ irqinfo, 1, 1, do_irqinfo,
+ "print information about IRQs",
+ ""
+);
#include <common.h>
-#if defined(CONFIG_CMD_LICENSE)
-
/* COPYING is currently 15951 bytes in size */
#define LICENSE_MAX 20480
#include <command.h>
#include <malloc.h>
#include <license.h>
-int gunzip(void *, int, unsigned char *, unsigned long *);
int do_license(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
"print GPL license text",
""
);
-
-#endif /* CONFIG_CMD_LICENSE */
#endif
#ifdef CONFIG_CMD_UNZIP
-int gunzip (void *, int, unsigned char *, unsigned long *);
-
int do_unzip ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
unsigned long src, dst;
#include <common.h>
#include <command.h>
-#if defined (CONFIG_CMD_MG_DISK)
-
#include <mg_disk.h>
int do_mg_disk_cmd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
" - sector read : mgd readsec [sector] [to] [counts]\n"
" - sector write : mgd writesec [from] [sector] [counts]"
);
-
-#endif
return 0;
}
-/* Implemented in $(CPU)/interrupts.c */
-#if defined(CONFIG_CMD_IRQ)
-int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
-
-U_BOOT_CMD(
- irqinfo, 1, 1, do_irqinfo,
- "print information about IRQs",
- ""
-);
-#endif
-
U_BOOT_CMD(
sleep , 2, 1, do_sleep,
"delay execution for some time",
*/
#include <common.h>
-
-
-/*
- *
- * New NAND support
- *
- */
-#include <common.h>
#include <linux/mtd/mtd.h>
-
-#if defined(CONFIG_CMD_NAND)
-
#include <command.h>
#include <watchdog.h>
#include <malloc.h>
"boot from NAND device",
"[partition] | [[[loadAddr] dev] offset]"
);
-#endif
#include <asm/io.h>
-#if !defined(CONFIG_SYS_64BIT_VSPRINTF)
-#warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output!
-#endif
-
static struct mtd_info *mtd;
static loff_t next_ofs;
--- /dev/null
+/*
+ * Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ char **ap;
+ int left, adv, expr, last_expr, neg, last_cmp;
+
+ /* args? */
+ if (argc < 3)
+ return 1;
+
+#if 0
+ {
+ printf("test:");
+ left = 1;
+ while (argv[left])
+ printf(" %s", argv[left++]);
+ }
+#endif
+
+ last_expr = 0;
+ left = argc - 1; ap = argv + 1;
+ if (left > 0 && strcmp(ap[0], "!") == 0) {
+ neg = 1;
+ ap++;
+ left--;
+ } else
+ neg = 0;
+
+ expr = -1;
+ last_cmp = -1;
+ last_expr = -1;
+ while (left > 0) {
+
+ if (strcmp(ap[0], "-o") == 0 || strcmp(ap[0], "-a") == 0)
+ adv = 1;
+ else if (strcmp(ap[0], "-z") == 0 || strcmp(ap[0], "-n") == 0)
+ adv = 2;
+ else
+ adv = 3;
+
+ if (left < adv) {
+ expr = 1;
+ break;
+ }
+
+ if (adv == 1) {
+ if (strcmp(ap[0], "-o") == 0) {
+ last_expr = expr;
+ last_cmp = 0;
+ } else if (strcmp(ap[0], "-a") == 0) {
+ last_expr = expr;
+ last_cmp = 1;
+ } else {
+ expr = 1;
+ break;
+ }
+ }
+
+ if (adv == 2) {
+ if (strcmp(ap[0], "-z") == 0)
+ expr = strlen(ap[1]) == 0 ? 1 : 0;
+ else if (strcmp(ap[0], "-n") == 0)
+ expr = strlen(ap[1]) == 0 ? 0 : 1;
+ else {
+ expr = 1;
+ break;
+ }
+
+ if (last_cmp == 0)
+ expr = last_expr || expr;
+ else if (last_cmp == 1)
+ expr = last_expr && expr;
+ last_cmp = -1;
+ }
+
+ if (adv == 3) {
+ if (strcmp(ap[1], "=") == 0)
+ expr = strcmp(ap[0], ap[2]) == 0;
+ else if (strcmp(ap[1], "!=") == 0)
+ expr = strcmp(ap[0], ap[2]) != 0;
+ else if (strcmp(ap[1], ">") == 0)
+ expr = strcmp(ap[0], ap[2]) > 0;
+ else if (strcmp(ap[1], "<") == 0)
+ expr = strcmp(ap[0], ap[2]) < 0;
+ else if (strcmp(ap[1], "-eq") == 0)
+ expr = simple_strtol(ap[0], NULL, 10) == simple_strtol(ap[2], NULL, 10);
+ else if (strcmp(ap[1], "-ne") == 0)
+ expr = simple_strtol(ap[0], NULL, 10) != simple_strtol(ap[2], NULL, 10);
+ else if (strcmp(ap[1], "-lt") == 0)
+ expr = simple_strtol(ap[0], NULL, 10) < simple_strtol(ap[2], NULL, 10);
+ else if (strcmp(ap[1], "-le") == 0)
+ expr = simple_strtol(ap[0], NULL, 10) <= simple_strtol(ap[2], NULL, 10);
+ else if (strcmp(ap[1], "-gt") == 0)
+ expr = simple_strtol(ap[0], NULL, 10) > simple_strtol(ap[2], NULL, 10);
+ else if (strcmp(ap[1], "-ge") == 0)
+ expr = simple_strtol(ap[0], NULL, 10) >= simple_strtol(ap[2], NULL, 10);
+ else {
+ expr = 1;
+ break;
+ }
+
+ if (last_cmp == 0)
+ expr = last_expr || expr;
+ else if (last_cmp == 1)
+ expr = last_expr && expr;
+ last_cmp = -1;
+ }
+
+ ap += adv; left -= adv;
+ }
+
+ if (neg)
+ expr = !expr;
+
+ expr = !expr;
+
+ debug (": returns %d\n", expr);
+
+ return expr;
+}
+
+U_BOOT_CMD(
+ test, CONFIG_SYS_MAXARGS, 1, do_test,
+ "minimal test like /bin/sh",
+ "[args..]"
+);
+
+int do_false(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ return 1;
+}
+
+U_BOOT_CMD(
+ false, CONFIG_SYS_MAXARGS, 1, do_false,
+ "do nothing, unsuccessfully",
+ NULL
+);
+
+int do_true(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ return 0;
+}
+
+U_BOOT_CMD(
+ true, CONFIG_SYS_MAXARGS, 1, do_true,
+ "do nothing, successfully",
+ NULL
+);
{
if (dev->descriptor.bDescriptorType == USB_DT_DEVICE) {
printf("%d: %s, USB Revision %x.%x\n", dev->devnum,
- usb_get_class_desc(dev->config.if_desc[0].bInterfaceClass),
+ usb_get_class_desc(dev->config.if_desc[0].desc.bInterfaceClass),
(dev->descriptor.bcdUSB>>8) & 0xff,
dev->descriptor.bcdUSB & 0xff);
} else {
printf(" - Class: (from Interface) %s\n",
usb_get_class_desc(
- dev->config.if_desc[0].bInterfaceClass));
+ dev->config.if_desc[0].desc.bInterfaceClass));
}
printf(" - PacketSize: %d Configurations: %d\n",
dev->descriptor.bMaxPacketSize0,
}
-void usb_display_conf_desc(struct usb_config_descriptor *config,
+void usb_display_conf_desc(struct usb_configuration_descriptor *config,
struct usb_device *dev)
{
printf(" Configuration: %d\n", config->bConfigurationValue);
printf(" - Interfaces: %d %s%s%dmA\n", config->bNumInterfaces,
(config->bmAttributes & 0x40) ? "Self Powered " : "Bus Powered ",
(config->bmAttributes & 0x20) ? "Remote Wakeup " : "",
- config->MaxPower*2);
+ config->bMaxPower*2);
if (config->iConfiguration) {
printf(" - ");
usb_display_string(dev, config->iConfiguration);
/* main routine to diasplay the configs, interfaces and endpoints */
void usb_display_config(struct usb_device *dev)
{
- struct usb_config_descriptor *config;
- struct usb_interface_descriptor *ifdesc;
+ struct usb_config *config;
+ struct usb_interface *ifdesc;
struct usb_endpoint_descriptor *epdesc;
int i, ii;
config = &dev->config;
- usb_display_conf_desc(config, dev);
+ usb_display_conf_desc(&config->desc, dev);
for (i = 0; i < config->no_of_if; i++) {
ifdesc = &config->if_desc[i];
- usb_display_if_desc(ifdesc, dev);
+ usb_display_if_desc(&ifdesc->desc, dev);
for (ii = 0; ii < ifdesc->no_of_ep; ii++) {
epdesc = &ifdesc->ep_desc[ii];
usb_display_ep_desc(epdesc);
pre[index++] = has_child ? '|' : ' ';
pre[index] = 0;
printf(" %s (%s, %dmA)\n", usb_get_class_desc(
- dev->config.if_desc[0].bInterfaceClass),
+ dev->config.if_desc[0].desc.bInterfaceClass),
portspeed(dev->speed),
- dev->config.MaxPower * 2);
+ dev->config.desc.bMaxPower * 2);
if (strlen(dev->mf) || strlen(dev->prod) || strlen(dev->serial))
printf(" %s %s %s %s\n", pre, dev->mf, dev->prod, dev->serial);
printf(" %s\n", pre);
return 1;
}
}
+ if (strcmp(argv[1], "write") == 0) {
+ if (usb_stor_curr_dev < 0) {
+ printf("no current device selected\n");
+ return 1;
+ }
+ if (argc == 5) {
+ unsigned long addr = simple_strtoul(argv[2], NULL, 16);
+ unsigned long blk = simple_strtoul(argv[3], NULL, 16);
+ unsigned long cnt = simple_strtoul(argv[4], NULL, 16);
+ unsigned long n;
+ printf("\nUSB write: device %d block # %ld, count %ld"
+ " ... ", usb_stor_curr_dev, blk, cnt);
+ stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+ n = stor_dev->block_write(usb_stor_curr_dev, blk, cnt,
+ (ulong *)addr);
+ printf("%ld blocks write: %s\n", n,
+ (n == cnt) ? "OK" : "ERROR");
+ if (n == cnt)
+ return 0;
+ return 1;
+ }
+ }
if (strncmp(argv[1], "dev", 3) == 0) {
if (argc == 3) {
int dev = (int)simple_strtoul(argv[2], NULL, 10);
" devices\n"
"usb read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"
" to memory address `addr'"
+ "usb write addr blk# cnt - write `cnt' blocks starting at block `blk#'\n"
+ " from memory address `addr'"
);
--- /dev/null
+/*
+ * Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+extern char version_string[];
+
+int do_version(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ printf("\n%s\n", version_string);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ version, 1, 1, do_version,
+ "print monitor version",
+ ""
+);
#include <common.h>
#include <command.h>
-int
-do_version (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- extern char version_string[];
- printf ("\n%s\n", version_string);
- return 0;
-}
-
-U_BOOT_CMD(
- version, 1, 1, do_version,
- "print monitor version",
- ""
-);
-
-#if defined(CONFIG_CMD_ECHO)
-
-int
-do_echo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- int i, putnl = 1;
-
- for (i = 1; i < argc; i++) {
- char *p = argv[i], c;
-
- if (i > 1)
- putc(' ');
- while ((c = *p++) != '\0') {
- if (c == '\\' && *p == 'c') {
- putnl = 0;
- p++;
- } else {
- putc(c);
- }
- }
- }
-
- if (putnl)
- putc('\n');
- return 0;
-}
-
-U_BOOT_CMD(
- echo, CONFIG_SYS_MAXARGS, 1, do_echo,
- "echo args to console",
- "[args..]\n"
- " - echo args to console; \\c suppresses newline"
-);
-
-#endif
-
-#ifdef CONFIG_SYS_HUSH_PARSER
-
-int
-do_test (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- char **ap;
- int left, adv, expr, last_expr, neg, last_cmp;
-
- /* args? */
- if (argc < 3)
- return 1;
-
-#if 0
- {
- printf("test:");
- left = 1;
- while (argv[left])
- printf(" %s", argv[left++]);
- }
-#endif
-
- last_expr = 0;
- left = argc - 1; ap = argv + 1;
- if (left > 0 && strcmp(ap[0], "!") == 0) {
- neg = 1;
- ap++;
- left--;
- } else
- neg = 0;
-
- expr = -1;
- last_cmp = -1;
- last_expr = -1;
- while (left > 0) {
-
- if (strcmp(ap[0], "-o") == 0 || strcmp(ap[0], "-a") == 0)
- adv = 1;
- else if (strcmp(ap[0], "-z") == 0 || strcmp(ap[0], "-n") == 0)
- adv = 2;
- else
- adv = 3;
-
- if (left < adv) {
- expr = 1;
- break;
- }
-
- if (adv == 1) {
- if (strcmp(ap[0], "-o") == 0) {
- last_expr = expr;
- last_cmp = 0;
- } else if (strcmp(ap[0], "-a") == 0) {
- last_expr = expr;
- last_cmp = 1;
- } else {
- expr = 1;
- break;
- }
- }
-
- if (adv == 2) {
- if (strcmp(ap[0], "-z") == 0)
- expr = strlen(ap[1]) == 0 ? 1 : 0;
- else if (strcmp(ap[0], "-n") == 0)
- expr = strlen(ap[1]) == 0 ? 0 : 1;
- else {
- expr = 1;
- break;
- }
-
- if (last_cmp == 0)
- expr = last_expr || expr;
- else if (last_cmp == 1)
- expr = last_expr && expr;
- last_cmp = -1;
- }
-
- if (adv == 3) {
- if (strcmp(ap[1], "=") == 0)
- expr = strcmp(ap[0], ap[2]) == 0;
- else if (strcmp(ap[1], "!=") == 0)
- expr = strcmp(ap[0], ap[2]) != 0;
- else if (strcmp(ap[1], ">") == 0)
- expr = strcmp(ap[0], ap[2]) > 0;
- else if (strcmp(ap[1], "<") == 0)
- expr = strcmp(ap[0], ap[2]) < 0;
- else if (strcmp(ap[1], "-eq") == 0)
- expr = simple_strtol(ap[0], NULL, 10) == simple_strtol(ap[2], NULL, 10);
- else if (strcmp(ap[1], "-ne") == 0)
- expr = simple_strtol(ap[0], NULL, 10) != simple_strtol(ap[2], NULL, 10);
- else if (strcmp(ap[1], "-lt") == 0)
- expr = simple_strtol(ap[0], NULL, 10) < simple_strtol(ap[2], NULL, 10);
- else if (strcmp(ap[1], "-le") == 0)
- expr = simple_strtol(ap[0], NULL, 10) <= simple_strtol(ap[2], NULL, 10);
- else if (strcmp(ap[1], "-gt") == 0)
- expr = simple_strtol(ap[0], NULL, 10) > simple_strtol(ap[2], NULL, 10);
- else if (strcmp(ap[1], "-ge") == 0)
- expr = simple_strtol(ap[0], NULL, 10) >= simple_strtol(ap[2], NULL, 10);
- else {
- expr = 1;
- break;
- }
-
- if (last_cmp == 0)
- expr = last_expr || expr;
- else if (last_cmp == 1)
- expr = last_expr && expr;
- last_cmp = -1;
- }
-
- ap += adv; left -= adv;
- }
-
- if (neg)
- expr = !expr;
-
- expr = !expr;
-
- debug (": returns %d\n", expr);
-
- return expr;
-}
-
-U_BOOT_CMD(
- test, CONFIG_SYS_MAXARGS, 1, do_test,
- "minimal test like /bin/sh",
- "[args..]"
-);
-
-int
-do_exit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- int r;
-
- r = 0;
- if (argc > 1)
- r = simple_strtoul(argv[1], NULL, 10);
-
- return -r - 2;
-}
-
-U_BOOT_CMD(
- exit, 2, 1, do_exit,
- "exit script",
- ""
-);
-
-
-#endif
-
/*
* Use puts() instead of printf() to avoid printf buffer overflow
* for long help messages
return rcode;
}
-int do_help (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- return _do_help(&__u_boot_cmd_start,
- &__u_boot_cmd_end - &__u_boot_cmd_start,
- cmdtp, flag, argc, argv);
-}
-
-
-U_BOOT_CMD(
- help, CONFIG_SYS_MAXARGS, 1, do_help,
- "print online help",
- "[command ...]\n"
- " - show help information (for 'command')\n"
- "'help' prints online help for the monitor commands.\n\n"
- "Without arguments, it prints a short usage message for all commands.\n\n"
- "To get detailed help information for specific commands you can type\n"
- "'help' with one or more command names as arguments."
-);
-
-/* This does not use the U_BOOT_CMD macro as ? can't be used in symbol names */
-#ifdef CONFIG_SYS_LONGHELP
-cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = {
- "?", CONFIG_SYS_MAXARGS, 1, do_help,
- "alias for 'help'",
- ""
-};
-#else
-cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = {
- "?", CONFIG_SYS_MAXARGS, 1, do_help,
- "alias for 'help'"
-};
-#endif /* CONFIG_SYS_LONGHELP */
-
/***************************************************************************
* find command table entry for a command
*/
return (void *)old;
}
-#ifndef CONFIG_X86
-/*
- * x86 boards use a slightly different init sequence thus they implement
- * their own version of mem_malloc_init()
- */
void mem_malloc_init(ulong start, ulong size)
{
mem_malloc_start = start;
memset((void *)mem_malloc_start, 0, size);
}
-#endif
/* field-extraction macros */
void env_relocate_spec(void)
{
struct mtd_info *mtd = &onenand_mtd;
+#ifdef CONFIG_ENV_ADDR_FLEX
+ struct onenand_chip *this = &onenand_chip;
+#endif
loff_t env_addr;
int use_default = 0;
size_t retlen;
env_addr = CONFIG_ENV_ADDR;
-
+#ifdef CONFIG_ENV_ADDR_FLEX
+ if (FLEXONENAND(this))
+ env_addr = CONFIG_ENV_ADDR_FLEX;
+#endif
/* Check OneNAND exist */
if (mtd->writesize)
/* Ignore read fail */
int saveenv(void)
{
struct mtd_info *mtd = &onenand_mtd;
+#ifdef CONFIG_ENV_ADDR_FLEX
+ struct onenand_chip *this = &onenand_chip;
+#endif
loff_t env_addr = CONFIG_ENV_ADDR;
struct erase_info instr = {
.callback = NULL,
size_t retlen;
instr.len = CONFIG_ENV_SIZE;
+#ifdef CONFIG_ENV_ADDR_FLEX
+ if (FLEXONENAND(this)) {
+ env_addr = CONFIG_ENV_ADDR_FLEX;
+ instr.len = CONFIG_ENV_SIZE_FLEX;
+ instr.len <<= onenand_mtd.eraseregions[0].numblocks == 1 ?
+ 1 : 0;
+ }
+#endif
instr.addr = env_addr;
instr.mtd = mtd;
if (mtd->erase(mtd, &instr)) {
return XF_VERSION;
}
-void jumptable_init (void)
-{
- int i;
-
- gd->jt = (void **) malloc (XF_MAX * sizeof (void *));
- for (i = 0; i < XF_MAX; i++)
- gd->jt[i] = (void *) dummy;
+/* Reuse _exports.h with a little trickery to avoid bitrot */
+#define EXPORT_FUNC(sym) gd->jt[XF_##sym] = (void *)sym;
- gd->jt[XF_get_version] = (void *) get_version;
- gd->jt[XF_malloc] = (void *) malloc;
- gd->jt[XF_free] = (void *) free;
- gd->jt[XF_getenv] = (void *) getenv;
- gd->jt[XF_setenv] = (void *) setenv;
- gd->jt[XF_get_timer] = (void *) get_timer;
- gd->jt[XF_simple_strtoul] = (void *) simple_strtoul;
- gd->jt[XF_udelay] = (void *) udelay;
- gd->jt[XF_simple_strtol] = (void *) simple_strtol;
- gd->jt[XF_strcmp] = (void *) strcmp;
-#if defined(CONFIG_I386) || defined(CONFIG_PPC)
- gd->jt[XF_install_hdlr] = (void *) irq_install_handler;
- gd->jt[XF_free_hdlr] = (void *) irq_free_handler;
-#endif /* I386 || PPC */
-#if defined(CONFIG_CMD_I2C)
- gd->jt[XF_i2c_write] = (void *) i2c_write;
- gd->jt[XF_i2c_read] = (void *) i2c_read;
+#if !defined(CONFIG_I386) && !defined(CONFIG_PPC)
+# define install_hdlr dummy
+# define free_hdlr dummy
+#else /* kludge for non-standard function naming */
+# define install_hdlr irq_install_handler
+# define free_hdlr irq_free_handler
+#endif
+#ifndef CONFIG_CMD_I2C
+# define i2c_write dummy
+# define i2c_read dummy
#endif
-#ifdef CONFIG_CMD_SPI
- gd->jt[XF_spi_init] = (void *) spi_init;
- gd->jt[XF_spi_setup_slave] = (void *) spi_setup_slave;
- gd->jt[XF_spi_free_slave] = (void *) spi_free_slave;
- gd->jt[XF_spi_claim_bus] = (void *) spi_claim_bus;
- gd->jt[XF_spi_release_bus] = (void *) spi_release_bus;
- gd->jt[XF_spi_xfer] = (void *) spi_xfer;
+#ifndef CONFIG_CMD_SPI
+# define spi_init dummy
+# define spi_setup_slave dummy
+# define spi_free_slave dummy
+# define spi_claim_bus dummy
+# define spi_release_bus dummy
+# define spi_xfer dummy
#endif
+#ifndef CONFIG_HAS_UID
+# define forceenv dummy
+#endif
+
+void jumptable_init(void)
+{
+ gd->jt = malloc(XF_MAX * sizeof(void *));
+#include <_exports.h>
}
{ IH_COMP_BZIP2, "bzip2", "bzip2 compressed", },
{ IH_COMP_GZIP, "gzip", "gzip compressed", },
{ IH_COMP_LZMA, "lzma", "lzma compressed", },
+ { IH_COMP_LZO, "lzo", "lzo compressed", },
{ -1, "", "", },
};
char *s = getenv ("bootm_size");
if (s) {
phys_size_t tmp;
-#ifdef CONFIG_SYS_64BIT_STRTOUL
tmp = (phys_size_t)simple_strtoull (s, NULL, 16);
-#else
- tmp = (phys_size_t)simple_strtoul (s, NULL, 16);
-#endif
return tmp;
}
{
int i, ii;
- for (i = 0; i < dev->config.bNumInterfaces; i++)
- for (ii = 0; ii < dev->config.if_desc[i].bNumEndpoints; ii++)
+ for (i = 0; i < dev->config.desc.bNumInterfaces; i++)
+ for (ii = 0; ii < dev->config.if_desc[i].desc.bNumEndpoints; ii++)
usb_set_maxpacket_ep(dev,
&dev->config.if_desc[i].ep_desc[ii]);
return -1;
}
memcpy(&dev->config, buffer, buffer[0]);
- le16_to_cpus(&(dev->config.wTotalLength));
+ le16_to_cpus(&(dev->config.desc.wTotalLength));
dev->config.no_of_if = 0;
- index = dev->config.bLength;
+ index = dev->config.desc.bLength;
/* Ok the first entry must be a configuration entry,
* now process the others */
head = (struct usb_descriptor_header *) &buffer[index];
- while (index + 1 < dev->config.wTotalLength) {
+ while (index + 1 < dev->config.desc.wTotalLength) {
switch (head->bDescriptorType) {
case USB_DT_INTERFACE:
if (((struct usb_interface_descriptor *) \
dev->config.if_desc[ifno].no_of_ep = 0;
dev->config.if_desc[ifno].num_altsetting = 1;
curr_if_num =
- dev->config.if_desc[ifno].bInterfaceNumber;
+ dev->config.if_desc[ifno].desc.bInterfaceNumber;
} else {
/* found alternate setting for the interface */
dev->config.if_desc[ifno].num_altsetting++;
{
int result;
unsigned int tmp;
- struct usb_config_descriptor *config;
+ struct usb_configuration_descriptor *config;
-
- config = (struct usb_config_descriptor *)&buffer[0];
+ config = (struct usb_configuration_descriptor *)&buffer[0];
result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, 9);
if (result < 9) {
if (result < 0)
*/
int usb_set_interface(struct usb_device *dev, int interface, int alternate)
{
- struct usb_interface_descriptor *if_face = NULL;
+ struct usb_interface *if_face = NULL;
int ret, i;
- for (i = 0; i < dev->config.bNumInterfaces; i++) {
- if (dev->config.if_desc[i].bInterfaceNumber == interface) {
+ for (i = 0; i < dev->config.desc.bNumInterfaces; i++) {
+ if (dev->config.if_desc[i].desc.bInterfaceNumber == interface) {
if_face = &dev->config.if_desc[i];
break;
}
usb_parse_config(dev, &tmpbuf[0], 0);
usb_set_maxpacket(dev);
/* we set the default configuration here */
- if (usb_set_configuration(dev, dev->config.bConfigurationValue)) {
+ if (usb_set_configuration(dev, dev->config.desc.bConfigurationValue)) {
printf("failed to set default configuration " \
"len %d, status %lX\n", dev->act_len, dev->status);
return -1;
int usb_hub_probe(struct usb_device *dev, int ifnum)
{
- struct usb_interface_descriptor *iface;
+ struct usb_interface *iface;
struct usb_endpoint_descriptor *ep;
int ret;
iface = &dev->config.if_desc[ifnum];
/* Is it a hub? */
- if (iface->bInterfaceClass != USB_CLASS_HUB)
+ if (iface->desc.bInterfaceClass != USB_CLASS_HUB)
return 0;
/* Some hubs have a subclass of 1, which AFAICT according to the */
/* specs is not defined, but it works */
- if ((iface->bInterfaceSubClass != 0) &&
- (iface->bInterfaceSubClass != 1))
+ if ((iface->desc.bInterfaceSubClass != 0) &&
+ (iface->desc.bInterfaceSubClass != 1))
return 0;
/* Multiple endpoints? What kind of mutant ninja-hub is this? */
- if (iface->bNumEndpoints != 1)
+ if (iface->desc.bNumEndpoints != 1)
return 0;
ep = &iface->ep_desc[0];
/* Output endpoint? Curiousier and curiousier.. */
static void usb_kbd_setled(struct usb_device *dev)
{
- struct usb_interface_descriptor *iface;
+ struct usb_interface *iface;
iface = &dev->config.if_desc[0];
leds=0;
if(scroll_lock!=0)
leds|=1;
usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
USB_REQ_SET_REPORT, USB_TYPE_CLASS | USB_RECIP_INTERFACE,
- 0x200, iface->bInterfaceNumber,(void *)&leds, 1, 0);
+ 0x200, iface->desc.bInterfaceNumber, (void *)&leds, 1, 0);
}
/* probes the USB device dev for keyboard type */
static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum)
{
- struct usb_interface_descriptor *iface;
+ struct usb_interface *iface;
struct usb_endpoint_descriptor *ep;
int pipe,maxp;
if (dev->descriptor.bNumConfigurations != 1) return 0;
iface = &dev->config.if_desc[ifnum];
- if (iface->bInterfaceClass != 3) return 0;
- if (iface->bInterfaceSubClass != 1) return 0;
- if (iface->bInterfaceProtocol != 1) return 0;
- if (iface->bNumEndpoints != 1) return 0;
+ if (iface->desc.bInterfaceClass != 3)
+ return 0;
+ if (iface->desc.bInterfaceSubClass != 1)
+ return 0;
+ if (iface->desc.bInterfaceProtocol != 1)
+ return 0;
+ if (iface->desc.bNumEndpoints != 1)
+ return 0;
ep = &iface->ep_desc[0];
USB_KBD_PRINTF("USB KBD found set protocol...\n");
/* ok, we found a USB Keyboard, install it */
/* usb_kbd_get_hid_desc(dev); */
- usb_set_protocol(dev, iface->bInterfaceNumber, 0);
+ usb_set_protocol(dev, iface->desc.bInterfaceNumber, 0);
USB_KBD_PRINTF("USB KBD found set idle...\n");
- usb_set_idle(dev, iface->bInterfaceNumber, REPEAT_RATE, 0);
+ usb_set_idle(dev, iface->desc.bInterfaceNumber, REPEAT_RATE, 0);
memset(&new[0], 0, 8);
memset(&old[0], 0, 8);
repeat_delay=0;
struct us_data *ss);
unsigned long usb_stor_read(int device, unsigned long blknr,
unsigned long blkcnt, void *buffer);
+unsigned long usb_stor_write(int device, unsigned long blknr,
+ unsigned long blkcnt, const void *buffer);
struct usb_device * usb_get_dev_index(int index);
void uhci_show_temp_int_td(void);
usb_dev_desc[i].dev = i;
usb_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
usb_dev_desc[i].block_read = usb_stor_read;
+ usb_dev_desc[i].block_write = usb_stor_write;
}
usb_max_devs = 0;
return ss->transport(srb, ss);
}
+static int usb_write_10(ccb *srb, struct us_data *ss, unsigned long start,
+ unsigned short blocks)
+{
+ memset(&srb->cmd[0], 0, 12);
+ srb->cmd[0] = SCSI_WRITE10;
+ srb->cmd[2] = ((unsigned char) (start >> 24)) & 0xff;
+ srb->cmd[3] = ((unsigned char) (start >> 16)) & 0xff;
+ srb->cmd[4] = ((unsigned char) (start >> 8)) & 0xff;
+ srb->cmd[5] = ((unsigned char) (start)) & 0xff;
+ srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff;
+ srb->cmd[8] = (unsigned char) blocks & 0xff;
+ srb->cmdlen = 12;
+ USB_STOR_PRINTF("write10: start %lx blocks %x\n", start, blocks);
+ return ss->transport(srb, ss);
+}
+
#ifdef CONFIG_USB_BIN_FIXUP
/*
return blkcnt;
}
+#define USB_MAX_WRITE_BLK 20
+
+unsigned long usb_stor_write(int device, unsigned long blknr,
+ unsigned long blkcnt, const void *buffer)
+{
+ unsigned long start, blks, buf_addr;
+ unsigned short smallblks;
+ struct usb_device *dev;
+ int retry, i;
+ ccb *srb = &usb_ccb;
+
+ if (blkcnt == 0)
+ return 0;
+
+ device &= 0xff;
+ /* Setup device */
+ USB_STOR_PRINTF("\nusb_write: dev %d \n", device);
+ dev = NULL;
+ for (i = 0; i < USB_MAX_DEVICE; i++) {
+ dev = usb_get_dev_index(i);
+ if (dev == NULL)
+ return 0;
+ if (dev->devnum == usb_dev_desc[device].target)
+ break;
+ }
+
+ usb_disable_asynch(1); /* asynch transfer not allowed */
+
+ srb->lun = usb_dev_desc[device].lun;
+ buf_addr = (unsigned long)buffer;
+ start = blknr;
+ blks = blkcnt;
+ if (usb_test_unit_ready(srb, (struct us_data *)dev->privptr)) {
+ printf("Device NOT ready\n Request Sense returned %02X %02X"
+ " %02X\n", srb->sense_buf[2], srb->sense_buf[12],
+ srb->sense_buf[13]);
+ return 0;
+ }
+
+ USB_STOR_PRINTF("\nusb_write: dev %d startblk %lx, blccnt %lx"
+ " buffer %lx\n", device, start, blks, buf_addr);
+
+ do {
+ /* If write fails retry for max retry count else
+ * return with number of blocks written successfully.
+ */
+ retry = 2;
+ srb->pdata = (unsigned char *)buf_addr;
+ if (blks > USB_MAX_WRITE_BLK)
+ smallblks = USB_MAX_WRITE_BLK;
+ else
+ smallblks = (unsigned short) blks;
+retry_it:
+ if (smallblks == USB_MAX_WRITE_BLK)
+ usb_show_progress();
+ srb->datalen = usb_dev_desc[device].blksz * smallblks;
+ srb->pdata = (unsigned char *)buf_addr;
+ if (usb_write_10(srb, (struct us_data *)dev->privptr, start,
+ smallblks)) {
+ USB_STOR_PRINTF("Write ERROR\n");
+ usb_request_sense(srb, (struct us_data *)dev->privptr);
+ if (retry--)
+ goto retry_it;
+ blkcnt -= blks;
+ break;
+ }
+ start += smallblks;
+ blks -= smallblks;
+ buf_addr += srb->datalen;
+ } while (blks != 0);
+
+ USB_STOR_PRINTF("usb_write: end startblk %lx, blccnt %x buffer %lx\n",
+ start, smallblks, buf_addr);
+
+ usb_disable_asynch(0); /* asynch transfer allowed */
+ if (blkcnt >= USB_MAX_WRITE_BLK)
+ printf("\n");
+ return blkcnt;
+
+}
/* Probe to see if a new device is actually a Storage device */
int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,
struct us_data *ss)
{
- struct usb_interface_descriptor *iface;
+ struct usb_interface *iface;
int i;
unsigned int flags = 0;
#endif
if (dev->descriptor.bDeviceClass != 0 ||
- iface->bInterfaceClass != USB_CLASS_MASS_STORAGE ||
- iface->bInterfaceSubClass < US_SC_MIN ||
- iface->bInterfaceSubClass > US_SC_MAX) {
+ iface->desc.bInterfaceClass != USB_CLASS_MASS_STORAGE ||
+ iface->desc.bInterfaceSubClass < US_SC_MIN ||
+ iface->desc.bInterfaceSubClass > US_SC_MAX) {
/* if it's not a mass storage, we go no further */
return 0;
}
ss->subclass = subclass;
ss->protocol = protocol;
} else {
- ss->subclass = iface->bInterfaceSubClass;
- ss->protocol = iface->bInterfaceProtocol;
+ ss->subclass = iface->desc.bInterfaceSubClass;
+ ss->protocol = iface->desc.bInterfaceProtocol;
}
/* set the handler pointers based on the protocol */
* An optional interrupt is OK (necessary for CBI protocol).
* We will ignore any others.
*/
- for (i = 0; i < iface->bNumEndpoints; i++) {
+ for (i = 0; i < iface->desc.bNumEndpoints; i++) {
/* is it an BULK endpoint? */
if ((iface->ep_desc[i].bmAttributes &
USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
ss->ep_in, ss->ep_out, ss->ep_int);
/* Do some basic sanity checks, and bail if we find a problem */
- if (usb_set_interface(dev, iface->bInterfaceNumber, 0) ||
+ if (usb_set_interface(dev, iface->desc.bInterfaceNumber, 0) ||
!ss->ep_in || !ss->ep_out ||
(ss->protocol == US_PR_CBI && ss->ep_int == 0)) {
USB_STOR_PRINTF("Problems with device\n");
#########################################################################
+HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer \
+ $(HOSTCPPFLAGS)
+HOSTSTRIP = strip
+
+#
+# Mac OS X / Darwin's C preprocessor is Apple specific. It
+# generates numerous errors and warnings. We want to bypass it
+# and use GNU C's cpp. To do this we pass the -traditional-cpp
+# option to the compiler. Note that the -traditional-cpp flag
+# DOES NOT have the same semantics as GNU C's flag, all it does
+# is invoke the GNU preprocessor in stock ANSI/ISO C fashion.
+#
+# Apple's linker is similar, thanks to the new 2 stage linking
+# multiple symbol definitions are treated as errors, hence the
+# -multiply_defined suppress option to turn off this error.
+#
+
ifeq ($(HOSTOS),darwin)
HOSTCC = cc
+HOSTCFLAGS += -traditional-cpp
+HOSTLDFLAGS += -multiply_defined suppress
else
HOSTCC = gcc
endif
-HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
-HOSTSTRIP = strip
+
+ifeq ($(HOSTOS),cygwin)
+HOSTCFLAGS += -ansi
+endif
+
+# We build some files with extra pedantic flags to try to minimize things
+# that won't build on some weird host compiler -- though there are lots of
+# exceptions for files that aren't complaint.
+
+HOSTCFLAGS_NOPED = $(filter-out -pedantic,$(HOSTCFLAGS))
+HOSTCFLAGS += -pedantic
#########################################################################
#
#########################################################################
-export HOSTCC HOSTCFLAGS CROSS_COMPILE \
+export HOSTCC HOSTCFLAGS HOSTLDFLAGS PEDCFLAGS HOSTSTRIP CROSS_COMPILE \
AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP MAKE
export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS
}
/* delay x useconds AND perserve advance timstamp value */
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
}
/* delay x useconds AND perserve advance timstamp value */
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
ulong tmo, tmp;
timestamp = t * (timer_load_val / (100 * CONFIG_SYS_HZ));
}
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
timestamp = t;
}
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
ulong tmo;
return timestamp - base;
}
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
u32 ticks;
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+SOBJS += reset.o
+COBJS += timer.o
+COBJS += ftsmc020.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ftsmc020.h>
+
+struct ftsmc020_config {
+ unsigned int config;
+ unsigned int timing;
+};
+
+static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS;
+
+static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE;
+
+static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config *cfg)
+{
+ if (bank > 3) {
+ printf("bank # %u invalid\n", bank);
+ return;
+ }
+
+ writel(cfg->config, &smc->bank[bank].cr);
+ writel(cfg->timing, &smc->bank[bank].tpr);
+}
+
+void ftsmc020_init(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(config); i++)
+ ftsmc020_setup_bank(i, &config[i]);
+}
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+.global reset_cpu
+reset_cpu:
+ b reset_cpu
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ftpmu010.h>
+#include <asm/arch/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
+
+#define TIMER_CLOCK 32768
+#define TIMER_LOAD_VAL 0xffffffff
+
+int timer_init(void)
+{
+ unsigned int oscc;
+ unsigned int cr;
+
+ debug("%s()\n", __func__);
+
+ /* disable timers */
+ writel(0, &tmr->cr);
+
+ /*
+ * use 32768Hz oscillator for RTC, WDT, TIMER
+ */
+
+ /* enable the 32768Hz oscillator */
+ oscc = readl(&pmu->OSCC);
+ oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI);
+ writel(oscc, &pmu->OSCC);
+
+ /* wait until ready */
+ while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE))
+ ;
+
+ /* select 32768Hz oscillator */
+ oscc = readl(&pmu->OSCC);
+ oscc |= FTPMU010_OSCC_OSCL_RTCLSEL;
+ writel(oscc, &pmu->OSCC);
+
+ /* setup timer */
+ writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+ writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+ writel(0, &tmr->timer3_match1);
+ writel(0, &tmr->timer3_match2);
+
+ /* we don't want timer to issue interrupts */
+ writel(FTTMR010_TM3_MATCH1 |
+ FTTMR010_TM3_MATCH2 |
+ FTTMR010_TM3_OVERFLOW,
+ &tmr->interrupt_mask);
+
+ cr = readl(&tmr->cr);
+ cr |= FTTMR010_TM3_CLOCK; /* use external clock */
+ cr |= FTTMR010_TM3_ENABLE;
+ writel(cr, &tmr->cr);
+
+ /* init the timestamp and lastdec value */
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+ /* capure current decrementer value time */
+ lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+
+ debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+ debug("%s()\n", __func__);
+ reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+ /* current tick value */
+ ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+
+ debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+ if (lastdec >= now) {
+ /*
+ * normal mode (non roll)
+ * move stamp fordward with absoulte diff ticks
+ */
+ timestamp += lastdec - now;
+ } else {
+ /*
+ * we have overflow of the count down timer
+ *
+ * nts = ts + ld + (TLV - now)
+ * ts=old stamp, ld=time that passed before passing through -1
+ * (TLV-now) amount of time after passing though -1
+ * nts = new "advancing time stamp"...it could also roll and
+ * cause problems.
+ */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+
+ lastdec = now;
+
+ debug("%s() returns %lx\n", __func__, timestamp);
+
+ return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+ debug("%s(%lx)\n", __func__, base);
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ debug("%s(%lx)\n", __func__, t);
+ timestamp = t;
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay(unsigned long usec)
+{
+ long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+ unsigned long now, last = readl(&tmr->timer3_counter);
+
+ debug("%s(%lu)\n", __func__, usec);
+ while (tmo > 0) {
+ now = readl(&tmr->timer3_counter);
+ if (now > last) /* count down timer overflow */
+ tmo -= TIMER_LOAD_VAL + last - now;
+ else
+ tmo -= last - now;
+ last = now;
+ }
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ debug("%s()\n", __func__);
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ debug("%s()\n", __func__);
+ return CONFIG_SYS_HZ;
+}
timestamp = t;
}
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
udelay_masked(usec);
}
} while (diff >= 0);
}
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
udelay_masked(usec);
}
timer_ticks = t;
}
-void udelay(ulong usec)
+void __udelay(ulong usec)
{
ulong start = get_timer_masked();
ulong end;
timestamp = t;
}
-void udelay(unsigned long usec)
+void __udelay (unsigned long usec)
{
ulong tmo;
ulong start = get_ticks();
struct s3c24x0_watchdog *watchdog;
#ifdef CONFIG_TRAB
+ extern void disable_vfd(void);
+
disable_vfd();
#endif
}
/* delay x useconds AND preserve advance timestamp value */
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
int32_t tmo = usec * (TIMER_CLOCK / 1000) / 1000;
uint32_t now, last = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
return tick_to_time(get_ticks());
}
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
#include <common.h>
#include <netdev.h>
#include <asm/arch/hardware.h>
-
+#include <asm/io.h>
/* offsets from PLL controller base */
#define PLLC_PLLCTL 0x100
#define DDR_PLLDIV PLLC_PLLDIV1
#endif
+#ifdef CONFIG_SOC_DA8XX
+const dv_reg * const sysdiv[7] = {
+ &davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2,
+ &davinci_pllc_regs->plldiv3, &davinci_pllc_regs->plldiv4,
+ &davinci_pllc_regs->plldiv5, &davinci_pllc_regs->plldiv6,
+ &davinci_pllc_regs->plldiv7
+};
+
+int clk_get(enum davinci_clk_ids id)
+{
+ int pre_div;
+ int pllm;
+ int post_div;
+ int pll_out;
+
+ pll_out = CONFIG_SYS_OSCIN_FREQ;
+
+ if (id == DAVINCI_AUXCLK_CLKID)
+ goto out;
+
+ /*
+ * Lets keep this simple. Combining operations can result in
+ * unexpected approximations
+ */
+ pre_div = (readl(&davinci_pllc_regs->prediv) &
+ DAVINCI_PLLC_DIV_MASK) + 1;
+ pllm = readl(&davinci_pllc_regs->pllm) + 1;
+
+ pll_out /= pre_div;
+ pll_out *= pllm;
+
+ if (id == DAVINCI_PLLM_CLKID)
+ goto out;
+
+ post_div = (readl(&davinci_pllc_regs->postdiv) &
+ DAVINCI_PLLC_DIV_MASK) + 1;
+
+ pll_out /= post_div;
+
+ if (id == DAVINCI_PLLC_CLKID)
+ goto out;
+
+ pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PLLC_DIV_MASK) + 1;
+
+out:
+ return pll_out;
+}
+#endif /* CONFIG_SOC_DA8XX */
#ifdef CONFIG_DISPLAY_CPUINFO
#include <common.h>
#include <asm/arch/hardware.h>
+#include <asm/io.h>
/*
* The PSC manages three inputs to a "module" which may be a peripheral or
/* Works on Always On power domain only (no PD argument) */
void lpsc_on(unsigned int id)
{
- dv_reg_p mdstat, mdctl;
+ dv_reg_p mdstat, mdctl, ptstat, ptcmd;
+#ifdef CONFIG_SOC_DA8XX
+ struct davinci_psc_regs *psc_regs;
+#endif
+#ifndef CONFIG_SOC_DA8XX
if (id >= DAVINCI_LPSC_GEM)
return; /* Don't work on DSP Power Domain */
mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
+ ptstat = REG_P(PSC_PTSTAT);
+ ptcmd = REG_P(PSC_PTCMD);
+#else
+ if (id < DAVINCI_LPSC_PSC1_BASE) {
+ if (id >= PSC_PSC0_MODULE_ID_CNT)
+ return;
+ psc_regs = davinci_psc0_regs;
+ mdstat = &psc_regs->psc0.mdstat[id];
+ mdctl = &psc_regs->psc0.mdctl[id];
+ } else {
+ id -= DAVINCI_LPSC_PSC1_BASE;
+ if (id >= PSC_PSC1_MODULE_ID_CNT)
+ return;
+ psc_regs = davinci_psc1_regs;
+ mdstat = &psc_regs->psc1.mdstat[id];
+ mdctl = &psc_regs->psc1.mdctl[id];
+ }
+ ptstat = &psc_regs->ptstat;
+ ptcmd = &psc_regs->ptcmd;
+#endif
- while (REG(PSC_PTSTAT) & 0x01)
+ while (readl(ptstat) & 0x01)
continue;
- if ((*mdstat & 0x1f) == 0x03)
- return; /* Already on and enabled */
+ if ((readl(mdstat) & 0x1f) == 0x03)
+ return; /* Already on and enabled */
- *mdctl |= 0x03;
+ writel(readl(mdctl) | 0x03, mdctl);
switch (id) {
#ifdef CONFIG_SOC_DM644X
case DAVINCI_LPSC_MEMSTICK:
case DAVINCI_LPSC_McBSP:
case DAVINCI_LPSC_GPIO:
- *mdctl |= 0x200;
+ writel(readl(mdctl) | 0x200, mdctl);
break;
#endif
}
- REG(PSC_PTCMD) = 0x01;
+ writel(0x01, ptcmd);
- while (REG(PSC_PTSTAT) & 0x03)
+ while (readl(ptstat) & 0x01)
continue;
- while ((*mdstat & 0x1f) != 0x03) /* Probably an overkill... */
+ while ((readl(mdstat) & 0x1f) != 0x03)
continue;
}
*/
#include <common.h>
+#include <asm/io.h>
-typedef volatile struct {
+struct davinci_timer {
u_int32_t pid12;
u_int32_t emumgt;
u_int32_t na1;
u_int32_t tcr;
u_int32_t tgcr;
u_int32_t wdtcr;
-} davinci_timer;
+};
-davinci_timer *timer = (davinci_timer *)CONFIG_SYS_TIMERBASE;
+static struct davinci_timer * const timer =
+ (struct davinci_timer *)CONFIG_SYS_TIMERBASE;
#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
#define TIM_CLK_DIV 16
int timer_init(void)
{
/* We are using timer34 in unchained 32-bit mode, full speed */
- timer->tcr = 0x0;
- timer->tgcr = 0x0;
- timer->tgcr = 0x06 | ((TIM_CLK_DIV - 1) << 8);
- timer->tim34 = 0x0;
- timer->prd34 = TIMER_LOAD_VAL;
+ writel(0x0, &timer->tcr);
+ writel(0x0, &timer->tgcr);
+ writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
+ writel(0x0, &timer->tim34);
+ writel(TIMER_LOAD_VAL, &timer->prd34);
lastinc = 0;
timestamp = 0;
- timer->tcr = 2 << 22;
+ writel(2 << 22, &timer->tcr);
return(0);
}
void reset_timer(void)
{
- timer->tcr = 0x0;
- timer->tim34 = 0;
+ writel(0x0, &timer->tcr);
+ writel(0x0, &timer->tim34);
lastinc = 0;
timestamp = 0;
- timer->tcr = 2 << 22;
+ writel(2 << 22, &timer->tcr);
}
static ulong get_timer_raw(void)
{
- ulong now = timer->tim34;
+ ulong now = readl(&timer->tim34);
if (now >= lastinc) {
/* normal mode */
timestamp = t;
}
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
ulong tmo;
ulong endtime;
timestamp = t;
}
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
uint current;
ulong delayticks;
}
/* delay x useconds AND preserve advance timstamp value */
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
}
/* Delay x useconds */
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
ulong ini, end;
}
/* delay x useconds AND perserve advance timstamp value */
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
ulong tmo, tmp;
}
/* delay x useconds AND perserve advance timstamp value */
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
ulong tmo, tmp;
U_BOOT_CMD(
nandecc, 2, 1, do_switch_ecc,
- "nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
+ "switch OMAP3 NAND ECC calculation algorithm",
"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
);
writel(0, &sdrc_base->sysconfig);
/* setup sdrc to ball mux */
- writel(SDP_SDRC_SHARING, &sdrc_base->sharing);
+ writel(SDRC_SHARING, &sdrc_base->sharing);
/* Disable Power Down of CKE cuz of 1 CKE on combo part */
- writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
+ writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH,
+ &sdrc_base->power);
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
sdelay(0x20000);
****************************************************/
u32 is_mem_sdr(void)
{
- if (readl(&sdrc_base->cs[CS0].mr) == SDP_SDRC_MR_0_SDR)
+ if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
return 1;
return 0;
}
}
/* delay x useconds */
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
unsigned long now, last = readl(&timer_base->tcrr);
}
/* delay x useconds */
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
unsigned long tmo, tmp;
START-y += start.o
COBJS-y += cpu.o
-COBJS-y += hsdramc.o
+COBJS-$(CONFIG_SYS_HSDRAMC) += hsdramc.o
COBJS-y += exception.o
COBJS-y += cache.o
COBJS-y += interrupts.o
*/
#include <common.h>
-#ifdef CONFIG_SYS_HSDRAMC
#include <asm/io.h>
#include <asm/sdram.h>
return sdram_size;
}
-
-#endif /* CONFIG_SYS_HSDRAMC */
/*
* For short delays only. It will overflow after a few seconds.
*/
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
unsigned long cycles;
unsigned long base;
return 1;
}
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
unsigned long delay, start, stop;
unsigned long cclk;
LIB = $(obj)lib$(CPU).a
START = start.o start16.o resetvec.o
-COBJS = serial.o interrupts.o exceptions.o cpu.o
+COBJS = serial.o interrupts.o cpu.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
#include <command.h>
#include <asm/interrupt.h>
-int cpu_init(void)
+int cpu_init_f(void)
{
/* initialize FPU, reset EM, set MP and NE */
asm ("fninit\n" \
"orl $0x22, %eax\n" \
"movl %eax, %cr0\n" );
+ return 0;
+}
+
+int cpu_init_r(void)
+{
/* Initialize core interrupt and exception functionality of CPU */
cpu_init_interrupts ();
- cpu_init_exceptions ();
-
return 0;
}
/* segment 0x70 is an arbitrary segment which does not exist */
asm(".globl generate_gpf\n"
+ ".hidden generate_gpf\n"
+ ".type generate_gpf, @function\n"
"generate_gpf:\n"
"ljmp $0x70, $0x47114711\n");
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/interrupt.h>
-
-asm (".globl exp_return\n"
- "exp_return:\n"
- " addl $12, %esp\n"
- " pop %esp\n"
- " popa\n"
- " iret\n");
-
-char exception_stack[4096];
-
-/*
- * For detailed description of each exception, refer to:
- * Intel® 64 and IA-32 Architectures Software Developer's Manual
- * Volume 1: Basic Architecture
- * Order Number: 253665-029US, November 2008
- * Table 6-1. Exceptions and Interrupts
- */
-DECLARE_EXCEPTION(0, divide_error_entry);
-DECLARE_EXCEPTION(1, debug_entry);
-DECLARE_EXCEPTION(2, nmi_interrupt_entry);
-DECLARE_EXCEPTION(3, breakpoint_entry);
-DECLARE_EXCEPTION(4, overflow_entry);
-DECLARE_EXCEPTION(5, bound_range_exceeded_entry);
-DECLARE_EXCEPTION(6, invalid_opcode_entry);
-DECLARE_EXCEPTION(7, device_not_available_entry);
-DECLARE_EXCEPTION(8, double_fault_entry);
-DECLARE_EXCEPTION(9, coprocessor_segment_overrun_entry);
-DECLARE_EXCEPTION(10, invalid_tss_entry);
-DECLARE_EXCEPTION(11, segment_not_present_entry);
-DECLARE_EXCEPTION(12, stack_segment_fault_entry);
-DECLARE_EXCEPTION(13, general_protection_entry);
-DECLARE_EXCEPTION(14, page_fault_entry);
-DECLARE_EXCEPTION(15, reserved_exception_entry);
-DECLARE_EXCEPTION(16, floating_point_error_entry);
-DECLARE_EXCEPTION(17, alignment_check_entry);
-DECLARE_EXCEPTION(18, machine_check_entry);
-DECLARE_EXCEPTION(19, simd_floating_point_exception_entry);
-DECLARE_EXCEPTION(20, reserved_exception_entry);
-DECLARE_EXCEPTION(21, reserved_exception_entry);
-DECLARE_EXCEPTION(22, reserved_exception_entry);
-DECLARE_EXCEPTION(23, reserved_exception_entry);
-DECLARE_EXCEPTION(24, reserved_exception_entry);
-DECLARE_EXCEPTION(25, reserved_exception_entry);
-DECLARE_EXCEPTION(26, reserved_exception_entry);
-DECLARE_EXCEPTION(27, reserved_exception_entry);
-DECLARE_EXCEPTION(28, reserved_exception_entry);
-DECLARE_EXCEPTION(29, reserved_exception_entry);
-DECLARE_EXCEPTION(30, reserved_exception_entry);
-DECLARE_EXCEPTION(31, reserved_exception_entry);
-
-__isr__ reserved_exception_entry(int cause, int ip, int seg)
-{
- printf("Reserved Exception %d at %04x:%08x\n", cause, seg, ip);
-}
-
-__isr__ divide_error_entry(int cause, int ip, int seg)
-{
- printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip);
- while(1);
-}
-
-__isr__ debug_entry(int cause, int ip, int seg)
-{
- printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip);
-}
-
-__isr__ nmi_interrupt_entry(int cause, int ip, int seg)
-{
- printf("NMI Interrupt at %04x:%08x\n", seg, ip);
-}
-
-__isr__ breakpoint_entry(int cause, int ip, int seg)
-{
- printf("Breakpoint at %04x:%08x\n", seg, ip);
-}
-
-__isr__ overflow_entry(int cause, int ip, int seg)
-{
- printf("Overflow at %04x:%08x\n", seg, ip);
- while(1);
-}
-
-__isr__ bound_range_exceeded_entry(int cause, int ip, int seg)
-{
- printf("BOUND Range Exceeded at %04x:%08x\n", seg, ip);
- while(1);
-}
-
-__isr__ invalid_opcode_entry(int cause, int ip, int seg)
-{
- printf("Invalid Opcode (UnDefined Opcode) at %04x:%08x\n", seg, ip);
- while(1);
-}
-
-__isr__ device_not_available_entry(int cause, int ip, int seg)
-{
- printf("Device Not Available (No Math Coprocessor) at %04x:%08x\n", seg, ip);
- while(1);
-}
-
-__isr__ double_fault_entry(int cause, int ip, int seg)
-{
- printf("Double fault at %04x:%08x\n", seg, ip);
- while(1);
-}
-
-__isr__ coprocessor_segment_overrun_entry(int cause, int ip, int seg)
-{
- printf("Co-processor segment overrun at %04x:%08x\n", seg, ip);
- while(1);
-}
-
-__isr__ invalid_tss_entry(int cause, int ip, int seg)
-{
- printf("Invalid TSS at %04x:%08x\n", seg, ip);
-}
-
-__isr__ segment_not_present_entry(int cause, int ip, int seg)
-{
- printf("Segment Not Present at %04x:%08x\n", seg, ip);
- while(1);
-}
-
-__isr__ stack_segment_fault_entry(int cause, int ip, int seg)
-{
- printf("Stack Segment Fault at %04x:%08x\n", seg, ip);
- while(1);
-}
-
-__isr__ general_protection_entry(int cause, int ip, int seg)
-{
- printf("General Protection at %04x:%08x\n", seg, ip);
-}
-
-__isr__ page_fault_entry(int cause, int ip, int seg)
-{
- printf("Page fault at %04x:%08x\n", seg, ip);
- while(1);
-}
-
-__isr__ floating_point_error_entry(int cause, int ip, int seg)
-{
- printf("Floating-Point Error (Math Fault) at %04x:%08x\n", seg, ip);
-}
-
-__isr__ alignment_check_entry(int cause, int ip, int seg)
-{
- printf("Alignment check at %04x:%08x\n", seg, ip);
-}
-
-__isr__ machine_check_entry(int cause, int ip, int seg)
-{
- printf("Machine Check at %04x:%08x\n", seg, ip);
-}
-
-__isr__ simd_floating_point_exception_entry(int cause, int ip, int seg)
-{
- printf("SIMD Floating-Point Exception at %04x:%08x\n", seg, ip);
-}
-
-int cpu_init_exceptions(void)
-{
- /* Just in case... */
- disable_interrupts();
-
- /* Setup exceptions */
- set_vector(0x00, exp_0);
- set_vector(0x01, exp_1);
- set_vector(0x02, exp_2);
- set_vector(0x03, exp_3);
- set_vector(0x04, exp_4);
- set_vector(0x05, exp_5);
- set_vector(0x06, exp_6);
- set_vector(0x07, exp_7);
- set_vector(0x08, exp_8);
- set_vector(0x09, exp_9);
- set_vector(0x0a, exp_10);
- set_vector(0x0b, exp_11);
- set_vector(0x0c, exp_12);
- set_vector(0x0d, exp_13);
- set_vector(0x0e, exp_14);
- set_vector(0x0f, exp_15);
- set_vector(0x10, exp_16);
- set_vector(0x11, exp_17);
- set_vector(0x12, exp_18);
- set_vector(0x13, exp_19);
- set_vector(0x14, exp_20);
- set_vector(0x15, exp_21);
- set_vector(0x16, exp_22);
- set_vector(0x17, exp_23);
- set_vector(0x18, exp_24);
- set_vector(0x19, exp_25);
- set_vector(0x1a, exp_26);
- set_vector(0x1b, exp_27);
- set_vector(0x1c, exp_28);
- set_vector(0x1d, exp_29);
- set_vector(0x1e, exp_30);
- set_vector(0x1f, exp_31);
-
- /* It is now safe to enable interrupts */
- enable_interrupts();
-
- return 0;
-}
/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
*
#include <common.h>
#include <asm/interrupt.h>
+#define DECLARE_INTERRUPT(x) \
+ ".globl irq_"#x"\n" \
+ ".hidden irq_"#x"\n" \
+ ".type irq_"#x", @function\n" \
+ "irq_"#x":\n" \
+ "pushl %ebp\n" \
+ "movl %esp,%ebp\n" \
+ "pusha\n" \
+ "pushl $"#x"\n" \
+ "jmp irq_common_entry\n"
struct idt_entry {
u16 base_low;
u16 base_high;
} __attribute__ ((packed));
+struct desc_ptr {
+ unsigned short size;
+ unsigned long address;
+ unsigned short segment;
+} __attribute__((packed));
struct idt_entry idt[256];
+struct desc_ptr idt_ptr;
-asm (".globl irq_return\n"
- "irq_return:\n"
- " addl $4, %esp\n"
- " popa\n"
- " iret\n");
-
-void __attribute__ ((regparm(0))) default_isr(void);
-asm ("default_isr: iret\n");
-
-asm ("idt_ptr:\n"
- ".word 0x800\n" /* size of the table 8*256 bytes */
- ".long idt\n" /* offset */
- ".word 0x18\n");/* data segment */
+static inline void load_idt(const struct desc_ptr *dtr)
+{
+ asm volatile("cs lidt %0"::"m" (*dtr));
+}
void set_vector(u8 intnum, void *routine)
{
- idt[intnum].base_high = (u16)((u32)(routine + gd->reloc_off) >> 16);
- idt[intnum].base_low = (u16)((u32)(routine + gd->reloc_off) & 0xffff);
+ idt[intnum].base_high = (u16)((u32)(routine) >> 16);
+ idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
}
+void irq_0(void);
+void irq_1(void);
int cpu_init_interrupts(void)
{
int i;
+ int irq_entry_size = irq_1 - irq_0;
+ void *irq_entry = (void *)irq_0;
+
/* Just in case... */
disable_interrupts();
idt[i].access = 0x8e;
idt[i].res = 0;
idt[i].selector = 0x10;
- set_vector(i, default_isr);
+ set_vector(i, irq_entry);
+ irq_entry += irq_entry_size;
}
- asm ("cs lidt idt_ptr\n");
+ idt_ptr.size = 256 * 8;
+ idt_ptr.address = (unsigned long) idt;
+ idt_ptr.segment = 0x18;
+
+ load_idt(&idt_ptr);
/* It is now safe to enable interrupts */
enable_interrupts();
return 0;
}
+void __do_irq(int irq)
+{
+ printf("Unhandled IRQ : %d\n", irq);
+}
+void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
+
void enable_interrupts(void)
{
asm("sti\n");
return (flags&0x200); /* IE flags is bit 9 */
}
+
+/* IRQ Low-Level Service Routine */
+__isr__ irq_llsr(int ip, int seg, int irq)
+{
+ /*
+ * For detailed description of each exception, refer to:
+ * Intel® 64 and IA-32 Architectures Software Developer's Manual
+ * Volume 1: Basic Architecture
+ * Order Number: 253665-029US, November 2008
+ * Table 6-1. Exceptions and Interrupts
+ */
+ switch (irq) {
+ case 0x00:
+ printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip);
+ while(1);
+ break;
+ case 0x01:
+ printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip);
+ break;
+ case 0x02:
+ printf("NMI Interrupt at %04x:%08x\n", seg, ip);
+ break;
+ case 0x03:
+ printf("Breakpoint at %04x:%08x\n", seg, ip);
+ break;
+ case 0x04:
+ printf("Overflow at %04x:%08x\n", seg, ip);
+ while(1);
+ break;
+ case 0x05:
+ printf("BOUND Range Exceeded at %04x:%08x\n", seg, ip);
+ while(1);
+ break;
+ case 0x06:
+ printf("Invalid Opcode (UnDefined Opcode) at %04x:%08x\n", seg, ip);
+ while(1);
+ break;
+ case 0x07:
+ printf("Device Not Available (No Math Coprocessor) at %04x:%08x\n", seg, ip);
+ while(1);
+ break;
+ case 0x08:
+ printf("Double fault at %04x:%08x\n", seg, ip);
+ while(1);
+ break;
+ case 0x09:
+ printf("Co-processor segment overrun at %04x:%08x\n", seg, ip);
+ while(1);
+ break;
+ case 0x0a:
+ printf("Invalid TSS at %04x:%08x\n", seg, ip);
+ break;
+ case 0x0b:
+ printf("Segment Not Present at %04x:%08x\n", seg, ip);
+ while(1);
+ break;
+ case 0x0c:
+ printf("Stack Segment Fault at %04x:%08x\n", seg, ip);
+ while(1);
+ break;
+ case 0x0d:
+ printf("General Protection at %04x:%08x\n", seg, ip);
+ break;
+ case 0x0e:
+ printf("Page fault at %04x:%08x\n", seg, ip);
+ while(1);
+ break;
+ case 0x0f:
+ printf("Floating-Point Error (Math Fault) at %04x:%08x\n", seg, ip);
+ break;
+ case 0x10:
+ printf("Alignment check at %04x:%08x\n", seg, ip);
+ break;
+ case 0x11:
+ printf("Machine Check at %04x:%08x\n", seg, ip);
+ break;
+ case 0x12:
+ printf("SIMD Floating-Point Exception at %04x:%08x\n", seg, ip);
+ break;
+ case 0x13:
+ case 0x14:
+ case 0x15:
+ case 0x16:
+ case 0x17:
+ case 0x18:
+ case 0x19:
+ case 0x1a:
+ case 0x1b:
+ case 0x1c:
+ case 0x1d:
+ case 0x1e:
+ case 0x1f:
+ printf("Reserved Exception %d at %04x:%08x\n", irq, seg, ip);
+ break;
+
+ default:
+ /* Hardware or User IRQ */
+ do_irq(irq);
+ }
+}
+
+/*
+ * OK - This looks really horrible, but it serves a purpose - It helps create
+ * fully relocatable code.
+ * - The call to irq_llsr will be a relative jump
+ * - The IRQ entries will be guaranteed to be in order
+ * It's a bit annoying that we need to waste 3 bytes per interrupt entry
+ * (total of 768 code bytes), but we MUST create a Stack Frame and this is
+ * the easiest way I could do it. Maybe it can be made better later.
+ */
+asm(".globl irq_common_entry\n" \
+ ".hidden irq_common_entry\n" \
+ ".type irq_common_entry, @function\n" \
+ "irq_common_entry:\n" \
+ "pushl $0\n" \
+ "pushl $0\n" \
+ "call irq_llsr\n" \
+ "popl %eax\n" \
+ "popl %eax\n" \
+ "popl %eax\n" \
+ "popa\n" \
+ "leave\n"\
+ "iret\n" \
+ DECLARE_INTERRUPT(0) \
+ DECLARE_INTERRUPT(1) \
+ DECLARE_INTERRUPT(2) \
+ DECLARE_INTERRUPT(3) \
+ DECLARE_INTERRUPT(4) \
+ DECLARE_INTERRUPT(5) \
+ DECLARE_INTERRUPT(6) \
+ DECLARE_INTERRUPT(7) \
+ DECLARE_INTERRUPT(8) \
+ DECLARE_INTERRUPT(9) \
+ DECLARE_INTERRUPT(10) \
+ DECLARE_INTERRUPT(11) \
+ DECLARE_INTERRUPT(12) \
+ DECLARE_INTERRUPT(13) \
+ DECLARE_INTERRUPT(14) \
+ DECLARE_INTERRUPT(15) \
+ DECLARE_INTERRUPT(16) \
+ DECLARE_INTERRUPT(17) \
+ DECLARE_INTERRUPT(18) \
+ DECLARE_INTERRUPT(19) \
+ DECLARE_INTERRUPT(20) \
+ DECLARE_INTERRUPT(21) \
+ DECLARE_INTERRUPT(22) \
+ DECLARE_INTERRUPT(23) \
+ DECLARE_INTERRUPT(24) \
+ DECLARE_INTERRUPT(25) \
+ DECLARE_INTERRUPT(26) \
+ DECLARE_INTERRUPT(27) \
+ DECLARE_INTERRUPT(28) \
+ DECLARE_INTERRUPT(29) \
+ DECLARE_INTERRUPT(30) \
+ DECLARE_INTERRUPT(31) \
+ DECLARE_INTERRUPT(32) \
+ DECLARE_INTERRUPT(33) \
+ DECLARE_INTERRUPT(34) \
+ DECLARE_INTERRUPT(35) \
+ DECLARE_INTERRUPT(36) \
+ DECLARE_INTERRUPT(37) \
+ DECLARE_INTERRUPT(38) \
+ DECLARE_INTERRUPT(39) \
+ DECLARE_INTERRUPT(40) \
+ DECLARE_INTERRUPT(41) \
+ DECLARE_INTERRUPT(42) \
+ DECLARE_INTERRUPT(43) \
+ DECLARE_INTERRUPT(44) \
+ DECLARE_INTERRUPT(45) \
+ DECLARE_INTERRUPT(46) \
+ DECLARE_INTERRUPT(47) \
+ DECLARE_INTERRUPT(48) \
+ DECLARE_INTERRUPT(49) \
+ DECLARE_INTERRUPT(50) \
+ DECLARE_INTERRUPT(51) \
+ DECLARE_INTERRUPT(52) \
+ DECLARE_INTERRUPT(53) \
+ DECLARE_INTERRUPT(54) \
+ DECLARE_INTERRUPT(55) \
+ DECLARE_INTERRUPT(56) \
+ DECLARE_INTERRUPT(57) \
+ DECLARE_INTERRUPT(58) \
+ DECLARE_INTERRUPT(59) \
+ DECLARE_INTERRUPT(60) \
+ DECLARE_INTERRUPT(61) \
+ DECLARE_INTERRUPT(62) \
+ DECLARE_INTERRUPT(63) \
+ DECLARE_INTERRUPT(64) \
+ DECLARE_INTERRUPT(65) \
+ DECLARE_INTERRUPT(66) \
+ DECLARE_INTERRUPT(67) \
+ DECLARE_INTERRUPT(68) \
+ DECLARE_INTERRUPT(69) \
+ DECLARE_INTERRUPT(70) \
+ DECLARE_INTERRUPT(71) \
+ DECLARE_INTERRUPT(72) \
+ DECLARE_INTERRUPT(73) \
+ DECLARE_INTERRUPT(74) \
+ DECLARE_INTERRUPT(75) \
+ DECLARE_INTERRUPT(76) \
+ DECLARE_INTERRUPT(77) \
+ DECLARE_INTERRUPT(78) \
+ DECLARE_INTERRUPT(79) \
+ DECLARE_INTERRUPT(80) \
+ DECLARE_INTERRUPT(81) \
+ DECLARE_INTERRUPT(82) \
+ DECLARE_INTERRUPT(83) \
+ DECLARE_INTERRUPT(84) \
+ DECLARE_INTERRUPT(85) \
+ DECLARE_INTERRUPT(86) \
+ DECLARE_INTERRUPT(87) \
+ DECLARE_INTERRUPT(88) \
+ DECLARE_INTERRUPT(89) \
+ DECLARE_INTERRUPT(90) \
+ DECLARE_INTERRUPT(91) \
+ DECLARE_INTERRUPT(92) \
+ DECLARE_INTERRUPT(93) \
+ DECLARE_INTERRUPT(94) \
+ DECLARE_INTERRUPT(95) \
+ DECLARE_INTERRUPT(97) \
+ DECLARE_INTERRUPT(96) \
+ DECLARE_INTERRUPT(98) \
+ DECLARE_INTERRUPT(99) \
+ DECLARE_INTERRUPT(100) \
+ DECLARE_INTERRUPT(101) \
+ DECLARE_INTERRUPT(102) \
+ DECLARE_INTERRUPT(103) \
+ DECLARE_INTERRUPT(104) \
+ DECLARE_INTERRUPT(105) \
+ DECLARE_INTERRUPT(106) \
+ DECLARE_INTERRUPT(107) \
+ DECLARE_INTERRUPT(108) \
+ DECLARE_INTERRUPT(109) \
+ DECLARE_INTERRUPT(110) \
+ DECLARE_INTERRUPT(111) \
+ DECLARE_INTERRUPT(112) \
+ DECLARE_INTERRUPT(113) \
+ DECLARE_INTERRUPT(114) \
+ DECLARE_INTERRUPT(115) \
+ DECLARE_INTERRUPT(116) \
+ DECLARE_INTERRUPT(117) \
+ DECLARE_INTERRUPT(118) \
+ DECLARE_INTERRUPT(119) \
+ DECLARE_INTERRUPT(120) \
+ DECLARE_INTERRUPT(121) \
+ DECLARE_INTERRUPT(122) \
+ DECLARE_INTERRUPT(123) \
+ DECLARE_INTERRUPT(124) \
+ DECLARE_INTERRUPT(125) \
+ DECLARE_INTERRUPT(126) \
+ DECLARE_INTERRUPT(127) \
+ DECLARE_INTERRUPT(128) \
+ DECLARE_INTERRUPT(129) \
+ DECLARE_INTERRUPT(130) \
+ DECLARE_INTERRUPT(131) \
+ DECLARE_INTERRUPT(132) \
+ DECLARE_INTERRUPT(133) \
+ DECLARE_INTERRUPT(134) \
+ DECLARE_INTERRUPT(135) \
+ DECLARE_INTERRUPT(136) \
+ DECLARE_INTERRUPT(137) \
+ DECLARE_INTERRUPT(138) \
+ DECLARE_INTERRUPT(139) \
+ DECLARE_INTERRUPT(140) \
+ DECLARE_INTERRUPT(141) \
+ DECLARE_INTERRUPT(142) \
+ DECLARE_INTERRUPT(143) \
+ DECLARE_INTERRUPT(144) \
+ DECLARE_INTERRUPT(145) \
+ DECLARE_INTERRUPT(146) \
+ DECLARE_INTERRUPT(147) \
+ DECLARE_INTERRUPT(148) \
+ DECLARE_INTERRUPT(149) \
+ DECLARE_INTERRUPT(150) \
+ DECLARE_INTERRUPT(151) \
+ DECLARE_INTERRUPT(152) \
+ DECLARE_INTERRUPT(153) \
+ DECLARE_INTERRUPT(154) \
+ DECLARE_INTERRUPT(155) \
+ DECLARE_INTERRUPT(156) \
+ DECLARE_INTERRUPT(157) \
+ DECLARE_INTERRUPT(158) \
+ DECLARE_INTERRUPT(159) \
+ DECLARE_INTERRUPT(160) \
+ DECLARE_INTERRUPT(161) \
+ DECLARE_INTERRUPT(162) \
+ DECLARE_INTERRUPT(163) \
+ DECLARE_INTERRUPT(164) \
+ DECLARE_INTERRUPT(165) \
+ DECLARE_INTERRUPT(166) \
+ DECLARE_INTERRUPT(167) \
+ DECLARE_INTERRUPT(168) \
+ DECLARE_INTERRUPT(169) \
+ DECLARE_INTERRUPT(170) \
+ DECLARE_INTERRUPT(171) \
+ DECLARE_INTERRUPT(172) \
+ DECLARE_INTERRUPT(173) \
+ DECLARE_INTERRUPT(174) \
+ DECLARE_INTERRUPT(175) \
+ DECLARE_INTERRUPT(176) \
+ DECLARE_INTERRUPT(177) \
+ DECLARE_INTERRUPT(178) \
+ DECLARE_INTERRUPT(179) \
+ DECLARE_INTERRUPT(180) \
+ DECLARE_INTERRUPT(181) \
+ DECLARE_INTERRUPT(182) \
+ DECLARE_INTERRUPT(183) \
+ DECLARE_INTERRUPT(184) \
+ DECLARE_INTERRUPT(185) \
+ DECLARE_INTERRUPT(186) \
+ DECLARE_INTERRUPT(187) \
+ DECLARE_INTERRUPT(188) \
+ DECLARE_INTERRUPT(189) \
+ DECLARE_INTERRUPT(190) \
+ DECLARE_INTERRUPT(191) \
+ DECLARE_INTERRUPT(192) \
+ DECLARE_INTERRUPT(193) \
+ DECLARE_INTERRUPT(194) \
+ DECLARE_INTERRUPT(195) \
+ DECLARE_INTERRUPT(196) \
+ DECLARE_INTERRUPT(197) \
+ DECLARE_INTERRUPT(198) \
+ DECLARE_INTERRUPT(199) \
+ DECLARE_INTERRUPT(200) \
+ DECLARE_INTERRUPT(201) \
+ DECLARE_INTERRUPT(202) \
+ DECLARE_INTERRUPT(203) \
+ DECLARE_INTERRUPT(204) \
+ DECLARE_INTERRUPT(205) \
+ DECLARE_INTERRUPT(206) \
+ DECLARE_INTERRUPT(207) \
+ DECLARE_INTERRUPT(208) \
+ DECLARE_INTERRUPT(209) \
+ DECLARE_INTERRUPT(210) \
+ DECLARE_INTERRUPT(211) \
+ DECLARE_INTERRUPT(212) \
+ DECLARE_INTERRUPT(213) \
+ DECLARE_INTERRUPT(214) \
+ DECLARE_INTERRUPT(215) \
+ DECLARE_INTERRUPT(216) \
+ DECLARE_INTERRUPT(217) \
+ DECLARE_INTERRUPT(218) \
+ DECLARE_INTERRUPT(219) \
+ DECLARE_INTERRUPT(220) \
+ DECLARE_INTERRUPT(221) \
+ DECLARE_INTERRUPT(222) \
+ DECLARE_INTERRUPT(223) \
+ DECLARE_INTERRUPT(224) \
+ DECLARE_INTERRUPT(225) \
+ DECLARE_INTERRUPT(226) \
+ DECLARE_INTERRUPT(227) \
+ DECLARE_INTERRUPT(228) \
+ DECLARE_INTERRUPT(229) \
+ DECLARE_INTERRUPT(230) \
+ DECLARE_INTERRUPT(231) \
+ DECLARE_INTERRUPT(232) \
+ DECLARE_INTERRUPT(233) \
+ DECLARE_INTERRUPT(234) \
+ DECLARE_INTERRUPT(235) \
+ DECLARE_INTERRUPT(236) \
+ DECLARE_INTERRUPT(237) \
+ DECLARE_INTERRUPT(238) \
+ DECLARE_INTERRUPT(239) \
+ DECLARE_INTERRUPT(240) \
+ DECLARE_INTERRUPT(241) \
+ DECLARE_INTERRUPT(242) \
+ DECLARE_INTERRUPT(243) \
+ DECLARE_INTERRUPT(244) \
+ DECLARE_INTERRUPT(245) \
+ DECLARE_INTERRUPT(246) \
+ DECLARE_INTERRUPT(247) \
+ DECLARE_INTERRUPT(248) \
+ DECLARE_INTERRUPT(249) \
+ DECLARE_INTERRUPT(250) \
+ DECLARE_INTERRUPT(251) \
+ DECLARE_INTERRUPT(252) \
+ DECLARE_INTERRUPT(253) \
+ DECLARE_INTERRUPT(254) \
+ DECLARE_INTERRUPT(255));
int timer_init(void)
{
+ /* Register the SC520 specific timer interrupt handler */
+ register_timer_isr (sc520_timer_isr);
+
+ /* Install interrupt handler for GP Timer 1 */
+ irq_install_handler (0, timer_isr, NULL);
+
/* Map GP Timer 1 to Master PIC IR0 */
sc520_mmcr->gp_tmr_int_map[1] = 0x01;
sc520_mmcr->gptmr1maxcmpa = 100;
sc520_mmcr->gptmr1ctl = 0xe009;
- /* Register the SC520 specific timer interrupt handler */
- register_timer_isr (sc520_timer_isr);
-
- /* Install interrupt handler for GP Timer 1 */
- irq_install_handler (0, timer_isr, NULL);
unmask_irq (0);
/* Clear the GP Timer 1 status register to get the show rolling*/
return 0;
}
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
int m = 0;
long u;
jmp mem_init
mem_init_ret:
- /* check ammount of configured memory
- * (we need atleast bss start+bss size+stack size) */
- movl $_i386boot_bss_start, %ecx /* BSS start */
- addl $_i386boot_bss_size, %ecx /* BSS size */
- addl $CONFIG_SYS_STACK_SIZE, %ecx
+ /* Check we have enough memory for stack */
+ movl $CONFIG_SYS_STACK_SIZE, %ecx
cmpl %ecx, %eax
jae mem_ok
.progress0a:
jmp die
mem_ok:
+ /* Set stack pointer to upper memory limit*/
+ movl %eax, %esp
/* indicate progress */
movw $0x02, %ax
jmp show_boot_progress_asm
.progress1:
- /* create a stack after the bss */
- movl $_i386boot_bss_start, %eax
- addl $_i386boot_bss_size, %eax
- addl $CONFIG_SYS_STACK_SIZE, %eax
- movl %eax, %esp
-
+ /* Test the stack */
pushl $0
popl %eax
cmpl $0, %eax
jmp show_boot_progress_asm
.progress2:
- /* copy data section to ram, size must be 4-byte aligned */
- movl $_i386boot_romdata_dest, %edi /* destination address */
- movl $_i386boot_romdata_start, %esi /* source address */
- movl $_i386boot_romdata_size, %ecx /* number of bytes to copy */
- movl %ecx, %eax
- andl $3, %eax
- jnz data_fail
-
- shrl $2, %ecx /* copy 4 byte each time */
- cld
- cmpl $0, %ecx
- je data_ok
-data_segment:
- movsl
- loop data_segment
- jmp data_ok
-data_fail:
- /* indicate (lack of) progress */
- movw $0x83, %ax
- movl $.progress2a, %ebp
- jmp show_boot_progress_asm
-.progress2a:
- jmp die
-
-data_ok:
-
- /* indicate progress */
- movw $0x04, %ax
- movl $.progress3, %ebp
- jmp show_boot_progress_asm
-.progress3:
-
- /* clear bss section in ram, size must be 4-byte aligned */
- movl $_i386boot_bss_start, %edi /* MK_CHG BSS start */
- movl $_i386boot_bss_size, %ecx /* BSS size */
- movl %ecx, %eax
- andl $3, %eax
- jnz bss_fail
- shrl $2, %ecx /* clear 4 byte each time */
- cld
- cmpl $0, %ecx
- je bss_ok
-bss:
- movl $0, (%edi)
- add $4, %edi
- loop bss
- jmp bss_ok
-
-bss_fail:
- /* indicate (lack of) progress */
- movw $0x84, %ax
- movl $.progress3a, %ebp
- jmp show_boot_progress_asm
-.progress3a:
- jmp die
-
-bss_ok:
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
- /* indicate progress */
- movw $0x06, %ax
- movl $.progress6, %ebp
- jmp show_boot_progress_asm
-.progress6:
-
- /* copy text section to ram, size must be 4-byte aligned */
- movl $CONFIG_SYS_BL_START_RAM, %edi /* destination address */
- movl $TEXT_BASE, %esi /* source address */
- movl $_i386boot_text_size, %ecx /* number of bytes to copy */
- movl %ecx, %eax
- andl $3, %eax
- jz text_copy /* Already 4-byte aligned */
- subl $4, %eax /* Add extra bytes to size */
- addl %eax, %ecx
-text_copy:
- shrl $2, %ecx /* copy 4 byte each time */
- cld
- cmpl $0, %ecx
- je text_ok
-text_segment:
- movsl
- loop text_segment
- jmp text_ok
-text_fail:
- /* indicate (lack of) progress */
- movw $0x86, %ax
- movl $.progress5a, %ebp
- jmp show_boot_progress_asm
-.progress5a:
- jmp die
-
-text_ok:
-#endif
wbinvd
+ /* Get upper memory limit */
+ movl %esp, %ecx
+ subl $CONFIG_SYS_STACK_SIZE, %ecx
- /* indicate progress */
- movw $0x05, %ax
- movl $.progress4, %ebp
- jmp show_boot_progress_asm
-.progress4:
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
- /* Jump to the RAM copy of start_i386boot */
- movl $start_i386boot, %ebp
- addl $(CONFIG_SYS_BL_START_RAM - TEXT_BASE), %ebp
- call *%ebp /* Enter, U-boot! */
-#else
- call start_i386boot /* Enter, U-boot! */
-#endif
+ /* Create a Stack Frame */
+ pushl %ebp
+ movl %esp, %ebp
+
+ /* stack_limit parameter */
+ pushl %ecx
+ call board_init_f /* Enter, U-boot! */
/* indicate (lack of) progress */
movw $0x85, %ax
/*
* 0 <= r0 <= 2000
*/
-.globl udelay
-udelay:
+.globl __udelay
+__udelay:
mov r2, #0x6800
orr r2, r2, #0x00db
mul r0, r2, r0
while (!(*IXP425_OSST & IXP425_OSST_TIMER_1_PEND));
}
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
while (usec--) ixp425_udelay(1);
}
timestamp = t;
}
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
ulong tmo,tmp;
#endif
extern void dtimer_intr_setup(void);
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
u32 now, freq;
#ifdef CONFIG_HAS_ETH0
fdt_fixup_ethernet(blob);
#endif
+ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif
}
#endif
+ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif
"timebase-frequency", OF_TBCLK, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"clock-frequency", bd->bi_intfreq, 1);
+ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif /* CONFIG_OF_LIBFDT */
#endif
#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
(ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
+ (ACR_APARK << ACR_APARK_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
+ (ACR_PARKM << ACR_PARKM_SHIFT) |
#endif
0;
__be32 acr_val =
#endif
#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
+ (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
+ (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
#endif
0;
__be32 spcr_mask =
#endif
#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
+#endif
+ 0;
+ __be32 lcrr_mask =
+#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
+ LCRR_DBYP |
+#endif
+#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
+ LCRR_EADC |
+#endif
+#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
+ LCRR_CLKDIV |
+#endif
+ 0;
+ __be32 lcrr_val =
+#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
+ CONFIG_SYS_LCRR_DBYP |
+#endif
+#ifdef CONFIG_SYS_LCRR_EADC
+ CONFIG_SYS_LCRR_EADC |
+#endif
+#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
+ CONFIG_SYS_LCRR_CLKDIV |
#endif
0;
*/
__raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
+ /* LCRR - Clock Ratio Register (10.3.1.16)
+ * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
+ */
+ clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
+ __raw_readl(&im->lbus.lcrr);
+ isync();
+
/* Enable Time Base & Decrementer ( so we will have udelay() )*/
setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
int cpu_init_r (void)
{
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
#ifdef CONFIG_QE
uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
-#endif
- __be32 lcrr_mask =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
- LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
- LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
- LCRR_CLKDIV |
-#endif
- 0;
- __be32 lcrr_val =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
- CONFIG_SYS_LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC
- CONFIG_SYS_LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
- CONFIG_SYS_LCRR_CLKDIV |
-#endif
- 0;
- /* LCRR - Clock Ratio Register (10.3.1.16)
- * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
- */
- clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
- __raw_readl(&im->lbus.lcrr);
- isync();
-
-#ifdef CONFIG_QE
qe_init(qe_base);
qe_reset();
#endif
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <i2c.h>
#include <spd.h>
#include <asm/mmu.h>
unsigned int ddrc_ecc_enable;
unsigned int pvr = get_pvr();
+ /*
+ * First disable the memory controller (could be enabled
+ * by the debugger)
+ */
+ clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
+ sync();
+ isync();
+
/* Read SPD parameters with I2C */
CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
#ifdef SPD_DEBUG
#ifdef CONFIG_FSL_CORENET
corenet_tb_init();
#endif
+ init_used_tlb_cams();
}
while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
;
+#ifdef CONFIG_SYS_CACHE_STASHING
+ /* set stash id to (coreID) * 2 + 32 + L2 (1) */
+ mtspr(SPRN_L2CSR1, (32 + 1));
+#endif
+
/* enable the cache */
mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
goto next;
}
+#ifdef CONFIG_SYS_CACHE_STASHING
+ {
+ u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
+ if (reg)
+ fdt_setprop_cell(blob, l2_off, "cache-stash-id",
+ (*reg * 2) + 32 + 1);
+ }
+#endif
+
fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
fdt_setprop_cell(blob, l2_off, "cache-size", size);
fdt_setprop_cell(blob, off, "d-cache-size", dsize);
fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
+#ifdef CONFIG_SYS_CACHE_STASHING
+ {
+ u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
+ if (reg)
+ fdt_setprop_cell(blob, off, "cache-stash-id",
+ (*reg * 2) + 32 + 0);
+ }
+#endif
+
/* i-side config */
isize = (l1cfg1 & 0x7ff) * 1024;
inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
}
+#if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
+static void ft_fixup_clks(void *blob, const char *alias, unsigned long freq)
+{
+ const char *path = fdt_get_alias(blob, alias);
+
+ int off = fdt_path_offset(blob, path);
+
+ if (off >= 0) {
+ off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
+ if (off > 0)
+ printf("WARNING enable to set clock-frequency "
+ "for %s: %s\n", alias, fdt_strerror(off));
+ }
+}
+
+static void ft_fixup_dpaa_clks(void *blob)
+{
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+ ft_fixup_clks(blob, "fman0", sysinfo.freqFMan[0]);
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ ft_fixup_clks(blob, "fman1", sysinfo.freqFMan[1]);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_PME
+ ft_fixup_clks(blob, "pme", sysinfo.freqPME);
+#endif
+}
+#else
+#define ft_fixup_dpaa_clks(x)
+#endif
+
void ft_cpu_setup(void *blob, bd_t *bd)
{
int off;
#if defined(CONFIG_FSL_ESDHC)
fdt_fixup_esdhc(blob, bd);
#endif
+
+ ft_fixup_dpaa_clks(blob);
}
return 1;
}
-#ifdef CONFIG_SYS_64BIT_STRTOUL
boot_addr = simple_strtoull(argv[0], NULL, 16);
-#else
- boot_addr = simple_strtoul(argv[0], NULL, 16);
-#endif
/* handle pir, r3, r6 */
for (i = 1; i < 4; i++) {
e = find_law(bootpg);
out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K);
+ /* readback to sync write */
+ in_be32(&ccm->bstrar);
+
/* disable time base at the platform */
out_be32(&rcpm->ctbenrl, cpu_up_mask);
disable_tlb(i);
set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
slwi r8,r4,5
add r10,r3,r8
+#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
+ /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
+ slwi r8,r4,1
+ addi r8,r8,32
+ mtspr L1CSR2,r8
+#endif
+
#ifdef CONFIG_BACKSIDE_L2_CACHE
/* Enable/invalidate the L2 cache */
msync
- lis r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
- ori r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
- mtspr SPRN_L2CSR0,r3
+ lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
+ ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
+ mtspr SPRN_L2CSR0,r2
1:
mfspr r3,SPRN_L2CSR0
- andis. r1,r3,L2CSR0_L2FI@h
+ and. r1,r3,r2
bne 1b
+#ifdef CONFIG_SYS_CACHE_STASHING
+ /* set stash id to (coreID) * 2 + 32 + L2 (1) */
+ addi r3,r8,1
+ mtspr SPRN_L2CSR1,r3
+#endif
+
lis r3,CONFIG_SYS_INIT_L2CSR0@h
ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
mtspr SPRN_L2CSR0,r3
isync
+2:
+ mfspr r3,SPRN_L2CSR0
+ andis. r1,r3,L2CSR0_L2E@h
+ beq 2b
#endif
#define EPAPR_MAGIC (0x45504150)
lis r11,(MAS1_VALID|MAS1_IPROT)@h
ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
mtspr SPRN_MAS1,r11
- oris r11,r13,(MAS2_I)@h
- ori r11,r13,(MAS2_I)@l
+ oris r11,r13,(MAS2_I|MAS2_G)@h
+ ori r11,r13,(MAS2_I|MAS2_G)@l
mtspr SPRN_MAS2,r11
oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
#ifdef CONFIG_SYS_DPAA_PME
if (rcw_tmp & PME_CLK_SEL)
- sysInfo->freqPME = freqCC_PLL[2] / 2;
- else
sysInfo->freqPME = sysInfo->freqSystemBus / 2;
+ else
+ sysInfo->freqPME = freqCC_PLL[2] / 2;
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
if (rcw_tmp & FM1_CLK_SEL)
- sysInfo->freqFMan[0] = freqCC_PLL[2] / 2;
- else
sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
+ else
+ sysInfo->freqFMan[0] = freqCC_PLL[2] / 2;
#if (CONFIG_SYS_NUM_FMAN) == 2
if (rcw_tmp & FM2_CLK_SEL)
- sysInfo->freqFMan[1] = freqCC_PLL[2] / 2;
- else
sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
+ else
+ sysInfo->freqFMan[1] = freqCC_PLL[2] / 2;
#endif
#endif
/*
- * Copyright 2004, 2007-2009 Freescale Semiconductor.
+ * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
* Copyright (C) 2003 Motorola,Inc.
*
* See file CREDITS for list of people who contributed to this
*
*/
+#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
+ /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
+ li r2,(32 + 0)
+ mtspr L1CSR2,r2
+#endif
+
lis r2,L1CSR0_CPE@H /* enable parity */
ori r2,r2,L1CSR0_DCE
mtspr L1CSR0,r2 /* enable L1 Dcache */
}
#ifndef CONFIG_NAND_SPL
+static inline void use_tlb_cam(u8 idx)
+{
+ int i = idx / 32;
+ int bit = idx % 32;
+
+ gd->used_tlb_cams[i] |= (1 << bit);
+}
+
+static inline void free_tlb_cam(u8 idx)
+{
+ int i = idx / 32;
+ int bit = idx % 32;
+
+ gd->used_tlb_cams[i] &= ~(1 << bit);
+}
+
+void init_used_tlb_cams(void)
+{
+ int i;
+ unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
+
+ for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++)
+ gd->used_tlb_cams[i] = 0;
+
+ /* walk all the entries */
+ for (i = 0; i < num_cam; i++) {
+ u32 _mas1;
+
+ mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
+
+ asm volatile("tlbre;isync");
+ _mas1 = mfspr(MAS1);
+
+ /* if the entry isn't valid skip it */
+ if ((_mas1 & MAS1_VALID))
+ use_tlb_cam(i);
+ }
+}
+
+int find_free_tlbcam(void)
+{
+ int i;
+ u32 idx;
+
+ for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) {
+ idx = ffz(gd->used_tlb_cams[i]);
+
+ if (idx != 32)
+ break;
+ }
+
+ idx += i * 32;
+
+ if (idx >= CONFIG_SYS_NUM_TLBCAMS)
+ return -1;
+
+ return idx;
+}
+
void set_tlb(u8 tlb, u32 epn, u64 rpn,
u8 perms, u8 wimge,
u8 ts, u8 esel, u8 tsize, u8 iprot)
{
u32 _mas0, _mas1, _mas2, _mas3, _mas7;
+ if (tlb == 1)
+ use_tlb_cam(esel);
+
_mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
_mas2 = FSL_BOOKE_MAS2(epn, wimge);
{
u32 _mas0, _mas1, _mas2, _mas3, _mas7;
+ free_tlb_cam(esel);
+
_mas0 = FSL_BOOKE_MAS0(1, esel, 0);
_mas1 = 0;
_mas2 = 0;
void init_addr_map(void)
{
int i;
- unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff;
+ unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
/* walk all the entries */
- for (i = 0; i < max_cam; i++) {
+ for (i = 0; i < num_cam; i++) {
unsigned long epn;
u32 tsize, _mas1;
phys_addr_t rpn;
}
#endif
-#ifndef CONFIG_SYS_DDR_TLB_START
-#define CONFIG_SYS_DDR_TLB_START 8
-#endif
-
unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
{
+ int i;
unsigned int tlb_size;
- unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
u64 size, memsize = (u64)memsize_in_meg << 20;
/* Convert (4^max) kB to (2^max) bytes */
max_cam = max_cam * 2 + 10;
- for (; size && ram_tlb_index < 16; ram_tlb_index++) {
+ for (i = 0; size && i < 8; i++) {
+ int ram_tlb_index = find_free_tlbcam();
u32 camsize = __ilog2_u64(size) & ~1U;
u32 align = __ilog2(ram_tlb_address) & ~1U;
+ if (ram_tlb_index == -1)
+ break;
+
if (align == -2) align = max_cam;
if (camsize > align)
camsize = align;
.text :
{
*(.text)
- *(.fixup)
*(.got1)
} :text
_etext = .;
* The DDR3 spec has not tXARD,
* we use the tXP instead of it.
* tXP=max(3nCK, 7.5ns) for DDR3.
- * we use the tXP=6
* spec has not the tAXPD, we use
* tAXPD=8, need design to confirm.
*/
- act_pd_exit_mclk = 6;
- pre_pd_exit_mclk = 6;
+ int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
+ act_pd_exit_mclk = picos_to_mclk(tXP);
+ /* Mode register MR0[A12] is '1' - fast exit */
+ pre_pd_exit_mclk = act_pd_exit_mclk;
taxpd_mclk = 8;
tmrd_mclk = 4;
#else /* CONFIG_FSL_DDR2 */
}
/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr)
+static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts)
{
unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
#if defined(CONFIG_FSL_DDR3)
- unsigned int rtt_wr = 2; /* 120 ohm Rtt_WR */
+ unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
unsigned int srt = 0; /* self-refresh temerature, normal range */
unsigned int asr = 0; /* auto self-refresh disable */
unsigned int cwl = compute_cas_write_latency() - 5;
unsigned int pasr = 0; /* partial array self refresh disable */
+ if (popts->rtt_override)
+ rtt_wr = popts->rtt_wr_override_value;
+
esdmode2 = (0
| ((rtt_wr & 0x3) << 9)
| ((srt & 0x1) << 7)
}
/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
-static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr,
- unsigned int wrlvl_en)
+static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
+ const memctl_options_t *popts)
{
/*
* First DQS pulse rising edge after margining mode
/* tWL_DQSEN min = 25 nCK, we set it 32 */
wrlvl_dqsen = 0x5;
/*
- * Write leveling sample time at least need 14 clocks
- * due to tWLO = 9, we set it 15 clocks
+ * Write leveling sample time at least need 6 clocks
+ * higher than tWLO to allow enough time for progagation
+ * delay and sampling the prime data bits.
*/
wrlvl_smpl = 0xf;
/*
* Write leveling start time
* The value use for the DQS_ADJUST for the first sample
* when write leveling is enabled.
- * we set it 1 clock delay
*/
wrlvl_start = 0x8;
+ /*
+ * Override the write leveling sample and start time
+ * according to specific board
+ */
+ if (popts->wrlvl_override) {
+ wrlvl_smpl = popts->wrlvl_sample;
+ wrlvl_start = popts->wrlvl_start;
+ }
}
ddr->ddr_wrlvl_cntl = (0
/* Don't set up boundaries for other CS
* other than CS0, if bank interleaving
* is enabled and not CS2+CS3 interleaved.
+ * But we need to set the ODT_RD_CFG and
+ * ODT_WR_CFG for CS1_CONFIG here.
*/
+ set_csn_config(i, ddr, popts, dimm_params);
break;
}
set_ddr_sdram_cfg_2(ddr, popts);
set_ddr_sdram_mode(ddr, popts, common_dimm,
cas_latency, additive_latency);
- set_ddr_sdram_mode_2(ddr);
+ set_ddr_sdram_mode_2(ddr, popts);
set_ddr_sdram_interval(ddr, popts, common_dimm);
set_ddr_data_init(ddr);
set_ddr_sdram_clk_cntl(ddr, popts);
set_timing_cfg_5(ddr);
set_ddr_zq_cntl(ddr, zq_en);
- set_ddr_wrlvl_cntl(ddr, wrlvl_en);
+ set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
set_ddr_sr_cntr(ddr, sr_it);
unsigned int ctrl_num)
{
unsigned int i;
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
const char *p;
-#endif
/* Chip select options. */
* meet the tQDSS under different loading.
*/
popts->wrlvl_en = 1;
+ popts->wrlvl_override = 0;
#endif
/*
simple_strtoul(p, NULL, 0);
}
}
+#endif
- if( (p = getenv("ba_intlv_ctl")) != NULL) {
+ if( ((p = getenv("ba_intlv_ctl")) != NULL) &&
+ (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
if (strcmp(p, "cs0_cs1") == 0)
popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
else if (strcmp(p, "cs2_cs3") == 0)
break;
}
}
-#endif
fsl_ddr_board_options(popts, pdimm, ctrl_num);
#include <pci.h>
struct pci_info {
- u16 agent;
u16 cfg;
};
-/* The agent field is a bit mask in which each bit represents the value of
- * cfg_host_agt[] signal and the bit is set of the given interface would be
- * in agent/end-point mode for the given interface.
- *
- * The same idea is true of the cfg field. The bit will be set if the
- * interface would be enabled based on the value of cfg_IO_ports[] signal
+/* The cfg field is a bit mask in which each bit represents the value of
+ * cfg_IO_ports[] signal and the bit is set if the interface would be
+ * enabled based on the value of cfg_IO_ports[] signal
*
* On MPC86xx/PQ3 based systems:
- * we extract cfg_host_agt from GUTS register PORBMSR
* we extract cfg_IO_ports from GUTS register PORDEVSR
*
* cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCI] = {
- .agent = (1 << 0) | (1 << 2),
.cfg = 0,
},
};
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCI] = {
- .agent = (1 << 0),
.cfg = 0,
},
};
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCI] = {
- .agent = (1 << 6),
.cfg = 0,
},
[LAW_TRGT_IF_PCIE_1] = {
- .agent = (1 << 5),
.cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7),
},
[LAW_TRGT_IF_PCIE_2] = {
- .agent = (1 << 3),
.cfg = (1 << 5) | (1 << 7),
},
[LAW_TRGT_IF_PCIE_3] = {
- .agent = (1 << 1),
.cfg = (1 << 7),
},
};
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCI] = {
- .agent = (1 << 6),
.cfg = 0,
},
[LAW_TRGT_IF_PCIE_1] = {
- .agent = (1 << 5),
.cfg = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
(1 << 6) | (1 << 7),
},
[LAW_TRGT_IF_PCIE_2] = {
- .agent = (1 << 3),
.cfg = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7),
},
[LAW_TRGT_IF_PCIE_3] = {
- .agent = (1 << 1),
.cfg = (1 << 6) | (1 << 7),
},
};
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCI_1] = {
- .agent = (1 << 4) | (1 << 6),
.cfg = 0,
},
[LAW_TRGT_IF_PCI_2] = {
- .agent = (1 << 4) | (1 << 6),
.cfg = 0,
},
/* PCI_2 is always host and we dont use iosel to determine enable/disable */
[LAW_TRGT_IF_PCIE_1] = {
- .agent = (1 << 0) | (1 << 2),
.cfg = (1 << 3) | (1 << 4) | (1 << 7),
},
};
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCI] = {
- .agent = (1 << 0) | (1 << 4) | (1 << 6),
.cfg = 0,
},
[LAW_TRGT_IF_PCIE_1] = {
- .agent = (1 << 0) | (1 << 2) | (1 << 4),
.cfg = (1 << 3) | (1 << 4) | (1 << 7),
},
};
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCIE_1] = {
- .agent = (1 << 0) | (1 << 6),
.cfg = (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) |
(1 << 8) | (1 << 0xc) | (1 << 0xf),
},
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCIE_1] = {
- .agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5),
.cfg = (1 << 2) | (1 << 3) | (1 << 7) |
(1 << 0xb) | (1 << 0xc) | (1 << 0xf),
},
[LAW_TRGT_IF_PCIE_2] = {
- .agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6),
.cfg = (1 << 3) | (1 << 7),
},
[LAW_TRGT_IF_PCIE_3] = {
- .agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6),
.cfg = (1 << 7),
},
};
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCI_1] = {
- .agent = (1 << 4) | (1 << 5) | (1 << 6),
.cfg = 0,
},
[LAW_TRGT_IF_PCIE_1] = {
- .agent = (1 << 0) | (1 << 2) | (1 << 5),
.cfg = (1 << 1) | (1 << 4),
},
[LAW_TRGT_IF_PCIE_2] = {
- .agent = (1 << 0) | (1 << 1) | (1 << 4),
.cfg = (1 << 0) | (1 << 4),
},
};
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCIE_1] = {
- .agent = 0, /* we dont use agent on 8641 */
.cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) |
(1 << 7) | (1 << 0xe) | (1 << 0xf),
},
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCIE_1] = {
- .agent = (1 << 0) | (1 << 1),
.cfg = (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf),
},
[LAW_TRGT_IF_PCIE_2] = {
- .agent = (1 << 0) | (1 << 2),
.cfg = (1 << 0xe),
},
};
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCIE_1] = {
- .agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5),
.cfg = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) |
(1 << 0xd) | (1 << 0xe) | (1 << 0xf),
},
[LAW_TRGT_IF_PCIE_2] = {
- .agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6),
.cfg = (1 << 2) | (1 << 0xe),
},
[LAW_TRGT_IF_PCIE_3] = {
- .agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6),
.cfg = (1 << 2) | (1 << 4),
},
};
+#elif defined(CONFIG_FSL_CORENET)
#else
#error Need to define pci_config_info for processor
#endif
-int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent)
-{
- return ((1 << host_agent) & pci_config_info[trgt].agent);
-}
-
+#ifndef CONFIG_FSL_CORENET
int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel)
{
return ((1 << io_sel) & pci_config_info[trgt].cfg);
}
+#endif
PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
- PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR);
+ PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES);
#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT))
PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
#include <common.h>
#include <command.h>
-#if !defined(CONFIG_440)
#include <asm/4xx_pci.h>
-#endif
#include <asm/processor.h>
+#include <asm/io.h>
#include <pci.h>
#ifdef CONFIG_PCI
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
+
+#if defined(CONFIG_PMC405)
+ushort pmc405_pci_subsys_deviceid(void);
+#endif
+
+/*#define DEBUG*/
+
/*
* Board-specific pci initialization
* Platform code can reimplement pci_pre_init() if needed
*/
int __pci_pre_init(struct pci_controller *hose)
{
-#if defined (CONFIG_405EP)
+#if defined(CONFIG_405EP)
/*
* Enable the internal PCI arbiter by default.
*
return 1;
}
-int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init")));
-
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
-
-#if defined(CONFIG_PMC405)
-ushort pmc405_pci_subsys_deviceid(void);
-#endif
-
-/*#define DEBUG*/
+int pci_pre_init(struct pci_controller *hose)
+ __attribute__((weak, alias("__pci_pre_init")));
int __is_pci_host(struct pci_controller *hose)
{
pciauto_region_init(hose->pci_fb);
/* Let board change/modify hose & do initial checks */
- if (pci_pre_init (hose) == 0) {
+ if (pci_pre_init(hose) == 0) {
printf("PCI: Board-specific initialization failed.\n");
printf("PCI: Configuration aborted.\n");
return;
static struct pci_controller ppc440_hose = {0};
+/*
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ * Weak default implementation: "Normal" boards implement the PCI
+ * host functionality. This can be overridden for PCI adapter boards.
+ */
+int __is_pci_host(struct pci_controller *hose)
+{
+ return 1;
+}
+int is_pci_host(struct pci_controller *hose)
+ __attribute__((weak, alias("__is_pci_host")));
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440GRX)
+
+#if defined(CONFIG_SYS_PCI_TARGET_INIT)
+/*
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
+void __pci_target_init(struct pci_controller *hose)
+{
+ /*
+ * Set up Direct MMIO registers
+ */
+
+ /*
+ * PowerPC440 EP PCI Master configuration.
+ * Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+ * Use byte reversed out routines to handle endianess.
+ * Make this region non-prefetchable.
+ */
+ /* PMM0 Mask/Attribute - disabled b4 setting */
+ out_le32((void *)PCIL0_PMM0MA, 0x00000000);
+ /* PMM0 Local Address */
+ out_le32((void *)PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
+ /* PMM0 PCI Low Address */
+ out_le32((void *)PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
+ /* PMM0 PCI High Address */
+ out_le32((void *)PCIL0_PMM0PCIHA, 0x00000000);
+ /* 512M + No prefetching, and enable region */
+ out_le32((void *)PCIL0_PMM0MA, 0xE0000001);
+
+ /* PMM1 Mask/Attribute - disabled b4 setting */
+ out_le32((void *)PCIL0_PMM1MA, 0x00000000);
+ /* PMM1 Local Address */
+ out_le32((void *)PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
+ /* PMM1 PCI Low Address */
+ out_le32((void *)PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
+ /* PMM1 PCI High Address */
+ out_le32((void *)PCIL0_PMM1PCIHA, 0x00000000);
+ /* 512M + No prefetching, and enable region */
+ out_le32((void *)PCIL0_PMM1MA, 0xE0000001);
+
+ out_le32((void *)PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out_le32((void *)PCIL0_PTM1LA, 0); /* Local Addr. Reg */
+ out_le32((void *)PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
+ out_le32((void *)PCIL0_PTM2LA, 0); /* Local Addr. Reg */
+
+ /*
+ * Set up Configuration registers
+ */
+
+ /* Program the board's subsystem id/vendor id */
+ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+ CONFIG_SYS_PCI_SUBSYS_VENDORID);
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
+
+ /* Configure command register as bus master */
+ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+ /* 240nS PCI clock */
+ pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+ /* No error reporting */
+ pci_write_config_word(0, PCI_ERREN, 0);
+
+ pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+}
+#endif /* CONFIG_SYS_PCI_TARGET_INIT */
+
+/*
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ */
+int __pci_pre_init(struct pci_controller *hose)
+{
+ u32 reg;
+
+ /*
+ * Set priority for all PLB3 devices to 0.
+ * Set PLB3 arbiter to fair mode.
+ */
+ mfsdr(SD0_AMP1, reg);
+ mtsdr(SD0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
+ reg = mfdcr(PLB3_ACR);
+ mtdcr(PLB3_ACR, reg | 0x80000000);
+
+ /*
+ * Set priority for all PLB4 devices to 0.
+ */
+ mfsdr(SD0_AMP0, reg);
+ mtsdr(SD0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
+ reg = mfdcr(PLB4_ACR) | 0xa0000000;
+ mtdcr(PLB4_ACR, reg);
+
+ /*
+ * Set Nebula PLB4 arbiter to fair mode.
+ */
+ /* Segment0 */
+ reg = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
+ reg = (reg & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
+ reg = (reg & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
+ reg = (reg & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
+ mtdcr(PLB0_ACR, reg);
+
+ /* Segment1 */
+ reg = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
+ reg = (reg & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
+ reg = (reg & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
+ reg = (reg & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
+ mtdcr(PLB1_ACR, reg);
+
+#if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
+ hose->fixup_irq = board_pci_fixup_irq;
+#endif
+
+ return 1;
+}
+
+#else /* defined(CONFIG_440EP) ... */
+
+#if defined(CONFIG_SYS_PCI_TARGET_INIT)
+void __pci_target_init(struct pci_controller * hose)
+{
+ /*
+ * Disable everything
+ */
+ out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
+ out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
+ out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
+ out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
+
+ /*
+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
+ * strapping options do not support sizes such as 128/256 MB.
+ */
+ out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+ out_le32((void *)PCIL0_PIM0LAH, 0);
+ out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
+ out_le32((void *)PCIL0_BAR0, 0);
+
+ /*
+ * Program the board's subsystem id/vendor id
+ */
+ out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+ out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+
+ out_le16((void *)PCIL0_CMD, in_le16((void *)PCIL0_CMD) |
+ PCI_COMMAND_MEMORY);
+}
+#endif /* CONFIG_SYS_PCI_TARGET_INIT */
+
+int __pci_pre_init(struct pci_controller *hose)
+{
+ /*
+ * This board is always configured as the host & requires the
+ * PCI arbiter to be enabled.
+ */
+ if (!pci_arbiter_enabled()) {
+ printf("PCI: PCI Arbiter disabled!\n");
+ return 0;
+ }
+
+ return 1;
+}
+
+#endif /* defined(CONFIG_440EP) ... */
+
+#if defined(CONFIG_SYS_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose)
+ __attribute__((weak, alias("__pci_target_init")));
+#endif /* CONFIG_SYS_PCI_TARGET_INIT */
+
+int pci_pre_init(struct pci_controller *hose)
+ __attribute__((weak, alias("__pci_pre_init")));
+
+#if defined(CONFIG_SYS_PCI_MASTER_INIT)
+void __pci_master_init(struct pci_controller *hose)
+{
+ u16 reg;
+
+ /*
+ * Write the PowerPC440 EP PCI Configuration regs.
+ * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ * Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ */
+ pci_read_config_word(0, PCI_COMMAND, ®);
+ pci_write_config_word(0, PCI_COMMAND, reg |
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+}
+void pci_master_init(struct pci_controller *hose)
+ __attribute__((weak, alias("__pci_master_init")));
+#endif /* CONFIG_SYS_PCI_MASTER_INIT */
int pci_440_init (struct pci_controller *hose)
{
pci_setup_indirect(hose, PCIL0_CFGADR, PCIL0_CFGDATA);
/* Let board change/modify hose & do initial checks */
- if (pci_pre_init (hose) == 0) {
+ if (pci_pre_init(hose) == 0) {
printf("PCI: Board-specific initialization failed.\n");
printf("PCI: Configuration aborted.\n");
return -1;
LNKW_X8 = 0x8
};
+static struct pci_controller pcie_hose[CONFIG_SYS_PCIE_NR_PORTS];
+
+/*
+ * Per default, all cards are present, so we need to check if the
+ * link comes up.
+ */
+int __board_pcie_card_present(int port)
+{
+ return 1;
+}
+int board_pcie_card_present(int port)
+ __attribute__((weak, alias("__board_pcie_card_present")));
+
+/*
+ * Some boards have runtime detection of the first and last PCIe
+ * slot used, so let's provide weak default functions for the
+ * common version.
+ */
+int __board_pcie_first(void)
+{
+ return 0;
+}
+int board_pcie_first(void)
+ __attribute__((weak, alias("__board_pcie_first")));
+
+int __board_pcie_last(void)
+{
+ return CONFIG_SYS_PCIE_NR_PORTS - 1;
+}
+int board_pcie_last(void)
+ __attribute__((weak, alias("__board_pcie_last")));
+
+void __board_pcie_setup_port(int port, int rootpoint)
+{
+ /* noting in this weak default implementation */
+}
+void board_pcie_setup_port(int port, int rootpoint)
+ __attribute__((weak, alias("__board_pcie_setup_port")));
+
+void pcie_setup_hoses(int busno)
+{
+ struct pci_controller *hose;
+ int i, bus;
+ int ret = 0;
+ char *env;
+ unsigned int delay;
+ int first = board_pcie_first();
+ int last = board_pcie_last();
+
+ /*
+ * Assume we're called after the PCI(X) hose(s) are initialized,
+ * which takes bus ID 0... and therefore start numbering PCIe's
+ * from the next number.
+ */
+ bus = busno;
+
+ for (i = first; i <= last; i++) {
+ /*
+ * Some boards (e.g. Katmai) can detects via hardware
+ * if a PCIe card is plugged, so let's check this.
+ */
+ if (!board_pcie_card_present(i))
+ continue;
+
+ if (is_end_point(i)) {
+ board_pcie_setup_port(i, 0);
+ ret = ppc4xx_init_pcie_endport(i);
+ } else {
+ board_pcie_setup_port(i, 1);
+ ret = ppc4xx_init_pcie_rootport(i);
+ }
+ if (ret == -ENODEV)
+ continue;
+ if (ret) {
+ printf("PCIE%d: initialization as %s failed\n", i,
+ is_end_point(i) ? "endpoint" : "root-complex");
+ continue;
+ }
+
+ hose = &pcie_hose[i];
+ hose->first_busno = bus;
+ hose->last_busno = bus;
+ hose->current_busno = bus;
+
+ /* setup mem resource */
+ pci_set_region(hose->regions + 0,
+ CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+ CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+ CONFIG_SYS_PCIE_MEMSIZE,
+ PCI_REGION_MEM);
+ hose->region_count = 1;
+ pci_register_hose(hose);
+
+ if (is_end_point(i)) {
+ ppc4xx_setup_pcie_endpoint(hose, i);
+ /*
+ * Reson for no scanning is endpoint can not generate
+ * upstream configuration accesses.
+ */
+ } else {
+ ppc4xx_setup_pcie_rootpoint(hose, i);
+ env = getenv ("pciscandelay");
+ if (env != NULL) {
+ delay = simple_strtoul(env, NULL, 10);
+ if (delay > 5)
+ printf("Warning, expect noticable delay before "
+ "PCIe scan due to 'pciscandelay' value!\n");
+ mdelay(delay * 1000);
+ }
+
+ /*
+ * Config access can only go down stream
+ */
+ hose->last_busno = pci_hose_scan(hose);
+ bus = hose->last_busno + 1;
+ }
+ }
+}
+
static int validate_endpoint(struct pci_controller *hose)
{
if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE0_CFGBASE)
int cur_config_nr = -1;
u8 cur_config[CONFIG_4xx_CONFIG_BLOCKSIZE];
+ /*
+ * First switch to correct I2C bus. This is I2C bus 0
+ * for all currently available 4xx derivats.
+ */
+ I2C_SET_BUS(0);
+
#ifdef CONFIG_CMD_EEPROM
ret = eeprom_read(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET,
else
PLATFORM_CPPFLAGS += -Wa,-m405 -mcpu=405
endif
+
+# Use default linker script. Board port can override in board/*/config.mk
+LDSCRIPT := $(SRCTREE)/cpu/ppc4xx/u-boot.lds
#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
!defined(CONFIG_405) && !defined(CONFIG_405EX)
-static int pci_arbiter_enabled(void)
+int pci_arbiter_enabled(void)
{
#if defined(CONFIG_405GP)
return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_I2C_MULTI_BUS)
-/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
+/*
+ * Initialize the bus pointer to whatever one the SPD EEPROM is on.
* Default is bus 0. This is necessary because the DDR initialization
* runs from ROM, and we can't switch buses because we can't modify
* the global variables.
#ifndef CONFIG_SYS_SPD_BUS_NUM
#define CONFIG_SYS_SPD_BUS_NUM 0
#endif
-static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM;
+static unsigned int i2c_bus_num __attribute__ ((section (".data"))) =
+ CONFIG_SYS_SPD_BUS_NUM;
#endif /* CONFIG_I2C_MULTI_BUS */
static void _i2c_bus_reset(void)
{
+ struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
int i;
u8 dc;
/* Reset status register */
/* write 1 in SCMP and IRQA to clear these fields */
- out_8((u8 *)IIC_STS, 0x0A);
+ out_8(&i2c->sts, 0x0A);
/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
- out_8((u8 *)IIC_EXTSTS, 0x8F);
+ out_8(&i2c->extsts, 0x8F);
/* Place chip in the reset state */
- out_8((u8 *)IIC_XTCNTLSS, IIC_XTCNTLSS_SRST);
+ out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST);
/* Check if bus is free */
- dc = in_8((u8 *)IIC_DIRECTCNTL);
+ dc = in_8(&i2c->directcntl);
if (!DIRCTNL_FREE(dc)){
/* Try to set bus free state */
- out_8((u8 *)IIC_DIRECTCNTL, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
+ out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
/* Wait until we regain bus control */
for (i = 0; i < 100; ++i) {
- dc = in_8((u8 *)IIC_DIRECTCNTL);
+ dc = in_8(&i2c->directcntl);
if (DIRCTNL_FREE(dc))
break;
/* Toggle SCL line */
dc ^= IIC_DIRCNTL_SCC;
- out_8((u8 *)IIC_DIRECTCNTL, dc);
+ out_8(&i2c->directcntl, dc);
udelay(10);
dc ^= IIC_DIRCNTL_SCC;
- out_8((u8 *)IIC_DIRECTCNTL, dc);
+ out_8(&i2c->directcntl, dc);
}
}
/* Remove reset */
- out_8((u8 *)IIC_XTCNTLSS, 0);
+ out_8(&i2c->xtcntlss, 0);
}
-void i2c_init(int speed, int slaveadd)
+void i2c_init(int speed, int slaveaddr)
{
- unsigned long freqOPB;
+ struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
int val, divisor;
int bus;
#ifdef CONFIG_SYS_I2C_INIT_BOARD
- /* call board specific i2c bus reset routine before accessing the */
- /* environment, which might be in a chip on that bus. For details */
- /* about this problem see doc/I2C_Edge_Conditions. */
+ /*
+ * Call board specific i2c bus reset routine before accessing the
+ * environment, which might be in a chip on that bus. For details
+ * about this problem see doc/I2C_Edge_Conditions.
+ */
i2c_init_board();
#endif
_i2c_bus_reset();
/* clear lo master address */
- out_8((u8 *)IIC_LMADR, 0);
+ out_8(&i2c->lmadr, 0);
/* clear hi master address */
- out_8((u8 *)IIC_HMADR, 0);
+ out_8(&i2c->hmadr, 0);
/* clear lo slave address */
- out_8((u8 *)IIC_LSADR, 0);
+ out_8(&i2c->lsadr, 0);
/* clear hi slave address */
- out_8((u8 *)IIC_HSADR, 0);
+ out_8(&i2c->hsadr, 0);
/* Clock divide Register */
- /* get OPB frequency */
- freqOPB = get_OPB_freq();
- /* set divisor according to freqOPB */
- divisor = (freqOPB - 1) / 10000000;
+ /* set divisor according to freq_opb */
+ divisor = (get_OPB_freq() - 1) / 10000000;
if (divisor == 0)
divisor = 1;
- out_8((u8 *)IIC_CLKDIV, divisor);
+ out_8(&i2c->clkdiv, divisor);
/* no interrupts */
- out_8((u8 *)IIC_INTRMSK, 0);
+ out_8(&i2c->intrmsk, 0);
/* clear transfer count */
- out_8((u8 *)IIC_XFRCNT, 0);
+ out_8(&i2c->xfrcnt, 0);
/* clear extended control & stat */
/* write 1 in SRC SRS SWC SWS to clear these fields */
- out_8((u8 *)IIC_XTCNTLSS, 0xF0);
+ out_8(&i2c->xtcntlss, 0xF0);
/* Mode Control Register
Flush Slave/Master data buffer */
- out_8((u8 *)IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
+ out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
- val = in_8((u8 *)IIC_MDCNTL);
+ val = in_8(&i2c->mdcntl);
/* Ignore General Call, slave transfers are ignored,
* disable interrupts, exit unknown bus state, enable hold
* SCL 100kHz normaly or FastMode for 400kHz and above
*/
- val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
+ val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL;
if (speed >= 400000)
val |= IIC_MDCNTL_FSM;
- out_8((u8 *)IIC_MDCNTL, val);
+ out_8(&i2c->mdcntl, val);
/* clear control reg */
- out_8((u8 *)IIC_CNTL, 0x00);
+ out_8(&i2c->cntl, 0x00);
}
/* set to SPD bus as default bus upon powerup */
unsigned char data[],
unsigned short data_len)
{
- unsigned char* ptr;
+ struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
+ u8 *ptr;
int reading;
- int tran,cnt;
+ int tran, cnt;
int result;
int status;
int i;
- uchar creg;
+ u8 creg;
if (data == 0 || data_len == 0) {
/* Don't support data transfer of no length or to address 0 */
}
/* Clear Stop Complete Bit */
- out_8((u8 *)IIC_STS, IIC_STS_SCMP);
+ out_8(&i2c->sts, IIC_STS_SCMP);
+
/* Check init */
i = 10;
do {
/* Get status */
- status = in_8((u8 *)IIC_STS);
+ status = in_8(&i2c->sts);
i--;
} while ((status & IIC_STS_PT) && (i > 0));
result = IIC_NOK_TOUT;
return(result);
}
+
/* flush the Master/Slave Databuffers */
- out_8((u8 *)IIC_MDCNTL, ((in_8((u8 *)IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
+ out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) |
+ IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB);
+
/* need to wait 4 OPB clocks? code below should take that long */
/* 7-bit adressing */
- out_8((u8 *)IIC_HMADR, 0);
- out_8((u8 *)IIC_LMADR, chip);
+ out_8(&i2c->hmadr, 0);
+ out_8(&i2c->lmadr, chip);
tran = 0;
result = IIC_OK;
while (tran != cnt && (result == IIC_OK)) {
int bc,j;
- /* Control register =
- * Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
- * Transfer is a sequence of transfers
+ /*
+ * Control register =
+ * Normal transfer, 7-bits adressing, Transfer up to
+ * bc bytes, Normal start, Transfer is a sequence of transfers
*/
creg |= IIC_CNTL_PT;
if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
creg |= IIC_CNTL_CHT;
- if (reading)
+ if (reading) {
creg |= IIC_CNTL_READ;
- else
- for(j=0; j < bc; j++)
+ } else {
+ for(j = 0; j < bc; j++) {
/* Set buffer */
- out_8((u8 *)IIC_MDBUF, ptr[tran+j]);
- out_8((u8 *)IIC_CNTL, creg);
+ out_8(&i2c->mdbuf, ptr[tran + j]);
+ }
+ }
+ out_8(&i2c->cntl, creg);
- /* Transfer is in progress
+ /*
+ * Transfer is in progress
* we have to wait for upto 5 bytes of data
* 1 byte chip address+r/w bit then bc bytes
* of data.
* udelay(10) is 1 bit time at 100khz
* Doubled for slop. 20 is too small.
*/
- i = 2*5*8;
+ i = 2 * 5 * 8;
do {
/* Get status */
- status = in_8((u8 *)IIC_STS);
+ status = in_8(&i2c->sts);
udelay(10);
i--;
- } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) && (i > 0));
+ } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) &&
+ (i > 0));
if (status & IIC_STS_ERR) {
result = IIC_NOK;
- status = in_8((u8 *)IIC_EXTSTS);
+ status = in_8(&i2c->extsts);
/* Lost arbitration? */
if (status & IIC_EXTSTS_LA)
result = IIC_NOK_LA;
} else if ( status & IIC_STS_PT) {
result = IIC_NOK_TOUT;
}
+
/* Command is reading => get buffer */
if ((reading) && (result == IIC_OK)) {
/* Are there data in buffer */
if (status & IIC_STS_MDBS) {
/*
- * even if we have data we have to wait 4OPB clocks
- * for it to hit the front of the FIFO, after that
- * we can just read. We should check XFCNT here and
- * if the FIFO is full there is no need to wait.
+ * even if we have data we have to wait 4OPB
+ * clocks for it to hit the front of the FIFO,
+ * after that we can just read. We should check
+ * XFCNT here and if the FIFO is full there is
+ * no need to wait.
*/
udelay(1);
- for (j=0; j<bc; j++)
- ptr[tran+j] = in_8((u8 *)IIC_MDBUF);
+ for (j = 0; j < bc; j++)
+ ptr[tran + j] = in_8(&i2c->mdbuf);
} else
result = IIC_NOK_DATA;
}
creg = IIC_CNTL_RPST;
}
}
- return (result);
+ return result;
}
int i2c_probe(uchar chip)
* address was <ACK>ed (i.e. there was a chip at that address which
* drove the data line low).
*/
- return (i2c_transfer(1, chip << 1, 0,0, buf, 1) != 0);
+ return (i2c_transfer(1, chip << 1, 0, 0, buf, 1) != 0);
}
-
-int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
+static int ppc4xx_i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer,
+ int len, int read)
{
uchar xaddr[4];
int ret;
if (alen > 4) {
- printf ("I2C read: addr len %d not supported\n", alen);
+ printf("I2C: addr len %d not supported\n", alen);
return 1;
}
* hidden in the chip address.
*/
if (alen > 0)
- chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+ chip |= ((addr >> (alen * 8)) &
+ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
- if ((ret = i2c_transfer(1, chip<<1, &xaddr[4-alen], alen, buffer, len)) != 0) {
- if (gd->have_console)
- printf( "I2c read: failed %d\n", ret);
+ if ((ret = i2c_transfer(read, chip << 1, &xaddr[4 - alen], alen,
+ buffer, len)) != 0) {
+ if (gd->have_console) {
+ printf("I2C %s: failed %d\n",
+ read ? "read" : "write", ret);
+ }
+
return 1;
}
+
return 0;
}
-int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
+int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
{
- uchar xaddr[4];
-
- if (alen > 4) {
- printf ("I2C write: addr len %d not supported\n", alen);
- return 1;
-
- }
-
- if (alen > 0) {
- xaddr[0] = (addr >> 24) & 0xFF;
- xaddr[1] = (addr >> 16) & 0xFF;
- xaddr[2] = (addr >> 8) & 0xFF;
- xaddr[3] = addr & 0xFF;
- }
-
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
- /*
- * EEPROM chips that implement "address overflow" are ones
- * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
- * address and the extra bits end up in the "chip address"
- * bit slots. This makes a 24WC08 (1Kbyte) chip look like
- * four 256 byte chips.
- *
- * Note that we consider the length of the address field to
- * still be one byte because the extra address bits are
- * hidden in the chip address.
- */
- if (alen > 0)
- chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
-#endif
+ return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 1);
+}
- return (i2c_transfer(0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
+int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+ return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 0);
}
#if defined(CONFIG_I2C_MULTI_BUS)
/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
+#include "config.h" /* CONFIG_BOARDDIR */
+
+#ifndef RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
-SECTIONS
+PHDRS
{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+SECTIONS
+{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.plt : { *(.plt) }
.text :
{
- cpu/ppc4xx/start.o (.text)
- board/pcs440ep/init.o (.text)
- lib_generic/sha1.o (.text)
-
*(.text)
*(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
+ } :text
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
+ } :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
. = ALIGN(256);
__init_end = .;
+#ifdef CONFIG_440
+ .bootpg RESET_VECTOR_ADDRESS - 0xffc :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+
+ /*
+ * PPC440 board need a board specific object with the
+ * TLB definitions. This needs to get included right after
+ * start.o, since the first shadow TLB only covers 4k
+ * of address space.
+ */
+ CONFIG_BOARDDIR/init.o (.bootpg)
+ } :text = 0xffff
+#endif
+
+ .resetvec RESET_VECTOR_ADDRESS :
+ {
+ *(.resetvec)
+ } :text = 0xffff
+
+ . = RESET_VECTOR_ADDRESS + 0x4;
+
+ /*
+ * Make sure that the bss segment isn't linked at 0x0, otherwise its
+ * address won't be updated during relocation fixups. Note that
+ * this is a temporary fix. Code to dynamically the fixup the bss
+ * location will be added in the future. When the bss relocation
+ * fixup code is present this workaround should be removed.
+ */
+#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
+ . |= 0x10;
+#endif
+
__bss_start = .;
.bss (NOLOAD) :
{
*(.dynbss)
*(.bss)
*(COMMON)
- . = ALIGN(4);
- }
+ } :bss
+ . = ALIGN(4);
_end = . ;
PROVIDE (end = .);
}
{
/*will hold the packet received */
struct usb_device_descriptor usb_device_packet;
- struct usb_config_descriptor usb_config_packet;
+ struct usb_configuration_descriptor usb_config_packet;
struct usb_string_descriptor usb_string_packet;
struct devrequest setup_packet;
unsigned int *setup_packet_pt;
usb_config_packet.bConfigurationValue = 1;
usb_config_packet.iConfiguration = 0;
usb_config_packet.bmAttributes = 0x40;
- usb_config_packet.MaxPower = 0;
+ usb_config_packet.bMaxPower = 0;
/*put packet in fifo */
packet_pt = (unsigned char *)&usb_config_packet;
/* nop */
}
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
udelay_masked (usec);
}
timestamp = t;
}
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
ulong tmo;
/* nop */
}
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
udelay_masked (usec);
}
if (dev_desc->lba48)
printf (" Supports 48-bit addressing\n");
#endif
-#if defined(CONFIG_SYS_64BIT_LBA) && defined(CONFIG_SYS_64BIT_VSPRINTF)
+#if defined(CONFIG_SYS_64BIT_LBA)
printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%Ld x %ld)\n",
mb_quot, mb_rem,
gb_quot, gb_rem,
--- /dev/null
+Summary
+=======
+
+This README is about U-Boot support for TI's ARM 926EJS based family of SoCs.
+These SOCs are used for cameras, video security and surveillance, DVR's, etc.
+DaVinci SOC's comprise of DM644x, DM646x, DM35x and DM36x series of SOC's
+Additionally there are some SOCs meant for the audio market which though have
+an OMAP part number are very similar to the DaVinci series of SOC's
+Additionally, some family members contain a TI DSP and/or graphics
+co processors along with a host of other peripherals.
+
+Currently the following boards are supported:
+
+* TI DaVinci DM644x EVM
+
+* TI DaVinci DM646x EVM
+
+* TI DaVinci DM355 EVM
+
+* TI DaVinci DM365 EVM
+
+* TI DA830 EVM
+
+* DM355 based Leopard board
+
+* DM644x based schmoogie board
+
+* DM644x based sffsdr board
+
+* DM644x based sonata board
+
+Build
+=====
+
+* TI DaVinci DM644x EVM:
+
+make davinci_dvevm_config
+make
+
+* TI DaVinci DM646x EVM:
+
+make davinci_dm6467evm_config
+make
+
+* TI DaVinci DM355 EVM:
+
+make davinci_dm355evm_config
+make
+
+* TI DaVinci DM365 EVM:
+
+make davinci_dm365evm_config
+make
+
+* TI DA830 EVM:
+
+make da830evm_config
+make
+
+* DM355 based Leopard board:
+
+make davinci_dm355leopard_config
+make
+
+* DM644x based schmoogie board:
+
+make davinci_schmoogie_config
+make
+
+* DM644x based sffsdr board:
+
+make davinci_sffsdr_config
+make
+
+* DM644x based sonata board:
+
+make davinci_sonata_config
+make
+
+Bootloaders
+===============
+
+The DaVinci SOC's use 2 bootloaders. The low level initialization
+is done by a UBL(user boot loader). The UBL is written to a NAND/NOR/SPI flash
+by a programmer. During initial bootup, the ROM Bootloader reads the UBL
+from a storage device and loads it into the IRAM. The UBL then loads the U-Boot
+into the RAM.
+The programmers and UBL are always released as part of any standard TI
+software release associated with an SOC.
+
+Links
+=====
+
+1) TI DaVinci DM355 EVM:
+http://focus.ti.com/docs/prod/folders/print/tms320dm355.html
+http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=203&osCsid=c499af6087317f11b3da19b4e8f1af32
+
+2) TI DaVinci DM365 EVM:
+http://focus.ti.com/docs/prod/folders/print/tms320dm365.html?247SEM=
+http://support.spectrumdigital.com/boards/evmdm365/revc/
+
+3) DaVinci DM355 based leopard board
+http://designsomething.org/leopardboard/default.aspx
+http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=192&osCsid=67c20335668ffc57cb35727106eb24b1
+
+4) TI DaVinci DM6467 EVM:
+http://focus.ti.com/docs/prod/folders/print/tms320dm6467.html
+http://support.spectrumdigital.com/boards/evmdm6467/revf/
+
+5) TI DaVinci DM6446 EVM:
+http://focus.ti.com/docs/prod/folders/print/tms320dm6446.html
+http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=222
+
+6) TI DA830 EVM
+http://focus.ti.com/apps/docs/gencontent.tsp?appId=1&contentId=52385
+http://www.spectrumdigital.com/product_info.php?cPath=37&products_id=214
The recv function should process packets as long as the hardware has them
readily available before returning. i.e. you should drain the hardware fifo.
-The common code sets up packet buffers for you already (NetRxPackets), so there
-is no need to allocate your own. For each packet you receive, you should call
-the NetReceive() function on it with the packet length. So the pseudo code
-here would look something like:
+For each packet you receive, you should call the NetReceive() function on it
+along with the packet length. The common code sets up packet buffers for you
+already in the .bss (NetRxPackets), so there should be no need to allocate your
+own. This doesn't mean you must use the NetRxPackets array however; you're
+free to call the NetReceive() function with any buffer you wish. So the pseudo
+code here would look something like:
int ape_recv(struct eth_device *dev)
{
int length, i = 0;
}
The halt function should turn off / disable the hardware and place it back in
-its reset state.
+its reset state. It can be called at any time (before any call to the related
+init function), so make sure it can handle this sort of thing.
So the call graph at this stage would look something like:
some net operation (ping / tftp / whatever...)
4321 4321
(where the '*' indicates the position of the tab of the switch.)
+ To boot the image at the beginning of NAND flash, use these
+ DIP switch settings for S3 S4:
+
+ +------+ +------+
+ | * | | *** |
+ | *** | | * |
+ +------+ ON +------+ ON
+ 4321 4321
+ (where the '*' indicates the position of the tab of the switch.)
+
+ When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
+
2. Memory Map
The memory map looks like this:
0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K
0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
+ When booting from NAND, NAND flash is CS0 and NOR flash
+ is CS1.
+
3. Definitions
3.1 Explanation of NEW definitions in:
export CROSS_COMPILE=your-cross-compiler-prefix-
make distclean
- make MPC8315ERDB_config
+ make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
make all
5. Downloading and Flashing Images
5.1 Reflash U-boot Image using U-boot
+ NOR flash:
+
tftp 40000 u-boot.bin
protect off all
erase fe000000 fe1fffff
You have to supply the correct byte count with 'xxxx'
from the TFTP result log.
+ NAND flash:
+
+ =>tftpboot $loadaddr <filename>
+ =>nand erase 0 0x80000
+ =>nand write $loadaddr 0 0x80000
+
+ ...where 0x80000 is the filesize rounded up to
+ the next 0x20000 increment.
+
5.2 Downloading and Booting Linux Kernel
Ensure that all networking-related environment variables are set
6 Notes
- Booting from NAND flash is not yet supported.
The console baudrate for MPC8315ERDB is 115200bps.
/*
* Simple U-boot uImage source file containing a single kernel
*/
+
+/dts-v1/;
+
/ {
description = "Simple image with single Linux kernel";
#address-cells = <1>;
/*
* Simple U-boot uImage source file containing a single kernel and FDT blob
*/
+
+/dts-v1/;
+
/ {
description = "Simple image with single Linux kernel and FDT blob";
#address-cells = <1>;
/*
* U-boot uImage source file with multiple kernels, ramdisks and FDT blobs
*/
+
+/dts-v1/;
+
/ {
description = "Various kernels, ramdisks and FDT blobs";
#address-cells = <1>;
/*
* Example Automatic software update file.
*/
+
+/dts-v1/;
+
/ {
description = "Automatic software updates: kernel, ramdisk, FDT";
#address-cells = <1>;
* Automatic software update for U-Boot
* Make sure the flashing addresses ('load' prop) is correct for your board!
*/
+
+/dts-v1/;
+
/ {
description = "Automatic U-Boot update";
#address-cells = <1>;
CFLAGS += $(EXTRA_CFLAGS)
HOSTCFLAGS += $(EXTRA_CFLAGS)
+CPPFLAGS += $(EXTRA_CFLAGS)
all: $(LIB)
COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o
+COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
#ifdef TWI0_CLKDIV
#define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val)
+#define bfin_read_TWI_CLKDIV(val) bfin_read_TWI0_CLKDIV(val)
#define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val)
#define bfin_read_TWI_CONTROL(val) bfin_read_TWI0_CONTROL(val)
#define bfin_write_TWI_MASTER_ADDR(val) bfin_write_TWI0_MASTER_ADDR(val)
#ifdef CONFIG_TWICLK_KHZ
# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED
#endif
-#if CONFIG_SYS_I2C_SPEED > 400000
-# error The Blackfin I2C hardware can only operate at 400KHz max
+
+/*
+ * The way speed is changed into duty often results in integer truncation
+ * with 50% duty, so we'll force rounding up to the next duty by adding 1
+ * to the max. In practice this will get us a speed of something like
+ * 385 KHz. The other limit is easy to handle as it is only 8 bits.
+ */
+#define I2C_SPEED_MAX 400000
+#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
+#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
+#define I2C_DUTY_MIN 0xff /* 8 bit limited */
+#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
+/* Note: duty is inverse of speed, so the comparisons below are correct */
+#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
+# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz"
#endif
/* All transfers are described by this data structure */
u8 *abuf; /* addr buffer */
};
+/* Allow msec timeout per ~byte transfer */
+#define I2C_TIMEOUT 10
+
/**
* wait_for_completion - manage the actual i2c transfer
* @msg: the i2c msg
static int wait_for_completion(struct i2c_msg *msg)
{
uint16_t int_stat;
+ ulong timebase = get_timer(0);
- while (!ctrlc()) {
+ do {
int_stat = bfin_read_TWI_INT_STAT();
if (int_stat & XMTSERV) {
debugi("processing MERR");
bfin_write_TWI_INT_STAT(MERR);
SSYNC();
- break;
+ return msg->len;
}
if (int_stat & MCOMP) {
debugi("processing MCOMP");
} else
break;
}
- }
+
+ /* If we were able to do something, reset timeout */
+ if (int_stat)
+ timebase = get_timer(0);
+
+ } while (get_timer(timebase) < I2C_TIMEOUT);
return msg->len;
}
return ret;
}
-/*
+/**
+ * i2c_set_bus_speed - set i2c bus speed
+ * @speed: bus speed (in HZ)
+ */
+int i2c_set_bus_speed(unsigned int speed)
+{
+ u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
+
+ /* Set TWI interface clock */
+ if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
+ return -1;
+ bfin_write_TWI_CLKDIV((clkdiv << 8) | (clkdiv & 0xff));
+
+ /* Don't turn it on */
+ bfin_write_TWI_MASTER_CTL(speed > 100000 ? FAST : 0);
+
+ return 0;
+}
+
+/**
+ * i2c_get_bus_speed - get i2c bus speed
+ * @speed: bus speed (in HZ)
+ */
+unsigned int i2c_get_bus_speed(void)
+{
+ /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */
+ return 5000000 / (bfin_read_TWI_CLKDIV() & 0xff);
+}
+
+/**
* i2c_init - initialize the i2c bus
* @speed: bus speed (in HZ)
* @slaveaddr: address of device in slave mode (0 - not slave)
bfin_write_TWI_CONTROL(prescale);
/* Set TWI interface clock as specified */
- bfin_write_TWI_CLKDIV(
- ((5 * 1024 / (speed / 1000)) << 8) |
- ((5 * 1024 / (speed / 1000)) & 0xFF)
- );
-
- /* Don't turn it on */
- bfin_write_TWI_MASTER_CTL(speed > 100000 ? FAST : 0);
+ i2c_set_bus_speed(speed);
- /* But enable it */
+ /* Enable it */
bfin_write_TWI_CONTROL(TWI_ENA | prescale);
SSYNC();
static u16 wait_for_pin (void);
static void flush_fifo(void);
+static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;
+
+static unsigned int bus_initialized[I2C_BUS_MAX];
+static unsigned int current_bus;
+
void i2c_init (int speed, int slaveadd)
{
int psc, fsscll, fssclh;
sclh = (unsigned int)fssclh;
}
- writew(0x2, I2C_SYSC); /* for ES2 after soft reset */
+ writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
udelay(1000);
- writew(0x0, I2C_SYSC); /* will probably self clear but */
+ writew(0x0, &i2c_base->sysc); /* will probably self clear but */
- if (readw (I2C_CON) & I2C_CON_EN) {
- writew (0, I2C_CON);
+ if (readw (&i2c_base->con) & I2C_CON_EN) {
+ writew (0, &i2c_base->con);
udelay (50000);
}
- writew(psc, I2C_PSC);
- writew(scll, I2C_SCLL);
- writew(sclh, I2C_SCLH);
+ writew(psc, &i2c_base->psc);
+ writew(scll, &i2c_base->scll);
+ writew(sclh, &i2c_base->sclh);
/* own address */
- writew (slaveadd, I2C_OA);
- writew (I2C_CON_EN, I2C_CON);
+ writew (slaveadd, &i2c_base->oa);
+ writew (I2C_CON_EN, &i2c_base->con);
/* have to enable intrrupts or OMAP i2c module doesn't work */
writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
- I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE);
+ I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
udelay (1000);
flush_fifo();
- writew (0xFFFF, I2C_STAT);
- writew (0, I2C_CNT);
+ writew (0xFFFF, &i2c_base->stat);
+ writew (0, &i2c_base->cnt);
+
+ bus_initialized[current_bus] = 1;
}
static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
wait_for_bb ();
/* one byte only */
- writew (1, I2C_CNT);
+ writew (1, &i2c_base->cnt);
/* set slave address */
- writew (devaddr, I2C_SA);
+ writew (devaddr, &i2c_base->sa);
/* no stop bit needed here */
- writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON);
+ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con);
status = wait_for_pin ();
if (status & I2C_STAT_XRDY) {
/* Important: have to use byte access */
- writeb (regoffset, I2C_DATA);
+ writeb (regoffset, &i2c_base->data);
udelay (20000);
- if (readw (I2C_STAT) & I2C_STAT_NACK) {
+ if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
i2c_error = 1;
}
} else {
if (!i2c_error) {
/* free bus, otherwise we can't use a combined transction */
- writew (0, I2C_CON);
- while (readw (I2C_STAT) || (readw (I2C_CON) & I2C_CON_MST)) {
+ writew (0, &i2c_base->con);
+ while (readw (&i2c_base->stat) || (readw (&i2c_base->con) & I2C_CON_MST)) {
udelay (10000);
/* Have to clear pending interrupt to clear I2C_STAT */
- writew (0xFFFF, I2C_STAT);
+ writew (0xFFFF, &i2c_base->stat);
}
wait_for_bb ();
/* set slave address */
- writew (devaddr, I2C_SA);
+ writew (devaddr, &i2c_base->sa);
/* read one byte from slave */
- writew (1, I2C_CNT);
+ writew (1, &i2c_base->cnt);
/* need stop bit here */
writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
- I2C_CON);
+ &i2c_base->con);
status = wait_for_pin ();
if (status & I2C_STAT_RRDY) {
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
- *value = readb (I2C_DATA);
+ *value = readb (&i2c_base->data);
#else
- *value = readw (I2C_DATA);
+ *value = readw (&i2c_base->data);
#endif
udelay (20000);
} else {
}
if (!i2c_error) {
- writew (I2C_CON_EN, I2C_CON);
- while (readw (I2C_STAT)
- || (readw (I2C_CON) & I2C_CON_MST)) {
+ writew (I2C_CON_EN, &i2c_base->con);
+ while (readw (&i2c_base->stat)
+ || (readw (&i2c_base->con) & I2C_CON_MST)) {
udelay (10000);
- writew (0xFFFF, I2C_STAT);
+ writew (0xFFFF, &i2c_base->stat);
}
}
}
flush_fifo();
- writew (0xFFFF, I2C_STAT);
- writew (0, I2C_CNT);
+ writew (0xFFFF, &i2c_base->stat);
+ writew (0, &i2c_base->cnt);
return i2c_error;
}
wait_for_bb ();
/* two bytes */
- writew (2, I2C_CNT);
+ writew (2, &i2c_base->cnt);
/* set slave address */
- writew (devaddr, I2C_SA);
+ writew (devaddr, &i2c_base->sa);
/* stop bit needed here */
writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
- I2C_CON_STP, I2C_CON);
+ I2C_CON_STP, &i2c_base->con);
/* wait until state change */
status = wait_for_pin ();
if (status & I2C_STAT_XRDY) {
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
/* send out 1 byte */
- writeb (regoffset, I2C_DATA);
- writew (I2C_STAT_XRDY, I2C_STAT);
+ writeb (regoffset, &i2c_base->data);
+ writew (I2C_STAT_XRDY, &i2c_base->stat);
status = wait_for_pin ();
if ((status & I2C_STAT_XRDY)) {
/* send out next 1 byte */
- writeb (value, I2C_DATA);
- writew (I2C_STAT_XRDY, I2C_STAT);
+ writeb (value, &i2c_base->data);
+ writew (I2C_STAT_XRDY, &i2c_base->stat);
} else {
i2c_error = 1;
}
#else
/* send out two bytes */
- writew ((value << 8) + regoffset, I2C_DATA);
+ writew ((value << 8) + regoffset, &i2c_base->data);
#endif
/* must have enough delay to allow BB bit to go low */
udelay (50000);
- if (readw (I2C_STAT) & I2C_STAT_NACK) {
+ if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
i2c_error = 1;
}
} else {
if (!i2c_error) {
int eout = 200;
- writew (I2C_CON_EN, I2C_CON);
- while ((stat = readw (I2C_STAT)) || (readw (I2C_CON) & I2C_CON_MST)) {
+ writew (I2C_CON_EN, &i2c_base->con);
+ while ((stat = readw (&i2c_base->stat)) || (readw (&i2c_base->con) & I2C_CON_MST)) {
udelay (1000);
/* have to read to clear intrrupt */
- writew (0xFFFF, I2C_STAT);
+ writew (0xFFFF, &i2c_base->stat);
if(--eout == 0) /* better leave with error than hang */
break;
}
}
flush_fifo();
- writew (0xFFFF, I2C_STAT);
- writew (0, I2C_CNT);
+ writew (0xFFFF, &i2c_base->stat);
+ writew (0, &i2c_base->cnt);
return i2c_error;
}
* you get a bus error
*/
while(1){
- stat = readw(I2C_STAT);
+ stat = readw(&i2c_base->stat);
if(stat == I2C_STAT_RRDY){
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
- readb(I2C_DATA);
+ readb(&i2c_base->data);
#else
- readw(I2C_DATA);
+ readw(&i2c_base->data);
#endif
- writew(I2C_STAT_RRDY,I2C_STAT);
+ writew(I2C_STAT_RRDY,&i2c_base->stat);
udelay(1000);
}else
break;
{
int res = 1; /* default = fail */
- if (chip == readw (I2C_OA)) {
+ if (chip == readw (&i2c_base->oa)) {
return res;
}
wait_for_bb ();
/* try to read one byte */
- writew (1, I2C_CNT);
+ writew (1, &i2c_base->cnt);
/* set slave address */
- writew (chip, I2C_SA);
+ writew (chip, &i2c_base->sa);
/* stop bit needed here */
- writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON);
+ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con);
/* enough delay for the NACK bit set */
udelay (50000);
- if (!(readw (I2C_STAT) & I2C_STAT_NACK)) {
+ if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) {
res = 0; /* success case */
flush_fifo();
- writew(0xFFFF, I2C_STAT);
+ writew(0xFFFF, &i2c_base->stat);
} else {
- writew(0xFFFF, I2C_STAT); /* failue, clear sources*/
- writew (readw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */
+ writew(0xFFFF, &i2c_base->stat); /* failue, clear sources*/
+ writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); /* finish up xfer */
udelay(20000);
wait_for_bb ();
}
flush_fifo();
- writew (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/
- writew(0xFFFF, I2C_STAT);
+ writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/
+ writew(0xFFFF, &i2c_base->stat);
return res;
}
int timeout = 10;
u16 stat;
- writew(0xFFFF, I2C_STAT); /* clear current interruts...*/
- while ((stat = readw (I2C_STAT) & I2C_STAT_BB) && timeout--) {
- writew (stat, I2C_STAT);
+ writew(0xFFFF, &i2c_base->stat); /* clear current interruts...*/
+ while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
+ writew (stat, &i2c_base->stat);
udelay (50000);
}
if (timeout <= 0) {
printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
- readw (I2C_STAT));
+ readw (&i2c_base->stat));
}
- writew(0xFFFF, I2C_STAT); /* clear delayed stuff*/
+ writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
}
static u16 wait_for_pin (void)
do {
udelay (1000);
- status = readw (I2C_STAT);
+ status = readw (&i2c_base->stat);
} while ( !(status &
(I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
if (timeout <= 0) {
printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
- readw (I2C_STAT));
- writew(0xFFFF, I2C_STAT);
+ readw (&i2c_base->stat));
+ writew(0xFFFF, &i2c_base->stat);
}
return status;
}
+
+int i2c_set_bus_num(unsigned int bus)
+{
+ if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
+ printf("Bad bus: %d\n", bus);
+ return -1;
+ }
+
+#if I2C_BUS_MAX==3
+ if (bus == 2)
+ i2c_base = (struct i2c *)I2C_BASE3;
+ else
+#endif
+ if (bus == 1)
+ i2c_base = (struct i2c *)I2C_BASE2;
+ else
+ i2c_base = (struct i2c *)I2C_BASE1;
+
+ current_bus = bus;
+
+ if(!bus_initialized[current_bus])
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ return 0;
+}
--- /dev/null
+/*
+ * File: drivers/i2c/pca9564.c
+ * Based on: drivers/i2c/s3c44b0_i2c.c
+ * Author:
+ *
+ * Created: 2009-06-23
+ * Description: PCA9564 i2c bridge driver
+ *
+ * Modified:
+ * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
+ *
+ * Bugs:
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <pca9564.h>
+#include <asm/io.h>
+
+#define PCA_STA (CONFIG_PCA9564_BASE + 0)
+#define PCA_TO (CONFIG_PCA9564_BASE + 0)
+#define PCA_DAT (CONFIG_PCA9564_BASE + (1 << 2))
+#define PCA_ADR (CONFIG_PCA9564_BASE + (2 << 2))
+#define PCA_CON (CONFIG_PCA9564_BASE + (3 << 2))
+
+static unsigned char pca_read_reg(unsigned int reg)
+{
+ return readb((void *)reg);
+}
+
+static void pca_write_reg(unsigned int reg, unsigned char value)
+{
+ writeb(value, (void *)reg);
+}
+
+static int pca_wait_busy(void)
+{
+ unsigned int timeout = 10000;
+
+ while (!(pca_read_reg(PCA_CON) & PCA_CON_SI) && --timeout)
+ udelay(1);
+
+ if (timeout == 0)
+ debug("I2C timeout!\n");
+
+ debug("CON = 0x%02x, STA = 0x%02x\n", pca_read_reg(PCA_CON),
+ pca_read_reg(PCA_STA));
+
+ return timeout ? 0 : 1;
+}
+
+/*=====================================================================*/
+/* Public Functions */
+/*=====================================================================*/
+
+/*-----------------------------------------------------------------------
+ * Initialization
+ */
+void i2c_init(int speed, int slaveaddr)
+{
+ pca_write_reg(PCA_CON, PCA_CON_ENSIO | speed);
+}
+
+/*
+ * Probe the given I2C chip address. Returns 0 if a chip responded,
+ * not 0 on failure.
+ */
+
+int i2c_probe(uchar chip)
+{
+ unsigned char res;
+
+ pca_write_reg(PCA_CON, PCA_CON_STA | PCA_CON_ENSIO);
+ pca_wait_busy();
+
+ pca_write_reg(PCA_CON, PCA_CON_STA | PCA_CON_ENSIO);
+
+ pca_write_reg(PCA_DAT, (chip << 1) | 1);
+ res = pca_wait_busy();
+
+ if ((res == 0) && (pca_read_reg(PCA_STA) == 0x48))
+ res = 1;
+
+ pca_write_reg(PCA_CON, PCA_CON_STO | PCA_CON_ENSIO);
+
+ return res;
+}
+
+/*
+ * Read/Write interface:
+ * chip: I2C chip address, range 0..127
+ * addr: Memory (register) address within the chip
+ * alen: Number of bytes to use for addr (typically 1, 2 for larger
+ * memories, 0 for register type devices with only one
+ * register)
+ * buffer: Where to read/write the data
+ * len: How many bytes to read/write
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+ int i;
+
+ pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA);
+ pca_wait_busy();
+
+ pca_write_reg(PCA_CON, PCA_CON_ENSIO);
+
+ pca_write_reg(PCA_DAT, (chip << 1));
+ pca_wait_busy();
+ pca_write_reg(PCA_CON, PCA_CON_ENSIO);
+
+ if (alen > 0) {
+ pca_write_reg(PCA_DAT, addr);
+ pca_wait_busy();
+ pca_write_reg(PCA_CON, PCA_CON_ENSIO);
+ }
+
+ pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STO);
+
+ udelay(500);
+
+ pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA);
+ pca_wait_busy();
+ pca_write_reg(PCA_CON, PCA_CON_ENSIO);
+
+ pca_write_reg(PCA_DAT, (chip << 1) | 1);
+ pca_wait_busy();
+
+ for (i = 0; i < len; ++i) {
+ if (i == len - 1)
+ pca_write_reg(PCA_CON, PCA_CON_ENSIO);
+ else
+ pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_AA);
+
+ pca_wait_busy();
+ buffer[i] = pca_read_reg(PCA_DAT);
+
+ }
+
+ pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STO);
+
+ return 0;
+}
+
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+ int i;
+
+ pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA);
+ pca_wait_busy();
+ pca_write_reg(PCA_CON, PCA_CON_ENSIO);
+
+ pca_write_reg(PCA_DAT, chip << 1);
+ pca_wait_busy();
+ pca_write_reg(PCA_CON, PCA_CON_ENSIO);
+
+ if (alen > 0) {
+ pca_write_reg(PCA_DAT, addr);
+ pca_wait_busy();
+ pca_write_reg(PCA_CON, PCA_CON_ENSIO);
+ }
+
+ for (i = 0; i < len; ++i) {
+ pca_write_reg(PCA_DAT, buffer[i]);
+ pca_wait_busy();
+ pca_write_reg(PCA_CON, PCA_CON_ENSIO);
+ }
+
+ pca_write_reg(PCA_CON, PCA_CON_STO | PCA_CON_ENSIO);
+
+ return 0;
+}
#include <asm/io.h>
#include <asm/arch/hardware.h>
#endif
+#ifdef CONFIG_AT91SAM9263 /* only valid for AT91SAM9263 */
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#endif
#ifdef CONFIG_IXP425 /* only valid for IXP425 */
#include <asm/arch/ixp425.h>
#endif
#include <twl4030.h>
-#define LEDAON (0x1 << 0)
-#define LEDBON (0x1 << 1)
-#define LEDAPWM (0x1 << 4)
-#define LEDBPWM (0x1 << 5)
-
-void twl4030_led_init(void)
+void twl4030_led_init(unsigned char ledon_mask)
{
- unsigned char byte;
-
- /* enable LED */
- byte = LEDBPWM | LEDAPWM | LEDBON | LEDAON;
+ /* LEDs need to have corresponding PWMs enabled */
+ if (ledon_mask & TWL4030_LED_LEDEN_LEDAON)
+ ledon_mask |= TWL4030_LED_LEDEN_LEDAPWM;
+ if (ledon_mask & TWL4030_LED_LEDEN_LEDBON)
+ ledon_mask |= TWL4030_LED_LEDEN_LEDBPWM;
- twl4030_i2c_write_u8(TWL4030_CHIP_LED, byte,
+ twl4030_i2c_write_u8(TWL4030_CHIP_LED, ledon_mask,
TWL4030_LED_LEDEN);
}
{
t2_t *t2_base = (t2_t *)T2_BASE;
+#if defined(CONFIG_TWL4030_POWER)
twl4030_power_mmc_init();
+#endif
writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE;
+/*
+ * Exploit the little endianness of the ARM to do multi-byte transfers
+ * per device read. This can perform over twice as quickly as individual
+ * byte transfers when buffer alignment is conducive.
+ *
+ * NOTE: This only works if the NAND is not connected to the 2 LSBs of
+ * the address bus. On Davinci EVM platforms this has always been true.
+ */
+static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ struct nand_chip *chip = mtd->priv;
+ const u32 *nand = chip->IO_ADDR_R;
+
+ /* Make sure that buf is 32 bit aligned */
+ if (((int)buf & 0x3) != 0) {
+ if (((int)buf & 0x1) != 0) {
+ if (len) {
+ *buf = readb(nand);
+ buf += 1;
+ len--;
+ }
+ }
+
+ if (((int)buf & 0x3) != 0) {
+ if (len >= 2) {
+ *(u16 *)buf = readw(nand);
+ buf += 2;
+ len -= 2;
+ }
+ }
+ }
+
+ /* copy aligned data */
+ while (len >= 4) {
+ *(u32 *)buf = readl(nand);
+ buf += 4;
+ len -= 4;
+ }
+
+ /* mop up any remaining bytes */
+ if (len) {
+ if (len >= 2) {
+ *(u16 *)buf = readw(nand);
+ buf += 2;
+ len -= 2;
+ }
+
+ if (len)
+ *buf = readb(nand);
+ }
+}
+
+static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
+ int len)
+{
+ struct nand_chip *chip = mtd->priv;
+ const u32 *nand = chip->IO_ADDR_W;
+
+ /* Make sure that buf is 32 bit aligned */
+ if (((int)buf & 0x3) != 0) {
+ if (((int)buf & 0x1) != 0) {
+ if (len) {
+ writeb(*buf, nand);
+ buf += 1;
+ len--;
+ }
+ }
+
+ if (((int)buf & 0x3) != 0) {
+ if (len >= 2) {
+ writew(*(u16 *)buf, nand);
+ buf += 2;
+ len -= 2;
+ }
+ }
+ }
+
+ /* copy aligned data */
+ while (len >= 4) {
+ writel(*(u32 *)buf, nand);
+ buf += 4;
+ len -= 4;
+ }
+
+ /* mop up any remaining bytes */
+ if (len) {
+ if (len >= 2) {
+ writew(*(u16 *)buf, nand);
+ buf += 2;
+ len -= 2;
+ }
+
+ if (len)
+ writeb(*buf, nand);
+ }
+}
+
static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
-
if (ctrl & NAND_CTRL_CHANGE) {
+ IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
+
if ( ctrl & NAND_CLE )
IO_ADDR_W |= MASK_CLE;
if ( ctrl & NAND_ALE )
}
if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
+ writeb(cmd, IO_ADDR_W);
}
#ifdef CONFIG_SYS_NAND_HW_ECC
static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
{
- int dummy;
+ u_int32_t val;
- dummy = emif_regs->NANDF1ECC;
+ (void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2]));
- /* FIXME: only chipselect 0 is supported for now */
- emif_regs->NANDFCR |= 1 << 8;
+ val = readl(&emif_regs->NANDFCR);
+ val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
+ writel(val, &emif_regs->NANDFCR);
}
static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
{
u_int32_t ecc = 0;
- if (region == 1)
- ecc = emif_regs->NANDF1ECC;
- else if (region == 2)
- ecc = emif_regs->NANDF2ECC;
- else if (region == 3)
- ecc = emif_regs->NANDF3ECC;
- else if (region == 4)
- ecc = emif_regs->NANDF4ECC;
+ ecc = readl(&(emif_regs->NANDFECC[region - 1]));
return(ecc);
}
#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
-/*
- * TI uses a different layout for 4K page deviecs. Since the
- * eccpos filed can hold only a limited number of entries, adding
- * support for 4K page will result in compilation warnings
- * 4K Support will be added later
- */
-#ifdef CONFIG_SYS_NAND_PAGE_2K
+#if defined(CONFIG_SYS_NAND_PAGE_2K)
.eccbytes = 40,
.eccpos = {
24, 25, 26, 27, 28,
.oobfree = {
{.offset = 2, .length = 22, },
},
+#elif defined(CONFIG_SYS_NAND_PAGE_4K)
+ .eccbytes = 80,
+ .eccpos = {
+ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
+ 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
+ 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
+ 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
+ 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
+ 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
+ 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
+ 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
+ },
+ .oobfree = {
+ {.offset = 2, .length = 46, },
+ },
#endif
};
* Start a new ECC calculation for reading or writing 512 bytes
* of data.
*/
- val = (emif_regs->NANDFCR & ~(3 << 4)) | (1 << 12);
- emif_regs->NANDFCR = val;
+ val = readl(&emif_regs->NANDFCR);
+ val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
+ val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_4BIT_ECC_START;
+ writel(val, &emif_regs->NANDFCR);
break;
case NAND_ECC_READSYN:
val = emif_regs->NAND4BITECC1;
const uint8_t *dat,
uint8_t *ecc_code)
{
- unsigned int hw_4ecc[4] = { 0, 0, 0, 0 };
- unsigned int const1 = 0, const2 = 0;
- unsigned char count1 = 0;
+ unsigned int hw_4ecc[4];
+ unsigned int i;
nand_davinci_4bit_readecc(mtd, hw_4ecc);
/*Convert 10 bit ecc value to 8 bit */
- for (count1 = 0; count1 < 2; count1++) {
- const2 = count1 * 5;
- const1 = count1 * 2;
+ for (i = 0; i < 2; i++) {
+ unsigned int hw_ecc_low = hw_4ecc[i * 2];
+ unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
/* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
- ecc_code[const2] = hw_4ecc[const1] & 0xFF;
+ *ecc_code++ = hw_ecc_low & 0xFF;
/*
* Take 2 bits as LSB bits from val1 (count1=0) or val5
* (count1=1) and 6 bits from val2 (count1=0) or
* val5 (count1=1)
*/
- ecc_code[const2 + 1] =
- ((hw_4ecc[const1] >> 8) & 0x3) | ((hw_4ecc[const1] >> 14) &
- 0xFC);
+ *ecc_code++ =
+ ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
/*
* Take 4 bits from val2 (count1=0) or val5 (count1=1) and
* 4 bits from val3 (count1=0) or val6 (count1=1)
*/
- ecc_code[const2 + 2] =
- ((hw_4ecc[const1] >> 22) & 0xF) |
- ((hw_4ecc[const1 + 1] << 4) & 0xF0);
+ *ecc_code++ =
+ ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
/*
* Take 6 bits from val3(count1=0) or val6 (count1=1) and
* 2 bits from val4 (count1=0) or val7 (count1=1)
*/
- ecc_code[const2 + 3] =
- ((hw_4ecc[const1 + 1] >> 4) & 0x3F) |
- ((hw_4ecc[const1 + 1] >> 10) & 0xC0);
+ *ecc_code++ =
+ ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
/* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
- ecc_code[const2 + 4] = (hw_4ecc[const1 + 1] >> 18) & 0xFF;
+ *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
}
+
return 0;
}
-
static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
uint8_t *read_ecc, uint8_t *calc_ecc)
{
- unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
int i;
- unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0;
- unsigned short *pspare = NULL, *pspare1 = NULL;
+ unsigned int hw_4ecc[4];
+ unsigned int iserror;
+ unsigned short *ecc16;
unsigned int numerrors, erroraddress, errorvalue;
u32 val;
return 0;
/* Convert 8 bit in to 10 bit */
- pspare = (unsigned short *)&read_ecc[2];
- pspare1 = (unsigned short *)&read_ecc[0];
+ ecc16 = (unsigned short *)&read_ecc[0];
- /* Take 10 bits from 0th and 1st bytes */
- ecc_10bit[0] = (*pspare1) & 0x3FF;
+ /*
+ * Write the parity values in the NAND Flash 4-bit ECC Load register.
+ * Write each parity value one at a time starting from 4bit_ecc_val8
+ * to 4bit_ecc_val1.
+ */
- /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
- ecc_10bit[1] = (((*pspare1) >> 10) & 0x3F)
- | (((pspare[0]) << 6) & 0x3C0);
+ /*Take 2 bits from 8th byte and 8 bits from 9th byte */
+ writel(((ecc16[4]) >> 6) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
- /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
- ecc_10bit[2] = ((pspare[0]) >> 4) & 0x3FF;
+ /* Take 4 bits from 7th byte and 6 bits from 8th byte */
+ writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
+ &emif_regs->NAND4BITECCLOAD);
- /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
- ecc_10bit[3] = (((pspare[0]) >> 14) & 0x3)
- | ((((pspare[1])) << 2) & 0x3FC);
+ /* Take 6 bits from 6th byte and 4 bits from 7th byte */
+ writel((ecc16[3] >> 2) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
/* Take 8 bits from 5th byte and 2 bits from 6th byte */
- ecc_10bit[4] = ((pspare[1]) >> 8)
- | ((((pspare[2])) << 8) & 0x300);
+ writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
+ &emif_regs->NAND4BITECCLOAD);
- /* Take 6 bits from 6th byte and 4 bits from 7th byte */
- ecc_10bit[5] = (pspare[2] >> 2) & 0x3FF;
+ /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
+ writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
+ &emif_regs->NAND4BITECCLOAD);
- /* Take 4 bits from 7th byte and 6 bits from 8th byte */
- ecc_10bit[6] = (((pspare[2]) >> 12) & 0xF)
- | ((((pspare[3])) << 4) & 0x3F0);
+ /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
+ writel(((ecc16[1]) >> 4) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
- /*Take 2 bits from 8th byte and 8 bits from 9th byte */
- ecc_10bit[7] = ((pspare[3]) >> 6) & 0x3FF;
+ /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
+ writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
+ &emif_regs->NAND4BITECCLOAD);
- /*
- * Write the parity values in the NAND Flash 4-bit ECC Load register.
- * Write each parity value one at a time starting from 4bit_ecc_val8
- * to 4bit_ecc_val1.
- */
- for (i = 7; i >= 0; i--)
- emif_regs->NAND4BITECCLOAD = ecc_10bit[i];
+ /* Take 10 bits from 0th and 1st bytes */
+ writel((ecc16[0]) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
/*
* Perform a dummy read to the EMIF Revision Code and Status register.
*/
nand_davinci_4bit_readecc(mtd, hw_4ecc);
- if (hw_4ecc[0] == ECC_STATE_NO_ERR && hw_4ecc[1] == ECC_STATE_NO_ERR &&
- hw_4ecc[2] == ECC_STATE_NO_ERR && hw_4ecc[3] == ECC_STATE_NO_ERR)
+ if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
return 0;
/*
/* Set address of hardware control function */
nand->cmd_ctrl = nand_davinci_hwcontrol;
+ nand->read_buf = nand_davinci_read_buf;
+ nand->write_buf = nand_davinci_write_buf;
+
nand->dev_ready = nand_davinci_dev_ready;
nand_flash_init();
nand->waitfunc = fsl_elbc_wait;
/* set up nand options */
- /* redirect the pointer of bbt pattern to RAM */
- bbt_main_descr.pattern = bbt_pattern;
- bbt_mirror_descr.pattern = mirror_pattern;
nand->bbt_td = &bbt_main_descr;
nand->bbt_md = &bbt_mirror_descr;
/* Large-page-specific setup */
if (or & OR_FCM_PGS) {
priv->page_size = 1;
- largepage_memorybased.pattern = scan_ff_pattern;
nand->badblock_pattern = &largepage_memorybased;
/* adjust ecc setup if needed */
* @mtd: mtd info structure
* @chip: nand chip info structure
* @buf: buffer to store read data
+ * @page: page number to read
+ *
+ * Not for syndrome calculating ecc controllers, which use a special oob layout
*/
static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
uint8_t *buf, int page)
return 0;
}
+/**
+ * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @page: page number to read
+ *
+ * We need a special oob layout and handling even when OOB isn't used.
+ */
+static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int page)
+{
+ int eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ uint8_t *oob = chip->oob_poi;
+ int steps, size;
+
+ for (steps = chip->ecc.steps; steps > 0; steps--) {
+ chip->read_buf(mtd, buf, eccsize);
+ buf += eccsize;
+
+ if (chip->ecc.prepad) {
+ chip->read_buf(mtd, oob, chip->ecc.prepad);
+ oob += chip->ecc.prepad;
+ }
+
+ chip->read_buf(mtd, oob, eccbytes);
+ oob += eccbytes;
+
+ if (chip->ecc.postpad) {
+ chip->read_buf(mtd, oob, chip->ecc.postpad);
+ oob += chip->ecc.postpad;
+ }
+ }
+
+ size = mtd->oobsize - (oob - chip->oob_poi);
+ if (size)
+ chip->read_buf(mtd, oob, size);
+
+ return 0;
+}
+
/**
* nand_read_page_swecc - [REPLACABLE] software ecc based page read function
* @mtd: mtd info structure
* @chip: nand chip info structure
* @buf: buffer to store read data
+ * @page: page number to read
*/
static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
uint8_t *buf, int page)
* nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
* @mtd: mtd info structure
* @chip: nand chip info structure
- * @dataofs offset of requested data within the page
- * @readlen data length
- * @buf: buffer to store read data
+ * @data_offs: offset of requested data within the page
+ * @readlen: data length
+ * @bufpoi: buffer to store read data
*/
static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
{
int stat;
stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
- if (stat < 0)
+ if (stat == -1)
mtd->ecc_stats.failed++;
else
mtd->ecc_stats.corrected += stat;
* @mtd: mtd info structure
* @chip: nand chip info structure
* @buf: buffer to store read data
+ * @page: page number to read
*
* Not for syndrome calculating ecc controllers which need a special oob layout
*/
int stat;
stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
- if (stat == -1)
+ if (stat < 0)
mtd->ecc_stats.failed++;
else
mtd->ecc_stats.corrected += stat;
* @mtd: mtd info structure
* @chip: nand chip info structure
* @buf: buffer to store read data
+ * @page: page number to read
*
* Hardware ECC for large page chips, require OOB to be read first.
* For this ECC mode, the write_page method is re-used from ECC_HW.
* @mtd: mtd info structure
* @chip: nand chip info structure
* @buf: buffer to store read data
+ * @page: page number to read
*
* The hw generator calculates the error syndrome automatically. Therefor
* we need a special oob layout and handling.
* @mtd: mtd info structure
* @chip: nand chip info structure
* @buf: data buffer
+ *
+ * Not for syndrome calculating ecc controllers, which use a special oob layout
*/
static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
const uint8_t *buf)
chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
}
+/**
+ * nand_write_page_raw_syndrome - [Intern] raw page write function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: data buffer
+ *
+ * We need a special oob layout and handling even when ECC isn't checked.
+ */
+static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf)
+{
+ int eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ uint8_t *oob = chip->oob_poi;
+ int steps, size;
+
+ for (steps = chip->ecc.steps; steps > 0; steps--) {
+ chip->write_buf(mtd, buf, eccsize);
+ buf += eccsize;
+
+ if (chip->ecc.prepad) {
+ chip->write_buf(mtd, oob, chip->ecc.prepad);
+ oob += chip->ecc.prepad;
+ }
+
+ chip->read_buf(mtd, oob, eccbytes);
+ oob += eccbytes;
+
+ if (chip->ecc.postpad) {
+ chip->write_buf(mtd, oob, chip->ecc.postpad);
+ oob += chip->ecc.postpad;
+ }
+ }
+
+ size = mtd->oobsize - (oob - chip->oob_poi);
+ if (size)
+ chip->write_buf(mtd, oob, size);
+}
/**
* nand_write_page_swecc - [REPLACABLE] software ecc based page write function
* @mtd: mtd info structure
int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
int allowbbt)
{
- int page, len, status, pages_per_block, ret, chipnr;
+ int page, status, pages_per_block, ret, chipnr;
struct nand_chip *chip = mtd->priv;
- int rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS]={0};
+ loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
unsigned int bbt_masked_page = 0xffffffff;
+ loff_t len;
- MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
- (unsigned int) instr->addr, (unsigned int) instr->len);
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, "
+ "len = %llu\n", (unsigned long long) instr->addr,
+ (unsigned long long) instr->len);
/* Start address must align on block boundary */
if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
"Failed erase, page 0x%08x\n", page);
instr->state = MTD_ERASE_FAILED;
- instr->fail_addr = (page << chip->page_shift);
+ instr->fail_addr = ((loff_t)page << chip->page_shift);
goto erase_exit;
}
*/
if (bbt_masked_page != 0xffffffff &&
(page & BBT_PAGE_MASK) == bbt_masked_page)
- rewrite_bbt[chipnr] = (page << chip->page_shift);
+ rewrite_bbt[chipnr] =
+ ((loff_t)page << chip->page_shift);
/* Increment page address and decrement length */
len -= (1 << chip->phys_erase_shift);
continue;
/* update the BBT for chip */
MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
- "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
- chip->bbt_td->pages[chipnr]);
+ "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
+ chip->bbt_td->pages[chipnr]);
nand_update_bbt(mtd, rewrite_bbt[chipnr]);
}
if (!mtd->name)
mtd->name = type->name;
- chip->chipsize = type->chipsize << 20;
+ chip->chipsize = (uint64_t)type->chipsize << 20;
/* Newer devices have all the information in additional id bytes */
if (!type->pagesize) {
chip->bbt_erase_shift = chip->phys_erase_shift =
ffs(mtd->erasesize) - 1;
- chip->chip_shift = ffs(chip->chipsize) - 1;
+ if (chip->chipsize & 0xffffffff)
+ chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
+ else
+ chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31;
/* Set the bad block position */
chip->badblockpos = mtd->writesize > 512 ?
/**
* nand_scan_tail - [NAND Interface] Scan for the NAND device
* @mtd: MTD device structure
- * @maxchips: Number of chips to scan for
*
* This is the second phase of the normal nand_scan() function. It
* fills out all the uninitialized function pointers with the defaults
default:
printk(KERN_WARNING "No oob scheme defined for "
"oobsize %d\n", mtd->oobsize);
-/* BUG(); */
}
}
* check ECC mode, default to software if 3byte/512byte hardware ECC is
* selected and we have 256 byte pagesize fallback to software ECC
*/
- if (!chip->ecc.read_page_raw)
- chip->ecc.read_page_raw = nand_read_page_raw;
- if (!chip->ecc.write_page_raw)
- chip->ecc.write_page_raw = nand_write_page_raw;
switch (chip->ecc.mode) {
case NAND_ECC_HW_OOB_FIRST:
chip->ecc.read_page = nand_read_page_hwecc;
if (!chip->ecc.write_page)
chip->ecc.write_page = nand_write_page_hwecc;
+ if (!chip->ecc.read_page_raw)
+ chip->ecc.read_page_raw = nand_read_page_raw;
+ if (!chip->ecc.write_page_raw)
+ chip->ecc.write_page_raw = nand_write_page_raw;
if (!chip->ecc.read_oob)
chip->ecc.read_oob = nand_read_oob_std;
if (!chip->ecc.write_oob)
chip->ecc.read_page = nand_read_page_syndrome;
if (!chip->ecc.write_page)
chip->ecc.write_page = nand_write_page_syndrome;
+ if (!chip->ecc.read_page_raw)
+ chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
+ if (!chip->ecc.write_page_raw)
+ chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
if (!chip->ecc.read_oob)
chip->ecc.read_oob = nand_read_oob_syndrome;
if (!chip->ecc.write_oob)
chip->ecc.read_page = nand_read_page_swecc;
chip->ecc.read_subpage = nand_read_subpage;
chip->ecc.write_page = nand_write_page_swecc;
+ chip->ecc.read_page_raw = nand_read_page_raw;
+ chip->ecc.write_page_raw = nand_write_page_raw;
chip->ecc.read_oob = nand_read_oob_std;
chip->ecc.write_oob = nand_write_oob_std;
chip->ecc.size = 256;
chip->ecc.read_page = nand_read_page_raw;
chip->ecc.write_page = nand_write_page_raw;
chip->ecc.read_oob = nand_read_oob_std;
+ chip->ecc.read_page_raw = nand_read_page_raw;
+ chip->ecc.write_page_raw = nand_write_page_raw;
chip->ecc.write_oob = nand_write_oob_std;
chip->ecc.size = mtd->writesize;
chip->ecc.bytes = 0;
* the out of band area
*/
chip->ecc.layout->oobavail = 0;
- for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
+ for (i = 0; chip->ecc.layout->oobfree[i].length
+ && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
chip->ecc.layout->oobavail +=
chip->ecc.layout->oobfree[i].length;
mtd->oobavail = chip->ecc.layout->oobavail;
break;
case 4:
case 8:
+ case 16:
mtd->subpage_sft = 2;
break;
}
if (tmp == msk)
continue;
if (reserved_block_code && (tmp == reserved_block_code)) {
- printk(KERN_DEBUG "nand_read_bbt: Reserved block at 0x%08x\n",
- ((offs << 2) + (act >> 1)) << this->bbt_erase_shift);
+ printk(KERN_DEBUG "nand_read_bbt: Reserved block at 0x%012llx\n",
+ (loff_t)((offs << 2) +
+ (act >> 1)) <<
+ this->bbt_erase_shift);
this->bbt[offs + (act >> 3)] |= 0x2 << (act & 0x06);
mtd->ecc_stats.bbtblocks++;
continue;
}
/* Leave it for now, if its matured we can move this
* message to MTD_DEBUG_LEVEL0 */
- printk(KERN_DEBUG "nand_read_bbt: Bad block at 0x%08x\n",
- ((offs << 2) + (act >> 1)) << this->bbt_erase_shift);
+ printk(KERN_DEBUG "nand_read_bbt: Bad block at 0x%012llx\n",
+ (loff_t)((offs << 2) + (act >> 1)) <<
+ this->bbt_erase_shift);
/* Factory marked bad or worn out ? */
if (tmp == 0)
this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06);
/* Read the primary version, if available */
if (td->options & NAND_BBT_VERSION) {
- scan_read_raw(mtd, buf, td->pages[0] << this->page_shift,
- mtd->writesize);
+ scan_read_raw(mtd, buf, (loff_t)td->pages[0] <<
+ this->page_shift, mtd->writesize);
td->version[0] = buf[mtd->writesize + td->veroffs];
printk(KERN_DEBUG "Bad block table at page %d, version 0x%02X\n",
td->pages[0], td->version[0]);
/* Read the mirror version, if available */
if (md && (md->options & NAND_BBT_VERSION)) {
- scan_read_raw(mtd, buf, md->pages[0] << this->page_shift,
- mtd->writesize);
+ scan_read_raw(mtd, buf, (loff_t)md->pages[0] <<
+ this->page_shift, mtd->writesize);
md->version[0] = buf[mtd->writesize + md->veroffs];
printk(KERN_DEBUG "Bad block table at page %d, version 0x%02X\n",
md->pages[0], md->version[0]);
numblocks = this->chipsize >> (this->bbt_erase_shift - 1);
startblock = chip * numblocks;
numblocks += startblock;
- from = startblock << (this->bbt_erase_shift - 1);
+ from = (loff_t)startblock << (this->bbt_erase_shift - 1);
}
for (i = startblock; i < numblocks;) {
if (ret) {
this->bbt[i >> 3] |= 0x03 << (i & 0x6);
MTDDEBUG (MTD_DEBUG_LEVEL0,
- "Bad eraseblock %d at 0x%08x\n",
- i >> 1, (unsigned int)from);
+ "Bad eraseblock %d at 0x%012llx\n",
+ i >> 1, (unsigned long long)from);
mtd->ecc_stats.badblocks++;
}
for (block = 0; block < td->maxblocks; block++) {
int actblock = startblock + dir * block;
- loff_t offs = actblock << this->bbt_erase_shift;
+ loff_t offs = (loff_t)actblock << this->bbt_erase_shift;
/* Read first page */
scan_read_raw(mtd, buf, offs, mtd->writesize);
memset(&einfo, 0, sizeof(einfo));
einfo.mtd = mtd;
- einfo.addr = (unsigned long)to;
+ einfo.addr = to;
einfo.len = 1 << this->bbt_erase_shift;
res = nand_erase_nand(mtd, &einfo, 1);
if (res < 0)
if (res < 0)
goto outerr;
- printk(KERN_DEBUG "Bad block table written to 0x%08x, version "
- "0x%02X\n", (unsigned int)to, td->version[chip]);
+ printk(KERN_DEBUG "Bad block table written to 0x%012llx, "
+ "version 0x%02X\n", (unsigned long long)to,
+ td->version[chip]);
/* Mark it as used */
td->pages[chip] = page;
newval = oldval | (0x2 << (block & 0x06));
this->bbt[(block >> 3)] = newval;
if ((oldval != newval) && td->reserved_block_code)
- nand_update_bbt(mtd, block << (this->bbt_erase_shift - 1));
+ nand_update_bbt(mtd, (loff_t)block <<
+ (this->bbt_erase_shift - 1));
continue;
}
update = 0;
new ones have been marked, then we need to update the stored
bbts. This should only happen once. */
if (update && td->reserved_block_code)
- nand_update_bbt(mtd, (block - 2) << (this->bbt_erase_shift - 1));
+ nand_update_bbt(mtd, (loff_t)(block - 2) <<
+ (this->bbt_erase_shift - 1));
}
}
if (!this->bbt || !td)
return -EINVAL;
- len = mtd->size >> (this->bbt_erase_shift + 2);
/* Allocate a temporary buffer for one eraseblock incl. oob */
len = (1 << this->bbt_erase_shift);
len += (len >> this->page_shift) * mtd->oobsize;
#include <nand.h>
#include <jffs2/jffs2.h>
-#if !defined(CONFIG_SYS_64BIT_VSPRINTF)
-#warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output!
-#endif
-
typedef struct erase_info erase_info_t;
typedef struct mtd_info mtd_info_t;
len_incl_bad += block_len;
offset += block_len;
- if ((offset + len_incl_bad) >= nand->size)
+ if (offset >= nand->size)
break;
}
len_incl_bad = get_len_incl_bad (nand, offset, *length);
- if ((offset + len_incl_bad) >= nand->size) {
+ if ((offset + len_incl_bad) > nand->size) {
printf ("Attempt to write outside the flash area\n");
return -EINVAL;
}
len_incl_bad = get_len_incl_bad (nand, offset, *length);
- if ((offset + len_incl_bad) >= nand->size) {
+ if ((offset + len_incl_bad) > nand->size) {
printf ("Attempt to read outside the flash area\n");
return -EINVAL;
}
#define S3C2410_ADDR_NALE 4
#define S3C2410_ADDR_NCLE 8
+#ifdef CONFIG_NAND_SPL
+
+/* in the early stage of NAND flash booting, printf() is not available */
+#define printf(fmt, args...)
+
+static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ int i;
+ struct nand_chip *this = mtd->priv;
+
+ for (i = 0; i < len; i++)
+ buf[i] = readb(this->IO_ADDR_R);
+}
+#endif
+
static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *chip = mtd->priv;
static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{
- ecc_code[0] = NFECC0;
- ecc_code[1] = NFECC1;
- ecc_code[2] = NFECC2;
+ struct s3c2410_nand *nand = s3c2410_get_base_nand();
+ ecc_code[0] = readb(&nand->NFECC);
+ ecc_code[1] = readb(&nand->NFECC + 1);
+ ecc_code[2] = readb(&nand->NFECC + 2);
debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
/* initialize nand_chip data structure */
nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA;
+ nand->select_chip = NULL;
+
/* read_buf and write_buf are default */
/* read_byte and write_byte are default */
+#ifdef CONFIG_NAND_SPL
+ nand->read_buf = nand_read_buf;
+#endif
/* hwcontrol always must be implemented */
nand->cmd_ctrl = s3c2410_hwcontrol;
nand->ecc.hwctl = s3c2410_nand_enable_hwecc;
nand->ecc.calculate = s3c2410_nand_calculate_ecc;
nand->ecc.correct = s3c2410_nand_correct_data;
- nand->ecc.mode = NAND_ECC_HW3_512;
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
+ nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
#else
nand->ecc.mode = NAND_ECC_SOFT;
#endif
* auto-placement support, read-while load support, various fixes
* Copyright (C) Nokia Corporation, 2007
*
+ * Rohit Hagargundgi <h.rohit at samsung.com>,
+ * Amul Kumar Saha <amul.saha@samsung.com>:
+ * Flex-OneNAND support
+ * Copyright (C) Samsung Electronics, 2009
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
#include <malloc.h>
/* It should access 16-bit instead of 8-bit */
-static inline void *memcpy_16(void *dst, const void *src, unsigned int len)
+static void *memcpy_16(void *dst, const void *src, unsigned int len)
{
void *ret = dst;
short *d = dst;
return ret;
}
+/**
+ * onenand_oob_128 - oob info for Flex-Onenand with 4KB page
+ * For now, we expose only 64 out of 80 ecc bytes
+ */
+static struct nand_ecclayout onenand_oob_128 = {
+ .eccbytes = 64,
+ .eccpos = {
+ 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
+ 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
+ 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
+ 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
+ 102, 103, 104, 105
+ },
+ .oobfree = {
+ {2, 4}, {18, 4}, {34, 4}, {50, 4},
+ {66, 4}, {82, 4}, {98, 4}, {114, 4}
+ }
+};
+
/**
* onenand_oob_64 - oob info for large (2KB) page
*/
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 80 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 96 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 112 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 128 */
};
/**
return ((bsa << ONENAND_BSA_SHIFT) | bsc);
}
+/**
+ * flexonenand_block - Return block number for flash address
+ * @param this - OneNAND device structure
+ * @param addr - Address for which block number is needed
+ */
+static unsigned int flexonenand_block(struct onenand_chip *this, loff_t addr)
+{
+ unsigned int boundary, blk, die = 0;
+
+ if (ONENAND_IS_DDP(this) && addr >= this->diesize[0]) {
+ die = 1;
+ addr -= this->diesize[0];
+ }
+
+ boundary = this->boundary[die];
+
+ blk = addr >> (this->erase_shift - 1);
+ if (blk > boundary)
+ blk = (blk + boundary + 1) >> 1;
+
+ blk += die ? this->density_mask : 0;
+ return blk;
+}
+
+unsigned int onenand_block(struct onenand_chip *this, loff_t addr)
+{
+ if (!FLEXONENAND(this))
+ return addr >> this->erase_shift;
+ return flexonenand_block(this, addr);
+}
+
+/**
+ * flexonenand_addr - Return address of the block
+ * @this: OneNAND device structure
+ * @block: Block number on Flex-OneNAND
+ *
+ * Return address of the block
+ */
+static loff_t flexonenand_addr(struct onenand_chip *this, int block)
+{
+ loff_t ofs = 0;
+ int die = 0, boundary;
+
+ if (ONENAND_IS_DDP(this) && block >= this->density_mask) {
+ block -= this->density_mask;
+ die = 1;
+ ofs = this->diesize[0];
+ }
+
+ boundary = this->boundary[die];
+ ofs += (loff_t) block << (this->erase_shift - 1);
+ if (block > (boundary + 1))
+ ofs += (loff_t) (block - boundary - 1)
+ << (this->erase_shift - 1);
+ return ofs;
+}
+
+loff_t onenand_addr(struct onenand_chip *this, int block)
+{
+ if (!FLEXONENAND(this))
+ return (loff_t) block << this->erase_shift;
+ return flexonenand_addr(this, block);
+}
+
+/**
+ * flexonenand_region - [Flex-OneNAND] Return erase region of addr
+ * @param mtd MTD device structure
+ * @param addr address whose erase region needs to be identified
+ */
+int flexonenand_region(struct mtd_info *mtd, loff_t addr)
+{
+ int i;
+
+ for (i = 0; i < mtd->numeraseregions; i++)
+ if (addr < mtd->eraseregions[i].offset)
+ break;
+ return i - 1;
+}
+
/**
* onenand_get_density - [DEFAULT] Get OneNAND density
* @param dev_id OneNAND device ID
size_t len)
{
struct onenand_chip *this = mtd->priv;
- int value, readcmd = 0;
+ int value;
int block, page;
+
/* Now we use page size operation */
- int sectors = 4, count = 4;
+ int sectors = 0, count = 0;
/* Address translation */
switch (cmd) {
page = -1;
break;
+ case FLEXONENAND_CMD_PI_ACCESS:
+ /* addr contains die index */
+ block = addr * this->density_mask;
+ page = -1;
+ break;
+
case ONENAND_CMD_ERASE:
case ONENAND_CMD_BUFFERRAM:
- block = (int)(addr >> this->erase_shift);
+ block = onenand_block(this, addr);
page = -1;
break;
+ case FLEXONENAND_CMD_READ_PI:
+ cmd = ONENAND_CMD_READ;
+ block = addr * this->density_mask;
+ page = 0;
+ break;
+
default:
- block = (int)(addr >> this->erase_shift);
- page = (int)(addr >> this->page_shift);
+ block = onenand_block(this, addr);
+ page = (int) (addr
+ - onenand_addr(this, block)) >> this->page_shift;
page &= this->page_mask;
break;
}
this->write_word(value,
this->base + ONENAND_REG_START_ADDRESS2);
- /* Switch to the next data buffer */
- ONENAND_SET_NEXT_BUFFERRAM(this);
+ if (ONENAND_IS_MLC(this))
+ ONENAND_SET_BUFFERRAM0(this);
+ else
+ /* Switch to the next data buffer */
+ ONENAND_SET_NEXT_BUFFERRAM(this);
return 0;
}
this->write_word(value,
this->base + ONENAND_REG_START_ADDRESS1);
- /* Write 'DFS, FBA' of Flash */
+ /* Select DataRAM for DDP */
value = onenand_bufferram_address(this, block);
this->write_word(value,
this->base + ONENAND_REG_START_ADDRESS2);
int dataram;
switch (cmd) {
+ case FLEXONENAND_CMD_RECOVER_LSB:
case ONENAND_CMD_READ:
case ONENAND_CMD_READOOB:
- dataram = ONENAND_SET_NEXT_BUFFERRAM(this);
- readcmd = 1;
+ if (ONENAND_IS_MLC(this))
+ dataram = ONENAND_SET_BUFFERRAM0(this);
+ else
+ dataram = ONENAND_SET_NEXT_BUFFERRAM(this);
+
break;
default:
return 0;
}
+/**
+ * onenand_read_ecc - return ecc status
+ * @param this onenand chip structure
+ */
+static int onenand_read_ecc(struct onenand_chip *this)
+{
+ int ecc, i;
+
+ if (!FLEXONENAND(this))
+ return this->read_word(this->base + ONENAND_REG_ECC_STATUS);
+
+ for (i = 0; i < 4; i++) {
+ ecc = this->read_word(this->base
+ + ((ONENAND_REG_ECC_STATUS + i) << 1));
+ if (likely(!ecc))
+ continue;
+ if (ecc & FLEXONENAND_UNCORRECTABLE_ERROR)
+ return ONENAND_ECC_2BIT_ALL;
+ }
+
+ return 0;
+}
+
/**
* onenand_wait - [DEFAULT] wait until the command is done
* @param mtd MTD device structure
struct onenand_chip *this = mtd->priv;
unsigned int flags = ONENAND_INT_MASTER;
unsigned int interrupt = 0;
- unsigned int ctrl, ecc;
+ unsigned int ctrl;
while (1) {
interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
+ if (interrupt & ONENAND_INT_READ) {
+ int ecc = onenand_read_ecc(this);
+ if (ecc & ONENAND_ECC_2BIT_ALL) {
+ printk("onenand_wait: ECC error = 0x%04x\n", ecc);
+ return -EBADMSG;
+ }
+ }
+
if (ctrl & ONENAND_CTRL_ERROR) {
printk("onenand_wait: controller error = 0x%04x\n", ctrl);
if (ctrl & ONENAND_CTRL_LOCK)
return -EIO;
}
- if (interrupt & ONENAND_INT_READ) {
- ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS);
- if (ecc & ONENAND_ECC_2BIT_ALL) {
- MTDDEBUG (MTD_DEBUG_LEVEL0,
- "onenand_wait: ECC error = 0x%04x\n", ecc);
- return -EBADMSG;
- }
- }
return 0;
}
if (found && ONENAND_IS_DDP(this)) {
/* Select DataRAM for DDP */
- int block = (int) (addr >> this->erase_shift);
+ int block = onenand_block(this, addr);
int value = onenand_bufferram_address(this, block);
this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
}
return 0;
}
+/**
+ * onenand_recover_lsb - [Flex-OneNAND] Recover LSB page data
+ * @param mtd MTD device structure
+ * @param addr address to recover
+ * @param status return value from onenand_wait
+ *
+ * MLC NAND Flash cell has paired pages - LSB page and MSB page. LSB page has
+ * lower page address and MSB page has higher page address in paired pages.
+ * If power off occurs during MSB page program, the paired LSB page data can
+ * become corrupt. LSB page recovery read is a way to read LSB page though page
+ * data are corrupted. When uncorrectable error occurs as a result of LSB page
+ * read after power up, issue LSB page recovery read.
+ */
+static int onenand_recover_lsb(struct mtd_info *mtd, loff_t addr, int status)
+{
+ struct onenand_chip *this = mtd->priv;
+ int i;
+
+ /* Recovery is only for Flex-OneNAND */
+ if (!FLEXONENAND(this))
+ return status;
+
+ /* check if we failed due to uncorrectable error */
+ if (status != -EBADMSG && status != ONENAND_BBT_READ_ECC_ERROR)
+ return status;
+
+ /* check if address lies in MLC region */
+ i = flexonenand_region(mtd, addr);
+ if (mtd->eraseregions[i].erasesize < (1 << this->erase_shift))
+ return status;
+
+ printk("onenand_recover_lsb:"
+ "Attempting to recover from uncorrectable read\n");
+
+ /* Issue the LSB page recovery command */
+ this->command(mtd, FLEXONENAND_CMD_RECOVER_LSB, addr, this->writesize);
+ return this->wait(mtd, FL_READING);
+}
+
/**
* onenand_read_ops_nolock - [OneNAND Interface] OneNAND read main and/or out-of-band
* @param mtd MTD device structure
stats = mtd->ecc_stats;
/* Read-while-load method */
+ /* Note: We can't use this feature in MLC */
/* Do first load to bufferRAM */
if (read < len) {
this->main_buf = buf;
this->command(mtd, ONENAND_CMD_READ, from, writesize);
ret = this->wait(mtd, FL_READING);
+ if (unlikely(ret))
+ ret = onenand_recover_lsb(mtd, from, ret);
onenand_update_bufferram(mtd, from, !ret);
if (ret == -EBADMSG)
ret = 0;
while (!ret) {
/* If there is more to load then start next load */
from += thislen;
- if (read + thislen < len) {
+ if (!ONENAND_IS_MLC(this) && read + thislen < len) {
this->main_buf = buf + thislen;
this->command(mtd, ONENAND_CMD_READ, from, writesize);
/*
oobcolumn = 0;
}
+ if (ONENAND_IS_MLC(this) && (read + thislen < len)) {
+ this->command(mtd, ONENAND_CMD_READ, from, writesize);
+ ret = this->wait(mtd, FL_READING);
+ if (unlikely(ret))
+ ret = onenand_recover_lsb(mtd, from, ret);
+ onenand_update_bufferram(mtd, from, !ret);
+ if (ret == -EBADMSG)
+ ret = 0;
+ }
+
/* See if we are done */
read += thislen;
if (read == len)
/* Set up for next read from bufferRAM */
if (unlikely(boundary))
this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2);
- ONENAND_SET_NEXT_BUFFERRAM(this);
+ if (!ONENAND_IS_MLC(this))
+ ONENAND_SET_NEXT_BUFFERRAM(this);
buf += thislen;
thislen = min_t(int, writesize, len - read);
column = 0;
- /* Now wait for load */
- ret = this->wait(mtd, FL_READING);
- onenand_update_bufferram(mtd, from, !ret);
- if (ret == -EBADMSG)
- ret = 0;
+ if (!ONENAND_IS_MLC(this)) {
+ /* Now wait for load */
+ ret = this->wait(mtd, FL_READING);
+ onenand_update_bufferram(mtd, from, !ret);
+ if (ret == -EBADMSG)
+ ret = 0;
+ }
}
/*
size_t len = ops->ooblen;
mtd_oob_mode_t mode = ops->mode;
u_char *buf = ops->oobbuf;
- int ret = 0;
+ int ret = 0, readcmd;
from += ops->ooboffs;
stats = mtd->ecc_stats;
+ readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB;
+
while (read < len) {
thislen = oobsize - column;
thislen = min_t(int, thislen, len);
this->spare_buf = buf;
- this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize);
+ this->command(mtd, readcmd, from, mtd->oobsize);
onenand_update_bufferram(mtd, from, 0);
ret = this->wait(mtd, FL_READING);
+ if (unlikely(ret))
+ ret = onenand_recover_lsb(mtd, from, ret);
+
if (ret && ret != -EBADMSG) {
printk(KERN_ERR "onenand_read_oob_nolock: read failed = 0x%x\n", ret);
break;
ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
if (interrupt & ONENAND_INT_READ) {
- int ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS);
- if (ecc & ONENAND_ECC_2BIT_ALL)
+ int ecc = onenand_read_ecc(this);
+ if (ecc & ONENAND_ECC_2BIT_ALL) {
+ printk(KERN_INFO "onenand_bbt_wait: ecc error = 0x%04x"
+ ", controller = 0x%04x\n", ecc, ctrl);
return ONENAND_BBT_READ_ERROR;
+ }
} else {
printk(KERN_ERR "onenand_bbt_wait: read timeout!"
"ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt);
{
struct onenand_chip *this = mtd->priv;
int read = 0, thislen, column;
- int ret = 0;
+ int ret = 0, readcmd;
size_t len = ops->ooblen;
u_char *buf = ops->oobbuf;
MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_bbt_read_oob: from = 0x%08x, len = %zi\n", (unsigned int) from, len);
+ readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB;
+
/* Initialize return value */
ops->oobretlen = 0;
thislen = min_t(int, thislen, len);
this->spare_buf = buf;
- this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize);
+ this->command(mtd, readcmd, from, mtd->oobsize);
onenand_update_bufferram(mtd, from, 0);
ret = this->bbt_wait(mtd, FL_READING);
+ if (unlikely(ret))
+ ret = onenand_recover_lsb(mtd, from, ret);
+
if (ret)
break;
{
struct onenand_chip *this = mtd->priv;
u_char *oob_buf = this->oob_buf;
- int status, i;
+ int status, i, readcmd;
- this->command(mtd, ONENAND_CMD_READOOB, to, mtd->oobsize);
+ readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB;
+
+ this->command(mtd, readcmd, to, mtd->oobsize);
onenand_update_bufferram(mtd, to, 0);
status = this->wait(mtd, FL_READING);
if (status)
{
struct onenand_chip *this = mtd->priv;
int column, ret = 0, oobsize;
- int written = 0;
+ int written = 0, oobcmd;
u_char *oobbuf;
size_t len = ops->ooblen;
const u_char *buf = ops->oobbuf;
oobbuf = this->oob_buf;
+ oobcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_PROG : ONENAND_CMD_PROGOOB;
+
/* Loop until all data write */
while (written < len) {
int thislen = min_t(int, oobsize, len - written);
memcpy(oobbuf + column, buf, thislen);
this->write_bufferram(mtd, 0, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize);
- this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize);
+ if (ONENAND_IS_MLC(this)) {
+ /* Set main area of DataRAM to 0xff*/
+ memset(this->page_buf, 0xff, mtd->writesize);
+ this->write_bufferram(mtd, 0, ONENAND_DATARAM,
+ this->page_buf, 0, mtd->writesize);
+ }
+
+ this->command(mtd, oobcmd, to, mtd->oobsize);
onenand_update_bufferram(mtd, to, 0);
if (ONENAND_IS_2PLANE(this)) {
{
struct onenand_chip *this = mtd->priv;
unsigned int block_size;
- loff_t addr;
- int len;
- int ret = 0;
-
- MTDDEBUG (MTD_DEBUG_LEVEL3,
- "onenand_erase: start = 0x%08x, len = %i\n",
- (unsigned int)instr->addr, (unsigned int)instr->len);
+ loff_t addr = instr->addr;
+ unsigned int len = instr->len;
+ int ret = 0, i;
+ struct mtd_erase_region_info *region = NULL;
+ unsigned int region_end = 0;
- block_size = (1 << this->erase_shift);
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n",
+ (unsigned int) addr, len);
- /* Start address must align on block boundary */
- if (unlikely(instr->addr & (block_size - 1))) {
- MTDDEBUG (MTD_DEBUG_LEVEL0,
- "onenand_erase: Unaligned address\n");
+ /* Do not allow erase past end of device */
+ if (unlikely((len + addr) > mtd->size)) {
+ MTDDEBUG(MTD_DEBUG_LEVEL0, "onenand_erase:"
+ "Erase past end of device\n");
return -EINVAL;
}
- /* Length must align on block boundary */
- if (unlikely(instr->len & (block_size - 1))) {
- MTDDEBUG (MTD_DEBUG_LEVEL0,
- "onenand_erase: Length not block aligned\n");
- return -EINVAL;
+ if (FLEXONENAND(this)) {
+ /* Find the eraseregion of this address */
+ i = flexonenand_region(mtd, addr);
+ region = &mtd->eraseregions[i];
+
+ block_size = region->erasesize;
+ region_end = region->offset
+ + region->erasesize * region->numblocks;
+
+ /* Start address within region must align on block boundary.
+ * Erase region's start offset is always block start address.
+ */
+ if (unlikely((addr - region->offset) & (block_size - 1))) {
+ MTDDEBUG(MTD_DEBUG_LEVEL0, "onenand_erase:"
+ " Unaligned address\n");
+ return -EINVAL;
+ }
+ } else {
+ block_size = 1 << this->erase_shift;
+
+ /* Start address must align on block boundary */
+ if (unlikely(addr & (block_size - 1))) {
+ MTDDEBUG(MTD_DEBUG_LEVEL0, "onenand_erase:"
+ "Unaligned address\n");
+ return -EINVAL;
+ }
}
- /* Do not allow erase past end of device */
- if (unlikely((instr->len + instr->addr) > mtd->size)) {
+ /* Length must align on block boundary */
+ if (unlikely(len & (block_size - 1))) {
MTDDEBUG (MTD_DEBUG_LEVEL0,
- "onenand_erase: Erase past end of device\n");
+ "onenand_erase: Length not block aligned\n");
return -EINVAL;
}
onenand_get_device(mtd, FL_ERASING);
/* Loop throught the pages */
- len = instr->len;
- addr = instr->addr;
-
instr->state = MTD_ERASING;
while (len) {
else
MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_erase: "
"Failed erase, block %d\n",
- (unsigned)(addr >> this->erase_shift));
- if (ret == -EPERM)
- printk("onenand_erase: "
- "Device is write protected!!!\n");
- else
- printk("onenand_erase: "
- "Failed erase, block %d\n",
- (unsigned)(addr >> this->erase_shift));
+ onenand_block(this, addr));
instr->state = MTD_ERASE_FAILED;
instr->fail_addr = addr;
len -= block_size;
addr += block_size;
+
+ if (addr == region_end) {
+ if (!len)
+ break;
+ region++;
+
+ block_size = region->erasesize;
+ region_end = region->offset
+ + region->erasesize * region->numblocks;
+
+ if (len & (block_size - 1)) {
+ /* This has been checked at MTD
+ * partitioning level. */
+ printk("onenand_erase: Unaligned address\n");
+ goto erase_exit;
+ }
+ }
}
instr->state = MTD_ERASE_DONE;
int block;
/* Get block number */
- block = ((int) ofs) >> bbm->bbt_erase_shift;
+ block = onenand_block(this, ofs);
if (bbm->bbt)
bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
int start, end, block, value, status;
int wp_status_mask;
- start = ofs >> this->erase_shift;
- end = len >> this->erase_shift;
+ start = onenand_block(this, ofs);
+ end = onenand_block(this, ofs + len);
if (cmd == ONENAND_CMD_LOCK)
wp_status_mask = ONENAND_WP_LS;
}
/* Block lock scheme */
- for (block = start; block < start + end; block++) {
+ for (block = start; block < end; block++) {
/* Set block address */
value = onenand_block_address(this, block);
this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
{
struct onenand_chip *this = mtd->priv;
loff_t ofs = 0;
- size_t len = this->chipsize;
+ size_t len = mtd->size;
if (this->options & ONENAND_HAS_UNLOCK_ALL) {
/* Set start block address */
& ONENAND_CTRL_ONGO)
continue;
- return;
-
/* Check lock status */
if (onenand_check_lock_status(this))
return;
/* Workaround for all block unlock in DDP */
- if (ONENAND_IS_DDP(this)) {
+ if (ONENAND_IS_DDP(this) && !FLEXONENAND(this)) {
/* All blocks on another chip */
ofs = this->chipsize >> 1;
len = this->chipsize >> 1;
break;
}
+ if (ONENAND_IS_MLC(this))
+ this->options &= ~ONENAND_HAS_2PLANE;
+
+ if (FLEXONENAND(this)) {
+ this->options &= ~ONENAND_HAS_CONT_LOCK;
+ this->options |= ONENAND_HAS_UNLOCK_ALL;
+ }
+
if (this->options & ONENAND_HAS_CONT_LOCK)
printk(KERN_DEBUG "Lock scheme is Continuous Lock\n");
if (this->options & ONENAND_HAS_UNLOCK_ALL)
*/
char *onenand_print_device_info(int device, int version)
{
- int vcc, demuxed, ddp, density;
+ int vcc, demuxed, ddp, density, flexonenand;
char *dev_info = malloc(80);
char *p = dev_info;
vcc = device & ONENAND_DEVICE_VCC_MASK;
demuxed = device & ONENAND_DEVICE_IS_DEMUX;
ddp = device & ONENAND_DEVICE_IS_DDP;
- density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
- p += sprintf(dev_info, "%sOneNAND%s %dMB %sV 16-bit (0x%02x)",
+ density = onenand_get_density(device);
+ flexonenand = device & DEVICE_IS_FLEXONENAND;
+ p += sprintf(dev_info, "%s%sOneNAND%s %dMB %sV 16-bit (0x%02x)",
demuxed ? "" : "Muxed ",
+ flexonenand ? "Flex-" : "",
ddp ? "(DDP)" : "",
(16 << density), vcc ? "2.65/3.3" : "1.8", device);
char *name;
int i;
- for (i = 0; size; i++)
+ for (i = 0; i < size; i++)
if (manuf == onenand_manuf_ids[i].id)
break;
return i == size;
}
+/**
+* flexonenand_get_boundary - Reads the SLC boundary
+* @param onenand_info - onenand info structure
+*
+* Fill up boundary[] field in onenand_chip
+**/
+static int flexonenand_get_boundary(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+ unsigned int die, bdry;
+ int ret, syscfg, locked;
+
+ /* Disable ECC */
+ syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1);
+ this->write_word((syscfg | 0x0100), this->base + ONENAND_REG_SYS_CFG1);
+
+ for (die = 0; die < this->dies; die++) {
+ this->command(mtd, FLEXONENAND_CMD_PI_ACCESS, die, 0);
+ this->wait(mtd, FL_SYNCING);
+
+ this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0);
+ ret = this->wait(mtd, FL_READING);
+
+ bdry = this->read_word(this->base + ONENAND_DATARAM);
+ if ((bdry >> FLEXONENAND_PI_UNLOCK_SHIFT) == 3)
+ locked = 0;
+ else
+ locked = 1;
+ this->boundary[die] = bdry & FLEXONENAND_PI_MASK;
+
+ this->command(mtd, ONENAND_CMD_RESET, 0, 0);
+ ret = this->wait(mtd, FL_RESETING);
+
+ printk(KERN_INFO "Die %d boundary: %d%s\n", die,
+ this->boundary[die], locked ? "(Locked)" : "(Unlocked)");
+ }
+
+ /* Enable ECC */
+ this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
+ return 0;
+}
+
+/**
+ * flexonenand_get_size - Fill up fields in onenand_chip and mtd_info
+ * boundary[], diesize[], mtd->size, mtd->erasesize,
+ * mtd->eraseregions
+ * @param mtd - MTD device structure
+ */
+static void flexonenand_get_size(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+ int die, i, eraseshift, density;
+ int blksperdie, maxbdry;
+ loff_t ofs;
+
+ density = onenand_get_density(this->device_id);
+ blksperdie = ((loff_t)(16 << density) << 20) >> (this->erase_shift);
+ blksperdie >>= ONENAND_IS_DDP(this) ? 1 : 0;
+ maxbdry = blksperdie - 1;
+ eraseshift = this->erase_shift - 1;
+
+ mtd->numeraseregions = this->dies << 1;
+
+ /* This fills up the device boundary */
+ flexonenand_get_boundary(mtd);
+ die = 0;
+ ofs = 0;
+ i = -1;
+ for (; die < this->dies; die++) {
+ if (!die || this->boundary[die-1] != maxbdry) {
+ i++;
+ mtd->eraseregions[i].offset = ofs;
+ mtd->eraseregions[i].erasesize = 1 << eraseshift;
+ mtd->eraseregions[i].numblocks =
+ this->boundary[die] + 1;
+ ofs += mtd->eraseregions[i].numblocks << eraseshift;
+ eraseshift++;
+ } else {
+ mtd->numeraseregions -= 1;
+ mtd->eraseregions[i].numblocks +=
+ this->boundary[die] + 1;
+ ofs += (this->boundary[die] + 1) << (eraseshift - 1);
+ }
+ if (this->boundary[die] != maxbdry) {
+ i++;
+ mtd->eraseregions[i].offset = ofs;
+ mtd->eraseregions[i].erasesize = 1 << eraseshift;
+ mtd->eraseregions[i].numblocks = maxbdry ^
+ this->boundary[die];
+ ofs += mtd->eraseregions[i].numblocks << eraseshift;
+ eraseshift--;
+ } else
+ mtd->numeraseregions -= 1;
+ }
+
+ /* Expose MLC erase size except when all blocks are SLC */
+ mtd->erasesize = 1 << this->erase_shift;
+ if (mtd->numeraseregions == 1)
+ mtd->erasesize >>= 1;
+
+ printk(KERN_INFO "Device has %d eraseregions\n", mtd->numeraseregions);
+ for (i = 0; i < mtd->numeraseregions; i++)
+ printk(KERN_INFO "[offset: 0x%08llx, erasesize: 0x%05x,"
+ " numblocks: %04u]\n", mtd->eraseregions[i].offset,
+ mtd->eraseregions[i].erasesize,
+ mtd->eraseregions[i].numblocks);
+
+ for (die = 0, mtd->size = 0; die < this->dies; die++) {
+ this->diesize[die] = (loff_t) (blksperdie << this->erase_shift);
+ this->diesize[die] -= (loff_t) (this->boundary[die] + 1)
+ << (this->erase_shift - 1);
+ mtd->size += this->diesize[die];
+ }
+}
+
+/**
+ * flexonenand_check_blocks_erased - Check if blocks are erased
+ * @param mtd_info - mtd info structure
+ * @param start - first erase block to check
+ * @param end - last erase block to check
+ *
+ * Converting an unerased block from MLC to SLC
+ * causes byte values to change. Since both data and its ECC
+ * have changed, reads on the block give uncorrectable error.
+ * This might lead to the block being detected as bad.
+ *
+ * Avoid this by ensuring that the block to be converted is
+ * erased.
+ */
+static int flexonenand_check_blocks_erased(struct mtd_info *mtd,
+ int start, int end)
+{
+ struct onenand_chip *this = mtd->priv;
+ int i, ret;
+ int block;
+ struct mtd_oob_ops ops = {
+ .mode = MTD_OOB_PLACE,
+ .ooboffs = 0,
+ .ooblen = mtd->oobsize,
+ .datbuf = NULL,
+ .oobbuf = this->oob_buf,
+ };
+ loff_t addr;
+
+ printk(KERN_DEBUG "Check blocks from %d to %d\n", start, end);
+
+ for (block = start; block <= end; block++) {
+ addr = flexonenand_addr(this, block);
+ if (onenand_block_isbad_nolock(mtd, addr, 0))
+ continue;
+
+ /*
+ * Since main area write results in ECC write to spare,
+ * it is sufficient to check only ECC bytes for change.
+ */
+ ret = onenand_read_oob_nolock(mtd, addr, &ops);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < mtd->oobsize; i++)
+ if (this->oob_buf[i] != 0xff)
+ break;
+
+ if (i != mtd->oobsize) {
+ printk(KERN_WARNING "Block %d not erased.\n", block);
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * flexonenand_set_boundary - Writes the SLC boundary
+ * @param mtd - mtd info structure
+ */
+int flexonenand_set_boundary(struct mtd_info *mtd, int die,
+ int boundary, int lock)
+{
+ struct onenand_chip *this = mtd->priv;
+ int ret, density, blksperdie, old, new, thisboundary;
+ loff_t addr;
+
+ if (die >= this->dies)
+ return -EINVAL;
+
+ if (boundary == this->boundary[die])
+ return 0;
+
+ density = onenand_get_density(this->device_id);
+ blksperdie = ((16 << density) << 20) >> this->erase_shift;
+ blksperdie >>= ONENAND_IS_DDP(this) ? 1 : 0;
+
+ if (boundary >= blksperdie) {
+ printk("flexonenand_set_boundary:"
+ "Invalid boundary value. "
+ "Boundary not changed.\n");
+ return -EINVAL;
+ }
+
+ /* Check if converting blocks are erased */
+ old = this->boundary[die] + (die * this->density_mask);
+ new = boundary + (die * this->density_mask);
+ ret = flexonenand_check_blocks_erased(mtd, min(old, new)
+ + 1, max(old, new));
+ if (ret) {
+ printk(KERN_ERR "flexonenand_set_boundary: Please erase blocks before boundary change\n");
+ return ret;
+ }
+
+ this->command(mtd, FLEXONENAND_CMD_PI_ACCESS, die, 0);
+ this->wait(mtd, FL_SYNCING);
+
+ /* Check is boundary is locked */
+ this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0);
+ ret = this->wait(mtd, FL_READING);
+
+ thisboundary = this->read_word(this->base + ONENAND_DATARAM);
+ if ((thisboundary >> FLEXONENAND_PI_UNLOCK_SHIFT) != 3) {
+ printk(KERN_ERR "flexonenand_set_boundary: boundary locked\n");
+ goto out;
+ }
+
+ printk(KERN_INFO "flexonenand_set_boundary: Changing die %d boundary: %d%s\n",
+ die, boundary, lock ? "(Locked)" : "(Unlocked)");
+
+ boundary &= FLEXONENAND_PI_MASK;
+ boundary |= lock ? 0 : (3 << FLEXONENAND_PI_UNLOCK_SHIFT);
+
+ addr = die ? this->diesize[0] : 0;
+ this->command(mtd, ONENAND_CMD_ERASE, addr, 0);
+ ret = this->wait(mtd, FL_ERASING);
+ if (ret) {
+ printk("flexonenand_set_boundary:"
+ "Failed PI erase for Die %d\n", die);
+ goto out;
+ }
+
+ this->write_word(boundary, this->base + ONENAND_DATARAM);
+ this->command(mtd, ONENAND_CMD_PROG, addr, 0);
+ ret = this->wait(mtd, FL_WRITING);
+ if (ret) {
+ printk("flexonenand_set_boundary:"
+ "Failed PI write for Die %d\n", die);
+ goto out;
+ }
+
+ this->command(mtd, FLEXONENAND_CMD_PI_UPDATE, die, 0);
+ ret = this->wait(mtd, FL_WRITING);
+out:
+ this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_REG_COMMAND);
+ this->wait(mtd, FL_RESETING);
+ if (!ret)
+ /* Recalculate device size on boundary change*/
+ flexonenand_get_size(mtd);
+
+ return ret;
+}
+
/**
* onenand_probe - [OneNAND Interface] Probe the OneNAND device
* @param mtd MTD device structure
maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID);
dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID);
ver_id = this->read_word(this->base + ONENAND_REG_VERSION_ID);
+ this->technology = this->read_word(this->base + ONENAND_REG_TECHNOLOGY);
/* Check OneNAND device */
if (maf_id != bram_maf_id || dev_id != bram_dev_id)
return -ENXIO;
- /* FIXME : Current OneNAND MTD doesn't support Flex-OneNAND */
- if (dev_id & (1 << 9)) {
- printk("Not yet support Flex-OneNAND\n");
- return -ENXIO;
- }
-
/* Flash device information */
mtd->name = onenand_print_device_info(dev_id, ver_id);
this->device_id = dev_id;
this->version_id = ver_id;
density = onenand_get_density(dev_id);
+ if (FLEXONENAND(this)) {
+ this->dies = ONENAND_IS_DDP(this) ? 2 : 1;
+ /* Maximum possible erase regions */
+ mtd->numeraseregions = this->dies << 1;
+ mtd->eraseregions = malloc(sizeof(struct mtd_erase_region_info)
+ * (this->dies << 1));
+ if (!mtd->eraseregions)
+ return -ENOMEM;
+ }
+
+ /*
+ * For Flex-OneNAND, chipsize represents maximum possible device size.
+ * mtd->size represents the actual device size.
+ */
this->chipsize = (16 << density) << 20;
- /* Set density mask. it is used for DDP */
- if (ONENAND_IS_DDP(this))
- this->density_mask = (1 << (density + 6));
- else
- this->density_mask = 0;
/* OneNAND page size & block size */
/* The data buffer size is equal to page size */
mtd->writesize =
this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE);
+ /* We use the full BufferRAM */
+ if (ONENAND_IS_MLC(this))
+ mtd->writesize <<= 1;
+
mtd->oobsize = mtd->writesize >> 5;
/* Pagers per block is always 64 in OneNAND */
mtd->erasesize = mtd->writesize << 6;
+ /*
+ * Flex-OneNAND SLC area has 64 pages per block.
+ * Flex-OneNAND MLC area has 128 pages per block.
+ * Expose MLC erase size to find erase_shift and page_mask.
+ */
+ if (FLEXONENAND(this))
+ mtd->erasesize <<= 1;
this->erase_shift = ffs(mtd->erasesize) - 1;
this->page_shift = ffs(mtd->writesize) - 1;
this->ppb_shift = (this->erase_shift - this->page_shift);
this->page_mask = (mtd->erasesize / mtd->writesize) - 1;
+ /* Set density mask. it is used for DDP */
+ if (ONENAND_IS_DDP(this))
+ this->density_mask = this->chipsize >> (this->erase_shift + 1);
/* It's real page size */
this->writesize = mtd->writesize;
/* REVIST: Multichip handling */
- mtd->size = this->chipsize;
+ if (FLEXONENAND(this))
+ flexonenand_get_size(mtd);
+ else
+ mtd->size = this->chipsize;
/* Check OneNAND features */
onenand_check_features(mtd);
* Allow subpage writes up to oobsize.
*/
switch (mtd->oobsize) {
+ case 128:
+ this->ecclayout = &onenand_oob_128;
+ mtd->subpage_sft = 0;
+ break;
+
case 64:
this->ecclayout = &onenand_oob_64;
mtd->subpage_sft = 2;
loff_t from;
size_t readlen, ooblen;
struct mtd_oob_ops ops;
+ int rgn;
printk(KERN_INFO "Scanning device for bad blocks\n");
/* Note that numblocks is 2 * (real numblocks) here;
* see i += 2 below as it makses shifting and masking less painful
*/
- numblocks = mtd->size >> (bbm->bbt_erase_shift - 1);
+ numblocks = this->chipsize >> (bbm->bbt_erase_shift - 1);
startblock = 0;
from = 0;
}
}
i += 2;
- from += (1 << bbm->bbt_erase_shift);
+
+ if (FLEXONENAND(this)) {
+ rgn = flexonenand_region(mtd, from);
+ from += mtd->eraseregions[rgn].erasesize;
+ } else
+ from += (1 << bbm->bbt_erase_shift);
}
return 0;
uint8_t res;
/* Get block number * 2 */
- block = (int)(offs >> (bbm->bbt_erase_shift - 1));
+ block = (int) (onenand_block(this, offs) << 1);
res = (bbm->bbt[block >> 3] >> (block & 0x06)) & 0x03;
MTDDEBUG (MTD_DEBUG_LEVEL2,
struct bbm_info *bbm = this->bbm;
int len, ret = 0;
- len = mtd->size >> (this->erase_shift + 2);
+ len = this->chipsize >> (this->erase_shift + 2);
/* Allocate memory (2bit per block) */
bbm->bbt = malloc(len);
if (!bbm->bbt) {
onenand_scan(&onenand_mtd, 1);
+ if (onenand_chip.device_id & DEVICE_IS_FLEXONENAND)
+ puts("Flex-");
puts("OneNAND: ");
- print_size(onenand_mtd.size, "\n");
+ print_size(onenand_chip.chipsize, "\n");
#ifdef CONFIG_MTD_DEVICE
/*
COBJS-$(CONFIG_SPI_FLASH_SPANSION) += spansion.o
COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o
COBJS-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.o
+COBJS-$(CONFIG_SPI_FLASH_WINBOND) += winbond.o
COBJS-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
COBJS := $(COBJS-y)
flash = spi_flash_probe_macronix(spi, idcode);
break;
#endif
+#ifdef CONFIG_SPI_FLASH_WINBOND
+ case 0xef:
+ flash = spi_flash_probe_winbond(spi, idcode);
+ break;
+#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
case 0x20:
flash = spi_flash_probe_stmicro(spi, idcode);
struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode);
ret = 0;
for (actual = 0; actual < len; actual++) {
- cmd[1] = (offset / sector_size) + actual;
+ cmd[1] = offset >> 16;
+ offset += sector_size;
ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0);
if (ret < 0) {
--- /dev/null
+/*
+ * Copyright 2008, Network Appliance Inc.
+ * Author: Jason McMullan <mcmullan <at> netapp.com>
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi_flash.h>
+
+#include "spi_flash_internal.h"
+
+/* M25Pxx-specific commands */
+#define CMD_W25_WREN 0x06 /* Write Enable */
+#define CMD_W25_WRDI 0x04 /* Write Disable */
+#define CMD_W25_RDSR 0x05 /* Read Status Register */
+#define CMD_W25_WRSR 0x01 /* Write Status Register */
+#define CMD_W25_READ 0x03 /* Read Data Bytes */
+#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
+#define CMD_W25_PP 0x02 /* Page Program */
+#define CMD_W25_SE 0x20 /* Sector (4K) Erase */
+#define CMD_W25_BE 0xd8 /* Block (64K) Erase */
+#define CMD_W25_CE 0xc7 /* Chip Erase */
+#define CMD_W25_DP 0xb9 /* Deep Power-down */
+#define CMD_W25_RES 0xab /* Release from DP, and Read Signature */
+
+#define WINBOND_ID_W25X16 0x3015
+#define WINBOND_ID_W25X32 0x3016
+#define WINBOND_ID_W25X64 0x3017
+
+#define WINBOND_SR_WIP (1 << 0) /* Write-in-Progress */
+
+struct winbond_spi_flash_params {
+ uint16_t id;
+ /* Log2 of page size in power-of-two mode */
+ uint8_t l2_page_size;
+ uint16_t pages_per_sector;
+ uint16_t sectors_per_block;
+ uint8_t nr_blocks;
+ const char *name;
+};
+
+/* spi_flash needs to be first so upper layers can free() it */
+struct winbond_spi_flash {
+ struct spi_flash flash;
+ const struct winbond_spi_flash_params *params;
+};
+
+static inline struct winbond_spi_flash *
+to_winbond_spi_flash(struct spi_flash *flash)
+{
+ return container_of(flash, struct winbond_spi_flash, flash);
+}
+
+static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
+ {
+ .id = WINBOND_ID_W25X16,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 32,
+ .name = "W25X16",
+ },
+ {
+ .id = WINBOND_ID_W25X32,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 64,
+ .name = "W25X32",
+ },
+ {
+ .id = WINBOND_ID_W25X64,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 128,
+ .name = "W25X64",
+ },
+};
+
+static int winbond_wait_ready(struct spi_flash *flash, unsigned long timeout)
+{
+ struct spi_slave *spi = flash->spi;
+ unsigned long timebase;
+ int ret;
+ u8 status;
+ u8 cmd[4] = { CMD_W25_RDSR, 0xff, 0xff, 0xff };
+
+ ret = spi_xfer(spi, 32, &cmd[0], NULL, SPI_XFER_BEGIN);
+ if (ret) {
+ debug("SF: Failed to send command %02x: %d\n", cmd, ret);
+ return ret;
+ }
+
+ timebase = get_timer(0);
+ do {
+ ret = spi_xfer(spi, 8, NULL, &status, 0);
+ if (ret) {
+ debug("SF: Failed to get status for cmd %02x: %d\n", cmd, ret);
+ return -1;
+ }
+
+ if ((status & WINBOND_SR_WIP) == 0)
+ break;
+
+ } while (get_timer(timebase) < timeout);
+
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
+
+ if ((status & WINBOND_SR_WIP) == 0)
+ return 0;
+
+ debug("SF: Timed out on command %02x: %d\n", cmd, ret);
+ /* Timed out */
+ return -1;
+}
+
+/*
+ * Assemble the address part of a command for Winbond devices in
+ * non-power-of-two page size mode.
+ */
+static void winbond_build_address(struct winbond_spi_flash *stm, u8 *cmd, u32 offset)
+{
+ unsigned long page_addr;
+ unsigned long byte_addr;
+ unsigned long page_size;
+ unsigned int page_shift;
+
+ /*
+ * The "extra" space per page is the power-of-two page size
+ * divided by 32.
+ */
+ page_shift = stm->params->l2_page_size;
+ page_size = (1 << page_shift);
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ cmd[0] = page_addr >> (16 - page_shift);
+ cmd[1] = page_addr << (page_shift - 8) | (byte_addr >> 8);
+ cmd[2] = byte_addr;
+}
+
+static int winbond_read_fast(struct spi_flash *flash,
+ u32 offset, size_t len, void *buf)
+{
+ struct winbond_spi_flash *stm = to_winbond_spi_flash(flash);
+ u8 cmd[5];
+
+ cmd[0] = CMD_READ_ARRAY_FAST;
+ winbond_build_address(stm, cmd + 1, offset);
+ cmd[4] = 0x00;
+
+ return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len);
+}
+
+static int winbond_write(struct spi_flash *flash,
+ u32 offset, size_t len, const void *buf)
+{
+ struct winbond_spi_flash *stm = to_winbond_spi_flash(flash);
+ unsigned long page_addr;
+ unsigned long byte_addr;
+ unsigned long page_size;
+ unsigned int page_shift;
+ size_t chunk_len;
+ size_t actual;
+ int ret;
+ u8 cmd[4];
+
+ page_shift = stm->params->l2_page_size;
+ page_size = (1 << page_shift);
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ for (actual = 0; actual < len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size - byte_addr);
+
+ cmd[0] = CMD_W25_PP;
+ cmd[1] = page_addr >> (16 - page_shift);
+ cmd[2] = page_addr << (page_shift - 8) | (byte_addr >> 8);
+ cmd[3] = byte_addr;
+ debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n",
+ buf + actual,
+ cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+
+ ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0);
+ if (ret < 0) {
+ debug("SF: Enabling Write failed\n");
+ goto out;
+ }
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, 4,
+ buf + actual, chunk_len);
+ if (ret < 0) {
+ debug("SF: Winbond Page Program failed\n");
+ goto out;
+ }
+
+ ret = winbond_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret < 0) {
+ debug("SF: Winbond page programming timed out\n");
+ goto out;
+ }
+
+ page_addr++;
+ byte_addr = 0;
+ }
+
+ debug("SF: Winbond: Successfully programmed %u bytes @ 0x%x\n",
+ len, offset);
+ ret = 0;
+
+out:
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+int winbond_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ struct winbond_spi_flash *stm = to_winbond_spi_flash(flash);
+ unsigned long sector_size;
+ unsigned int page_shift;
+ size_t actual;
+ int ret;
+ u8 cmd[4];
+
+ /*
+ * This function currently uses sector erase only.
+ * probably speed things up by using bulk erase
+ * when possible.
+ */
+
+ page_shift = stm->params->l2_page_size;
+ sector_size = (1 << page_shift) * stm->params->pages_per_sector;
+
+ if (offset % sector_size || len % sector_size) {
+ debug("SF: Erase offset/length not multiple of sector size\n");
+ return -1;
+ }
+
+ len /= sector_size;
+ cmd[0] = CMD_W25_SE;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ for (actual = 0; actual < len; actual++) {
+ winbond_build_address(stm, &cmd[1], offset + actual * sector_size);
+ printf("Erase: %02x %02x %02x %02x\n",
+ cmd[0], cmd[1], cmd[2], cmd[3]);
+
+ ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0);
+ if (ret < 0) {
+ debug("SF: Enabling Write failed\n");
+ goto out;
+ }
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0);
+ if (ret < 0) {
+ debug("SF: Winbond sector erase failed\n");
+ goto out;
+ }
+
+ ret = winbond_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
+ if (ret < 0) {
+ debug("SF: Winbond sector erase timed out\n");
+ goto out;
+ }
+ }
+
+ debug("SF: Winbond: Successfully erased %u bytes @ 0x%x\n",
+ len * sector_size, offset);
+ ret = 0;
+
+out:
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode)
+{
+ const struct winbond_spi_flash_params *params;
+ unsigned long page_size;
+ struct winbond_spi_flash *stm;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) {
+ params = &winbond_spi_flash_table[i];
+ if (params->id == ((idcode[1] << 8) | idcode[2]))
+ break;
+ }
+
+ if (i == ARRAY_SIZE(winbond_spi_flash_table)) {
+ debug("SF: Unsupported Winbond ID %02x%02x\n",
+ idcode[1], idcode[2]);
+ return NULL;
+ }
+
+ stm = malloc(sizeof(struct winbond_spi_flash));
+ if (!stm) {
+ debug("SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ stm->params = params;
+ stm->flash.spi = spi;
+ stm->flash.name = params->name;
+
+ /* Assuming power-of-two page size initially. */
+ page_size = 1 << params->l2_page_size;
+
+ stm->flash.write = winbond_write;
+ stm->flash.erase = winbond_erase;
+ stm->flash.read = winbond_read_fast;
+ stm->flash.size = page_size * params->pages_per_sector
+ * params->sectors_per_block
+ * params->nr_blocks;
+
+ debug("SF: Detected %s with page size %u, total %u bytes\n",
+ params->name, page_size, stm->flash.size);
+
+ return &stm->flash;
+}
COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o
COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
-COBJS-$(CONFIG_DRIVER_LAN91C96) += lan91c96.o
+COBJS-$(CONFIG_LAN91C96) += lan91c96.o
COBJS-$(CONFIG_MACB) += macb.o
COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
#define REG_READ(a) readl((a))
/* we don't need 16 bit initialisation on 32 bit bus */
-#define get_reg_init_bus(x) get_reg((x))
+#define get_reg_init_bus(r,d) get_reg((r),(d))
#else
memset(priv, 0, sizeof(*priv));
priv->regs = (struct cs8900_regs *)base_addr;
- /* Load MAC address from EEPROM */
- cs8900_get_enetaddr(dev);
-
dev->iobase = base_addr;
dev->priv = priv;
dev->init = cs8900_init;
dev->halt = cs8900_halt;
dev->send = cs8900_send;
dev->recv = cs8900_recv;
+
+ /* Load MAC address from EEPROM */
+ cs8900_get_enetaddr(dev);
+
sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);
eth_register(dev);
#define DM9000_DMP_PACKET(func,packet,length) \
do { \
int i; \
- printf(func ": length: %d\n", length); \
+ printf("%s: length: %d\n", func, length); \
for (i = 0; i < length; i++) { \
if (i % 8 == 0) \
printf("\n%s: %02x: ", func, i); \
int i, oft, lnk;
u8 io_mode;
struct board_info *db = &dm9000_info;
- uchar enetaddr[6];
DM9000_DBG("%s\n", __func__);
/* Clear interrupt status */
DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
- /* Set Node address */
- if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-#if !defined(CONFIG_DM9000_NO_SROM)
- for (i = 0; i < 3; i++)
- dm9000_read_srom_word(i, enetaddr + 2 * i);
- eth_setenv_enetaddr("ethaddr", enetaddr);
-#endif
- }
-
- printf("MAC: %pM\n", enetaddr);
+ printf("MAC: %pM\n", dev->enetaddr);
/* fill device MAC address registers */
for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
- DM9000_iow(oft, enetaddr[i]);
+ DM9000_iow(oft, dev->enetaddr[i]);
for (i = 0, oft = 0x16; i < 8; i++, oft++)
DM9000_iow(oft, 0xff);
}
#endif
+static void dm9000_get_enetaddr(struct eth_device *dev)
+{
+#if !defined(CONFIG_DM9000_NO_SROM)
+ int i;
+ for (i = 0; i < 3; i++)
+ dm9000_read_srom_word(i, dev->enetaddr + (2 * i));
+#endif
+}
+
/*
Read a byte from I/O port
*/
{
struct eth_device *dev = &(dm9000_info.netdev);
+ /* Load MAC address from EEPROM */
+ dm9000_get_enetaddr(dev);
+
dev->init = dm9000_init;
dev->halt = dm9000_halt;
dev->send = dm9000_send;
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
.tbd_base = NULL,
.tbd_index = 0,
.bd = NULL,
+ .rdb_ptr = NULL,
+ .base_ptr = NULL,
};
/*
/*
* Set the auto-negotiation advertisement register bits
*/
- miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR, 0x1e0);
+ miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR,
+ PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
+ PHY_ANLPAR_10 | PHY_ANLPAR_PSB_802_3);
miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
uint32_t p = 0;
/* reserve data memory and consider alignment */
- fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
+ if (fec->rdb_ptr == NULL)
+ fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
p = (uint32_t)fec->rdb_ptr;
if (!p) {
puts("fec_imx27: not enough malloc memory!\n");
writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
miiphy_wait_aneg(edev);
- miiphy_speed(edev->name, 0);
- miiphy_duplex(edev->name, 0);
+ miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);
+ miiphy_duplex(edev->name, CONFIG_FEC_MXC_PHYADDR);
/*
* Enable SmartDMA receive task
* Datasheet forces the startaddress of each chain is 16 byte
* aligned
*/
- fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
- sizeof(struct fec_bd) + DB_ALIGNMENT);
+ if (fec->base_ptr == NULL)
+ fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
+ sizeof(struct fec_bd) + DB_ALIGNMENT);
base = (uint32_t)fec->base_ptr;
if (!base) {
puts("fec_imx27: not enough malloc memory!\n");
*/
if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
free(fec->base_ptr);
+ fec->base_ptr = NULL;
return -ENOMEM;
}
fec_tbd_init(fec);
writel(0, &fec->eth->ecntrl);
fec->rbd_index = 0;
fec->tbd_index = 0;
- free(fec->rdb_ptr);
- free(fec->base_ptr);
debug("eth_halt: done\n");
}
#include <common.h>
#include <command.h>
+#include <malloc.h>
#include "lan91c96.h"
#include <net.h>
*
*------------------------------------------------------------------------
*/
-#define CARDNAME "LAN91C96"
-
-#define SMC_BASE_ADDRESS CONFIG_LAN91C96_BASE
-
-#define SMC_DEV_NAME "LAN91C96"
+#define DRIVER_NAME "LAN91C96"
#define SMC_ALLOC_MAX_TRY 5
#define SMC_TX_TIMEOUT 30
#undef USE_32_BIT
#endif
-/*-----------------------------------------------------------------
- *
- * The driver can be entered at any of the following entry points.
- *
- *-----------------------------------------------------------------
- */
-
-extern int eth_init (bd_t * bd);
-extern void eth_halt (void);
-extern int eth_rx (void);
-extern int eth_send (volatile void *packet, int length);
-#if 0
-static int smc_hw_init (void);
-#endif
-
-/*
- * This is called by register_netdev(). It is responsible for
- * checking the portlist for the SMC9000 series chipset. If it finds
- * one, then it will initialize the device, find the hardware information,
- * and sets up the appropriate device parameters.
- * NOTE: Interrupts are *OFF* when this procedure is called.
- *
- * NB:This shouldn't be static since it is referred to externally.
- */
-int smc_init (void);
-
-/*
- * This is called by unregister_netdev(). It is responsible for
- * cleaning up before the driver is finally unregistered and discarded.
- */
-void smc_destructor (void);
-
-/*
- * The kernel calls this function when someone wants to use the device,
- * typically 'ifconfig ethX up'.
- */
-static int smc_open (bd_t *bd);
-
-
-/*
- * This is called by the kernel in response to 'ifconfig ethX down'. It
- * is responsible for cleaning up everything that the open routine
- * does, and maybe putting the card into a powerdown state.
- */
-static int smc_close (void);
-
-/*
- * This is a separate procedure to handle the receipt of a packet, to
- * leave the interrupt code looking slightly cleaner
- */
-static int smc_rcv (void);
-
/* See if a MAC address is defined in the current environment. If so use it. If not
. print a warning and set the environment and other globals with the default.
. If an EEPROM is present it really should be consulted.
*/
-int smc_get_ethaddr(bd_t *bd);
-int get_rom_mac(unsigned char *v_rom_mac);
+static int smc_get_ethaddr(bd_t *bd, struct eth_device *dev);
+static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac);
/* ------------------------------------------------------------
* Internal routines
* the default mac address.
*/
-void smc_set_mac_addr (const unsigned char *addr)
+static void smc_set_mac_addr(const unsigned char *addr)
{
int i;
}
}
-/*
- * smc_get_macaddr is no longer used. If you want to override the default
- * mac address, call smc_get_mac_addr as a part of the board initialisation.
- */
-
-#if 0
-void smc_get_macaddr (byte * addr)
-{
- /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
- unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010);
- int i;
-
-
- for (i = 0; i < 6; i++) {
- addr[0] = *(dnp1110_mac + 0);
- addr[1] = *(dnp1110_mac + 1);
- addr[2] = *(dnp1110_mac + 2);
- addr[3] = *(dnp1110_mac + 3);
- addr[4] = *(dnp1110_mac + 4);
- addr[5] = *(dnp1110_mac + 5);
- }
-}
-#endif /* 0 */
-
/***********************************************
* Show available memory *
***********************************************/
-void dump_memory_info (void)
+void dump_memory_info(struct eth_device *dev)
{
word mem_info;
word old_bank;
- old_bank = SMC_inw (LAN91C96_BANK_SELECT) & 0xF;
+ old_bank = SMC_inw(dev, LAN91C96_BANK_SELECT) & 0xF;
- SMC_SELECT_BANK (0);
- mem_info = SMC_inw (LAN91C96_MIR);
+ SMC_SELECT_BANK(dev, 0);
+ mem_info = SMC_inw(dev, LAN91C96_MIR);
PRINTK2 ("Memory: %4d available\n", (mem_info >> 8) * 2048);
- SMC_SELECT_BANK (old_bank);
+ SMC_SELECT_BANK(dev, old_bank);
}
/*
static void print_packet (byte *, int);
#endif
-/* #define tx_done(dev) 1 */
-
-
-/* this does a soft reset on the device */
-static void smc_reset (void);
-
-/* Enable Interrupts, Receive, and Transmit */
-static void smc_enable (void);
-
-/* this puts the device in an inactive state */
-static void smc_shutdown (void);
-
-
-static int poll4int (byte mask, int timeout)
+static int poll4int (struct eth_device *dev, byte mask, int timeout)
{
int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
int is_timeout = 0;
- word old_bank = SMC_inw (LAN91C96_BANK_SELECT);
+ word old_bank = SMC_inw(dev, LAN91C96_BANK_SELECT);
PRINTK2 ("Polling...\n");
- SMC_SELECT_BANK (2);
- while ((SMC_inw (LAN91C96_INT_STATS) & mask) == 0) {
+ SMC_SELECT_BANK(dev, 2);
+ while ((SMC_inw(dev, LAN91C96_INT_STATS) & mask) == 0) {
if (get_timer (0) >= tmo) {
is_timeout = 1;
break;
}
/* restore old bank selection */
- SMC_SELECT_BANK (old_bank);
+ SMC_SELECT_BANK(dev, old_bank);
if (is_timeout)
return 1;
}
/*
- * Function: smc_reset( void )
+ * Function: smc_reset
* Purpose:
* This sets the SMC91111 chip to its normal state, hopefully from whatever
* mess that any other DOS driver has put it in.
* 5. clear all interrupts
*
*/
-static void smc_reset (void)
+static void smc_reset(struct eth_device *dev)
{
- PRINTK2 ("%s:smc_reset\n", SMC_DEV_NAME);
+ PRINTK2("%s:smc_reset\n", dev->name);
/* This resets the registers mostly to defaults, but doesn't
affect EEPROM. That seems unnecessary */
- SMC_SELECT_BANK (0);
- SMC_outw (LAN91C96_RCR_SOFT_RST, LAN91C96_RCR);
+ SMC_SELECT_BANK(dev, 0);
+ SMC_outw(dev, LAN91C96_RCR_SOFT_RST, LAN91C96_RCR);
udelay (10);
/* Disable transmit and receive functionality */
- SMC_outw (0, LAN91C96_RCR);
- SMC_outw (0, LAN91C96_TCR);
+ SMC_outw(dev, 0, LAN91C96_RCR);
+ SMC_outw(dev, 0, LAN91C96_TCR);
/* set the control register */
- SMC_SELECT_BANK (1);
- SMC_outw (SMC_inw (LAN91C96_CONTROL) | LAN91C96_CTR_BIT_8,
+ SMC_SELECT_BANK(dev, 1);
+ SMC_outw(dev, SMC_inw(dev, LAN91C96_CONTROL) | LAN91C96_CTR_BIT_8,
LAN91C96_CONTROL);
/* Disable all interrupts */
- SMC_outb (0, LAN91C96_INT_MASK);
+ SMC_outb(dev, 0, LAN91C96_INT_MASK);
}
/*
* 2. Enable the transmitter
* 3. Enable the receiver
*/
-static void smc_enable ()
+static void smc_enable(struct eth_device *dev)
{
- PRINTK2 ("%s:smc_enable\n", SMC_DEV_NAME);
- SMC_SELECT_BANK (0);
+ PRINTK2("%s:smc_enable\n", dev->name);
+ SMC_SELECT_BANK(dev, 0);
/* Initialize the Memory Configuration Register. See page
49 of the LAN91C96 data sheet for details. */
- SMC_outw (LAN91C96_MCR_TRANSMIT_PAGES, LAN91C96_MCR);
+ SMC_outw(dev, LAN91C96_MCR_TRANSMIT_PAGES, LAN91C96_MCR);
/* Initialize the Transmit Control Register */
- SMC_outw (LAN91C96_TCR_TXENA, LAN91C96_TCR);
+ SMC_outw(dev, LAN91C96_TCR_TXENA, LAN91C96_TCR);
/* Initialize the Receive Control Register
* FIXME:
* The promiscuous bit set because I could not receive ARP reply
* packets from the server when I send a ARP request. It only works
* when I set the promiscuous bit
*/
- SMC_outw (LAN91C96_RCR_RXEN | LAN91C96_RCR_PRMS, LAN91C96_RCR);
+ SMC_outw(dev, LAN91C96_RCR_RXEN | LAN91C96_RCR_PRMS, LAN91C96_RCR);
}
/*
* the manual says that it will wake up in response to any I/O requests
* in the register space. Empirical results do not show this working.
*/
-static void smc_shutdown ()
+static void smc_shutdown(struct eth_device *dev)
{
- PRINTK2 (CARDNAME ":smc_shutdown\n");
+ PRINTK2("%s:smc_shutdown\n", dev->name);
/* no more interrupts for me */
- SMC_SELECT_BANK (2);
- SMC_outb (0, LAN91C96_INT_MASK);
+ SMC_SELECT_BANK(dev, 2);
+ SMC_outb(dev, 0, LAN91C96_INT_MASK);
/* and tell the card to stay away from that nasty outside world */
- SMC_SELECT_BANK (0);
- SMC_outb (0, LAN91C96_RCR);
- SMC_outb (0, LAN91C96_TCR);
+ SMC_SELECT_BANK(dev, 0);
+ SMC_outb(dev, 0, LAN91C96_RCR);
+ SMC_outb(dev, 0, LAN91C96_TCR);
}
* Enable the transmit interrupt, so I know if it failed
* Free the kernel data if I actually sent it.
*/
-static int smc_send_packet (volatile void *packet, int packet_length)
+static int smc_send_packet(struct eth_device *dev, volatile void *packet,
+ int packet_length)
{
byte packet_no;
unsigned long ioaddr;
byte status;
- PRINTK3 ("%s:smc_hardware_send_packet\n", SMC_DEV_NAME);
+ PRINTK3("%s:smc_hardware_send_packet\n", dev->name);
length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
numPages >>= 8; /* Divide by 256 */
if (numPages > 7) {
- printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
+ printf("%s: Far too big packet error. \n", dev->name);
return 0;
}
/* now, try to allocate the memory */
- SMC_SELECT_BANK (2);
- SMC_outw (LAN91C96_MMUCR_ALLOC_TX | numPages, LAN91C96_MMU);
+ SMC_SELECT_BANK(dev, 2);
+ SMC_outw(dev, LAN91C96_MMUCR_ALLOC_TX | numPages, LAN91C96_MMU);
again:
try++;
time_out = MEMORY_WAIT_TIME;
do {
- status = SMC_inb (LAN91C96_INT_STATS);
+ status = SMC_inb(dev, LAN91C96_INT_STATS);
if (status & LAN91C96_IST_ALLOC_INT) {
- SMC_outb (LAN91C96_IST_ALLOC_INT, LAN91C96_INT_STATS);
+ SMC_outb(dev, LAN91C96_IST_ALLOC_INT,
+ LAN91C96_INT_STATS);
break;
}
} while (--time_out);
if (!time_out) {
PRINTK2 ("%s: memory allocation, try %d failed ...\n",
- SMC_DEV_NAME, try);
+ dev->name, try);
if (try < SMC_ALLOC_MAX_TRY)
goto again;
else
}
PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
- SMC_DEV_NAME, try);
+ dev->name, try);
/* I can send the packet now.. */
- ioaddr = SMC_BASE_ADDRESS;
+ ioaddr = dev->iobase;
buf = (byte *) packet;
/* If I get here, I _know_ there is a packet slot waiting for me */
- packet_no = SMC_inb (LAN91C96_ARR);
+ packet_no = SMC_inb(dev, LAN91C96_ARR);
if (packet_no & LAN91C96_ARR_FAILED) {
/* or isn't there? BAD CHIP! */
- printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
+ printf("%s: Memory allocation failed. \n", dev->name);
return 0;
}
/* we have a packet address, so tell the card to use it */
- SMC_outb (packet_no, LAN91C96_PNR);
+ SMC_outb(dev, packet_no, LAN91C96_PNR);
/* point to the beginning of the packet */
- SMC_outw (LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER);
+ SMC_outw(dev, LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER);
- PRINTK3 ("%s: Trying to xmit packet of length %x\n",
- SMC_DEV_NAME, length);
+ PRINTK3("%s: Trying to xmit packet of length %x\n",
+ dev->name, length);
#if SMC_DEBUG > 2
printf ("Transmitting Packet\n");
/* send the packet length ( +6 for status, length and ctl byte )
and the status word ( set to zeros ) */
#ifdef USE_32_BIT
- SMC_outl ((length + 6) << 16, LAN91C96_DATA_HIGH);
+ SMC_outl(dev, (length + 6) << 16, LAN91C96_DATA_HIGH);
#else
- SMC_outw (0, LAN91C96_DATA_HIGH);
+ SMC_outw(dev, 0, LAN91C96_DATA_HIGH);
/* send the packet length ( +6 for status words, length, and ctl */
- SMC_outw ((length + 6), LAN91C96_DATA_HIGH);
+ SMC_outw(dev, (length + 6), LAN91C96_DATA_HIGH);
#endif /* USE_32_BIT */
/* send the actual data
* almost as much time as is saved?
*/
#ifdef USE_32_BIT
- SMC_outsl (LAN91C96_DATA_HIGH, buf, length >> 2);
+ SMC_outsl(dev, LAN91C96_DATA_HIGH, buf, length >> 2);
if (length & 0x2)
- SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))),
+ SMC_outw(dev, *((word *) (buf + (length & 0xFFFFFFFC))),
LAN91C96_DATA_HIGH);
#else
- SMC_outsw (LAN91C96_DATA_HIGH, buf, (length) >> 1);
+ SMC_outsw(dev, LAN91C96_DATA_HIGH, buf, (length) >> 1);
#endif /* USE_32_BIT */
/* Send the last byte, if there is one. */
if ((length & 1) == 0) {
- SMC_outw (0, LAN91C96_DATA_HIGH);
+ SMC_outw(dev, 0, LAN91C96_DATA_HIGH);
} else {
- SMC_outw (buf[length - 1] | 0x2000, LAN91C96_DATA_HIGH);
+ SMC_outw(dev, buf[length - 1] | 0x2000, LAN91C96_DATA_HIGH);
}
/* and let the chipset deal with it */
- SMC_outw (LAN91C96_MMUCR_ENQUEUE, LAN91C96_MMU);
+ SMC_outw(dev, LAN91C96_MMUCR_ENQUEUE, LAN91C96_MMU);
/* poll for TX INT */
- if (poll4int (LAN91C96_MSK_TX_INT, SMC_TX_TIMEOUT)) {
+ if (poll4int (dev, LAN91C96_MSK_TX_INT, SMC_TX_TIMEOUT)) {
/* sending failed */
- PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
+ PRINTK2("%s: TX timeout, sending failed...\n", dev->name);
/* release packet */
- SMC_outw (LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
+ SMC_outw(dev, LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
/* wait for MMU getting ready (low) */
- while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) {
+ while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
udelay (10);
- }
- PRINTK2 ("MMU ready\n");
+ PRINTK2("MMU ready\n");
return 0;
} else {
/* ack. int */
- SMC_outw (LAN91C96_IST_TX_INT, LAN91C96_INT_STATS);
+ SMC_outw(dev, LAN91C96_IST_TX_INT, LAN91C96_INT_STATS);
- PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, length);
+ PRINTK2("%s: Sent packet of length %d \n", dev->name, length);
/* release packet */
- SMC_outw (LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
+ SMC_outw(dev, LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
/* wait for MMU getting ready (low) */
- while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) {
+ while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
udelay (10);
- }
PRINTK2 ("MMU ready\n");
}
return length;
}
-/*-------------------------------------------------------------------------
- * smc_destructor( struct net_device * dev )
- * Input parameters:
- * dev, pointer to the device structure
- *
- * Output:
- * None.
- *--------------------------------------------------------------------------
- */
-void smc_destructor ()
-{
- PRINTK2 (CARDNAME ":smc_destructor\n");
-}
-
/*
* Open and Initialize the board
* Set up everything, reset the card, etc ..
*
*/
-static int smc_open (bd_t *bd)
+static int smc_open(bd_t *bd, struct eth_device *dev)
{
int i, err; /* used to set hw ethernet address */
- PRINTK2 ("%s:smc_open\n", SMC_DEV_NAME);
+ PRINTK2("%s:smc_open\n", dev->name);
/* reset the hardware */
- smc_reset ();
- smc_enable ();
-
- SMC_SELECT_BANK (1);
+ smc_reset(dev);
+ smc_enable(dev);
- err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */
+ SMC_SELECT_BANK(dev, 1);
+ /* set smc_mac_addr, and sync it with u-boot globals */
+ err = smc_get_ethaddr(bd, dev);
if (err < 0)
return -1;
#ifdef USE_32_BIT
address = smc_mac_addr[i + 1] << 8;
address |= smc_mac_addr[i];
- SMC_outw (address, LAN91C96_IA0 + i);
+ SMC_outw(dev, address, LAN91C96_IA0 + i);
}
#else
for (i = 0; i < 6; i++)
- SMC_outb (smc_mac_addr[i], LAN91C96_IA0 + i);
+ SMC_outb(dev, smc_mac_addr[i], LAN91C96_IA0 + i);
#endif
return 0;
}
* o otherwise, read in the packet
*-------------------------------------------------------------
*/
-static int smc_rcv ()
+static int smc_rcv(struct eth_device *dev)
{
int packet_number;
word status;
#endif
- SMC_SELECT_BANK (2);
- packet_number = SMC_inw (LAN91C96_FIFO);
+ SMC_SELECT_BANK(dev, 2);
+ packet_number = SMC_inw(dev, LAN91C96_FIFO);
if (packet_number & LAN91C96_FIFO_RXEMPTY) {
return 0;
}
- PRINTK3 ("%s:smc_rcv\n", SMC_DEV_NAME);
+ PRINTK3("%s:smc_rcv\n", dev->name);
/* start reading from the start of the packet */
- SMC_outw (LAN91C96_PTR_READ | LAN91C96_PTR_RCV |
+ SMC_outw(dev, LAN91C96_PTR_READ | LAN91C96_PTR_RCV |
LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER);
/* First two words are status and packet_length */
#ifdef USE_32_BIT
- stat_len = SMC_inl (LAN91C96_DATA_HIGH);
+ stat_len = SMC_inl(dev, LAN91C96_DATA_HIGH);
status = stat_len & 0xffff;
packet_length = stat_len >> 16;
#else
- status = SMC_inw (LAN91C96_DATA_HIGH);
- packet_length = SMC_inw (LAN91C96_DATA_HIGH);
+ status = SMC_inw(dev, LAN91C96_DATA_HIGH);
+ packet_length = SMC_inw(dev, LAN91C96_DATA_HIGH);
#endif
packet_length &= 0x07ff; /* mask off top bits */
to send the DWORDs or the bytes first, or some
mixture. A mixture might improve already slow PIO
performance */
- SMC_insl (LAN91C96_DATA_HIGH, NetRxPackets[0], packet_length >> 2);
+ SMC_insl(dev, LAN91C96_DATA_HIGH, NetRxPackets[0],
+ packet_length >> 2);
/* read the left over bytes */
if (packet_length & 3) {
int i;
byte *tail = (byte *) (NetRxPackets[0] + (packet_length & ~3));
- dword leftover = SMC_inl (LAN91C96_DATA_HIGH);
+ dword leftover = SMC_inl(dev, LAN91C96_DATA_HIGH);
for (i = 0; i < (packet_length & 3); i++)
*tail++ = (byte) (leftover >> (8 * i)) & 0xff;
#else
PRINTK3 (" Reading %d words and %d byte(s) \n",
(packet_length >> 1), packet_length & 1);
- SMC_insw (LAN91C96_DATA_HIGH, NetRxPackets[0], packet_length >> 1);
+ SMC_insw(dev, LAN91C96_DATA_HIGH, NetRxPackets[0],
+ packet_length >> 1);
#endif /* USE_32_BIT */
#if SMC_DEBUG > 2
printf ("Receiving Packet\n");
- print_packet (NetRxPackets[0], packet_length);
+ print_packet((byte *)NetRxPackets[0], packet_length);
#endif
} else {
/* error ... */
is_error = 1;
}
- while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
+ while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
udelay (1); /* Wait until not busy */
/* error or good, tell the card to get rid of this packet */
- SMC_outw (LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU);
+ SMC_outw(dev, LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU);
- while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
+ while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
udelay (1); /* Wait until not busy */
if (!is_error) {
* an 'ifconfig ethX down'
*
-----------------------------------------------------*/
-static int smc_close ()
+static int smc_close(struct eth_device *dev)
{
- PRINTK2 ("%s:smc_close\n", SMC_DEV_NAME);
+ PRINTK2("%s:smc_close\n", dev->name);
/* clear everything */
- smc_shutdown ();
+ smc_shutdown(dev);
return 0;
}
#if SMC_DEBUG > 2
-static void print_packet (byte * buf, int length)
+static void print_packet(byte *buf, int length)
{
#if 0
int i;
}
#endif /* SMC_DEBUG > 2 */
-int eth_init (bd_t * bd)
-{
- return (smc_open(bd));
-}
-
-void eth_halt ()
+static int lan91c96_init(struct eth_device *dev, bd_t *bd)
{
- smc_close ();
+ return smc_open(bd, dev);
}
-int eth_rx ()
+static void lan91c96_halt(struct eth_device *dev)
{
- return smc_rcv ();
+ smc_close(dev);
}
-int eth_send (volatile void *packet, int length)
+static int lan91c96_recv(struct eth_device *dev)
{
- return smc_send_packet (packet, length);
+ return smc_rcv(dev);
}
-
-#if 0
-/*-------------------------------------------------------------------------
- * smc_hw_init()
- *
- * Function:
- * Reset and enable the device, check if the I/O space location
- * is correct
- *
- * Input parameters:
- * None
- *
- * Output:
- * 0 --> success
- * 1 --> error
- *--------------------------------------------------------------------------
- */
-static int smc_hw_init ()
+static int lan91c96_send(struct eth_device *dev, volatile void *packet,
+ int length)
{
- unsigned short status_test;
-
- /* The attribute register of the LAN91C96 is located at address
- 0x0e000000 on the lubbock platform */
- volatile unsigned *attaddr = (unsigned *) (0x0e000000);
-
- /* first reset, then enable the device. Sequence is critical */
- attaddr[LAN91C96_ECOR] |= LAN91C96_ECOR_SRESET;
- udelay (100);
- attaddr[LAN91C96_ECOR] &= ~LAN91C96_ECOR_SRESET;
- attaddr[LAN91C96_ECOR] |= LAN91C96_ECOR_ENABLE;
-
- /* force 16-bit mode */
- attaddr[LAN91C96_ECSR] &= ~LAN91C96_ECSR_IOIS8;
- udelay (100);
-
- /* check if the I/O address is correct, the upper byte of the
- bank select register should read 0x33 */
-
- status_test = SMC_inw (LAN91C96_BANK_SELECT);
- if ((status_test & 0xFF00) != 0x3300) {
- printf ("Failed to initialize ethernetchip\n");
- return 1;
- }
- return 0;
+ return smc_send_packet(dev, packet, length);
}
-#endif /* 0 */
-/* smc_get_ethaddr (bd_t * bd)
+/* smc_get_ethaddr
*
* This checks both the environment and the ROM for an ethernet address. If
* found, the environment takes precedence.
*/
-int smc_get_ethaddr (bd_t * bd)
+static int smc_get_ethaddr(bd_t *bd, struct eth_device *dev)
{
uchar v_mac[6];
if (!eth_getenv_enetaddr("ethaddr", v_mac)) {
/* get ROM mac value if any */
- if (!get_rom_mac(v_mac)) {
+ if (!get_rom_mac(dev, v_mac)) {
printf("\n*** ERROR: ethaddr is NOT set !!\n");
return -1;
}
* Note, this has omly been tested for the OMAP730 P2.
*/
-int get_rom_mac (unsigned char *v_rom_mac)
+static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac)
{
#ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */
char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };
return (1);
#else
int i;
- SMC_SELECT_BANK (1);
+ SMC_SELECT_BANK(dev, 1);
for (i=0; i<6; i++)
{
- v_rom_mac[i] = SMC_inb (LAN91C96_IA0 + i);
+ v_rom_mac[i] = SMC_inb(dev, LAN91C96_IA0 + i);
}
return (1);
#endif
}
+
+/* Structure to detect the device IDs */
+struct id_type {
+ u8 id;
+ char *name;
+};
+static struct id_type supported_chips[] = {
+ {0, ""}, /* Dummy entry to prevent id check failure */
+ {9, "LAN91C110"},
+ {8, "LAN91C100FD"},
+ {7, "LAN91C100"},
+ {5, "LAN91C95"},
+ {4, "LAN91C94/LAN91C96"},
+ {3, "LAN91C90/LAN91C92"},
+};
+/* lan91c96_detect_chip
+ * See:
+ * http://www.embeddedsys.com/subpages/resources/images/documents/LAN91C96_datasheet.pdf
+ * page 71 - that is the closest we get to detect this device
+ */
+static int lan91c96_detect_chip(struct eth_device *dev)
+{
+ u8 chip_id;
+ int r;
+ SMC_SELECT_BANK(dev, 3);
+ chip_id = SMC_inw(dev, 0xA) & LAN91C96_REV_REVID;
+ SMC_SELECT_BANK(dev, 0);
+ for (r = 0; r < sizeof(supported_chips) / sizeof(struct id_type); r++)
+ if (chip_id == supported_chips[r].id)
+ return r;
+ return 0;
+}
+
+int lan91c96_initialize(u8 dev_num, int base_addr)
+{
+ struct eth_device *dev;
+ int r = 0;
+
+ dev = malloc(sizeof(*dev));
+ if (!dev) {
+ free(dev);
+ return 0;
+ }
+ memset(dev, 0, sizeof(*dev));
+
+ dev->iobase = base_addr;
+
+ /* Try to detect chip. Will fail if not present. */
+ r = lan91c96_detect_chip(dev);
+ if (!r) {
+ free(dev);
+ return 0;
+ }
+ get_rom_mac(dev, dev->enetaddr);
+
+ dev->init = lan91c96_init;
+ dev->halt = lan91c96_halt;
+ dev->send = lan91c96_send;
+ dev->recv = lan91c96_recv;
+ sprintf(dev->name, "%s-%hu", supported_chips[r].name, dev_num);
+
+ eth_register(dev);
+ return 0;
+}
#include <asm/io.h>
#include <config.h>
-/*
- * This function may be called by the board specific initialisation code
- * in order to override the default mac address.
- */
-
-void smc_set_mac_addr(const unsigned char *addr);
-
-
/* I want some simple types */
typedef unsigned char byte;
#define SMC_IO_SHIFT 0
#endif
-#define SMCREG(r) (SMC_BASE_ADDRESS+((r)<<SMC_IO_SHIFT))
+#define SMCREG(edev, r) ((edev)->iobase+((r)<<SMC_IO_SHIFT))
-#define SMC_inl(r) (*((volatile dword *)SMCREG(r)))
-#define SMC_inw(r) (*((volatile word *)SMCREG(r)))
-#define SMC_inb(p) ({ \
+#define SMC_inl(edev, r) (*((volatile dword *)SMCREG(edev, r)))
+#define SMC_inw(edev, r) (*((volatile word *)SMCREG(edev, r)))
+#define SMC_inb(edev, p) ({ \
unsigned int __p = p; \
- unsigned int __v = SMC_inw(__p & ~1); \
+ unsigned int __v = SMC_inw(edev, __p & ~1); \
if (__p & 1) __v >>= 8; \
else __v &= 0xff; \
__v; })
-#define SMC_outl(d,r) (*((volatile dword *)SMCREG(r)) = d)
-#define SMC_outw(d,r) (*((volatile word *)SMCREG(r)) = d)
-#define SMC_outb(d,r) ({ word __d = (byte)(d); \
- word __w = SMC_inw((r)&~1); \
+#define SMC_outl(edev, d, r) (*((volatile dword *)SMCREG(edev, r)) = d)
+#define SMC_outw(edev, d, r) (*((volatile word *)SMCREG(edev, r)) = d)
+#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \
+ word __w = SMC_inw(edev, (r)&~1); \
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
__w |= ((r)&1) ? __d<<8 : __d; \
- SMC_outw(__w,(r)&~1); \
+ SMC_outw(edev, __w, (r)&~1); \
})
-#define SMC_outsl(r,b,l) ({ int __i; \
+#define SMC_outsl(edev, r, b, l) ({ int __i; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
- SMC_outl( *(__b2 + __i), r ); \
+ SMC_outl(edev, *(__b2 + __i),\
+ r); \
} \
})
-#define SMC_outsw(r,b,l) ({ int __i; \
+#define SMC_outsw(edev, r, b, l) ({ int __i; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
- SMC_outw( *(__b2 + __i), r ); \
+ SMC_outw(edev, *(__b2 + __i),\
+ r); \
} \
})
-#define SMC_insl(r,b,l) ({ int __i ; \
+#define SMC_insl(edev, r, b, l) ({ int __i ; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inl(r); \
- SMC_inl(0); \
+ *(__b2 + __i) = SMC_inl(edev,\
+ r); \
+ SMC_inl(edev, 0); \
}; \
})
-#define SMC_insw(r,b,l) ({ int __i ; \
+#define SMC_insw(edev, r, b, l) ({ int __i ; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inw(r); \
- SMC_inw(0); \
+ *(__b2 + __i) = SMC_inw(edev,\
+ r); \
+ SMC_inw(edev, 0); \
}; \
})
-#define SMC_insb(r,b,l) ({ int __i ; \
+#define SMC_insb(edev, r, b, l) ({ int __i ; \
byte *__b2; \
__b2 = (byte *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inb(r); \
- SMC_inb(0); \
+ *(__b2 + __i) = SMC_inb(edev,\
+ r); \
+ SMC_inb(edev, 0); \
}; \
})
* We have only 16 Bit PCMCIA access on Socket 0
*/
-#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
-#define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)
+#define SMC_inw(edev, r) (*((volatile word *)((edev)->iobase+(r))))
+#define SMC_inb(edev, r) (((r)&1) ? SMC_inw(edev, (r)&~1)>>8 :\
+ SMC_inw(edev, r)&0xFF)
-#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
-#define SMC_outb(d,r) ({ word __d = (byte)(d); \
- word __w = SMC_inw((r)&~1); \
+#define SMC_outw(edev, d, r) (*((volatile word *)((edev)->iobase+(r))) = d)
+#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \
+ word __w = SMC_inw(edev, (r)&~1); \
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
__w |= ((r)&1) ? __d<<8 : __d; \
- SMC_outw(__w,(r)&~1); \
+ SMC_outw(edev, __w, (r)&~1); \
})
-#if 0
-#define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l))
-#else
-#define SMC_outsw(r,b,l) ({ int __i; \
+#define SMC_outsw(edev, r, b, l) ({ int __i; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
- SMC_outw( *(__b2 + __i), r); \
+ SMC_outw(edev, *(__b2 + __i),\
+ r); \
} \
})
-#endif
-#if 0
-#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l))
-#else
-#define SMC_insw(r,b,l) ({ int __i ; \
+#define SMC_insw(edev, r, b, l) ({ int __i ; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inw(r); \
- SMC_inw(0); \
+ *(__b2 + __i) = SMC_inw(edev,\
+ r); \
+ SMC_inw(edev, 0); \
}; \
})
-#endif
#endif
/* select a register bank, 0 to 3 */
-#define SMC_SELECT_BANK(x) { SMC_outw( x, LAN91C96_BANK_SELECT ); }
+#define SMC_SELECT_BANK(edev, x) { SMC_outw(edev, x, LAN91C96_BANK_SELECT); }
/* this enables an interrupt in the interrupt mask register */
-#define SMC_ENABLE_INT(x) {\
+#define SMC_ENABLE_INT(edev, x) {\
unsigned char mask;\
- SMC_SELECT_BANK(2);\
- mask = SMC_inb( LAN91C96_INT_MASK );\
+ SMC_SELECT_BANK(edev, 2);\
+ mask = SMC_inb(edev, LAN91C96_INT_MASK);\
mask |= (x);\
- SMC_outb( mask, LAN91C96_INT_MASK ); \
+ SMC_outb(edev, mask, LAN91C96_INT_MASK); \
}
/* this disables an interrupt from the interrupt mask register */
-#define SMC_DISABLE_INT(x) {\
+#define SMC_DISABLE_INT(edev, x) {\
unsigned char mask;\
- SMC_SELECT_BANK(2);\
- mask = SMC_inb( LAN91C96_INT_MASK );\
+ SMC_SELECT_BANK(edev, 2);\
+ mask = SMC_inb(edev, LAN91C96_INT_MASK);\
mask &= ~(x);\
- SMC_outb( mask, LAN91C96_INT_MASK ); \
+ SMC_outb(edev, mask, LAN91C96_INT_MASK); \
}
/*----------------------------------------------------------------------
#ifdef CONFIG_PXA250
#ifdef CONFIG_XSENGINE
-#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1))))
-#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r<<1))))
+#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1))))
+#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1))))
#define SMC_inb(a,p) ({ \
- unsigned int __p = (unsigned int)((a)->iobase + (p<<1)); \
+ unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \
unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
if (__p & 2) __v >>= 8; \
else __v &= 0xff; \
__v; })
#define SMC_inb(a,p) ({ \
unsigned int ___v = SMC_inw((a),(p) & ~1); \
- if (p & 1) ___v >>= 8; \
+ if ((p) & 1) ___v >>= 8; \
else ___v &= 0xff; \
___v; })
#else
#define mdelay(n) udelay((n)*1000)
-static void smx911x_handle_mac_address(struct eth_device *dev)
+static void smc911x_handle_mac_address(struct eth_device *dev)
{
unsigned long addrh, addrl;
uchar *m = dev->enetaddr;
/* Configure the PHY, initialize the link state */
smc911x_phy_configure(dev);
- smx911x_handle_mac_address(dev);
+ smc911x_handle_mac_address(dev);
/* Turn on Tx + Rx */
smc911x_enable(dev);
dev = malloc(sizeof(*dev));
if (!dev) {
free(dev);
- return 0;
+ return -1;
}
memset(dev, 0, sizeof(*dev));
}
eth_register(dev);
- return 0;
+ return 1;
}
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
- * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004-2009 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* author Andy Fleming
*
#ifdef CONFIG_MPC85XX_FEC
{
.regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
- .miiregs = (tsec_t *)(TSEC_BASE_ADDR),
+ .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR),
.devname = CONFIG_MPC85XX_FEC_NAME,
.phyaddr = FEC_PHY_ADDR,
.flags = FEC_FLAGS
privlist[num_tsecs++] = priv;
priv->regs = tsec_info->regs;
priv->phyregs = tsec_info->miiregs;
+ priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
priv->phyaddr = tsec_info->phyaddr;
priv->flags = tsec_info->flags;
}
/* Writes the given phy's reg with value, using the specified MDIO regs */
-static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr,
+static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr,
uint reg, uint value)
{
int timeout = 1000000;
* notvalid bit cleared), and the bus to cease activity (miimind
* busy bit cleared), and then returns the value
*/
-uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum)
+uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, uint phyid, uint regnum)
{
uint value;
{
/* Access TBI PHY registers at given TSEC register offset as opposed to the
* register offset used for external PHY accesses */
- tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA,
+ tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA,
TBIANA_SETTINGS);
- tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON,
+ tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON,
TBICON_CLK_SELECT);
- tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR,
+ tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR,
TBICR_SETTINGS);
}
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct phy_info *curphy;
- volatile tsec_t *phyregs = priv->phyregs;
volatile tsec_t *regs = priv->regs;
/* Assign a Physical address to the TBI */
regs->tbipa = CONFIG_SYS_TBIPA_VALUE;
- phyregs->tbipa = CONFIG_SYS_TBIPA_VALUE;
asm("sync");
/* Reset MII (due to new addresses) */
uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
{
uint phyid;
- volatile tsec_t *regbase = priv->phyregs;
+ volatile tsec_mdio_t *regbase = priv->phyregs;
int timeout = 1000000;
for (phyid = 0; phyid < 4; phyid++) {
{
int i;
uint result;
- volatile tsec_t *phyregs = priv->phyregs;
+ volatile tsec_mdio_t *phyregs = priv->phyregs;
phyregs->miimcfg = MIIMCFG_RESET;
#define FSL_PCI_PBFR 0x44
#define FSL_PCIE_CAP_ID 0x4c
#define FSL_PCIE_CFG_RDY 0x4b0
+#define FSL_PROG_IF_AGENT 0x1
void pciauto_prescan_setup_bridge(struct pci_controller *hose,
pci_dev_t dev, int sub_bus);
out_be32(&pi->piwar, flag | sz);
}
+int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
+
+ pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
+
+ return fsl_is_pci_agent(hose);
+}
+
static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
u64 out_lo, u8 pcie_cap,
volatile pit_t *pi)
}
}
+int fsl_is_pci_agent(struct pci_controller *hose)
+{
+ u8 prog_if;
+ pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
+
+ pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
+
+ return (prog_if == FSL_PROG_IF_AGENT);
+}
+
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
- struct pci_controller *hose, int busno, int pcie_ep)
+ struct pci_controller *hose, int busno)
{
volatile ccsr_fsl_pci_t *pci;
struct pci_region *r;
pci = (ccsr_fsl_pci_t *) pci_info->regs;
- if (pcie_ep) {
- volatile pit_t *pi = &pci->pit[2];
-
- pci_setup_indirect(hose, (u32)&pci->cfg_addr,
- (u32)&pci->cfg_data);
- out_be32(&pi->pitar, 0);
- out_be32(&pi->piwbar, 0);
- out_be32(&pi->piwar, PIWAR_EN | PIWAR_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_IWS_4K);
-
- fsl_pci_config_unlock(hose);
- return 0;
- }
-
/* on non-PCIe controllers we don't have pme_msg_det so this code
* should do nothing since the read will return 0
*/
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
+ if (fsl_is_pci_agent(hose)) {
+ fsl_pci_config_unlock(hose);
+ hose->last_busno = hose->first_busno;
+ }
+
printf(" PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
hose->first_busno, hose->last_busno);
COBJS-$(CONFIG_RTC_DS164x) += ds164x.o
COBJS-$(CONFIG_RTC_DS174x) += ds174x.o
COBJS-$(CONFIG_RTC_DS3231) += ds3231.o
+COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o
COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o
COBJS-$(CONFIG_RTC_M41T11) += m41t11.o
COBJS-$(CONFIG_RTC_M41T60) += m41t60.o
--- /dev/null
+/*
+ * Faraday FTRTC010 Real Time Clock
+ *
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <rtc.h>
+#include <asm/io.h>
+
+struct ftrtc010 {
+ unsigned int sec; /* 0x00 */
+ unsigned int min; /* 0x04 */
+ unsigned int hour; /* 0x08 */
+ unsigned int day; /* 0x0c */
+ unsigned int alarm_sec; /* 0x10 */
+ unsigned int alarm_min; /* 0x14 */
+ unsigned int alarm_hour; /* 0x18 */
+ unsigned int record; /* 0x1c */
+ unsigned int cr; /* 0x20 */
+};
+
+/*
+ * RTC Control Register
+ */
+#define FTRTC010_CR_ENABLE (1 << 0)
+#define FTRTC010_CR_INTERRUPT_SEC (1 << 1) /* per second irq */
+#define FTRTC010_CR_INTERRUPT_MIN (1 << 2) /* per minute irq */
+#define FTRTC010_CR_INTERRUPT_HR (1 << 3) /* per hour irq */
+#define FTRTC010_CR_INTERRUPT_DAY (1 << 4) /* per day irq */
+
+static struct ftrtc010 *rtc = (struct ftrtc010 *)CONFIG_FTRTC010_BASE;
+
+static void ftrtc010_enable(void)
+{
+ writel(FTRTC010_CR_ENABLE, &rtc->cr);
+}
+
+/*
+ * return current time in seconds
+ */
+static unsigned long ftrtc010_time(void)
+{
+ unsigned long day;
+ unsigned long hour;
+ unsigned long minute;
+ unsigned long second;
+ unsigned long second2;
+
+ do {
+ second = readl(&rtc->sec);
+ day = readl(&rtc->day);
+ hour = readl(&rtc->hour);
+ minute = readl(&rtc->min);
+ second2 = readl(&rtc->sec);
+ } while (second != second2);
+
+ return day * 24 * 60 * 60 + hour * 60 * 60 + minute * 60 + second;
+}
+
+/*
+ * Get the current time from the RTC
+ */
+
+int rtc_get(struct rtc_time *tmp)
+{
+ unsigned long now;
+
+ debug("%s(): record register: %x\n",
+ __func__, readl(&rtc->record));
+
+ now = ftrtc010_time() + readl(&rtc->record);
+
+ to_tm(now, tmp);
+
+ return 0;
+}
+
+/*
+ * Set the RTC
+ */
+int rtc_set(struct rtc_time *tmp)
+{
+ unsigned long new;
+ unsigned long now;
+
+ debug("%s(): DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ __func__,
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+ new = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour,
+ tmp->tm_min, tmp->tm_sec);
+
+ now = ftrtc010_time();
+
+ debug("%s(): write %lx to record register\n", __func__, new - now);
+
+ writel(new - now, &rtc->record);
+
+ return 0;
+}
+
+void rtc_reset(void)
+{
+ debug("%s()\n", __func__);
+ ftrtc010_enable();
+}
val = val & 0x3F;/*turn off freq test keep calibration*/
i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1);
}
-
-int rtc_store(int addr, unsigned char* data, int size)
-{
- /*don't let things wrap onto the time on a write*/
- if( (addr+size) >= M41T11_STORAGE_SZ )
- return 1;
- return i2c_write( CONFIG_SYS_I2C_RTC_ADDR, REG_CNT+addr, 1, data, size );
-}
-
-int rtc_recall(int addr, unsigned char* data, int size)
-{
- return i2c_read( CONFIG_SYS_I2C_RTC_ADDR, REG_CNT+addr, 1, data, size );
-}
-
#endif
* Could not be tested as the reset pin is not wired on
* the sbc35-ag20 board
*/
- return 0;
}
spi_release_bus(slave);
- return -1;
+ return 0;
}
void rtc_reset(void)
#include <usb/mpc8xx_udc.h>
#elif defined(CONFIG_OMAP1510)
#include <usb/omap1510_udc.h>
+#elif defined(CONFIG_MUSB_UDC)
+#include <usb/musb_udc.h>
#elif defined(CONFIG_PXA27X)
#include <usb/pxa27x_udc.h>
#endif
#include <dataflash.h>
#define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
-#define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 0: NPCS0%1101 */
+#define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 1: NPCS1%1101 */
+#define AT91_SPI_PCS2_DATAFLASH_CARD 0xB /* Chip Select 2: NPCS2%1011 */
#define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
void AT91F_SpiInit(void)
((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
AT91_BASE_SPI + AT91_SPI_CSR(1));
#endif
-
+#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2
+ /* Configure CS2 */
+ writel(AT91_SPI_NCPHA |
+ (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
+ (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
+ ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
+ AT91_BASE_SPI + AT91_SPI_CSR(2));
+#endif
#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
/* Configure CS3 */
writel(AT91_SPI_NCPHA |
writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
AT91_BASE_SPI + AT91_SPI_MR);
break;
+ case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */
+ mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
+ mode &= 0xFFF0FFFF;
+ writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
+ AT91_BASE_SPI + AT91_SPI_MR);
+ break;
case 3:
mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
mode &= 0xFFF0FFFF;
# echi
COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o
COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
+COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
* UE_DIR_IN | EHCI_INTR_ENDPT
*/
3, /* bmAttributes: UE_INTERRUPT */
- 8, 0, /* wMaxPacketSize */
+ 8, /* wMaxPacketSize */
255 /* bInterval */
},
};
* root
*/
wait_ms(50);
+ /* terminate the reset */
+ ehci_writel(status_reg, reg & ~EHCI_PS_PR);
+ wait_ms(2);
portreset |= 1 << le16_to_cpu(req->index);
}
break;
--- /dev/null
+/*
+ * (C) Copyright 2010, Chris Zhang <chris@seamicro.com>
+ *
+ * Author: Chris Zhang <chris@seamicro.com>
+ * This code is based on ehci freescale driver
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <usb.h>
+
+#include "ehci.h"
+#include "ehci-core.h"
+
+/*
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(void)
+{
+ hccr = (struct ehci_hccr *)(CONFIG_SYS_PPC4XX_USB_ADDR);
+ hcor = (struct ehci_hcor *)((uint32_t) hccr +
+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ usb_dev_init();
+ return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the the EHCI host controller.
+ */
+int ehci_hcd_stop(void)
+{
+ return 0;
+}
LIB := $(obj)libusb_musb.a
COBJS-$(CONFIG_MUSB_HCD) += musb_hcd.o musb_core.o
+COBJS-$(CONFIG_MUSB_UDC) += musb_udc.o musb_core.o
+COBJS-$(CONFIG_USB_BLACKFIN) += blackfin_usb.o
COBJS-$(CONFIG_USB_DAVINCI) += davinci.o
+COBJS-$(CONFIG_USB_OMAP3) += omap3.o
+COBJS-$(CONFIG_USB_DA8XX) += da8xx.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * Blackfin MUSB HCD (Host Controller Driver) for u-boot
+ *
+ * Copyright (c) 2008-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+
+#include <usb.h>
+
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/usb.h>
+
+#include "musb_core.h"
+
+/* MUSB platform configuration */
+struct musb_config musb_cfg = {
+ .regs = (struct musb_regs *)USB_FADDR,
+ .timeout = 0x3FFFFFF,
+ .musb_speed = 0,
+};
+
+/*
+ * This function read or write data to endpoint fifo
+ * Blackfin use DMA polling method to avoid buffer alignment issues
+ *
+ * ep - Endpoint number
+ * length - Number of bytes to write to FIFO
+ * fifo_data - Pointer to data buffer to be read/write
+ * is_write - Flag for read or write
+ */
+void rw_fifo(u8 ep, u32 length, void *fifo_data, int is_write)
+{
+ struct bfin_musb_dma_regs *regs;
+ u32 val = (u32)fifo_data;
+
+ blackfin_dcache_flush_invalidate_range(fifo_data, fifo_data + length);
+
+ regs = (void *)USB_DMA_INTERRUPT;
+ regs += ep;
+
+ /* Setup DMA address register */
+ bfin_write16(®s->addr_low, val);
+ SSYNC();
+
+ bfin_write16(®s->addr_high, val >> 16);
+ SSYNC();
+
+ /* Setup DMA count register */
+ bfin_write16(®s->count_low, length);
+ bfin_write16(®s->count_high, 0);
+ SSYNC();
+
+ /* Enable the DMA */
+ val = (ep << 4) | DMA_ENA | INT_ENA;
+ if (is_write)
+ val |= DIRECTION;
+ bfin_write16(®s->control, val);
+ SSYNC();
+
+ /* Wait for compelete */
+ while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << ep)))
+ continue;
+
+ /* acknowledge dma interrupt */
+ bfin_write_USB_DMA_INTERRUPT(1 << ep);
+ SSYNC();
+
+ /* Reset DMA */
+ bfin_write16(®s->control, 0);
+ SSYNC();
+}
+
+void write_fifo(u8 ep, u32 length, void *fifo_data)
+{
+ rw_fifo(ep, length, fifo_data, 1);
+}
+
+void read_fifo(u8 ep, u32 length, void *fifo_data)
+{
+ rw_fifo(ep, length, fifo_data, 0);
+}
+
+
+/*
+ * CPU and board-specific MUSB initializations. Aliased function
+ * signals caller to move on.
+ */
+static void __def_musb_init(void)
+{
+}
+void board_musb_init(void) __attribute__((weak, alias("__def_musb_init")));
+
+int musb_platform_init(void)
+{
+ /* board specific initialization */
+ board_musb_init();
+
+ if (ANOMALY_05000346) {
+ bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
+ SSYNC();
+ }
+
+ if (ANOMALY_05000347) {
+ bfin_write_USB_APHY_CNTRL(0x0);
+ SSYNC();
+ }
+
+ /* Configure PLL oscillator register */
+ bfin_write_USB_PLLOSC_CTRL(0x30a8);
+ SSYNC();
+
+ bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
+ SSYNC();
+
+ bfin_write_USB_EP_NI0_RXMAXP(64);
+ SSYNC();
+
+ bfin_write_USB_EP_NI0_TXMAXP(64);
+ SSYNC();
+
+ /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
+ bfin_write_USB_GLOBINTR(0x7);
+ SSYNC();
+
+ bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
+ EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
+ EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
+ EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
+ EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
+ SSYNC();
+
+ return 0;
+}
+
+/*
+ * This function performs Blackfin platform specific deinitialization for usb.
+*/
+void musb_platform_deinit(void)
+{
+}
--- /dev/null
+/*
+ * Blackfin MUSB HCD (Host Controller Driver) for u-boot
+ *
+ * Copyright (c) 2008-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BLACKFIN_USB_H__
+#define __BLACKFIN_USB_H__
+
+#include <linux/types.h>
+
+/* Every register is 32bit aligned, but only 16bits in size */
+#define ureg(name) u16 name; u16 __pad_##name;
+
+#define musb_regs musb_regs
+struct musb_regs {
+ /* common registers */
+ ureg(faddr)
+ ureg(power)
+ ureg(intrtx)
+ ureg(intrrx)
+ ureg(intrtxe)
+ ureg(intrrxe)
+ ureg(intrusb)
+ ureg(intrusbe)
+ ureg(frame)
+ ureg(index)
+ ureg(testmode)
+ ureg(globintr)
+ ureg(global_ctl)
+ u32 reserved0[3];
+ /* indexed registers */
+ ureg(txmaxp)
+ ureg(txcsr)
+ ureg(rxmaxp)
+ ureg(rxcsr)
+ ureg(rxcount)
+ ureg(txtype)
+ ureg(txinterval)
+ ureg(rxtype)
+ ureg(rxinterval)
+ u32 reserved1;
+ ureg(txcount)
+ u32 reserved2[5];
+ /* fifo */
+ u16 fifox[32];
+ /* OTG, dynamic FIFO, version & vendor registers */
+ u32 reserved3[16];
+ ureg(devctl)
+ ureg(vbus_irq)
+ ureg(vbus_mask)
+ u32 reserved4[15];
+ ureg(linkinfo)
+ ureg(vplen)
+ ureg(hseof1)
+ ureg(fseof1)
+ ureg(lseof1)
+ u32 reserved5[41];
+ /* target address registers */
+ struct musb_tar_regs {
+ ureg(txmaxp)
+ ureg(txcsr)
+ ureg(rxmaxp)
+ ureg(rxcsr)
+ ureg(rxcount)
+ ureg(txtype)
+ ureg(txinternal)
+ ureg(rxtype)
+ ureg(rxinternal)
+ u32 reserved6;
+ ureg(txcount)
+ u32 reserved7[5];
+ } tar[8];
+} __attribute__((packed));
+
+struct bfin_musb_dma_regs {
+ ureg(interrupt);
+ ureg(control);
+ ureg(addr_low);
+ ureg(addr_high);
+ ureg(count_low);
+ ureg(count_high);
+ ureg(pad);
+};
+
+#undef ureg
+
+/* EP5-EP7 are the only ones with 1024 byte FIFOs which BULK really needs */
+#define MUSB_BULK_EP 5
+
+/* Blackfin FIFO's are static */
+#define MUSB_NO_DYNAMIC_FIFO
+
+/* No HUB support :( */
+#define MUSB_NO_MULTIPOINT
+
+#endif
--- /dev/null
+/*
+ * da8xx.c - TI's DA8xx platform specific usb wrapper functions.
+ *
+ * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
+ *
+ * Based on drivers/usb/musb/davinci.c
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+
+#include "da8xx.h"
+
+/* MUSB platform configuration */
+struct musb_config musb_cfg = {
+ (struct musb_regs *)DA8XX_USB_OTG_CORE_BASE,
+ DA8XX_USB_OTG_TIMEOUT,
+ 0
+};
+
+/*
+ * This function enables VBUS by driving the GPIO Bank4 Pin 15 high.
+ */
+static void enable_vbus(void)
+{
+ u32 value;
+
+ /* configure GPIO bank4 pin 15 in output direction */
+ value = readl(&davinci_gpio_bank45->dir);
+ writel((value & (~DA8XX_USB_VBUS_GPIO)), &davinci_gpio_bank45->dir);
+
+ /* set GPIO bank4 pin 15 high to drive VBUS */
+ value = readl(&davinci_gpio_bank45->set_data);
+ writel((value | DA8XX_USB_VBUS_GPIO), &davinci_gpio_bank45->set_data);
+}
+
+/*
+ * Enable the usb0 phy. This initialization procedure is explained in
+ * the DA8xx USB user guide document.
+ */
+static u8 phy_on(void)
+{
+ u32 timeout;
+ u32 cfgchip2;
+
+ cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
+
+ cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN |
+ CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ);
+ cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON |
+ CFGCHIP2_REFFREQ_24MHZ;
+
+ writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
+
+ /* wait until the usb phy pll locks */
+ timeout = musb_cfg.timeout;
+ while (timeout--)
+ if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD)
+ return 1;
+
+ /* USB phy was not turned on */
+ return 0;
+}
+
+/*
+ * Disable the usb phy
+ */
+static void phy_off(void)
+{
+ u32 cfgchip2;
+
+ /*
+ * Power down the on-chip PHY.
+ */
+ cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
+ cfgchip2 &= ~CFGCHIP2_PHY_PLLON;
+ cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
+ writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
+}
+
+/*
+ * This function performs DA8xx platform specific initialization for usb0.
+ */
+int musb_platform_init(void)
+{
+ u32 revision;
+
+ /* enable psc for usb2.0 */
+ lpsc_on(33);
+
+ /* enable usb vbus */
+ enable_vbus();
+
+ /* reset the controller */
+ writel(0x1, &da8xx_usb_regs->control);
+ udelay(5000);
+
+ /* start the on-chip usb phy and its pll */
+ if (phy_on() == 0)
+ return -1;
+
+ /* Returns zero if e.g. not clocked */
+ revision = readl(&da8xx_usb_regs->revision);
+ if (revision == 0)
+ return -1;
+
+ /* Disable all interrupts */
+ writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
+ DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_set);
+ return 0;
+}
+
+/*
+ * This function performs DA8xx platform specific deinitialization for usb0.
+ */
+void musb_platform_deinit(void)
+{
+ /* Turn of the phy */
+ phy_off();
+
+ /* flush any interrupts */
+ writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
+ DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_clr);
+ writel(0, &da8xx_usb_regs->eoi);
+}
--- /dev/null
+/*
+ * da8xx.h -- TI's DA8xx platform specific usb wrapper definitions.
+ *
+ * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
+ *
+ * Based on drivers/usb/musb/davinci.h
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __DA8XX_MUSB_H__
+#define __DA8XX_MUSB_H__
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio_defs.h>
+#include "musb_core.h"
+
+/* Base address of da8xx usb0 wrapper */
+#define DA8XX_USB_OTG_BASE 0x01E00000
+
+/* Base address of da8xx musb core */
+#define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400)
+
+/* Timeout for DA8xx usb module */
+#define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF
+
+/*
+ * DA8xx platform USB wrapper register overlay.
+ */
+struct da8xx_usb_regs {
+ dv_reg revision;
+ dv_reg control;
+ dv_reg status;
+ dv_reg emulation;
+ dv_reg mode;
+ dv_reg autoreq;
+ dv_reg srpfixtime;
+ dv_reg teardown;
+ dv_reg intsrc;
+ dv_reg intsrc_set;
+ dv_reg intsrc_clr;
+ dv_reg intmsk;
+ dv_reg intmsk_set;
+ dv_reg intmsk_clr;
+ dv_reg intsrcmsk;
+ dv_reg eoi;
+ dv_reg intvector;
+ dv_reg grndis_size[4];
+};
+
+#define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE)
+
+/* DA8XX interrupt bits definitions */
+#define DA8XX_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */
+#define DA8XX_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */
+#define DA8XX_USB_TXINT_SHIFT 0
+#define DA8XX_USB_RXINT_SHIFT 8
+
+#define DA8XX_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */
+#define DA8XX_USB_TXINT_MASK \
+ (DA8XX_USB_TX_ENDPTS_MASK << DA8XX_USB_TXINT_SHIFT)
+#define DA8XX_USB_RXINT_MASK \
+ (DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT)
+
+/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
+#define CFGCHIP2_PHYCLKGD (1 << 17)
+#define CFGCHIP2_VBUSSENSE (1 << 16)
+#define CFGCHIP2_RESET (1 << 15)
+#define CFGCHIP2_OTGMODE (3 << 13)
+#define CFGCHIP2_NO_OVERRIDE (0 << 13)
+#define CFGCHIP2_FORCE_HOST (1 << 13)
+#define CFGCHIP2_FORCE_DEVICE (2 << 13)
+#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
+#define CFGCHIP2_USB1PHYCLKMUX (1 << 12)
+#define CFGCHIP2_USB2PHYCLKMUX (1 << 11)
+#define CFGCHIP2_PHYPWRDN (1 << 10)
+#define CFGCHIP2_OTGPWRDN (1 << 9)
+#define CFGCHIP2_DATPOL (1 << 8)
+#define CFGCHIP2_USB1SUSPENDM (1 << 7)
+#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */
+#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */
+#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */
+#define CFGCHIP2_REFFREQ (0xf << 0)
+#define CFGCHIP2_REFFREQ_12MHZ (1 << 0)
+#define CFGCHIP2_REFFREQ_24MHZ (2 << 0)
+#define CFGCHIP2_REFFREQ_48MHZ (3 << 0)
+
+#define DA8XX_USB_VBUS_GPIO (1 << 15)
+#endif /* __DA8XX_MUSB_H__ */
+
*/
void musb_start(void)
{
+#if defined(CONFIG_MUSB_HCD)
u8 devctl;
+#endif
/* disable all interrupts */
writew(0, &musbr->intrtxe);
#endif
}
+#ifdef MUSB_NO_DYNAMIC_FIFO
+# define config_fifo(dir, idx, addr)
+#else
+# define config_fifo(dir, idx, addr) \
+ do { \
+ writeb(idx, &musbr->dir##fifosz); \
+ writew(fifoaddr >> 3, &musbr->dir##fifoadd); \
+ } while (0)
+#endif
+
/*
* This function configures the endpoint configuration. The musb hcd or musb
* device implementation can use this function to configure the endpoints
writeb(epinfo->epnum, &musbr->index);
if (epinfo->epdir) {
/* Configure fifo size and fifo base address */
- writeb(idx, &musbr->txfifosz);
- writew(fifoaddr >> 3, &musbr->txfifoadd);
+ config_fifo(tx, idx, fifoaddr);
+
+ csr = readw(&musbr->txcsr);
#if defined(CONFIG_MUSB_HCD)
/* clear the data toggle bit */
- csr = readw(&musbr->txcsr);
writew(csr | MUSB_TXCSR_CLRDATATOG, &musbr->txcsr);
#endif
/* Flush fifo if required */
&musbr->txcsr);
} else {
/* Configure fifo size and fifo base address */
- writeb(idx, &musbr->rxfifosz);
- writew(fifoaddr >> 3, &musbr->rxfifoadd);
+ config_fifo(rx, idx, fifoaddr);
+
+ csr = readw(&musbr->rxcsr);
#if defined(CONFIG_MUSB_HCD)
/* clear the data toggle bit */
- csr = readw(&musbr->rxcsr);
writew(csr | MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr);
#endif
/* Flush fifo if required */
* length - number of bytes to write to FIFO
* fifo_data - Pointer to data buffer that contains the data to write
*/
+__attribute__((weak))
void write_fifo(u8 ep, u32 length, void *fifo_data)
{
u8 *data = (u8 *)fifo_data;
* length - number of bytes to read from FIFO
* fifo_data - pointer to data buffer into which data is read
*/
+__attribute__((weak))
void read_fifo(u8 ep, u32 length, void *fifo_data)
{
u8 *data = (u8 *)fifo_data;
#include <usb_defs.h>
#include <asm/io.h>
+#ifdef CONFIG_USB_BLACKFIN
+# include "blackfin_usb.h"
+#endif
+
#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
+/* EP0 */
+struct musb_ep0_regs {
+ u16 reserved4;
+ u16 csr0;
+ u16 reserved5;
+ u16 reserved6;
+ u16 count0;
+ u8 host_type0;
+ u8 host_naklimit0;
+ u8 reserved7;
+ u8 reserved8;
+ u8 reserved9;
+ u8 configdata;
+};
+
+/* EP 1-15 */
+struct musb_epN_regs {
+ u16 txmaxp;
+ u16 txcsr;
+ u16 rxmaxp;
+ u16 rxcsr;
+ u16 rxcount;
+ u8 txtype;
+ u8 txinterval;
+ u8 rxtype;
+ u8 rxinterval;
+ u8 reserved0;
+ u8 fifosize;
+};
+
/* Mentor USB core register overlay structure */
+#ifndef musb_regs
struct musb_regs {
/* common registers */
u8 faddr;
u8 rxhubaddr;
u8 rxhubport;
} tar[16];
-} __attribute__((aligned(32)));
+ /*
+ * end point registers
+ * ep0 elements are valid when array index is 0
+ * otherwise epN is valid
+ */
+ union musb_ep_regs {
+ struct musb_ep0_regs ep0;
+ struct musb_epN_regs epN;
+ } ep[16];
+
+} __attribute__((packed, aligned(32)));
+#endif
/*
* MUSB Register bits
extern void write_fifo(u8 ep, u32 length, void *fifo_data);
extern void read_fifo(u8 ep, u32 length, void *fifo_data);
+#if defined(CONFIG_USB_BLACKFIN)
+/* Every USB register is accessed as a 16-bit even if the value itself
+ * is only 8-bits in size. Fun stuff.
+ */
+# undef readb
+# define readb(addr) (u8)bfin_read16(addr)
+# undef writeb
+# define writeb(b, addr) bfin_write16(addr, b)
+#endif
+
#endif /* __MUSB_HDRC_DEFS_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Define MUSB_DEBUG before including this file to get debug macros */
+#ifdef MUSB_DEBUG
+
+#define MUSB_FLAGS_PRINT(v, x, y) \
+ if (((v) & MUSB_##x##_##y)) \
+ serial_printf("\t\t"#y"\n")
+
+static inline void musb_print_pwr(u8 b)
+{
+ serial_printf("\tpower 0x%2.2x\n", b);
+ MUSB_FLAGS_PRINT(b, POWER, ISOUPDATE);
+ MUSB_FLAGS_PRINT(b, POWER, SOFTCONN);
+ MUSB_FLAGS_PRINT(b, POWER, HSENAB);
+ MUSB_FLAGS_PRINT(b, POWER, HSMODE);
+ MUSB_FLAGS_PRINT(b, POWER, RESET);
+ MUSB_FLAGS_PRINT(b, POWER, RESUME);
+ MUSB_FLAGS_PRINT(b, POWER, SUSPENDM);
+ MUSB_FLAGS_PRINT(b, POWER, ENSUSPEND);
+}
+
+static inline void musb_print_csr0(u16 w)
+{
+ serial_printf("\tcsr0 0x%4.4x\n", w);
+ MUSB_FLAGS_PRINT(w, CSR0, FLUSHFIFO);
+ MUSB_FLAGS_PRINT(w, CSR0_P, SVDSETUPEND);
+ MUSB_FLAGS_PRINT(w, CSR0_P, SVDRXPKTRDY);
+ MUSB_FLAGS_PRINT(w, CSR0_P, SENDSTALL);
+ MUSB_FLAGS_PRINT(w, CSR0_P, SETUPEND);
+ MUSB_FLAGS_PRINT(w, CSR0_P, DATAEND);
+ MUSB_FLAGS_PRINT(w, CSR0_P, SENTSTALL);
+ MUSB_FLAGS_PRINT(w, CSR0, TXPKTRDY);
+ MUSB_FLAGS_PRINT(w, CSR0, RXPKTRDY);
+}
+
+static inline void musb_print_intrusb(u8 b)
+{
+ serial_printf("\tintrusb 0x%2.2x\n", b);
+ MUSB_FLAGS_PRINT(b, INTR, VBUSERROR);
+ MUSB_FLAGS_PRINT(b, INTR, SESSREQ);
+ MUSB_FLAGS_PRINT(b, INTR, DISCONNECT);
+ MUSB_FLAGS_PRINT(b, INTR, CONNECT);
+ MUSB_FLAGS_PRINT(b, INTR, SOF);
+ MUSB_FLAGS_PRINT(b, INTR, RESUME);
+ MUSB_FLAGS_PRINT(b, INTR, SUSPEND);
+
+ if (b & MUSB_INTR_BABBLE)
+ serial_printf("\t\tMUSB_INTR_RESET or MUSB_INTR_BABBLE\n");
+
+}
+
+static inline void musb_print_intrtx(u16 w)
+{
+ serial_printf("\tintrtx 0x%4.4x\n", w);
+}
+
+static inline void musb_print_intrrx(u16 w)
+{
+ serial_printf("\tintrx 0x%4.4x\n", w);
+}
+
+static inline void musb_print_devctl(u8 b)
+{
+ serial_printf("\tdevctl 0x%2.2x\n", b);
+ if (b & MUSB_DEVCTL_BDEVICE)
+ serial_printf("\t\tB device\n");
+ else
+ serial_printf("\t\tA device\n");
+ if (b & MUSB_DEVCTL_FSDEV)
+ serial_printf("\t\tFast Device -(host mode)\n");
+ if (b & MUSB_DEVCTL_LSDEV)
+ serial_printf("\t\tSlow Device -(host mode)\n");
+ if (b & MUSB_DEVCTL_HM)
+ serial_printf("\t\tHost mode\n");
+ else
+ serial_printf("\t\tPeripherial mode\n");
+ if (b & MUSB_DEVCTL_HR)
+ serial_printf("\t\tHost request started(B device)\n");
+ else
+ serial_printf("\t\tHost request finished(B device)\n");
+ if (b & MUSB_DEVCTL_BDEVICE) {
+ if (b & MUSB_DEVCTL_SESSION)
+ serial_printf("\t\tStart of session(B device)\n");
+ else
+ serial_printf("\t\tEnd of session(B device)\n");
+ } else {
+ if (b & MUSB_DEVCTL_SESSION)
+ serial_printf("\t\tStart of session(A device)\n");
+ else
+ serial_printf("\t\tEnd of session(A device)\n");
+ }
+}
+
+static inline void musb_print_config(u8 b)
+{
+ serial_printf("\tconfig 0x%2.2x\n", b);
+ if (b & MUSB_CONFIGDATA_MPRXE)
+ serial_printf("\t\tAuto combine rx bulk packets\n");
+ if (b & MUSB_CONFIGDATA_MPTXE)
+ serial_printf("\t\tAuto split tx bulk packets\n");
+ if (b & MUSB_CONFIGDATA_BIGENDIAN)
+ serial_printf("\t\tBig Endian ordering\n");
+ else
+ serial_printf("\t\tLittle Endian ordering\n");
+ if (b & MUSB_CONFIGDATA_HBRXE)
+ serial_printf("\t\tHigh speed rx iso endpoint\n");
+ if (b & MUSB_CONFIGDATA_HBTXE)
+ serial_printf("\t\tHigh speed tx iso endpoint\n");
+ if (b & MUSB_CONFIGDATA_DYNFIFO)
+ serial_printf("\t\tDynamic fifo sizing\n");
+ if (b & MUSB_CONFIGDATA_SOFTCONE)
+ serial_printf("\t\tSoft Connect\n");
+ if (b & MUSB_CONFIGDATA_UTMIDW)
+ serial_printf("\t\t16 bit data width\n");
+ else
+ serial_printf("\t\t8 bit data width\n");
+}
+
+static inline void musb_print_rxmaxp(u16 w)
+{
+ serial_printf("\trxmaxp 0x%4.4x\n", w);
+}
+
+static inline void musb_print_rxcsr(u16 w)
+{
+ serial_printf("\trxcsr 0x%4.4x\n", w);
+ MUSB_FLAGS_PRINT(w, RXCSR, AUTOCLEAR);
+ MUSB_FLAGS_PRINT(w, RXCSR, DMAENAB);
+ MUSB_FLAGS_PRINT(w, RXCSR, DISNYET);
+ MUSB_FLAGS_PRINT(w, RXCSR, PID_ERR);
+ MUSB_FLAGS_PRINT(w, RXCSR, DMAMODE);
+ MUSB_FLAGS_PRINT(w, RXCSR, CLRDATATOG);
+ MUSB_FLAGS_PRINT(w, RXCSR, FLUSHFIFO);
+ MUSB_FLAGS_PRINT(w, RXCSR, DATAERROR);
+ MUSB_FLAGS_PRINT(w, RXCSR, FIFOFULL);
+ MUSB_FLAGS_PRINT(w, RXCSR, RXPKTRDY);
+ MUSB_FLAGS_PRINT(w, RXCSR_P, SENTSTALL);
+ MUSB_FLAGS_PRINT(w, RXCSR_P, SENDSTALL);
+ MUSB_FLAGS_PRINT(w, RXCSR_P, OVERRUN);
+
+ if (w & MUSB_RXCSR_P_ISO)
+ serial_printf("\t\tiso mode\n");
+ else
+ serial_printf("\t\tbulk mode\n");
+
+}
+
+static inline void musb_print_txmaxp(u16 w)
+{
+ serial_printf("\ttxmaxp 0x%4.4x\n", w);
+}
+
+static inline void musb_print_txcsr(u16 w)
+{
+ serial_printf("\ttxcsr 0x%4.4x\n", w);
+ MUSB_FLAGS_PRINT(w, TXCSR, TXPKTRDY);
+ MUSB_FLAGS_PRINT(w, TXCSR, FIFONOTEMPTY);
+ MUSB_FLAGS_PRINT(w, TXCSR, FLUSHFIFO);
+ MUSB_FLAGS_PRINT(w, TXCSR, CLRDATATOG);
+ MUSB_FLAGS_PRINT(w, TXCSR_P, UNDERRUN);
+ MUSB_FLAGS_PRINT(w, TXCSR_P, SENTSTALL);
+ MUSB_FLAGS_PRINT(w, TXCSR_P, SENDSTALL);
+
+ if (w & MUSB_TXCSR_MODE)
+ serial_printf("\t\tTX mode\n");
+ else
+ serial_printf("\t\tRX mode\n");
+}
+
+#else
+
+/* stubs */
+
+#define musb_print_pwr(b)
+#define musb_print_csr0(w)
+#define musb_print_intrusb(b)
+#define musb_print_intrtx(w)
+#define musb_print_intrrx(w)
+#define musb_print_devctl(b)
+#define musb_print_config(b)
+#define musb_print_rxmaxp(w)
+#define musb_print_rxcsr(w)
+#define musb_print_txmaxp(w)
+#define musb_print_txcsr(w)
+
+#endif /* MUSB_DEBUG */
{MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */
};
+/* --- Virtual Root Hub ---------------------------------------------------- */
+#ifdef MUSB_NO_MULTIPOINT
+static int rh_devnum;
+static u32 port_status;
+
+/* Device descriptor */
+static u8 root_hub_dev_des[] = {
+ 0x12, /* __u8 bLength; */
+ 0x01, /* __u8 bDescriptorType; Device */
+ 0x00, /* __u16 bcdUSB; v1.1 */
+ 0x02,
+ 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 bDeviceSubClass; */
+ 0x00, /* __u8 bDeviceProtocol; */
+ 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
+ 0x00, /* __u16 idVendor; */
+ 0x00,
+ 0x00, /* __u16 idProduct; */
+ 0x00,
+ 0x00, /* __u16 bcdDevice; */
+ 0x00,
+ 0x00, /* __u8 iManufacturer; */
+ 0x01, /* __u8 iProduct; */
+ 0x00, /* __u8 iSerialNumber; */
+ 0x01 /* __u8 bNumConfigurations; */
+};
+
+/* Configuration descriptor */
+static u8 root_hub_config_des[] = {
+ 0x09, /* __u8 bLength; */
+ 0x02, /* __u8 bDescriptorType; Configuration */
+ 0x19, /* __u16 wTotalLength; */
+ 0x00,
+ 0x01, /* __u8 bNumInterfaces; */
+ 0x01, /* __u8 bConfigurationValue; */
+ 0x00, /* __u8 iConfiguration; */
+ 0x40, /* __u8 bmAttributes;
+ Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+ 0x00, /* __u8 MaxPower; */
+
+ /* interface */
+ 0x09, /* __u8 if_bLength; */
+ 0x04, /* __u8 if_bDescriptorType; Interface */
+ 0x00, /* __u8 if_bInterfaceNumber; */
+ 0x00, /* __u8 if_bAlternateSetting; */
+ 0x01, /* __u8 if_bNumEndpoints; */
+ 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 if_bInterfaceSubClass; */
+ 0x00, /* __u8 if_bInterfaceProtocol; */
+ 0x00, /* __u8 if_iInterface; */
+
+ /* endpoint */
+ 0x07, /* __u8 ep_bLength; */
+ 0x05, /* __u8 ep_bDescriptorType; Endpoint */
+ 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
+ 0x03, /* __u8 ep_bmAttributes; Interrupt */
+ 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+ 0x02,
+ 0xff /* __u8 ep_bInterval; 255 ms */
+};
+
+static unsigned char root_hub_str_index0[] = {
+ 0x04, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 0x09, /* __u8 lang ID */
+ 0x04, /* __u8 lang ID */
+};
+
+static unsigned char root_hub_str_index1[] = {
+ 0x1c, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 'M', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'U', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'S', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'B', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'R', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 't', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'u', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'b', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+};
+#endif
+
/*
* This function writes the data toggle value.
*/
if (dev->parent->children[chid] == dev)
break;
+#ifndef MUSB_NO_MULTIPOINT
/* configure the hub address and the port address */
writeb(hub, &musbr->tar[ep].txhubaddr);
writeb((chid + 1), &musbr->tar[ep].txhubport);
writeb(hub, &musbr->tar[ep].rxhubaddr);
writeb((chid + 1), &musbr->tar[ep].rxhubport);
+#endif
+}
+
+#ifdef MUSB_NO_MULTIPOINT
+
+static void musb_port_reset(int do_reset)
+{
+ u8 power = readb(&musbr->power);
+
+ if (do_reset) {
+ power &= 0xf0;
+ writeb(power | MUSB_POWER_RESET, &musbr->power);
+ port_status |= USB_PORT_STAT_RESET;
+ port_status &= ~USB_PORT_STAT_ENABLE;
+ udelay(30000);
+ } else {
+ writeb(power & ~MUSB_POWER_RESET, &musbr->power);
+
+ power = readb(&musbr->power);
+ if (power & MUSB_POWER_HSMODE)
+ port_status |= USB_PORT_STAT_HIGH_SPEED;
+
+ port_status &= ~(USB_PORT_STAT_RESET | (USB_PORT_STAT_C_CONNECTION << 16));
+ port_status |= USB_PORT_STAT_ENABLE
+ | (USB_PORT_STAT_C_RESET << 16)
+ | (USB_PORT_STAT_C_ENABLE << 16);
+ }
}
+/*
+ * root hub control
+ */
+static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len,
+ struct devrequest *cmd)
+{
+ int leni = transfer_len;
+ int len = 0;
+ int stat = 0;
+ u32 datab[4];
+ u8 *data_buf = (u8 *) datab;
+ u16 bmRType_bReq;
+ u16 wValue;
+ u16 wIndex;
+ u16 wLength;
+ u16 int_usb;
+
+ if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+ debug("Root-Hub submit IRQ: NOT implemented\n");
+ return 0;
+ }
+
+ bmRType_bReq = cmd->requesttype | (cmd->request << 8);
+ wValue = swap_16(cmd->value);
+ wIndex = swap_16(cmd->index);
+ wLength = swap_16(cmd->length);
+
+ debug("--- HUB ----------------------------------------\n");
+ debug("submit rh urb, req=%x val=%#x index=%#x len=%d\n",
+ bmRType_bReq, wValue, wIndex, wLength);
+ debug("------------------------------------------------\n");
+
+ switch (bmRType_bReq) {
+ case RH_GET_STATUS:
+ debug("RH_GET_STATUS\n");
+
+ *(__u16 *) data_buf = swap_16(1);
+ len = 2;
+ break;
+
+ case RH_GET_STATUS | RH_INTERFACE:
+ debug("RH_GET_STATUS | RH_INTERFACE\n");
+
+ *(__u16 *) data_buf = swap_16(0);
+ len = 2;
+ break;
+
+ case RH_GET_STATUS | RH_ENDPOINT:
+ debug("RH_GET_STATUS | RH_ENDPOINT\n");
+
+ *(__u16 *) data_buf = swap_16(0);
+ len = 2;
+ break;
+
+ case RH_GET_STATUS | RH_CLASS:
+ debug("RH_GET_STATUS | RH_CLASS\n");
+
+ *(__u32 *) data_buf = swap_32(0);
+ len = 4;
+ break;
+
+ case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+ debug("RH_GET_STATUS | RH_OTHER | RH_CLASS\n");
+
+ int_usb = readw(&musbr->intrusb);
+ if (int_usb & MUSB_INTR_CONNECT) {
+ port_status |= USB_PORT_STAT_CONNECTION
+ | (USB_PORT_STAT_C_CONNECTION << 16);
+ port_status |= USB_PORT_STAT_HIGH_SPEED
+ | USB_PORT_STAT_ENABLE;
+ }
+
+ if (port_status & USB_PORT_STAT_RESET)
+ musb_port_reset(0);
+
+ *(__u32 *) data_buf = swap_32(port_status);
+ len = 4;
+ break;
+
+ case RH_CLEAR_FEATURE | RH_ENDPOINT:
+ debug("RH_CLEAR_FEATURE | RH_ENDPOINT\n");
+
+ switch (wValue) {
+ case RH_ENDPOINT_STALL:
+ debug("C_HUB_ENDPOINT_STALL\n");
+ len = 0;
+ break;
+ }
+ port_status &= ~(1 << wValue);
+ break;
+
+ case RH_CLEAR_FEATURE | RH_CLASS:
+ debug("RH_CLEAR_FEATURE | RH_CLASS\n");
+
+ switch (wValue) {
+ case RH_C_HUB_LOCAL_POWER:
+ debug("C_HUB_LOCAL_POWER\n");
+ len = 0;
+ break;
+
+ case RH_C_HUB_OVER_CURRENT:
+ debug("C_HUB_OVER_CURRENT\n");
+ len = 0;
+ break;
+ }
+ port_status &= ~(1 << wValue);
+ break;
+
+ case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+ debug("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS\n");
+
+ switch (wValue) {
+ case RH_PORT_ENABLE:
+ len = 0;
+ break;
+
+ case RH_PORT_SUSPEND:
+ len = 0;
+ break;
+
+ case RH_PORT_POWER:
+ len = 0;
+ break;
+
+ case RH_C_PORT_CONNECTION:
+ len = 0;
+ break;
+
+ case RH_C_PORT_ENABLE:
+ len = 0;
+ break;
+
+ case RH_C_PORT_SUSPEND:
+ len = 0;
+ break;
+
+ case RH_C_PORT_OVER_CURRENT:
+ len = 0;
+ break;
+
+ case RH_C_PORT_RESET:
+ len = 0;
+ break;
+
+ default:
+ debug("invalid wValue\n");
+ stat = USB_ST_STALLED;
+ }
+
+ port_status &= ~(1 << wValue);
+ break;
+
+ case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+ debug("RH_SET_FEATURE | RH_OTHER | RH_CLASS\n");
+
+ switch (wValue) {
+ case RH_PORT_SUSPEND:
+ len = 0;
+ break;
+
+ case RH_PORT_RESET:
+ musb_port_reset(1);
+ len = 0;
+ break;
+
+ case RH_PORT_POWER:
+ len = 0;
+ break;
+
+ case RH_PORT_ENABLE:
+ len = 0;
+ break;
+
+ default:
+ debug("invalid wValue\n");
+ stat = USB_ST_STALLED;
+ }
+
+ port_status |= 1 << wValue;
+ break;
+
+ case RH_SET_ADDRESS:
+ debug("RH_SET_ADDRESS\n");
+
+ rh_devnum = wValue;
+ len = 0;
+ break;
+
+ case RH_GET_DESCRIPTOR:
+ debug("RH_GET_DESCRIPTOR: %x, %d\n", wValue, wLength);
+
+ switch (wValue) {
+ case (USB_DT_DEVICE << 8): /* device descriptor */
+ len = min_t(unsigned int,
+ leni, min_t(unsigned int,
+ sizeof(root_hub_dev_des),
+ wLength));
+ data_buf = root_hub_dev_des;
+ break;
+
+ case (USB_DT_CONFIG << 8): /* configuration descriptor */
+ len = min_t(unsigned int,
+ leni, min_t(unsigned int,
+ sizeof(root_hub_config_des),
+ wLength));
+ data_buf = root_hub_config_des;
+ break;
+
+ case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */
+ len = min_t(unsigned int,
+ leni, min_t(unsigned int,
+ sizeof(root_hub_str_index0),
+ wLength));
+ data_buf = root_hub_str_index0;
+ break;
+
+ case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */
+ len = min_t(unsigned int,
+ leni, min_t(unsigned int,
+ sizeof(root_hub_str_index1),
+ wLength));
+ data_buf = root_hub_str_index1;
+ break;
+
+ default:
+ debug("invalid wValue\n");
+ stat = USB_ST_STALLED;
+ }
+
+ break;
+
+ case RH_GET_DESCRIPTOR | RH_CLASS:
+ debug("RH_GET_DESCRIPTOR | RH_CLASS\n");
+
+ data_buf[0] = 0x09; /* min length; */
+ data_buf[1] = 0x29;
+ data_buf[2] = 0x1; /* 1 port */
+ data_buf[3] = 0x01; /* per-port power switching */
+ data_buf[3] |= 0x10; /* no overcurrent reporting */
+
+ /* Corresponds to data_buf[4-7] */
+ data_buf[4] = 0;
+ data_buf[5] = 5;
+ data_buf[6] = 0;
+ data_buf[7] = 0x02;
+ data_buf[8] = 0xff;
+
+ len = min_t(unsigned int, leni,
+ min_t(unsigned int, data_buf[0], wLength));
+ break;
+
+ case RH_GET_CONFIGURATION:
+ debug("RH_GET_CONFIGURATION\n");
+
+ *(__u8 *) data_buf = 0x01;
+ len = 1;
+ break;
+
+ case RH_SET_CONFIGURATION:
+ debug("RH_SET_CONFIGURATION\n");
+
+ len = 0;
+ break;
+
+ default:
+ debug("*** *** *** unsupported root hub command *** *** ***\n");
+ stat = USB_ST_STALLED;
+ }
+
+ len = min_t(int, len, leni);
+ if (buffer != data_buf)
+ memcpy(buffer, data_buf, len);
+
+ dev->act_len = len;
+ dev->status = stat;
+ debug("dev act_len %d, status %d\n", dev->act_len, dev->status);
+
+ return stat;
+}
+
+static void musb_rh_init(void)
+{
+ rh_devnum = 0;
+ port_status = 0;
+}
+
+#else
+
+static void musb_rh_init(void) {}
+
+#endif
+
/*
* do a control transfer
*/
u16 csr;
u8 devspeed;
+#ifdef MUSB_NO_MULTIPOINT
+ /* Control message is for the HUB? */
+ if (devnum == rh_devnum)
+ return musb_submit_rh_msg(dev, pipe, buffer, len, setup);
+#endif
+
/* select control endpoint */
writeb(MUSB_CONTROL_EP, &musbr->index);
csr = readw(&musbr->txcsr);
+#ifndef MUSB_NO_MULTIPOINT
/* target addr and (for multipoint) hub addr/port */
writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr);
writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr);
+#endif
/* configure the hub address and the port number as required */
devspeed = get_dev_speed(dev);
writeb(devspeed << 6, &musbr->txtype);
} else {
writeb(musb_cfg.musb_speed << 6, &musbr->txtype);
+#ifndef MUSB_NO_MULTIPOINT
writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr);
writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport);
writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr);
writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport);
+#endif
}
/* Control transfer setup phase */
{
int dir_out = usb_pipeout(pipe);
int ep = usb_pipeendpoint(pipe);
+#ifndef MUSB_NO_MULTIPOINT
int devnum = usb_pipedevice(pipe);
+#endif
u8 type;
u16 csr;
u32 txlen = 0;
/* select bulk endpoint */
writeb(MUSB_BULK_EP, &musbr->index);
+#ifndef MUSB_NO_MULTIPOINT
/* write the address of the device */
if (dir_out)
writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr);
else
writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr);
+#endif
/* configure the hub address and the port number as required */
devspeed = get_dev_speed(dev);
*/
config_hub_port(dev, MUSB_BULK_EP);
} else {
+#ifndef MUSB_NO_MULTIPOINT
if (dir_out) {
writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr);
writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport);
writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr);
writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport);
}
+#endif
devspeed = musb_cfg.musb_speed;
}
(len-txlen) : dev->epmaxpacketin[ep];
/* Set the ReqPkt bit */
- writew(MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
+ csr = readw(&musbr->rxcsr);
+ writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
/* Wait until the RxPktRdy bit is set */
if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) {
u8 power;
u32 timeout;
+ musb_rh_init();
+
if (musb_platform_init() == -1)
return -1;
{
int dir_out = usb_pipeout(pipe);
int ep = usb_pipeendpoint(pipe);
+#ifndef MUSB_NO_MULTIPOINT
int devnum = usb_pipedevice(pipe);
+#endif
u8 type;
u16 csr;
u32 txlen = 0;
/* select interrupt endpoint */
writeb(MUSB_INTR_EP, &musbr->index);
+#ifndef MUSB_NO_MULTIPOINT
/* write the address of the device */
if (dir_out)
writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr);
else
writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr);
+#endif
/* configure the hub address and the port number as required */
devspeed = get_dev_speed(dev);
*/
config_hub_port(dev, MUSB_INTR_EP);
} else {
+#ifndef MUSB_NO_MULTIPOINT
if (dir_out) {
writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr);
writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport);
writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr);
writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport);
}
+#endif
devspeed = musb_cfg.musb_speed;
}
(len-txlen) : dev->epmaxpacketin[ep];
/* Set the ReqPkt bit */
- writew(MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
+ csr = readw(&musbr->rxcsr);
+ writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
/* Wait until the RxPktRdy bit is set */
if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) {
{
struct stdio_dev *dev;
struct usb_device *usb_kbd_dev;
- struct usb_interface_descriptor *iface;
+ struct usb_interface *iface;
struct usb_endpoint_descriptor *ep;
int pipe;
int maxp;
#define MUSB_CONTROL_EP 0
/* This defines the endpoint number used for bulk transfer */
-#define MUSB_BULK_EP 1
+#ifndef MUSB_BULK_EP
+# define MUSB_BULK_EP 1
+#endif
/* This defines the endpoint number used for interrupt transfer */
#define MUSB_INTR_EP 2
((readb(&musbr->power) & MUSB_POWER_HSMODE) \
>> MUSB_POWER_HSMODE_SHIFT)
+#define min_t(type, x, y) \
+ ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
+
+/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
+
+/* destination of request */
+#define RH_INTERFACE 0x01
+#define RH_ENDPOINT 0x02
+#define RH_OTHER 0x03
+
+#define RH_CLASS 0x20
+#define RH_VENDOR 0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS 0x0080
+#define RH_CLEAR_FEATURE 0x0100
+#define RH_SET_FEATURE 0x0300
+#define RH_SET_ADDRESS 0x0500
+#define RH_GET_DESCRIPTOR 0x0680
+#define RH_SET_DESCRIPTOR 0x0700
+#define RH_GET_CONFIGURATION 0x0880
+#define RH_SET_CONFIGURATION 0x0900
+#define RH_GET_STATE 0x0280
+#define RH_GET_INTERFACE 0x0A80
+#define RH_SET_INTERFACE 0x0B00
+#define RH_SYNC_FRAME 0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP 0x2000
+
+/* Hub port features */
+#define RH_PORT_CONNECTION 0x00
+#define RH_PORT_ENABLE 0x01
+#define RH_PORT_SUSPEND 0x02
+#define RH_PORT_OVER_CURRENT 0x03
+#define RH_PORT_RESET 0x04
+#define RH_PORT_POWER 0x08
+#define RH_PORT_LOW_SPEED 0x09
+
+#define RH_C_PORT_CONNECTION 0x10
+#define RH_C_PORT_ENABLE 0x11
+#define RH_C_PORT_SUSPEND 0x12
+#define RH_C_PORT_OVER_CURRENT 0x13
+#define RH_C_PORT_RESET 0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER 0x00
+#define RH_C_HUB_OVER_CURRENT 0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP 0x00
+#define RH_ENDPOINT_STALL 0x01
+
+#define RH_ACK 0x01
+#define RH_REQ_ERR -1
+#define RH_NACK 0x00
+
/* extern functions */
extern int musb_platform_init(void);
extern void musb_platform_deinit(void);
--- /dev/null
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This file is a rewrite of the usb device part of
+ * repository git.omapzoom.org/repo/u-boot.git, branch master,
+ * file cpu/omap3/fastboot.c
+ *
+ * This is the unique part of its copyright :
+ *
+ * -------------------------------------------------------------------------
+ *
+ * (C) Copyright 2008 - 2009
+ * Windriver, <www.windriver.com>
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * -------------------------------------------------------------------------
+ *
+ * The details of connecting the device to the uboot usb device subsystem
+ * came from the old omap3 repository www.sakoman.net/u-boot-omap3.git,
+ * branch omap3-dev-usb, file drivers/usb/usbdcore_musb.c
+ *
+ * This is the unique part of its copyright :
+ *
+ * -------------------------------------------------------------------------
+ *
+ * (C) Copyright 2008 Texas Instruments Incorporated.
+ *
+ * Based on
+ * u-boot OMAP1510 USB drivers (drivers/usbdcore_omap1510.c)
+ * twl4030 init based on linux (drivers/i2c/chips/twl4030_usb.c)
+ *
+ * Author: Diego Dompe (diego.dompe@ridgerun.com)
+ * Atin Malaviya (atin.malaviya@gmail.com)
+ *
+ * -------------------------------------------------------------------------
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <usb/musb_udc.h>
+#include "../gadget/ep0.h"
+#include "musb_core.h"
+#if defined(CONFIG_USB_OMAP3)
+#include "omap3.h"
+#elif defined(CONFIG_USB_DAVINCI)
+#include "davinci.h"
+#endif
+
+/* Define MUSB_DEBUG for debugging */
+/* #define MUSB_DEBUG */
+#include "musb_debug.h"
+
+#define MAX_ENDPOINT 15
+
+#define GET_ENDPOINT(dev,ep) \
+(((struct usb_device_instance *)(dev))->bus->endpoint_array + ep)
+
+#define SET_EP0_STATE(s) \
+do { \
+ if ((0 <= (s)) && (SET_ADDRESS >= (s))) { \
+ if ((s) != ep0_state) { \
+ if ((debug_setup) && (debug_level > 1)) \
+ serial_printf("INFO : Changing state " \
+ "from %s to %s in %s at " \
+ "line %d\n", \
+ ep0_state_strings[ep0_state],\
+ ep0_state_strings[s], \
+ __PRETTY_FUNCTION__, \
+ __LINE__); \
+ ep0_state = s; \
+ } \
+ } else { \
+ if (debug_level > 0) \
+ serial_printf("Error at %s %d with setting " \
+ "state %d is invalid\n", \
+ __PRETTY_FUNCTION__, __LINE__, s); \
+ } \
+} while (0)
+
+/* static implies these initialized to 0 or NULL */
+static int debug_setup;
+static int debug_level;
+static struct musb_epinfo epinfo[MAX_ENDPOINT * 2];
+static enum ep0_state_enum {
+ IDLE = 0,
+ TX,
+ RX,
+ SET_ADDRESS
+} ep0_state = IDLE;
+static char *ep0_state_strings[4] = {
+ "IDLE",
+ "TX",
+ "RX",
+ "SET_ADDRESS",
+};
+
+static struct urb *ep0_urb;
+struct usb_endpoint_instance *ep0_endpoint;
+static struct usb_device_instance *udc_device;
+static int enabled;
+
+#ifdef MUSB_DEBUG
+static void musb_db_regs(void)
+{
+ u8 b;
+ u16 w;
+
+ b = readb(&musbr->faddr);
+ serial_printf("\tfaddr 0x%2.2x\n", b);
+
+ b = readb(&musbr->power);
+ musb_print_pwr(b);
+
+ w = readw(&musbr->ep[0].ep0.csr0);
+ musb_print_csr0(w);
+
+ b = readb(&musbr->devctl);
+ musb_print_devctl(b);
+
+ b = readb(&musbr->ep[0].ep0.configdata);
+ musb_print_config(b);
+
+ w = readw(&musbr->frame);
+ serial_printf("\tframe 0x%4.4x\n", w);
+
+ b = readb(&musbr->index);
+ serial_printf("\tindex 0x%2.2x\n", b);
+
+ w = readw(&musbr->ep[1].epN.rxmaxp);
+ musb_print_rxmaxp(w);
+
+ w = readw(&musbr->ep[1].epN.rxcsr);
+ musb_print_rxcsr(w);
+
+ w = readw(&musbr->ep[1].epN.txmaxp);
+ musb_print_txmaxp(w);
+
+ w = readw(&musbr->ep[1].epN.txcsr);
+ musb_print_txcsr(w);
+}
+#else
+#define musb_db_regs()
+#endif /* DEBUG_MUSB */
+
+static void musb_peri_softconnect(void)
+{
+ u8 power, devctl;
+ u8 intrusb;
+ u16 intrrx, intrtx;
+
+ /* Power off MUSB */
+ power = readb(&musbr->power);
+ power &= ~MUSB_POWER_SOFTCONN;
+ writeb(power, &musbr->power);
+
+ /* Read intr to clear */
+ intrusb = readb(&musbr->intrusb);
+ intrrx = readw(&musbr->intrrx);
+ intrtx = readw(&musbr->intrtx);
+
+ udelay(1000 * 1000); /* 1 sec */
+
+ /* Power on MUSB */
+ power = readb(&musbr->power);
+ power |= MUSB_POWER_SOFTCONN;
+ /*
+ * The usb device interface is usb 1.1
+ * Disable 2.0 high speed by clearring the hsenable bit.
+ */
+ power &= ~MUSB_POWER_HSENAB;
+ writeb(power, &musbr->power);
+
+ /* Check if device is in b-peripheral mode */
+ devctl = readb(&musbr->devctl);
+ if (!(devctl & MUSB_DEVCTL_BDEVICE) ||
+ (devctl & MUSB_DEVCTL_HM)) {
+ serial_printf("ERROR : Unsupport USB mode\n");
+ serial_printf("Check that mini-B USB cable is attached "
+ "to the device\n");
+ }
+
+ if (debug_setup && (debug_level > 1))
+ musb_db_regs();
+}
+
+static void musb_peri_reset(void)
+{
+ if ((debug_setup) && (debug_level > 1))
+ serial_printf("INFO : %s reset\n", __PRETTY_FUNCTION__);
+
+ if (ep0_endpoint)
+ ep0_endpoint->endpoint_address = 0xff;
+
+ /* Sync sw and hw addresses */
+ writeb(udc_device->address, &musbr->faddr);
+
+ SET_EP0_STATE(IDLE);
+}
+
+static void musb_peri_resume(void)
+{
+ /* noop */
+}
+
+static void musb_peri_ep0_stall(void)
+{
+ u16 csr0;
+
+ csr0 = readw(&musbr->ep[0].ep0.csr0);
+ csr0 |= MUSB_CSR0_P_SENDSTALL;
+ writew(csr0, &musbr->ep[0].ep0.csr0);
+ if ((debug_setup) && (debug_level > 1))
+ serial_printf("INFO : %s stall\n", __PRETTY_FUNCTION__);
+}
+
+static void musb_peri_ep0_ack_req(void)
+{
+ u16 csr0;
+
+ csr0 = readw(&musbr->ep[0].ep0.csr0);
+ csr0 |= MUSB_CSR0_P_SVDRXPKTRDY;
+ writew(csr0, &musbr->ep[0].ep0.csr0);
+}
+
+static void musb_ep0_tx_ready(void)
+{
+ u16 csr0;
+
+ csr0 = readw(&musbr->ep[0].ep0.csr0);
+ csr0 |= MUSB_CSR0_TXPKTRDY;
+ writew(csr0, &musbr->ep[0].ep0.csr0);
+}
+
+static void musb_ep0_tx_ready_and_last(void)
+{
+ u16 csr0;
+
+ csr0 = readw(&musbr->ep[0].ep0.csr0);
+ csr0 |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_P_DATAEND);
+ writew(csr0, &musbr->ep[0].ep0.csr0);
+}
+
+static void musb_peri_ep0_last(void)
+{
+ u16 csr0;
+
+ csr0 = readw(&musbr->ep[0].ep0.csr0);
+ csr0 |= MUSB_CSR0_P_DATAEND;
+ writew(csr0, &musbr->ep[0].ep0.csr0);
+}
+
+static void musb_peri_ep0_set_address(void)
+{
+ u8 faddr;
+ writeb(udc_device->address, &musbr->faddr);
+
+ /* Verify */
+ faddr = readb(&musbr->faddr);
+ if (udc_device->address == faddr) {
+ SET_EP0_STATE(IDLE);
+ usbd_device_event_irq(udc_device, DEVICE_ADDRESS_ASSIGNED, 0);
+ if ((debug_setup) && (debug_level > 1))
+ serial_printf("INFO : %s Address set to %d\n",
+ __PRETTY_FUNCTION__, udc_device->address);
+ } else {
+ if (debug_level > 0)
+ serial_printf("ERROR : %s Address missmatch "
+ "sw %d vs hw %d\n",
+ __PRETTY_FUNCTION__,
+ udc_device->address, faddr);
+ }
+}
+
+static void musb_peri_rx_ack(unsigned int ep)
+{
+ u16 peri_rxcsr;
+
+ peri_rxcsr = readw(&musbr->ep[ep].epN.rxcsr);
+ peri_rxcsr &= ~MUSB_RXCSR_RXPKTRDY;
+ writew(peri_rxcsr, &musbr->ep[ep].epN.rxcsr);
+}
+
+static void musb_peri_tx_ready(unsigned int ep)
+{
+ u16 peri_txcsr;
+
+ peri_txcsr = readw(&musbr->ep[ep].epN.txcsr);
+ peri_txcsr |= MUSB_TXCSR_TXPKTRDY;
+ writew(peri_txcsr, &musbr->ep[ep].epN.txcsr);
+}
+
+static void musb_peri_ep0_zero_data_request(int err)
+{
+ musb_peri_ep0_ack_req();
+
+ if (err) {
+ musb_peri_ep0_stall();
+ SET_EP0_STATE(IDLE);
+ } else {
+
+ musb_peri_ep0_last();
+
+ /* USBD state */
+ switch (ep0_urb->device_request.bRequest) {
+ case USB_REQ_SET_ADDRESS:
+ if ((debug_setup) && (debug_level > 1))
+ serial_printf("INFO : %s received set "
+ "address\n", __PRETTY_FUNCTION__);
+ break;
+
+ case USB_REQ_SET_CONFIGURATION:
+ if ((debug_setup) && (debug_level > 1))
+ serial_printf("INFO : %s Configured\n",
+ __PRETTY_FUNCTION__);
+ usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0);
+ break;
+ }
+
+ /* EP0 state */
+ if (USB_REQ_SET_ADDRESS == ep0_urb->device_request.bRequest) {
+ SET_EP0_STATE(SET_ADDRESS);
+ } else {
+ SET_EP0_STATE(IDLE);
+ }
+ }
+}
+
+static void musb_peri_ep0_rx_data_request(void)
+{
+ /*
+ * This is the completion of the data OUT / RX
+ *
+ * Host is sending data to ep0 that is not
+ * part of setup. This comes from the cdc_recv_setup
+ * op that is device specific.
+ *
+ */
+ musb_peri_ep0_ack_req();
+
+ ep0_endpoint->rcv_urb = ep0_urb;
+ ep0_urb->actual_length = 0;
+ SET_EP0_STATE(RX);
+}
+
+static void musb_peri_ep0_tx_data_request(int err)
+{
+ if (err) {
+ musb_peri_ep0_stall();
+ SET_EP0_STATE(IDLE);
+ } else {
+ musb_peri_ep0_ack_req();
+
+ ep0_endpoint->tx_urb = ep0_urb;
+ ep0_endpoint->sent = 0;
+ SET_EP0_STATE(TX);
+ }
+}
+
+static void musb_peri_ep0_idle(void)
+{
+ u16 count0;
+ int err;
+ u16 csr0;
+
+ /*
+ * Verify addresses
+ * A lot of confusion can be caused if the address
+ * in software, udc layer, does not agree with the
+ * hardware. Since the setting of the hardware address
+ * must be set after the set address request, the
+ * usb state machine is out of sync for a few frame.
+ * It is a good idea to run this check when changes
+ * are made to the state machine.
+ */
+ if ((debug_level > 0) &&
+ (ep0_state != SET_ADDRESS)) {
+ u8 faddr;
+
+ faddr = readb(&musbr->faddr);
+ if (udc_device->address != faddr) {
+ serial_printf("ERROR : %s addresses do not"
+ "match sw %d vs hw %d\n",
+ __PRETTY_FUNCTION__,
+ udc_device->address, faddr);
+ udelay(1000 * 1000);
+ hang();
+ }
+ }
+
+ csr0 = readw(&musbr->ep[0].ep0.csr0);
+
+ if (!(MUSB_CSR0_RXPKTRDY & csr0))
+ goto end;
+
+ count0 = readw(&musbr->ep[0].ep0.count0);
+ if (count0 == 0)
+ goto end;
+
+ if (count0 != 8) {
+ if ((debug_setup) && (debug_level > 1))
+ serial_printf("WARN : %s SETUP incorrect size %d\n",
+ __PRETTY_FUNCTION__, count0);
+ musb_peri_ep0_stall();
+ goto end;
+ }
+
+ read_fifo(0, count0, &ep0_urb->device_request);
+
+ if (debug_level > 2)
+ print_usb_device_request(&ep0_urb->device_request);
+
+ if (ep0_urb->device_request.wLength == 0) {
+ err = ep0_recv_setup(ep0_urb);
+
+ /* Zero data request */
+ musb_peri_ep0_zero_data_request(err);
+ } else {
+ /* Is data coming or going ? */
+ u8 reqType = ep0_urb->device_request.bmRequestType;
+
+ if (USB_REQ_DEVICE2HOST == (reqType & USB_REQ_DIRECTION_MASK)) {
+ err = ep0_recv_setup(ep0_urb);
+ /* Device to host */
+ musb_peri_ep0_tx_data_request(err);
+ } else {
+ /*
+ * Host to device
+ *
+ * The RX routine will call ep0_recv_setup
+ * when the data packet has arrived.
+ */
+ musb_peri_ep0_rx_data_request();
+ }
+ }
+
+end:
+ return;
+}
+
+static void musb_peri_ep0_rx(void)
+{
+ /*
+ * This is the completion of the data OUT / RX
+ *
+ * Host is sending data to ep0 that is not
+ * part of setup. This comes from the cdc_recv_setup
+ * op that is device specific.
+ *
+ * Pass the data back to driver ep0_recv_setup which
+ * should give the cdc_recv_setup the chance to handle
+ * the rx
+ */
+ u16 csr0;
+ u16 count0;
+
+ if (debug_level > 3) {
+ if (0 != ep0_urb->actual_length) {
+ serial_printf("%s finished ? %d of %d\n",
+ __PRETTY_FUNCTION__,
+ ep0_urb->actual_length,
+ ep0_urb->device_request.wLength);
+ }
+ }
+
+ if (ep0_urb->device_request.wLength == ep0_urb->actual_length) {
+ musb_peri_ep0_last();
+ SET_EP0_STATE(IDLE);
+ ep0_recv_setup(ep0_urb);
+ return;
+ }
+
+ csr0 = readw(&musbr->ep[0].ep0.csr0);
+ if (!(MUSB_CSR0_RXPKTRDY & csr0))
+ return;
+
+ count0 = readw(&musbr->ep[0].ep0.count0);
+
+ if (count0) {
+ struct usb_endpoint_instance *endpoint;
+ u32 length;
+ u8 *data;
+
+ endpoint = ep0_endpoint;
+ if (endpoint && endpoint->rcv_urb) {
+ struct urb *urb = endpoint->rcv_urb;
+ unsigned int remaining_space = urb->buffer_length -
+ urb->actual_length;
+
+ if (remaining_space) {
+ int urb_bad = 0; /* urb is good */
+
+ if (count0 > remaining_space)
+ length = remaining_space;
+ else
+ length = count0;
+
+ data = (u8 *) urb->buffer_data;
+ data += urb->actual_length;
+
+ /* The common musb fifo reader */
+ read_fifo(0, length, data);
+
+ musb_peri_ep0_ack_req();
+
+ /*
+ * urb's actual_length is updated in
+ * usbd_rcv_complete
+ */
+ usbd_rcv_complete(endpoint, length, urb_bad);
+
+ } else {
+ if (debug_level > 0)
+ serial_printf("ERROR : %s no space in "
+ "rcv buffer\n",
+ __PRETTY_FUNCTION__);
+ }
+ } else {
+ if (debug_level > 0)
+ serial_printf("ERROR : %s problem with "
+ "endpoint\n",
+ __PRETTY_FUNCTION__);
+ }
+ } else {
+ if (debug_level > 0)
+ serial_printf("ERROR : %s with nothing to do\n",
+ __PRETTY_FUNCTION__);
+ }
+}
+
+static void musb_peri_ep0_tx(void)
+{
+ u16 csr0;
+ int transfer_size = 0;
+ unsigned int p, pm;
+
+ csr0 = readw(&musbr->ep[0].ep0.csr0);
+
+ /* Check for pending tx */
+ if (csr0 & MUSB_CSR0_TXPKTRDY)
+ goto end;
+
+ /* Check if this is the last packet sent */
+ if (ep0_endpoint->sent >= ep0_urb->actual_length) {
+ SET_EP0_STATE(IDLE);
+ goto end;
+ }
+
+ transfer_size = ep0_urb->actual_length - ep0_endpoint->sent;
+ /* Is the transfer size negative ? */
+ if (transfer_size <= 0) {
+ if (debug_level > 0)
+ serial_printf("ERROR : %s problem with the"
+ " transfer size %d\n",
+ __PRETTY_FUNCTION__,
+ transfer_size);
+ SET_EP0_STATE(IDLE);
+ goto end;
+ }
+
+ /* Truncate large transfers to the fifo size */
+ if (transfer_size > ep0_endpoint->tx_packetSize)
+ transfer_size = ep0_endpoint->tx_packetSize;
+
+ write_fifo(0, transfer_size, &ep0_urb->buffer[ep0_endpoint->sent]);
+ ep0_endpoint->sent += transfer_size;
+
+ /* Done or more to send ? */
+ if (ep0_endpoint->sent >= ep0_urb->actual_length)
+ musb_ep0_tx_ready_and_last();
+ else
+ musb_ep0_tx_ready();
+
+ /* Wait a bit */
+ pm = 10;
+ for (p = 0; p < pm; p++) {
+ csr0 = readw(&musbr->ep[0].ep0.csr0);
+ if (!(csr0 & MUSB_CSR0_TXPKTRDY))
+ break;
+
+ /* Double the delay. */
+ udelay(1 << pm);
+ }
+
+ if ((ep0_endpoint->sent >= ep0_urb->actual_length) && (p < pm))
+ SET_EP0_STATE(IDLE);
+
+end:
+ return;
+}
+
+static void musb_peri_ep0(void)
+{
+ u16 csr0;
+
+ if (SET_ADDRESS == ep0_state)
+ return;
+
+ csr0 = readw(&musbr->ep[0].ep0.csr0);
+
+ /* Error conditions */
+ if (MUSB_CSR0_P_SENTSTALL & csr0) {
+ csr0 &= ~MUSB_CSR0_P_SENTSTALL;
+ writew(csr0, &musbr->ep[0].ep0.csr0);
+ SET_EP0_STATE(IDLE);
+ }
+ if (MUSB_CSR0_P_SETUPEND & csr0) {
+ csr0 |= MUSB_CSR0_P_SVDSETUPEND;
+ writew(csr0, &musbr->ep[0].ep0.csr0);
+ SET_EP0_STATE(IDLE);
+ if ((debug_setup) && (debug_level > 1))
+ serial_printf("WARN: %s SETUPEND\n",
+ __PRETTY_FUNCTION__);
+ }
+
+ /* Normal states */
+ if (IDLE == ep0_state)
+ musb_peri_ep0_idle();
+
+ if (TX == ep0_state)
+ musb_peri_ep0_tx();
+
+ if (RX == ep0_state)
+ musb_peri_ep0_rx();
+}
+
+static void musb_peri_rx_ep(unsigned int ep)
+{
+ u16 peri_rxcount = readw(&musbr->ep[ep].epN.rxcount);
+
+ if (peri_rxcount) {
+ struct usb_endpoint_instance *endpoint;
+ u32 length;
+ u8 *data;
+
+ endpoint = GET_ENDPOINT(udc_device, ep);
+ if (endpoint && endpoint->rcv_urb) {
+ struct urb *urb = endpoint->rcv_urb;
+ unsigned int remaining_space = urb->buffer_length -
+ urb->actual_length;
+
+ if (remaining_space) {
+ int urb_bad = 0; /* urb is good */
+
+ if (peri_rxcount > remaining_space)
+ length = remaining_space;
+ else
+ length = peri_rxcount;
+
+ data = (u8 *) urb->buffer_data;
+ data += urb->actual_length;
+
+ /* The common musb fifo reader */
+ read_fifo(ep, length, data);
+
+ musb_peri_rx_ack(ep);
+
+ /*
+ * urb's actual_length is updated in
+ * usbd_rcv_complete
+ */
+ usbd_rcv_complete(endpoint, length, urb_bad);
+
+ } else {
+ if (debug_level > 0)
+ serial_printf("ERROR : %s %d no space "
+ "in rcv buffer\n",
+ __PRETTY_FUNCTION__, ep);
+ }
+ } else {
+ if (debug_level > 0)
+ serial_printf("ERROR : %s %d problem with "
+ "endpoint\n",
+ __PRETTY_FUNCTION__, ep);
+ }
+
+ } else {
+ if (debug_level > 0)
+ serial_printf("ERROR : %s %d with nothing to do\n",
+ __PRETTY_FUNCTION__, ep);
+ }
+}
+
+static void musb_peri_rx(u16 intr)
+{
+ unsigned int ep;
+
+ /* Check for EP0 */
+ if (0x01 & intr)
+ musb_peri_ep0();
+
+ for (ep = 1; ep < 16; ep++) {
+ if ((1 << ep) & intr)
+ musb_peri_rx_ep(ep);
+ }
+}
+
+static void musb_peri_tx(u16 intr)
+{
+ /* Check for EP0 */
+ if (0x01 & intr)
+ musb_peri_ep0_tx();
+
+ /*
+ * Use this in the future when handling epN tx
+ *
+ * u8 ep;
+ *
+ * for (ep = 1; ep < 16; ep++) {
+ * if ((1 << ep) & intr) {
+ * / * handle tx for this endpoint * /
+ * }
+ * }
+ */
+}
+
+void udc_irq(void)
+{
+ /* This is a high freq called function */
+ if (enabled) {
+ u8 intrusb;
+
+ intrusb = readb(&musbr->intrusb);
+
+ /*
+ * See drivers/usb/gadget/mpc8xx_udc.c for
+ * state diagram going from detached through
+ * configuration.
+ */
+ if (MUSB_INTR_RESUME & intrusb) {
+ usbd_device_event_irq(udc_device,
+ DEVICE_BUS_ACTIVITY, 0);
+ musb_peri_resume();
+ }
+
+ musb_peri_ep0();
+
+ if (MUSB_INTR_RESET & intrusb) {
+ usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
+ musb_peri_reset();
+ }
+
+ if (MUSB_INTR_DISCONNECT & intrusb) {
+ /* cable unplugged from hub/host */
+ usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
+ musb_peri_reset();
+ usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0);
+ }
+
+ if (MUSB_INTR_SOF & intrusb) {
+ usbd_device_event_irq(udc_device,
+ DEVICE_BUS_ACTIVITY, 0);
+ musb_peri_resume();
+ }
+
+ if (MUSB_INTR_SUSPEND & intrusb) {
+ usbd_device_event_irq(udc_device,
+ DEVICE_BUS_INACTIVE, 0);
+ }
+
+ if (ep0_state != SET_ADDRESS) {
+ u16 intrrx, intrtx;
+
+ intrrx = readw(&musbr->intrrx);
+ intrtx = readw(&musbr->intrtx);
+
+ if (intrrx)
+ musb_peri_rx(intrrx);
+
+ if (intrtx)
+ musb_peri_tx(intrtx);
+ } else {
+ if (MUSB_INTR_SOF & intrusb) {
+ u8 faddr;
+ faddr = readb(&musbr->faddr);
+ /*
+ * Setting of the address can fail.
+ * Normally it succeeds the second time.
+ */
+ if (udc_device->address != faddr)
+ musb_peri_ep0_set_address();
+ }
+ }
+ }
+}
+
+void udc_set_nak(int ep_num)
+{
+ /* noop */
+}
+
+void udc_unset_nak(int ep_num)
+{
+ /* noop */
+}
+
+int udc_endpoint_write(struct usb_endpoint_instance *endpoint)
+{
+ int ret = 0;
+
+ /* Transmit only if the hardware is available */
+ if (endpoint->tx_urb && endpoint->state == 0) {
+ unsigned int ep = endpoint->endpoint_address &
+ USB_ENDPOINT_NUMBER_MASK;
+
+ u16 peri_txcsr = readw(&musbr->ep[ep].epN.txcsr);
+
+ /* Error conditions */
+ if (peri_txcsr & MUSB_TXCSR_P_UNDERRUN) {
+ peri_txcsr &= ~MUSB_TXCSR_P_UNDERRUN;
+ writew(peri_txcsr, &musbr->ep[ep].epN.txcsr);
+ }
+
+ if (debug_level > 1)
+ musb_print_txcsr(peri_txcsr);
+
+ /* Check if a packet is waiting to be sent */
+ if (!(peri_txcsr & MUSB_TXCSR_TXPKTRDY)) {
+ u32 length;
+ u8 *data;
+ struct urb *urb = endpoint->tx_urb;
+ unsigned int remaining_packet = urb->actual_length -
+ endpoint->sent;
+
+ if (endpoint->tx_packetSize < remaining_packet)
+ length = endpoint->tx_packetSize;
+ else
+ length = remaining_packet;
+
+ data = (u8 *) urb->buffer;
+ data += endpoint->sent;
+
+ /* common musb fifo function */
+ write_fifo(ep, length, data);
+
+ musb_peri_tx_ready(ep);
+
+ endpoint->last = length;
+ /* usbd_tx_complete will take care of updating 'sent' */
+ usbd_tx_complete(endpoint);
+ }
+ } else {
+ if (debug_level > 0)
+ serial_printf("ERROR : %s Problem with urb %p "
+ "or ep state %d\n",
+ __PRETTY_FUNCTION__,
+ endpoint->tx_urb, endpoint->state);
+ }
+
+ return ret;
+}
+
+void udc_setup_ep(struct usb_device_instance *device, unsigned int id,
+ struct usb_endpoint_instance *endpoint)
+{
+ if (0 == id) {
+ /* EP0 */
+ ep0_endpoint = endpoint;
+ ep0_endpoint->endpoint_address = 0xff;
+ ep0_urb = usbd_alloc_urb(device, endpoint);
+ } else if (MAX_ENDPOINT >= id) {
+ int ep_addr;
+
+ /* Check the direction */
+ ep_addr = endpoint->endpoint_address;
+ if (USB_DIR_IN == (ep_addr & USB_ENDPOINT_DIR_MASK)) {
+ /* IN */
+ epinfo[(id * 2) + 1].epsize = endpoint->tx_packetSize;
+ } else {
+ /* OUT */
+ epinfo[id * 2].epsize = endpoint->rcv_packetSize;
+ }
+
+ musb_configure_ep(&epinfo[0],
+ sizeof(epinfo) / sizeof(struct musb_epinfo));
+ } else {
+ if (debug_level > 0)
+ serial_printf("ERROR : %s endpoint request %d "
+ "exceeds maximum %d\n",
+ __PRETTY_FUNCTION__, id, MAX_ENDPOINT);
+ }
+}
+
+void udc_connect(void)
+{
+ /* noop */
+}
+
+void udc_disconnect(void)
+{
+ /* noop */
+}
+
+void udc_enable(struct usb_device_instance *device)
+{
+ /* Save the device structure pointer */
+ udc_device = device;
+
+ enabled = 1;
+}
+
+void udc_disable(void)
+{
+ enabled = 0;
+}
+
+void udc_startup_events(struct usb_device_instance *device)
+{
+ /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */
+ usbd_device_event_irq(device, DEVICE_INIT, 0);
+
+ /*
+ * The DEVICE_CREATE event puts the USB device in the state
+ * STATE_ATTACHED.
+ */
+ usbd_device_event_irq(device, DEVICE_CREATE, 0);
+
+ /* Resets the address to 0 */
+ usbd_device_event_irq(device, DEVICE_RESET, 0);
+
+ udc_enable(device);
+}
+
+int udc_init(void)
+{
+ int ret;
+ int ep_loop;
+
+ ret = musb_platform_init();
+ if (ret < 0)
+ goto end;
+
+ /* Configure all the endpoint FIFO's and start usb controller */
+ musbr = musb_cfg.regs;
+
+ /* Initialize the endpoints */
+ for (ep_loop = 0; ep_loop < MAX_ENDPOINT * 2; ep_loop++) {
+ epinfo[ep_loop].epnum = (ep_loop / 2) + 1;
+ epinfo[ep_loop].epdir = ep_loop % 2; /* OUT, IN */
+ epinfo[ep_loop].epsize = 0;
+ }
+
+ musb_peri_softconnect();
+
+ ret = 0;
+end:
+
+ return ret;
+}
--- /dev/null
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This is file is based on
+ * repository git.gitorious.org/u-boot-omap3/mainline.git,
+ * branch omap3-dev-usb, file drivers/usb/host/omap3530_usb.c
+ *
+ * This is the unique part of its copyright :
+ *
+ * ------------------------------------------------------------------------
+ *
+ * Copyright (c) 2009 Texas Instruments
+ *
+ * ------------------------------------------------------------------------
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <twl4030.h>
+#include "omap3.h"
+
+static int platform_needs_initialization = 1;
+
+struct musb_config musb_cfg = {
+ (struct musb_regs *)MENTOR_USB0_BASE,
+ OMAP3_USB_TIMEOUT,
+ 0
+};
+
+/*
+ * OMAP3 USB OTG registers.
+ */
+struct omap3_otg_regs {
+ u32 revision;
+ u32 sysconfig;
+ u32 sysstatus;
+ u32 interfsel;
+ u32 simenable;
+ u32 forcestdby;
+};
+
+static struct omap3_otg_regs *otg;
+
+#define OMAP3_OTG_SYSCONFIG_SMART_STANDBY_MODE 0x2000
+#define OMAP3_OTG_SYSCONFIG_NO_STANDBY_MODE 0x1000
+#define OMAP3_OTG_SYSCONFIG_SMART_IDLE_MODE 0x0010
+#define OMAP3_OTG_SYSCONFIG_NO_IDLE_MODE 0x0008
+#define OMAP3_OTG_SYSCONFIG_ENABLEWAKEUP 0x0004
+#define OMAP3_OTG_SYSCONFIG_SOFTRESET 0x0002
+#define OMAP3_OTG_SYSCONFIG_AUTOIDLE 0x0001
+
+#define OMAP3_OTG_SYSSTATUS_RESETDONE 0x0001
+
+#define OMAP3_OTG_INTERFSEL_OMAP 0x0001
+
+#define OMAP3_OTG_FORCESTDBY_STANDBY 0x0001
+
+
+#ifdef DEBUG_MUSB_OMAP3
+static void musb_db_otg_regs(void)
+{
+ u32 l;
+ l = readl(&otg->revision);
+ serial_printf("OTG_REVISION 0x%x\n", l);
+ l = readl(&otg->sysconfig);
+ serial_printf("OTG_SYSCONFIG 0x%x\n", l);
+ l = readl(&otg->sysstatus);
+ serial_printf("OTG_SYSSTATUS 0x%x\n", l);
+ l = readl(&otg->interfsel);
+ serial_printf("OTG_INTERFSEL 0x%x\n", l);
+ l = readl(&otg->forcestdby);
+ serial_printf("OTG_FORCESTDBY 0x%x\n", l);
+}
+#endif
+
+int musb_platform_init(void)
+{
+ int ret = -1;
+
+ if (platform_needs_initialization) {
+ u32 stdby;
+
+ /*
+ * OMAP3EVM uses ISP1504 phy and so
+ * twl4030 related init is not required.
+ */
+#ifdef CONFIG_TWL4030_USB
+ if (twl4030_usb_ulpi_init()) {
+ serial_printf("ERROR: %s Could not initialize PHY\n",
+ __PRETTY_FUNCTION__);
+ goto end;
+ }
+#endif
+ otg = (struct omap3_otg_regs *)OMAP3_OTG_BASE;
+
+ /* Set OTG to always be on */
+ writel(OMAP3_OTG_SYSCONFIG_NO_STANDBY_MODE |
+ OMAP3_OTG_SYSCONFIG_NO_IDLE_MODE, &otg->sysconfig);
+
+ /* Set the interface */
+ writel(OMAP3_OTG_INTERFSEL_OMAP, &otg->interfsel);
+
+ /* Clear force standby */
+ stdby = readl(&otg->forcestdby);
+ stdby &= ~OMAP3_OTG_FORCESTDBY_STANDBY;
+ writel(stdby, &otg->forcestdby);
+
+ platform_needs_initialization = 0;
+ }
+
+ ret = platform_needs_initialization;
+
+#ifdef CONFIG_TWL4030_USB
+end:
+#endif
+ return ret;
+
+}
+
+void musb_platform_deinit(void)
+{
+ /* noop */
+}
--- /dev/null
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This file is based on the file drivers/usb/musb/davinci.h
+ *
+ * This is the unique part of its copyright:
+ *
+ * --------------------------------------------------------------------
+ *
+ * Copyright (c) 2008 Texas Instruments
+ * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
+ *
+ * --------------------------------------------------------------------
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MUSB_OMAP3_H_
+#define _MUSB_OMAP3_H_
+
+#include "musb_core.h"
+
+/* Base address of MUSB registers */
+#define MENTOR_USB0_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
+
+/* Base address of OTG registers */
+#define OMAP3_OTG_BASE (MENTOR_USB0_BASE + 0x400)
+
+/* Timeout for USB module */
+#define OMAP3_USB_TIMEOUT 0x3FFFFFF
+
+int musb_platform_init(void);
+
+#endif /* _MUSB_OMAP3_H */
+
--- /dev/null
+#
+# Copyright (c) 2009 Wind River Systems, Inc.
+# Tom Rix <Tom.Rix@windriver.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)libusb_phy.a
+
+COBJS-$(CONFIG_TWL4030_USB) += twl4030.o
+COBJS-y := twl4030.o
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This is file is based on
+ * repository git.gitorious.org/u-boot-omap3/mainline.git,
+ * branch omap3-dev-usb, file drivers/usb/gadget/twl4030_usb.c
+ *
+ * This is the unique part of its copyright :
+ *
+ * ------------------------------------------------------------------------
+ *
+ * * (C) Copyright 2009 Atin Malaviya (atin.malaviya@gmail.com)
+ *
+ * Based on: twl4030_usb.c in linux 2.6 (drivers/i2c/chips/twl4030_usb.c)
+ * Copyright (C) 2004-2007 Texas Instruments
+ * Copyright (C) 2008 Nokia Corporation
+ * Contact: Felipe Balbi <felipe.balbi@nokia.com>
+ *
+ * Author: Atin Malaviya (atin.malaviya@gmail.com)
+ *
+ * ------------------------------------------------------------------------
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <twl4030.h>
+
+/* Defines for bits in registers */
+#define OPMODE_MASK (3 << 3)
+#define XCVRSELECT_MASK (3 << 0)
+#define CARKITMODE (1 << 2)
+#define OTG_ENAB (1 << 5)
+#define PHYPWD (1 << 0)
+#define CLOCKGATING_EN (1 << 2)
+#define CLK32K_EN (1 << 1)
+#define REQ_PHY_DPLL_CLK (1 << 0)
+#define PHY_DPLL_CLK (1 << 0)
+
+static int twl4030_usb_write(u8 address, u8 data)
+{
+ int ret;
+
+ ret = twl4030_i2c_write_u8(TWL4030_CHIP_USB, data, address);
+ if (ret != 0)
+ printf("TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
+
+ return ret;
+}
+
+static int twl4030_usb_read(u8 address)
+{
+ u8 data;
+ int ret;
+
+ ret = twl4030_i2c_read_u8(TWL4030_CHIP_USB, &data, address);
+ if (ret == 0)
+ ret = data;
+ else
+ printf("TWL4030:USB:Read[0x%x] Error %d\n", address, ret);
+
+ return ret;
+}
+
+static void twl4030_usb_ldo_init(void)
+{
+ /* Enable writing to power configuration registers */
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0xC0,
+ TWL4030_PM_MASTER_PROTECT_KEY);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x0C,
+ TWL4030_PM_MASTER_PROTECT_KEY);
+
+ /* put VUSB3V1 LDO in active state */
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00,
+ TWL4030_PM_RECEIVER_VUSB_DEDICATED2);
+
+ /* input to VUSB3V1 LDO is from VBAT, not VBUS */
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x14,
+ TWL4030_PM_RECEIVER_VUSB_DEDICATED1);
+
+ /* turn on 3.1V regulator */
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20,
+ TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00,
+ TWL4030_PM_RECEIVER_VUSB3V1_TYPE);
+
+ /* turn on 1.5V regulator */
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20,
+ TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00,
+ TWL4030_PM_RECEIVER_VUSB1V5_TYPE);
+
+ /* turn on 1.8V regulator */
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20,
+ TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00,
+ TWL4030_PM_RECEIVER_VUSB1V8_TYPE);
+
+ /* disable access to power configuration registers */
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x00,
+ TWL4030_PM_MASTER_PROTECT_KEY);
+}
+
+static void twl4030_phy_power(void)
+{
+ u8 pwr, clk;
+
+ /* Power the PHY */
+ pwr = twl4030_usb_read(TWL4030_USB_PHY_PWR_CTRL);
+ pwr &= ~PHYPWD;
+ twl4030_usb_write(TWL4030_USB_PHY_PWR_CTRL, pwr);
+ /* Enable clocks */
+ clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL);
+ clk |= CLOCKGATING_EN | CLK32K_EN;
+ twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk);
+}
+
+/*
+ * Initiaze the ULPI interface
+ * ULPI : Universal Transceiver Macrocell Low Pin Interface
+ * An interface between the USB link controller like musb and the
+ * the PHY or transceiver that drives the actual bus.
+ */
+int twl4030_usb_ulpi_init(void)
+{
+ long timeout = 1000 * 1000; /* 1 sec */;
+ u8 clk, sts, pwr;
+
+ /* twl4030 ldo init */
+ twl4030_usb_ldo_init();
+
+ /* Enable the twl4030 phy */
+ twl4030_phy_power();
+
+ /* Enable DPLL to access PHY registers over I2C */
+ clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL);
+ clk |= REQ_PHY_DPLL_CLK;
+ twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk);
+
+ /* Check if the PHY DPLL is locked */
+ sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS);
+ while (!(sts & PHY_DPLL_CLK) && 0 < timeout) {
+ udelay(10);
+ sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS);
+ timeout -= 10;
+ }
+
+ /* Final check */
+ sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS);
+ if (!(sts & PHY_DPLL_CLK)) {
+ printf("Error:TWL4030:USB Timeout setting PHY DPLL clock\n");
+ return -1;
+ }
+
+ /*
+ * There are two circuit blocks attached to the PHY,
+ * Carkit and USB OTG. Disable Carkit and enable USB OTG
+ */
+ twl4030_usb_write(TWL4030_USB_IFC_CTRL_CLR, CARKITMODE);
+ pwr = twl4030_usb_read(TWL4030_USB_POWER_CTRL);
+ pwr |= OTG_ENAB;
+ twl4030_usb_write(TWL4030_USB_POWER_CTRL_SET, pwr);
+
+ /* Clear the opmode bits to ensure normal encode */
+ twl4030_usb_write(TWL4030_USB_FUNC_CTRL_CLR, OPMODE_MASK);
+
+ /* Clear the xcvrselect bits to enable the high speed transeiver */
+ twl4030_usb_write(TWL4030_USB_FUNC_CTRL_CLR, XCVRSELECT_MASK);
+
+ /* Let ULPI control the DPLL clock */
+ clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL);
+ clk &= ~REQ_PHY_DPLL_CLK;
+ twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk);
+
+ return 0;
+}
#ifdef CONFIG_VIDEO_CORALP
#define VIDEO_FB_LITTLE_ENDIAN
#endif
+#ifdef CONFIG_VIDEO_MB862xx_ACCEL
#define VIDEO_HW_RECTFILL
#define VIDEO_HW_BITBLT
#endif
+#endif
/*****************************************************************************/
/* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc */
#else
#define SWAP16(x) (x)
#define SWAP32(x) (x)
-#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
+#if defined(VIDEO_FB_16BPP_WORD_SWAP)
#define SHORTSWAP32(x) ( ((x) >> 16) | ((x) << 16) )
#else
#define SHORTSWAP32(x) (x)
{ 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff } };
-int gunzip(void *, int, unsigned char *, unsigned long *);
-
/******************************************************************************/
static void video_drawchars (int xx, int yy, unsigned char *s, int count)
(GC_DISP_BASE | GC_L0PAL0) + \
((idx) << 2)), (val))
+#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
static void gdc_sw_reset (void)
{
GraphicDevice *dev = &mb862xx;
break;
}
}
+#endif
#if !defined(CONFIG_VIDEO_CORALP)
static void board_disp_init (void)
#endif
/*
- * Init drawing engine
+ * Init drawing engine if accel enabled.
+ * Also clears visible framebuffer.
*/
static void de_init (void)
{
GraphicDevice *dev = &mb862xx;
+#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
/* sync with SW access to framebuffer */
de_wait ();
+#else
+ unsigned int i, *p;
+
+ i = dev->winSizeX * dev->winSizeY;
+ p = (unsigned int *)dev->frameAdrs;
+ while (i--)
+ *p++ = 0;
+#endif
}
#if defined(CONFIG_VIDEO_CORALP)
}
#endif
+
+#if !defined(CONFIG_VIDEO_CORALP)
+int mb862xx_probe(unsigned int addr)
+{
+ GraphicDevice *dev = &mb862xx;
+ unsigned int reg;
+
+ dev->frameAdrs = addr;
+ dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
+
+ /* Try to access GDC ID/Revision registers */
+ reg = HOST_RD_REG (GC_CID);
+ reg = HOST_RD_REG (GC_CID);
+ if (reg == 0x303) {
+ reg = DE_RD_REG(GC_REV);
+ reg = DE_RD_REG(GC_REV);
+ if ((reg & ~0xff) == 0x20050100)
+ return MB862XX_TYPE_LIME;
+ }
+
+ return 0;
+}
+#endif
+
void *video_hw_init (void)
{
GraphicDevice *dev = &mb862xx;
if ((dev->frameAdrs = board_video_init ()) == 0) {
puts ("Controller not found!\n");
return NULL;
- } else
+ } else {
puts ("Lime\n");
+
+ /* Set Change of Clock Frequency Register */
+ HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
+ /* Delay required */
+ udelay(300);
+ /* Set Memory I/F Mode Register) */
+ HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
+ }
#endif
de_init ();
L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
}
+#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
/*
* Drawing engine Fill and BitBlt screen region
*/
DE_WR_FIFO ((height << 16) | width);
de_wait (); /* sync */
}
+#endif
EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/ctype.o
EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/div64.o
EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/string.o
+EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/time.o
EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/vsprintf.o
ifeq ($(ARCH),ppc)
EXT_SOBJ_FILES-$(CONFIG_API) += lib_ppc/ppcstring.o
ub_putc(c);
}
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
ub_udelay(usec);
}
ELF-ppc += sched
ELF-oxc += eepro100_eeprom
-ELF := $(ELF-y) $(ELF-$(ARCH)) $(ELF-$(BOARD)) $(ELF-$(CPU))
+#
+# Some versions of make do not handle trailing white spaces properly;
+# leading to build failures. The problem was found with GNU Make 3.80.
+# Using 'strip' as a workaround for the problem.
+#
+ELF := $(strip $(ELF-y) $(ELF-$(ARCH)) $(ELF-$(BOARD)) $(ELF-$(CPU)))
+
SREC = $(addsuffix .srec,$(ELF))
BIN = $(addsuffix .bin,$(ELF))
+++ /dev/null
-/*
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-OUTPUT_FORMAT("elf32-littlenios2")
-OUTPUT_ARCH(nios2)
-ENTRY(_start)
-
-SECTIONS
-{
- .text :
- {
- *(.text)
- *(.text.*)
- *(.gnu.linkonce.t*)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- *(.gnu.linkonce.r*)
- }
- . = ALIGN (4);
- _etext = .;
- PROVIDE (etext = .);
-
- /* INIT DATA sections - "Small" data (see the gcc -G option)
- * is always gp-relative. Here we make all init data sections
- * adjacent to simplify the startup code -- and provide
- * the global pointer for gp-relative access.
- */
- _data = .;
- .data :
- {
- *(.data)
- *(.data.*)
- *(.gnu.linkonce.d*)
- }
-
- . = ALIGN(16);
- _gp = .; /* Global pointer addr */
- PROVIDE (gp = .);
-
- .sdata :
- {
- *(.sdata)
- *(.sdata.*)
- *(.gnu.linkonce.s.*)
- }
- . = ALIGN(4);
-
- _edata = .;
- PROVIDE (edata = .);
-
- /* UNINIT DATA - Small uninitialized data is first so it's
- * adjacent to sdata and can be referenced via gp. The normal
- * bss follows. We keep it adjacent to simplify init code.
- */
- __bss_start = .;
- .sbss (NOLOAD) :
- {
- *(.sbss)
- *(.sbss.*)
- *(.gnu.linkonce.sb.*)
- *(.scommon)
- }
- . = ALIGN(4);
- .bss (NOLOAD) :
- {
- *(.bss)
- *(.bss.*)
- *(.dynbss)
- *(COMMON)
- *(.scommon)
- }
- . = ALIGN(4);
- _end = .;
- PROVIDE (end = .);
-
- /* CMD TABLE - uboot command sections
- */
- . = .;
- __uboot_cmd_start = .;
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- }
- . = ALIGN(4);
- __u_boot_cmd_end = .;
-
- /* DEBUG -- symbol table, string table, etc. etc.
- */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- .debug_info 0 : { *(.debug_info) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_line 0 : { *(.debug_line) }
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
-}
struct eth_device { unsigned long iobase; };
#include "../drivers/net/smc91111.h"
-#ifdef CONFIG_SMC91111
-
#ifndef SMC91111_EEPROM_INIT
# define SMC91111_EEPROM_INIT()
#endif
printf ("\n");
}
}
-
-#else
-
-int smc91111_eeprom (int argc, char *argv[])
-{
- printf("Not supported for this board\n");
- return 1;
-}
-
-#endif
* smc911x_eeprom.c - EEPROM interface to SMC911x parts.
* Only tested on SMSC9118 though ...
*
- * Copyright 2004-2008 Analog Devices Inc.
+ * Copyright 2004-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*
#include <common.h>
#include <exports.h>
-#ifdef CONFIG_DRIVER_SMC911X
-
+/* the smc911x.h gets base addr through eth_device' iobase */
+struct eth_device {
+ const char *name;
+ unsigned long iobase;
+ void *priv;
+};
#include "../drivers/net/smc911x.h"
/**
* Registers 0x00 - 0x50 are FIFOs. The 0x50+ are the control registers
* and they're all 32bits long. 0xB8+ are reserved, so don't bother.
*/
-static void dump_regs(void)
+static void dump_regs(struct eth_device *dev)
{
u8 i, j = 0;
for (i = 0x50; i < 0xB8; i += sizeof(u32))
printf("%02x: 0x%08x %c", i,
- smc911x_reg_read(CONFIG_DRIVER_SMC911X_BASE + i),
+ smc911x_reg_read(dev, i),
(j++ % 2 ? '\n' : ' '));
}
/**
* do_eeprom_cmd - handle eeprom communication
*/
-static int do_eeprom_cmd(int cmd, u8 reg)
+static int do_eeprom_cmd(struct eth_device *dev, int cmd, u8 reg)
{
- if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY) {
+ if (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY) {
printf("eeprom_cmd: busy at start (E2P_CMD = 0x%08x)\n",
- smc911x_reg_read(E2P_CMD));
+ smc911x_reg_read(dev, E2P_CMD));
return -1;
}
- smc911x_reg_write(E2P_CMD, E2P_CMD_EPC_BUSY | cmd | reg);
+ smc911x_reg_write(dev, E2P_CMD, E2P_CMD_EPC_BUSY | cmd | reg);
- while (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
+ while (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
if (smsc_ctrlc()) {
printf("eeprom_cmd: timeout (E2P_CMD = 0x%08x)\n",
- smc911x_reg_read(E2P_CMD));
+ smc911x_reg_read(dev, E2P_CMD));
return -1;
}
/**
* read_eeprom_reg - read specified register in EEPROM
*/
-static u8 read_eeprom_reg(u8 reg)
+static u8 read_eeprom_reg(struct eth_device *dev, u8 reg)
{
- int ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_READ, reg);
- return (ret ? : smc911x_reg_read(E2P_DATA));
+ int ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_READ, reg);
+ return (ret ? : smc911x_reg_read(dev, E2P_DATA));
}
/**
* write_eeprom_reg - write specified value into specified register in EEPROM
*/
-static int write_eeprom_reg(u8 value, u8 reg)
+static int write_eeprom_reg(struct eth_device *dev, u8 value, u8 reg)
{
int ret;
/* enable erasing/writing */
- ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_EWEN, reg);
+ ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_EWEN, reg);
if (ret)
goto done;
/* erase the eeprom reg */
- ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_ERASE, reg);
+ ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_ERASE, reg);
if (ret)
goto done;
/* write the eeprom reg */
- smc911x_reg_write(E2P_DATA, value);
- ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_WRITE, reg);
+ smc911x_reg_write(dev, E2P_DATA, value);
+ ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_WRITE, reg);
if (ret)
goto done;
/* disable erasing/writing */
- ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_EWDS, reg);
+ ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_EWDS, reg);
done:
return ret;
/**
* write_stuff - handle writing of MAC registers / eeprom
*/
-static void write_stuff(char *line)
+static void write_stuff(struct eth_device *dev, char *line)
{
char dest;
char *endp;
/* Finally, execute the command */
if (dest == 'E') {
printf("Writing EEPROM register %02x with %02x\n", reg, value);
- write_eeprom_reg(value, reg);
+ write_eeprom_reg(dev, value, reg);
} else {
printf("Writing MAC register %02x with %08x\n", reg, value);
- smc911x_reg_write(CONFIG_DRIVER_SMC911X_BASE + reg, value);
+ smc911x_reg_write(dev, reg, value);
}
}
/**
* copy_from_eeprom - copy MAC address in eeprom to address registers
*/
-static void copy_from_eeprom(void)
+static void copy_from_eeprom(struct eth_device *dev)
{
ulong addrl =
- read_eeprom_reg(0x01) |
- read_eeprom_reg(0x02) << 8 |
- read_eeprom_reg(0x03) << 16 |
- read_eeprom_reg(0x04) << 24;
+ read_eeprom_reg(dev, 0x01) |
+ read_eeprom_reg(dev, 0x02) << 8 |
+ read_eeprom_reg(dev, 0x03) << 16 |
+ read_eeprom_reg(dev, 0x04) << 24;
ulong addrh =
- read_eeprom_reg(0x05) |
- read_eeprom_reg(0x06) << 8;
- smc911x_set_mac_csr(ADDRL, addrl);
- smc911x_set_mac_csr(ADDRH, addrh);
+ read_eeprom_reg(dev, 0x05) |
+ read_eeprom_reg(dev, 0x06) << 8;
+ smc911x_set_mac_csr(dev, ADDRL, addrl);
+ smc911x_set_mac_csr(dev, ADDRH, addrh);
puts("EEPROM contents copied to MAC\n");
}
/**
* print_macaddr - print MAC address registers and MAC address in eeprom
*/
-static void print_macaddr(void)
+static void print_macaddr(struct eth_device *dev)
{
puts("Current MAC Address in MAC: ");
- ulong addrl = smc911x_get_mac_csr(ADDRL);
- ulong addrh = smc911x_get_mac_csr(ADDRH);
+ ulong addrl = smc911x_get_mac_csr(dev, ADDRL);
+ ulong addrh = smc911x_get_mac_csr(dev, ADDRH);
printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
(u8)(addrl), (u8)(addrl >> 8), (u8)(addrl >> 16),
(u8)(addrl >> 24), (u8)(addrh), (u8)(addrh >> 8));
puts("Current MAC Address in EEPROM: ");
int i;
for (i = 1; i < 6; ++i)
- printf("%02x:", read_eeprom_reg(i));
- printf("%02x\n", read_eeprom_reg(i));
+ printf("%02x:", read_eeprom_reg(dev, i));
+ printf("%02x\n", read_eeprom_reg(dev, i));
}
/**
* dump_eeprom - dump the whole content of the EEPROM
*/
-static void dump_eeprom(void)
+static void dump_eeprom(struct eth_device *dev)
{
int i;
puts("EEPROM:\n");
for (i = 0; i < 7; ++i)
- printf("%02x: 0x%02x\n", i, read_eeprom_reg(i));
+ printf("%02x: 0x%02x\n", i, read_eeprom_reg(dev, i));
}
/**
* smc911x_init - get the MAC/EEPROM up and ready for use
*/
-static int smc911x_init(void)
+static int smc911x_init(struct eth_device *dev)
{
/* See if there is anything there */
- if (!smc911x_detect_chip())
+ if (!smc911x_detect_chip(dev))
return 1;
- smc911x_reset();
+ smc911x_reset(dev);
/* Make sure we set EEDIO/EECLK to the EEPROM */
- if (smc911x_reg_read(GPIO_CFG) & GPIO_CFG_EEPR_EN) {
- while (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
+ if (smc911x_reg_read(dev, GPIO_CFG) & GPIO_CFG_EEPR_EN) {
+ while (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
if (smsc_ctrlc()) {
printf("init: timeout (E2P_CMD = 0x%08x)\n",
- smc911x_reg_read(E2P_CMD));
+ smc911x_reg_read(dev, E2P_CMD));
return 1;
}
- smc911x_reg_write(GPIO_CFG, smc911x_reg_read(GPIO_CFG) & ~GPIO_CFG_EEPR_EN);
+ smc911x_reg_write(dev, GPIO_CFG,
+ smc911x_reg_read(dev, GPIO_CFG) & ~GPIO_CFG_EEPR_EN);
}
return 0;
*/
int smc911x_eeprom(int argc, char *argv[])
{
+ /* Avoid initializing on stack as gcc likes to call memset() */
+ struct eth_device dev;
+ dev.name = __func__;
+ dev.iobase = CONFIG_SMC911X_BASE;
+
/* Print the ABI version */
app_startup(argv);
if (XF_VERSION != get_version()) {
/* Initialize the MAC/EEPROM somewhat */
puts("\n");
- if (smc911x_init())
+ if (smc911x_init(&dev))
return 1;
/* Dump helpful usage information */
/* Now parse the command */
switch (line[0]) {
- case 'W': write_stuff(line); break;
- case 'D': dump_eeprom(); break;
- case 'M': dump_regs(); break;
- case 'C': copy_from_eeprom(); break;
- case 'P': print_macaddr(); break;
+ case 'W': write_stuff(&dev, line); break;
+ case 'D': dump_eeprom(&dev); break;
+ case 'M': dump_regs(&dev); break;
+ case 'C': copy_from_eeprom(&dev); break;
+ case 'P': print_macaddr(&dev); break;
unknown_cmd:
default: puts("ERROR: Unknown command!\n\n");
case '?':
}
}
}
-
-#else
-int smc911x_eeprom(int argc, char *argv[])
-{
- puts("Not supported for this board\n");
- return 1;
-}
-#endif
uint32_t *indir2_block = NULL;
int indir2_size = 0;
int indir2_blkno = -1;
+static unsigned int inode_size;
static int ext2fs_blockgroup
unsigned int blkoff;
#ifdef DEBUG
- printf ("ext2fs read inode %d\n", ino);
+ printf ("ext2fs read inode %d, inode_size %d\n", ino, inode_size);
#endif
/* It is easier to calculate if the first inode is 0. */
ino--;
return (0);
}
- inodes_per_block = EXT2_BLOCK_SIZE(data) / __le16_to_cpu(sblock->inode_size);
-
-#ifdef DEBUG
- printf ("ext2fs read inode blkno %d blkoff %d\n", blkno, blkoff);
-#endif
+ inodes_per_block = EXT2_BLOCK_SIZE(data) / inode_size;
blkno = __le32_to_cpu (blkgrp.inode_table_id) +
(ino % __le32_to_cpu (sblock->inodes_per_group))
/ inodes_per_block;
- blkoff = (ino % inodes_per_block) * __le16_to_cpu (sblock->inode_size);
+ blkoff = (ino % inodes_per_block) * inode_size;
#ifdef DEBUG
printf ("ext2fs read inode blkno %d blkoff %d\n", blkno, blkoff);
#endif
if (__le16_to_cpu (data->sblock.magic) != EXT2_MAGIC) {
goto fail;
}
+ if (__le32_to_cpu(data->sblock.revision_level == 0)) {
+ inode_size = 128;
+ } else {
+ inode_size = __le16_to_cpu(data->sblock.inode_size);
+ }
+#ifdef DEBUG
+ printf("EXT2 rev %d, inode_size %d\n",
+ __le32_to_cpu(data->sblock.revision_level), inode_size);
+#endif
data->diropen.data = data;
data->diropen.ino = 2;
data->diropen.inode_read = 1;
#include "ubifs.h"
#include <u-boot/zlib.h>
-#if !defined(CONFIG_SYS_64BIT_VSPRINTF)
-#warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output!
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
/* compress.c */
/* todo: Move these to a common U-Boot header */
int lzo1x_decompress_safe(const unsigned char *in, size_t in_len,
unsigned char *out, size_t *out_len);
-
-int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp,
- int stoponerr, int offset);
#endif /* !__UBIFS_H__ */
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
#define I2C_BASE_ADDR (0xEF600500 + I2C_BUS_OFFS)
#endif
-#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
-#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
-#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
-#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
-#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
-#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
-#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
-#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS)
-#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
-#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
-#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
-#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IIC0_CLKDIV)
-#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
-#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
-#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
-#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
+struct ppc4xx_i2c {
+ u8 mdbuf;
+ u8 res1;
+ u8 sdbuf;
+ u8 res2;
+ u8 lmadr;
+ u8 hmadr;
+ u8 cntl;
+ u8 mdcntl;
+ u8 sts;
+ u8 extsts;
+ u8 lsadr;
+ u8 hsadr;
+ u8 clkdiv;
+ u8 intrmsk;
+ u8 xfrcnt;
+ u8 xtcntlss;
+ u8 directcntl;
+ u8 intr;
+};
/* MDCNTL Register Bit definition */
#define IIC_MDCNTL_HSCL 0x01
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __A320_H
+#define __A320_H
+
+/*
+ * Hardware register bases
+ */
+#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */
+#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */
+#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */
+#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */
+#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */
+#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */
+#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/
+
+#endif /* __A320_H */
+
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Power Management Unit
+ */
+#ifndef __FTPMU010_H
+#define __FTPMU010_H
+
+struct ftpmu010 {
+ unsigned int IDNMBR0; /* 0x00 */
+ unsigned int reserved0; /* 0x04 */
+ unsigned int OSCC; /* 0x08 */
+ unsigned int PMODE; /* 0x0C */
+ unsigned int PMCR; /* 0x10 */
+ unsigned int PED; /* 0x14 */
+ unsigned int PEDSR; /* 0x18 */
+ unsigned int reserved1; /* 0x1C */
+ unsigned int PMSR; /* 0x20 */
+ unsigned int PGSR; /* 0x24 */
+ unsigned int MFPSR; /* 0x28 */
+ unsigned int MISC; /* 0x2C */
+ unsigned int PDLLCR0; /* 0x30 */
+ unsigned int PDLLCR1; /* 0x34 */
+ unsigned int AHBMCLKOFF; /* 0x38 */
+ unsigned int APBMCLKOFF; /* 0x3C */
+ unsigned int DCSRCR0; /* 0x40 */
+ unsigned int DCSRCR1; /* 0x44 */
+ unsigned int DCSRCR2; /* 0x48 */
+ unsigned int SDRAMHTC; /* 0x4C */
+ unsigned int PSPR0; /* 0x50 */
+ unsigned int PSPR1; /* 0x54 */
+ unsigned int PSPR2; /* 0x58 */
+ unsigned int PSPR3; /* 0x5C */
+ unsigned int PSPR4; /* 0x60 */
+ unsigned int PSPR5; /* 0x64 */
+ unsigned int PSPR6; /* 0x68 */
+ unsigned int PSPR7; /* 0x6C */
+ unsigned int PSPR8; /* 0x70 */
+ unsigned int PSPR9; /* 0x74 */
+ unsigned int PSPR10; /* 0x78 */
+ unsigned int PSPR11; /* 0x7C */
+ unsigned int PSPR12; /* 0x80 */
+ unsigned int PSPR13; /* 0x84 */
+ unsigned int PSPR14; /* 0x88 */
+ unsigned int PSPR15; /* 0x8C */
+ unsigned int AHBDMA_RACCS; /* 0x90 */
+ unsigned int reserved2; /* 0x94 */
+ unsigned int reserved3; /* 0x98 */
+ unsigned int JSS; /* 0x9C */
+ unsigned int CFC_RACC; /* 0xA0 */
+ unsigned int SSP1_RACC; /* 0xA4 */
+ unsigned int UART1TX_RACC; /* 0xA8 */
+ unsigned int UART1RX_RACC; /* 0xAC */
+ unsigned int UART2TX_RACC; /* 0xB0 */
+ unsigned int UART2RX_RACC; /* 0xB4 */
+ unsigned int SDC_RACC; /* 0xB8 */
+ unsigned int I2SAC97_RACC; /* 0xBC */
+ unsigned int IRDATX_RACC; /* 0xC0 */
+ unsigned int reserved4; /* 0xC4 */
+ unsigned int USBD_RACC; /* 0xC8 */
+ unsigned int IRDARX_RACC; /* 0xCC */
+ unsigned int IRDA_RACC; /* 0xD0 */
+ unsigned int ED0_RACC; /* 0xD4 */
+ unsigned int ED1_RACC; /* 0xD8 */
+};
+
+/*
+ * ID Number 0 Register
+ */
+#define FTPMU010_ID_A320A 0x03200000
+#define FTPMU010_ID_A320C 0x03200010
+#define FTPMU010_ID_A320D 0x03200030
+
+/*
+ * OSC Control Register
+ */
+#define FTPMU010_OSCC_OSCH_TRI (1 << 11)
+#define FTPMU010_OSCC_OSCH_STABLE (1 << 9)
+#define FTPMU010_OSCC_OSCH_OFF (1 << 8)
+
+#define FTPMU010_OSCC_OSCL_TRI (1 << 3)
+#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2)
+#define FTPMU010_OSCC_OSCL_STABLE (1 << 1)
+#define FTPMU010_OSCC_OSCL_OFF (1 << 0)
+
+/*
+ * Power Mode Register
+ */
+#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7)
+#define FTPMU010_PMODE_FCS (1 << 2)
+#define FTPMU010_PMODE_TURBO (1 << 1)
+#define FTPMU010_PMODE_SLEEP (1 << 0)
+
+/*
+ * Power Manager Status Register
+ */
+#define FTPMU010_PMSR_SMR (1 << 10)
+
+#define FTPMU010_PMSR_RDH (1 << 2)
+#define FTPMU010_PMSR_PH (1 << 1)
+#define FTPMU010_PMSR_CKEHLOW (1 << 0)
+
+/*
+ * Multi-Function Port Setting Register
+ */
+#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14)
+#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13)
+#define FTPMU010_MFPSR_AC97PINSEL (1 << 3)
+
+/*
+ * PLL/DLL Control Register 0
+ */
+#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) >> 20) & 0xf)
+#define FTPMU010_PDLLCR0_DLLFRAG (1 << 19)
+#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18)
+#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17)
+#define FTPMU010_PDLLCR0_DLLDIS (1 << 16)
+#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) >> 3) & 0x1ff)
+#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2)
+#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1)
+#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0)
+
+#endif /* __FTPMU010_H */
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * SDRAM Controller
+ */
+#ifndef __FTSDMC020_H
+#define __FTSDMC020_H
+
+#define FTSDMC020_OFFSET_TP0 0x00
+#define FTSDMC020_OFFSET_TP1 0x04
+#define FTSDMC020_OFFSET_CR 0x08
+#define FTSDMC020_OFFSET_BANK0_BSR 0x0C
+#define FTSDMC020_OFFSET_BANK1_BSR 0x10
+#define FTSDMC020_OFFSET_BANK2_BSR 0x14
+#define FTSDMC020_OFFSET_BANK3_BSR 0x18
+#define FTSDMC020_OFFSET_BANK4_BSR 0x1C
+#define FTSDMC020_OFFSET_BANK5_BSR 0x20
+#define FTSDMC020_OFFSET_BANK6_BSR 0x24
+#define FTSDMC020_OFFSET_BANK7_BSR 0x28
+#define FTSDMC020_OFFSET_ACR 0x34
+
+/*
+ * Timing Parametet 0 Register
+ */
+#define FTSDMC020_TP0_TCL(x) ((x) & 0x3)
+#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4)
+#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8)
+#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12)
+#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16)
+#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20)
+
+/*
+ * Timing Parametet 1 Register
+ */
+#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff)
+#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16)
+#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20)
+
+/*
+ * Configuration Register
+ */
+#define FTSDMC020_CR_SREF (1 << 0)
+#define FTSDMC020_CR_PWDN (1 << 1)
+#define FTSDMC020_CR_ISMR (1 << 2)
+#define FTSDMC020_CR_IREF (1 << 3)
+#define FTSDMC020_CR_IPREC (1 << 4)
+#define FTSDMC020_CR_REFTYPE (1 << 5)
+
+/*
+ * SDRAM External Bank Base/Size Register
+ */
+#define FTSDMC020_BANK_ENABLE (1 << 28)
+
+#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16)
+
+#define FTSDMC020_BANK_DDW_X4 (0 << 12)
+#define FTSDMC020_BANK_DDW_X8 (1 << 12)
+#define FTSDMC020_BANK_DDW_X16 (2 << 12)
+#define FTSDMC020_BANK_DDW_X32 (3 << 12)
+
+#define FTSDMC020_BANK_DSZ_16M (0 << 8)
+#define FTSDMC020_BANK_DSZ_64M (1 << 8)
+#define FTSDMC020_BANK_DSZ_128M (2 << 8)
+#define FTSDMC020_BANK_DSZ_256M (3 << 8)
+
+#define FTSDMC020_BANK_MBW_8 (0 << 4)
+#define FTSDMC020_BANK_MBW_16 (1 << 4)
+#define FTSDMC020_BANK_MBW_32 (2 << 4)
+
+#define FTSDMC020_BANK_SIZE_1M 0x0
+#define FTSDMC020_BANK_SIZE_2M 0x1
+#define FTSDMC020_BANK_SIZE_4M 0x2
+#define FTSDMC020_BANK_SIZE_8M 0x3
+#define FTSDMC020_BANK_SIZE_16M 0x4
+#define FTSDMC020_BANK_SIZE_32M 0x5
+#define FTSDMC020_BANK_SIZE_64M 0x6
+#define FTSDMC020_BANK_SIZE_128M 0x7
+#define FTSDMC020_BANK_SIZE_256M 0x8
+
+/*
+ * Arbiter Control Register
+ */
+#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f)
+#define FTSDMC020_ACR_TOE (1 << 8)
+
+#endif /* __FTSDMC020_H */
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Static Memory Controller
+ */
+#ifndef __FTSMC020_H
+#define __FTSMC020_H
+
+#ifndef __ASSEMBLY__
+
+struct ftsmc020 {
+ struct {
+ unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */
+ unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */
+ } bank[4];
+ unsigned int pad[8]; /* 0x20 - 0x3c */
+ unsigned int ssr; /* 0x40 */
+};
+
+void ftsmc020_init(void);
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Memory Bank Configuration Register
+ */
+#define FTSMC020_BANK_ENABLE (1 << 28)
+#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000)
+
+#define FTSMC020_BANK_WPROT (1 << 11)
+
+#define FTSMC020_BANK_SIZE_32K (0xb << 4)
+#define FTSMC020_BANK_SIZE_64K (0xc << 4)
+#define FTSMC020_BANK_SIZE_128K (0xd << 4)
+#define FTSMC020_BANK_SIZE_256K (0xe << 4)
+#define FTSMC020_BANK_SIZE_512K (0xf << 4)
+#define FTSMC020_BANK_SIZE_1M (0x0 << 4)
+#define FTSMC020_BANK_SIZE_2M (0x1 << 4)
+#define FTSMC020_BANK_SIZE_4M (0x2 << 4)
+#define FTSMC020_BANK_SIZE_8M (0x3 << 4)
+#define FTSMC020_BANK_SIZE_16M (0x4 << 4)
+#define FTSMC020_BANK_SIZE_32M (0x5 << 4)
+
+#define FTSMC020_BANK_MBW_8 (0x0 << 0)
+#define FTSMC020_BANK_MBW_16 (0x1 << 0)
+#define FTSMC020_BANK_MBW_32 (0x2 << 0)
+
+/*
+ * Memory Bank Timing Parameter Register
+ */
+#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28)
+#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24)
+#define FTSMC020_TPR_RBE (1 << 20)
+#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18)
+#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16)
+#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12)
+#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8)
+#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6)
+#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4)
+#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0)
+
+#endif /* __FTSMC020_H */
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Timer
+ */
+#ifndef __FTTMR010_H
+#define __FTTMR010_H
+
+struct fttmr010 {
+ unsigned int timer1_counter; /* 0x00 */
+ unsigned int timer1_load; /* 0x04 */
+ unsigned int timer1_match1; /* 0x08 */
+ unsigned int timer1_match2; /* 0x0c */
+ unsigned int timer2_counter; /* 0x10 */
+ unsigned int timer2_load; /* 0x14 */
+ unsigned int timer2_match1; /* 0x18 */
+ unsigned int timer2_match2; /* 0x1c */
+ unsigned int timer3_counter; /* 0x20 */
+ unsigned int timer3_load; /* 0x24 */
+ unsigned int timer3_match1; /* 0x28 */
+ unsigned int timer3_match2; /* 0x2c */
+ unsigned int cr; /* 0x30 */
+ unsigned int interrupt_state; /* 0x34 */
+ unsigned int interrupt_mask; /* 0x38 */
+};
+
+/*
+ * Timer Control Register
+ */
+#define FTTMR010_TM3_UPDOWN (1 << 11)
+#define FTTMR010_TM2_UPDOWN (1 << 10)
+#define FTTMR010_TM1_UPDOWN (1 << 9)
+#define FTTMR010_TM3_OFENABLE (1 << 8)
+#define FTTMR010_TM3_CLOCK (1 << 7)
+#define FTTMR010_TM3_ENABLE (1 << 6)
+#define FTTMR010_TM2_OFENABLE (1 << 5)
+#define FTTMR010_TM2_CLOCK (1 << 4)
+#define FTTMR010_TM2_ENABLE (1 << 3)
+#define FTTMR010_TM1_OFENABLE (1 << 2)
+#define FTTMR010_TM1_CLOCK (1 << 1)
+#define FTTMR010_TM1_ENABLE (1 << 0)
+
+/*
+ * Timer Interrupt State & Mask Registers
+ */
+#define FTTMR010_TM3_OVERFLOW (1 << 8)
+#define FTTMR010_TM3_MATCH2 (1 << 7)
+#define FTTMR010_TM3_MATCH1 (1 << 6)
+#define FTTMR010_TM2_OVERFLOW (1 << 5)
+#define FTTMR010_TM2_MATCH2 (1 << 4)
+#define FTTMR010_TM2_MATCH1 (1 << 3)
+#define FTTMR010_TM1_OVERFLOW (1 << 2)
+#define FTTMR010_TM1_MATCH2 (1 << 1)
+#define FTTMR010_TM1_MATCH1 (1 << 0)
+
+#endif /* __FTTMR010_H */
dv_reg NANDFCR;
dv_reg NANDFSR;
u_int8_t RSVD1[8];
- dv_reg NANDF1ECC;
- dv_reg NANDF2ECC;
- dv_reg NANDF3ECC;
- dv_reg NANDF4ECC;
+ dv_reg NANDFECC[4];
u_int8_t RSVD2[60];
dv_reg NAND4BITECCLOAD;
dv_reg NAND4BITECC1;
} emif_registers;
typedef emif_registers *emifregs;
+
+#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2))
+#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
+#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4)
+#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2)))
+#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
+#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
+
#endif
#ifndef _GPIO_DEFS_H_
#define _GPIO_DEFS_H_
+#ifndef CONFIG_SOC_DA8XX
#define DAVINCI_GPIO_BINTEN 0x01C67008
#define DAVINCI_GPIO_BANK01 0x01C67010
#define DAVINCI_GPIO_BANK23 0x01C67038
#define DAVINCI_GPIO_BANK45 0x01C67060
#define DAVINCI_GPIO_BANK67 0x01C67088
+#else /* CONFIG_SOC_DA8XX */
+#define DAVINCI_GPIO_BINTEN 0x01E26008
+#define DAVINCI_GPIO_BANK01 0x01E26010
+#define DAVINCI_GPIO_BANK23 0x01E26038
+#define DAVINCI_GPIO_BANK45 0x01E26060
+#define DAVINCI_GPIO_BANK67 0x01E26088
+#endif /* CONFIG_SOC_DA8XX */
+
struct davinci_gpio {
unsigned int dir;
unsigned int out_data;
unsigned long base;
};
+#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01)
+#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
+#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
+#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
+
#endif
* on other DaVinci chips. Double check them before you try
* using the addresses ... or PSC module identifiers, etc.
*/
+#ifndef CONFIG_SOC_DA8XX
+
#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
#endif
+#else /* CONFIG_SOC_DA8XX */
+
+#define DAVINCI_UART0_BASE 0x01c42000
+#define DAVINCI_UART1_BASE 0x01d0c000
+#define DAVINCI_UART2_BASE 0x01d0d000
+#define DAVINCI_I2C0_BASE 0x01c22000
+#define DAVINCI_I2C1_BASE 0x01e28000
+#define DAVINCI_TIMER0_BASE 0x01c20000
+#define DAVINCI_TIMER1_BASE 0x01c21000
+#define DAVINCI_WDOG_BASE 0x01c21000
+#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
+#define DAVINCI_PSC0_BASE 0x01c10000
+#define DAVINCI_PSC1_BASE 0x01e27000
+#define DAVINCI_SPI0_BASE 0x01c41000
+#define DAVINCI_USB_OTG_BASE 0x01e00000
+#define DAVINCI_SPI1_BASE 0x01e12000
+#define DAVINCI_GPIO_BASE 0x01e26000
+#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
+#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
+#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
+#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
+#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
+#define DAVINCI_INTC_BASE 0xfffee000
+#define DAVINCI_BOOTCFG_BASE 0x01c14000
+
+#endif /* CONFIG_SOC_DA8XX */
+
/* Power and Sleep Controller (PSC) Domains */
#define DAVINCI_GPSC_ARMDOMAIN 0
#define DAVINCI_GPSC_DSPDOMAIN 1
+#ifndef CONFIG_SOC_DA8XX
+
#define DAVINCI_LPSC_VPSSMSTR 0
#define DAVINCI_LPSC_VPSSSLV 1
#define DAVINCI_LPSC_TPCC 2
#define DAVINCI_DM646X_LPSC_UART0 26
#define DAVINCI_DM646X_LPSC_I2C 31
+#else /* CONFIG_SOC_DA8XX */
+
+enum davinci_lpsc_ids {
+ DAVINCI_LPSC_TPCC = 0,
+ DAVINCI_LPSC_TPTC0,
+ DAVINCI_LPSC_TPTC1,
+ DAVINCI_LPSC_AEMIF,
+ DAVINCI_LPSC_SPI0,
+ DAVINCI_LPSC_MMC_SD,
+ DAVINCI_LPSC_AINTC,
+ DAVINCI_LPSC_ARM_RAM_ROM,
+ DAVINCI_LPSC_SECCTL_KEYMGR,
+ DAVINCI_LPSC_UART0,
+ DAVINCI_LPSC_SCR0,
+ DAVINCI_LPSC_SCR1,
+ DAVINCI_LPSC_SCR2,
+ DAVINCI_LPSC_DMAX,
+ DAVINCI_LPSC_ARM,
+ DAVINCI_LPSC_GEM,
+ /* for LPSCs in PSC1, offset from 32 for differentiation */
+ DAVINCI_LPSC_PSC1_BASE = 32,
+ DAVINCI_LPSC_USB11,
+ DAVINCI_LPSC_USB20,
+ DAVINCI_LPSC_GPIO,
+ DAVINCI_LPSC_UHPI,
+ DAVINCI_LPSC_EMAC,
+ DAVINCI_LPSC_DDR_EMIF,
+ DAVINCI_LPSC_McASP0,
+ DAVINCI_LPSC_McASP1,
+ DAVINCI_LPSC_McASP2,
+ DAVINCI_LPSC_SPI1,
+ DAVINCI_LPSC_I2C1,
+ DAVINCI_LPSC_UART1,
+ DAVINCI_LPSC_UART2,
+ DAVINCI_LPSC_LCDC,
+ DAVINCI_LPSC_ePWM,
+ DAVINCI_LPSC_eCAP,
+ DAVINCI_LPSC_eQEP,
+ DAVINCI_LPSC_SCR_P0,
+ DAVINCI_LPSC_SCR_P1,
+ DAVINCI_LPSC_CR_P3,
+ DAVINCI_LPSC_L3_CBA_RAM
+};
+
+#endif /* CONFIG_SOC_DA8XX */
+
void lpsc_on(unsigned int id);
void dsp_on(void);
void davinci_enable_i2c(void);
void davinci_errata_workarounds(void);
+#ifndef CONFIG_SOC_DA8XX
+
/* Some PSC defines */
#define PSC_CHP_SHRTSW (0x01c40038)
#define PSC_GBLCTL (0x01c41010)
#define PSC_SILVER_BULLET (0x01c41a20)
+#else /* CONFIG_SOC_DA8XX */
+
+#define PSC_PSC0_MODULE_ID_CNT 16
+#define PSC_PSC1_MODULE_ID_CNT 32
+
+struct davinci_psc_regs {
+ dv_reg revid;
+ dv_reg rsvd0[71];
+ dv_reg ptcmd;
+ dv_reg rsvd1;
+ dv_reg ptstat;
+ dv_reg rsvd2[437];
+ union {
+ struct {
+ dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];
+ dv_reg rsvd3[112];
+ dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];
+ } psc0;
+ struct {
+ dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT];
+ dv_reg rsvd3[96];
+ dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT];
+ } psc1;
+ };
+};
+
+#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
+#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
+
+#endif /* CONFIG_SOC_DA8XX */
+
+#ifndef CONFIG_SOC_DA8XX
+
/* Miscellania... */
#define VBPR (0x20000020)
#define PINMUX3 0x01c4000c
#define PINMUX4 0x01c40010
+#else /* CONFIG_SOC_DA8XX */
+
+struct davinci_pllc_regs {
+ dv_reg revid;
+ dv_reg rsvd1[56];
+ dv_reg rstype;
+ dv_reg rsvd2[6];
+ dv_reg pllctl;
+ dv_reg ocsel;
+ dv_reg rsvd3[2];
+ dv_reg pllm;
+ dv_reg prediv;
+ dv_reg plldiv1;
+ dv_reg plldiv2;
+ dv_reg plldiv3;
+ dv_reg oscdiv;
+ dv_reg postdiv;
+ dv_reg rsvd4[3];
+ dv_reg pllcmd;
+ dv_reg pllstat;
+ dv_reg alnctl;
+ dv_reg dchange;
+ dv_reg cken;
+ dv_reg ckstat;
+ dv_reg systat;
+ dv_reg rsvd5[3];
+ dv_reg plldiv4;
+ dv_reg plldiv5;
+ dv_reg plldiv6;
+ dv_reg plldiv7;
+ dv_reg rsvd6[32];
+ dv_reg emucnt0;
+ dv_reg emucnt1;
+};
+
+#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define DAVINCI_PLLC_DIV_MASK 0x1f
+
+/* Clock IDs */
+enum davinci_clk_ids {
+ DAVINCI_SPI0_CLKID = 2,
+ DAVINCI_UART2_CLKID = 2,
+ DAVINCI_MDIO_CLKID = 4,
+ DAVINCI_ARM_CLKID = 6,
+ DAVINCI_PLLM_CLKID = 0xff,
+ DAVINCI_PLLC_CLKID = 0x100,
+ DAVINCI_AUXCLK_CLKID = 0x101
+};
+
+int clk_get(enum davinci_clk_ids id);
+
+/* Boot config */
+struct davinci_syscfg_regs {
+ dv_reg revid;
+ dv_reg rsvd[71];
+ dv_reg pinmux[20];
+ dv_reg suspsrc;
+ dv_reg chipsig;
+ dv_reg chipsig_clr;
+ dv_reg cfgchip0;
+ dv_reg cfgchip1;
+ dv_reg cfgchip2;
+ dv_reg cfgchip3;
+ dv_reg cfgchip4;
+};
+
+#define davinci_syscfg_regs \
+ ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
+
+/* Emulation suspend bits */
+#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
+#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
+#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
+#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
+#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
+
+/* Interrupt controller */
+struct davinci_aintc_regs {
+ dv_reg revid;
+ dv_reg cr;
+ dv_reg dummy0[2];
+ dv_reg ger;
+ dv_reg dummy1[219];
+ dv_reg ecr1;
+ dv_reg ecr2;
+ dv_reg ecr3;
+ dv_reg dummy2[1117];
+ dv_reg hier;
+};
+
+#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
+
+struct davinci_uart_ctrl_regs {
+ dv_reg revid1;
+ dv_reg revid2;
+ dv_reg pwremu_mgmt;
+ dv_reg mdr;
+};
+
+#define DAVINCI_UART_CTRL_BASE 0x28
+#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
+#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
+#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
+
+#define davinci_uart0_ctrl_regs \
+ ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
+#define davinci_uart1_ctrl_regs \
+ ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
+#define davinci_uart2_ctrl_regs \
+ ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
+
+/* UART PWREMU_MGMT definitions */
+#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
+#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
+#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
+
+#endif /* CONFIG_SOC_DA8XX */
+
#endif /* __ASM_ARCH_HARDWARE_H */
#define I2C_WRITE 0
#define I2C_READ 1
+#ifndef CONFIG_SOC_DA8XX
#define I2C_BASE 0x01c21000
+#else
+#define I2C_BASE 0x01c22000
+#endif
#define I2C_OA (I2C_BASE + 0x00)
#define I2C_IE (I2C_BASE + 0x04)
#define I2C_CON_XA (1 << 8) /* Expand address */
#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
+#define I2C_CON_FREE (1 << 14) /* Free run on emulation */
#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */
#ifndef _OMAP24XX_I2C_H_
#define _OMAP24XX_I2C_H_
-#define I2C_BASE 0x48070000
+#define I2C_BASE1 0x48070000
#define I2C_BASE2 0x48072000 /* nothing hooked up on h4 */
-#define I2C_REV (I2C_BASE + 0x00)
-#define I2C_IE (I2C_BASE + 0x04)
-#define I2C_STAT (I2C_BASE + 0x08)
-#define I2C_IV (I2C_BASE + 0x0c)
-#define I2C_BUF (I2C_BASE + 0x14)
-#define I2C_CNT (I2C_BASE + 0x18)
-#define I2C_DATA (I2C_BASE + 0x1c)
-#define I2C_SYSC (I2C_BASE + 0x20)
-#define I2C_CON (I2C_BASE + 0x24)
-#define I2C_OA (I2C_BASE + 0x28)
-#define I2C_SA (I2C_BASE + 0x2c)
-#define I2C_PSC (I2C_BASE + 0x30)
-#define I2C_SCLL (I2C_BASE + 0x34)
-#define I2C_SCLH (I2C_BASE + 0x38)
-#define I2C_SYSTEST (I2C_BASE + 0x3c)
+#define I2C_DEFAULT_BASE I2C_BASE1
+
+struct i2c {
+ unsigned short rev; /* 0x00 */
+ unsigned short res1;
+ unsigned short ie; /* 0x04 */
+ unsigned short res2;
+ unsigned short stat; /* 0x08 */
+ unsigned short res3;
+ unsigned short iv; /* 0x0C */
+ unsigned short res4[3];
+ unsigned short buf; /* 0x14 */
+ unsigned short res5;
+ unsigned short cnt; /* 0x18 */
+ unsigned short res6;
+ unsigned short data; /* 0x1C */
+ unsigned short res7;
+ unsigned short sysc; /* 0x20 */
+ unsigned short res8;
+ unsigned short con; /* 0x24 */
+ unsigned short res9;
+ unsigned short oa; /* 0x28 */
+ unsigned short res10;
+ unsigned short sa; /* 0x2C */
+ unsigned short res11;
+ unsigned short psc; /* 0x30 */
+ unsigned short res12;
+ unsigned short scll; /* 0x34 */
+ unsigned short res13;
+ unsigned short sclh; /* 0x38 */
+ unsigned short res14;
+ unsigned short systest; /* 0x3c */
+ unsigned short res15;
+};
+
+#define I2C_BUS_MAX 2
/* I2C masks */
#define PAGEPOLICY_HIGH (0x1 << 0)
#define SRFRONRESET (0x1 << 7)
+#define PWDNEN (0x1 << 2)
#define WAKEUPPROC (0x1 << 26)
#define DDR_SDRAM (0x1 << 0)
#define I2C_DEFAULT_BASE I2C_BASE1
-#define I2C_REV (I2C_DEFAULT_BASE + 0x00)
-#define I2C_IE (I2C_DEFAULT_BASE + 0x04)
-#define I2C_STAT (I2C_DEFAULT_BASE + 0x08)
-#define I2C_IV (I2C_DEFAULT_BASE + 0x0c)
-#define I2C_BUF (I2C_DEFAULT_BASE + 0x14)
-#define I2C_CNT (I2C_DEFAULT_BASE + 0x18)
-#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c)
-#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20)
-#define I2C_CON (I2C_DEFAULT_BASE + 0x24)
-#define I2C_OA (I2C_DEFAULT_BASE + 0x28)
-#define I2C_SA (I2C_DEFAULT_BASE + 0x2c)
-#define I2C_PSC (I2C_DEFAULT_BASE + 0x30)
-#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34)
-#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38)
-#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c)
+struct i2c {
+ unsigned short rev; /* 0x00 */
+ unsigned short res1;
+ unsigned short ie; /* 0x04 */
+ unsigned short res2;
+ unsigned short stat; /* 0x08 */
+ unsigned short res3;
+ unsigned short iv; /* 0x0C */
+ unsigned short res4[3];
+ unsigned short buf; /* 0x14 */
+ unsigned short res5;
+ unsigned short cnt; /* 0x18 */
+ unsigned short res6;
+ unsigned short data; /* 0x1C */
+ unsigned short res7;
+ unsigned short sysc; /* 0x20 */
+ unsigned short res8;
+ unsigned short con; /* 0x24 */
+ unsigned short res9;
+ unsigned short oa; /* 0x28 */
+ unsigned short res10;
+ unsigned short sa; /* 0x2C */
+ unsigned short res11;
+ unsigned short psc; /* 0x30 */
+ unsigned short res12;
+ unsigned short scll; /* 0x34 */
+ unsigned short res13;
+ unsigned short sclh; /* 0x38 */
+ unsigned short res14;
+ unsigned short systest; /* 0x3c */
+ unsigned short res15;
+};
+
+#define I2C_BUS_MAX 3
/* I2C masks */
#define EARLY_INIT 1
/* Slower full frequency range default timings for x32 operation*/
-#define SDP_SDRC_SHARING 0x00000100
-#define SDP_SDRC_MR_0_SDR 0x00000031
-
-/* optimized timings good for current shipping parts */
-#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
+#define SDRC_SHARING 0x00000100
+#define SDRC_MR_0_SDR 0x00000031
#define DLL_OFFSET 0
#define DLL_WRITEDDRCLKX2DIS 1
* TCKE = 2
* XSR = 120/6 = 20
*/
-#define TDAL_165 6
-#define TDPL_165 3
-#define TRRD_165 2
-#define TRCD_165 3
-#define TRP_165 3
-#define TRAS_165 7
-#define TRC_165 10
-#define TRFC_165 21
-#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \
- (TRAS_165 << 18) | (TRP_165 << 15) | \
- (TRCD_165 << 12) | (TRRD_165 << 9) | \
- (TDPL_165 << 6) | (TDAL_165))
-
-#define TWTR_165 1
-#define TCKE_165 1
-#define TXP_165 5
-#define XSR_165 23
-#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \
- (TXP_165 << 8) | (TWTR_165 << 16))
-
-#define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
-#define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165
-#define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
+#define INFINEON_TDAL_165 6
+#define INFINEON_TDPL_165 3
+#define INFINEON_TRRD_165 2
+#define INFINEON_TRCD_165 3
+#define INFINEON_TRP_165 3
+#define INFINEON_TRAS_165 7
+#define INFINEON_TRC_165 10
+#define INFINEON_TRFC_165 12
+#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | \
+ (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) | \
+ (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) | \
+ (INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) | \
+ (INFINEON_TDAL_165))
+
+#define INFINEON_TWTR_165 1
+#define INFINEON_TCKE_165 2
+#define INFINEON_TXP_165 2
+#define INFINEON_XSR_165 20
+#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | \
+ (INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) | \
+ (INFINEON_TWTR_165 << 16))
+
+/* Micron part of 3430 EVM (165MHz optimized) 6.06ns
+ * ACTIMA
+ * TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6
+ * TDPL (Twr) = 15/6 = 2.5 -> 3
+ * TRRD = 12/6 = 2
+ * TRCD = 18/6 = 3
+ * TRP = 18/6 = 3
+ * TRAS = 42/6 = 7
+ * TRC = 60/6 = 10
+ * TRFC = 125/6 = 21
+ * ACTIMB
+ * TWTR = 1
+ * TCKE = 1
+ * TXSR = 138/6 = 23
+ * TXP = 25/6 = 4.1 ~5
+ */
+#define MICRON_TDAL_165 6
+#define MICRON_TDPL_165 3
+#define MICRON_TRRD_165 2
+#define MICRON_TRCD_165 3
+#define MICRON_TRP_165 3
+#define MICRON_TRAS_165 7
+#define MICRON_TRC_165 10
+#define MICRON_TRFC_165 21
+#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | \
+ (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) | \
+ (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) | \
+ (MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) | \
+ (MICRON_TDAL_165))
+
+#define MICRON_TWTR_165 1
+#define MICRON_TCKE_165 1
+#define MICRON_XSR_165 23
+#define MICRON_TXP_165 5
+#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | \
+ (MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \
+ (MICRON_TWTR_165 << 16))
+
+#ifdef CONFIG_OMAP3_INFINEON_DDR
+#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
+#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
+#endif
+#ifdef CONFIG_OMAP3_MICRON_DDR
+#define V_ACTIMA_165 MICRON_V_ACTIMA_165
+#define V_ACTIMB_165 MICRON_V_ACTIMB_165
+#endif
+
+#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
+#error "Please choose the right DDR type in config header"
+#endif
/*
* GPMC settings -
/*
- * This was automagically generated from mach-types!
+ * This was automagically generated from arch/arm/tools/mach-types!
* Do NOT edit
- *
- * Last update: Fri Sep 4 22:16:22 2009
- *
*/
#ifndef __ASM_ARM_MACH_TYPE_H
#define MACH_TYPE_AML_M8050 1644
#define MACH_TYPE_MX35_3DS 1645
#define MACH_TYPE_MARS 1646
-#define MACH_TYPE_NTOSD_644XA 1647
+#define MACH_TYPE_NEUROS_OSD2 1647
#define MACH_TYPE_BADGER 1648
#define MACH_TYPE_TRIZEPS4WL 1649
#define MACH_TYPE_TRIZEPS5 1650
#define MACH_TYPE_ZORAN43XX 1660
#define MACH_TYPE_SONIX926 1661
#define MACH_TYPE_CELESTIALSEMI 1662
-#define MACH_TYPE_CC9M2443 1663
+#define MACH_TYPE_CC9M2443JS 1663
#define MACH_TYPE_TW5334 1664
#define MACH_TYPE_HTCARTEMIS 1665
#define MACH_TYPE_NAL_HLITE 1666
#define MACH_TYPE_WDG002 1785
#define MACH_TYPE_SG560ADSL 1786
#define MACH_TYPE_NEXTIO_N2800_ICA 1787
+#define MACH_TYPE_DOVE_DB 1788
#define MACH_TYPE_MARVELL_NEWDB 1789
#define MACH_TYPE_VANDIHUD 1790
#define MACH_TYPE_MAGX_E8 1791
#define MACH_TYPE_RD88F5181L_GE 1812
#define MACH_TYPE_SIFMAIN 1813
#define MACH_TYPE_SAM9_L9261 1814
-#define MACH_TYPE_CC9M2443JS 1815
+#define MACH_TYPE_CC9M2443 1815
#define MACH_TYPE_XARIA300 1816
#define MACH_TYPE_IT9200 1817
#define MACH_TYPE_RD88F5181L_FXO 1818
#define MACH_TYPE_MULTIBUS_MASTER 2416
#define MACH_TYPE_MULTIBUS_PBK 2417
#define MACH_TYPE_TNETV107X 2418
+#define MACH_TYPE_SNAKE 2419
+#define MACH_TYPE_CWMX27 2420
+#define MACH_TYPE_SCH_M480 2421
+#define MACH_TYPE_PLATYPUS 2422
+#define MACH_TYPE_PSS2 2423
+#define MACH_TYPE_DAVINCI_APM150 2424
+#define MACH_TYPE_STR9100 2425
+#define MACH_TYPE_NET5BIG 2426
+#define MACH_TYPE_SEABED9263 2427
+#define MACH_TYPE_MX51_M2ID 2428
+#define MACH_TYPE_OCTVOCPLUS_EB 2429
+#define MACH_TYPE_KLK_FIREFOX 2430
+#define MACH_TYPE_KLK_WIRMA_MODULE 2431
+#define MACH_TYPE_KLK_WIRMA_MMI 2432
+#define MACH_TYPE_SUPERSONIC 2433
+#define MACH_TYPE_LIBERTY 2434
+#define MACH_TYPE_MH355 2435
+#define MACH_TYPE_PC7802 2436
+#define MACH_TYPE_GNET_SGC 2437
+#define MACH_TYPE_EINSTEIN15 2438
+#define MACH_TYPE_CMPD 2439
+#define MACH_TYPE_DAVINCI_HASE1 2440
+#define MACH_TYPE_LGEINCITEPHONE 2441
+#define MACH_TYPE_EA313X 2442
+#define MACH_TYPE_FWBD_39064 2443
+#define MACH_TYPE_FWBD_390128 2444
+#define MACH_TYPE_PELCO_MOE 2445
+#define MACH_TYPE_MINIMIX27 2446
+#define MACH_TYPE_OMAP3_THUNDER 2447
+#define MACH_TYPE_PASSIONC 2448
+#define MACH_TYPE_MX27AMATA 2449
+#define MACH_TYPE_BGAT1 2450
+#define MACH_TYPE_BUZZ 2451
+#define MACH_TYPE_MB9G20 2452
+#define MACH_TYPE_YUSHAN 2453
+#define MACH_TYPE_LIZARD 2454
+#define MACH_TYPE_OMAP3POLYCOM 2455
+#define MACH_TYPE_SMDKV210 2456
+#define MACH_TYPE_BRAVO 2457
+#define MACH_TYPE_SIOGENTOO1 2458
+#define MACH_TYPE_SIOGENTOO2 2459
+#define MACH_TYPE_SM3K 2460
+#define MACH_TYPE_ACER_TEMPO_F900 2461
+#define MACH_TYPE_SST61VC010_DEV 2462
+#define MACH_TYPE_GLITTERTIND 2463
+#define MACH_TYPE_OMAP_ZOOM3 2464
+#define MACH_TYPE_OMAP_3630SDP 2465
+#define MACH_TYPE_CYBOOK2440 2466
+#define MACH_TYPE_TORINO_S 2467
+#define MACH_TYPE_HAVANA 2468
+#define MACH_TYPE_BEAUMONT_11 2469
+#define MACH_TYPE_VANGUARD 2470
+#define MACH_TYPE_S5PC110_DRACO 2471
+#define MACH_TYPE_CARTESIO_TWO 2472
+#define MACH_TYPE_ASTER 2473
+#define MACH_TYPE_VOGUESV210 2474
+#define MACH_TYPE_ACM500X 2475
+#define MACH_TYPE_KM9260 2476
+#define MACH_TYPE_NIDEFLEXG1 2477
+#define MACH_TYPE_CTERA_PLUG_IO 2478
+#define MACH_TYPE_SMARTQ7 2479
+#define MACH_TYPE_AT91SAM9G10EK2 2480
+#define MACH_TYPE_ASUSP527 2481
+#define MACH_TYPE_AT91SAM9G20MPM2 2482
+#define MACH_TYPE_TOPASA900 2483
+#define MACH_TYPE_ELECTRUM_100 2484
+#define MACH_TYPE_MX51GRB 2485
+#define MACH_TYPE_XEA300 2486
+#define MACH_TYPE_HTCSTARTREK 2487
+#define MACH_TYPE_LIMA 2488
+#define MACH_TYPE_CSB740 2489
+#define MACH_TYPE_USB_S8815 2490
+#define MACH_TYPE_WATSON_EFM_PLUGIN 2491
+#define MACH_TYPE_MILKYWAY 2492
+#define MACH_TYPE_G4EVM 2493
+#define MACH_TYPE_PICOMOD6 2494
+#define MACH_TYPE_OMAPL138_HAWKBOARD 2495
+#define MACH_TYPE_IP6000 2496
+#define MACH_TYPE_IP6010 2497
+#define MACH_TYPE_UTM400 2498
+#define MACH_TYPE_OMAP3_ZYBEX 2499
+#define MACH_TYPE_WIRELESS_SPACE 2500
+#define MACH_TYPE_SX560 2501
+#define MACH_TYPE_TS41X 2502
+#define MACH_TYPE_ELPHEL10373 2503
+#define MACH_TYPE_RHOBOT 2504
+#define MACH_TYPE_MX51_REFRESH 2505
+#define MACH_TYPE_LS9260 2506
+#define MACH_TYPE_SHANK 2507
+#define MACH_TYPE_QSD8X50_ST1 2508
+#define MACH_TYPE_AT91SAM9M10EKES 2509
+#define MACH_TYPE_HIRAM 2510
+#define MACH_TYPE_PHY3250 2511
+#define MACH_TYPE_EA3250 2512
+#define MACH_TYPE_FDI3250 2513
+#define MACH_TYPE_WHITESTONE 2514
+#define MACH_TYPE_AT91SAM9263NIT 2515
+#define MACH_TYPE_CCMX51 2516
+#define MACH_TYPE_CCMX51JS 2517
+#define MACH_TYPE_CCWMX51 2518
+#define MACH_TYPE_CCWMX51JS 2519
+#define MACH_TYPE_MINI6410 2520
+#define MACH_TYPE_TINY6410 2521
+#define MACH_TYPE_NANO6410 2522
+#define MACH_TYPE_AT572D940HFNLDB 2523
+#define MACH_TYPE_HTCLEO 2524
+#define MACH_TYPE_AVP13 2525
+#define MACH_TYPE_XXSVIDEOD 2526
+#define MACH_TYPE_VPNEXT 2527
+#define MACH_TYPE_SWARCO_ITC3 2528
+#define MACH_TYPE_TX51 2529
+#define MACH_TYPE_DOLBY_CAT1021 2530
+#define MACH_TYPE_MX28EVK 2531
+#define MACH_TYPE_PHOENIX260 2532
+#define MACH_TYPE_UVACA_STORK 2533
+#define MACH_TYPE_SMARTQ5 2534
+#define MACH_TYPE_ALL3078 2535
+#define MACH_TYPE_CTERA_2BAY_DS 2536
+#define MACH_TYPE_SIOGENTOO3 2537
+#define MACH_TYPE_EPB5000 2538
+#define MACH_TYPE_HY9263 2539
+#define MACH_TYPE_ACER_TEMPO_M900 2540
+#define MACH_TYPE_ACER_TEMPO_DX900 2541
+#define MACH_TYPE_ACER_TEMPO_X960 2542
+#define MACH_TYPE_ACER_ETEN_V900 2543
+#define MACH_TYPE_ACER_ETEN_X900 2544
+#define MACH_TYPE_BONNELL 2545
+#define MACH_TYPE_OHT_MX27 2546
+#define MACH_TYPE_HTCQUARTZ 2547
+#define MACH_TYPE_DAVINCI_DM6467TEVM 2548
+#define MACH_TYPE_C3AX03 2549
+#define MACH_TYPE_MXT_TD60 2550
+#define MACH_TYPE_ESYX 2551
+#define MACH_TYPE_DOVE_DB2 2552
+#define MACH_TYPE_BULLDOG 2553
+#define MACH_TYPE_DERELL_ME2000 2554
+#define MACH_TYPE_BCMRING_BASE 2555
+#define MACH_TYPE_BCMRING_EVM 2556
+#define MACH_TYPE_BCMRING_EVM_JAZZ 2557
+#define MACH_TYPE_BCMRING_SP 2558
+#define MACH_TYPE_BCMRING_SV 2559
+#define MACH_TYPE_BCMRING_SV_JAZZ 2560
+#define MACH_TYPE_BCMRING_TABLET 2561
+#define MACH_TYPE_BCMRING_VP 2562
+#define MACH_TYPE_BCMRING_EVM_SEIKOR 2563
+#define MACH_TYPE_BCMRING_SP_WQVGA 2564
+#define MACH_TYPE_BCMRING_CUSTOM 2565
+#define MACH_TYPE_ACER_S200 2566
+#define MACH_TYPE_BT270 2567
+#define MACH_TYPE_ISEO 2568
+#define MACH_TYPE_CEZANNE 2569
+#define MACH_TYPE_LUCCA 2570
+#define MACH_TYPE_SUPERSMART 2571
+#define MACH_TYPE_CS_MISANO 2572
+#define MACH_TYPE_MAGNOLIA2 2573
+#define MACH_TYPE_EMXX 2574
+#define MACH_TYPE_OUTLAW 2575
+#define MACH_TYPE_RIOT_BEI2 2576
+#define MACH_TYPE_RIOT_VOX 2577
+#define MACH_TYPE_RIOT_X37 2578
+#define MACH_TYPE_MEGA25MX 2579
+#define MACH_TYPE_BENZINA2 2580
+#define MACH_TYPE_IGNITE 2581
+#define MACH_TYPE_FOGGIA 2582
+#define MACH_TYPE_AREZZO 2583
+#define MACH_TYPE_LEICA_SKYWALKER 2584
+#define MACH_TYPE_JACINTO2_JAMR 2585
+#define MACH_TYPE_GTS_NOVA 2586
+#define MACH_TYPE_P3600 2587
+#define MACH_TYPE_DLT2 2588
+#define MACH_TYPE_DF3120 2589
+#define MACH_TYPE_ECUCORE_9G20 2590
+#define MACH_TYPE_NAUTEL_LPC3240 2591
+#define MACH_TYPE_GLACIER 2592
+#define MACH_TYPE_PHRAZER_BULLDOG 2593
+#define MACH_TYPE_OMAP3_BULLDOG 2594
+#define MACH_TYPE_PCA101 2595
+#define MACH_TYPE_BUZZC 2596
+#define MACH_TYPE_SASIE2 2597
+#define MACH_TYPE_DAVINCI_CIO 2598
+#define MACH_TYPE_SMARTMETER_DL 2599
+#define MACH_TYPE_WZL6410 2600
+#define MACH_TYPE_WZL6410M 2601
+#define MACH_TYPE_WZL6410F 2602
+#define MACH_TYPE_WZL6410I 2603
+#define MACH_TYPE_SPACECOM1 2604
+#define MACH_TYPE_PINGU920 2605
+#define MACH_TYPE_BRAVOC 2606
+#define MACH_TYPE_CYBO2440 2607
+#define MACH_TYPE_VDSSW 2608
+#define MACH_TYPE_ROMULUS 2609
+#define MACH_TYPE_OMAP_MAGIC 2610
+#define MACH_TYPE_ELTD100 2611
+#define MACH_TYPE_CAPC7117 2612
+#define MACH_TYPE_SWAN 2613
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
# else
# define machine_arch_type MACH_TYPE_REA_2D
# endif
-# define machine_is_rea_2d() (machine_arch_type == MACH_TYPE_REA_2D)
+# define machine_is_rea_cpu2() (machine_arch_type == MACH_TYPE_REA_2D)
#else
-# define machine_is_rea_2d() (0)
+# define machine_is_rea_cpu2() (0)
#endif
#ifdef CONFIG_MACH_TI3E524
# define machine_is_mars() (0)
#endif
-#ifdef CONFIG_MACH_NTOSD_644XA
+#ifdef CONFIG_MACH_NEUROS_OSD2
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_NTOSD_644XA
+# define machine_arch_type MACH_TYPE_NEUROS_OSD2
# endif
-# define machine_is_ntosd_644xa() (machine_arch_type == MACH_TYPE_NTOSD_644XA)
+# define machine_is_neuros_osd2() (machine_arch_type == MACH_TYPE_NEUROS_OSD2)
#else
-# define machine_is_ntosd_644xa() (0)
+# define machine_is_neuros_osd2() (0)
#endif
#ifdef CONFIG_MACH_BADGER
# define machine_is_celestialsemi() (0)
#endif
-#ifdef CONFIG_MACH_CC9M2443
+#ifdef CONFIG_MACH_CC9M2443JS
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_CC9M2443
+# define machine_arch_type MACH_TYPE_CC9M2443JS
# endif
-# define machine_is_cc9m2443() (machine_arch_type == MACH_TYPE_CC9M2443)
+# define machine_is_cc9m2443js() (machine_arch_type == MACH_TYPE_CC9M2443JS)
#else
-# define machine_is_cc9m2443() (0)
+# define machine_is_cc9m2443js() (0)
#endif
#ifdef CONFIG_MACH_TW5334
# define machine_is_nextio_n2800_ica() (0)
#endif
+#ifdef CONFIG_MACH_DOVE_DB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DOVE_DB
+# endif
+# define machine_is_dove_db() (machine_arch_type == MACH_TYPE_DOVE_DB)
+#else
+# define machine_is_dove_db() (0)
+#endif
+
#ifdef CONFIG_MACH_MARVELL_NEWDB
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_is_sam9_l9261() (0)
#endif
-#ifdef CONFIG_MACH_CC9M2443JS
+#ifdef CONFIG_MACH_CC9M2443
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_CC9M2443JS
+# define machine_arch_type MACH_TYPE_CC9M2443
# endif
-# define machine_is_cc9m2443js() (machine_arch_type == MACH_TYPE_CC9M2443JS)
+# define machine_is_cc9m2443() (machine_arch_type == MACH_TYPE_CC9M2443)
#else
-# define machine_is_cc9m2443js() (0)
+# define machine_is_cc9m2443() (0)
#endif
#ifdef CONFIG_MACH_XARIA300
# else
# define machine_arch_type MACH_TYPE_SIENNA
# endif
-# define machine_is_sienna() (machine_arch_type == MACH_TYPE_SIENNA)
+# define machine_is_siena() (machine_arch_type == MACH_TYPE_SIENNA)
#else
-# define machine_is_sienna() (0)
+# define machine_is_siena() (0)
#endif
#ifdef CONFIG_MACH_HTC_EXCALIBUR_S620
# define machine_is_tnetv107x() (0)
#endif
+#ifdef CONFIG_MACH_SNAKE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SNAKE
+# endif
+# define machine_is_snake() (machine_arch_type == MACH_TYPE_SNAKE)
+#else
+# define machine_is_snake() (0)
+#endif
+
+#ifdef CONFIG_MACH_CWMX27
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CWMX27
+# endif
+# define machine_is_cwmx27() (machine_arch_type == MACH_TYPE_CWMX27)
+#else
+# define machine_is_cwmx27() (0)
+#endif
+
+#ifdef CONFIG_MACH_SCH_M480
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SCH_M480
+# endif
+# define machine_is_sch_m480() (machine_arch_type == MACH_TYPE_SCH_M480)
+#else
+# define machine_is_sch_m480() (0)
+#endif
+
+#ifdef CONFIG_MACH_PLATYPUS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PLATYPUS
+# endif
+# define machine_is_platypus() (machine_arch_type == MACH_TYPE_PLATYPUS)
+#else
+# define machine_is_platypus() (0)
+#endif
+
+#ifdef CONFIG_MACH_PSS2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PSS2
+# endif
+# define machine_is_pss2() (machine_arch_type == MACH_TYPE_PSS2)
+#else
+# define machine_is_pss2() (0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_APM150
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DAVINCI_APM150
+# endif
+# define machine_is_davinci_apm150() (machine_arch_type == MACH_TYPE_DAVINCI_APM150)
+#else
+# define machine_is_davinci_apm150() (0)
+#endif
+
+#ifdef CONFIG_MACH_STR9100
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_STR9100
+# endif
+# define machine_is_str9100() (machine_arch_type == MACH_TYPE_STR9100)
+#else
+# define machine_is_str9100() (0)
+#endif
+
+#ifdef CONFIG_MACH_NET5BIG
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NET5BIG
+# endif
+# define machine_is_net5big() (machine_arch_type == MACH_TYPE_NET5BIG)
+#else
+# define machine_is_net5big() (0)
+#endif
+
+#ifdef CONFIG_MACH_SEABED9263
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SEABED9263
+# endif
+# define machine_is_seabed9263() (machine_arch_type == MACH_TYPE_SEABED9263)
+#else
+# define machine_is_seabed9263() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_M2ID
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX51_M2ID
+# endif
+# define machine_is_mx51_m2id() (machine_arch_type == MACH_TYPE_MX51_M2ID)
+#else
+# define machine_is_mx51_m2id() (0)
+#endif
+
+#ifdef CONFIG_MACH_OCTVOCPLUS_EB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OCTVOCPLUS_EB
+# endif
+# define machine_is_octvocplus_eb() (machine_arch_type == MACH_TYPE_OCTVOCPLUS_EB)
+#else
+# define machine_is_octvocplus_eb() (0)
+#endif
+
+#ifdef CONFIG_MACH_KLK_FIREFOX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KLK_FIREFOX
+# endif
+# define machine_is_klk_firefox() (machine_arch_type == MACH_TYPE_KLK_FIREFOX)
+#else
+# define machine_is_klk_firefox() (0)
+#endif
+
+#ifdef CONFIG_MACH_KLK_WIRMA_MODULE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KLK_WIRMA_MODULE
+# endif
+# define machine_is_klk_wirma_module() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MODULE)
+#else
+# define machine_is_klk_wirma_module() (0)
+#endif
+
+#ifdef CONFIG_MACH_KLK_WIRMA_MMI
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KLK_WIRMA_MMI
+# endif
+# define machine_is_klk_wirma_mmi() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MMI)
+#else
+# define machine_is_klk_wirma_mmi() (0)
+#endif
+
+#ifdef CONFIG_MACH_SUPERSONIC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SUPERSONIC
+# endif
+# define machine_is_supersonic() (machine_arch_type == MACH_TYPE_SUPERSONIC)
+#else
+# define machine_is_supersonic() (0)
+#endif
+
+#ifdef CONFIG_MACH_LIBERTY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LIBERTY
+# endif
+# define machine_is_liberty() (machine_arch_type == MACH_TYPE_LIBERTY)
+#else
+# define machine_is_liberty() (0)
+#endif
+
+#ifdef CONFIG_MACH_MH355
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MH355
+# endif
+# define machine_is_mh355() (machine_arch_type == MACH_TYPE_MH355)
+#else
+# define machine_is_mh355() (0)
+#endif
+
+#ifdef CONFIG_MACH_PC7802
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PC7802
+# endif
+# define machine_is_pc7802() (machine_arch_type == MACH_TYPE_PC7802)
+#else
+# define machine_is_pc7802() (0)
+#endif
+
+#ifdef CONFIG_MACH_GNET_SGC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GNET_SGC
+# endif
+# define machine_is_gnet_sgc() (machine_arch_type == MACH_TYPE_GNET_SGC)
+#else
+# define machine_is_gnet_sgc() (0)
+#endif
+
+#ifdef CONFIG_MACH_EINSTEIN15
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EINSTEIN15
+# endif
+# define machine_is_einstein15() (machine_arch_type == MACH_TYPE_EINSTEIN15)
+#else
+# define machine_is_einstein15() (0)
+#endif
+
+#ifdef CONFIG_MACH_CMPD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CMPD
+# endif
+# define machine_is_cmpd() (machine_arch_type == MACH_TYPE_CMPD)
+#else
+# define machine_is_cmpd() (0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_HASE1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DAVINCI_HASE1
+# endif
+# define machine_is_davinci_hase1() (machine_arch_type == MACH_TYPE_DAVINCI_HASE1)
+#else
+# define machine_is_davinci_hase1() (0)
+#endif
+
+#ifdef CONFIG_MACH_LGEINCITEPHONE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LGEINCITEPHONE
+# endif
+# define machine_is_lgeincitephone() (machine_arch_type == MACH_TYPE_LGEINCITEPHONE)
+#else
+# define machine_is_lgeincitephone() (0)
+#endif
+
+#ifdef CONFIG_MACH_EA313X
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EA313X
+# endif
+# define machine_is_ea313x() (machine_arch_type == MACH_TYPE_EA313X)
+#else
+# define machine_is_ea313x() (0)
+#endif
+
+#ifdef CONFIG_MACH_FWBD_39064
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_FWBD_39064
+# endif
+# define machine_is_fwbd_39064() (machine_arch_type == MACH_TYPE_FWBD_39064)
+#else
+# define machine_is_fwbd_39064() (0)
+#endif
+
+#ifdef CONFIG_MACH_FWBD_390128
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_FWBD_390128
+# endif
+# define machine_is_fwbd_390128() (machine_arch_type == MACH_TYPE_FWBD_390128)
+#else
+# define machine_is_fwbd_390128() (0)
+#endif
+
+#ifdef CONFIG_MACH_PELCO_MOE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PELCO_MOE
+# endif
+# define machine_is_pelco_moe() (machine_arch_type == MACH_TYPE_PELCO_MOE)
+#else
+# define machine_is_pelco_moe() (0)
+#endif
+
+#ifdef CONFIG_MACH_MINIMIX27
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MINIMIX27
+# endif
+# define machine_is_minimix27() (machine_arch_type == MACH_TYPE_MINIMIX27)
+#else
+# define machine_is_minimix27() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_THUNDER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3_THUNDER
+# endif
+# define machine_is_omap3_thunder() (machine_arch_type == MACH_TYPE_OMAP3_THUNDER)
+#else
+# define machine_is_omap3_thunder() (0)
+#endif
+
+#ifdef CONFIG_MACH_PASSIONC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PASSIONC
+# endif
+# define machine_is_passionc() (machine_arch_type == MACH_TYPE_PASSIONC)
+#else
+# define machine_is_passionc() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX27AMATA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX27AMATA
+# endif
+# define machine_is_mx27amata() (machine_arch_type == MACH_TYPE_MX27AMATA)
+#else
+# define machine_is_mx27amata() (0)
+#endif
+
+#ifdef CONFIG_MACH_BGAT1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BGAT1
+# endif
+# define machine_is_bgat1() (machine_arch_type == MACH_TYPE_BGAT1)
+#else
+# define machine_is_bgat1() (0)
+#endif
+
+#ifdef CONFIG_MACH_BUZZ
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BUZZ
+# endif
+# define machine_is_buzz() (machine_arch_type == MACH_TYPE_BUZZ)
+#else
+# define machine_is_buzz() (0)
+#endif
+
+#ifdef CONFIG_MACH_MB9G20
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MB9G20
+# endif
+# define machine_is_mb9g20() (machine_arch_type == MACH_TYPE_MB9G20)
+#else
+# define machine_is_mb9g20() (0)
+#endif
+
+#ifdef CONFIG_MACH_YUSHAN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_YUSHAN
+# endif
+# define machine_is_yushan() (machine_arch_type == MACH_TYPE_YUSHAN)
+#else
+# define machine_is_yushan() (0)
+#endif
+
+#ifdef CONFIG_MACH_LIZARD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LIZARD
+# endif
+# define machine_is_lizard() (machine_arch_type == MACH_TYPE_LIZARD)
+#else
+# define machine_is_lizard() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3POLYCOM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3POLYCOM
+# endif
+# define machine_is_omap3polycom() (machine_arch_type == MACH_TYPE_OMAP3POLYCOM)
+#else
+# define machine_is_omap3polycom() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMDKV210
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMDKV210
+# endif
+# define machine_is_smdkv210() (machine_arch_type == MACH_TYPE_SMDKV210)
+#else
+# define machine_is_smdkv210() (0)
+#endif
+
+#ifdef CONFIG_MACH_BRAVO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BRAVO
+# endif
+# define machine_is_bravo() (machine_arch_type == MACH_TYPE_BRAVO)
+#else
+# define machine_is_bravo() (0)
+#endif
+
+#ifdef CONFIG_MACH_SIOGENTOO1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SIOGENTOO1
+# endif
+# define machine_is_siogentoo1() (machine_arch_type == MACH_TYPE_SIOGENTOO1)
+#else
+# define machine_is_siogentoo1() (0)
+#endif
+
+#ifdef CONFIG_MACH_SIOGENTOO2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SIOGENTOO2
+# endif
+# define machine_is_siogentoo2() (machine_arch_type == MACH_TYPE_SIOGENTOO2)
+#else
+# define machine_is_siogentoo2() (0)
+#endif
+
+#ifdef CONFIG_MACH_SM3K
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SM3K
+# endif
+# define machine_is_sm3k() (machine_arch_type == MACH_TYPE_SM3K)
+#else
+# define machine_is_sm3k() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_TEMPO_F900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_TEMPO_F900
+# endif
+# define machine_is_acer_tempo_f900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_F900)
+#else
+# define machine_is_acer_tempo_f900() (0)
+#endif
+
+#ifdef CONFIG_MACH_SST61VC010_DEV
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SST61VC010_DEV
+# endif
+# define machine_is_sst61vc010_dev() (machine_arch_type == MACH_TYPE_SST61VC010_DEV)
+#else
+# define machine_is_sst61vc010_dev() (0)
+#endif
+
+#ifdef CONFIG_MACH_GLITTERTIND
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GLITTERTIND
+# endif
+# define machine_is_glittertind() (machine_arch_type == MACH_TYPE_GLITTERTIND)
+#else
+# define machine_is_glittertind() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_ZOOM3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP_ZOOM3
+# endif
+# define machine_is_omap_zoom3() (machine_arch_type == MACH_TYPE_OMAP_ZOOM3)
+#else
+# define machine_is_omap_zoom3() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_3630SDP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP_3630SDP
+# endif
+# define machine_is_omap_3630sdp() (machine_arch_type == MACH_TYPE_OMAP_3630SDP)
+#else
+# define machine_is_omap_3630sdp() (0)
+#endif
+
+#ifdef CONFIG_MACH_CYBOOK2440
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CYBOOK2440
+# endif
+# define machine_is_cybook2440() (machine_arch_type == MACH_TYPE_CYBOOK2440)
+#else
+# define machine_is_cybook2440() (0)
+#endif
+
+#ifdef CONFIG_MACH_TORINO_S
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TORINO_S
+# endif
+# define machine_is_torino_s() (machine_arch_type == MACH_TYPE_TORINO_S)
+#else
+# define machine_is_torino_s() (0)
+#endif
+
+#ifdef CONFIG_MACH_HAVANA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HAVANA
+# endif
+# define machine_is_havana() (machine_arch_type == MACH_TYPE_HAVANA)
+#else
+# define machine_is_havana() (0)
+#endif
+
+#ifdef CONFIG_MACH_BEAUMONT_11
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BEAUMONT_11
+# endif
+# define machine_is_beaumont_11() (machine_arch_type == MACH_TYPE_BEAUMONT_11)
+#else
+# define machine_is_beaumont_11() (0)
+#endif
+
+#ifdef CONFIG_MACH_VANGUARD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VANGUARD
+# endif
+# define machine_is_vanguard() (machine_arch_type == MACH_TYPE_VANGUARD)
+#else
+# define machine_is_vanguard() (0)
+#endif
+
+#ifdef CONFIG_MACH_S5PC110_DRACO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_S5PC110_DRACO
+# endif
+# define machine_is_s5pc110_draco() (machine_arch_type == MACH_TYPE_S5PC110_DRACO)
+#else
+# define machine_is_s5pc110_draco() (0)
+#endif
+
+#ifdef CONFIG_MACH_CARTESIO_TWO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CARTESIO_TWO
+# endif
+# define machine_is_cartesio_two() (machine_arch_type == MACH_TYPE_CARTESIO_TWO)
+#else
+# define machine_is_cartesio_two() (0)
+#endif
+
+#ifdef CONFIG_MACH_ASTER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ASTER
+# endif
+# define machine_is_aster() (machine_arch_type == MACH_TYPE_ASTER)
+#else
+# define machine_is_aster() (0)
+#endif
+
+#ifdef CONFIG_MACH_VOGUESV210
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VOGUESV210
+# endif
+# define machine_is_voguesv210() (machine_arch_type == MACH_TYPE_VOGUESV210)
+#else
+# define machine_is_voguesv210() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACM500X
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACM500X
+# endif
+# define machine_is_acm500x() (machine_arch_type == MACH_TYPE_ACM500X)
+#else
+# define machine_is_acm500x() (0)
+#endif
+
+#ifdef CONFIG_MACH_KM9260
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KM9260
+# endif
+# define machine_is_km9260() (machine_arch_type == MACH_TYPE_KM9260)
+#else
+# define machine_is_km9260() (0)
+#endif
+
+#ifdef CONFIG_MACH_NIDEFLEXG1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NIDEFLEXG1
+# endif
+# define machine_is_nideflexg1() (machine_arch_type == MACH_TYPE_NIDEFLEXG1)
+#else
+# define machine_is_nideflexg1() (0)
+#endif
+
+#ifdef CONFIG_MACH_CTERA_PLUG_IO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CTERA_PLUG_IO
+# endif
+# define machine_is_ctera_plug_io() (machine_arch_type == MACH_TYPE_CTERA_PLUG_IO)
+#else
+# define machine_is_ctera_plug_io() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTQ7
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMARTQ7
+# endif
+# define machine_is_smartq7() (machine_arch_type == MACH_TYPE_SMARTQ7)
+#else
+# define machine_is_smartq7() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9G10EK2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9G10EK2
+# endif
+# define machine_is_at91sam9g10ek2() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK2)
+#else
+# define machine_is_at91sam9g10ek2() (0)
+#endif
+
+#ifdef CONFIG_MACH_ASUSP527
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ASUSP527
+# endif
+# define machine_is_asusp527() (machine_arch_type == MACH_TYPE_ASUSP527)
+#else
+# define machine_is_asusp527() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9G20MPM2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9G20MPM2
+# endif
+# define machine_is_at91sam9g20mpm2() (machine_arch_type == MACH_TYPE_AT91SAM9G20MPM2)
+#else
+# define machine_is_at91sam9g20mpm2() (0)
+#endif
+
+#ifdef CONFIG_MACH_TOPASA900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TOPASA900
+# endif
+# define machine_is_topasa900() (machine_arch_type == MACH_TYPE_TOPASA900)
+#else
+# define machine_is_topasa900() (0)
+#endif
+
+#ifdef CONFIG_MACH_ELECTRUM_100
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ELECTRUM_100
+# endif
+# define machine_is_electrum_100() (machine_arch_type == MACH_TYPE_ELECTRUM_100)
+#else
+# define machine_is_electrum_100() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX51GRB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX51GRB
+# endif
+# define machine_is_mx51grb() (machine_arch_type == MACH_TYPE_MX51GRB)
+#else
+# define machine_is_mx51grb() (0)
+#endif
+
+#ifdef CONFIG_MACH_XEA300
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_XEA300
+# endif
+# define machine_is_xea300() (machine_arch_type == MACH_TYPE_XEA300)
+#else
+# define machine_is_xea300() (0)
+#endif
+
+#ifdef CONFIG_MACH_HTCSTARTREK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HTCSTARTREK
+# endif
+# define machine_is_htcstartrek() (machine_arch_type == MACH_TYPE_HTCSTARTREK)
+#else
+# define machine_is_htcstartrek() (0)
+#endif
+
+#ifdef CONFIG_MACH_LIMA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LIMA
+# endif
+# define machine_is_lima() (machine_arch_type == MACH_TYPE_LIMA)
+#else
+# define machine_is_lima() (0)
+#endif
+
+#ifdef CONFIG_MACH_CSB740
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CSB740
+# endif
+# define machine_is_csb740() (machine_arch_type == MACH_TYPE_CSB740)
+#else
+# define machine_is_csb740() (0)
+#endif
+
+#ifdef CONFIG_MACH_USB_S8815
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_USB_S8815
+# endif
+# define machine_is_usb_s8815() (machine_arch_type == MACH_TYPE_USB_S8815)
+#else
+# define machine_is_usb_s8815() (0)
+#endif
+
+#ifdef CONFIG_MACH_WATSON_EFM_PLUGIN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WATSON_EFM_PLUGIN
+# endif
+# define machine_is_watson_efm_plugin() (machine_arch_type == MACH_TYPE_WATSON_EFM_PLUGIN)
+#else
+# define machine_is_watson_efm_plugin() (0)
+#endif
+
+#ifdef CONFIG_MACH_MILKYWAY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MILKYWAY
+# endif
+# define machine_is_milkyway() (machine_arch_type == MACH_TYPE_MILKYWAY)
+#else
+# define machine_is_milkyway() (0)
+#endif
+
+#ifdef CONFIG_MACH_G4EVM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_G4EVM
+# endif
+# define machine_is_g4evm() (machine_arch_type == MACH_TYPE_G4EVM)
+#else
+# define machine_is_g4evm() (0)
+#endif
+
+#ifdef CONFIG_MACH_PICOMOD6
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PICOMOD6
+# endif
+# define machine_is_picomod6() (machine_arch_type == MACH_TYPE_PICOMOD6)
+#else
+# define machine_is_picomod6() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAPL138_HAWKBOARD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAPL138_HAWKBOARD
+# endif
+# define machine_is_omapl138_hawkboard() (machine_arch_type == MACH_TYPE_OMAPL138_HAWKBOARD)
+#else
+# define machine_is_omapl138_hawkboard() (0)
+#endif
+
+#ifdef CONFIG_MACH_IP6000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IP6000
+# endif
+# define machine_is_ip6000() (machine_arch_type == MACH_TYPE_IP6000)
+#else
+# define machine_is_ip6000() (0)
+#endif
+
+#ifdef CONFIG_MACH_IP6010
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IP6010
+# endif
+# define machine_is_ip6010() (machine_arch_type == MACH_TYPE_IP6010)
+#else
+# define machine_is_ip6010() (0)
+#endif
+
+#ifdef CONFIG_MACH_UTM400
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_UTM400
+# endif
+# define machine_is_utm400() (machine_arch_type == MACH_TYPE_UTM400)
+#else
+# define machine_is_utm400() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_ZYBEX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3_ZYBEX
+# endif
+# define machine_is_omap3_zybex() (machine_arch_type == MACH_TYPE_OMAP3_ZYBEX)
+#else
+# define machine_is_omap3_zybex() (0)
+#endif
+
+#ifdef CONFIG_MACH_WIRELESS_SPACE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WIRELESS_SPACE
+# endif
+# define machine_is_wireless_space() (machine_arch_type == MACH_TYPE_WIRELESS_SPACE)
+#else
+# define machine_is_wireless_space() (0)
+#endif
+
+#ifdef CONFIG_MACH_SX560
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SX560
+# endif
+# define machine_is_sx560() (machine_arch_type == MACH_TYPE_SX560)
+#else
+# define machine_is_sx560() (0)
+#endif
+
+#ifdef CONFIG_MACH_TS41X
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TS41X
+# endif
+# define machine_is_ts41x() (machine_arch_type == MACH_TYPE_TS41X)
+#else
+# define machine_is_ts41x() (0)
+#endif
+
+#ifdef CONFIG_MACH_ELPHEL10373
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ELPHEL10373
+# endif
+# define machine_is_elphel10373() (machine_arch_type == MACH_TYPE_ELPHEL10373)
+#else
+# define machine_is_elphel10373() (0)
+#endif
+
+#ifdef CONFIG_MACH_RHOBOT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_RHOBOT
+# endif
+# define machine_is_rhobot() (machine_arch_type == MACH_TYPE_RHOBOT)
+#else
+# define machine_is_rhobot() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_REFRESH
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX51_REFRESH
+# endif
+# define machine_is_mx51_refresh() (machine_arch_type == MACH_TYPE_MX51_REFRESH)
+#else
+# define machine_is_mx51_refresh() (0)
+#endif
+
+#ifdef CONFIG_MACH_LS9260
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LS9260
+# endif
+# define machine_is_ls9260() (machine_arch_type == MACH_TYPE_LS9260)
+#else
+# define machine_is_ls9260() (0)
+#endif
+
+#ifdef CONFIG_MACH_SHANK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SHANK
+# endif
+# define machine_is_shank() (machine_arch_type == MACH_TYPE_SHANK)
+#else
+# define machine_is_shank() (0)
+#endif
+
+#ifdef CONFIG_MACH_QSD8X50_ST1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_QSD8X50_ST1
+# endif
+# define machine_is_qsd8x50_st1() (machine_arch_type == MACH_TYPE_QSD8X50_ST1)
+#else
+# define machine_is_qsd8x50_st1() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9M10EKES
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9M10EKES
+# endif
+# define machine_is_at91sam9m10ekes() (machine_arch_type == MACH_TYPE_AT91SAM9M10EKES)
+#else
+# define machine_is_at91sam9m10ekes() (0)
+#endif
+
+#ifdef CONFIG_MACH_HIRAM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HIRAM
+# endif
+# define machine_is_hiram() (machine_arch_type == MACH_TYPE_HIRAM)
+#else
+# define machine_is_hiram() (0)
+#endif
+
+#ifdef CONFIG_MACH_PHY3250
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PHY3250
+# endif
+# define machine_is_phy3250() (machine_arch_type == MACH_TYPE_PHY3250)
+#else
+# define machine_is_phy3250() (0)
+#endif
+
+#ifdef CONFIG_MACH_EA3250
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EA3250
+# endif
+# define machine_is_ea3250() (machine_arch_type == MACH_TYPE_EA3250)
+#else
+# define machine_is_ea3250() (0)
+#endif
+
+#ifdef CONFIG_MACH_FDI3250
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_FDI3250
+# endif
+# define machine_is_fdi3250() (machine_arch_type == MACH_TYPE_FDI3250)
+#else
+# define machine_is_fdi3250() (0)
+#endif
+
+#ifdef CONFIG_MACH_WHITESTONE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WHITESTONE
+# endif
+# define machine_is_whitestone() (machine_arch_type == MACH_TYPE_WHITESTONE)
+#else
+# define machine_is_whitestone() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9263NIT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9263NIT
+# endif
+# define machine_is_at91sam9263nit() (machine_arch_type == MACH_TYPE_AT91SAM9263NIT)
+#else
+# define machine_is_at91sam9263nit() (0)
+#endif
+
+#ifdef CONFIG_MACH_CCMX51
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CCMX51
+# endif
+# define machine_is_ccmx51() (machine_arch_type == MACH_TYPE_CCMX51)
+#else
+# define machine_is_ccmx51() (0)
+#endif
+
+#ifdef CONFIG_MACH_CCMX51JS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CCMX51JS
+# endif
+# define machine_is_ccmx51js() (machine_arch_type == MACH_TYPE_CCMX51JS)
+#else
+# define machine_is_ccmx51js() (0)
+#endif
+
+#ifdef CONFIG_MACH_CCWMX51
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CCWMX51
+# endif
+# define machine_is_ccwmx51() (machine_arch_type == MACH_TYPE_CCWMX51)
+#else
+# define machine_is_ccwmx51() (0)
+#endif
+
+#ifdef CONFIG_MACH_CCWMX51JS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CCWMX51JS
+# endif
+# define machine_is_ccwmx51js() (machine_arch_type == MACH_TYPE_CCWMX51JS)
+#else
+# define machine_is_ccwmx51js() (0)
+#endif
+
+#ifdef CONFIG_MACH_MINI6410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MINI6410
+# endif
+# define machine_is_mini6410() (machine_arch_type == MACH_TYPE_MINI6410)
+#else
+# define machine_is_mini6410() (0)
+#endif
+
+#ifdef CONFIG_MACH_TINY6410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TINY6410
+# endif
+# define machine_is_tiny6410() (machine_arch_type == MACH_TYPE_TINY6410)
+#else
+# define machine_is_tiny6410() (0)
+#endif
+
+#ifdef CONFIG_MACH_NANO6410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NANO6410
+# endif
+# define machine_is_nano6410() (machine_arch_type == MACH_TYPE_NANO6410)
+#else
+# define machine_is_nano6410() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT572D940HFNLDB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT572D940HFNLDB
+# endif
+# define machine_is_at572d940hfnldb() (machine_arch_type == MACH_TYPE_AT572D940HFNLDB)
+#else
+# define machine_is_at572d940hfnldb() (0)
+#endif
+
+#ifdef CONFIG_MACH_HTCLEO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HTCLEO
+# endif
+# define machine_is_htcleo() (machine_arch_type == MACH_TYPE_HTCLEO)
+#else
+# define machine_is_htcleo() (0)
+#endif
+
+#ifdef CONFIG_MACH_AVP13
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AVP13
+# endif
+# define machine_is_avp13() (machine_arch_type == MACH_TYPE_AVP13)
+#else
+# define machine_is_avp13() (0)
+#endif
+
+#ifdef CONFIG_MACH_XXSVIDEOD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_XXSVIDEOD
+# endif
+# define machine_is_xxsvideod() (machine_arch_type == MACH_TYPE_XXSVIDEOD)
+#else
+# define machine_is_xxsvideod() (0)
+#endif
+
+#ifdef CONFIG_MACH_VPNEXT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VPNEXT
+# endif
+# define machine_is_vpnext() (machine_arch_type == MACH_TYPE_VPNEXT)
+#else
+# define machine_is_vpnext() (0)
+#endif
+
+#ifdef CONFIG_MACH_SWARCO_ITC3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SWARCO_ITC3
+# endif
+# define machine_is_swarco_itc3() (machine_arch_type == MACH_TYPE_SWARCO_ITC3)
+#else
+# define machine_is_swarco_itc3() (0)
+#endif
+
+#ifdef CONFIG_MACH_TX51
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TX51
+# endif
+# define machine_is_tx51() (machine_arch_type == MACH_TYPE_TX51)
+#else
+# define machine_is_tx51() (0)
+#endif
+
+#ifdef CONFIG_MACH_DOLBY_CAT1021
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DOLBY_CAT1021
+# endif
+# define machine_is_dolby_cat1021() (machine_arch_type == MACH_TYPE_DOLBY_CAT1021)
+#else
+# define machine_is_dolby_cat1021() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX28EVK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX28EVK
+# endif
+# define machine_is_mx28evk() (machine_arch_type == MACH_TYPE_MX28EVK)
+#else
+# define machine_is_mx28evk() (0)
+#endif
+
+#ifdef CONFIG_MACH_PHOENIX260
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PHOENIX260
+# endif
+# define machine_is_phoenix260() (machine_arch_type == MACH_TYPE_PHOENIX260)
+#else
+# define machine_is_phoenix260() (0)
+#endif
+
+#ifdef CONFIG_MACH_UVACA_STORK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_UVACA_STORK
+# endif
+# define machine_is_uvaca_stork() (machine_arch_type == MACH_TYPE_UVACA_STORK)
+#else
+# define machine_is_uvaca_stork() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTQ5
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMARTQ5
+# endif
+# define machine_is_smartq5() (machine_arch_type == MACH_TYPE_SMARTQ5)
+#else
+# define machine_is_smartq5() (0)
+#endif
+
+#ifdef CONFIG_MACH_ALL3078
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ALL3078
+# endif
+# define machine_is_all3078() (machine_arch_type == MACH_TYPE_ALL3078)
+#else
+# define machine_is_all3078() (0)
+#endif
+
+#ifdef CONFIG_MACH_CTERA_2BAY_DS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CTERA_2BAY_DS
+# endif
+# define machine_is_ctera_2bay_ds() (machine_arch_type == MACH_TYPE_CTERA_2BAY_DS)
+#else
+# define machine_is_ctera_2bay_ds() (0)
+#endif
+
+#ifdef CONFIG_MACH_SIOGENTOO3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SIOGENTOO3
+# endif
+# define machine_is_siogentoo3() (machine_arch_type == MACH_TYPE_SIOGENTOO3)
+#else
+# define machine_is_siogentoo3() (0)
+#endif
+
+#ifdef CONFIG_MACH_EPB5000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EPB5000
+# endif
+# define machine_is_epb5000() (machine_arch_type == MACH_TYPE_EPB5000)
+#else
+# define machine_is_epb5000() (0)
+#endif
+
+#ifdef CONFIG_MACH_HY9263
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HY9263
+# endif
+# define machine_is_hy9263() (machine_arch_type == MACH_TYPE_HY9263)
+#else
+# define machine_is_hy9263() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_TEMPO_M900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_TEMPO_M900
+# endif
+# define machine_is_acer_tempo_m900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_M900)
+#else
+# define machine_is_acer_tempo_m900() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_TEMPO_DX900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_TEMPO_DX900
+# endif
+# define machine_is_acer_tempo_dx650() (machine_arch_type == MACH_TYPE_ACER_TEMPO_DX900)
+#else
+# define machine_is_acer_tempo_dx650() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_TEMPO_X960
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_TEMPO_X960
+# endif
+# define machine_is_acer_tempo_x960() (machine_arch_type == MACH_TYPE_ACER_TEMPO_X960)
+#else
+# define machine_is_acer_tempo_x960() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_ETEN_V900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_ETEN_V900
+# endif
+# define machine_is_acer_eten_v900() (machine_arch_type == MACH_TYPE_ACER_ETEN_V900)
+#else
+# define machine_is_acer_eten_v900() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_ETEN_X900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_ETEN_X900
+# endif
+# define machine_is_acer_eten_x900() (machine_arch_type == MACH_TYPE_ACER_ETEN_X900)
+#else
+# define machine_is_acer_eten_x900() (0)
+#endif
+
+#ifdef CONFIG_MACH_BONNELL
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BONNELL
+# endif
+# define machine_is_bonnell() (machine_arch_type == MACH_TYPE_BONNELL)
+#else
+# define machine_is_bonnell() (0)
+#endif
+
+#ifdef CONFIG_MACH_OHT_MX27
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OHT_MX27
+# endif
+# define machine_is_oht_mx27() (machine_arch_type == MACH_TYPE_OHT_MX27)
+#else
+# define machine_is_oht_mx27() (0)
+#endif
+
+#ifdef CONFIG_MACH_HTCQUARTZ
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HTCQUARTZ
+# endif
+# define machine_is_htcquartz() (machine_arch_type == MACH_TYPE_HTCQUARTZ)
+#else
+# define machine_is_htcquartz() (0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DM6467TEVM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DAVINCI_DM6467TEVM
+# endif
+# define machine_is_davinci_dm6467tevm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467TEVM)
+#else
+# define machine_is_davinci_dm6467tevm() (0)
+#endif
+
+#ifdef CONFIG_MACH_C3AX03
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_C3AX03
+# endif
+# define machine_is_c3ax03() (machine_arch_type == MACH_TYPE_C3AX03)
+#else
+# define machine_is_c3ax03() (0)
+#endif
+
+#ifdef CONFIG_MACH_MXT_TD60
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MXT_TD60
+# endif
+# define machine_is_mxt_td60() (machine_arch_type == MACH_TYPE_MXT_TD60)
+#else
+# define machine_is_mxt_td60() (0)
+#endif
+
+#ifdef CONFIG_MACH_ESYX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ESYX
+# endif
+# define machine_is_esyx() (machine_arch_type == MACH_TYPE_ESYX)
+#else
+# define machine_is_esyx() (0)
+#endif
+
+#ifdef CONFIG_MACH_DOVE_DB2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DOVE_DB2
+# endif
+# define machine_is_dove_db2() (machine_arch_type == MACH_TYPE_DOVE_DB2)
+#else
+# define machine_is_dove_db2() (0)
+#endif
+
+#ifdef CONFIG_MACH_BULLDOG
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BULLDOG
+# endif
+# define machine_is_bulldog() (machine_arch_type == MACH_TYPE_BULLDOG)
+#else
+# define machine_is_bulldog() (0)
+#endif
+
+#ifdef CONFIG_MACH_DERELL_ME2000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DERELL_ME2000
+# endif
+# define machine_is_derell_me2000() (machine_arch_type == MACH_TYPE_DERELL_ME2000)
+#else
+# define machine_is_derell_me2000() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_BASE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_BASE
+# endif
+# define machine_is_bcmring_base() (machine_arch_type == MACH_TYPE_BCMRING_BASE)
+#else
+# define machine_is_bcmring_base() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_EVM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_EVM
+# endif
+# define machine_is_bcmring_evm() (machine_arch_type == MACH_TYPE_BCMRING_EVM)
+#else
+# define machine_is_bcmring_evm() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_EVM_JAZZ
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_EVM_JAZZ
+# endif
+# define machine_is_bcmring_evm_jazz() (machine_arch_type == MACH_TYPE_BCMRING_EVM_JAZZ)
+#else
+# define machine_is_bcmring_evm_jazz() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_SP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_SP
+# endif
+# define machine_is_bcmring_sp() (machine_arch_type == MACH_TYPE_BCMRING_SP)
+#else
+# define machine_is_bcmring_sp() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_SV
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_SV
+# endif
+# define machine_is_bcmring_sv() (machine_arch_type == MACH_TYPE_BCMRING_SV)
+#else
+# define machine_is_bcmring_sv() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_SV_JAZZ
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_SV_JAZZ
+# endif
+# define machine_is_bcmring_sv_jazz() (machine_arch_type == MACH_TYPE_BCMRING_SV_JAZZ)
+#else
+# define machine_is_bcmring_sv_jazz() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_TABLET
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_TABLET
+# endif
+# define machine_is_bcmring_tablet() (machine_arch_type == MACH_TYPE_BCMRING_TABLET)
+#else
+# define machine_is_bcmring_tablet() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_VP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_VP
+# endif
+# define machine_is_bcmring_vp() (machine_arch_type == MACH_TYPE_BCMRING_VP)
+#else
+# define machine_is_bcmring_vp() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_EVM_SEIKOR
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_EVM_SEIKOR
+# endif
+# define machine_is_bcmring_evm_seikor() (machine_arch_type == MACH_TYPE_BCMRING_EVM_SEIKOR)
+#else
+# define machine_is_bcmring_evm_seikor() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_SP_WQVGA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_SP_WQVGA
+# endif
+# define machine_is_bcmring_sp_wqvga() (machine_arch_type == MACH_TYPE_BCMRING_SP_WQVGA)
+#else
+# define machine_is_bcmring_sp_wqvga() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_CUSTOM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_CUSTOM
+# endif
+# define machine_is_bcmring_custom() (machine_arch_type == MACH_TYPE_BCMRING_CUSTOM)
+#else
+# define machine_is_bcmring_custom() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_S200
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_S200
+# endif
+# define machine_is_acer_s200() (machine_arch_type == MACH_TYPE_ACER_S200)
+#else
+# define machine_is_acer_s200() (0)
+#endif
+
+#ifdef CONFIG_MACH_BT270
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BT270
+# endif
+# define machine_is_bt270() (machine_arch_type == MACH_TYPE_BT270)
+#else
+# define machine_is_bt270() (0)
+#endif
+
+#ifdef CONFIG_MACH_ISEO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ISEO
+# endif
+# define machine_is_iseo() (machine_arch_type == MACH_TYPE_ISEO)
+#else
+# define machine_is_iseo() (0)
+#endif
+
+#ifdef CONFIG_MACH_CEZANNE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CEZANNE
+# endif
+# define machine_is_cezanne() (machine_arch_type == MACH_TYPE_CEZANNE)
+#else
+# define machine_is_cezanne() (0)
+#endif
+
+#ifdef CONFIG_MACH_LUCCA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LUCCA
+# endif
+# define machine_is_lucca() (machine_arch_type == MACH_TYPE_LUCCA)
+#else
+# define machine_is_lucca() (0)
+#endif
+
+#ifdef CONFIG_MACH_SUPERSMART
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SUPERSMART
+# endif
+# define machine_is_supersmart() (machine_arch_type == MACH_TYPE_SUPERSMART)
+#else
+# define machine_is_supersmart() (0)
+#endif
+
+#ifdef CONFIG_MACH_CS_MISANO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CS_MISANO
+# endif
+# define machine_is_arm11_board() (machine_arch_type == MACH_TYPE_CS_MISANO)
+#else
+# define machine_is_arm11_board() (0)
+#endif
+
+#ifdef CONFIG_MACH_MAGNOLIA2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MAGNOLIA2
+# endif
+# define machine_is_magnolia2() (machine_arch_type == MACH_TYPE_MAGNOLIA2)
+#else
+# define machine_is_magnolia2() (0)
+#endif
+
+#ifdef CONFIG_MACH_EMXX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EMXX
+# endif
+# define machine_is_emxx() (machine_arch_type == MACH_TYPE_EMXX)
+#else
+# define machine_is_emxx() (0)
+#endif
+
+#ifdef CONFIG_MACH_OUTLAW
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OUTLAW
+# endif
+# define machine_is_outlaw() (machine_arch_type == MACH_TYPE_OUTLAW)
+#else
+# define machine_is_outlaw() (0)
+#endif
+
+#ifdef CONFIG_MACH_RIOT_BEI2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_RIOT_BEI2
+# endif
+# define machine_is_riot_bei2() (machine_arch_type == MACH_TYPE_RIOT_BEI2)
+#else
+# define machine_is_riot_bei2() (0)
+#endif
+
+#ifdef CONFIG_MACH_RIOT_VOX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_RIOT_VOX
+# endif
+# define machine_is_riot_vox() (machine_arch_type == MACH_TYPE_RIOT_VOX)
+#else
+# define machine_is_riot_vox() (0)
+#endif
+
+#ifdef CONFIG_MACH_RIOT_X37
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_RIOT_X37
+# endif
+# define machine_is_riot_x37() (machine_arch_type == MACH_TYPE_RIOT_X37)
+#else
+# define machine_is_riot_x37() (0)
+#endif
+
+#ifdef CONFIG_MACH_MEGA25MX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MEGA25MX
+# endif
+# define machine_is_mega25mx() (machine_arch_type == MACH_TYPE_MEGA25MX)
+#else
+# define machine_is_mega25mx() (0)
+#endif
+
+#ifdef CONFIG_MACH_BENZINA2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BENZINA2
+# endif
+# define machine_is_benzina2() (machine_arch_type == MACH_TYPE_BENZINA2)
+#else
+# define machine_is_benzina2() (0)
+#endif
+
+#ifdef CONFIG_MACH_IGNITE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IGNITE
+# endif
+# define machine_is_ignite() (machine_arch_type == MACH_TYPE_IGNITE)
+#else
+# define machine_is_ignite() (0)
+#endif
+
+#ifdef CONFIG_MACH_FOGGIA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_FOGGIA
+# endif
+# define machine_is_foggia() (machine_arch_type == MACH_TYPE_FOGGIA)
+#else
+# define machine_is_foggia() (0)
+#endif
+
+#ifdef CONFIG_MACH_AREZZO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AREZZO
+# endif
+# define machine_is_arezzo() (machine_arch_type == MACH_TYPE_AREZZO)
+#else
+# define machine_is_arezzo() (0)
+#endif
+
+#ifdef CONFIG_MACH_LEICA_SKYWALKER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LEICA_SKYWALKER
+# endif
+# define machine_is_leica_skywalker() (machine_arch_type == MACH_TYPE_LEICA_SKYWALKER)
+#else
+# define machine_is_leica_skywalker() (0)
+#endif
+
+#ifdef CONFIG_MACH_JACINTO2_JAMR
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_JACINTO2_JAMR
+# endif
+# define machine_is_jacinto2_jamr() (machine_arch_type == MACH_TYPE_JACINTO2_JAMR)
+#else
+# define machine_is_jacinto2_jamr() (0)
+#endif
+
+#ifdef CONFIG_MACH_GTS_NOVA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GTS_NOVA
+# endif
+# define machine_is_gts_nova() (machine_arch_type == MACH_TYPE_GTS_NOVA)
+#else
+# define machine_is_gts_nova() (0)
+#endif
+
+#ifdef CONFIG_MACH_P3600
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_P3600
+# endif
+# define machine_is_p3600() (machine_arch_type == MACH_TYPE_P3600)
+#else
+# define machine_is_p3600() (0)
+#endif
+
+#ifdef CONFIG_MACH_DLT2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DLT2
+# endif
+# define machine_is_dlt2() (machine_arch_type == MACH_TYPE_DLT2)
+#else
+# define machine_is_dlt2() (0)
+#endif
+
+#ifdef CONFIG_MACH_DF3120
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DF3120
+# endif
+# define machine_is_df3120() (machine_arch_type == MACH_TYPE_DF3120)
+#else
+# define machine_is_df3120() (0)
+#endif
+
+#ifdef CONFIG_MACH_ECUCORE_9G20
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ECUCORE_9G20
+# endif
+# define machine_is_ecucore_9g20() (machine_arch_type == MACH_TYPE_ECUCORE_9G20)
+#else
+# define machine_is_ecucore_9g20() (0)
+#endif
+
+#ifdef CONFIG_MACH_NAUTEL_LPC3240
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NAUTEL_LPC3240
+# endif
+# define machine_is_nautel_lpc3240() (machine_arch_type == MACH_TYPE_NAUTEL_LPC3240)
+#else
+# define machine_is_nautel_lpc3240() (0)
+#endif
+
+#ifdef CONFIG_MACH_GLACIER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GLACIER
+# endif
+# define machine_is_glacier() (machine_arch_type == MACH_TYPE_GLACIER)
+#else
+# define machine_is_glacier() (0)
+#endif
+
+#ifdef CONFIG_MACH_PHRAZER_BULLDOG
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PHRAZER_BULLDOG
+# endif
+# define machine_is_phrazer_bulldog() (machine_arch_type == MACH_TYPE_PHRAZER_BULLDOG)
+#else
+# define machine_is_phrazer_bulldog() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_BULLDOG
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3_BULLDOG
+# endif
+# define machine_is_omap3_bulldog() (machine_arch_type == MACH_TYPE_OMAP3_BULLDOG)
+#else
+# define machine_is_omap3_bulldog() (0)
+#endif
+
+#ifdef CONFIG_MACH_PCA101
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PCA101
+# endif
+# define machine_is_pca101() (machine_arch_type == MACH_TYPE_PCA101)
+#else
+# define machine_is_pca101() (0)
+#endif
+
+#ifdef CONFIG_MACH_BUZZC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BUZZC
+# endif
+# define machine_is_buzzc() (machine_arch_type == MACH_TYPE_BUZZC)
+#else
+# define machine_is_buzzc() (0)
+#endif
+
+#ifdef CONFIG_MACH_SASIE2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SASIE2
+# endif
+# define machine_is_sasie2() (machine_arch_type == MACH_TYPE_SASIE2)
+#else
+# define machine_is_sasie2() (0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_CIO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DAVINCI_CIO
+# endif
+# define machine_is_davinci_cio() (machine_arch_type == MACH_TYPE_DAVINCI_CIO)
+#else
+# define machine_is_davinci_cio() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTMETER_DL
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMARTMETER_DL
+# endif
+# define machine_is_smartmeter_dl() (machine_arch_type == MACH_TYPE_SMARTMETER_DL)
+#else
+# define machine_is_smartmeter_dl() (0)
+#endif
+
+#ifdef CONFIG_MACH_WZL6410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WZL6410
+# endif
+# define machine_is_wzl6410() (machine_arch_type == MACH_TYPE_WZL6410)
+#else
+# define machine_is_wzl6410() (0)
+#endif
+
+#ifdef CONFIG_MACH_WZL6410M
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WZL6410M
+# endif
+# define machine_is_wzl6410m() (machine_arch_type == MACH_TYPE_WZL6410M)
+#else
+# define machine_is_wzl6410m() (0)
+#endif
+
+#ifdef CONFIG_MACH_WZL6410F
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WZL6410F
+# endif
+# define machine_is_wzl6410f() (machine_arch_type == MACH_TYPE_WZL6410F)
+#else
+# define machine_is_wzl6410f() (0)
+#endif
+
+#ifdef CONFIG_MACH_WZL6410I
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WZL6410I
+# endif
+# define machine_is_wzl6410i() (machine_arch_type == MACH_TYPE_WZL6410I)
+#else
+# define machine_is_wzl6410i() (0)
+#endif
+
+#ifdef CONFIG_MACH_SPACECOM1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SPACECOM1
+# endif
+# define machine_is_spacecom1() (machine_arch_type == MACH_TYPE_SPACECOM1)
+#else
+# define machine_is_spacecom1() (0)
+#endif
+
+#ifdef CONFIG_MACH_PINGU920
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PINGU920
+# endif
+# define machine_is_pingu920() (machine_arch_type == MACH_TYPE_PINGU920)
+#else
+# define machine_is_pingu920() (0)
+#endif
+
+#ifdef CONFIG_MACH_BRAVOC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BRAVOC
+# endif
+# define machine_is_bravoc() (machine_arch_type == MACH_TYPE_BRAVOC)
+#else
+# define machine_is_bravoc() (0)
+#endif
+
+#ifdef CONFIG_MACH_CYBO2440
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CYBO2440
+# endif
+# define machine_is_cybo2440() (machine_arch_type == MACH_TYPE_CYBO2440)
+#else
+# define machine_is_cybo2440() (0)
+#endif
+
+#ifdef CONFIG_MACH_VDSSW
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VDSSW
+# endif
+# define machine_is_vdssw() (machine_arch_type == MACH_TYPE_VDSSW)
+#else
+# define machine_is_vdssw() (0)
+#endif
+
+#ifdef CONFIG_MACH_ROMULUS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ROMULUS
+# endif
+# define machine_is_romulus() (machine_arch_type == MACH_TYPE_ROMULUS)
+#else
+# define machine_is_romulus() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_MAGIC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP_MAGIC
+# endif
+# define machine_is_omap_magic() (machine_arch_type == MACH_TYPE_OMAP_MAGIC)
+#else
+# define machine_is_omap_magic() (0)
+#endif
+
+#ifdef CONFIG_MACH_ELTD100
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ELTD100
+# endif
+# define machine_is_eltd100() (machine_arch_type == MACH_TYPE_ELTD100)
+#else
+# define machine_is_eltd100() (0)
+#endif
+
+#ifdef CONFIG_MACH_CAPC7117
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CAPC7117
+# endif
+# define machine_is_capc7117() (machine_arch_type == MACH_TYPE_CAPC7117)
+#else
+# define machine_is_capc7117() (0)
+#endif
+
+#ifdef CONFIG_MACH_SWAN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SWAN
+# endif
+# define machine_is_swan() (machine_arch_type == MACH_TYPE_SWAN)
+#else
+# define machine_is_swan() (0)
+#endif
+
/*
* These have not yet been registered
*/
#ifndef _ASM_ARM_UNALIGNED_H
#define _ASM_ARM_UNALIGNED_H
-#include <linux/unaligned/access_ok.h>
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/be_byteshift.h>
#include <linux/unaligned/generic.h>
/*
* first constant multiplications gets optimized away if the delay is
* a constant)
*/
-extern __inline__ void udelay(unsigned long usecs)
+extern __inline__ void __udelay(unsigned long usecs)
{
__delay(usecs);
}
--- /dev/null
+/*
+ * USB Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_USB__
+#define __BFIN_PERIPHERAL_USB__
+
+/* Bit masks for USB_FADDR */
+
+#define FUNCTION_ADDRESS 0x7f /* Function address */
+
+/* Bit masks for USB_POWER */
+
+#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
+#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
+#define RESUME_MODE 0x4 /* DMA Mode */
+#define RESET 0x8 /* Reset indicator */
+#define HS_MODE 0x10 /* High Speed mode indicator */
+#define HS_ENABLE 0x20 /* high Speed Enable */
+#define SOFT_CONN 0x40 /* Soft connect */
+#define ISO_UPDATE 0x80 /* Isochronous update */
+
+/* Bit masks for USB_INTRTX */
+
+#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
+#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
+#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
+#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
+#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
+#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
+#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
+#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
+
+/* Bit masks for USB_INTRRX */
+
+#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
+#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
+#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
+#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
+#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
+#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
+#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
+
+/* Bit masks for USB_INTRTXE */
+
+#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
+#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt enable */
+#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt enable */
+#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt enable */
+#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt enable */
+#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt enable */
+#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt enable */
+#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt enable */
+
+/* Bit masks for USB_INTRRXE */
+
+#define EP1_RX_E 0x02 /* Rx Endpoint 1 interrupt enable */
+#define EP2_RX_E 0x04 /* Rx Endpoint 2 interrupt enable */
+#define EP3_RX_E 0x08 /* Rx Endpoint 3 interrupt enable */
+#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt enable */
+#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt enable */
+#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt enable */
+#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt enable */
+
+/* Bit masks for USB_INTRUSB */
+
+#define SUSPEND_B 0x01 /* Suspend indicator */
+#define RESUME_B 0x02 /* Resume indicator */
+#define RESET_OR_BABLE_B 0x04 /* Reset/babble indicator */
+#define SOF_B 0x08 /* Start of frame */
+#define CONN_B 0x10 /* Connection indicator */
+#define DISCON_B 0x20 /* Disconnect indicator */
+#define SESSION_REQ_B 0x40 /* Session Request */
+#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
+
+/* Bit masks for USB_INTRUSBE */
+
+#define SUSPEND_BE 0x01 /* Suspend indicator int enable */
+#define RESUME_BE 0x02 /* Resume indicator int enable */
+#define RESET_OR_BABLE_BE 0x04 /* Reset/babble indicator int enable */
+#define SOF_BE 0x08 /* Start of frame int enable */
+#define CONN_BE 0x10 /* Connection indicator int enable */
+#define DISCON_BE 0x20 /* Disconnect indicator int enable */
+#define SESSION_REQ_BE 0x40 /* Session Request int enable */
+#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
+
+/* Bit masks for USB_FRAME */
+
+#define FRAME_NUMBER 0x7ff /* Frame number */
+
+/* Bit masks for USB_INDEX */
+
+#define SELECTED_ENDPOINT 0xf /* selected endpoint */
+
+/* Bit masks for USB_GLOBAL_CTL */
+
+#define GLOBAL_ENA 0x0001 /* enables USB module */
+#define EP1_TX_ENA 0x0002 /* Transmit endpoint 1 enable */
+#define EP2_TX_ENA 0x0004 /* Transmit endpoint 2 enable */
+#define EP3_TX_ENA 0x0008 /* Transmit endpoint 3 enable */
+#define EP4_TX_ENA 0x0010 /* Transmit endpoint 4 enable */
+#define EP5_TX_ENA 0x0020 /* Transmit endpoint 5 enable */
+#define EP6_TX_ENA 0x0040 /* Transmit endpoint 6 enable */
+#define EP7_TX_ENA 0x0080 /* Transmit endpoint 7 enable */
+#define EP1_RX_ENA 0x0100 /* Receive endpoint 1 enable */
+#define EP2_RX_ENA 0x0200 /* Receive endpoint 2 enable */
+#define EP3_RX_ENA 0x0400 /* Receive endpoint 3 enable */
+#define EP4_RX_ENA 0x0800 /* Receive endpoint 4 enable */
+#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
+#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
+#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
+
+/* Bit masks for USB_OTG_DEV_CTL */
+
+#define SESSION 0x1 /* session indicator */
+#define HOST_REQ 0x2 /* Host negotiation request */
+#define HOST_MODE 0x4 /* indicates USBDRC is a host */
+#define VBUS0 0x8 /* Vbus level indicator[0] */
+#define VBUS1 0x10 /* Vbus level indicator[1] */
+#define LSDEV 0x20 /* Low-speed indicator */
+#define FSDEV 0x40 /* Full or High-speed indicator */
+#define B_DEVICE 0x80 /* A' or 'B' device indicator */
+
+/* Bit masks for USB_OTG_VBUS_IRQ */
+
+#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
+#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
+#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
+#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
+#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
+#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
+
+/* Bit masks for USB_OTG_VBUS_MASK */
+
+#define DRIVE_VBUS_ON_ENA 0x01 /* enable DRIVE_VBUS_ON interrupt */
+#define DRIVE_VBUS_OFF_ENA 0x02 /* enable DRIVE_VBUS_OFF interrupt */
+#define CHRG_VBUS_START_ENA 0x04 /* enable CHRG_VBUS_START interrupt */
+#define CHRG_VBUS_END_ENA 0x08 /* enable CHRG_VBUS_END interrupt */
+#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
+#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
+
+/* Bit masks for USB_CSR0 */
+
+#define RXPKTRDY 0x1 /* data packet receive indicator */
+#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
+#define STALL_SENT 0x4 /* STALL handshake sent */
+#define DATAEND 0x8 /* Data end indicator */
+#define SETUPEND 0x10 /* Setup end */
+#define SENDSTALL 0x20 /* Send STALL handshake */
+#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
+#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
+#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
+#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
+#define SETUPPKT_H 0x8 /* send Setup token host mode */
+#define ERROR_H 0x10 /* timeout error indicator host mode */
+#define REQPKT_H 0x20 /* Request an IN transaction host mode */
+#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
+#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
+
+/* Bit masks for USB_COUNT0 */
+
+#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
+
+/* Bit masks for USB_NAKLIMIT0 */
+
+#define EP0_NAK_LIMIT 0x1f /* frames/micro frames count after which EP0 timeouts */
+
+/* Bit masks for USB_TX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_RX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_TXCSR */
+
+#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
+#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
+#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
+#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
+#define STALL_SEND_T 0x10 /* issue a Stall handshake */
+#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
+#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
+#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
+#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
+#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
+#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
+#define ISO_T 0x4000 /* enable Isochronous transfers */
+#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
+#define ERROR_TH 0x4 /* error condition host mode */
+#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
+#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
+
+/* Bit masks for USB_TXCOUNT */
+
+#define TX_COUNT 0x1fff /* Byte len for the selected endpoint Tx FIFO */
+
+/* Bit masks for USB_RXCSR */
+
+#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
+#define FIFO_FULL_R 0x2 /* FIFO not empty */
+#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
+#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
+#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
+#define STALL_SEND_R 0x20 /* issue a Stall handshake */
+#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
+#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
+#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
+#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
+#define DISNYET_R 0x1000 /* disable Nyet handshakes */
+#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
+#define ISO_R 0x4000 /* enable Isochronous transfers */
+#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
+#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
+#define REQPKT_RH 0x20 /* request an IN transaction host mode */
+#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
+#define INCOMPRX_RH 0x100 /* large packet is split host mode */
+#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
+#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
+
+/* Bit masks for USB_RXCOUNT */
+
+#define RX_COUNT 0x1fff /* Packet byte len in the Rx FIFO */
+
+/* Bit masks for USB_TXTYPE */
+
+#define TARGET_EP_NO_T 0xf /* EP number */
+#define PROTOCOL_T 0xc /* transfer type */
+
+/* Bit masks for USB_TXINTERVAL */
+
+#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
+
+/* Bit masks for USB_RXTYPE */
+
+#define TARGET_EP_NO_R 0xf /* EP number */
+#define PROTOCOL_R 0xc /* transfer type */
+
+/* Bit masks for USB_RXINTERVAL */
+
+#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
+
+/* Bit masks for USB_DMA_INTERRUPT */
+
+#define DMA0_INT 0x1 /* DMA0 pending interrupt */
+#define DMA1_INT 0x2 /* DMA1 pending interrupt */
+#define DMA2_INT 0x4 /* DMA2 pending interrupt */
+#define DMA3_INT 0x8 /* DMA3 pending interrupt */
+#define DMA4_INT 0x10 /* DMA4 pending interrupt */
+#define DMA5_INT 0x20 /* DMA5 pending interrupt */
+#define DMA6_INT 0x40 /* DMA6 pending interrupt */
+#define DMA7_INT 0x80 /* DMA7 pending interrupt */
+
+/* Bit masks for USB_DMAxCONTROL */
+
+#define DMA_ENA 0x1 /* DMA enable */
+#define DIRECTION 0x2 /* direction of DMA transfer */
+#define MODE 0x4 /* DMA Bus error */
+#define INT_ENA 0x8 /* Interrupt enable */
+#define EPNUM 0xf0 /* EP number */
+#define BUSERROR 0x100 /* DMA Bus error */
+
+#endif
#define __isr__ void __attribute__ ((regparm(0)))
-#define DECLARE_INTERRUPT(x) \
- asm(".globl irq_"#x"\n" \
- "irq_"#x":\n" \
- "pusha \n" \
- "pushl $"#x"\n" \
- "pushl $irq_return\n" \
- "jmp do_irq\n"); \
- __isr__ irq_##x(void)
-
-#define DECLARE_EXCEPTION(x, f) \
- asm(".globl exp_"#x"\n" \
- "exp_"#x":\n" \
- "pusha \n" \
- "movl %esp, %ebx\n" \
- "movl $exception_stack, %eax\n" \
- "movl %eax, %esp \n" \
- "pushl %ebx\n" \
- "movl 32(%esp), %ebx\n" \
- "xorl %edx, %edx\n" \
- "movw 36(%esp), %dx\n" \
- "pushl %edx\n" \
- "pushl %ebx\n" \
- "pushl $"#x"\n" \
- "pushl $exp_return\n" \
- "jmp "#f"\n"); \
- __isr__ exp_##x(void)
-
#endif
#ifndef _U_BOOT_I386_H_
#define _U_BOOT_I386_H_ 1
-/* for the following variables, see start.S */
-extern ulong i386boot_start; /* code start (in flash) */
-extern ulong i386boot_end; /* code end (in flash) */
-extern ulong i386boot_romdata_start;/* datasegment in flash (also code+rodata end) */
-extern ulong i386boot_romdata_dest; /* data location segment in ram */
-extern ulong i386boot_romdata_size; /* size of data segment */
-extern ulong i386boot_bss_start; /* bss start */
-extern ulong i386boot_bss_size; /* bss size */
-extern ulong i386boot_stack_end; /* first usable RAM address after bss and stack */
-extern ulong i386boot_ram_end; /* end of ram */
-
-extern ulong i386boot_realmode; /* start of realmode entry code */
-extern ulong i386boot_realmode_size;/* size of realmode entry code */
-extern ulong i386boot_bios; /* start of BIOS emulation code */
-extern ulong i386boot_bios_size; /* size of BIOS emulation code */
-
-
/* cpu/.../cpu.c */
-int cpu_init(void);
+int cpu_init_r(void);
+int cpu_init_f(void);
/* cpu/.../timer.c */
void timer_isr(void *);
/* cpu/.../interrupts.c */
int cpu_init_interrupts(void);
-/* cpu/.../exceptions.c */
-int cpu_init_exceptions(void);
-
/* board/.../... */
int board_init(void);
int dram_init(void);
return result + ffz(tmp);
}
-#define ffs(x) generic_ffs(x)
-
/*
* hweightN: returns the hamming weight (i.e. the number
* of bits set) of a N-bit word
#ifndef _405GP_PCI_H
#define _405GP_PCI_H
+#include <pci.h>
+
/*----------------------------------------------------------------------------+
| 405GP PCI core memory map defines.
+----------------------------------------------------------------------------*/
#define PCIDEVID_405GP 0x0
+void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
+int pci_arbiter_enabled(void);
+int __pci_pre_init(struct pci_controller *hose);
+void __pci_target_init(struct pci_controller *hose);
+void __pci_master_init(struct pci_controller *hose);
+
#endif
#endif
#endif
+/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */
+#if defined(CONFIG_TSEC_ENET) && \
+ (defined(CONFIG_P1020) || defined(CONFIG_P1011))
+#define CONFIG_TSECV2
+#endif
+
+/* Number of TLB CAM entries we have on FSL Book-E chips */
+#if defined(CONFIG_E500MC)
+#define CONFIG_SYS_NUM_TLBCAMS 64
+#elif defined(CONFIG_E500)
+#define CONFIG_SYS_NUM_TLBCAMS 16
+#endif
+
/* Relocation to SDRAM works on all PPC boards */
#define CONFIG_RELOC_FIXUP_WORKS
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
unsigned int clk_adjust; /* */
unsigned int cpo_override;
unsigned int write_data_delay; /* DQS adjust */
+
+ unsigned int wrlvl_override;
+ unsigned int wrlvl_sample; /* Write leveling */
+ unsigned int wrlvl_start;
+
unsigned int half_strength_driver_enable;
unsigned int twoT_en;
unsigned int threeT_en;
/* Rtt impedance */
unsigned int rtt_override; /* rtt_override enable */
unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
+ unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
/* Automatic self refresh */
unsigned int auto_self_refresh_en;
LAW_SIZE_32G,
};
+#define law_size_bits(sz) (__ilog2_u64(sz) - 1)
+
#ifdef CONFIG_FSL_CORENET
enum law_trgt_if {
LAW_TRGT_IF_PCIE_1 = 0x00,
LAW_TRGT_IF_CCSR = 0x08,
LAW_TRGT_IF_DDR_INTRLV = 0x0b,
LAW_TRGT_IF_RIO = 0x0c,
+ LAW_TRGT_IF_RIO_2 = 0x0d,
LAW_TRGT_IF_DDR = 0x0f,
LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
};
-/* (C) Copyright 2007 Freescale Semiconductor, Inc.
+/*
+ * Copyright 2007,2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
#include <asm/fsl_law.h>
-int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent);
int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel);
+int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
+int fsl_is_pci_agent(struct pci_controller *hose);
void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data);
void fsl_pci_config_unlock(struct pci_controller *hose);
void ft_fsl_pci_setup(void *blob, const char *pci_alias,
#define PIWAR_LOCAL 0x00f00000
#define PIWAR_READ_SNOOP 0x00050000
#define PIWAR_WRITE_SNOOP 0x00005000
-#define PIWAR_IWS_4K 0x0000000b
u32 res2[3];
} pit_t;
};
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
- struct pci_controller *hose, int busno, int pcie_ep);
+ struct pci_controller *hose, int busno);
#define SET_STD_PCI_INFO(x, num) \
{ \
#if defined(CONFIG_FSL_LAW)
u32 used_laws;
#endif
+#if defined(CONFIG_E500)
+ u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
+#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;
unsigned long pci_clk;
/*
- * (C) Copyright 2004-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004-2009 Freescale Semiconductor, Inc.
*
* MPC83xx Internal Memory Map
*
#endif
#define CONFIG_SYS_MPC83xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
+
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_MDIO1_OFFSET 0x24000
+
+#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
#endif /* __IMMAP_83xx__ */
* Copyright(c) 2002,2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
*/
#ifndef __IMMAP_85xx__
u8 res[8];
} par_io_t;
+#ifdef CONFIG_SYS_FSL_CPC
+/*
+ * Define a single offset that is the start of all the CPC register
+ * blocks - if there is more than one CPC, we expect these to be
+ * contiguous 4k regions
+ */
+
+typedef struct cpc_corenet {
+ u32 cpccsr0; /* Config/status reg */
+ u32 res1;
+ u32 cpccfg0; /* Configuration register */
+ u32 res2;
+ u32 cpcewcr0; /* External Write reg 0 */
+ u32 cpcewabr0; /* External write base reg 0 */
+ u32 res3[2];
+ u32 cpcewcr1; /* External Write reg 1 */
+ u32 cpcewabr1; /* External write base reg 1 */
+ u32 res4[54];
+ u32 cpcsrcr1; /* SRAM control reg 1 */
+ u32 cpcsrcr0; /* SRAM control reg 0 */
+ u32 res5[62];
+ struct {
+ u32 id; /* partition ID */
+ u32 res;
+ u32 alloc; /* partition allocation */
+ u32 way; /* partition way */
+ } partition_regs[16];
+ u32 res6[704];
+ u32 cpcerrinjhi; /* Error injection high */
+ u32 cpcerrinjlo; /* Error injection lo */
+ u32 cpcerrinjctl; /* Error injection control */
+ u32 res7[5];
+ u32 cpccaptdatahi; /* capture data high */
+ u32 cpccaptdatalo; /* capture data low */
+ u32 cpcaptecc; /* capture ECC */
+ u32 res8[5];
+ u32 cpcerrdet; /* error detect */
+ u32 cpcerrdis; /* error disable */
+ u32 cpcerrinten; /* errir interrupt enable */
+ u32 cpcerrattr; /* error attribute */
+ u32 cpcerreaddr; /* error extended address */
+ u32 cpcerraddr; /* error address */
+ u32 cpcerrctl; /* error control */
+ u32 res9[105]; /* pad out to 4k */
+} cpc_corenet_t;
+
+#define CPC_CSR0_CE 0x80000000 /* Cache Enable */
+#define CPC_CSR0_PE 0x40000000 /* Enable ECC */
+#define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
+#define CPC_CSR0_WT 0x00080000 /* Write-through mode */
+#define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
+#define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
+#define CPC_CFG0_SZ_MASK 0x00003fff
+#define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
+#define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
+#define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
+#define CPC_SRCR1_SRBARU_MASK 0x0000ffff
+#define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
+ & CPC_SRCR1_SRBARU_MASK)
+#define CPC_SRCR0_SRBARL_MASK 0xffff8000
+#define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
+#define CPC_SRCR0_INTLVEN 0x00000100
+#define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
+#define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
+#define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
+#define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
+#define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
+#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
+#define CPC_SRCR0_SRAMEN 0x00000001
+#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
+#endif /* CONFIG_SYS_FSL_CPC */
+
/* Global Utilities Block */
#ifdef CONFIG_FSL_CORENET
typedef struct ccsr_gur {
} ccsr_gur_t;
#endif
+typedef struct serdes_corenet {
+ struct {
+ u32 rstctl; /* Reset Control Register */
+#define SRDS_RSTCTL_RST 0x80000000
+#define SRDS_RSTCTL_RSTDONE 0x40000000
+#define SRDS_RSTCTL_RSTERR 0x20000000
+ u32 pllcr0; /* PLL Control Register 0 */
+ u32 pllcr1; /* PLL Control Register 1 */
+#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
+ u32 res[5];
+ } bank[3];
+ u32 res1[12];
+ u32 srdstcalcr; /* TX Calibration Control */
+ u32 res2[3];
+ u32 srdsrcalcr; /* RX Calibration Control */
+ u32 res3[3];
+ u32 srdsgr0; /* General Register 0 */
+ u32 res4[11];
+ u32 srdspccr0; /* Protocol Converter Config 0 */
+ u32 srdspccr1; /* Protocol Converter Config 1 */
+ u32 srdspccr2; /* Protocol Converter Config 2 */
+#define SRDS_PCCR2_RST_XGMII1 0x00800000
+#define SRDS_PCCR2_RST_XGMII2 0x00400000
+ u32 res5[197];
+ struct {
+ u32 gcr0; /* General Control Register 0 */
+#define SRDS_GCR0_RRST 0x00400000
+#define SRDS_GCR0_1STLANE 0x00010000
+ u32 gcr1; /* General Control Register 1 */
+#define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
+#define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
+#define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
+#define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
+#define SRDS_GCR1_OPAD_CTL 0x04000000
+ u32 res1[4];
+ u32 tecr0; /* TX Equalization Control Reg 0 */
+#define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
+#define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
+ u32 res3;
+ u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
+ u32 res4[7];
+ } lane[24];
+ u32 res6[384];
+} serdes_corenet_t;
+
+enum {
+ FSL_SRDS_B1_LANE_A = 0,
+ FSL_SRDS_B1_LANE_B = 1,
+ FSL_SRDS_B1_LANE_C = 2,
+ FSL_SRDS_B1_LANE_D = 3,
+ FSL_SRDS_B1_LANE_E = 4,
+ FSL_SRDS_B1_LANE_F = 5,
+ FSL_SRDS_B1_LANE_G = 6,
+ FSL_SRDS_B1_LANE_H = 7,
+ FSL_SRDS_B1_LANE_I = 8,
+ FSL_SRDS_B1_LANE_J = 9,
+ FSL_SRDS_B2_LANE_A = 16,
+ FSL_SRDS_B2_LANE_B = 17,
+ FSL_SRDS_B2_LANE_C = 18,
+ FSL_SRDS_B2_LANE_D = 19,
+ FSL_SRDS_B3_LANE_A = 20,
+ FSL_SRDS_B3_LANE_B = 21,
+ FSL_SRDS_B3_LANE_C = 22,
+ FSL_SRDS_B3_LANE_D = 23,
+};
+
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000
#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
+#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
+#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
+#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000
#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000
#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000
#else
#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
+#ifdef CONFIG_TSECV2
+#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
+#else
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#endif
+#define CONFIG_SYS_MDIO1_OFFSET 0x24000
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
+#define CONFIG_SYS_FSL_CPC_ADDR \
+ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
#define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET)
#define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
#define CONFIG_SYS_MPC85xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
+#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+
#endif /*__IMMAP_85xx__*/
/*
* MPC86xx Internal Memory Map
*
- * Copyright(c) 2004 Freescale Semiconductor
+ * Copyright 2004 Freescale Semiconductor
* Jeff Brown (Jeffrey@freescale.com)
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
#define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000)
#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_MDIO1_OFFSET 0x24000
+
+#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+
#endif /*__IMMAP_86xx__*/
extern void invalidate_tlb(u8 tlb);
extern void init_tlbs(void);
extern int find_tlb_idx(void *addr, u8 tlbsel);
+extern void init_used_tlb_cams(void);
+extern int find_free_tlbcam(void);
extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
#endif
#endif
+#define IS_SVR_REV(svr, maj, min) \
+ ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
+
/*
* SVR_SOC_VER() Version Values
*/
#ifdef CONFIG_BLACKFIN
#include <asm/blackfin.h>
#endif
+#ifdef CONFIG_SOC_DA8XX
+#include <asm/arch/hardware.h>
+#endif
#include <part.h>
#include <flash.h>
void wait_ticks (unsigned long);
/* lib_$(ARCH)/time.c */
-void udelay (unsigned long);
+void __udelay (unsigned long);
ulong usec2ticks (unsigned long usec);
ulong ticks2usec (unsigned long ticks);
int init_timebase (void);
+/* lib_generic/gunzip.c */
+int gunzip(void *, int, unsigned char *, unsigned long *);
+int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp,
+ int stoponerr, int offset);
+
+/* lib_generic/time.c */
+void udelay (unsigned long);
+
/* lib_generic/vsprintf.c */
ulong simple_strtoul(const char *cp,char **endp,unsigned int base);
-#ifdef CONFIG_SYS_64BIT_VSPRINTF
unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base);
-#endif
long simple_strtol(const char *cp,char **endp,unsigned int base);
void panic(const char *fmt, ...)
__attribute__ ((format (__printf__, 1, 2)));
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#ifdef CONFIG_PCI2
-#define CONFIG_SYS_PCI2_MEM_BASE 0xC0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_BUS 0xC0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS
#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
#endif
#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
#endif
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE 0x04000300 /* base address */
#define CONFIG_SMC_USE_32_BIT
#undef CONFIG_SHOW_ACTIVITY
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
-
+#define CONFIG_NET_MULTI
#define CONFIG_BOOTDELAY 5
#define CONFIG_ETHADDR 00:50:c2:1e:af:fb
#define CONFIG_BOOTARGS "setenv bootargs root=/dev/ram ip=192.168.0.70:::::eth0:off \
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-#define CONFIG_SYS_PCI_IOBASE 0xe8000000
-
+#define CONFIG_SYS_PCI_IOBASE 0xe8000000
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
+#define CONFIG_SYS_PCI_SUBSYS_ID 0x0444 /* device ID for DU440 */
/* Don't change either of these */
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
#define CONFIG_SYS_NAND0_BASE 0xE1000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#endif /* CONFIG_CMD_NAND */
/*-----------------------------------------------------------------------
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
#ifndef __CONFIG_H
#define __CONFIG_H
+#ifdef CONFIG_MK_NAND
+#define CONFIG_NAND_U_BOOT 1
+#define CONFIG_RAMBOOT_TEXT_BASE 0x00100000
+#endif
+
/*
* High Level Configuration Options
*/
HRCWL_SVCOD_DIV_2 |\
HRCWL_CSB_TO_CLKIN_2X1 |\
HRCWL_CORE_TO_CSB_3X1)
-#define CONFIG_SYS_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH_BASE (\
HRCWH_PCI_HOST |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
HRCWH_TSEC1M_IN_RGMII |\
HRCWH_TSEC2M_IN_RGMII |\
HRCWH_BIG_ENDIAN |\
HRCWH_LALE_NORMAL)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
+ HRCWH_FROM_0XFFF00100 |\
+ HRCWH_ROM_LOC_NAND_SP_8BIT |\
+ HRCWH_RL_EXT_NAND)
+#else
+#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_RL_EXT_LEGACY)
+#endif
+
/*
* System IO Config
*/
*/
#define CONFIG_SYS_IMMR 0xE0000000
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
+#endif
+
/*
* Arbiter Setup
*/
*/
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
-#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
+#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
| (2 << BR_PS_SHIFT) /* 16 bit port size */ \
| BR_V ) /* valid */
-#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+#define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
/*
* NAND Flash on the Local Bus
*/
-#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
+
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE 0xFFF00000
+#else
+#define CONFIG_SYS_NAND_BASE 0xE0600000
+#endif
+
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \
+#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V ) /* valid */
-#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_EHTR )
/* 0xFFFF8396 */
+#ifdef CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
+#else
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
+#endif
+
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+
+#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
+ !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
/*
* Serial Port
*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*
* Environment
*/
-#ifndef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_NAND_U_BOOT)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET (512 * 1024)
+ #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+ #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+ #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+ #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
+ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
+ CONFIG_ENV_RANGE)
+#elif !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PCI
-#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | \
+ BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
#define CONFIG_NAND_FSL_UPM 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the CDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-
-
/*
* I2C
*/
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
#define CONFIG_FSL_VIA
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the CDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the CDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-
/* I2C */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_FSL_VIA
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the CDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
#define CONFIG_FSL_VIA
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the CDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the MDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif /*Replace a call to get_clock_freq (after it is implemented)*/
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the MDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
#define PLPDIR1_I2C_BIT_MASK 0x0000000F
#define PLPDIR1_I2C2_VAL 0x0000000F
#define PLPDIR1_ESDHC_VAL 0x00000006
+#define PLPPAR1_UART0_BIT_MASK 0x00000fc0
+#define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
+#define PLPDIR1_UART0_BIT_MASK 0x00000fc0
+#define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
/*
* General PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the CDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
/* DDR Setup */
-#define CONFIG_SYS_DDR_TLB_START 9
#define CONFIG_VERY_BIG_RAM
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/* new uImage format support */
#define CONFIG_FIT 1
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_RUN
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
#define CONFIG_SYS_DDR_SBE 0x00FF0000
-#define CONFIG_SYS_DDR_TLB_START 9
-
/*
* Memory map
*
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/* new uImage format support */
#define CONFIG_FIT 1
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the CDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
#ifndef __ASSEMBLY__
extern unsigned long calculate_board_sys_clk(unsigned long dummy);
extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
/* DDR Setup */
-#define CONFIG_SYS_DDR_TLB_START 9
#define CONFIG_VERY_BIG_RAM
#define CONFIG_FSL_DDR3 1
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/* new uImage format support */
#define CONFIG_FIT 1
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
#define CONFIG_SUPPORT_VFAT
-#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*
* PCI stuff
*/
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFA0000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserve 384kB for malloc() */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
/*
* Environment Variable setup
/*
* External Bus Controller (EBC) Setup
*/
-#define CAN_BA 0xF0000000 /* CAN Base Address */
+#define CAN0_BA 0xF0000000 /* CAN0 Base Address */
+#define CAN1_BA 0xF0000100 /* CAN1 Base Address */
#define DUART0_BA 0xF0000400 /* DUART Base Address */
#define DUART1_BA 0xF0000408 /* DUART Base Address */
#define RTC_BA 0xF0000500 /* RTC Base Address */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
#define CONFIG_USB_STORAGE 1
+/*
+ * UBI
+ */
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
#endif /* __CONFIG_H */
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
/* PCI identification */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */
#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
+/* for weak __pci_target_init() */
+#define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
*-----------------------------------------------------------------------
*/
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*
* nand device 1 on dave (PPChameleonEVB) needs more time,
* so we just introduce additional wait in nand_wait(),
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
WRITE_NAND(d, addr); \
} while(0)
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#endif /* CONFIG_CMD_NAND */
#define CONFIG_PCI
#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#endif /* CONFIG_NAND */
/*
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Configuation settings for the Faraday A320 board.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/a320.h>
+
+/*-----------------------------------------------------------------------
+ * CPU and Board Configuration Options
+ */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*-----------------------------------------------------------------------
+ * Timer
+ */
+#define CONFIG_SYS_HZ 1000 /* timer ticks per second */
+
+/*-----------------------------------------------------------------------
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*-----------------------------------------------------------------------
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART */
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1 0x98200000
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_CLK 18432000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY 3
+
+/*-----------------------------------------------------------------------
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+
+/*-----------------------------------------------------------------------
+ * size in bytes reserved for initial data
+*/
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*-----------------------------------------------------------------------
+ * SDRAM controller configuration
+ */
+#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \
+ FTSDMC020_TP0_TRP(1) | \
+ FTSDMC020_TP0_TRCD(1) | \
+ FTSDMC020_TP0_TRF(3) | \
+ FTSDMC020_TP0_TWR(1) | \
+ FTSDMC020_TP0_TCL(2))
+
+#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \
+ FTSDMC020_TP1_INI_REFT(8) | \
+ FTSDMC020_TP1_REF_INTV(0x180))
+
+#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \
+ FTSDMC020_BANK_DDW_X16 | \
+ FTSDMC020_BANK_DSZ_256M | \
+ FTSDMC020_BANK_MBW_32 | \
+ FTSDMC020_BANK_SIZE_64M)
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+/*
+ * Load address and memory test area should agree with
+ * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x12000000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x13F00000
+
+/*-----------------------------------------------------------------------
+ * Static memory controller configuration
+ */
+
+#include <asm/arch/ftsmc020.h>
+
+#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
+ FTSMC020_BANK_SIZE_1M | \
+ FTSMC020_BANK_MBW_8)
+
+#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
+ FTSMC020_TPR_AST(3) | \
+ FTSMC020_TPR_CTW(3) | \
+ FTSMC020_TPR_ATI(0xf) | \
+ FTSMC020_TPR_AT2(3) | \
+ FTSMC020_TPR_WTC(3) | \
+ FTSMC020_TPR_AHT(3) | \
+ FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_BASE(PHYS_FLASH_2) | \
+ FTSMC020_BANK_SIZE_32M | \
+ FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \
+ FTSMC020_TPR_CTW(3) | \
+ FTSMC020_TPR_ATI(0xf) | \
+ FTSMC020_TPR_AT2(3) | \
+ FTSMC020_TPR_WTC(3) | \
+ FTSMC020_TPR_AHT(3) | \
+ FTSMC020_TPR_TRNA(0xf))
+
+#define CONFIG_SYS_FTSMC020_CONFIGS { \
+ { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
+ { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
+}
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* support JEDEC */
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_LEGACY_512Kx8
+
+#define PHYS_FLASH_1 0x00000000
+#define PHYS_FLASH_2 0x00400000
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
+
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR 0x00060000
+#define CONFIG_ENV_SIZE 0x20000
+
+#endif /* __CONFIG_H */
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* NOR flash - no real flash on this board */
*/
#include <config_cmd_default.h>
-#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
#undef CONFIG_CMD_NFS
#undef CONFIG_WATCHDOG /* watchdog disabled */
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE_FLEX SZ_256K
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_1M)
/* bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* SMC91c96 Etherent
*/
-#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_NET_MULTI
+#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE (APOLLON_CS1_BASE+0x300)
#define CONFIG_LAN91C96_EXT_PHY
/*
* Miscellaneous configurable options
*/
-#define V_PROMPT "Apollon # "
-
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT V_PROMPT
+#define CONFIG_SYS_PROMPT "Apollon # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MONITOR_LEN SZ_256K /* U-Boot image size */
#define CONFIG_ENV_IS_IN_ONENAND 1
#define CONFIG_ENV_ADDR 0x00020000
-
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#define CONFIG_ENV_ADDR_FLEX 0x00040000
#ifdef CONFIG_SYS_USE_UBI
#define CONFIG_CMD_MTDPARTS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*
* Configuration parameters for MPC5121 NAND driver
*/
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_LAN91C96 /* we have an SMC9194 on-board */
+#define CONFIG_NET_MULTI
+#define CONFIG_LAN91C96 /* we have an SMC9194 on-board */
#define CONFIG_LAN91C96_BASE 0x18000000
/*
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* NOR flash - no real flash on this board */
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* NOR flash - no real flash on this board */
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
/* NOR flash, if populated */
#ifndef CONFIG_CMD_NAND
#define CONFIG_SYS_NO_FLASH 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#else
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet - not present */
# define CONFIG_CMD_SPIBOOTLDR
# endif
#endif
-#ifdef CONFIG_CMD_NAND
-# define CONFIG_SYS_64BIT_VSPRINTF
-#endif
/*
* Console Settings
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
#endif /* !defined(CONFIG_ARCHES) */
-#define CONFIG_SYS_EBC_CFG 0xB8400000 /* EBC0_CFG */
+#define CONFIG_SYS_EBC_CFG 0xbfc00000
/*
* Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/* NOR flash */
#define CONFIG_SYS_FLASH_CFI 1
--- /dev/null
+/*
+ * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com>
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_DA830_EVM
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ 24000000
+#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
+#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* memtest start addr */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) /* 16MB test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */
+#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+
+/*
+ * I2C EEPROM definitions for catalyst 24W256 EEPROM chip
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#endif
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_CS 3
+#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_CLE_MASK 0x10
+#define CONFIG_SYS_ALE_MASK 0x8
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define DEF_BOOTM ""
+#endif
+
+#ifdef CONFIG_USE_NOR
+#define CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ (64 << 10) /* 64KB */
+#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3)
+#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define PHYS_FLASH_SIZE (32 << 20) /* Flash size 32MB */
+#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
+#define CONFIG_SYS_FLASH_SPL_ACCESS
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE (16 << 10)
+#define CONFIG_ENV_OFFSET (256 << 10)
+#define CONFIG_ENV_SECT_SIZE 4096
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE
+#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED 50000000
+#define CONFIG_SYS_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#endif
+
+/*
+ * USB configuration
+ */
+#define CONFIG_USB_DA8XX /* Platform hookup to MUSB controller */
+#define CONFIG_MUSB_HCD
+
+/*
+ * U-Boot general configuration
+ */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#undef CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "DA830-evm > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock/2 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND ""
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_EEPROM
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SAVEENV
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+ !defined(CONFIG_USE_NOR) && \
+ !defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE (16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_ENV
+#endif
+
+#ifdef CONFIG_USB_DA8XX
+
+#ifdef CONFIG_MUSB_HCD /* include support for usb host */
+#define CONFIG_CMD_USB /* include support for usb cmd */
+
+#define CONFIG_USB_STORAGE /* MSC class support */
+#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
+#define CONFIG_CMD_FAT /* inclue support for FAT/storage */
+#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
+
+#ifdef CONFIG_USB_KEYBOARD /* HID class support */
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_PREBOOT "usb start"
+#endif /* CONFIG_USB_KEYBOARD */
+
+#endif /* CONFIG_MUSB_HCD */
+
+#ifdef CONFIG_MUSB_UDC
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID 0x0451
+#define CONFIG_USBD_PRODUCTID 0x5678
+#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME "DA830EVM"
+#endif /* CONFIG_MUSB_UDC */
+
+#endif /* CONFIG_USB_DA8XX */
+#endif /* __CONFIG_H */
/* NAND: socketed, two chipselects, normally 2 GBytes */
#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
/* NAND */
#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x3C0000
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE
#endif
/* NAND: socketed, two chipselects, normally 2 GBytes */
#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
#define CONFIG_SYS_NO_FLASH
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS 2
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_SYS_NAND_BASE_LIST {0x42000000, }
#define CONFIG_SYS_NAND_HW_ECC
/*=====================*/
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS 2
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define DEF_BOOTM ""
#elif defined(CONFIG_SYS_USE_NOR)
#ifdef CONFIG_NOR_UART_BOOT
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS 2
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/*=====================*/
/* Board related stuff */
/*=====================*/
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS 2
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/* I2C switch definitions for PCA9543 chip */
#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70
#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
/*=====================*/
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS 2
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define DEF_BOOTM ""
#elif defined(CONFIG_SYS_USE_NOR)
#ifdef CONFIG_NOR_UART_BOOT
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/* nand timeout values */
#define CONFIG_SYS_NAND_PROG_ERASE_TO 3000
#define CONFIG_SYS_NAND_OTHER_TO 100
/* Hardware drivers */
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* DM9000 */
#define CONFIG_NET_MULTI 1
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_RELOC_FIXUP_WORKS
+
/*
* Stuff still to be dealt with -
*/
/*
* Size of malloc() pool
*/
-#define CONFIG_MALLOC_SIZE (CONFIG_SYS_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
#define CONFIG_BAUDRATE 9600
#ifndef __ASSEMBLER__
extern unsigned long ip;
-#define PRINTIP asm ("call next_line\n" \
- "next_line:\n" \
+#define PRINTIP asm ("call 0\n" \
+ "0:\n" \
"pop %%eax\n" \
"movl %%eax, %0\n" \
:"=r"(ip) \
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_LAN91C96 /* we have an SMC9194 on-board */
+#define CONFIG_NET_MULTI
+#define CONFIG_LAN91C96 /* we have an SMC9194 on-board */
#define CONFIG_LAN91C96_BASE 0x100e0000
/*
/*
* MTD
*/
+#define CONFIG_FLASH_CFI_MTD
#define CONFIG_MTD_DEVICE
/*
#define CONFIG_SYS_NAND_BASE 0xd8000000
#define CONFIG_JFFS2_NAND
#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/*
* SD/MMC
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * MicroSys GmbH
+ *
+ * (C) Copyright 2009
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_MPC5200
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPX5200 1 /* ... on MPX5200 board */
+#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
+#define CONFIG_IPEK01 /* Motherboard is ipek01 */
+
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
+
+#define CONFIG_MISC_INIT_R
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#define CONFIG_BAUDRATE 115200 /* ... at 9600 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+
+/*
+ * Video configuration for LIME GDC
+ */
+#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
+/* Lime clock frequency */
+#define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */
+/* SDRAM parameter */
+#define CONFIG_SYS_MB862xx_MMR 0x41c767e3
+#endif
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI 1
+#define CONFIG_PCI_PNP 1
+#define CONFIG_PCI_SCAN_SHOW 1
+
+#define CONFIG_PCI_MEM_BUS 0x40000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x50000000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x01000000
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1
+#define CONFIG_EEPRO100 1
+#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP /* BMP support */
+#endif
+#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
+#define CONFIG_CMD_DHCP /* DHCP Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_IDE /* IDE harddisk support */
+#define CONFIG_CMD_IRQ /* irqinfo */
+#define CONFIG_CMD_MII /* MII support */
+#define CONFIG_CMD_PCI /* pciinfo */
+#define CONFIG_CMD_USB /* USB Support */
+
+#define CONFIG_SYS_LOWBOOT 1
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyPSC0\0" \
+ "hostname=ipek01\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} " \
+ "console=${consoledev},${baudrate}\0" \
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr} - ${fdtaddr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \
+ "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \
+ "run nfsargs addip addtty;" \
+ "bootm ${loadaddr} - ${fdtaddr}\0" \
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "bootfile=ipek01/uImage\0" \
+ "load=tftp 100000 ipek01/u-boot.bin\0" \
+ "update=protect off FC000000 +60000; era FC000000 +60000; " \
+ "cp.b 100000 FC000000 ${filesize}\0" \
+ "upd=run load;run update\0" \
+ "fdtaddr=800000\0" \
+ "loadaddr=400000\0" \
+ "fdtfile=ipek01/ipek01.dtb\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */
+/* PCI clock must be 33, because board will not boot */
+#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */
+
+/*
+ * Open firmware flat tree support
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,5200@0"
+#define OF_SOC "soc5200@f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51
+
+#define CONFIG_SYS_FLASH_BASE 0xFC000000
+#define CONFIG_SYS_FLASH_SIZE 0x01000000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+
+/* use CFI flash driver */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR 0xf0000000
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
+#define CONFIG_SYS_SRAM_BASE 0xF1000000
+#define CONFIG_SYS_SRAM_SIZE 0x00200000
+#define CONFIG_SYS_LIME_BASE 0xE4000000
+#define CONFIG_SYS_LIME_SIZE 0x04000000
+#define CONFIG_SYS_FPGA_BASE 0xC0000000
+#define CONFIG_SYS_FPGA_SIZE 0x10000000
+#define CONFIG_SYS_MPEG_BASE 0xe2000000
+#define CONFIG_SYS_MPEG_SIZE 0x01000000
+#define CONFIG_SYS_CF_BASE 0xe1000000
+#define CONFIG_SYS_CF_SIZE 0x01000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
+/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+
+
+
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT 1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR 0x00
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
+
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL HID0_ICE
+#else
+#define CONFIG_SYS_HID0_INIT 0
+#define CONFIG_SYS_HID0_FINAL 0
+#endif
+
+#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
+#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE
+#define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE
+#define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE
+#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE
+#define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE
+#define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE
+#define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE
+#define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE
+
+#ifdef CONFIG_SYS_PCISPEED_66
+#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
+#define CONFIG_SYS_CS1_CFG 0x0004FB00
+#define CONFIG_SYS_CS2_CFG 0x0006F900
+#else
+#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
+#define CONFIG_SYS_CS1_CFG 0x0001FB00
+#define CONFIG_SYS_CS2_CFG 0x0002F90C
+#endif
+
+/*
+ * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
+ * waitstates, writeswap and readswap enabled
+ */
+#define CONFIG_SYS_CS3_CFG 0x00FFFB0C
+#define CONFIG_SYS_CS6_CFG 0x00FFFB0C
+#define CONFIG_SYS_CS7_CFG 0x4040751C
+
+#define CONFIG_SYS_CS_BURST 0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE 0x33330000
+
+#define CONFIG_SYS_RESET_ADDRESS 0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK 0x0001BBBB
+#define CONFIG_USB_CONFIG 0x00005000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
+
+/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
+
+/* Interval between registers */
+#define CONFIG_SYS_ATA_STRIDE 4
+
+#endif /* __CONFIG_H */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE 8
+
/* I2C RTC */
#define CONFIG_RTC_M41T11 1
#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_CHIP_CONFIG
#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for UBI/UBIFS */
-
/* UBI Support for all Keymile boards */
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
*/
#define CONFIG_SYS_IMMR 0xE0000000
+/*
+ * Bus Arbitration Configuration Register (ACR)
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
+#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
+#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
+
/*
* DDR Setup
*/
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE + 0x20000000)
/* Don't change either of these */
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0x70000000)
#undef CONFIG_SMC_USE_32_BIT
-#define CONFIG_SMC_USE_IOFUNCS
#endif /* __LPD7A400_10_H */
#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0x70000000)
#undef CONFIG_SMC_USE_32_BIT
-#define CONFIG_SMC_USE_IOFUNCS
#endif /* __LPD7A404_10_H */
#include <config_cmd_default.h>
#ifndef USE_920T_MMU
- #define CONFIG_CMD_PING)
+ #define CONFIG_CMD_PING
#undef CONFIG_CMD_CACHE
#else
#define CONFIG_CMD_DATE
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_NET_MULTI
+#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE 0x0C000000
/*
/* Video console */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_CONSOLE_EXTRA_INFO
#define VIDEO_FB_16BPP_PIXEL_SWAP
+#define VIDEO_FB_16BPP_WORD_SWAP
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
/*-----------------------------------------------------------------------
* Graphics (Fujitsu Lime)
*----------------------------------------------------------------------*/
-/* SDRAM Clock frequency adjustment register */
-#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
/* Lime Clock frequency is to set 100MHz */
#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
#if 0
#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
#endif
-/* SDRAM Parameter register */
-#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
and pixel flare on display when 133MHz was configured. According to
SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
-#define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F3
+#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
+#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
#else
-#define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F2
+#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
+#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
#endif
/*-----------------------------------------------------------------------
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_COMMAND_HISTORY 1
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Enable an alternate, more extensive memory test */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*
* Configuration parameters for MPC5121 NAND driver
*/
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
/* stack */
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MALLOC_BASE
/*#define RAMENV */
#define FLASH
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS \
- "root=/dev/mtdblock1 rootfstype=jffs2 console=ttyS1"
+ "root=/dev/mtdblock1 rootfstype=jffs2 fbmem=512k console=ttyS1"
#define CONFIG_BOOTCOMMAND \
"fsload boot/uImage; bootm"
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*
* Configuration parameters for MPC5121 NAND driver
*/
#define CONFIG_SYS_NAND_BASE 0x04000000 + (2 << 23)
#define NAND_ALLOW_ERASE_ALL 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_MEMTEST_END 0x0FFFFFFF
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
-#define CONFIG_SYS_64BIT_VSPRINTF /* mtd desires this */
#define BOARD_LATE_INIT /* call board_late_init during start up */
#define CONFIG_SMC9196_BASE 0x08000300
#define CONFIG_SMC9196_EXT_PHY
*/
-#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_NET_MULTI
+#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE 0x08000300
#define CONFIG_LAN91C96_EXT_PHY
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_NET_MULTI
+#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE 0x04000300
#define CONFIG_LAN91C96_EXT_PHY
*/
/*
*/
-#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_NET_MULTI
+#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE 0x04000300
#define CONFIG_LAN91C96_EXT_PHY
/*
* SMC91c96 Etherent
*/
-#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_NET_MULTI
+#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300)
#define CONFIG_LAN91C96_EXT_PHY
/*
* Miscellaneous configurable options
*/
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_APTIX
-#define V_PROMPT "OMAP2420 Aptix # "
+# define CONFIG_SYS_PROMPT "OMAP2420 Aptix # "
#else
-#define V_PROMPT "OMAP242x H4 # "
+# define CONFIG_SYS_PROMPT "OMAP242x H4 # "
#endif
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT V_PROMPT
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID 0x0451
+#define CONFIG_USBD_PRODUCTID 0x5678
+#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME "Beagle"
+
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
"console=ttyS2,115200n8\0" \
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
/*
* Miscellaneous configurable options
*/
-#define V_PROMPT "OMAP3 beagleboard.org # "
-
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT V_PROMPT
+#define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_MUSB_HCD 1
+/* #define CONFIG_MUSB_UDC 1 */
+
+#ifdef CONFIG_USB_OMAP3
+
+#ifdef CONFIG_MUSB_HCD
+#define CONFIG_CMD_USB
+
+#define CONFIG_USB_STORAGE
+#define CONGIG_CMD_STORAGE
+#define CONFIG_CMD_FAT
+
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_PREBOOT "usb start"
+#endif /* CONFIG_USB_KEYBOARD */
+
+#endif /* CONFIG_MUSB_HCD */
+
+#ifdef CONFIG_MUSB_UDC
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID 0x0451
+#define CONFIG_USBD_PRODUCTID 0x5678
+#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME "EVM"
+#endif /* CONFIG_MUSB_UDC */
+
+#endif /* CONFIG_USB_OMAP3 */
+
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
"console=ttyS2,115200n8\0" \
"mmcargs=setenv bootargs console=${console} " \
"root=/dev/mmcblk0p2 rw " \
/*
* Miscellaneous configurable options
*/
-#define V_PROMPT "OMAP3_EVM # "
-
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT V_PROMPT
+#define CONFIG_SYS_PROMPT "OMAP3_EVM # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
/*
* Miscellaneous configurable options
*/
-#define V_PROMPT "Overo # "
-
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT V_PROMPT
+#define CONFIG_SYS_PROMPT "Overo # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
/*
* Miscellaneous configurable options
*/
-#define V_PROMPT "Pandora # "
-
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT V_PROMPT
+#define CONFIG_SYS_PROMPT "Pandora # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
+/* DDR - I use Infineon DDR */
+#define CONFIG_OMAP3_INFINEON_DDR 1
+
/* OMITTED: single 1 Gbit MT29F1G NAND flash */
/*
*/
#if defined(CONFIG_CMD_NET)
-#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_NET_MULTI
+#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE DEBUG_BASE
#define CONFIG_LAN91C96_EXT_PHY
/*
* Miscellaneous configurable options
*/
-#define V_PROMPT "OMAP34XX SDP # "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT V_PROMPT
+#define CONFIG_SYS_PROMPT "OMAP34XX SDP # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID 0x0451
+#define CONFIG_USBD_PRODUCTID 0x5678
+#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME "Zoom1"
+
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
"console=ttyS2,115200n8\0" \
"videomode=1024x768@60,vxres=1024,vyres=768\0" \
"videospec=omapfb:vram:2M,vram:4M\0" \
/*
* Miscellaneous configurable options
*/
-#define V_PROMPT "OMAP3 Zoom1# "
-
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT V_PROMPT
+#define CONFIG_SYS_PROMPT "OMAP3 Zoom1 # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* Status LED */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED 1
#define CONFIG_OMAP3_GPIO_3 /* board revision */
#define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID 0x0451
+#define CONFIG_USBD_PRODUCTID 0x5678
+#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME "Zoom2"
+
/* commands to include */
#include <config_cmd_default.h>
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/* Environment information */
#define CONFIG_BOOTDELAY 10
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "usbtty=cdc_acm\0" \
+
/*
* Miscellaneous configurable options
*/
*/
/*
*/
-#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_NET_MULTI
+#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE 0x04800300
#define CONFIG_LAN91C96_EXT_PHY
* Hardware drivers
*/
-#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_NET_MULTI
+#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE 0x04000300
#define CONFIG_LAN91C96_EXT_PHY
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
#define NAND_ALLOW_ERASE_ALL 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/*
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/*
*/
/* None - PLEB 2 doesn't have any of this.
- #define CONFIG_DRIVER_LAN91C96
- #define CONFIG_LAN91C96_BASE 0x0C000000 */
+ #define CONFIG_NET_MULTI
+ #define CONFIG_LAN91C96
+ #define CONFIG_LAN91C96_BASE 0x0C000000
+ */
/*
* select serial console configuration
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA16
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
-
/* NOR flash */
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
#define CONFIG_CMD_JFFS2 1
#define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/*-----------------------------------------------------------------------
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
#define NAND_ALLOW_ERASE_ALL 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/*
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_OFFSET_REDUND 0x80000
#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
* CONFIG_SYS_FLASH_BASE -> start address of internal flash
* CONFIG_SYS_MONITOR_BASE -> start of u-boot
*/
-#ifndef __ASSEMBLER__
-extern unsigned long offsetOfBigFlash;
-extern unsigned long offsetOfEnvironment;
-#endif
-
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFFE00000
#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000 /* placed last 256k */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x77D00000
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
/* No command line, one static partition */
/*
* Size of malloc() pool
*/
-#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
#define CONFIG_BAUDRATE 9600
/*
* Size of malloc() pool
*/
-#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
#define CONFIG_BAUDRATE 9600
/* USB */
#ifdef CONFIG_440EPX
+
+#undef CONFIG_USB_EHCI /* OHCI by default */
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_PPC4XX
+#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#ifdef CONFIG_4xx_DCACHE
+#define CONFIG_EHCI_DCACHE
+#endif
+#else /* CONFIG_USB_EHCI */
#define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_STORAGE
#define CONFIG_SYS_OHCI_BE_CONTROLLER
#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#endif
+#define CONFIG_USB_STORAGE
/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE
/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
#define NAND_ALLOW_ERASE_ALL 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/*
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63}
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/* Boot configuration (define only one of next 3) */
#define CONFIG_BOOT_NAND
/* None of these are currently implemented. Left from the original Samsung
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */
#define CONFIG_IDENT_STRING " for SMDKC100"
-#define CONFIG_SYS_64BIT_VSPRINTF
-
#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
#define CONFIG_ENABLE_MMU
#endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_CMD_NAND
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/* LIME GDC */
#define CONFIG_SYS_LIME_BASE 0xc8000000
#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_CONSOLE_EXTRA_INFO
#define VIDEO_FB_16BPP_PIXEL_SWAP
+#define VIDEO_FB_16BPP_WORD_SWAP
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
+/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
+#define CONFIG_SYS_MB862xx_CCF 0x10000
+/* SDRAM parameter */
+#define CONFIG_SYS_MB862xx_MMR 0x4157BA63
+
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_OFFSET_REDUND 0x80000
#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"
#define CONFIG_BOOTCOMMAND "run test3"
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-/*
- * Needed for 64bit printf format
- */
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* UBI configuration
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+/*
+ * Top level Makefile configuration choices
+ */
+#ifdef CONFIG_MK_caddy2
+#define VME_CADDY2
+#endif
+
/*
* High Level Configuration Options
*/
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
+#define CONFIG_MISC_INIT_R
+
#define CONFIG_PCI
/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
*/
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
-#undef CONFIG_SPD_EEPROM /* dont use SPD EEPROM for DDR setup*/
+#define CONFIG_SPD_EEPROM
+#define SPD_EEPROM_ADDRESS 0x54
+#define CONFIG_SYS_READ_SPD vme8349_read_spd
#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
/*
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_DDR_2T_TIMING
-
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE 512 /* MB */
-
-#if (CONFIG_SYS_DDR_SIZE == 512)
-#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
- CSCONFIG_COL_BIT_10 | \
- CSCONFIG_BANK_BIT_3)
-#endif
-
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_TIMING_0 0x00220802
-#define CONFIG_SYS_DDR_TIMING_1 0x39377322
-#define CONFIG_SYS_DDR_TIMING_2 0x2f9848ca /* P9-45, tuning? */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuf,no DYN_PWR */
-#define CONFIG_SYS_DDR_MODE 0x07940242
-#define CONFIG_SYS_DDR_MODE2 0x00000000
-/* autocharge,no open page */
-#define CONFIG_SYS_DDR_INTERVAL 0x04060100
-#define CONFIG_SYS_DDR_SDRAM_CFG 0x63000000
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x04061000
+#define CONFIG_SYS_DDRCDR 0x80080001
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
-/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+#ifdef VME_CADDY2
+#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
+ (2 << BR_PS_SHIFT) | /* 32bit */ \
+ BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM 0xffc06ff7 /* 4 MB flash size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000015 /* 4 MB window size */
+#else
+#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
(2 << BR_PS_SHIFT) | /* 32bit */ \
BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM 0xF8006FF7 /* 128 MB flash size */
+#define CONFIG_SYS_OR0_PRELIM 0xf8006ff7 /* 128 MB flash size */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001A /* 128 MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001a /* 128 MB window size */
+#endif
+/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
#define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801)
-#define CONFIG_SYS_OR1_PRELIM (0xffff8000 | 0x00000200)
+#define CONFIG_SYS_OR1_PRELIM (0xfffc0008 | 0x00000200)
#define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000
-#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x0000000e)
+#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x00000011)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
-#undef CONFIG_SYS_RAMBOOT
+#undef CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
/*
* Local Bus LCRR and LBCR regs
- * LCRR: DLL bypass, Clock divider is 4
+ * LCRR: no DLL bypass, Clock divider is 4
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
#undef PCI_ONE_PCI1
#endif
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
+#ifndef VME_CADDY2
#define CONFIG_NET_MULTI
+#endif
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#define PCI_IDSEL_NUMBER 0xFIXME
#endif
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+
#endif /* CONFIG_PCI */
/*
* TSEC configuration
*/
+#ifdef VME_CADDY2
+#define CONFIG_E1000
+#else
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
+#endif
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI
#endif
-#define CONFIG_GMII /* MII PHY management */
+#define CONFIG_GMII /* MII PHY management */
#define CONFIG_TSEC1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2
#endif /* CONFIG_TSEC_ENET */
+#if defined(CONFIG_E1000)
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+#endif
+
/*
* Environment
*/
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* boot command will set bootargs */
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BAUDRATE 9600
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
#define CONFIG_BOOTCOMMAND "run flash_self"
+#ifndef __ASSEMBLY__
+int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
+ unsigned char *buffer, int len);
+#endif
+
#endif /* __CONFIG_H */
#define FPGA_REG1A_PE_SELSOURCE_0 0x0002
#define FPGA_REG1A_PE_SELSOURCE_1 0x0001
+#define FPGA_REG1A_GLED_ENCODE(n) (FPGA_REG1A_PE0_GLED >> (n))
+#define FPGA_REG1A_YLED_ENCODE(n) (FPGA_REG1A_PE0_YLED >> (n))
+#define FPGA_REG1A_PWRON_ENCODE(n) (FPGA_REG1A_PE0_PWRON >> (n))
+#define FPGA_REG1A_REFCLK_ENCODE(n) (FPGA_REG1A_PE0_REFCLK_ENABLE >> (n))
+
/*----------------------------------------------------------------------------+
| PCIe Miscellaneous
+----------------------------------------------------------------------------*/
#define FPGA_REG1C_PE1_PERST 0x0008
#define FPGA_REG1C_PE2_PERST 0x0004
+#define FPGA_REG1C_ROOTPOINT_ENCODE(n) (FPGA_REG1C_PE0_ROOTPOINT >> (n))
+#define FPGA_REG1C_PERST_ENCODE(n) (FPGA_REG1C_PE0_PERST >> (n))
+
/*----------------------------------------------------------------------------+
| Defines
+----------------------------------------------------------------------------*/
#define CONFIG_SYS_NAND_SENDCMD_RETRY 3
#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/* NAND Timing Parameters (in ns) */
#define NAND_TIMING_tCH 10
#define NAND_TIMING_tCS 0
void free_hdlr(int);
void *malloc(size_t);
void free(void*);
-void udelay(unsigned long);
+void __udelay(unsigned long);
unsigned long get_timer(unsigned long);
void vprintf(const char *, va_list);
void do_reset (void);
#define IH_COMP_GZIP 1 /* gzip Compression Used */
#define IH_COMP_BZIP2 2 /* bzip2 Compression Used */
#define IH_COMP_LZMA 3 /* lzma Compression Used */
+#define IH_COMP_LZO 4 /* lzo Compression Used */
#define IH_MAGIC 0x27051956 /* Image Magic Number */
#define IH_NMLEN 32 /* Image Name Length */
const char *fit_uname_rd; /* init ramdisk subimage node unit name */
int fit_noffset_rd; /* init ramdisk subimage node offset */
-#if defined(CONFIG_PPC)
void *fit_hdr_fdt; /* FDT blob FIT image header */
const char *fit_uname_fdt; /* FDT blob subimage node unit name */
int fit_noffset_fdt;/* FDT blob subimage node offset */
#endif
-#endif
#ifndef USE_HOSTCC
image_info_t os; /* os image info */
int lzo1x_decompress_safe(const unsigned char *src, size_t src_len,
unsigned char *dst, size_t *dst_len);
+/* decompress lzop format */
+int lzop_decompress(const unsigned char *src, size_t src_len,
+ unsigned char *dst, size_t *dst_len);
+
/*
* Return values (< 0 = Error)
*/
*/
struct nand_ecclayout {
uint32_t eccbytes;
- uint32_t eccpos[64];
+ uint32_t eccpos[128];
uint32_t oobavail;
struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
};
int bbt_erase_shift;
int chip_shift;
int numchips;
- unsigned long chipsize;
+ uint64_t chipsize;
int pagemask;
int pagebuf;
int subpagesize;
#include <linux/mtd/compat.h>
#include <linux/mtd/bbm.h>
+#define MAX_DIES 2
#define MAX_BUFFERRAM 2
-#define MAX_ONENAND_PAGESIZE (2048 + 64)
+#define MAX_ONENAND_PAGESIZE (4096 + 128)
/* Scan and identify a OneNAND device */
extern int onenand_scan (struct mtd_info *mtd, int max_chips);
/**
* struct onenand_chip - OneNAND Private Flash Chip Data
* @param base [BOARDSPECIFIC] address to access OneNAND
+ * @dies: [INTERN][FLEXONENAND] number of dies on chip
+ * @boundary: [INTERN][FLEXONENAND] Boundary of the dies
+ * @diesize: [INTERN][FLEXONENAND] Size of the dies
* @param chipsize [INTERN] the size of one chip for multichip arrays
* @param device_id [INTERN] device ID
* @param verstion_id [INTERN] version ID
+ * @technology [INTERN] describes the internal NAND array technology such as SLC or MLC.
+ * @density_mask: [INTERN] chip density, used for DDP devices
* @param options [BOARDSPECIFIC] various chip options. They can partly be set to inform onenand_scan about
* @param erase_shift [INTERN] number of address bits in a block
* @param page_shift [INTERN] number of address bits in a page
*/
struct onenand_chip {
void __iomem *base;
+ unsigned int dies;
+ unsigned int boundary[MAX_DIES];
+ unsigned int diesize[MAX_DIES];
unsigned int chipsize;
unsigned int device_id;
unsigned int version_id;
+ unsigned int technology;
unsigned int density_mask;
unsigned int options;
#define ONENAND_SET_BUFFERRAM0(this) (this->bufferram_index = 0)
#define ONENAND_SET_BUFFERRAM1(this) (this->bufferram_index = 1)
+#define FLEXONENAND(this) (this->device_id & DEVICE_IS_FLEXONENAND)
+#define ONENAND_IS_MLC(this) (this->technology & ONENAND_TECHNOLOGY_IS_MLC)
#define ONENAND_IS_DDP(this) \
(this->device_id & ONENAND_DEVICE_IS_DDP)
int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from,
struct mtd_oob_ops *ops);
+unsigned int onenand_block(struct onenand_chip *this, loff_t addr);
+int flexonenand_region(struct mtd_info *mtd, loff_t addr);
#endif /* __LINUX_MTD_ONENAND_H */
/*
* Device ID Register F001h (R)
*/
+#define DEVICE_IS_FLEXONENAND (1 << 9)
+#define FLEXONENAND_PI_MASK (0x3ff)
+#define FLEXONENAND_PI_UNLOCK_SHIFT (14)
#define ONENAND_DEVICE_DENSITY_MASK (0xf)
#define ONENAND_DEVICE_DENSITY_SHIFT (4)
#define ONENAND_DEVICE_IS_DDP (1 << 3)
*/
#define ONENAND_VERSION_PROCESS_SHIFT (8)
+/*
+ * Technology Register F006h (R)
+ */
+#define ONENAND_TECHNOLOGY_IS_MLC (1 << 0)
+
/*
* Start Address 1 F100h (R/W)
*/
/*
* Start Address 8 F107h (R/W)
*/
-#define ONENAND_FPA_MASK (0x3f)
+#define ONENAND_FPA_MASK (0x7f)
#define ONENAND_FPA_SHIFT (2)
#define ONENAND_FSA_MASK (0x03)
#define ONENAND_BSA_BOOTRAM (0 << 2)
#define ONENAND_BSA_DATARAM0 (2 << 2)
#define ONENAND_BSA_DATARAM1 (3 << 2)
-#define ONENAND_BSC_MASK (0x03)
+#define ONENAND_BSC_MASK (0x07)
/*
* Command Register F220h (R/W)
#define ONENAND_CMD_ERASE_VERIFY (0x71)
#define ONENAND_CMD_RESET (0xF0)
#define ONENAND_CMD_READID (0x90)
+#define FLEXONENAND_CMD_RESET (0xF3)
+#define FLEXONENAND_CMD_PI_UPDATE (0x05)
+#define FLEXONENAND_CMD_PI_ACCESS (0x66)
+#define FLEXONENAND_CMD_RECOVER_LSB (0x05)
/* NOTE: Those are not *REAL* commands */
#define ONENAND_CMD_BUFFERRAM (0x1978)
+#define FLEXONENAND_CMD_READ_PI (0x1985)
/*
* System Configuration 1 Register F221h (R, R/W)
#define ONENAND_ECC_2BIT (1 << 1)
#define ONENAND_ECC_2BIT_ALL (0xAAAA)
#define ONENAND_ECC_4BIT_UNCORRECTABLE (0x1010)
+#define FLEXONENAND_UNCORRECTABLE_ERROR (0x1010)
#endif /* __ONENAND_REG_H */
struct mtd_partition {
char *name; /* identifier string */
- u_int32_t size; /* partition size */
- u_int32_t offset; /* offset within the master MTD space */
+ uint64_t size; /* partition size */
+ uint64_t offset; /* offset within the master MTD space */
u_int32_t mask_flags; /* master MTD flags to mask out for this partition */
struct nand_ecclayout *ecclayout; /* out of band layout for this partition (NAND only)*/
struct mtd_info **mtdp; /* pointer to store the MTD object */
--- /dev/null
+#ifndef _LINUX_UNALIGNED_BE_BYTESHIFT_H
+#define _LINUX_UNALIGNED_BE_BYTESHIFT_H
+
+#include <linux/types.h>
+
+static inline u16 __get_unaligned_be16(const u8 *p)
+{
+ return p[0] << 8 | p[1];
+}
+
+static inline u32 __get_unaligned_be32(const u8 *p)
+{
+ return p[0] << 24 | p[1] << 16 | p[2] << 8 | p[3];
+}
+
+static inline u64 __get_unaligned_be64(const u8 *p)
+{
+ return (u64)__get_unaligned_be32(p) << 32 |
+ __get_unaligned_be32(p + 4);
+}
+
+static inline void __put_unaligned_be16(u16 val, u8 *p)
+{
+ *p++ = val >> 8;
+ *p++ = val;
+}
+
+static inline void __put_unaligned_be32(u32 val, u8 *p)
+{
+ __put_unaligned_be16(val >> 16, p);
+ __put_unaligned_be16(val, p + 2);
+}
+
+static inline void __put_unaligned_be64(u64 val, u8 *p)
+{
+ __put_unaligned_be32(val >> 32, p);
+ __put_unaligned_be32(val, p + 4);
+}
+
+static inline u16 get_unaligned_be16(const void *p)
+{
+ return __get_unaligned_be16((const u8 *)p);
+}
+
+static inline u32 get_unaligned_be32(const void *p)
+{
+ return __get_unaligned_be32((const u8 *)p);
+}
+
+static inline u64 get_unaligned_be64(const void *p)
+{
+ return __get_unaligned_be64((const u8 *)p);
+}
+
+static inline void put_unaligned_be16(u16 val, void *p)
+{
+ __put_unaligned_be16(val, p);
+}
+
+static inline void put_unaligned_be32(u32 val, void *p)
+{
+ __put_unaligned_be32(val, p);
+}
+
+static inline void put_unaligned_be64(u64 val, void *p)
+{
+ __put_unaligned_be64(val, p);
+}
+
+#endif /* _LINUX_UNALIGNED_BE_BYTESHIFT_H */
--- /dev/null
+#ifndef _LINUX_UNALIGNED_LE_BYTESHIFT_H
+#define _LINUX_UNALIGNED_LE_BYTESHIFT_H
+
+#include <linux/types.h>
+
+static inline u16 __get_unaligned_le16(const u8 *p)
+{
+ return p[0] | p[1] << 8;
+}
+
+static inline u32 __get_unaligned_le32(const u8 *p)
+{
+ return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24;
+}
+
+static inline u64 __get_unaligned_le64(const u8 *p)
+{
+ return (u64)__get_unaligned_le32(p + 4) << 32 |
+ __get_unaligned_le32(p);
+}
+
+static inline void __put_unaligned_le16(u16 val, u8 *p)
+{
+ *p++ = val;
+ *p++ = val >> 8;
+}
+
+static inline void __put_unaligned_le32(u32 val, u8 *p)
+{
+ __put_unaligned_le16(val >> 16, p + 2);
+ __put_unaligned_le16(val, p);
+}
+
+static inline void __put_unaligned_le64(u64 val, u8 *p)
+{
+ __put_unaligned_le32(val >> 32, p + 4);
+ __put_unaligned_le32(val, p);
+}
+
+static inline u16 get_unaligned_le16(const void *p)
+{
+ return __get_unaligned_le16((const u8 *)p);
+}
+
+static inline u32 get_unaligned_le32(const void *p)
+{
+ return __get_unaligned_le32((const u8 *)p);
+}
+
+static inline u64 get_unaligned_le64(const void *p)
+{
+ return __get_unaligned_le64((const u8 *)p);
+}
+
+static inline void put_unaligned_le16(u16 val, void *p)
+{
+ __put_unaligned_le16(val, p);
+}
+
+static inline void put_unaligned_le32(u32 val, void *p)
+{
+ __put_unaligned_le32(val, p);
+}
+
+static inline void put_unaligned_le64(u64 val, void *p)
+{
+ __put_unaligned_le64(val, p);
+}
+
+#endif /* _LINUX_UNALIGNED_LE_BYTESHIFT_H */
#define PCI_DEVICE_ID_CORAL_P 0x2019
#define PCI_DEVICE_ID_CORAL_PA 0x201E
+#define MB862XX_TYPE_LIME 0x1
+
#define GC_HOST_BASE 0x01fc0000
#define GC_DISP_BASE 0x01fd0000
#define GC_DRAW_BASE 0x01ff0000
/* Host interface registers */
#define GC_SRST 0x0000002c
#define GC_CCF 0x00000038
+#define GC_CID 0x000000f0
#define GC_MMR 0x0000fffc
/*
#define GC_FC 0x00000480
#define GC_BC 0x00000484
#define GC_FIFO 0x000004a0
+#define GC_REV 0x00008084
#define GC_GEO_FIFO 0x00008400
typedef struct {
unsigned int value;
} gdc_regs;
+int mb862xx_probe(unsigned int addr);
const gdc_regs *board_get_regs (void);
unsigned int board_video_init (void);
void board_backlight_switch(int);
void gt6426x_eth_initialize(bd_t *bis);
int inca_switch_initialize(bd_t *bis);
int kirkwood_egiga_initialize(bd_t *bis);
+int lan91c96_initialize(u8 dev_num, int base_addr);
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
int mcdmafec_initialize(bd_t *bis);
int mcffec_initialize(bd_t *bis);
struct onenand_chip;
extern struct mtd_info onenand_mtd;
+extern struct onenand_chip onenand_chip;
/* board */
extern void onenand_board_init(struct mtd_info *);
extern char *onenand_print_device_info(int device, int version);
+extern unsigned onenand_block(struct onenand_chip *this, loff_t addr);
+
+extern loff_t onenand_addr(struct onenand_chip *this, int block);
+
+extern int flexonenand_region(struct mtd_info *mtd, loff_t addr);
+
+extern int flexonenand_set_boundary(struct mtd_info *mtd, int die,
+ int boundary, int lock);
+
/* S3C64xx */
extern void s3c64xx_onenand_init(struct mtd_info *);
extern void s3c64xx_set_width_regs(struct onenand_chip *);
--- /dev/null
+/*
+ * File: include/pca9564.h
+ * Author:
+ *
+ * Created: 2009-06-23
+ * Description: PCA9564 i2c bridge driver
+ *
+ * Modified:
+ * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
+ *
+ * Bugs:
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _PCA9564_H
+#define _PCA9564_H
+
+/* Clock speeds for the bus */
+#define PCA_CON_330kHz 0x00
+#define PCA_CON_288kHz 0x01
+#define PCA_CON_217kHz 0x02
+#define PCA_CON_146kHz 0x03
+#define PCA_CON_88kHz 0x04
+#define PCA_CON_59kHz 0x05
+#define PCA_CON_44kHz 0x06
+#define PCA_CON_36kHz 0x07
+
+#define PCA_CON_AA 0x80 /* Assert Acknowledge */
+#define PCA_CON_ENSIO 0x40 /* Enable */
+#define PCA_CON_STA 0x20 /* Start */
+#define PCA_CON_STO 0x10 /* Stop */
+#define PCA_CON_SI 0x08 /* Serial Interrupt */
+#define PCA_CON_CR 0x07 /* Clock Rate (MASK) */
+
+#endif
+
#define PCI_DEVICE_ID_INTEL_82546EB_COPPER 0x1010
#define PCI_DEVICE_ID_INTEL_82545EM_FIBER 0x1011
#define PCI_DEVICE_ID_INTEL_82546EB_FIBER 0x1012
+#define PCI_DEVICE_ID_INTEL_82546GB_COPPER 0x1079
#define PCI_DEVICE_ID_INTEL_82540EM_LOM 0x1015
#define PCI_DEVICE_ID_INTEL_82545GM_COPPER 0x1026
#define PCI_DEVICE_ID_INTEL_82559 0x1030
#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */
#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */
-/*-----------------------------------------------------------------------------
-| IIC Register Offsets
-'----------------------------------------------------------------------------*/
-#define IICMDBUF 0x00
-#define IICSDBUF 0x02
-#define IICLMADR 0x04
-#define IICHMADR 0x05
-#define IICCNTL 0x06
-#define IICMDCNTL 0x07
-#define IICSTS 0x08
-#define IICEXTSTS 0x09
-#define IICLSADR 0x0A
-#define IICHSADR 0x0B
-#define IIC0_CLKDIV 0x0C
-#define IICINTRMSK 0x0D
-#define IICXFRCNT 0x0E
-#define IICXTCNTLSS 0x0F
-#define IICDIRECTCNTL 0x10
-
/*-----------------------------------------------------------------------------
| UART Register Offsets
'----------------------------------------------------------------------------*/
#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
#endif /* defined(CONFIG_440GP) */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
#define CPR0_PERD_PERDV0_MASK 0x07000000
#endif
-/*-----------------------------------------------------------------------------
-| IIC Register Offsets
-'----------------------------------------------------------------------------*/
-#define IICMDBUF 0x00
-#define IICSDBUF 0x02
-#define IICLMADR 0x04
-#define IICHMADR 0x05
-#define IICCNTL 0x06
-#define IICMDCNTL 0x07
-#define IICSTS 0x08
-#define IICEXTSTS 0x09
-#define IICLSADR 0x0A
-#define IICHSADR 0x0B
-#define IIC0_CLKDIV 0x0C
-#define IICINTRMSK 0x0D
-#define IICXFRCNT 0x0E
-#define IICXTCNTLSS 0x0F
-#define IICDIRECTCNTL 0x10
-
/*-----------------------------------------------------------------------------
| PCI Internal Registers et. al. (accessed via plb)
+----------------------------------------------------------------------------*/
#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
#if defined(CONFIG_440)
-/*
- * Enable long long (%ll ...) printf format on 440 PPC's since most of
- * them support 36bit physical addressing
- */
-#define CONFIG_SYS_64BIT_VSPRINTF
-#define CONFIG_SYS_64BIT_STRTOUL
#include <ppc440.h>
#else
#include <ppc405.h>
extern int serial_assign(char * name);
extern void serial_reinit_all(void);
+/* For usbtty */
+#ifdef CONFIG_USB_TTY
+
+extern int usbtty_getc(void);
+extern void usbtty_putc(const char c);
+extern void usbtty_puts(const char *str);
+extern int usbtty_tstc(void);
+
+#else
+
+/* stubs */
+#define usbtty_getc() 0
+#define usbtty_putc(a)
+#define usbtty_puts(a)
+#define usbtty_tstc() 0
+
+#endif /* CONFIG_USB_TTY */
+
#endif
--- /dev/null
+/*
+ * Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu>
+ *
+ * SJA1000 register layout for basic CAN mode
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SJA1000_H_
+#define _SJA1000_H_
+
+/*
+ * SJA1000 register layout in basic can mode
+ */
+struct sja1000_basic_s {
+ u8 cr;
+ u8 cmr;
+ u8 sr;
+ u8 ir;
+ u8 ac;
+ u8 am;
+ u8 btr0;
+ u8 btr1;
+ u8 oc;
+ u8 txb[10];
+ u8 rxb[10];
+ u8 unused;
+ u8 cdr;
+};
+
+/* control register */
+#define CR_RR 0x01
+
+/* output control register */
+#define OC_MODE0 0x01
+#define OC_MODE1 0x02
+#define OC_POL0 0x04
+#define OC_TN0 0x08
+#define OC_TP0 0x10
+#define OC_POL1 0x20
+#define OC_TN1 0x40
+#define OC_TP1 0x80
+
+#endif
#define _SPI_FLASH_H_
#include <spi.h>
+#include <linux/types.h>
struct spi_flash_region {
unsigned int count;
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
- * Copyright 2004, 2007 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007, 2009 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* maintained by Xianghua Xiao (x.xiao@motorola.com)
* author Andy Fleming
#include <net.h>
#include <config.h>
-#ifndef CONFIG_SYS_TSEC1_OFFSET
- #define CONFIG_SYS_TSEC1_OFFSET (0x24000)
-#endif
-
-#define TSEC_SIZE 0x01000
-
-/* FIXME: Should these be pushed back to 83xx and 85xx config files? */
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \
- || defined(CONFIG_MPC83xx)
- #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#endif
+#define TSEC_SIZE 0x01000
+#define TSEC_MDIO_OFFSET 0x01000
#define STD_TSEC_INFO(num) \
{ \
.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
- .miiregs = (tsec_t *)TSEC_BASE_ADDR, \
+ .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \
+ .miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
+ + (num - 1) * TSEC_MDIO_OFFSET), \
.devname = CONFIG_TSEC##num##_NAME, \
.phyaddr = TSEC##num##_PHY_ADDR, \
.flags = TSEC##num##_FLAGS \
#define SET_STD_TSEC_INFO(x, num) \
{ \
x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
- x.miiregs = (tsec_t *)TSEC_BASE_ADDR; \
+ x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \
+ x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
+ + (num - 1) * TSEC_MDIO_OFFSET); \
x.devname = CONFIG_TSEC##num##_NAME; \
x.phyaddr = TSEC##num##_PHY_ADDR; \
x.flags = TSEC##num##_FLAGS;\
uint res2[24];
} tsec_hash_t;
+typedef struct tsec_mdio {
+ uint res1[4];
+ uint ieventm;
+ uint imaskm;
+ uint res2;
+ uint emapm;
+ uint res3[320];
+ uint miimcfg; /* MII Management: Configuration */
+ uint miimcom; /* MII Management: Command */
+ uint miimadd; /* MII Management: Address */
+ uint miimcon; /* MII Management: Control */
+ uint miimstat; /* MII Management: Status */
+ uint miimind; /* MII Management: Indicators */
+ uint res4[690];
+} tsec_mdio_t;
+
typedef struct tsec
{
/* General Control and Status Registers (0x2_n000) */
uint res51c;
- uint miimcfg; /* MII Management: Configuration */
- uint miimcom; /* MII Management: Command */
- uint miimadd; /* MII Management: Address */
- uint miimcon; /* MII Management: Control */
- uint miimstat; /* MII Management: Status */
- uint miimind; /* MII Management: Indicators */
+ uint resmdio[6];
uint res538;
struct tsec_private {
volatile tsec_t *regs;
- volatile tsec_t *phyregs;
+ volatile tsec_mdio_t *phyregs;
+ volatile tsec_mdio_t *phyregs_sgmii;
struct phy_info *phyinfo;
uint phyaddr;
u32 flags;
struct tsec_info_struct {
tsec_t *regs;
- tsec_t *miiregs;
+ tsec_mdio_t *miiregs;
+ tsec_mdio_t *miiregs_sgmii;
char *devname;
unsigned int phyaddr;
u32 flags;
/* LED */
#define TWL4030_LED_LEDEN 0xEE
+#define TWL4030_LED_LEDEN_LEDAON (1 << 0)
+#define TWL4030_LED_LEDEN_LEDBON (1 << 1)
+#define TWL4030_LED_LEDEN_LEDAPWM (1 << 4)
+#define TWL4030_LED_LEDEN_LEDBPWM (1 << 5)
/* Keypad */
#define TWL4030_KEYPAD_KEYP_CTRL_REG 0xD2
#define TWL4030_KEYPAD_CTRL_SOFT_NRST (1 << 0)
/* USB */
-#define TWL4030_USB_FUNC_CTRL (0x04)
-#define TWL4030_USB_OPMODE_MASK (3 << 3)
-#define TWL4030_USB_XCVRSELECT_MASK (3 << 0)
-#define TWL4030_USB_IFC_CTRL (0x07)
-#define TWL4030_USB_CARKITMODE (1 << 2)
-#define TWL4030_USB_POWER_CTRL (0xAC)
-#define TWL4030_USB_OTG_ENAB (1 << 5)
-#define TWL4030_USB_PHY_PWR_CTRL (0xFD)
-#define TWL4030_USB_PHYPWD (1 << 0)
-#define TWL4030_USB_PHY_CLK_CTRL (0xFE)
-#define TWL4030_USB_CLOCKGATING_EN (1 << 2)
-#define TWL4030_USB_CLK32K_EN (1 << 1)
-#define TWL4030_USB_REQ_PHY_DPLL_CLK (1 << 0)
-#define TWL4030_USB_PHY_CLK_CTRL_STS (0xFF)
-#define TWL4030_USB_PHY_DPLL_CLK (1 << 0)
+#define TWL4030_USB_VENDOR_ID_LO 0x00
+#define TWL4030_USB_VENDOR_ID_HI 0x01
+#define TWL4030_USB_PRODUCT_ID_LO 0x02
+#define TWL4030_USB_PRODUCT_ID_HI 0x03
+#define TWL4030_USB_FUNC_CTRL 0x04
+#define TWL4030_USB_FUNC_CTRL_SET 0x05
+#define TWL4030_USB_FUNC_CTRL_CLR 0x06
+#define TWL4030_USB_IFC_CTRL 0x07
+#define TWL4030_USB_IFC_CTRL_SET 0x08
+#define TWL4030_USB_IFC_CTRL_CLR 0x09
+#define TWL4030_USB_OTG_CTRL 0x0A
+#define TWL4030_USB_OTG_CTRL_SET 0x0B
+#define TWL4030_USB_OTG_CTRL_CLR 0x0C
+#define TWL4030_USB_USB_INT_EN_RISE 0x0D
+#define TWL4030_USB_USB_INT_EN_RISE_SET 0x0E
+#define TWL4030_USB_USB_INT_EN_RISE_CLR 0x0F
+#define TWL4030_USB_USB_INT_EN_FALL 0x10
+#define TWL4030_USB_USB_INT_EN_FALL_SET 0x11
+#define TWL4030_USB_USB_INT_EN_FALL_CLR 0x12
+#define TWL4030_USB_USB_INT_STS 0x13
+#define TWL4030_USB_USB_INT_LATCH 0x14
+#define TWL4030_USB_DEBUG 0x15
+#define TWL4030_USB_SCRATCH_REG 0x16
+#define TWL4030_USB_SCRATCH_REG_SET 0x17
+#define TWL4030_USB_SCRATCH_REG_CLR 0x18
+#define TWL4030_USB_CARKIT_CTRL 0x19
+#define TWL4030_USB_CARKIT_CTRL_SET 0x1A
+#define TWL4030_USB_CARKIT_CTRL_CLR 0x1B
+#define TWL4030_USB_CARKIT_INT_DELAY 0x1C
+#define TWL4030_USB_CARKIT_INT_EN 0x1D
+#define TWL4030_USB_CARKIT_INT_EN_SET 0x1E
+#define TWL4030_USB_CARKIT_INT_EN_CLR 0x1F
+#define TWL4030_USB_CARKIT_INT_STS 0x20
+#define TWL4030_USB_CARKIT_INT_LATCH 0x21
+#define TWL4030_USB_CARKIT_PLS_CTRL 0x22
+#define TWL4030_USB_CARKIT_PLS_CTRL_SET 0x23
+#define TWL4030_USB_CARKIT_PLS_CTRL_CLR 0x24
+#define TWL4030_USB_TRANS_POS_WIDTH 0x25
+#define TWL4030_USB_TRANS_NEG_WIDTH 0x26
+#define TWL4030_USB_RCV_PLTY_RECOVERY 0x27
+#define TWL4030_USB_MCPC_CTRL 0x30
+#define TWL4030_USB_MCPC_CTRL_SET 0x31
+#define TWL4030_USB_MCPC_CTRL_CLR 0x32
+#define TWL4030_USB_MCPC_IO_CTRL 0x33
+#define TWL4030_USB_MCPC_IO_CTRL_SET 0x34
+#define TWL4030_USB_MCPC_IO_CTRL_CLR 0x35
+#define TWL4030_USB_MCPC_CTRL2 0x36
+#define TWL4030_USB_MCPC_CTRL2_SET 0x37
+#define TWL4030_USB_MCPC_CTRL2_CLR 0x38
+#define TWL4030_USB_OTHER_FUNC_CTRL 0x80
+#define TWL4030_USB_OTHER_FUNC_CTRL_SET 0x81
+#define TWL4030_USB_OTHER_FUNC_CTRL_CLR 0x82
+#define TWL4030_USB_OTHER_IFC_CTRL 0x83
+#define TWL4030_USB_OTHER_IFC_CTRL_SET 0x84
+#define TWL4030_USB_OTHER_IFC_CTRL_CLR 0x85
+#define TWL4030_USB_OTHER_INT_EN_RISE_SET 0x87
+#define TWL4030_USB_OTHER_INT_EN_RISE_CLR 0x88
+#define TWL4030_USB_OTHER_INT_EN_FALL 0x89
+#define TWL4030_USB_OTHER_INT_EN_FALL_SET 0x8A
+#define TWL4030_USB_OTHER_INT_EN_FALL_CLR 0x8B
+#define TWL4030_USB_OTHER_INT_STS 0x8C
+#define TWL4030_USB_OTHER_INT_LATCH 0x8D
+#define TWL4030_USB_ID_STATUS 0x96
+#define TWL4030_USB_CARKIT_SM_1_INT_EN 0x97
+#define TWL4030_USB_CARKIT_SM_1_INT_EN_SET 0x98
+#define TWL4030_USB_CARKIT_SM_1_INT_EN_CLR 0x99
+#define TWL4030_USB_CARKIT_SM_1_INT_STS 0x9A
+#define TWL4030_USB_CARKIT_SM_1_INT_LATCH 0x9B
+#define TWL4030_USB_CARKIT_SM_2_INT_EN 0x9C
+#define TWL4030_USB_CARKIT_SM_2_INT_EN_SET 0x9D
+#define TWL4030_USB_CARKIT_SM_2_INT_EN_CLR 0x9E
+#define TWL4030_USB_CARKIT_SM_2_INT_STS 0x9F
+#define TWL4030_USB_CARKIT_SM_2_INT_LATCH 0xA0
+#define TWL4030_USB_CARKIT_SM_CTRL 0xA1
+#define TWL4030_USB_CARKIT_SM_CTRL_SET 0xA2
+#define TWL4030_USB_CARKIT_SM_CTRL_CLR 0xA3
+#define TWL4030_USB_CARKIT_SM_CMD 0xA4
+#define TWL4030_USB_CARKIT_SM_CMD_SET 0xA5
+#define TWL4030_USB_CARKIT_SM_CMD_CLR 0xA6
+#define TWL4030_USB_CARKIT_SM_CMD_STS 0xA7
+#define TWL4030_USB_CARKIT_SM_STATUS 0xA8
+#define TWL4030_USB_CARKIT_SM_ERR_STATUS 0xAA
+#define TWL4030_USB_CARKIT_SM_CTRL_STATE 0xAB
+#define TWL4030_USB_POWER_CTRL 0xAC
+#define TWL4030_USB_POWER_CTRL_SET 0xAD
+#define TWL4030_USB_POWER_CTRL_CLR 0xAE
+#define TWL4030_USB_OTHER_IFC_CTRL2 0xAF
+#define TWL4030_USB_OTHER_IFC_CTRL2_SET 0xB0
+#define TWL4030_USB_OTHER_IFC_CTRL2_CLR 0xB1
+#define TWL4030_USB_REG_CTRL_EN 0xB2
+#define TWL4030_USB_REG_CTRL_EN_SET 0xB3
+#define TWL4030_USB_REG_CTRL_EN_CLR 0xB4
+#define TWL4030_USB_REG_CTRL_ERROR 0xB5
+#define TWL4030_USB_OTHER_FUNC_CTRL2 0xB8
+#define TWL4030_USB_OTHER_FUNC_CTRL2_SET 0xB9
+#define TWL4030_USB_OTHER_FUNC_CTRL2_CLR 0xBA
+#define TWL4030_USB_CARKIT_ANA_CTRL 0xBB
+#define TWL4030_USB_CARKIT_ANA_CTRL_SET 0xBC
+#define TWL4030_USB_CARKIT_ANA_CTRL_CLR 0xBD
+#define TWL4030_USB_VBUS_DEBOUNCE 0xC0
+#define TWL4030_USB_ID_DEBOUNCE 0xC1
+#define TWL4030_USB_TPH_DP_CON_MIN 0xC2
+#define TWL4030_USB_TPH_DP_CON_MAX 0xC3
+#define TWL4030_USB_TCR_DP_CON_MIN 0xC4
+#define TWL4030_USB_TCR_DP_CON_MAX 0xC5
+#define TWL4030_USB_TPH_DP_PD_SHORT 0xC6
+#define TWL4030_USB_TPH_CMD_DLY 0xC7
+#define TWL4030_USB_TPH_DET_RST 0xC8
+#define TWL4030_USB_TPH_AUD_BIAS 0xC9
+#define TWL4030_USB_TCR_UART_DET_MIN 0xCA
+#define TWL4030_USB_TCR_UART_DET_MAX 0xCB
+#define TWL4030_USB_TPH_ID_INT_PW 0xCD
+#define TWL4030_USB_TACC_ID_INT_WAIT 0xCE
+#define TWL4030_USB_TACC_ID_INT_PW 0xCF
+#define TWL4030_USB_TPH_CMD_WAIT 0xD0
+#define TWL4030_USB_TPH_ACK_WAIT 0xD1
+#define TWL4030_USB_TPH_DP_DISC_DET 0xD2
+#define TWL4030_USB_VBAT_TIMER 0xD3
+#define TWL4030_USB_CARKIT_4W_DEBUG 0xE0
+#define TWL4030_USB_CARKIT_5W_DEBUG 0xE1
+#define TWL4030_USB_PHY_PWR_CTRL 0xFD
+#define TWL4030_USB_PHY_CLK_CTRL 0xFE
+#define TWL4030_USB_PHY_CLK_CTRL_STS 0xFF
/*
* Convience functions to read and write from TWL4030
/*
* LED
*/
-void twl4030_led_init(void);
+void twl4030_led_init(unsigned char ledon_mask);
+
+/*
+ * USB
+ */
+int twl4030_usb_ulpi_init(void);
#endif /* TWL4030_H */
#define _USB_H_
#include <usb_defs.h>
+#include <usbdescriptors.h>
/* Everything is aribtrary */
#define USB_ALTSETTINGALLOC 4
#define USB_CNTL_TIMEOUT 100 /* 100ms timeout */
-/* String descriptor */
-struct usb_string_descriptor {
- unsigned char bLength;
- unsigned char bDescriptorType;
- unsigned short wData[1];
-} __attribute__ ((packed));
-
/* device request (setup) */
struct devrequest {
unsigned char requesttype;
unsigned char bDescriptorType;
} __attribute__ ((packed));
-/* Device descriptor */
-struct usb_device_descriptor {
- unsigned char bLength;
- unsigned char bDescriptorType;
- unsigned short bcdUSB;
- unsigned char bDeviceClass;
- unsigned char bDeviceSubClass;
- unsigned char bDeviceProtocol;
- unsigned char bMaxPacketSize0;
- unsigned short idVendor;
- unsigned short idProduct;
- unsigned short bcdDevice;
- unsigned char iManufacturer;
- unsigned char iProduct;
- unsigned char iSerialNumber;
- unsigned char bNumConfigurations;
-} __attribute__ ((packed));
-
-/* Endpoint descriptor */
-struct usb_endpoint_descriptor {
- unsigned char bLength;
- unsigned char bDescriptorType;
- unsigned char bEndpointAddress;
- unsigned char bmAttributes;
- unsigned short wMaxPacketSize;
- unsigned char bInterval;
- unsigned char bRefresh;
- unsigned char bSynchAddress;
-} __attribute__ ((packed)) __attribute__ ((aligned(2)));
-
-/* Interface descriptor */
-struct usb_interface_descriptor {
- unsigned char bLength;
- unsigned char bDescriptorType;
- unsigned char bInterfaceNumber;
- unsigned char bAlternateSetting;
- unsigned char bNumEndpoints;
- unsigned char bInterfaceClass;
- unsigned char bInterfaceSubClass;
- unsigned char bInterfaceProtocol;
- unsigned char iInterface;
+/* Interface */
+struct usb_interface {
+ struct usb_interface_descriptor desc;
unsigned char no_of_ep;
unsigned char num_altsetting;
struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
} __attribute__ ((packed));
-
-/* Configuration descriptor information.. */
-struct usb_config_descriptor {
- unsigned char bLength;
- unsigned char bDescriptorType;
- unsigned short wTotalLength;
- unsigned char bNumInterfaces;
- unsigned char bConfigurationValue;
- unsigned char iConfiguration;
- unsigned char bmAttributes;
- unsigned char MaxPower;
+/* Configuration information.. */
+struct usb_config {
+ struct usb_configuration_descriptor desc;
unsigned char no_of_if; /* number of interfaces */
- struct usb_interface_descriptor if_desc[USB_MAXINTERFACES];
+ struct usb_interface if_desc[USB_MAXINTERFACES];
} __attribute__ ((packed));
enum {
int configno; /* selected config number */
struct usb_device_descriptor descriptor; /* Device Descriptor */
- struct usb_config_descriptor config; /* config descriptor */
+ struct usb_config config; /* config descriptor */
int have_langid; /* whether string_langid is valid yet */
int string_langid; /* language ID for strings */
#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \
defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \
defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \
- defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI)
+ defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) || \
+ defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \
+ defined(CONFIG_USB_BLACKFIN)
int usb_lowlevel_init(void);
int usb_lowlevel_stop(void);
--- /dev/null
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __MUSB_UDC_H__
+#define __MUSB_UDC_H__
+
+#include <usbdevice.h>
+
+/* UDC level routines */
+void udc_irq(void);
+void udc_set_nak(int ep_num);
+void udc_unset_nak(int ep_num);
+int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
+void udc_setup_ep(struct usb_device_instance *device, unsigned int id,
+ struct usb_endpoint_instance *endpoint);
+void udc_connect(void);
+void udc_disconnect(void);
+void udc_enable(struct usb_device_instance *device);
+void udc_disable(void);
+void udc_startup_events(struct usb_device_instance *device);
+int udc_init(void);
+
+/* usbtty */
+#ifdef CONFIG_USB_TTY
+
+#define EP0_MAX_PACKET_SIZE 64 /* MUSB_EP0_FIFOSIZE */
+#define UDC_INT_ENDPOINT 1
+#define UDC_INT_PACKET_SIZE 64
+#define UDC_OUT_ENDPOINT 2
+#define UDC_OUT_PACKET_SIZE 64
+#define UDC_IN_ENDPOINT 3
+#define UDC_IN_PACKET_SIZE 64
+#define UDC_BULK_PACKET_SIZE 64
+
+#endif /* CONFIG_USB_TTY */
+
+#endif /* __MUSB_UDC_H__ */
+
} __attribute__ ((packed));
+#ifdef DEBUG
+static inline void print_device_descriptor(struct usb_device_descriptor *d)
+{
+ serial_printf("usb device descriptor \n");
+ serial_printf("\tbLength %2.2x\n", d->bLength);
+ serial_printf("\tbDescriptorType %2.2x\n", d->bDescriptorType);
+ serial_printf("\tbcdUSB %4.4x\n", d->bcdUSB);
+ serial_printf("\tbDeviceClass %2.2x\n", d->bDeviceClass);
+ serial_printf("\tbDeviceSubClass %2.2x\n", d->bDeviceSubClass);
+ serial_printf("\tbDeviceProtocol %2.2x\n", d->bDeviceProtocol);
+ serial_printf("\tbMaxPacketSize0 %2.2x\n", d->bMaxPacketSize0);
+ serial_printf("\tidVendor %4.4x\n", d->idVendor);
+ serial_printf("\tidProduct %4.4x\n", d->idProduct);
+ serial_printf("\tbcdDevice %4.4x\n", d->bcdDevice);
+ serial_printf("\tiManufacturer %2.2x\n", d->iManufacturer);
+ serial_printf("\tiProduct %2.2x\n", d->iProduct);
+ serial_printf("\tiSerialNumber %2.2x\n", d->iSerialNumber);
+ serial_printf("\tbNumConfigurations %2.2x\n", d->bNumConfigurations);
+}
+
+#else
+
+/* stubs */
+#define print_device_descriptor(d)
+
+#endif /* DEBUG */
#endif
void usbd_rcv_complete(struct usb_endpoint_instance *endpoint, int len, int urb_bad);
void usbd_tx_complete (struct usb_endpoint_instance *endpoint);
+/* These are macros used in debugging */
+#ifdef DEBUG
+static inline void print_urb(struct urb *u)
+{
+ serial_printf("urb %p\n", (u));
+ serial_printf("\tendpoint %p\n", u->endpoint);
+ serial_printf("\tdevice %p\n", u->device);
+ serial_printf("\tbuffer %p\n", u->buffer);
+ serial_printf("\tbuffer_length %d\n", u->buffer_length);
+ serial_printf("\tactual_length %d\n", u->actual_length);
+ serial_printf("\tstatus %d\n", u->status);
+ serial_printf("\tdata %d\n", u->data);
+}
+
+static inline void print_usb_device_request(struct usb_device_request *r)
+{
+ serial_printf("usb request\n");
+ serial_printf("\tbmRequestType 0x%2.2x\n", r->bmRequestType);
+ if ((r->bmRequestType & USB_REQ_DIRECTION_MASK) == 0)
+ serial_printf("\t\tDirection : To device\n");
+ else
+ serial_printf("\t\tDirection : To host\n");
+ if ((r->bmRequestType & USB_TYPE_STANDARD) == USB_TYPE_STANDARD)
+ serial_printf("\t\tType : Standard\n");
+ if ((r->bmRequestType & USB_TYPE_CLASS) == USB_TYPE_CLASS)
+ serial_printf("\t\tType : Standard\n");
+ if ((r->bmRequestType & USB_TYPE_VENDOR) == USB_TYPE_VENDOR)
+ serial_printf("\t\tType : Standard\n");
+ if ((r->bmRequestType & USB_TYPE_RESERVED) == USB_TYPE_RESERVED)
+ serial_printf("\t\tType : Standard\n");
+ if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) ==
+ USB_REQ_RECIPIENT_DEVICE)
+ serial_printf("\t\tRecipient : Device\n");
+ if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) ==
+ USB_REQ_RECIPIENT_INTERFACE)
+ serial_printf("\t\tRecipient : Interface\n");
+ if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) ==
+ USB_REQ_RECIPIENT_ENDPOINT)
+ serial_printf("\t\tRecipient : Endpoint\n");
+ if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) ==
+ USB_REQ_RECIPIENT_OTHER)
+ serial_printf("\t\tRecipient : Other\n");
+ serial_printf("\tbRequest 0x%2.2x\n", r->bRequest);
+ if (r->bRequest == USB_REQ_GET_STATUS)
+ serial_printf("\t\tGET_STATUS\n");
+ else if (r->bRequest == USB_REQ_SET_ADDRESS)
+ serial_printf("\t\tSET_ADDRESS\n");
+ else if (r->bRequest == USB_REQ_SET_FEATURE)
+ serial_printf("\t\tSET_FEATURE\n");
+ else if (r->bRequest == USB_REQ_GET_DESCRIPTOR)
+ serial_printf("\t\tGET_DESCRIPTOR\n");
+ else if (r->bRequest == USB_REQ_SET_CONFIGURATION)
+ serial_printf("\t\tSET_CONFIGURATION\n");
+ else if (r->bRequest == USB_REQ_SET_INTERFACE)
+ serial_printf("\t\tUSB_REQ_SET_INTERFACE\n");
+ else
+ serial_printf("\tUNKNOWN %d\n", r->bRequest);
+ serial_printf("\twValue 0x%4.4x\n", r->wValue);
+ if (r->bRequest == USB_REQ_GET_DESCRIPTOR) {
+ switch (r->wValue >> 8) {
+ case USB_DESCRIPTOR_TYPE_DEVICE:
+ serial_printf("\tDEVICE\n");
+ break;
+ case USB_DESCRIPTOR_TYPE_CONFIGURATION:
+ serial_printf("\tCONFIGURATION\n");
+ break;
+ case USB_DESCRIPTOR_TYPE_STRING:
+ serial_printf("\tSTRING\n");
+ break;
+ case USB_DESCRIPTOR_TYPE_INTERFACE:
+ serial_printf("\tINTERFACE\n");
+ break;
+ case USB_DESCRIPTOR_TYPE_ENDPOINT:
+ serial_printf("\tENDPOINT\n");
+ break;
+ case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER:
+ serial_printf("\tDEVICE_QUALIFIER\n");
+ break;
+ case USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION:
+ serial_printf("\tOTHER_SPEED_CONFIGURATION\n");
+ break;
+ case USB_DESCRIPTOR_TYPE_INTERFACE_POWER:
+ serial_printf("\tINTERFACE_POWER\n");
+ break;
+ case USB_DESCRIPTOR_TYPE_HID:
+ serial_printf("\tHID\n");
+ break;
+ case USB_DESCRIPTOR_TYPE_REPORT:
+ serial_printf("\tREPORT\n");
+ break;
+ default:
+ serial_printf("\tUNKNOWN TYPE\n");
+ break;
+ }
+ }
+ serial_printf("\twIndex 0x%4.4x\n", r->wIndex);
+ serial_printf("\twLength 0x%4.4x\n", r->wLength);
+}
+#else
+/* stubs */
+#define print_urb(u)
+#define print_usb_device_request(r)
+#endif /* DEBUG */
#endif
* May be supplied by boards if desired
*/
void inline __coloured_LED_init (void) {}
-void inline coloured_LED_init (void) __attribute__((weak, alias("__coloured_LED_init")));
+void coloured_LED_init (void) __attribute__((weak, alias("__coloured_LED_init")));
void inline __red_LED_on (void) {}
-void inline red_LED_on (void) __attribute__((weak, alias("__red_LED_on")));
+void red_LED_on (void) __attribute__((weak, alias("__red_LED_on")));
void inline __red_LED_off(void) {}
-void inline red_LED_off(void) __attribute__((weak, alias("__red_LED_off")));
+void red_LED_off(void) __attribute__((weak, alias("__red_LED_off")));
void inline __green_LED_on(void) {}
-void inline green_LED_on(void) __attribute__((weak, alias("__green_LED_on")));
+void green_LED_on(void) __attribute__((weak, alias("__green_LED_on")));
void inline __green_LED_off(void) {}
-void inline green_LED_off(void)__attribute__((weak, alias("__green_LED_off")));
+void green_LED_off(void) __attribute__((weak, alias("__green_LED_off")));
void inline __yellow_LED_on(void) {}
-void inline yellow_LED_on(void)__attribute__((weak, alias("__yellow_LED_on")));
+void yellow_LED_on(void) __attribute__((weak, alias("__yellow_LED_on")));
void inline __yellow_LED_off(void) {}
-void inline yellow_LED_off(void)__attribute__((weak, alias("__yellow_LED_off")));
+void yellow_LED_off(void) __attribute__((weak, alias("__yellow_LED_off")));
void inline __blue_LED_on(void) {}
-void inline blue_LED_on(void)__attribute__((weak, alias("__blue_LED_on")));
+void blue_LED_on(void) __attribute__((weak, alias("__blue_LED_on")));
void inline __blue_LED_off(void) {}
-void inline blue_LED_off(void)__attribute__((weak, alias("__blue_LED_off")));
+void blue_LED_off(void) __attribute__((weak, alias("__blue_LED_off")));
/************************************************************************
* Init Utilities *
COBJS-$(CONFIG_BZIP2) += bzlib_decompress.o
COBJS-$(CONFIG_BZIP2) += bzlib_randtable.o
COBJS-$(CONFIG_BZIP2) += bzlib_huffman.o
+COBJS-$(CONFIG_USB_TTY) += circbuf.o
COBJS-y += crc16.o
COBJS-y += crc32.o
COBJS-y += ctype.o
COBJS-$(CONFIG_SHA256) += sha256.o
COBJS-y += string.o
COBJS-y += strmhz.o
+COBJS-y += time.o
COBJS-y += vsprintf.o
COBJS-y += zlib.o
COBJS-$(CONFIG_RBTREE) += rbtree.o
* For conditions of distribution and use, see copyright notice in zlib.h
*/
-#ifndef USE_HOSTCC /* Shut down "ANSI does not permit..." warnings */
+#ifndef USE_HOSTCC
#include <common.h>
-#else
-#include <stdint.h>
#endif
+#include <compiler.h>
+#include <u-boot/crc.h>
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
#include <watchdog.h>
#define local static
#define ZEXPORT /* empty */
+#define tole(x) cpu_to_le32(x)
+
#ifdef DYNAMIC_CRC_TABLE
local int crc_table_empty = 1;
c = (uLong)n;
for (k = 0; k < 8; k++)
c = c & 1 ? poly ^ (c >> 1) : c >> 1;
- crc_table[n] = c;
+ crc_table[n] = tole(c);
}
crc_table_empty = 0;
}
/* ========================================================================
* Table of CRC-32's of all single-byte values (made by make_crc_table)
*/
+
local const uint32_t crc_table[256] = {
- 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
- 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
- 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
- 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL,
- 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L,
- 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L,
- 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L,
- 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,
- 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L,
- 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL,
- 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L,
- 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L,
- 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L,
- 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL,
- 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL,
- 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,
- 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL,
- 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L,
- 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L,
- 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L,
- 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL,
- 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L,
- 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L,
- 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,
- 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L,
- 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L,
- 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L,
- 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L,
- 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L,
- 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL,
- 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL,
- 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,
- 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L,
- 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL,
- 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL,
- 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L,
- 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL,
- 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L,
- 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL,
- 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,
- 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL,
- 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L,
- 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L,
- 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL,
- 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L,
- 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L,
- 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L,
- 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,
- 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L,
- 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L,
- 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL,
- 0x2d02ef8dL
+tole(0x00000000L), tole(0x77073096L), tole(0xee0e612cL), tole(0x990951baL),
+tole(0x076dc419L), tole(0x706af48fL), tole(0xe963a535L), tole(0x9e6495a3L),
+tole(0x0edb8832L), tole(0x79dcb8a4L), tole(0xe0d5e91eL), tole(0x97d2d988L),
+tole(0x09b64c2bL), tole(0x7eb17cbdL), tole(0xe7b82d07L), tole(0x90bf1d91L),
+tole(0x1db71064L), tole(0x6ab020f2L), tole(0xf3b97148L), tole(0x84be41deL),
+tole(0x1adad47dL), tole(0x6ddde4ebL), tole(0xf4d4b551L), tole(0x83d385c7L),
+tole(0x136c9856L), tole(0x646ba8c0L), tole(0xfd62f97aL), tole(0x8a65c9ecL),
+tole(0x14015c4fL), tole(0x63066cd9L), tole(0xfa0f3d63L), tole(0x8d080df5L),
+tole(0x3b6e20c8L), tole(0x4c69105eL), tole(0xd56041e4L), tole(0xa2677172L),
+tole(0x3c03e4d1L), tole(0x4b04d447L), tole(0xd20d85fdL), tole(0xa50ab56bL),
+tole(0x35b5a8faL), tole(0x42b2986cL), tole(0xdbbbc9d6L), tole(0xacbcf940L),
+tole(0x32d86ce3L), tole(0x45df5c75L), tole(0xdcd60dcfL), tole(0xabd13d59L),
+tole(0x26d930acL), tole(0x51de003aL), tole(0xc8d75180L), tole(0xbfd06116L),
+tole(0x21b4f4b5L), tole(0x56b3c423L), tole(0xcfba9599L), tole(0xb8bda50fL),
+tole(0x2802b89eL), tole(0x5f058808L), tole(0xc60cd9b2L), tole(0xb10be924L),
+tole(0x2f6f7c87L), tole(0x58684c11L), tole(0xc1611dabL), tole(0xb6662d3dL),
+tole(0x76dc4190L), tole(0x01db7106L), tole(0x98d220bcL), tole(0xefd5102aL),
+tole(0x71b18589L), tole(0x06b6b51fL), tole(0x9fbfe4a5L), tole(0xe8b8d433L),
+tole(0x7807c9a2L), tole(0x0f00f934L), tole(0x9609a88eL), tole(0xe10e9818L),
+tole(0x7f6a0dbbL), tole(0x086d3d2dL), tole(0x91646c97L), tole(0xe6635c01L),
+tole(0x6b6b51f4L), tole(0x1c6c6162L), tole(0x856530d8L), tole(0xf262004eL),
+tole(0x6c0695edL), tole(0x1b01a57bL), tole(0x8208f4c1L), tole(0xf50fc457L),
+tole(0x65b0d9c6L), tole(0x12b7e950L), tole(0x8bbeb8eaL), tole(0xfcb9887cL),
+tole(0x62dd1ddfL), tole(0x15da2d49L), tole(0x8cd37cf3L), tole(0xfbd44c65L),
+tole(0x4db26158L), tole(0x3ab551ceL), tole(0xa3bc0074L), tole(0xd4bb30e2L),
+tole(0x4adfa541L), tole(0x3dd895d7L), tole(0xa4d1c46dL), tole(0xd3d6f4fbL),
+tole(0x4369e96aL), tole(0x346ed9fcL), tole(0xad678846L), tole(0xda60b8d0L),
+tole(0x44042d73L), tole(0x33031de5L), tole(0xaa0a4c5fL), tole(0xdd0d7cc9L),
+tole(0x5005713cL), tole(0x270241aaL), tole(0xbe0b1010L), tole(0xc90c2086L),
+tole(0x5768b525L), tole(0x206f85b3L), tole(0xb966d409L), tole(0xce61e49fL),
+tole(0x5edef90eL), tole(0x29d9c998L), tole(0xb0d09822L), tole(0xc7d7a8b4L),
+tole(0x59b33d17L), tole(0x2eb40d81L), tole(0xb7bd5c3bL), tole(0xc0ba6cadL),
+tole(0xedb88320L), tole(0x9abfb3b6L), tole(0x03b6e20cL), tole(0x74b1d29aL),
+tole(0xead54739L), tole(0x9dd277afL), tole(0x04db2615L), tole(0x73dc1683L),
+tole(0xe3630b12L), tole(0x94643b84L), tole(0x0d6d6a3eL), tole(0x7a6a5aa8L),
+tole(0xe40ecf0bL), tole(0x9309ff9dL), tole(0x0a00ae27L), tole(0x7d079eb1L),
+tole(0xf00f9344L), tole(0x8708a3d2L), tole(0x1e01f268L), tole(0x6906c2feL),
+tole(0xf762575dL), tole(0x806567cbL), tole(0x196c3671L), tole(0x6e6b06e7L),
+tole(0xfed41b76L), tole(0x89d32be0L), tole(0x10da7a5aL), tole(0x67dd4accL),
+tole(0xf9b9df6fL), tole(0x8ebeeff9L), tole(0x17b7be43L), tole(0x60b08ed5L),
+tole(0xd6d6a3e8L), tole(0xa1d1937eL), tole(0x38d8c2c4L), tole(0x4fdff252L),
+tole(0xd1bb67f1L), tole(0xa6bc5767L), tole(0x3fb506ddL), tole(0x48b2364bL),
+tole(0xd80d2bdaL), tole(0xaf0a1b4cL), tole(0x36034af6L), tole(0x41047a60L),
+tole(0xdf60efc3L), tole(0xa867df55L), tole(0x316e8eefL), tole(0x4669be79L),
+tole(0xcb61b38cL), tole(0xbc66831aL), tole(0x256fd2a0L), tole(0x5268e236L),
+tole(0xcc0c7795L), tole(0xbb0b4703L), tole(0x220216b9L), tole(0x5505262fL),
+tole(0xc5ba3bbeL), tole(0xb2bd0b28L), tole(0x2bb45a92L), tole(0x5cb36a04L),
+tole(0xc2d7ffa7L), tole(0xb5d0cf31L), tole(0x2cd99e8bL), tole(0x5bdeae1dL),
+tole(0x9b64c2b0L), tole(0xec63f226L), tole(0x756aa39cL), tole(0x026d930aL),
+tole(0x9c0906a9L), tole(0xeb0e363fL), tole(0x72076785L), tole(0x05005713L),
+tole(0x95bf4a82L), tole(0xe2b87a14L), tole(0x7bb12baeL), tole(0x0cb61b38L),
+tole(0x92d28e9bL), tole(0xe5d5be0dL), tole(0x7cdcefb7L), tole(0x0bdbdf21L),
+tole(0x86d3d2d4L), tole(0xf1d4e242L), tole(0x68ddb3f8L), tole(0x1fda836eL),
+tole(0x81be16cdL), tole(0xf6b9265bL), tole(0x6fb077e1L), tole(0x18b74777L),
+tole(0x88085ae6L), tole(0xff0f6a70L), tole(0x66063bcaL), tole(0x11010b5cL),
+tole(0x8f659effL), tole(0xf862ae69L), tole(0x616bffd3L), tole(0x166ccf45L),
+tole(0xa00ae278L), tole(0xd70dd2eeL), tole(0x4e048354L), tole(0x3903b3c2L),
+tole(0xa7672661L), tole(0xd06016f7L), tole(0x4969474dL), tole(0x3e6e77dbL),
+tole(0xaed16a4aL), tole(0xd9d65adcL), tole(0x40df0b66L), tole(0x37d83bf0L),
+tole(0xa9bcae53L), tole(0xdebb9ec5L), tole(0x47b2cf7fL), tole(0x30b5ffe9L),
+tole(0xbdbdf21cL), tole(0xcabac28aL), tole(0x53b39330L), tole(0x24b4a3a6L),
+tole(0xbad03605L), tole(0xcdd70693L), tole(0x54de5729L), tole(0x23d967bfL),
+tole(0xb3667a2eL), tole(0xc4614ab8L), tole(0x5d681b02L), tole(0x2a6f2b94L),
+tole(0xb40bbe37L), tole(0xc30c8ea1L), tole(0x5a05df1bL), tole(0x2d02ef8dL)
};
#endif
#endif
/* ========================================================================= */
-#define DO1(buf) crc = crc_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8);
-#define DO2(buf) DO1(buf); DO1(buf);
-#define DO4(buf) DO2(buf); DO2(buf);
-#define DO8(buf) DO4(buf); DO4(buf);
+# ifdef __LITTLE_ENDIAN
+# define DO_CRC(x) crc = tab[(crc ^ (x)) & 255] ^ (crc >> 8)
+# else
+# define DO_CRC(x) crc = tab[((crc >> 24) ^ (x)) & 255] ^ (crc << 8)
+# endif
/* ========================================================================= */
-uint32_t ZEXPORT crc32 (uint32_t crc, const Bytef *buf, uInt len)
-{
-#ifdef DYNAMIC_CRC_TABLE
- if (crc_table_empty)
- make_crc_table();
-#endif
- crc = crc ^ 0xffffffffL;
- while (len >= 8)
- {
- DO8(buf);
- len -= 8;
- }
- if (len) do {
- DO1(buf);
- } while (--len);
- return crc ^ 0xffffffffL;
-}
-
-#if defined(CONFIG_CMD_JFFS2) || defined(CONFIG_CMD_NAND)
/* No ones complement version. JFFS2 (and other things ?)
* don't use ones compliment in their CRC calculations.
*/
uint32_t ZEXPORT crc32_no_comp(uint32_t crc, const Bytef *buf, uInt len)
{
+ const uint32_t *tab = crc_table;
+ const uint32_t *b =(const uint32_t *)buf;
+ size_t rem_len;
#ifdef DYNAMIC_CRC_TABLE
if (crc_table_empty)
make_crc_table();
#endif
- while (len >= 8)
- {
- DO8(buf);
- len -= 8;
+ crc = cpu_to_le32(crc);
+ /* Align it */
+ if (((long)b) & 3 && len) {
+ uint8_t *p = (uint8_t *)b;
+ do {
+ DO_CRC(*p++);
+ } while ((--len) && ((long)p)&3);
+ b = (uint32_t *)p;
+ }
+
+ rem_len = len & 3;
+ len = len >> 2;
+ for (--b; len; --len) {
+ /* load data 32 bits wide, xor data 32 bits wide. */
+ crc ^= *++b; /* use pre increment for speed */
+ DO_CRC(0);
+ DO_CRC(0);
+ DO_CRC(0);
+ DO_CRC(0);
+ }
+ len = rem_len;
+ /* And the last few bytes */
+ if (len) {
+ uint8_t *p = (uint8_t *)(b + 1) - 1;
+ do {
+ DO_CRC(*++p); /* use pre increment for speed */
+ } while (--len);
}
- if (len) do {
- DO1(buf);
- } while (--len);
- return crc;
+ return le32_to_cpu(crc);
}
+#undef DO_CRC
-#endif
+uint32_t ZEXPORT crc32 (uint32_t crc, const Bytef *p, uInt len)
+{
+ return crc32_no_comp(crc ^ 0xffffffffL, p, len) ^ 0xffffffffL;
+}
/*
* Calculate the crc32 checksum triggering the watchdog every 'chunk_sz' bytes
#define RESERVED 0xe0
#define DEFLATED 8
-int gunzip(void *, int, unsigned char *, unsigned long *);
void *zalloc(void *, unsigned, unsigned);
void zfree(void *, void *, unsigned);
-int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp,
- int stoponerr, int offset);
void *zalloc(void *x, unsigned items, unsigned size)
{
} else if (outSizeHigh != 0 || (UInt32)(SizeT)outSize != outSize) {
/*
* SizeT is a 32 bit uint => We cannot manage files larger than
- * 4GB!
+ * 4GB! Assume however that all 0xf values is "unknown size" and
+ * not actually a file of 2^64 bits.
*
*/
- debug ("LZMA: 64bit support not enabled.\n");
- return SZ_ERROR_DATA;
+ if (outSizeHigh != (SizeT)-1 || outSize != (SizeT)-1) {
+ debug ("LZMA: 64bit support not enabled.\n");
+ return SZ_ERROR_DATA;
+ }
}
debug ("LZMA: Uncompresed size............ 0x%lx\n", outSizeFull);
#define COPY4(dst, src) \
put_unaligned(get_unaligned((const u32 *)(src)), (u32 *)(dst))
+static const unsigned char lzop_magic[] = {
+ 0x89, 0x4c, 0x5a, 0x4f, 0x00, 0x0d, 0x0a, 0x1a, 0x0a
+};
+
+#define HEADER_HAS_FILTER 0x00000800L
+
+static inline const unsigned char *parse_header(const unsigned char *src)
+{
+ u8 level = 0;
+ u16 version;
+ int i;
+
+ /* read magic: 9 first bytes */
+ for (i = 0; i < ARRAY_SIZE(lzop_magic); i++) {
+ if (*src++ != lzop_magic[i])
+ return NULL;
+ }
+ /* get version (2bytes), skip library version (2),
+ * 'need to be extracted' version (2) and
+ * method (1) */
+ version = get_unaligned_be16(src);
+ src += 7;
+ if (version >= 0x0940)
+ level = *src++;
+ if (get_unaligned_be32(src) & HEADER_HAS_FILTER)
+ src += 4; /* filter info */
+
+ /* skip flags, mode and mtime_low */
+ src += 12;
+ if (version >= 0x0940)
+ src += 4; /* skip mtime_high */
+
+ i = *src++;
+ /* don't care about the file name, and skip checksum */
+ src += i + 4;
+
+ return src;
+}
+
+int lzop_decompress(const unsigned char *src, size_t src_len,
+ unsigned char *dst, size_t *dst_len)
+{
+ unsigned char *start = dst;
+ const unsigned char *send = src + src_len;
+ u32 slen, dlen;
+ size_t tmp;
+ int r;
+
+ src = parse_header(src);
+ if (!src)
+ return LZO_E_ERROR;
+
+ while (src < send) {
+ /* read uncompressed block size */
+ dlen = get_unaligned_be32(src);
+ src += 4;
+
+ /* exit if last block */
+ if (dlen == 0) {
+ *dst_len = dst - start;
+ return LZO_E_OK;
+ }
+
+ /* read compressed block size, and skip block checksum info */
+ slen = get_unaligned_be32(src);
+ src += 8;
+
+ if (slen <= 0 || slen > dlen)
+ return LZO_E_ERROR;
+
+ /* decompress */
+ tmp = dlen;
+ r = lzo1x_decompress_safe((u8 *) src, slen, dst, &tmp);
+
+ if (r != LZO_E_OK)
+ return r;
+
+ if (dlen != tmp)
+ return LZO_E_ERROR;
+
+ src += slen;
+ dst += dlen;
+ }
+
+ return LZO_E_INPUT_OVERRUN;
+}
+
int lzo1x_decompress_safe(const unsigned char *in, size_t in_len,
unsigned char *out, size_t *out_len)
{
--- /dev/null
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+
+#ifndef CONFIG_WD_PERIOD
+# define CONFIG_WD_PERIOD (10 * 1000 * 1000) /* 10 seconds default*/
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+void udelay(unsigned long usec)
+{
+ ulong kv;
+
+ do {
+ WATCHDOG_RESET();
+ kv = usec > CONFIG_WD_PERIOD ? CONFIG_WD_PERIOD : usec;
+ __udelay (kv);
+ usec -= kv;
+ } while(usec);
+}
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
#endif
-#ifdef CONFIG_SYS_64BIT_VSPRINTF
#include <div64.h>
# define NUM_TYPE long long
-#else
-# define NUM_TYPE long
-#define do_div(n, base) ({ \
- unsigned int __res; \
- __res = ((unsigned NUM_TYPE) n) % base; \
- n = ((unsigned NUM_TYPE) n) / base; \
- __res; \
-})
-#endif
#define noinline __attribute__((noinline))
-
const char hex_asc[] = "0123456789abcdef";
#define hex_asc_lo(x) hex_asc[((x) & 0x0f)]
#define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4]
return result;
}
-#ifdef CONFIG_SYS_64BIT_STRTOUL
unsigned long long simple_strtoull (const char *cp, char **endp, unsigned int base)
{
unsigned long long result = 0, value;
*endp = (char *) cp;
return result;
}
-#endif /* CONFIG_SYS_64BIT_STRTOUL */
/* we use this so that we can do without the ctype library */
#define is_digit(c) ((c) >= '0' && (c) <= '9')
--fmt;
continue;
}
-#ifdef CONFIG_SYS_64BIT_VSPRINTF
if (qualifier == 'L') /* "quad" for 64 bit variables */
num = va_arg(args, unsigned long long);
- else
-#endif
- if (qualifier == 'l') {
+ else if (qualifier == 'l') {
num = va_arg(args, unsigned long);
if (flags & SIGN)
num = (signed long) num;
#define ZUTIL_H
#define ZLIB_INTERNAL
-#include "u-boot/zlib.h"
#include <common.h>
+#include <compiler.h>
+#include <asm/unaligned.h>
+#include "u-boot/zlib.h"
+#undef OFF /* avoid conflicts */
+
/* To avoid a build time warning */
#ifdef STDC
#include <malloc.h>
*/
#define OFF 1
#define PUP(a) *++(a)
+#define UP_UNALIGNED(a) get_unaligned(++(a))
/*
Decode literal, length, and distance codes and write out the resulting
}
}
else {
+ unsigned short *sout;
+ unsigned long loops;
+
from = out - dist; /* copy direct from output */
- do { /* minimum length is three */
- PUP(out) = PUP(from);
- PUP(out) = PUP(from);
- PUP(out) = PUP(from);
- len -= 3;
- } while (len > 2);
- if (len) {
- PUP(out) = PUP(from);
- if (len > 1)
- PUP(out) = PUP(from);
- }
+ /* minimum length is three */
+ /* Align out addr */
+ if (!((long)(out - 1 + OFF) & 1)) {
+ PUP(out) = PUP(from);
+ len--;
+ }
+ sout = (unsigned short *)(out - OFF);
+ if (dist > 2 ) {
+ unsigned short *sfrom;
+
+ sfrom = (unsigned short *)(from - OFF);
+ loops = len >> 1;
+ do
+ PUP(sout) = UP_UNALIGNED(sfrom);
+ while (--loops);
+ out = (unsigned char *)sout + OFF;
+ from = (unsigned char *)sfrom + OFF;
+ } else { /* dist == 1 or dist == 2 */
+ unsigned short pat16;
+
+ pat16 = *(sout-2+2*OFF);
+ if (dist == 1)
+#if defined(__BIG_ENDIAN)
+ pat16 = (pat16 & 0xff) | ((pat16 & 0xff ) << 8);
+#elif defined(__LITTLE_ENDIAN)
+ pat16 = (pat16 & 0xff00) | ((pat16 & 0xff00 ) >> 8);
+#else
+#error __BIG_ENDIAN nor __LITTLE_ENDIAN is defined
+#endif
+ loops = len >> 1;
+ do
+ PUP(sout) = pat16;
+ while (--loops);
+ out = (unsigned char *)sout + OFF;
+ }
+ if (len & 1)
+ PUP(out) = PUP(from);
}
}
else if ((op & 64) == 0) { /* 2nd level distance code */
COBJS-y += bios_setup.o
COBJS-y += board.o
COBJS-y += bootm.o
+COBJS-y += interrupts.o
+COBJS-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o
+COBJS-$(CONFIG_SYS_GENERIC_TIMER) += pcat_timer.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS-$(CONFIG_PCI) += pci_type1.o
COBJS-y += realmode.o
+COBJS-y += timer.o
COBJS-y += video_bios.o
COBJS-y += video.o
COBJS-y += zimage.o
-COBJS-y += interrupts.o
-COBJS-y += timer.o
-COBJS-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o
-COBJS-$(CONFIG_SYS_GENERIC_TIMER) += pcat_timer.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
jmp realmode_reset
.globl rm_int00
+.hidden rm_int00
+.type rm_int00, @function
rm_int00:
pushw $0
jmp any_interrupt16
.globl rm_int01
+.hidden rm_int01
+.type rm_int01, @function
rm_int01:
pushw $1
jmp any_interrupt16
.globl rm_int02
+.hidden rm_int02
+.type rm_int02, @function
rm_int02:
pushw $2
jmp any_interrupt16
.globl rm_int03
+.hidden rm_int03
+.type rm_int03, @function
rm_int03:
pushw $3
jmp any_interrupt16
.globl rm_int04
+.hidden rm_int04
+.type rm_int04, @function
rm_int04:
pushw $4
jmp any_interrupt16
.globl rm_int05
+.hidden rm_int05
+.type rm_int05, @function
rm_int05:
pushw $5
jmp any_interrupt16
.globl rm_int06
+.hidden rm_int06
+.type rm_int06, @function
rm_int06:
pushw $6
jmp any_interrupt16
.globl rm_int07
+.hidden rm_int07
+.type rm_int07, @function
rm_int07:
pushw $7
jmp any_interrupt16
.globl rm_int08
+.hidden rm_int08
+.type rm_int08, @function
rm_int08:
pushw $8
jmp any_interrupt16
.globl rm_int09
+.hidden rm_int09
+.type rm_int09, @function
rm_int09:
pushw $9
jmp any_interrupt16
.globl rm_int0a
+.hidden rm_int0a
+.type rm_int0a, @function
rm_int0a:
pushw $10
jmp any_interrupt16
.globl rm_int0b
+.hidden rm_int0b
+.type rm_int0b, @function
rm_int0b:
pushw $11
jmp any_interrupt16
.globl rm_int0c
+.hidden rm_int0c
+.type rm_int0c, @function
rm_int0c:
pushw $12
jmp any_interrupt16
.globl rm_int0d
+.hidden rm_int0d
+.type rm_int0d, @function
rm_int0d:
pushw $13
jmp any_interrupt16
.globl rm_int0e
+.hidden rm_int0e
+.type rm_int0e, @function
rm_int0e:
pushw $14
jmp any_interrupt16
.globl rm_int0f
+.hidden rm_int0f
+.type rm_int0f, @function
rm_int0f:
pushw $15
jmp any_interrupt16
.globl rm_int10
+.hidden rm_int10
+.type rm_int10, @function
rm_int10:
pushw $16
jmp any_interrupt16
.globl rm_int11
+.hidden rm_int11
+.type rm_int11, @function
rm_int11:
pushw $17
jmp any_interrupt16
.globl rm_int12
+.hidden rm_int12
+.type rm_int12, @function
rm_int12:
pushw $18
jmp any_interrupt16
.globl rm_int13
+.hidden rm_int13
+.type rm_int13, @function
rm_int13:
pushw $19
jmp any_interrupt16
.globl rm_int14
+.hidden rm_int14
+.type rm_int14, @function
rm_int14:
pushw $20
jmp any_interrupt16
.globl rm_int15
+.hidden rm_int15
+.type rm_int15, @function
rm_int15:
pushw $21
jmp any_interrupt16
.globl rm_int16
+.hidden rm_int16
+.type rm_int16, @function
rm_int16:
pushw $22
jmp any_interrupt16
.globl rm_int17
+.hidden rm_int17
+.type rm_int17, @function
rm_int17:
pushw $23
jmp any_interrupt16
.globl rm_int18
+.hidden rm_int18
+.type rm_int18, @function
rm_int18:
pushw $24
jmp any_interrupt16
.globl rm_int19
+.hidden rm_int19
+.type rm_int19, @function
rm_int19:
pushw $25
jmp any_interrupt16
.globl rm_int1a
+.hidden rm_int1a
+.type rm_int1a, @function
rm_int1a:
pushw $26
jmp any_interrupt16
.globl rm_int1b
+.hidden rm_int1b
+.type rm_int1b, @function
rm_int1b:
pushw $27
jmp any_interrupt16
.globl rm_int1c
+.hidden rm_int1c
+.type rm_int1c, @function
rm_int1c:
pushw $28
jmp any_interrupt16
.globl rm_int1d
+.hidden rm_int1d
+.type rm_int1d, @function
rm_int1d:
pushw $29
jmp any_interrupt16
.globl rm_int1e
+.hidden rm_int1e
+.type rm_int1e, @function
rm_int1e:
pushw $30
jmp any_interrupt16
.globl rm_int1f
+.hidden rm_int1f
+.type rm_int1f, @function
rm_int1f:
pushw $31
jmp any_interrupt16
.globl rm_def_int
+.hidden rm_def_int
+.type rm_def_int, @function
rm_def_int:
iret
.globl ram_in_64kb_chunks
+.hidden ram_in_64kb_chunks
+.type ram_in_64kb_chunks, @function
ram_in_64kb_chunks:
.word 0
.globl bios_equipment
+.hidden bios_equipment
+.type bios_equipment, @function
bios_equipment:
.word 0
.section .bios, "ax"
.code16
.globl realmode_pci_bios_call_entry
+.hidden realmode_pci_bios_call_entry
+.type realmode_pci_bios_call_entry, @function
realmode_pci_bios_call_entry:
MAKE_BIOS_STACK
call realmode_pci_bios
#define BIOS_BASE ((char*)0xf0000)
#define BIOS_CS 0xf000
+extern ulong _i386boot_bios;
+extern ulong _i386boot_bios_size;
+
/* these are defined in a 16bit segment and needs
* to be accessed with the RELOC_16_xxxx() macros below
*/
int bios_setup(void)
{
+ ulong i386boot_bios = (ulong)&_i386boot_bios;
+ ulong i386boot_bios_size = (ulong)&_i386boot_bios_size;
+
static int done=0;
int vector;
#ifdef CONFIG_PCI
#include <net.h>
#include <ide.h>
#include <asm/u-boot-i386.h>
+#include <elf.h>
#ifdef CONFIG_BITBANGMII
#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
-extern long _i386boot_start;
-extern long _i386boot_end;
-extern long _i386boot_romdata_start;
-extern long _i386boot_romdata_dest;
-extern long _i386boot_romdata_size;
-extern long _i386boot_bss_start;
-extern long _i386boot_bss_size;
-
-extern long _i386boot_realmode;
-extern long _i386boot_realmode_size;
-extern long _i386boot_bios;
-extern long _i386boot_bios_size;
-
-/* The symbols defined by the linker script becomes pointers
- * which is somewhat inconveient ... */
-ulong i386boot_start = (ulong)&_i386boot_start; /* code start (in flash) defined in start.S */
-ulong i386boot_end = (ulong)&_i386boot_end; /* code end (in flash) */
-ulong i386boot_romdata_start = (ulong)&_i386boot_romdata_start; /* datasegment in flash (also code+rodata end) */
-ulong i386boot_romdata_dest = (ulong)&_i386boot_romdata_dest; /* data location segment in ram */
-ulong i386boot_romdata_size = (ulong)&_i386boot_romdata_size; /* size of data segment */
-ulong i386boot_bss_start = (ulong)&_i386boot_bss_start; /* bss start */
-ulong i386boot_bss_size = (ulong)&_i386boot_bss_size; /* bss size */
-
-ulong i386boot_realmode = (ulong)&_i386boot_realmode; /* start of realmode entry code */
-ulong i386boot_realmode_size = (ulong)&_i386boot_realmode_size; /* size of realmode entry code */
-ulong i386boot_bios = (ulong)&_i386boot_bios; /* start of BIOS emulation code */
-ulong i386boot_bios_size = (ulong)&_i386boot_bios_size; /* size of BIOS emulation code */
-
-
+/* Exports from the Linker Script */
+extern ulong _i386boot_text_start;
+extern ulong _i386boot_rel_dyn_start;
+extern ulong _i386boot_rel_dyn_end;
+extern ulong _i386boot_bss_start;
+extern ulong _i386boot_bss_size;
+void ram_bootstrap (void *);
const char version_string[] =
U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")";
-static int mem_malloc_init(void)
-{
- /* start malloc area right after the stack */
- mem_malloc_start = i386boot_bss_start +
- i386boot_bss_size + CONFIG_SYS_STACK_SIZE;
- mem_malloc_start = (mem_malloc_start+3)&~3;
-
- /* Use all available RAM for malloc() */
- mem_malloc_end = gd->ram_size;
-
- mem_malloc_brk = mem_malloc_start;
-
- return 0;
-}
-
/************************************************************************
* Init Utilities *
************************************************************************
{
printf ("\n\n%s\n\n", version_string);
+/*
printf ("U-Boot code: %08lX -> %08lX data: %08lX -> %08lX\n"
" BSS: %08lX -> %08lX stack: %08lX -> %08lX\n",
i386boot_start, i386boot_romdata_start-1,
i386boot_bss_start+i386boot_bss_size,
i386boot_bss_start+i386boot_bss_size+CONFIG_SYS_STACK_SIZE-1);
+*/
return (0);
}
print_size (size, "\n");
}
-
/*
* Breath some life into the board...
*
* can relocate the monitor code to RAM.
*/
+
/*
* All attempts to come up with a "common" initialization sequence
* that works for all boards and architectures failed: some of the
typedef int (init_fnc_t) (void);
init_fnc_t *init_sequence[] = {
- cpu_init, /* basic cpu dependent setup */
- board_init, /* basic board dependent setup */
+ serial_init,
+ cpu_init_r, /* basic cpu dependent setup */
+ board_early_init_r, /* basic board dependent setup */
dram_init, /* configure available RAM banks */
- mem_malloc_init, /* dependant on dram_init */
interrupt_init, /* set up exceptions */
timer_init,
- serial_init,
env_init, /* initialize environment */
init_baudrate, /* initialze baudrate settings */
serial_init, /* serial communications setup */
gd_t *gd;
-void start_i386boot (void)
+/*
+ * Load U-Boot into RAM, initialize BSS, perform relocation adjustments
+ */
+void board_init_f (ulong stack_limit)
+{
+ void *text_start = &_i386boot_text_start;
+ void *u_boot_cmd_end = &__u_boot_cmd_end;
+ Elf32_Rel *rel_dyn_start = (Elf32_Rel *)&_i386boot_rel_dyn_start;
+ Elf32_Rel *rel_dyn_end = (Elf32_Rel *)&_i386boot_rel_dyn_end;
+ void *bss_start = &_i386boot_bss_start;
+ void *bss_size = &_i386boot_bss_size;
+
+ size_t uboot_size;
+ void *ram_start;
+ ulong rel_offset;
+ Elf32_Rel *re;
+
+ void (*start_func)(void *);
+
+ /* compiler optimization barrier needed for GCC >= 3.4 */
+ __asm__ __volatile__("": : :"memory");
+
+ uboot_size = (size_t)u_boot_cmd_end - (size_t)text_start;
+ ram_start = (void *)stack_limit - (uboot_size + (ulong)bss_size);
+ rel_offset = text_start - ram_start;
+ start_func = ram_bootstrap - rel_offset;
+
+ /* First stage CPU initialization */
+ if (cpu_init_f() != 0)
+ hang();
+
+ /* First stage Board initialization */
+ if (board_early_init_f() != 0)
+ hang();
+
+ /* Copy U-Boot into RAM */
+ memcpy(ram_start, text_start, (size_t)uboot_size);
+
+ /* Clear BSS */
+ memset(bss_start - rel_offset, 0, (size_t)bss_size);
+
+ /* Perform relocation adjustments */
+ for (re = rel_dyn_start; re < rel_dyn_end; re++)
+ {
+ if (re->r_offset >= TEXT_BASE)
+ if (*(ulong *)re->r_offset >= TEXT_BASE)
+ *(ulong *)(re->r_offset - rel_offset) -= (Elf32_Addr)rel_offset;
+ }
+
+ start_func(ram_start);
+
+ /* NOTREACHED - relocate_code() does not return */
+ while(1);
+}
+
+/*
+ * All attempts to jump straight from board_init_f() to board_init_r()
+ * have failed, hence this special 'bootstrap' function.
+ */
+void ram_bootstrap (void *ram_start)
+{
+ static gd_t gd_data;
+
+ /* compiler optimization barrier needed for GCC >= 3.4 */
+ __asm__ __volatile__("": : :"memory");
+
+ board_init_r(&gd_data, (ulong)ram_start);
+}
+
+void board_init_r(gd_t *id, ulong ram_start)
{
char *s;
int i;
ulong size;
- static gd_t gd_data;
static bd_t bd_data;
init_fnc_t **init_fnc_ptr;
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
- cmd_tbl_t *p;
-#endif
show_boot_progress(0x21);
- gd = &gd_data;
+ gd = id;
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
gd->baudrate = CONFIG_BAUDRATE;
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
- /* Need to set relocation offset here for interrupt initialization */
- gd->reloc_off = CONFIG_SYS_BL_START_RAM - TEXT_BASE;
-#endif
+ gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
+
+ mem_malloc_init((((ulong)ram_start - CONFIG_SYS_MALLOC_LEN)+3)&~3,
+ CONFIG_SYS_MALLOC_LEN);
+
for (init_fnc_ptr = init_sequence, i=0; *init_fnc_ptr; ++init_fnc_ptr, i++) {
show_boot_progress(0xa130|i);
}
show_boot_progress(0x23);
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
- for (p = &__u_boot_cmd_start; p != &__u_boot_cmd_end; p++) {
- ulong addr;
- addr = (ulong) (p->cmd) + gd->reloc_off;
- p->cmd = (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
- addr = (ulong)(p->name) + gd->reloc_off;
- p->name = (char *)addr;
-
- if (p->usage != NULL) {
- addr = (ulong)(p->usage) + gd->reloc_off;
- p->usage = (char *)addr;
- }
- #ifdef CONFIG_SYS_LONGHELP
- if (p->help != NULL) {
- addr = (ulong)(p->help) + gd->reloc_off;
- p->help = (char *)addr;
- }
- #endif
- }
-#endif
/* configure available FLASH banks */
size = flash_init();
display_flash_config(size);
if (irq_handlers[irq].handler != NULL)
printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
- (ulong) handler + gd->reloc_off,
+ (ulong) handler,
(ulong) irq_handlers[irq].handler);
status = disable_interrupts ();
- irq_handlers[irq].handler = handler + gd->reloc_off;
+ irq_handlers[irq].handler = handler;
irq_handlers[irq].arg = arg;
irq_handlers[irq].count = 0;
return;
}
-__isr__ do_irq(int irq)
+void do_irq(int hw_irq)
{
+ int irq = hw_irq - 0x20;
+
if (irq < 0 || irq >= CONFIG_SYS_NUM_IRQS) {
printf("do_irq: bad irq number %d\n", irq);
return;
#error "CONFIG_SYS_NUM_IRQS must equal 16 if CONFIG_SYS_NUM_IRQS is defined"
#endif
-DECLARE_INTERRUPT(0);
-DECLARE_INTERRUPT(1);
-DECLARE_INTERRUPT(3);
-DECLARE_INTERRUPT(4);
-DECLARE_INTERRUPT(5);
-DECLARE_INTERRUPT(6);
-DECLARE_INTERRUPT(7);
-DECLARE_INTERRUPT(8);
-DECLARE_INTERRUPT(9);
-DECLARE_INTERRUPT(10);
-DECLARE_INTERRUPT(11);
-DECLARE_INTERRUPT(12);
-DECLARE_INTERRUPT(13);
-DECLARE_INTERRUPT(14);
-DECLARE_INTERRUPT(15);
-
int interrupt_init(void)
{
u8 i;
disable_interrupts();
- /* Setup interrupts */
- set_vector(0x20, irq_0);
- set_vector(0x21, irq_1);
- set_vector(0x23, irq_3);
- set_vector(0x24, irq_4);
- set_vector(0x25, irq_5);
- set_vector(0x26, irq_6);
- set_vector(0x27, irq_7);
- set_vector(0x28, irq_8);
- set_vector(0x29, irq_9);
- set_vector(0x2a, irq_10);
- set_vector(0x2b, irq_11);
- set_vector(0x2c, irq_12);
- set_vector(0x2d, irq_13);
- set_vector(0x2e, irq_14);
- set_vector(0x2f, irq_15);
-
/* Mask all interrupts */
outb(0xff, MASTER_PIC + IMR);
outb(0xff, SLAVE_PIC + IMR);
}
/* this is not very exact */
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
int counter;
int wraps;
#define REALMODE_MAILBOX ((char*)0xe00)
+extern ulong _i386boot_realmode;
+extern ulong _i386boot_realmode_size;
extern char realmode_enter;
int realmode_setup(void)
{
+ ulong i386boot_realmode = (ulong)&_i386boot_realmode;
+ ulong i386boot_realmode_size = (ulong)&_i386boot_realmode_size;
+
/* copy the realmode switch code */
if (i386boot_realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) {
printf("realmode switch too large (%ld bytes, max is %d)\n",
if (new_func == NULL)
return 1;
- new_func->isr_func = isr_func + gd->reloc_off;
+ new_func->isr_func = isr_func;
new_func->next = NULL;
/*
#endif
extern void dtimer_intr_setup(void);
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_UDELAY_BASE);
uint start, now, tmp;
static unsigned short lastinc;
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_UDELAY_BASE);
uint tmp;
#include <common.h>
#ifdef CONFIG_SYS_TIMER_0
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
int i;
i = get_timer (0);
while ((get_timer (0) - i) < (usec / 1000)) ;
}
#else
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
unsigned int i;
for (i = 0; i < (usec * CONFIG_XILINX_CLOCK_FREQ / 10000000); i++);
write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
}
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
unsigned int tmo;
CROSS_COMPILE ?= nios-elf-
-STANDALONE_LOAD_ADDR = 0x00800000 -L $(gcclibdir)/m32 -T nios.lds
+STANDALONE_LOAD_ADDR = 0x00800000 -L $(gcclibdir)/m32
PLATFORM_CPPFLAGS += -m32 -DCONFIG_NIOS -D__NIOS__ -ffixed-g7 -gstabs
extern void dly_clks( unsigned long ticks );
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
/* The Nios core doesn't have a timebase, so we do our
* best for now and call a low-level loop that counts
* cpu clocks.
*/
unsigned long cnt = (CONFIG_SYS_CLK_FREQ/1000000) * usec;
- WATCHDOG_RESET (); /* trigger watchdog if needed */
dly_clks (cnt);
}
{
bd_t *bd;
init_fnc_t **init_fnc_ptr;
- char *s, *e;
- int i;
/* Pointer is writable since we allocated a register for it.
* Nios treats CONFIG_SYS_GBL_DATA_OFFSET as an address.
#include <common.h>
#include <command.h>
#include <asm/byteorder.h>
+#include <asm/cache.h>
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
{
if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
return 1;
+ /* flushes data and instruction caches before calling the kernel */
+ flush_dcache (0,CONFIG_SYS_DCACHE_SIZE);
+ flush_icache (0,CONFIG_SYS_ICACHE_SIZE);
+
/* For now we assume the Microtronix linux ... which only
* needs to be called ;-)
*/
CROSS_COMPILE ?= nios2-elf-
-STANDALONE_LOAD_ADDR = 0x02000000 -L $(gcclibdir) -T nios2.lds
+STANDALONE_LOAD_ADDR = 0x02000000 -L $(gcclibdir)
PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__
PLATFORM_CPPFLAGS += -ffixed-r15 -G0
extern void dly_clks( unsigned long ticks );
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
/* The Nios core doesn't have a timebase, so we do our
* best for now and call a low-level loop that counts
* cpu clocks.
*/
unsigned long cnt = (CONFIG_SYS_CLK_FREQ/1000000) * usec;
- WATCHDOG_RESET (); /* trigger watchdog if needed */
dly_clks (cnt);
}
COBJS-y += cache.o
COBJS-y += extable.o
COBJS-y += interrupts.o
-COBJS-y += kgdb.o
+COBJS-$(CONFIG_CMD_KGDB) += kgdb.o
COBJS-y += time.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
/* The Malloc area is immediately below the monitor copy in DRAM */
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+ /*
+ * The gd->cpu pointer is set to an address in flash before relocation.
+ * We need to update it to point to the same CPU entry in RAM.
+ */
+ gd->cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
+#endif
+
#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
#endif
#include <common.h>
#include <command.h>
-
-#if defined(CONFIG_CMD_KGDB)
-
#include <kgdb.h>
#include <asm/signal.h>
#include <asm/processor.h>
breakinst: .long 0x7d821008\n\
");
}
-
-#endif
#include <common.h>
-#ifndef CONFIG_WD_PERIOD
-# define CONFIG_WD_PERIOD (10 * 1000 * 1000) /* 10 seconds default*/
-#endif
-
/* ------------------------------------------------------------------------- */
/*
* microseconds to wait) into a number of time base ticks; then we
* watch the time base until it has incremented by that amount.
*/
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
- ulong ticks, kv;
-
- do {
- kv = usec > CONFIG_WD_PERIOD ? CONFIG_WD_PERIOD : usec;
- ticks = usec2ticks (kv);
- wait_ticks (ticks);
- usec -= kv;
- } while(usec);
+ ulong ticks = usec2ticks (usec);
+ wait_ticks (ticks);
}
/* ------------------------------------------------------------------------- */
return 0 - readl(TCNT0);
}
-void udelay (unsigned long usec)
+void __udelay (unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
cmt_timer_start(0);
}
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
unsigned long end = get_usec() + usec;
* microseconds to wait) into a number of time base ticks; then we
* watch the time base until it has incremented by that amount.
*/
-void udelay(unsigned long usec)
+void __udelay(unsigned long usec)
{
ulong ticks = usec2ticks(usec);
[ $# -lt 4 ] && exit 1
[ $# -gt 6 ] && exit 1
+if [ "${ARCH}" -a "${ARCH}" != "$2" ]; then
+ echo "Failed: \$ARCH=${ARCH}, should be '$2' for ${BOARD_NAME}" 1>&2
+ exit 1
+fi
+
echo "Configuring for ${BOARD_NAME} board..."
#
[ "$6" ] && [ "$6" != "NULL" ] && echo "SOC = $6" >> config.mk
+# Assign board directory to BOARDIR variable
+if [ -z "$5" -o "$5" = "NULL" ] ; then
+ BOARDDIR=$4
+else
+ BOARDDIR=$5/$4
+fi
+
#
# Create board specific header file
#
echo "#define CONFIG_MK_${i} 1" >>config.h ;
done
+echo "#define CONFIG_BOARDDIR board/$BOARDDIR" >>config.h
+
echo "#include <configs/$1.h>" >>config.h
echo "#include <asm/config.h>" >>config.h
#include <common.h>
#include <asm/io.h>
-#include <asm/immap_83xx.h>
#include <asm/fsl_lbc.h>
#include <linux/mtd/nand.h>
LIB = $(obj)libnet.a
-COBJS-y += bootp.o
+COBJS-$(CONFIG_CMD_NET) += bootp.o
COBJS-$(CONFIG_CMD_DNS) += dns.o
-COBJS-y += eth.o
-COBJS-y += net.o
-COBJS-y += nfs.o
-COBJS-y += rarp.o
+COBJS-$(CONFIG_CMD_NET) += eth.o
+COBJS-$(CONFIG_CMD_NET) += net.o
+COBJS-$(CONFIG_CMD_NFS) += nfs.o
+COBJS-$(CONFIG_CMD_NET) += rarp.o
COBJS-$(CONFIG_CMD_SNTP) += sntp.o
-COBJS-y += tftp.o
+COBJS-$(CONFIG_CMD_NET) += tftp.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
#define BOOTP_VENDOR_MAGIC 0x63825363 /* RFC1048 Magic Cookie */
-#if defined(CONFIG_CMD_NET)
-
#define TIMEOUT 5000UL /* Milliseconds before trying BOOTP again */
#ifndef CONFIG_NET_RETRY_COUNT
# define TIMEOUT_COUNT 5 /* # of timeouts before giving up */
BootpRequest();
}
#endif /* CONFIG_CMD_DHCP */
-
-#endif /* CONFIG_CMD_NET */
#include <net.h>
#include <miiphy.h>
-#ifdef CONFIG_CMD_NET
void eth_parse_enetaddr(const char *addr, uchar *enetaddr)
{
char *end;
sprintf(enetvar, index ? "eth%daddr" : "ethaddr", index);
return eth_getenv_enetaddr(enetvar, enetaddr);
}
-#endif
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#ifdef CONFIG_NET_MULTI
/*
* CPU and board-specific Ethernet initializations. Aliased function
{
return (eth_current ? eth_current->name : "unknown");
}
-#elif defined(CONFIG_CMD_NET) && !defined(CONFIG_NET_MULTI)
+
+#else /* !CONFIG_NET_MULTI */
#warning Ethernet driver is deprecated. Please update to use CONFIG_NET_MULTI
#include "dns.h"
#endif
-#if defined(CONFIG_CMD_NET)
-
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_ARP_TIMEOUT
static int net_check_prereq (proto_t protocol);
+static int NetTryCount;
+
/**********************************************************************/
IPaddr_t NetArpWaitPacketIP;
NetArpWaitReplyIP = 0;
NetArpWaitTxPacket = NULL;
NetTxPacket = NULL;
+ NetTryCount = 1;
if (!NetTxPacket) {
int i;
void NetStartAgain (void)
{
char *nretry;
- int noretry = 0, once = 0;
+ int retry_forever = 0;
+ unsigned long retrycnt = 0;
+
+ nretry = getenv("netretry");
+ if (nretry) {
+ if (!strcmp(nretry, "yes"))
+ retry_forever = 1;
+ else if (!strcmp(nretry, "no"))
+ retrycnt = 0;
+ else if (!strcmp(nretry, "once"))
+ retrycnt = 1;
+ else
+ retrycnt = simple_strtoul(nretry, NULL, 0);
+ } else
+ retry_forever = 1;
- if ((nretry = getenv ("netretry")) != NULL) {
- noretry = (strcmp (nretry, "no") == 0);
- once = (strcmp (nretry, "once") == 0);
- }
- if (noretry) {
- eth_halt ();
+ if ((!retry_forever) && (NetTryCount >= retrycnt)) {
+ eth_halt();
NetState = NETLOOP_FAIL;
return;
}
+
+ NetTryCount++;
+
#ifndef CONFIG_NET_MULTI
NetSetTimeout (10000UL, startAgainTimeout);
NetSetHandler (startAgainHandler);
eth_init (gd->bd);
if (NetRestartWrap) {
NetRestartWrap = 0;
- if (NetDevExists && !once) {
+ if (NetDevExists) {
NetSetTimeout (10000UL, startAgainTimeout);
NetSetHandler (startAgainHandler);
} else {
*dst = '\0';
}
-#endif
-
#if defined(CONFIG_CMD_NFS) || defined(CONFIG_CMD_SNTP) || defined(CONFIG_CMD_DNS)
/*
* make port a little random, but use something trivial to compute
#include "nfs.h"
#include "bootp.h"
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_CMD_NFS)
-
#define HASHES_PER_LINE 65 /* Number of "loading" hashes per line */
#define NFS_RETRY_COUNT 30
#define NFS_TIMEOUT 2000UL
strcat (nfs_path, "/");
pathlen = strlen(nfs_path);
memcpy (nfs_path+pathlen, (uchar *)&(rpc_pkt.u.reply.data[2]), rlen);
- nfs_path[pathlen+rlen+1] = 0;
+ nfs_path[pathlen + rlen] = 0;
} else {
memcpy (nfs_path, (uchar *)&(rpc_pkt.u.reply.data[2]), rlen);
nfs_path[rlen] = 0;
static void
NfsTimeout (void)
{
- if ( NfsTimeoutCount++ < NFS_RETRY_COUNT ) {
+ if ( ++NfsTimeoutCount > NFS_RETRY_COUNT ) {
+ puts ("\nRetry count exceeded; starting again\n");
+ NetStartAgain ();
+ } else {
+ puts("T ");
+ NetSetTimeout (NFS_TIMEOUT, NfsTimeout);
NfsSend ();
- return;
}
- puts ("Timeout\n");
- NetState = NETLOOP_FAIL;
- return;
}
static void
NfsSend ();
}
-
-#endif
#include "rarp.h"
#include "tftp.h"
-#if defined(CONFIG_CMD_NET)
-
#define TIMEOUT 5000UL /* Milliseconds before trying BOOTP again */
#ifndef CONFIG_NET_RETRY_COUNT
# define TIMEOUT_COUNT 5 /* # of timeouts before giving up */
NetSetTimeout(TIMEOUT, RarpTimeout);
NetSetHandler(RarpHandler);
}
-
-#endif
#include "tftp.h"
#include "bootp.h"
-#if defined(CONFIG_CMD_NET)
-
#define WELL_KNOWN_PORT 69 /* Well known TFTP port # */
#define TIMEOUT 5000UL /* Millisecs to timeout for lost pkt */
#ifndef CONFIG_NET_RETRY_COUNT
ulong TftpRRQTimeoutMSecs = TIMEOUT;
int TftpRRQTimeoutCountMax = TIMEOUT_COUNT;
+enum {
+ TFTP_ERR_UNDEFINED = 0,
+ TFTP_ERR_FILE_NOT_FOUND = 1,
+ TFTP_ERR_ACCESS_DENIED = 2,
+ TFTP_ERR_DISK_FULL = 3,
+ TFTP_ERR_UNEXPECTED_OPCODE = 4,
+ TFTP_ERR_UNKNOWN_TRANSFER_ID = 5,
+ TFTP_ERR_FILE_ALREADY_EXISTS = 6,
+};
+
static IPaddr_t TftpServerIP;
static int TftpServerPort; /* The UDP port at their end */
static int TftpOurPort; /* The UDP port at our end */
case TFTP_ERROR:
printf ("\nTFTP error: '%s' (%d)\n",
pkt + 2, ntohs(*(ushort *)pkt));
- puts ("Starting again\n\n");
+
+ switch (ntohs(*(ushort *)pkt)) {
+ case TFTP_ERR_FILE_NOT_FOUND:
+ case TFTP_ERR_ACCESS_DENIED:
+ puts("Not retrying...\n");
+ eth_halt();
+ NetState = NETLOOP_FAIL;
+ break;
+ case TFTP_ERR_UNDEFINED:
+ case TFTP_ERR_DISK_FULL:
+ case TFTP_ERR_UNEXPECTED_OPCODE:
+ case TFTP_ERR_UNKNOWN_TRANSFER_ID:
+ case TFTP_ERR_FILE_ALREADY_EXISTS:
+ default:
+ puts("Starting again\n\n");
#ifdef CONFIG_MCAST_TFTP
- mcast_cleanup();
+ mcast_cleanup();
#endif
- NetStartAgain ();
+ NetStartAgain();
+ break;
+ }
break;
}
}
}
#endif /* Multicast TFTP */
-
-#endif
return res;
}
+/*
+ * Supply a default implementation for post_hotkeys_pressed() for boards
+ * without hotkey support. We always return 0 here, so that the
+ * long-running tests won't be started.
+ *
+ * Boards with hotkey support can override this weak default function
+ * by defining one in their board specific code.
+ */
+int __post_hotkeys_pressed(void)
+{
+ return 0; /* No hotkeys supported */
+}
+int post_hotkeys_pressed(void)
+ __attribute__((weak, alias("__post_hotkeys_pressed")));
+
+
void post_bootmode_init (void)
{
int bootmode = post_bootmode_get (0);
_depend: $(obj).depend
-$(obj).depend: $(src)Makefile $(TOPDIR)/config.mk $(SRCS)
+$(obj).depend: $(src)Makefile $(TOPDIR)/config.mk $(SRCS) $(HOSTSRCS)
@rm -f $@
@for f in $(SRCS); do \
g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \
- $(CC) -M $(HOSTCFLAGS) $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
+ $(CC) -M $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
done
+ @for f in $(HOSTSRCS); do \
+ g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \
+ $(HOSTCC) -M $(HOSTCPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
+ done
+
+$(HOSTOBJS): $(obj)%.o: %.c
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTCFLAGS_$(@F)) $(HOSTCFLAGS_$(BCURDIR)) -o $@ $< -c
+$(NOPEDOBJS): $(obj)%.o: %.c
+ $(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTCFLAGS_$(@F)) $(HOSTCFLAGS_$(BCURDIR)) -o $@ $< -c
#########################################################################
/ncp
/ubsha1
/inca-swap-bytes
+/*.exe
TOOLSUBDIRS =
-#
-# Mac OS X / Darwin's C preprocessor is Apple specific. It
-# generates numerous errors and warnings. We want to bypass it
-# and use GNU C's cpp. To do this we pass the -traditional-cpp
-# option to the compiler. Note that the -traditional-cpp flag
-# DOES NOT have the same semantics as GNU C's flag, all it does
-# is invoke the GNU preprocessor in stock ANSI/ISO C fashion.
-#
-# Apple's linker is similar, thanks to the new 2 stage linking
-# multiple symbol definitions are treated as errors, hence the
-# -multiply_defined suppress option to turn off this error.
-#
-
-HOSTCFLAGS = -Wall
-HOST_LDFLAGS =
-
-ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc)
-HOSTCFLAGS += -traditional-cpp
-HOST_LDFLAGS += -multiply_defined suppress
-else
-HOSTCFLAGS += -pedantic
-endif
-
-ifeq ($(HOSTOS),cygwin)
-HOSTCFLAGS += -ansi
-endif
-
#
# toolchains targeting win32 generate .exe files
#
# Source files located in the tools directory
OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o
-OBJ_FILES-y += default_image.o
-OBJ_FILES-$(CONFIG_ENV_IS_EMBEDDED) += envcrc.o
-OBJ_FILES-y += fit_image.o
+NOPED_OBJ_FILES-y += default_image.o
+OBJ_FILES-y += envcrc.o
+NOPED_OBJ_FILES-y += fit_image.o
OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o
-OBJ_FILES-y += kwbimage.o
-OBJ_FILES-y += mkimage.o
+NOPED_OBJ_FILES-y += kwbimage.o
+NOPED_OBJ_FILES-y += mkimage.o
OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
-OBJ_FILES-y += os_support.o
+NOPED_OBJ_FILES-y += os_support.o
OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
# Don't build by default
endif
# now $(obj) is defined
-SRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c))
-SRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c))
-SRCS += $(addprefix $(SRCTREE)/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c))
+HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c))
+HOSTSRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c))
+HOSTSRCS += $(addprefix $(SRCTREE)/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c))
BINS := $(addprefix $(obj),$(sort $(BIN_FILES-y)))
LIBFDT_OBJS := $(addprefix $(obj),$(LIBFDT_OBJ_FILES-y))
+HOSTOBJS := $(addprefix $(obj),$(OBJ_FILES-y))
+NOPEDOBJS := $(addprefix $(obj),$(NOPED_OBJ_FILES-y))
+
#
# Use native tools and options
# Define __KERNEL_STRICT_NAMES to prevent typedef overlaps
#
-CPPFLAGS = -idirafter $(SRCTREE)/include \
+HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \
-idirafter $(OBJTREE)/include2 \
-idirafter $(OBJTREE)/include \
-I $(SRCTREE)/libfdt \
-I $(SRCTREE)/tools \
-DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC \
-D__KERNEL_STRICT_NAMES
-CFLAGS = $(HOSTCFLAGS) $(CPPFLAGS) -O
-
-# No -pedantic switch to avoid libfdt compilation warnings
-FIT_CFLAGS = -Wall $(CPPFLAGS) -O
-AFLAGS = -D__ASSEMBLY__ $(CPPFLAGS)
-CC = $(HOSTCC)
-STRIP = $(HOSTSTRIP)
-MAKEDEPEND = makedepend
all: $(obj).depend $(BINS) $(LOGO-y) subdirs
$(obj)bin2header$(SFX): $(obj)bin2header.o
- $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
- $(STRIP) $@
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+ $(HOSTSTRIP) $@
$(obj)bmp_logo$(SFX): $(obj)bmp_logo.o
- $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
- $(STRIP) $@
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+ $(HOSTSTRIP) $@
$(obj)envcrc$(SFX): $(obj)crc32.o $(obj)env_embedded.o $(obj)envcrc.o $(obj)sha1.o
- $(CC) $(CFLAGS) -o $@ $^
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
$(obj)gen_eth_addr$(SFX): $(obj)gen_eth_addr.o
- $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
- $(STRIP) $@
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+ $(HOSTSTRIP) $@
$(obj)img2srec$(SFX): $(obj)img2srec.o
- $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
- $(STRIP) $@
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+ $(HOSTSTRIP) $@
$(obj)inca-swap-bytes$(SFX): $(obj)inca-swap-bytes.o
- $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
- $(STRIP) $@
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+ $(HOSTSTRIP) $@
$(obj)mkimage$(SFX): $(obj)crc32.o \
$(obj)default_image.o \
$(obj)os_support.o \
$(obj)sha1.o \
$(LIBFDT_OBJS)
- $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
- $(STRIP) $@
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+ $(HOSTSTRIP) $@
$(obj)mpc86x_clk$(SFX): $(obj)mpc86x_clk.o
- $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
- $(STRIP) $@
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+ $(HOSTSTRIP) $@
$(obj)ncb$(SFX): $(obj)ncb.o
- $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
- $(STRIP) $@
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+ $(HOSTSTRIP) $@
$(obj)ubsha1$(SFX): $(obj)os_support.o $(obj)sha1.o $(obj)ubsha1.o
- $(CC) $(CFLAGS) -o $@ $^
-
-# Some files complain if compiled with -pedantic, use FIT_CFLAGS
-$(obj)default_image.o: $(SRCTREE)/tools/default_image.c
- $(CC) -g $(FIT_CFLAGS) -c -o $@ $<
-
-$(obj)fit_image.o: $(SRCTREE)/tools/fit_image.c
- $(CC) -g $(FIT_CFLAGS) -c -o $@ $<
-
-$(obj)image.o: $(SRCTREE)/common/image.c
- $(CC) -g $(FIT_CFLAGS) -c -o $@ $<
-
-$(obj)kwbimage.o: $(SRCTREE)/tools/kwbimage.c
- $(CC) -g $(FIT_CFLAGS) -c -o $@ $<
-
-$(obj)mkimage.o: $(SRCTREE)/tools/mkimage.c
- $(CC) -g $(FIT_CFLAGS) -c -o $@ $<
-
-$(obj)os_support.o: $(SRCTREE)/tools/os_support.c
- $(CC) -g $(FIT_CFLAGS) -c -o $@ $<
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
# Some of the tool objects need to be accessed from outside the tools directory
$(obj)%.o: $(SRCTREE)/common/%.c
- $(CC) -g $(FIT_CFLAGS) -c -o $@ $<
+ $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
$(obj)%.o: $(SRCTREE)/lib_generic/%.c
- $(CC) -g $(CFLAGS) -c -o $@ $<
+ $(HOSTCC) -g $(HOSTCFLAGS) -c -o $@ $<
$(LIBFDT_OBJS):
- $(CC) -g $(FIT_CFLAGS) -c -o $@ $<
+ $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
subdirs:
ifeq ($(TOOLSUBDIRS),)
$(MAKE) \
HOSTOS=$(HOSTOS) \
HOSTARCH=$(HOSTARCH) \
- HOSTCFLAGS="$(HOSTCFLAGS)" \
- HOST_LDFLAGS="$(HOST_LDFLAGS)" \
-C $$dir || exit 1 ; \
done
endif
-CFLAGS += -Wall
+include $(TOPDIR)/config.mk
-all: easylogo
+all: $(obj)easylogo
+
+$(obj)easylogo: $(SRCTREE)/tools/easylogo/easylogo.c
+ $(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTLDFLAGS) -o $@ $^
clean:
- rm -f easylogo *.o
+ rm -f $(obj)easylogo
.PHONY: all clean
return (EXIT_SUCCESS);
}
-static void fit_set_header (void *ptr, struct stat *sbuf, int ifd,
- struct mkimage_params *params)
-{
- uint32_t checksum;
-
- image_header_t * hdr = (image_header_t *)ptr;
-
- checksum = crc32 (0,
- (const unsigned char *)(ptr +
- sizeof(image_header_t)),
- sbuf->st_size - sizeof(image_header_t));
-
- /* Build new header */
- image_set_magic (hdr, IH_MAGIC);
- image_set_time (hdr, sbuf->st_mtime);
- image_set_size (hdr, sbuf->st_size - sizeof(image_header_t));
- image_set_load (hdr, params->addr);
- image_set_ep (hdr, params->ep);
- image_set_dcrc (hdr, checksum);
- image_set_os (hdr, params->os);
- image_set_arch (hdr, params->arch);
- image_set_type (hdr, params->type);
- image_set_comp (hdr, params->comp);
-
- image_set_name (hdr, params->imagename);
-
- checksum = crc32 (0, (const unsigned char *)hdr,
- sizeof(image_header_t));
-
- image_set_hcrc (hdr, checksum);
-}
-
static int fit_check_params (struct mkimage_params *params)
{
return ((params->dflag && (params->fflag || params->lflag)) ||
.print_header = fit_print_contents,
.check_image_type = fit_check_image_types,
.fflag_handle = fit_handle_file,
- .set_header = fit_set_header,
+ .set_header = NULL, /* FIT images use DTB header */
.check_params = fit_check_params,
};
COBJS = gdbsend.o gdbcont.o error.o remote.o serial.o
-OBJS := $(addprefix $(obj),$(COBJS))
-SRCS := $(COBJS:.o=.c)
+HOSTOBJS := $(addprefix $(obj),$(COBJS))
+HOSTSRCS := $(COBJS:.o=.c)
BINS := $(addprefix $(obj),$(BINS))
#
# Use native tools and options
#
-CPPFLAGS = -I$(BFD_ROOT_DIR)/include
-CFLAGS = $(HOSTCFLAGS) -O $(CPPFLAGS)
-CC = $(HOSTCC)
-MAKEDEPEND = makedepend
+HOSTCPPFLAGS = -I$(BFD_ROOT_DIR)/include
HOSTOS := $(shell uname -s | sed -e 's/\([Cc][Yy][Gg][Ww][Ii][Nn]\).*/cygwin/')
all: $(obj).depend $(BINS)
$(obj)gdbsend: $(obj)gdbsend.o $(obj)error.o $(obj)remote.o $(obj)serial.o
- $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
$(obj)gdbcont: $(obj)gdbcont.o $(obj)error.o $(obj)remote.o $(obj)serial.o
- $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
clean:
- rm -f $(OBJS)
+ rm -f $(HOSTOBJS)
distclean: clean
rm -f $(BINS) $(obj)core $(obj)*.bak $(obj).depend
|*************************************************************************/
#include "os_support.h"
+#include <stdbool.h>
#include <stddef.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <errno.h>
-/*************************************************************************
-| DEFINES
-|*************************************************************************/
-
-#define FALSE 0
-#define TRUE 1
-
-/*************************************************************************
-| MACROS
-|*************************************************************************/
-
-/*************************************************************************
-| TYPEDEFS
-|*************************************************************************/
-
-typedef uint8_t CHAR;
-typedef uint8_t BYTE;
-typedef uint16_t WORD;
-typedef uint32_t DWORD;
-typedef int BOOL;
-
-/*************************************************************************
-| LOCALS
-|*************************************************************************/
-
-/*************************************************************************
-| PROTOTYPES
-|*************************************************************************/
-
-static char *ExtractHex(DWORD *value, char *getPtr);
-static char *ExtractDecimal(DWORD *value, char *getPtr);
-static void ExtractNumber(DWORD *value, char *getPtr);
-static BYTE *ExtractWord(WORD *value, BYTE *buffer);
-static BYTE *ExtractLong(DWORD *value, BYTE *buffer);
-static BYTE *ExtractBlock(WORD count, BYTE *data, BYTE *buffer);
-static char *WriteHex(char *pa, BYTE value, WORD *pCheckSum);
-static char *BuildSRecord(char *pa, WORD sType, DWORD addr,
- const BYTE *data, int nCount);
-static void ConvertELF(char *fileName, DWORD loadOffset);
-int main(int argc, char *argv[]);
-
/*************************************************************************
| FUNCTIONS
|*************************************************************************/
-static char* ExtractHex (DWORD* value, char* getPtr)
+static char* ExtractHex (uint32_t* value, char* getPtr)
{
- DWORD num;
- DWORD digit;
- BYTE c;
+ uint32_t num;
+ uint32_t digit;
+ uint8_t c;
while (*getPtr == ' ') getPtr++;
num = 0;
for (;;) {
c = *getPtr;
- if ((c >= '0') && (c <= '9')) digit = (DWORD)(c - '0');
- else if ((c >= 'A') && (c <= 'F')) digit = (DWORD)(c - 'A' + 10);
- else if ((c >= 'a') && (c <= 'f')) digit = (DWORD)(c - 'a' + 10);
+ if ((c >= '0') && (c <= '9')) digit = (uint32_t)(c - '0');
+ else if ((c >= 'A') && (c <= 'F')) digit = (uint32_t)(c - 'A' + 10);
+ else if ((c >= 'a') && (c <= 'f')) digit = (uint32_t)(c - 'a' + 10);
else break;
num <<= 4;
num += digit;
return getPtr;
} /* ExtractHex */
-static char* ExtractDecimal (DWORD* value, char* getPtr)
+static char* ExtractDecimal (uint32_t* value, char* getPtr)
{
- DWORD num;
- DWORD digit;
- BYTE c;
+ uint32_t num;
+ uint32_t digit;
+ uint8_t c;
while (*getPtr == ' ') getPtr++;
num = 0;
for (;;) {
c = *getPtr;
- if ((c >= '0') && (c <= '9')) digit = (DWORD)(c - '0');
+ if ((c >= '0') && (c <= '9')) digit = (uint32_t)(c - '0');
else break;
num *= 10;
num += digit;
} /* ExtractDecimal */
-static void ExtractNumber (DWORD* value, char* getPtr)
+static void ExtractNumber (uint32_t* value, char* getPtr)
{
- BOOL neg = FALSE;;
+ bool neg = false;;
while (*getPtr == ' ') getPtr++;
if (*getPtr == '-') {
- neg = TRUE;
+ neg = true;
getPtr++;
} /* if */
if ((*getPtr == '0') && ((*(getPtr+1) == 'x') || (*(getPtr+1) == 'X'))) {
} /* ExtractNumber */
-static BYTE* ExtractWord(WORD* value, BYTE* buffer)
+static uint8_t* ExtractWord(uint16_t* value, uint8_t* buffer)
{
- WORD x;
- x = (WORD)*buffer++;
- x = (x<<8) + (WORD)*buffer++;
+ uint16_t x;
+ x = (uint16_t)*buffer++;
+ x = (x<<8) + (uint16_t)*buffer++;
*value = x;
return buffer;
} /* ExtractWord */
-static BYTE* ExtractLong(DWORD* value, BYTE* buffer)
+static uint8_t* ExtractLong(uint32_t* value, uint8_t* buffer)
{
- DWORD x;
- x = (DWORD)*buffer++;
- x = (x<<8) + (DWORD)*buffer++;
- x = (x<<8) + (DWORD)*buffer++;
- x = (x<<8) + (DWORD)*buffer++;
+ uint32_t x;
+ x = (uint32_t)*buffer++;
+ x = (x<<8) + (uint32_t)*buffer++;
+ x = (x<<8) + (uint32_t)*buffer++;
+ x = (x<<8) + (uint32_t)*buffer++;
*value = x;
return buffer;
} /* ExtractLong */
-static BYTE* ExtractBlock(WORD count, BYTE* data, BYTE* buffer)
+static uint8_t* ExtractBlock(uint16_t count, uint8_t* data, uint8_t* buffer)
{
while (count--) *data++ = *buffer++;
return buffer;
} /* ExtractBlock */
-static char* WriteHex(char* pa, BYTE value, WORD* pCheckSum)
+static char* WriteHex(char* pa, uint8_t value, uint16_t* pCheckSum)
{
- WORD temp;
+ uint16_t temp;
static char ByteToHex[] = "0123456789ABCDEF";
}
-static char* BuildSRecord(char* pa, WORD sType, DWORD addr,
- const BYTE* data, int nCount)
+static char* BuildSRecord(char* pa, uint16_t sType, uint32_t addr,
+ const uint8_t* data, int nCount)
{
- WORD addrLen;
- WORD sRLen;
- WORD checkSum;
- WORD i;
+ uint16_t addrLen;
+ uint16_t sRLen;
+ uint16_t checkSum;
+ uint16_t i;
switch (sType) {
case 0:
*pa++ = (char)(sType + '0');
sRLen = addrLen + nCount + 1;
checkSum = 0;
- pa = WriteHex(pa, (BYTE)sRLen, &checkSum);
+ pa = WriteHex(pa, (uint8_t)sRLen, &checkSum);
/* Write address field */
for (i = 1; i <= addrLen; i++) {
- pa = WriteHex(pa, (BYTE)(addr >> (8 * (addrLen - i))), &checkSum);
+ pa = WriteHex(pa, (uint8_t)(addr >> (8 * (addrLen - i))), &checkSum);
} /* for */
/* Write code/data fields */
/* Write checksum field */
checkSum = ~checkSum;
- pa = WriteHex(pa, (BYTE)checkSum, &checkSum);
+ pa = WriteHex(pa, (uint8_t)checkSum, &checkSum);
*pa++ = '\0';
return pa;
}
-static void ConvertELF(char* fileName, DWORD loadOffset)
+static void ConvertELF(char* fileName, uint32_t loadOffset)
{
FILE* file;
int i;
int rxCount;
- BYTE rxBlock[1024];
- DWORD loadSize;
- DWORD firstAddr;
- DWORD loadAddr;
- DWORD loadDiff = 0;
+ uint8_t rxBlock[1024];
+ uint32_t loadSize;
+ uint32_t firstAddr;
+ uint32_t loadAddr;
+ uint32_t loadDiff = 0;
Elf32_Ehdr elfHeader;
Elf32_Shdr sectHeader[32];
- BYTE* getPtr;
+ uint8_t* getPtr;
char srecLine[128];
char *hdr_name;
getPtr = ExtractBlock(sizeof elfHeader.e_ident, elfHeader.e_ident, rxBlock);
getPtr = ExtractWord(&elfHeader.e_type, getPtr);
getPtr = ExtractWord(&elfHeader.e_machine, getPtr);
- getPtr = ExtractLong((DWORD *)&elfHeader.e_version, getPtr);
- getPtr = ExtractLong((DWORD *)&elfHeader.e_entry, getPtr);
- getPtr = ExtractLong((DWORD *)&elfHeader.e_phoff, getPtr);
- getPtr = ExtractLong((DWORD *)&elfHeader.e_shoff, getPtr);
- getPtr = ExtractLong((DWORD *)&elfHeader.e_flags, getPtr);
+ getPtr = ExtractLong((uint32_t *)&elfHeader.e_version, getPtr);
+ getPtr = ExtractLong((uint32_t *)&elfHeader.e_entry, getPtr);
+ getPtr = ExtractLong((uint32_t *)&elfHeader.e_phoff, getPtr);
+ getPtr = ExtractLong((uint32_t *)&elfHeader.e_shoff, getPtr);
+ getPtr = ExtractLong((uint32_t *)&elfHeader.e_flags, getPtr);
getPtr = ExtractWord(&elfHeader.e_ehsize, getPtr);
getPtr = ExtractWord(&elfHeader.e_phentsize, getPtr);
getPtr = ExtractWord(&elfHeader.e_phnum, getPtr);
fseek(file, elfHeader.e_shoff, SEEK_SET);
for (i = 0; i < elfHeader.e_shnum; i++) {
rxCount = fread(rxBlock, 1, sizeof sectHeader[0], file);
- getPtr = ExtractLong((DWORD *)§Header[i].sh_name, rxBlock);
- getPtr = ExtractLong((DWORD *)§Header[i].sh_type, getPtr);
- getPtr = ExtractLong((DWORD *)§Header[i].sh_flags, getPtr);
- getPtr = ExtractLong((DWORD *)§Header[i].sh_addr, getPtr);
- getPtr = ExtractLong((DWORD *)§Header[i].sh_offset, getPtr);
- getPtr = ExtractLong((DWORD *)§Header[i].sh_size, getPtr);
- getPtr = ExtractLong((DWORD *)§Header[i].sh_link, getPtr);
- getPtr = ExtractLong((DWORD *)§Header[i].sh_info, getPtr);
- getPtr = ExtractLong((DWORD *)§Header[i].sh_addralign, getPtr);
- getPtr = ExtractLong((DWORD *)§Header[i].sh_entsize, getPtr);
+ getPtr = ExtractLong((uint32_t *)§Header[i].sh_name, rxBlock);
+ getPtr = ExtractLong((uint32_t *)§Header[i].sh_type, getPtr);
+ getPtr = ExtractLong((uint32_t *)§Header[i].sh_flags, getPtr);
+ getPtr = ExtractLong((uint32_t *)§Header[i].sh_addr, getPtr);
+ getPtr = ExtractLong((uint32_t *)§Header[i].sh_offset, getPtr);
+ getPtr = ExtractLong((uint32_t *)§Header[i].sh_size, getPtr);
+ getPtr = ExtractLong((uint32_t *)§Header[i].sh_link, getPtr);
+ getPtr = ExtractLong((uint32_t *)§Header[i].sh_info, getPtr);
+ getPtr = ExtractLong((uint32_t *)§Header[i].sh_addralign, getPtr);
+ getPtr = ExtractLong((uint32_t *)§Header[i].sh_entsize, getPtr);
if (rxCount != sizeof sectHeader[0]) {
fclose(file);
fprintf (stderr, "*** illegal file format\n");
++hdr_name;
}
/* write start record */
- (void)BuildSRecord(srecLine, 0, 0, (BYTE *)hdr_name, strlen(hdr_name));
+ (void)BuildSRecord(srecLine, 0, 0, (uint8_t *)hdr_name, strlen(hdr_name));
printf("%s\r\n",srecLine);
/* write data records */
int main( int argc, char *argv[ ])
{
- DWORD offset;
+ uint32_t offset;
if (argc == 2) {
ConvertELF(argv[1], 0);
include $(TOPDIR)/config.mk
-HOSTCFLAGS = -Wall -pedantic
-
# Generated executable files
BIN_FILES-y += imls
LIBFDT_OBJS := $(addprefix $(obj),$(LIBFDT_OBJ_FILES-y))
#
-# Use native tools and options
+# Compile for a hosted environment on the target
# Define __KERNEL_STRICT_NAMES to prevent typedef overlaps
#
-CPPFLAGS = -idirafter $(SRCTREE)/include \
+HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \
-idirafter $(OBJTREE)/include2 \
-idirafter $(OBJTREE)/include \
-I $(SRCTREE)/libfdt \
-I $(SRCTREE)/tools \
-DUSE_HOSTCC -D__KERNEL_STRICT_NAMES
-CFLAGS = $(HOSTCFLAGS) $(CPPFLAGS) -O
-
-# No -pedantic switch to avoid libfdt compilation warnings
-FIT_CFLAGS = -Wall $(CPPFLAGS) -O
-
-CC = $(CROSS_COMPILER)gcc
-STRIP = $(CROSS_COMPILER)strip
ifeq ($(MTD_VERSION),old)
-CPPFLAGS += -DMTD_OLD
+HOSTCPPFLAGS += -DMTD_OLD
endif
all: $(BINS)
$(obj)imls: $(obj)imls.o $(obj)crc32.o $(obj)image.o $(obj)md5.o \
$(obj)sha1.o $(LIBFDT_OBJS)
- $(CC) $(CFLAGS) -o $@ $^
+ $(CC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
$(STRIP) $@
# Some files complain if compiled with -pedantic, use FIT_CFLAGS
$(obj)image.o: $(SRCTREE)/common/image.c
- $(CC) -g $(FIT_CFLAGS) -c -o $@ $<
+ $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-$(obj)imls.o: imls.c
- $(CC) -g $(FIT_CFLAGS) -c -o $@ $<
+$(obj)imls.o: $(SRCTREE)/tools/imls/imls.c
+ $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
# Some of the tool objects need to be accessed from outside the tools/imls directory
$(obj)%.o: $(SRCTREE)/common/%.c
- $(CC) -g $(FIT_CFLAGS) -c -o $@ $<
+ $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
$(obj)%.o: $(SRCTREE)/lib_generic/%.c
- $(CC) -g $(CFLAGS) -c -o $@ $<
+ $(CC) -g $(HOSTCFLAGS) -c -o $@ $<
$(obj)%.o: $(SRCTREE)/libfdt/%.c
- $(CC) -g $(FIT_CFLAGS) -c -o $@ $<
+ $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
clean:
rm -rf *.o imls
#include "mingw_support.h"
#include <stdio.h>
#include <stdint.h>
+#include <string.h>
#include <errno.h>
+#include <assert.h>
#include <io.h>
int fsync(int fd)
return 0;
}
+
+/* Reentrant string tokenizer. Generic version.
+ Copyright (C) 1991,1996-1999,2001,2004,2007 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */
+
+/* Parse S into tokens separated by characters in DELIM.
+ If S is NULL, the saved pointer in SAVE_PTR is used as
+ the next starting point. For example:
+ char s[] = "-abc-=-def";
+ char *sp;
+ x = strtok_r(s, "-", &sp); // x = "abc", sp = "=-def"
+ x = strtok_r(NULL, "-=", &sp); // x = "def", sp = NULL
+ x = strtok_r(NULL, "=", &sp); // x = NULL
+ // s = "abc\0-def\0"
+*/
+char *strtok_r(char *s, const char *delim, char **save_ptr)
+{
+ char *token;
+
+ if (s == NULL)
+ s = *save_ptr;
+
+ /* Scan leading delimiters. */
+ s += strspn(s, delim);
+ if (*s == '\0') {
+ *save_ptr = s;
+ return NULL;
+ }
+
+ /* Find the end of the token. */
+ token = s;
+ s = strpbrk (token, delim);
+ if (s == NULL) {
+ /* This token finishes the string. */
+ *save_ptr = memchr(token, '\0', strlen(token));
+ } else {
+ /* Terminate the token and make *SAVE_PTR point past it. */
+ *s = '\0';
+ *save_ptr = s + 1;
+ }
+ return token;
+}
+
+/* getline.c -- Replacement for GNU C library function getline
+
+Copyright (C) 1993, 1996, 2001, 2002 Free Software Foundation, Inc.
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License as
+published by the Free Software Foundation; either version 2 of the
+License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* Written by Jan Brittenson, bson@gnu.ai.mit.edu. */
+
+/* Always add at least this many bytes when extending the buffer. */
+#define MIN_CHUNK 64
+
+/* Read up to (and including) a TERMINATOR from STREAM into *LINEPTR
+ + OFFSET (and null-terminate it). *LINEPTR is a pointer returned from
+ malloc (or NULL), pointing to *N characters of space. It is realloc'd
+ as necessary. Return the number of characters read (not including the
+ null terminator), or -1 on error or EOF.
+ NOTE: There is another getstr() function declared in <curses.h>. */
+static int getstr(char **lineptr, size_t *n, FILE *stream,
+ char terminator, size_t offset)
+{
+ int nchars_avail; /* Allocated but unused chars in *LINEPTR. */
+ char *read_pos; /* Where we're reading into *LINEPTR. */
+ int ret;
+
+ if (!lineptr || !n || !stream)
+ return -1;
+
+ if (!*lineptr) {
+ *n = MIN_CHUNK;
+ *lineptr = malloc(*n);
+ if (!*lineptr)
+ return -1;
+ }
+
+ nchars_avail = *n - offset;
+ read_pos = *lineptr + offset;
+
+ for (;;) {
+ register int c = getc(stream);
+
+ /* We always want at least one char left in the buffer, since we
+ always (unless we get an error while reading the first char)
+ NUL-terminate the line buffer. */
+
+ assert(*n - nchars_avail == read_pos - *lineptr);
+ if (nchars_avail < 2) {
+ if (*n > MIN_CHUNK)
+ *n *= 2;
+ else
+ *n += MIN_CHUNK;
+
+ nchars_avail = *n + *lineptr - read_pos;
+ *lineptr = realloc(*lineptr, *n);
+ if (!*lineptr)
+ return -1;
+ read_pos = *n - nchars_avail + *lineptr;
+ assert(*n - nchars_avail == read_pos - *lineptr);
+ }
+
+ if (c == EOF || ferror (stream)) {
+ /* Return partial line, if any. */
+ if (read_pos == *lineptr)
+ return -1;
+ else
+ break;
+ }
+
+ *read_pos++ = c;
+ nchars_avail--;
+
+ if (c == terminator)
+ /* Return the line. */
+ break;
+ }
+
+ /* Done - NUL terminate and return the number of chars read. */
+ *read_pos = '\0';
+
+ ret = read_pos - (*lineptr + offset);
+ return ret;
+}
+
+int getline (char **lineptr, size_t *n, FILE *stream)
+{
+ return getstr(lineptr, n, stream, '\n', 0);
+}
int fsync(int fd);
void *mmap(void *, size_t, int, int, int, int);
int munmap(void *, size_t);
+char *strtok_r(char *s, const char *delim, char **save_ptr);
+int getline(char **lineptr, size_t *n, FILE *stream);
#endif /* __MINGW_SUPPORT_H_ */
case 'f':
if (--argc <= 0)
usage ();
+ /*
+ * The flattened image tree (FIT) format
+ * requires a flattened device tree image type
+ */
+ params.type = IH_TYPE_FLATDT;
params.datafile = *++argv;
params.fflag = 1;
goto NXTARG;
params.imagefile = *argv;
- if (!params.fflag){
- if (params.lflag) {
- ifd = open (params.imagefile, O_RDONLY|O_BINARY);
- } else {
- ifd = open (params.imagefile,
- O_RDWR|O_CREAT|O_TRUNC|O_BINARY, 0666);
- }
+ if (params.fflag){
+ if (tparams->fflag_handle)
+ /*
+ * in some cases, some additional processing needs
+ * to be done if fflag is defined
+ *
+ * For ex. fit_handle_file for Fit file support
+ */
+ retval = tparams->fflag_handle(¶ms);
- if (ifd < 0) {
- fprintf (stderr, "%s: Can't open %s: %s\n",
- params.cmdname, params.imagefile,
- strerror(errno));
- exit (EXIT_FAILURE);
- }
+ if (retval != EXIT_SUCCESS)
+ exit (retval);
+ }
+
+ if (params.lflag || params.fflag) {
+ ifd = open (params.imagefile, O_RDONLY|O_BINARY);
+ } else {
+ ifd = open (params.imagefile,
+ O_RDWR|O_CREAT|O_TRUNC|O_BINARY, 0666);
+ }
+
+ if (ifd < 0) {
+ fprintf (stderr, "%s: Can't open %s: %s\n",
+ params.cmdname, params.imagefile,
+ strerror(errno));
+ exit (EXIT_FAILURE);
}
- if (params.lflag) {
+ if (params.lflag || params.fflag) {
/*
* list header information of existing image
*/
(void) munmap((void *)ptr, sbuf.st_size);
(void) close (ifd);
- exit (retval);
- } else if (params.fflag) {
- if (tparams->fflag_handle)
- /*
- * in some cases, some additional processing needs
- * to be done if fflag is defined
- *
- * For ex. fit_handle_file for Fit file support
- */
- retval = tparams->fflag_handle(¶ms);
-
exit (retval);
}
projects / karo-tx-uboot.git / commitdiff