arm: mx6: fix definition of MXC_CCM_CSCDR2_IPU._DI._PRE_CLK_SEL_MASK

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 261a7b38d0c3a4c52d381833a33f64f4b1775322..ce465c617904c1ac1ee1c79bd3a898124c744f92 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -318,13 +318,13 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK                        (0x7 << MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET)
 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET              0
 #else
-#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK      (0x7 << MXC_CCM_CHSCCDR_DI1_PRE_CLK_SEL_OFFSET)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK      (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET)
 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET    15
 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK             (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET)
 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET           12
 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK          (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET)
 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET                9
-#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK      (0x7 << MXC_CCM_CHSCCDR_DI0_PRE_CLK_SEL_OFFSET)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK      (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET)
 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET    6
 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK             (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET           3
@@ -332,18 +332,22 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET                0
 #endif
 
+#define CHSCCDR_CLK_SEL_LDB_DI0                                3
+#define CHSCCDR_PODF_DIVIDE_BY_3                       2
+#define CHSCCDR_IPU_PRE_CLK_540M_PFD                   5
+
 /* Define the bits in register CSCDR2 */
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK             (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET           19
 /* All IPU2_DI1 are LCDIF1 on MX6SX */
-#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK       (0x7 << MXC_CCM_CSCDR2_DI1_PRE_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK       (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET     15
 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK              (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET)
 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET            12
 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK           (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET         9
 /* All IPU2_DI0 are LCDIF2 on MX6SX */
-#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK       (0x7 << MXC_CCM_CSCDR2_DI0_PRE_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK       (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET     6
 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK              (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET)
 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET            3