The current SDRAM timing setup is broken.
Adjust the timing parameters to match the need of the SDRAM in use.
# bit29-26: zero
# bit31-30: 01
-DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
# bit 4: 0=addr/cmd in smame cycle
# bit 5: 0=clk is driven during self refresh, we don't care for APX
# bit 6: 0=use recommended falling edge of clk for addr/cmd
# bit30-28: 3 required
# bit31: 0=no additional STARTBURST delay
-DATA 0xFFD01408 0x1101355b # DDR Timing (Low) (active cycles value +1)
+DATA 0xFFD01408 0x33136552 # DDR Timing (Low) (active cycles value +1)
# bit3-0: TRAS lsbs
# bit7-4: TRCD
# bit11- 8: TRP
# bit27-24: TRRD
# bit31-28: TRTP
-DATA 0xFFD0140C 0x00000034 # DDR Timing (High)
+DATA 0xFFD0140C 0x0000004e # DDR Timing (High)
# bit6-0: TRFC
# bit8-7: TR2R
# bit10-9: TR2W