1 #ifndef CYGONCE_FSL_BOARD_H
2 #define CYGONCE_FSL_BOARD_H
4 //=============================================================================
6 // Platform specific support (register layout, etc)
8 //=============================================================================
9 //####ECOSGPLCOPYRIGHTBEGIN####
10 // -------------------------------------------
11 // This file is part of eCos, the Embedded Configurable Operating System.
12 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
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38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //===========================================================================
43 #include <cyg/hal/hal_soc.h> // Hardware definitions
45 #define CPLD_SPI_BASE CSPI1_BASE_ADDR
46 #define CPLD_SPI_CHIP_SELECT_NO SPI_CTRL_CS0
47 #define CPLD_SPI_CTRL_MODE_MASTER SPI_CTRL_MODE_MASTER
49 #define PBC_BASE CS5_BASE_ADDR /* Peripheral Bus Controller */
50 #define PBC_LED_CTRL (PBC_BASE + 0x20000)
51 #define PBC_SB_STAT (PBC_BASE + 0x20008)
52 #define PBC_ID_AAAA (PBC_BASE + 0x20040)
53 #define PBC_ID_5555 (PBC_BASE + 0x20048)
54 #define PBC_VERSION (PBC_BASE + 0x20050)
55 #define PBC_ID_CAFE (PBC_BASE + 0x20058)
56 #define PBC_INT_STAT (PBC_BASE + 0x20010)
57 #define PBC_INT_MASK (PBC_BASE + 0x20038)
58 #define PBC_INT_REST (PBC_BASE + 0x20020)
59 #define PBC_SW_RESET (PBC_BASE + 0x20060)
60 #define BOARD_CS_LAN_BASE (PBC_BASE + 0x300)
61 #define BOARD_CS_UART_BASE (PBC_BASE + 0x8000)
63 #define BOARD_FLASH_START CS0_BASE_ADDR
64 #define REDBOOT_IMAGE_SIZE 0x40000
66 #define SDRAM_BASE_ADDR CSD0_BASE_ADDR
67 #define SDRAM_SIZE 0x08000000
68 #define RAM_BANK0_BASE CSD0_BASE_ADDR
69 #define RAM_BANK1_BASE CSD1_BASE_ADDR
71 #ifdef CYGPKG_DEVS_MXC_SPI
72 #define LAN92XX_REG_READ(reg_offset) ( \
73 cpld_reg_xfer(reg_offset, 0x0, 1) | \
74 (cpld_reg_xfer(reg_offset + 0x2, 0x0, 1) << 16))
76 #define LAN92XX_REG_WRITE(reg_offset, val) do {\
77 cpld_reg_xfer(reg_offset, val, 0); \
78 (cpld_reg_xfer(reg_offset + 0x2, (val >> 16), 0)); } while (0)
81 #define FEC_PHY_ADDR 0x1
84 #define LED_IS_ON(n) ((readw(PBC_LED_CTRL) & (1<<(n))) != 0)
85 #define TURN_LED_ON(n) writew((readw(PBC_LED_CTRL)|(1<<(n))), PBC_LED_CTRL)
86 #define TURN_LED_OFF(n) writew((readw(PBC_LED_CTRL)&(~(1<<(n)))), PBC_LED_CTRL)
88 #define BOARD_DEBUG_LED(n) \
90 if (n >= 0 && n < LED_MAX_NUM) { \
98 #endif /* CYGONCE_FSL_BOARD_H */