packages/hal/arm/mx25/var/v2_0/include/hal_cache.h

   1 #ifndef CYGONCE_HAL_CACHE_H
   2 #define CYGONCE_HAL_CACHE_H
   3
   4 //=============================================================================
   5 //
   6 //      hal_cache.h
   7 //
   8 //      HAL cache control API
   9 //
  10 //=============================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
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  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //=============================================================================
  44
  45 #include <cyg/infra/cyg_type.h>
  46 #include <cyg/hal/hal_soc.h>         // Variant specific hardware definitions
  47
  48 //-----------------------------------------------------------------------------
  49 // Cache dimensions
  50
  51 // Data cache
  52 #define HAL_DCACHE_SIZE                 0x4000    // 16KB Size of data cache in bytes
  53 #define HAL_DCACHE_LINE_SIZE            32    // Size of a data cache line
  54 #define HAL_DCACHE_WAYS                 64    // Associativity of the cache
  55
  56 // Instruction cache
  57 #define HAL_ICACHE_SIZE                 0x4000    // Size of cache in bytes
  58 #define HAL_ICACHE_LINE_SIZE            32    // Size of a cache line
  59 #define HAL_ICACHE_WAYS                 64    // Associativity of the cache
  60
  61 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
  62 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
  63
  64 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
  65 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP  0x20
  66 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x100
  67 //-----------------------------------------------------------------------------
  68 // Global control of data cache
  69
  70 // Enable the data cache
  71 #define HAL_DCACHE_ENABLE()                                             \
  72 CYG_MACRO_START                                                         \
  73     asm volatile (                                                      \
  74         "mrc  p15,0,r1,c1,c0,0;"                                        \
  75         "orr  r1,r1,#0x0007;" /* enable DCache (also ensures    */      \
  76                               /* the MMU, alignment faults, and */      \
  77         "mcr  p15,0,r1,c1,c0,0"                                         \
  78         :                                                               \
  79         :                                                               \
  80         : "r1" /* Clobber list */                                       \
  81         );                                                              \
  82 CYG_MACRO_END
  83
  84 // Disable the data cache
  85 #define HAL_DCACHE_DISABLE()    \
  86 CYG_MACRO_START                                                         \
  87     asm volatile (                                                      \
  88         "mov    r1,#0;"                                                 \
  89         "mcr  p15,0,r1,c7,c6,0;" /* clear data cache */                  \
  90         "mrc  p15,0,r1,c1,c0,0;"                                        \
  91         "bic  r1,r1,#0x0004;" /* disable DCache  */                     \
  92                               /* but not MMU and alignment faults */    \
  93         "mcr  p15,0,r1,c1,c0,0"                                        \
  94         :                                                               \
  95         :                                                               \
  96         : "r1" /* Clobber list */                                       \
  97         );                                                              \
  98 CYG_MACRO_END
  99
 100 // Sync  data cache in range
 101 #define HAL_DCACHE_SYNC_RANGE(start, end)                               \
 102 CYG_MACRO_START                                                         \
 103         asm volatile (                                                  \
 104                 "nop;"                                                  \
 105                 "nop;"                                                  \
 106                 "nop;"                                                  \
 107                 "nop;"                                                  \
 108                 "nop;"                                                  \
 109                 "nop;"                                                  \
 110                 "       bic %0, %0, %3;"                                \
 111                 "       add %1, %1, %3;"                                \
 112                 "       bic %1, %1, %3;"                                \
 113                 "1:     cmp %1, %0;"                                    \
 114                 "       mcrhi p15, 0, %0, c7, c14, 1;"                  \
 115                 "       addhi %0, %0, %2;"                              \
 116                 "       bhi     1b;"                                    \
 117                 "       mov %0, #0;"                                    \
 118                 "       mcr p15, 0, %0, c7, c10, 4"                     \
 119                 :                                                       \
 120                 :"r"(start), "r"(end),                          \
 121                         "I"(HAL_DCACHE_LINE_SIZE),                      \
 122                         "I"(HAL_DCACHE_LINE_SIZE-1)                     \
 123         );                                                              \
 124 CYG_MACRO_END
 125
 126 // Invalidate data cache in range
 127 #define HAL_DCACHE_INVALID_RANGE(start, end)                            \
 128 CYG_MACRO_START                                                         \
 129         asm volatile (                                                  \
 130                 "       bic %0, %0, %3;"                                \
 131                 "       add %1, %1, %3;"                                \
 132                 "       bic %1, %1, %3;"                                \
 133                 "1:     mcr p15, 0, %0, c7, c6, 1;"                     \
 134                 "       add %0, %0, %2;"                                \
 135                 "       cmp %0, %1;"                                    \
 136                 "       blo 1b"                 \
 137                 :                                                       \
 138                 :"r"(start), "r"(end),                                  \
 139                         "I"(HAL_DCACHE_LINE_SIZE),                      \
 140                         "I"(HAL_DCACHE_LINE_SIZE-1)                     \
 141         );                                                              \
 142 CYG_MACRO_END
 143
 144 // Invalidate the entire cache
 145 #define HAL_DCACHE_INVALIDATE_ALL()                                     \
 146 CYG_MACRO_START  /* this macro can discard dirty cache lines. */        \
 147     asm volatile (                                                      \
 148         "mov    r0,#0;"                                                 \
 149         "mcr    p15,0,r0,c7,c6,0;" /* flush d-cache */                  \
 150         "mcr    p15,0,r0,c8,c7,0;" /* flush i+d-TLBs */                 \
 151         :                                                               \
 152         :                                                               \
 153         : "r0","memory" /* clobber list */);                            \
 154 CYG_MACRO_END
 155
 156 // Synchronize the contents of the cache with memory.
 157 // using ARM9's defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX)
 158 #if 1
 159 #define HAL_DCACHE_SYNC()                                               \
 160 CYG_MACRO_START                                                         \
 161     asm volatile (                                                      \
 162         "nop; "                                                \
 163         "nop; "                                                \
 164         "nop; "                                                \
 165         "nop; "                                                \
 166         "nop; "                                                \
 167         "nop; "                                                \
 168         "1: "                                                \
 169         "mrc p15, 0, r15, c7, c14, 3;"                                                \
 170         "bne 1b;"                                                           \
 171         "mov    r0, #0x0;"                                                    \
 172         "mcr    p15,0,r0,c7,c10,4;" /* drain the write buffer */        \
 173         :                                                               \
 174         :                                                               \
 175         : "r0" /* Clobber list */                                       \
 176         );                                                              \
 177 CYG_MACRO_END
 178
 179 #else
 180 #define HAL_DCACHE_SYNC()                                               \
 181 CYG_MACRO_START                                                         \
 182     cyg_uint32 _tmp1, _tmp2;                                            \
 183     asm volatile (                                                      \
 184         "mov    %0, #0;"                                                \
 185         "1: "                                                           \
 186         "mov    %1, #0;"                                                \
 187         "2: "                                                           \
 188         "orr    r0,%0,%1;"                                              \
 189         "mcr    p15,0,r0,c7,c14,2;"  /* clean index in DCache */        \
 190         "add    %1,%1,%2;"                                              \
 191         "cmp    %1,%3;"                                                 \
 192         "bne    2b;"                                                    \
 193         "add    %0,%0,#0x04000000;"  /* get to next index */            \
 194         "cmp    %0,#0;"                                                 \
 195         "bne    1b;"                                                    \
 196         "mov    r0, #0x0;"                                                    \
 197         "mcr    p15,0,r0,c7,c10,4;" /* drain the write buffer */        \
 198         : "=r" (_tmp1), "=r" (_tmp2)                                    \
 199         : "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP),            \
 200           "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT)            \
 201         : "r0" /* Clobber list */                                       \
 202         );                                                              \
 203 CYG_MACRO_END
 204 #endif
 205
 206 // Query the state of the data cache
 207 #define HAL_DCACHE_IS_ENABLED(_state_)                                   \
 208 CYG_MACRO_START                                                          \
 209     register int reg;                                                    \
 210     asm volatile (  \
 211         "nop; "                                                \
 212         "nop; "                                                \
 213         "nop; "                                                \
 214         "nop; "                                                \
 215         "nop; "                                                \
 216         "mrc  p15,0,%0,c1,c0,0;"                               \
 217                   : "=r"(reg)                                            \
 218                   :                                                      \
 219         );                                                               \
 220     (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */           \
 221 CYG_MACRO_END
 222
 223 // Purge contents of data cache
 224 //#define HAL_DCACHE_PURGE_ALL() -- not used
 225
 226 // Set the data cache refill burst size
 227 //#define HAL_DCACHE_BURST_SIZE(_size_)
 228
 229 // Set the data cache write mode
 230 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
 231
 232 //#define HAL_DCACHE_WRITETHRU_MODE       0
 233 //#define HAL_DCACHE_WRITEBACK_MODE       1
 234
 235 // Load the contents of the given address range into the data cache
 236 // and then lock the cache so that it stays there.
 237 //#define HAL_DCACHE_LOCK(_base_, _size_)
 238
 239 // Undo a previous lock operation
 240 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
 241
 242 // Unlock entire cache
 243 //#define HAL_DCACHE_UNLOCK_ALL()
 244
 245 //-----------------------------------------------------------------------------
 246 // Data cache line control
 247
 248 // Allocate cache lines for the given address range without reading its
 249 // contents from memory.
 250 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 251
 252 // Write dirty cache lines to memory and invalidate the cache entries
 253 // for the given address range.
 254 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
 255
 256 // Invalidate cache lines in the given range without writing to memory.
 257 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
 258
 259 // Write dirty cache lines to memory for the given address range.
 260 //#define HAL_DCACHE_STORE( _base_ , _size_ )
 261
 262 // Preread the given range into the cache with the intention of reading
 263 // from it later.
 264 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
 265
 266 // Preread the given range into the cache with the intention of writing
 267 // to it later.
 268 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
 269
 270 // Allocate and zero the cache lines associated with the given range.
 271 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
 272
 273 //-----------------------------------------------------------------------------
 274 // Global control of Instruction cache
 275
 276 // Enable the instruction cache
 277 #define HAL_ICACHE_ENABLE()                                             \
 278 CYG_MACRO_START                                                         \
 279     asm volatile (                                                      \
 280         "mrc  p15,0,r1,c1,c0,0;"                                        \
 281         "orr  r1,r1,#0x1000;"                                           \
 282         "orr  r1,r1,#0x0003;" /* enable ICache (also ensures   */       \
 283                               /* that MMU and alignment faults */       \
 284                               /* are enabled)                  */       \
 285         "mcr  p15,0,r1,c1,c0,0"                                         \
 286         :                                                               \
 287         :                                                               \
 288         : "r1" /* Clobber list */                                       \
 289         );                                                              \
 290 CYG_MACRO_END
 291
 292 // Query the state of the instruction cache
 293 #define HAL_ICACHE_IS_ENABLED(_state_)                                   \
 294 CYG_MACRO_START                                                          \
 295     register cyg_uint32 reg;                                             \
 296     asm volatile ("mrc  p15,0,%0,c1,c0,0"                                \
 297                   : "=r"(reg)                                            \
 298                   :                                                      \
 299         );                                                               \
 300     (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */     \
 301 CYG_MACRO_END
 302
 303 // Disable the instruction cache
 304 #define HAL_ICACHE_DISABLE()                                            \
 305 CYG_MACRO_START                                                         \
 306     asm volatile (                                                      \
 307         "mrc    p15,0,r1,c1,c0,0;"                                      \
 308         "bic    r1,r1,#0x1000;" /* disable ICache (but not MMU, etc) */ \
 309         "mcr    p15,0,r1,c1,c0,0;"                                      \
 310         "mov    r1,#0;"                                                 \
 311         "mcr    p15,0,r1,c7,c5,0;"  /* flush ICache */                  \
 312         "nop;" /* next few instructions may be via cache    */          \
 313         "nop;"                                                          \
 314         "nop;"                                                          \
 315         "nop;"                                                          \
 316         "nop;"                                                          \
 317         "nop"                                                           \
 318         :                                                               \
 319         :                                                               \
 320         : "r1" /* Clobber list */                                       \
 321         );                                                              \
 322 CYG_MACRO_END
 323
 324 // Invalidate the entire cache
 325 #define HAL_ICACHE_INVALIDATE_ALL()                                     \
 326 CYG_MACRO_START                                                         \
 327     /* this macro can discard dirty cache lines (N/A for ICache) */     \
 328     asm volatile (                                                      \
 329         "mov    r1,#0;"                                                 \
 330         "mcr    p15,0,r1,c7,c5,0;"  /* flush ICache */                  \
 331         "mcr    p15,0,r1,c8,c5,0;"  /* flush ITLB only */               \
 332         "nop;" /* next few instructions may be via cache    */          \
 333         "nop;"                                                          \
 334         "nop;"                                                          \
 335         "nop;"                                                          \
 336         "nop;"                                                          \
 337         "nop;"                                                          \
 338         :                                                               \
 339         :                                                               \
 340         : "r1" /* Clobber list */                                       \
 341         );                                                              \
 342 CYG_MACRO_END
 343
 344 // Synchronize the contents of the cache with memory.
 345 // (which includes flushing out pending writes)
 346 #define HAL_ICACHE_SYNC()                                       \
 347 CYG_MACRO_START                                                 \
 348     HAL_DCACHE_SYNC(); /* ensure data gets to RAM */            \
 349     HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */       \
 350 CYG_MACRO_END
 351
 352 #else
 353
 354
 355 // Set the instruction cache refill burst size
 356 //#define HAL_ICACHE_BURST_SIZE(_size_)
 357
 358 // Load the contents of the given address range into the instruction cache
 359 // and then lock the cache so that it stays there.
 360 //#define HAL_ICACHE_LOCK(_base_, _size_)
 361
 362 // Undo a previous lock operation
 363 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
 364
 365 // Unlock entire cache
 366 //#define HAL_ICACHE_UNLOCK_ALL()
 367
 368 //-----------------------------------------------------------------------------
 369 // Instruction cache line control
 370
 371 // Invalidate cache lines in the given range without writing to memory.
 372 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
 373
 374 //-----------------------------------------------------------------------------
 375 #endif // ifndef CYGONCE_HAL_CACHE_H
 376 // End of hal_cache.h