1 //==========================================================================
5 // SoC chip definitions
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2002 Gary Thomas
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //========================================================================*/
46 #include <cyg/hal/mx27_pins.h>
50 #define REG8_VAL(a) (a)
51 #define REG16_VAL(a) (a)
52 #define REG32_VAL(a) (a)
54 #define REG8_PTR(a) (a)
55 #define REG16_PTR(a) (a)
56 #define REG32_PTR(a) (a)
58 #else /* __ASSEMBLER__ */
62 extern char HAL_PLATFORM_EXTRA[20];
63 #define REG8_VAL(a) ((unsigned char)(a))
64 #define REG16_VAL(a) ((unsigned short)(a))
65 #define REG32_VAL(a) ((unsigned int)(a))
67 #define REG8_PTR(a) ((volatile unsigned char *)(a))
68 #define REG16_PTR(a) ((volatile unsigned short *)(a))
69 #define REG32_PTR(a) ((volatile unsigned int *)(a))
70 #define readb(a) (*(volatile unsigned char *)(a))
71 #define readw(a) (*(volatile unsigned short *)(a))
72 #define readl(a) (*(volatile unsigned int *)(a))
73 #define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
74 #define writew(v,a) (*(volatile unsigned short *)(a) = (v))
75 #define writel(v,a) (*(volatile unsigned int *)(a) = (v))
77 #endif /* __ASSEMBLER__ */
80 * Default Memory Layout Definitions
83 #define SOC_AIPI1_BASE UL(0x10000000)
84 #define SOC_AIPI2_BASE UL(0x10020000)
86 #define SOC_AIPI_PAR_OFF 8
88 #define CSPI1_BASE_ADDR (SOC_AIPI1_BASE + 0x0E000)
89 #define CSPI2_BASE_ADDR (SOC_AIPI1_BASE + 0x0F000)
90 #define CSPI3_BASE_ADDR (SOC_AIPI1_BASE + 0x17000)
92 #define SOC_CRM_BASE UL(0x10027000)
93 #define SOC_CRM_CSCR (SOC_CRM_BASE + 0x0)
94 #define SOC_CRM_MPCTL0 (SOC_CRM_BASE + 0x4)
95 #define SOC_CRM_MPCTL1 (SOC_CRM_BASE + 0x8)
96 #define SOC_CRM_SPCTL0 (SOC_CRM_BASE + 0xC)
97 #define SOC_CRM_SPCTL1 (SOC_CRM_BASE + 0x10)
98 #define SOC_CRM_OSC26MCTL (SOC_CRM_BASE + 0x14)
99 #define SOC_CRM_PCDR0 (SOC_CRM_BASE + 0x18)
100 #define SOC_CRM_PCDR1 (SOC_CRM_BASE + 0x1C)
101 #define SOC_CRM_PCCR0 (SOC_CRM_BASE + 0x20)
102 #define SOC_CRM_PCCR1 (SOC_CRM_BASE + 0x24)
103 #define SOC_CRM_CCSR (SOC_CRM_BASE + 0x28)
104 #define SOC_CRM_PMCTL (SOC_CRM_BASE + 0x2C)
105 #define SOC_CRM_PMCOUNT (SOC_CRM_BASE + 0x30)
106 #define SOC_CRM_WKGDCTL (SOC_CRM_BASE + 0x34)
108 #define CRM_CSCR_IPDIV_OFFSET 8
109 #define CRM_CSCR_BCLKDIV_OFFSET 9
110 #define CRM_CSCR_PRESC_OFFSET 13
111 #define CRM_CSCR_SSI1_SEL_OFFSET 22
112 #define CRM_CSCR_SSI2_SEL_OFFSET 23
113 #define CRM_CSCR_USB_DIV_OFFSET 28
115 #define CRM_CSCR_ARM_OFFSET 12
116 #define CRM_CSCR_ARM_SRC (1<<15)
117 #define CRM_CSCR_AHB_OFFSET 8
119 #define FREQ_26MHZ 26000000
120 #define FREQ_27MHZ 27000000
121 #define FREQ_32768HZ (32768 * 512 * 2)
122 #define FREQ_32000HZ (32000 * 512 * 2)
125 /* These should be defined in platform specific files */
126 //#define CLOCK_266_133_66
127 #define CLOCK_399_133_66
128 //#define CLOCK_399_100_50
130 //#define PLL_REF_CLK FREQ_32768HZ
131 #define PLL_REF_CLK FREQ_26MHZ
132 //#define PLL_REF_CLK FREQ_32000HZ
134 #define PLL_REF_CLK CYGHWR_HAL_ARM_SOC_PLL_REF_CLOCK
135 #if (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == 399)
136 #if (CYGHWR_HAL_ARM_SOC_SYSTEM_CLOCK == 133)
137 #define CLOCK_399_133_66
138 #elif (CYGHWR_HAL_ARM_SOC_SYSTEM_CLOCK == 100)
139 #define CLOCK_399_100_50
141 #error Invalid SYSTEM clock (CYGHWR_HAL_ARM_SOC_SYSTEM_CLOCK) defined
143 #elif (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == 266)
144 #define CLOCK_266_133_66
146 #error Invalid processor clock (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK) defined
151 #define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) ((((pd)-1)<<26) + (((fd)-1)<<16) + ((fi)<<10) + (((fn) & 0x3ff) << 0))
152 #if (PLL_REF_CLK == FREQ_32768HZ)
153 #define PLL_REF_CLK_32768HZ
154 // SPCTL0 for 240 MHz
155 #define CRM_SPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 124, 7, 19)
156 #define CRM_SPCTL0_VAL_27MHZ CRM_SPCTL0_VAL
157 #define CRM_SPCTL0_VAL2 CRM_PLL_PCTL_PARAM(2, 755, 11, -205)
158 #define CRM_SPCTL0_VAL2_27MHZ CRM_SPCTL0_VAL2
159 #if defined (CLOCK_266_133_66)
160 #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 400, 7, 371)
161 #define CRM_MPCTL0_VAL_27MHZ CRM_MPCTL0_VAL
162 #define CRM_CSCR_VAL 0x33F00307
163 #define CRM_MPCTL0_VAL2 CRM_PLL_PCTL_PARAM(1, 496, 5, 469)
164 #define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL2
165 #define CRM_CSCR_VAL2 0x33F00107
166 #elif defined (CLOCK_399_133_66)
167 #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 100, 11, 89)
168 #define CRM_MPCTL0_VAL_27MHZ CRM_MPCTL0_VAL
169 #define CRM_CSCR_VAL 0x33F00507
170 #define CRM_MPCTL0_VAL2 CRM_PLL_PCTL_PARAM(1, 496, 5, 469)
171 #define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL2
172 #define CRM_CSCR_VAL2 0x33F08107
173 #elif defined (CLOCK_399_100_50)
174 #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 100, 11, 89)
175 #define CRM_MPCTL0_VAL_27MHZ CRM_MPCTL0_VAL
176 #define CRM_CSCR_VAL 0x33F00307
177 #define CRM_MPCTL0_VAL2 CRM_PLL_PCTL_PARAM(1, 100, 11, 94)
178 #define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL2
179 #define CRM_CSCR_VAL2 0x33F00307
181 #error This clock is not supported !!!!
182 #endif // CLOCK_266_133_66
184 // SPCTL0 for 240 MHz
185 #define CRM_SPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 13, 9, 3)
186 #define CRM_SPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(2, 9, 8, 8)
187 #define CRM_SPCTL0_VAL2 CRM_SPCTL0_VAL
188 #define CRM_SPCTL0_VAL2_27MHZ CRM_SPCTL0_VAL_27MHZ
190 #if defined (CLOCK_266_133_66)
191 #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 26, 10, 6)
192 #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(2, 15, 9, 13) // 266.4MHz
193 #define CRM_CSCR_VAL 0x33F30307
194 #define CRM_MPCTL0_VAL2 CRM_PLL_PCTL_PARAM(1, 52, 7, 35)
195 #define CRM_MPCTL0_VAL2_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6MHz
196 #define CRM_CSCR_VAL2 0x33F30107
197 #elif defined (CLOCK_399_133_66)
198 #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(1, 52, 7, 35)
199 #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6MHz
200 #define CRM_CSCR_VAL 0x33F30507
201 #define CRM_MPCTL0_VAL2 CRM_MPCTL0_VAL
202 #define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL_27MHZ
203 #define CRM_CSCR_VAL2 0x33F38107
204 #elif defined (CLOCK_399_100_50)
205 #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(1, 52, 7, 35)
206 #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6MHz
207 #define CRM_CSCR_VAL 0x33F30307
208 #define CRM_MPCTL0_VAL2 CRM_PLL_PCTL_PARAM(1, 52, 11, 28)
209 #define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL_27MHZ
210 #define CRM_CSCR_VAL2 0x33F30307
212 #error This clock is not supported !!!!
213 #endif // CLOCK_266_133_66
215 #endif // PLL_REF_CLK == FREQ_26MHZ
218 #define SOC_SYSCTRL_BASE UL(0x10027800)
219 #define SOC_SYSCTRL_CID (SOC_SYSCTRL_BASE + 0x00)
220 #define SOC_SYSCTRL_FMCR (SOC_SYSCTRL_BASE + 0x14)
221 #define FMCR_FMS (1 << 5)
222 #define FMCR_NF_16BIT (1 << 4)
223 #define FMCR_SLCDC_SEL (1 << 2)
224 #define FMCR_SDCS1_SEL (1 << 1)
225 #define FMCR_SDCS0_SEL (1 << 0)
226 #define SOC_SYSCTRL_GPCR (SOC_SYSCTRL_BASE + 0x18)
227 #define SOC_SYSCTRL_WBCR (SOC_SYSCTRL_BASE + 0x1C)
228 #define SOC_SYSCTRL_DSCR1 (SOC_SYSCTRL_BASE + 0x20)
229 #define SOC_SYSCTRL_DSCR2 (SOC_SYSCTRL_BASE + 0x24)
230 #define SOC_SYSCTRL_DSCR3 (SOC_SYSCTRL_BASE + 0x28)
231 #define SOC_SYSCTRL_DSCR4 (SOC_SYSCTRL_BASE + 0x2C)
232 #define SOC_SYSCTRL_DSCR5 (SOC_SYSCTRL_BASE + 0x30)
233 #define SOC_SYSCTRL_DSCR6 (SOC_SYSCTRL_BASE + 0x34)
234 #define SOC_SYSCTRL_DSCR7 (SOC_SYSCTRL_BASE + 0x38)
235 #define SOC_SYSCTRL_DSCR8 (SOC_SYSCTRL_BASE + 0x3C)
236 #define SOC_SYSCTRL_DSCR9 (SOC_SYSCTRL_BASE + 0x40)
237 #define SOC_SYSCTRL_DSCR10 (SOC_SYSCTRL_BASE + 0x44)
238 #define SOC_SYSCTRL_DSCR11 (SOC_SYSCTRL_BASE + 0x48)
239 #define SOC_SYSCTRL_DSCR12 (SOC_SYSCTRL_BASE + 0x4C)
240 #define SOC_SYSCTRL_DSCR13 (SOC_SYSCTRL_BASE + 0x50)
241 #define SOC_SYSCTRL_PSCR (SOC_SYSCTRL_BASE + 0x54)
242 #define SOC_SYSCTRL_PCSR (SOC_SYSCTRL_BASE + 0x58)
243 #define SOC_SYSCTRL_PMCR (SOC_SYSCTRL_BASE + 0x60)
244 #define SOC_SYSCTRL_DCVR0 (SOC_SYSCTRL_BASE + 0x64)
245 #define SOC_SYSCTRL_DCVR1 (SOC_SYSCTRL_BASE + 0x68)
246 #define SOC_SYSCTRL_DCVR2 (SOC_SYSCTRL_BASE + 0x6C)
247 #define SOC_SYSCTRL_DCVR3 (SOC_SYSCTRL_BASE + 0x70)
249 // Interrupt Controller Register Definitions.
250 #define SOC_AITC_BASE UL(0x10040000)
251 #define SOC_AITC_INTCNTL (SOC_AITC_BASE + 0x00)
252 #define SOC_AITC_NIMASK (SOC_AITC_BASE + 0x04)
253 #define SOC_AITC_INTENNUM (SOC_AITC_BASE + 0x08)
254 #define SOC_AITC_INTDISNUM (SOC_AITC_BASE + 0x0C)
255 #define SOC_AITC_INTENABLEH (SOC_AITC_BASE + 0x10)
256 #define SOC_AITC_INTENABLEL (SOC_AITC_BASE + 0x14)
257 #define SOC_AITC_INTTYPEH (SOC_AITC_BASE + 0x18)
258 #define SOC_AITC_INTTYPEL (SOC_AITC_BASE + 0x1C)
259 #define SOC_AITC_NIPRIORITY7 (SOC_AITC_BASE + 0x20)
260 #define SOC_AITC_NIPRIORITY6 (SOC_AITC_BASE + 0x24)
261 #define SOC_AITC_NIPRIORITY5 (SOC_AITC_BASE + 0x28)
262 #define SOC_AITC_NIPRIORITY4 (SOC_AITC_BASE + 0x2C)
263 #define SOC_AITC_NIPRIORITY3 (SOC_AITC_BASE + 0x30)
264 #define SOC_AITC_NIPRIORITY2 (SOC_AITC_BASE + 0x34)
265 #define SOC_AITC_NIPRIORITY1 (SOC_AITC_BASE + 0x38)
266 #define SOC_AITC_NIPRIORITY0 (SOC_AITC_BASE + 0x3C)
268 #define UART_WIDTH_32
270 // UART Base Addresses
271 #define SOC_UART1_BASE UL(0x1000A000)
272 #define SOC_UART2_BASE UL(0x1000B000)
273 #define SOC_UART3_BASE UL(0x1000C000)
274 #define SOC_UART4_BASE UL(0x1000D000)
275 #define SOC_UART5_BASE UL(0x1001B000)
276 #define SOC_UART6_BASE UL(0x1001C000)
278 #define SOC_MAX_BASE UL(0x1003F000)
279 // Slave port base offset
280 #define MAX_SLAVE_PORT0_OFFSET 0x0
281 #define MAX_SLAVE_PORT1_OFFSET 0x100
282 #define MAX_SLAVE_PORT2_OFFSET 0x200
283 // Register offset for slave port
284 #define MAX_SLAVE_MPR_OFFSET 0x0 /* Master Priority register */
285 #define MAX_SLAVE_AMPR_OFFSET 0x4 /* Alternate Master Priority register */
286 #define MAX_SLAVE_SGPCR_OFFSET 0x10 /* Slave General Purpose Control register */
287 #define MAX_SLAVE_ASGPCR_OFFSET 0x14 /* Alternate Slave General Purpose control register */
288 // Master port base offset
289 #define MAX_MASTER_PORT0_OFFSET 0x800
290 #define MAX_MASTER_PORT1_OFFSET 0x900
291 #define MAX_MASTER_PORT2_OFFSET 0xA00
292 #define MAX_MASTER_PORT3_OFFSET 0xB00
293 #define MAX_MASTER_PORT4_OFFSET 0xC00
294 #define MAX_MASTER_PORT5_OFFSET 0xD00
295 // Register offset for master port
296 #define MAX_MASTER_MGPCR_OFFSET 0x0 /* Master General Purpose Control Register */
298 * MX27 GPIO Register Definitions
300 #define SOC_GPIOA_BASE UL(0x10015000)
301 #define SOC_GPIOB_BASE UL(0x10015100)
302 #define SOC_GPIOC_BASE UL(0x10015200)
303 #define SOC_GPIOD_BASE UL(0x10015300)
304 #define SOC_GPIOE_BASE UL(0x10015400)
305 #define SOC_GPIOF_BASE UL(0x10015500)
306 #define SOC_GPIO_PMASK UL(0x10015600)
307 #define GPIO_DDIR 0x0 /* Data direction reg */
308 #define GPIO_OCR1 0x4 /* Output config reg 1 */
309 #define GPIO_OCR2 0x8 /* Output config reg 2 */
310 #define GPIO_ICONFA1 0xC /* Input config reg A1 */
311 #define GPIO_ICONFA2 0x10 /* Input config reg A2 */
312 #define GPIO_ICONFB1 0x14 /* Input config reg B1 */
313 #define GPIO_ICONFB2 0x18 /* Input config reg B2 */
314 #define GPIO_DR 0x1C /* Data reg */
315 #define GPIO_GIUS 0x20 /* GPIO in use reg */
316 #define GPIO_SSR 0x24 /* Sample status reg */
317 #define GPIO_ICR1 0x28 /* Int config reg 1 */
318 #define GPIO_ICR2 0x2C /* Int config reg 2 */
319 #define GPIO_IMR 0x30 /* Int mask reg */
320 #define GPIO_ISR 0x34 /* Int status reg */
321 #define GPIO_GPR 0x38 /* Gen purpose reg */
322 #define GPIO_SWR 0x3C /* Software reset reg */
323 #define GPIO_PUEN 0x40 /* Pull-up enable reg */
325 #define GPIO_OCR_A 0 /* External input a_IN */
326 #define GPIO_OCR_B 1 /* External input b_IN */
327 #define GPIO_OCR_C 2 /* External input c_IN */
328 #define GPIO_OCR_DR 3 /* Data register */
329 #define GPIO_ICONF_In 0 /* GPIO-in */
330 #define GPIO_ICONF_Isr 1 /* Interrupt status register */
331 #define GPIO_ICONF_0 2 /* 0 */
332 #define GPIO_ICONF_1 3 /* 1 */
333 #define GPIO_ICR_PosEdge 0 /* Positive edge */
334 #define GPIO_ICR_NegEdge 1 /* Negative edge */
335 #define GPIO_ICR_PosLvl 2 /* Positive level */
336 #define GPIO_ICR_NegLvl 3 /* Negative level */
337 #define GPIO_SWR_SWR 1 /* Software reset */
342 #define HAL_DELAY_TIMER SOC_GPT2_BASE // use timer2 for hal_delay_us()
344 #define SOC_GPT1_BASE UL(0x10003000)
345 #define SOC_GPT2_BASE UL(0x10004000)
346 #define SOC_GPT3_BASE UL(0x10005000)
347 #define SOC_GPT4_BASE UL(0x10019000)
348 #define SOC_GPT5_BASE UL(0x1001A000)
349 #define SOC_GPT6_BASE UL(0x1001F000)
350 #define GPT_TCTL_OFFSET 0x0
351 #define GPT_TPRER_OFFSET 0x4
352 #define GPT_TCMP_OFFSET 0x8
353 #define GPT_TCR_OFFSET 0xC
354 #define GPT_TCN_OFFSET 0x10
355 #define GPT_TSTAT_OFFSET 0x14
356 #define MX_STARTUP_DELAY (1000000 / 10) // 0.1s delay to get around the ethernet reset failure problem
358 #define TIMER_PRESCALER 3
359 #define SOC_SI_ID_REG UL(0x10027800)
360 #define SOC_SILICONID_Rev1_0 0x0
361 #define SOC_SILICONID_Rev2_0 0x1
362 #define SOC_SILICONID_Rev2_1 0x2
363 #define CHIP_REV_1_x 1
364 #define CHIP_REV_2_x 2
365 #define CHIP_REV_3_0 3
366 #define CHIP_REV_3_1 4
367 #define CHIP_REV_unknown 0x100
369 #define SOC_WDOG_BASE UL(0x10002000)
370 #define WDOG_BASE_ADDR SOC_WDOG_BASE
372 #define NFC_BASE UL(0xD8000000)
373 #define SOC_ESDCTL_BASE UL(0xD8001000)
374 #define SOC_EIM_BASE UL(0xD8002000)
375 #define SOC_M3IF_BASE UL(0xD8003000)
376 #define SOC_PCMCIA_BASE UL(0xD8004000)
378 #define SOC_CS0_CTL_BASE SOC_EIM_BASE
379 #define SOC_CS1_CTL_BASE (SOC_EIM_BASE + 0x10)
380 #define SOC_CS2_CTL_BASE (SOC_EIM_BASE + 0x20)
381 #define SOC_CS3_CTL_BASE (SOC_EIM_BASE + 0x30)
382 #define SOC_CS4_CTL_BASE (SOC_EIM_BASE + 0x40)
383 #define SOC_CS5_CTL_BASE (SOC_EIM_BASE + 0x50)
386 #define CSCRU_OFFSET 0x00
387 #define CSCRL_OFFSET 0x04
388 #define CSCRA_OFFSET 0x08
389 #define CSWCR_OFFSET 0x60
392 #define SOC_CSD0_BASE UL(0xA0000000)
393 #define SOC_CSD1_BASE UL(0xB0000000)
394 #define SOC_CS0_BASE UL(0xC0000000)
395 #define CS0_BASE_ADDR SOC_CS0_BASE
396 #define SOC_CS1_BASE UL(0xC8000000)
397 #define SOC_CS2_BASE UL(0xD0000000)
398 #define SOC_CS3_BASE UL(0xD2000000)
399 #define SOC_CS4_BASE UL(0xD4000000)
400 #define SOC_CS5_BASE UL(0xD6000000)
401 #define NAND_REG_BASE (NFC_BASE + 0xE00)
403 #define SOC_IIM_BASE UL(0x10028000)
404 #define SOC_FEC_MAC_BASE UL(0x10028C04)
405 #define SOC_FEC_MAC_BASE2 UL(0x10028814)
406 #define SOC_FEC_BASE UL(0x1002B000)
407 #define IIM_BASE_ADDR SOC_IIM_BASE
409 #define CHIP_REV_1_0 0x0 /* PASS 1.0 */
410 #define CHIP_REV_2_0 0x1 /* PASS 2.0 */
412 #define IIM_STAT_OFF 0x00
413 #define IIM_STAT_BUSY (1 << 7)
414 #define IIM_STAT_PRGD (1 << 1)
415 #define IIM_STAT_SNSD (1 << 0)
416 #define IIM_STATM_OFF 0x04
417 #define IIM_ERR_OFF 0x08
418 #define IIM_ERR_PRGE (1 << 7)
419 #define IIM_ERR_WPE (1 << 6)
420 #define IIM_ERR_OPE (1 << 5)
421 #define IIM_ERR_RPE (1 << 4)
422 #define IIM_ERR_WLRE (1 << 3)
423 #define IIM_ERR_SNSE (1 << 2)
424 #define IIM_ERR_PARITYE (1 << 1)
425 #define IIM_EMASK_OFF 0x0C
426 #define IIM_FCTL_OFF 0x10
427 #define IIM_UA_OFF 0x14
428 #define IIM_LA_OFF 0x18
429 #define IIM_SDAT_OFF 0x1C
430 #define IIM_PREV_OFF 0x20
431 #define IIM_SREV_OFF 0x24
432 #define IIM_PREG_P_OFF 0x28
433 #define IIM_SCS0_OFF 0x2C
434 #define IIM_SCS1_P_OFF 0x30
435 #define IIM_SCS2_OFF 0x34
436 #define IIM_SCS3_P_OFF 0x38
438 #define ESDCTL_ESDCTL0 0x00
439 #define ESDCTL_ESDCFG0 0x04
440 #define ESDCTL_ESDCTL1 0x08
441 #define ESDCTL_ESDCFG1 0x0C
442 #define ESDCTL_ESDMISC 0x10
444 #define NFC_BUFSIZE_REG_OFF (0 + 0x00)
445 #define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04)
446 #define NAND_FLASH_ADD_REG_OFF (0 + 0x06)
447 #define NAND_FLASH_CMD_REG_OFF (0 + 0x08)
448 #define NFC_CONFIGURATION_REG_OFF (0 + 0x0A)
449 #define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C)
450 #define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E)
451 #define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10)
452 #define NF_WR_PROT_REG_OFF (0 + 0x12)
453 #define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x14)
454 #define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x16)
455 #define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18)
456 #define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A)
457 #define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C)
458 #define RAM_BUFFER_ADDRESS_RBA_3 0x3
459 #define NFC_BUFSIZE_1KB 0x0
460 #define NFC_BUFSIZE_2KB 0x1
461 #define NFC_CONFIGURATION_UNLOCKED 0x2
462 #define ECC_STATUS_RESULT_NO_ERR 0x0
463 #define ECC_STATUS_RESULT_1BIT_ERR 0x1
464 #define ECC_STATUS_RESULT_2BIT_ERR 0x2
465 #define NF_WR_PROT_UNLOCK 0x4
466 #define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7)
467 #define NAND_FLASH_CONFIG1_RST (1 << 6)
468 #define NAND_FLASH_CONFIG1_BIG (1 << 5)
469 #define NAND_FLASH_CONFIG1_INT_MSK (1 << 4)
470 #define NAND_FLASH_CONFIG1_ECC_EN (1 << 3)
471 #define NAND_FLASH_CONFIG1_SP_EN (1 << 2)
472 #define NAND_FLASH_CONFIG2_INT_DONE (1 << 15)
473 #define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3)
474 #define NAND_FLASH_CONFIG2_FDO_ID (2 << 3)
475 #define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3)
476 #define NAND_FLASH_CONFIG2_FDI_EN (1 << 2)
477 #define NAND_FLASH_CONFIG2_FADD_EN (1 << 1)
478 #define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
479 #define FDO_PAGE_SPARE_VAL 0x8
481 #define MXC_NAND_BASE_DUMMY UL(0xE0000000)
482 #define NOR_FLASH_BOOT 0
483 #define NAND_FLASH_BOOT 0x10
484 #define SDRAM_NON_FLASH_BOOT 0x20
485 #define MXCBOOT_FLAG_REG SOC_AITC_NIPRIORITY7
487 #define MXCFIS_NOTHING 0x00000000
488 #define MXCFIS_NAND 0x10000000
489 #define MXCFIS_NOR 0x20000000
490 #define MXCFIS_FLAG_REG SOC_AITC_NIPRIORITY6
491 #ifndef MXCFLASH_SELECT_NAND
492 #define IS_BOOTING_FROM_NAND() 0
494 #define IS_BOOTING_FROM_NAND() (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
496 #ifndef MXCFLASH_SELECT_NOR
497 #define IS_BOOTING_FROM_NOR() 0
499 #define IS_BOOTING_FROM_NOR() (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
501 #ifndef IS_BOOTING_FROM_SDRAM
502 #define IS_BOOTING_FROM_SDRAM() (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
505 #ifndef MXCFLASH_SELECT_NAND
506 #define IS_FIS_FROM_NAND() 0
508 #ifndef MXCFLASH_SELECT_NOR
509 #define IS_FIS_FROM_NAND() 1
511 #define IS_FIS_FROM_NAND() (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
515 #ifndef MXCFLASH_SELECT_NOR
516 #define IS_FIS_FROM_NOR() 0
518 #define IS_FIS_FROM_NOR() (!IS_FIS_FROM_NAND())
521 #define MXC_ASSERT_NOR_BOOT() writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
522 #define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
524 #define SERIAL_DOWNLOAD_MAGIC 0x000000AA
525 #define SERIAL_DOWNLOAD_MAGIC_REG SOC_AITC_NIPRIORITY3
526 #define SERIAL_DOWNLOAD_SRC_REG SOC_AITC_NIPRIORITY2
527 #define SERIAL_DOWNLOAD_TGT_REG SOC_AITC_NIPRIORITY1
528 #define SERIAL_DOWNLOAD_SZ_REG SOC_AITC_NIPRIORITY0
530 #if !defined(__ASSEMBLER__)
531 void cyg_hal_plf_serial_init(void);
532 void cyg_hal_plf_serial_stop(void);
533 void hal_delay_us(unsigned int usecs);
534 #define HAL_DELAY_US(n) hal_delay_us(n)
537 MCU_PLL = SOC_CRM_MPCTL0,
538 SER_PLL = SOC_CRM_SPCTL0,
558 SPI1_CLK = CSPI1_BASE_ADDR,
559 SPI2_CLK = CSPI2_BASE_ADDR,
562 unsigned int pll_clock(enum plls pll);
564 unsigned int get_main_clock(enum main_clocks clk);
566 unsigned int get_peri_clock(enum peri_clocks clk);
567 #define GPIO_PORT_NUM 6
568 #define GPIO_NUM_PIN 32
569 #define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM)
571 #define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * GPIO_NUM_PIN) + ((pin >> MUX_IO_I) & ((1 << (MUX_IO_P - MUX_IO_I)) -1)))
572 #define IOMUX_TO_IRQ(pin) (MXC_GPIO_BASE + IOMUX_TO_GPIO(pin))
573 #define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
574 #define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
587 int gpio_request_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode);
588 void clock_spi_enable(unsigned int spi_clk);
590 typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
592 #endif //#if !defined(__ASSEMBLER__)
594 #define HAL_MMU_OFF() \
598 "mrc p15, 0, r15, c7, c14, 3;" /*test clean and inval*/ \
601 "mcr p15,0,r0,c7,c10,4;" /* Data Write Barrier */ \
602 "mcr p15,0,r0,c7,c5,0;" /* invalidate I cache */ \
603 "mrc p15,0,r0,c1,c0,0;" /* read c1 */ \
604 "bic r0,r0,#0x7;" /* disable DCache and MMU */ \
605 "bic r0,r0,#0x1000;" /* disable ICache */ \
606 "mcr p15,0,r0,c1,c0,0;" /* */ \
607 "nop;" /* flush i+d-TLBs */ \
608 "nop;" /* flush i+d-TLBs */ \
609 "nop;" /* flush i+d-TLBs */ \
612 : "r0","memory" /* clobber list */); \
615 #endif /* __HAL_SOC_H__ */