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34 # ====================================================================
35 ######DESCRIPTIONBEGIN####
38 # Original data: gthomas
42 #####DESCRIPTIONEND####
44 # ====================================================================
45 cdl_package CYGPKG_HAL_ARM_MX51 {
46 display "Freescale SoC architecture"
50 define_header hal_arm_soc.h
52 This HAL variant package provides generic
53 support for the Freescale SoC. It is also
54 necessary to select a specific target platform HAL
57 implements CYGINT_HAL_ARM_ARCH_ARM9
58 implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
60 # Let the architectural HAL see this variant's interrupts file -
61 # the SoC has no variation between targets here.
63 puts $::cdl_header "#define CYGBLD_HAL_VAR_INTS_H <cyg/hal/hal_var_ints.h>"
64 puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H"
66 puts $::cdl_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 1000000"
69 compile soc_diag.c soc_misc.c
70 compile -library=libextras.a cmds.c
72 cdl_option CYGHWR_MX51_TO2 {
73 display "MX51 Tapeout 2.0 support"
76 When this option is enabled, it indicates support for
79 puts $::cdl_system_header "#define IMX51_TO_2"
83 cdl_option CYGHWR_MX51_MDDR {
84 display "MX51 mDDR memory support"
87 When this option is enabled, it indicates support for
90 puts $::cdl_system_header "#define IMX51_MDDR"
94 cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
95 display "Processor clock rate"
96 active_if { CYG_HAL_STARTUP == "ROM" }
98 legal_values 150000 200000
99 default_value { CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT ?
100 CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT : 150000}
102 The processor can run at various frequencies.
103 These values are expressed in KHz. Note that there are
104 several steppings of the rate to run at different
105 maximum frequencies. Check the specs to make sure that your
106 particular processor can run at the rate you select here."
109 # Real-time clock/counter specifics
110 cdl_component CYGNUM_HAL_RTC_CONSTANTS {
111 display "Real-time clock constants"
115 cdl_option CYGNUM_HAL_RTC_NUMERATOR {
116 display "Real-time clock numerator"
118 calculated 1000000000
120 cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
121 display "Real-time clock denominator"
125 This option selects the heartbeat rate for the real-time clock.
126 The rate is specified in ticks per second. Change this value
127 with caution - too high and your system will become saturated
128 just handling clock interrupts, too low and some operations
129 such as thread scheduling may become sluggish."
131 cdl_option CYGNUM_HAL_RTC_PERIOD {
132 display "Real-time clock period"
134 calculated (3686400/CYGNUM_HAL_RTC_DENOMINATOR) ;# Clock for OS Timer is 3.6864MHz
138 # Control over hardware layout.
139 cdl_interface CYGHWR_HAL_ARM_SOC_UART1 {
140 display "UART1 available as diagnostic/debug channel"
142 The chip has multiple serial channels which may be
143 used for different things on different platforms. This
144 interface allows a platform to indicate that the specified
145 serial port can be used as a diagnostic and/or debug channel."
148 cdl_interface CYGHWR_HAL_ARM_SOC_UART2 {
149 display "UART2 available as diagnostic/debug channel"
151 The chip has multiple serial channels which may be
152 used for different things on different platforms. This
153 interface allows a platform to indicate that the specified
154 serial port can be used as a diagnostic and/or debug channel."
157 cdl_interface CYGHWR_HAL_ARM_SOC_UART3 {
158 display "UART3 available as diagnostic/debug channel"
160 The chip has multiple serial channels which may be
161 used for different things on different platforms. This
162 interface allows a platform to indicate that the specified
163 serial port can be used as a diagnostic and/or debug channel."
166 cdl_interface CYGHWR_HAL_ARM_SOC_UART4 {
167 display "UART4 available as diagnostic/debug channel"
169 The chip has multiple serial channels which may be
170 used for different things on different platforms. This
171 interface allows a platform to indicate that the specified
172 serial port can be used as a diagnostic and/or debug channel."
175 cdl_interface CYGHWR_HAL_ARM_SOC_UART5 {
176 display "UART5 available as diagnostic/debug channel"
178 The chip has multiple serial channels which may be
179 used for different things on different platforms. This
180 interface allows a platform to indicate that the specified
181 serial port can be used as a diagnostic and/or debug channel."