1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include CYGBLD_HAL_PLF_DEFS_H // Platform specific hardware definitions
51 #include CYGHWR_MEMORY_LAYOUT_H
53 #define CPU_CLK CYGNUM_HAL_ARM_TX53_CPU_CLK
55 #if defined(CYGNUM_HAL_ARM_TX53_DDR2_CLK)
56 #define SDRAM_CLK CYGNUM_HAL_ARM_TX53_DDR2_CLK
57 #elif defined(CYGNUM_HAL_ARM_TX53_DDR3_CLK)
58 #define SDRAM_CLK CYGNUM_HAL_ARM_TX53_DDR3_CLK
60 #error SDRAM clock not defined
63 #define DEBUG_LED_BIT 20
64 #define LED_GPIO_BASE GPIO2_BASE_ADDR
65 #define LED_MUX_OFFSET 0x174
66 #define LED_MUX_MODE 0x11
68 #ifdef CYGOPT_HAL_ARM_TX53_DEBUG
69 #define LED_ON bl led_on
70 #define LED_OFF bl led_off
76 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
77 #define PLATFORM_SETUP1 _platform_setup1
78 #define CYGHWR_HAL_ARM_HAS_MMU
80 #ifdef CYG_HAL_STARTUP_ROMRAM
81 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
84 #define TX53_NAND_PAGE_SIZE 2048
85 #define TX53_NAND_BLKS_PER_PAGE 64
87 #define PLATFORM_PREAMBLE flash_header
89 // This macro represents the initial startup code for the platform
90 .macro _platform_setup1
91 KARO_TX53_SETUP_START:
100 mov r0, #0 @ set up for MCR
101 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
102 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
105 * disable MMU stuff and caches
107 mrc p15, 0, r0, c1, c0, 0
108 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
109 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
110 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
111 orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB
112 mcr p15, 0, r0, c1, c0, 0
116 /* ARM errata ID #468414 */
117 mrc 15, 0, r1, c1, c0, 1
118 orr r1, r1, #(1 << 5) /* enable L1NEON bit */
119 mcr 15, 0, r1, c1, c0, 1
121 // Explicitly disable L2 cache
122 mrc 15, 0, r0, c1, c0, 1
124 mcr 15, 0, r0, c1, c0, 1
126 // reconfigure L2 cache aux control reg
127 mov r0, #0xC0 // tag RAM
128 add r0, r0, #0x4 // data RAM
129 orr r0, r0, #(1 << 24) // disable write allocate delay
130 orr r0, r0, #(1 << 23) // disable write allocate combine
131 orr r0, r0, #(1 << 22) // disable write allocate
133 mcr 15, 1, r0, c9, c0, 2
137 /* switch off LCD backlight */
138 ldr r10, =GPIO1_BASE_ADDR
140 ldr r9, [r10, #GPIO_DR]
141 orr r9, r9, #(1 << 1)
142 str r9, [r10, #GPIO_DR]
144 ldr r9, [r10, #GPIO_GDIR]
145 orr r9, r9, #(1 << 1)
146 str r9, [r10, #GPIO_GDIR]
155 Normal_Boot_Continue:
158 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
161 @ Set up a stack [for calling C code]
162 ldr r1, =__startup_stack
163 ldr r2, =RAM_BANK0_BASE
170 /* Workaround for arm erratum #709718 */
171 @ Setup PRRR so device is always mapped to non-shared
172 mrc MMU_CP, 0, r1, c10, c2, 0 // Read Primary Region Remap Register
174 mcr MMU_CP, 0, r1, c10, c2, 0 // Write Primary Region Remap Register
178 mrc MMU_CP, 0, r1, MMU_Control, c0
179 orr r1, r1, #7 @ enable MMU bit
180 orr r1, r1, #0x800 @ enable z bit
181 orr r1, r1, #(1 << 28) @ Enable TEX remap, workaround for L1 cache issue
182 mcr MMU_CP, 0, r1, MMU_Control, c0
184 /* Workaround for arm errata #621766 */
185 mrc MMU_CP, 0, r1, MMU_Control, c0, 1
186 orr r1, r1, #(1 << 5) @ enable L1NEON bit
187 mcr MMU_CP, 0, r1, MMU_Control, c0, 1
189 mov pc, r2 @ Change address spaces
193 .endm @ _platform_setup1
195 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
198 * Set all MPROTx to be non-bufferable, trusted for R/W,
199 * not forced to user-mode.
201 ldr r0, =AIPS1_CTRL_BASE_ADDR
205 ldr r0, =AIPS2_CTRL_BASE_ADDR
208 .endm /* init_aips */
211 ldr r0, =CCM_BASE_ADDR
212 ldr r1, [r0, #CLKCTL_CCR]
216 orr r1, r1, #(1 << 12)
217 str r1, [r0, #CLKCTL_CCR]
219 /* Switch ARM to step clock */
221 str r1, [r0, #CLKCTL_CCSR]
224 setup_pll PLL1_BASE_ADDR, 1000
226 setup_pll PLL1_BASE_ADDR, 800
230 setup_pll PLL3_BASE_ADDR, 400
232 /* Switch peripherals to PLL3 */
233 ldr r1, CCM_CBCMR_VAL1
234 str r1, [r0, #CLKCTL_CBCMR]
236 ldr r1, CCM_CBCDR_VAL1
237 str r1, [r0, #CLKCTL_CBCDR]
239 /* make sure change is effective */
240 ldr r1, [r0, #CLKCTL_CDHIPR]
246 setup_pll PLL2_BASE_ADDR, 400
247 #elif SDRAM_CLK == 333
248 setup_pll PLL2_BASE_ADDR, 333
249 #elif SDRAM_CLK == 266
250 setup_pll PLL2_BASE_ADDR, 266
251 #elif SDRAM_CLK == 216
252 setup_pll PLL2_BASE_ADDR, 216
253 #elif SDRAM_CLK == 666
254 setup_pll PLL2_BASE_ADDR, 666
258 /* Switch peripheral to PLL2 */
259 ldr r1, CCM_CBCDR_VAL2
260 str r1, [r0, #CLKCTL_CBCDR]
262 ldr r1, CCM_CBCMR_VAL2
263 str r1, [r0, #CLKCTL_CBCMR]
265 /* make sure change is effective */
267 ldr r1, [r0, #CLKCTL_CDHIPR]
272 setup_pll PLL3_BASE_ADDR, 216
274 /* Set the platform clock dividers */
275 ldr r2, =PLATFORM_BASE_ADDR
276 ldr r1, PLATFORM_CLOCK_DIV
277 str r1, [r2, #PLATFORM_ICGC]
280 str r1, [r0, #CLKCTL_CACRR] /* ARM podf */
282 /* Switch ARM back to PLL 1. */
284 str r1, [r0, #CLKCTL_CCSR]
288 str r1, [r0, #CLKCTL_CSCDR1]
290 str r1, [r0, #CLKCTL_CSCMR1]
293 str r1, [r0, #CLKCTL_CCDR]
295 /* for cko - for ARM div by 8 */
297 orr r1, r1, #0x00000F0
298 str r1, [r0, #CLKCTL_CCOSR]
302 .macro setup_pll pll, mhz
305 str r1, [r2, #PLL_DP_CTL] @ Set DPLL ON (set UPEN bit); BRMO=1
307 str r1, [r2, #PLL_DP_CONFIG] @ Enable auto-restart AREN bit
310 str r1, [r2, #PLL_DP_OP]
311 str r1, [r2, #PLL_DP_HFS_OP]
313 ldr r1, W_DP_MFD_\mhz
314 str r1, [r2, #PLL_DP_MFD]
315 str r1, [r2, #PLL_DP_HFS_MFD]
317 ldr r1, W_DP_MFN_\mhz
318 str r1, [r2, #PLL_DP_MFN]
319 str r1, [r2, #PLL_DP_HFS_MFN]
321 /* Now restart PLL */
323 str r1, [r2, #PLL_DP_CTL]
325 ldr r1, [r2, #PLL_DP_CTL]
332 /* Decrease the DRAM SDCLK pads to HIGH Drive strength */
333 ldr r0, =IOMUXC_BASE_ADDR
336 /* Change the delay line configuration */
337 ldr r0, =ESDCTL_BASE_ADDR
339 str r1, [r0, #ESDCTL_ESDCDLY1]
341 str r1, [r0, #ESDCTL_ESDCDLY2]
343 str r1, [r0, #ESDCTL_ESDCDLY3]
345 str r1, [r0, #ESDCTL_ESDCDLY4]
347 str r1, [r0, #ESDCTL_ESDCDLY5]
350 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
351 #define PLATFORM_SETUP1
353 #ifndef CYGOPT_HAL_ARM_TX53_DEBUG
359 #define CYGHWR_LED_MACRO LED_BLINK \x
373 // initialize GPIO4_10 (PAD CSI2_D13) for LED on STK5
374 ldr r10, =LED_GPIO_BASE
376 ldr r9, [r10, #GPIO_DR]
377 bic r9, #(1 << DEBUG_LED_BIT) @ LED OFF
378 str r9, [r10, #GPIO_DR]
380 ldr r9, [r10, #GPIO_GDIR]
381 orr r9, r9, #(1 << DEBUG_LED_BIT)
382 str r9, [r10, #GPIO_GDIR]
384 ldr r10, =IOMUXC_BASE_ADDR
385 mov r9, #LED_MUX_MODE
386 str r9, [r10, #LED_MUX_OFFSET]
389 #ifdef CYGOPT_HAL_ARM_TX53_DEBUG
391 ldr r10, =LED_GPIO_BASE
393 ldr r9, [r10, #GPIO_DR]
394 orr r9, #(1 << DEBUG_LED_BIT) @ LED ON
395 str r9, [r10, #GPIO_DR]
399 ldr r10, =LED_GPIO_BASE
401 ldr r9, [r10, #GPIO_DR]
402 bic r9, #(1 << DEBUG_LED_BIT) @ LED OFF
403 str r9, [r10, #GPIO_DR]
410 ldr r9, =(36000 / 10 / 10)
432 #define PLATFORM_VECTORS _platform_vectors
433 .macro _platform_vectors
437 .globl _KARO_STRUCT_SIZE
439 .word 0 // reserve space structure length
441 .globl _KARO_CECFG_START
444 .word 0 // reserve space for CE configuration
447 .globl _KARO_CECFG_END
452 .ascii "KARO TX53 " __DATE__ " " __TIME__
455 #define CPU_2_BE_32(l) \
456 ((((l) << 24) & 0xFF000000) | \
457 (((l) << 8) & 0x00FF0000) | \
458 (((l) >> 8) & 0x0000FF00) | \
459 (((l) >> 24) & 0x000000FF))
461 #define MXC_DCD_ITEM(addr, val) \
462 .word CPU_2_BE_32(addr) ; \
463 .word CPU_2_BE_32(val)
465 #define MXC_DCD_CMD_SZ_BYTE 1
466 #define MXC_DCD_CMD_SZ_SHORT 2
467 #define MXC_DCD_CMD_SZ_WORD 4
468 #define MXC_DCD_CMD_FLAG_WRITE 0x0
469 #define MXC_DCD_CMD_FLAG_CLR 0x2
470 #define MXC_DCD_CMD_FLAG_SET 0x3
471 #define MXC_DCD_CMD(type, flags, next) \
472 .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
474 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
476 .macro CK_VAL, name, clks, offs, max
480 .ifle \clks - \offs - \max
481 .set \name, \clks - \offs
486 .macro NS_VAL, name, ns, offs, max
490 CK_VAL \name, NS_TO_CK(\ns), \offs, \max
494 .macro CK_MAX, name, ck1, ck2, offs, max
496 CK_VAL \name, \ck1, \offs, \max
498 CK_VAL \name, \ck2, \offs, \max
502 #define SDRAM_TYPE_DDR2 2
503 #define SDRAM_TYPE_DDR3 3
505 #define ESDMISC_DDR_TYPE_DDR3 0
506 #define ESDMISC_DDR_TYPE_LPDDR2 1
507 #define ESDMISC_DDR_TYPE_DDR2 2
509 #define ESDOR_CLK_PERIOD 15625 /* base clock for ESDOR values 15.625uS */
511 #if CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == SDRAM_TYPE_DDR2
512 #define SDRAM_BURST_LENGTH 4
513 #define BANK_ADDR_BITS 1
514 #define COL_ADDR_BITS 10
517 #define ADDR_MIRROR 0
518 #define DDR_TYPE ESDMISC_DDR_TYPE_DDR2
520 #if SDRAM_SIZE > SZ_512M
521 #define ROW_ADDR_BITS 15
523 /* 1GiB SDRAM: MEM2G08D2DABG */
525 NS_VAL tRFC, 195, 1, 255 /* clks - 1 (0..255) */
526 CK_VAL tXS, tRFC + 1 + NS_TO_CK(10), 1, 255 /* clks - 1 (0..255) tRFC + 10 */
527 CK_VAL tXP, 2, 1, 7 /* clks - 1 (0..7) */
528 CK_VAL tXPDLL /* => tXARD */, 2, 1, 15 /* clks - 1 (0..15) */
529 NS_VAL tFAW, 35, 1, 31 /* clks - 1 (0..31) */
530 CK_VAL tCL, 5, 3, 8 /* clks - 3 (0..8) CAS Latency */
533 NS_VAL tRCD, 13, 1, 7 /* clks - 1 (0..7) */
534 NS_VAL tRP, 13, 1, 7 /* clks - 1 (0..7) */
535 NS_VAL tRC, 58, 1, 31 /* clks - 1 (0..31) */
536 NS_VAL tRAS, 45, 1, 31 /* clks - 1 (0..31) */
537 CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */
538 NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
539 CK_VAL tMRD, 2, 1, 15 /* clks - 1 (0..15) */
540 CK_VAL tCWL, tCL + 3 - 1, 2, 6 /* clks - 2 (0..6) tCL - 1 */
543 CK_VAL tDLLK, 200, 1, 511 /* clks - 1 (0..511) */
544 NS_VAL tRTP, 8, 1, 7 /* clks - 1 (0..7) */
545 NS_VAL tWTR, 8, 1, 7 /* clks - 1 (0..7) */
546 NS_VAL tRRD, 8, 1, 6 /* clks - 1 (0..6) */
548 #define ROW_ADDR_BITS 14
550 /* 512MiB SDRAM: V59C1G01(808) */
552 NS_VAL tRFC, 128, 1, 255 /* clks - 1 (0..255) */
553 CK_VAL tXS, tRFC + 1 + NS_TO_CK(10), 1, 255 /* clks - 1 (0..255) tRFC + 10 */
554 CK_VAL tXP, 2, 1, 7 /* clks - 1 (0..7) */
555 CK_VAL tXPDLL, /* tXARD */ 2, 1, 15 /* clks - 1 (0..15) */
556 NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) */
557 CK_VAL tCL, 5, 3, 8 /* clks - 3 (0..8) CAS Latency */
560 NS_VAL tRCD, 15, 1, 7 /* clks - 1 (0..7) */
561 NS_VAL tRP, 15, 1, 7 /* clks - 1 (0..7) */
562 NS_VAL tRC, 60, 1, 31 /* clks - 1 (0..31) */
563 NS_VAL tRAS, 45, 1, 31 /* clks - 1 (0..31) */
564 CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */
565 NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
566 CK_VAL tMRD, 2, 1, 15 /* clks - 1 (0..15) */
567 CK_VAL tCWL, tCL + 3 - 1, 2, 6 /* clks - 2 (0..6) tCL - 1 */
570 CK_VAL tDLLK, 200, 1, 511 /* clks - 1 (0..511) */
571 NS_VAL tRTP, 8, 1, 7 /* clks - 1 (0..7) */
572 CK_VAL tWTR, 2, 1, 7 /* clks - 1 (0..7) */
573 NS_VAL tRRD, 10, 1, 6 /* clks - 1 (0..6) */
577 NS_VAL tXPR, 400, 1, 255 /* clks - 1 (1..255) */
579 #define tSDE_RST 0 /* not relevant for DDR2 */
580 #define tRST_CKE ((200000 + (ESDOR_CLK_PERIOD - 1)) / ESDOR_CLK_PERIOD)
582 #define ESDSCR_MRS_VAL (0x8000 | (3 << 4) | \
583 ((((tCL + 3) << 4) | \
585 ((1 - (SDRAM_BURST_LENGTH / 8)) << 1)) << 16))
587 #elif CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == SDRAM_TYPE_DDR3
589 #if SDRAM_SIZE > SZ_512M
590 #define BANK_ADDR_BITS 2
592 #define BANK_ADDR_BITS 1
594 #define SDRAM_BURST_LENGTH 8
597 #define ADDR_MIRROR 0
598 #define DDR_TYPE ESDMISC_DDR_TYPE_DDR3
600 /* 512/1024MiB SDRAM: NT5CB128M16P-CG */
602 NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
603 CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
604 CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
605 CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
606 NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
607 CK_VAL tCL, 9, 3, 8 /* clks - 3 (0..8) CAS Latency */
610 NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
611 NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
612 NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
613 NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
614 CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
615 NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
616 CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
617 CK_VAL tCWL, 7, 2, 6 /* clks - 2 (0..6) */
620 CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
621 CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
622 CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
623 CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
626 CK_MAX tXPR, NS_TO_CK(160 + 10), 5, 1, 255 /* max(tRFC + 10, 5CK) */
628 #define tSDE_RST ((200000 + (ESDOR_CLK_PERIOD - 1)) / ESDOR_CLK_PERIOD)
629 #define tRST_CKE ((500000 + (ESDOR_CLK_PERIOD - 1)) / ESDOR_CLK_PERIOD)
631 #define ROW_ADDR_BITS 14
632 #define COL_ADDR_BITS 10
635 .set ESDSCR_MRS_VAL, (0x8000 | (3 << 4) | \
636 (((tWR - 3) << 9) | \
637 (((tCL + 3) - 4) << 4)) << 16)
639 .set ESDSCR_MRS_VAL, (0x8000 | (3 << 4) | \
640 ((((tWR + 1) / 2) << 9) | \
641 (((tCL + 3) - 4) << 4)) << 16)
645 #error Unsupported SDRAM type selected
648 #define ESDCFG0_VAL ( \
656 #define ESDCFG1_VAL ( \
666 #define ESDCFG2_VAL ( \
672 #define BL (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
673 #define ESDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
674 ((COL_ADDR_BITS - 9) << 20) | \
676 (1 << 16) | /* SDRAM bus width */ \
677 ((-1) << (32 - BANK_ADDR_BITS)))
679 #define ESDMISC_VAL ((1 << 12) | \
683 (ADDR_MIRROR << 19) | \
686 #define ESDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
692 .word 0x20424346 /* "FCB " marker */
693 .word 0x01 /* FCB version number */
695 .word 0x0 /* primary image starting page number */
696 .word 0x0 /* secondary image starting page number */
699 .word 0x0 /* DBBT start page (0 == NO DBBT) */
700 .word 0 /* Bad block marker offset in main area (unused) */
702 .word 0 /* BI Swap disabled */
703 .word 0 /* Bad Block marker offset in spare area */
770 #define ESDCFG0_VAL 0x9f5152e3
771 #define ESDCFG1_VAL 0xb68e8a63
772 #define ESDMISC_VAL 0x00011740
782 .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
798 .long REDBOOT_IMAGE_SIZE
803 #define DCD_VERSION 0x40
806 .word CPU_2_BE_32((0xd2 << 24) |
807 ((dcd_end - .) << 8) | DCD_VERSION)
809 MXC_DCD_CMD(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end)
810 /* disable all irrelevant clocks */
811 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR0, 0xffcc00cf)
812 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR1, 0x000fffc3)
813 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR2, 0x033c0000)
814 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR3, 0x00000000)
815 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR4, 0x00000000)
816 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR5, 0x00fff033)
817 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR6, 0x0f00030f)
818 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR7, 0xfff00000)
819 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CMEOR, 0x00000000)
821 MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x174, 0x00000011) /* EIM_D18 => GPIO2[20] STK5-LED */
823 MXC_DCD_ITEM(0x63fd800c, 0x00000000) /* M4IF: MUX NFC signals on WEIM */
824 #if CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == SDRAM_TYPE_DDR2
825 /* setup SDRAM pads */
826 MXC_DCD_ITEM(0x53fa8554, 0x00200000) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
827 MXC_DCD_ITEM(0x53fa8560, 0x00200000) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
828 MXC_DCD_ITEM(0x53fa8594, 0x00200000) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
829 MXC_DCD_ITEM(0x53fa8584, 0x00200000) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
831 MXC_DCD_ITEM(0x53fa8558, 0x00200040) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
832 MXC_DCD_ITEM(0x53fa8568, 0x00200040) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
833 MXC_DCD_ITEM(0x53fa8590, 0x00200040) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
834 MXC_DCD_ITEM(0x53fa857c, 0x00200040) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
836 MXC_DCD_ITEM(0x53fa8564, 0x00200040) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
837 MXC_DCD_ITEM(0x53fa8580, 0x00200040) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
838 MXC_DCD_ITEM(0x53fa8570, 0x00200000) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
839 MXC_DCD_ITEM(0x53fa8578, 0x00200000) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
841 MXC_DCD_ITEM(0x53fa872c, 0x00200000) @ IOMUXC_SW_PAD_CTL_GRP_B3DS
842 MXC_DCD_ITEM(0x53fa8728, 0x00200000) @ IOMUXC_SW_PAD_CTL_GRP_B2DS
843 MXC_DCD_ITEM(0x53fa871c, 0x00200000) @ IOMUXC_SW_PAD_CTL_GRP_B1DS
844 MXC_DCD_ITEM(0x53fa8718, 0x00200000) @ IOMUXC_SW_PAD_CTL_GRP_B0DS
846 MXC_DCD_ITEM(0x53fa8574, 0x00280000) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
847 MXC_DCD_ITEM(0x53fa8588, 0x00280000) @ IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
848 MXC_DCD_ITEM(0x53fa86f0, 0x00280000) @ IOMUXC_SW_PAD_CTL_GRP_ADDDS
849 MXC_DCD_ITEM(0x53fa8720, 0x00280000) @ IOMUXC_SW_PAD_CTL_GRP_CTLDS
851 MXC_DCD_ITEM(0x53fa86fc, 0x00000000) @ IOMUXC_SW_PAD_CTL_GRP_DDRPKE
853 #if CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == SDRAM_TYPE_DDR2
854 MXC_DCD_ITEM(0x53fa86f4, 0x00000200) @ IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DQS DIFF mode
855 MXC_DCD_ITEM(0x53fa8714, 0x00000000) @ IOMUXC_SW_PAD_CTL_GRP_DDRMODE - Data CMOS mode
856 MXC_DCD_ITEM(0x53fa8724, 0x06000000) @ IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=01
858 MXC_DCD_ITEM(0x53fa86f4, 0x00000000) @ IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DQS DIFF mode
859 MXC_DCD_ITEM(0x53fa8714, 0x00000000) @ IOMUXC_SW_PAD_CTL_GRP_DDRMODE - Data CMOS mode
860 MXC_DCD_ITEM(0x53fa8724, 0x04000000) @ IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=10
862 /* memory timing setup */
863 MXC_DCD_ITEM(0x63fd9088, 0x36353b38)
864 MXC_DCD_ITEM(0x63fd9090, 0x49434942)
865 MXC_DCD_ITEM(0x63fd90F8, 0x00000800)
866 MXC_DCD_ITEM(0x63fd907c, 0x01350138)
867 MXC_DCD_ITEM(0x63fd9080, 0x01380139)
868 MXC_DCD_ITEM(0x63fd9018, ESDMISC_VAL) @ ESDMISC
869 MXC_DCD_ITEM(0x63fd9000, ESDCTL_VAL)
870 MXC_DCD_ITEM(0x63fd900c, ESDCFG0_VAL)
871 MXC_DCD_ITEM(0x63fd9010, ESDCFG1_VAL)
872 MXC_DCD_ITEM(0x63fd9014, ESDCFG2_VAL)
874 MXC_DCD_ITEM(0x63fd902c, 0x000026d2) @ command delay
875 MXC_DCD_ITEM(0x63fd9030, ESDOR_VAL) @ out of reset delays
876 MXC_DCD_ITEM(0x63fd9008, 0x12273030) @ ODT timings
877 MXC_DCD_ITEM(0x63fd9004, 0x00030012) @ Power down control
879 /*********************************
880 * DDR device configuration:
881 **********************************/
883 #if CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == SDRAM_TYPE_DDR2
884 MXC_DCD_ITEM(0x63fd901c, 0x04008010)
885 MXC_DCD_ITEM(0x63fd901c, 0x00008020)
886 MXC_DCD_ITEM(0x63fd901c, 0x00008020)
888 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL)
889 //MXC_DCD_ITEM(0x63fd901c, 0x0a528030) @ MRS: BL: 4, BT: seq, CL: 5, WR: 6
890 #if CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == SDRAM_TYPE_DDR2
891 MXC_DCD_ITEM(0x63fd901c, 0x03868031) @ EMRS(1): OCD calibration default
892 MXC_DCD_ITEM(0x63fd901c, 0x00068031) @ EMRS(1): OCD calibration exit
893 MXC_DCD_ITEM(0x63fd901c, 0x00008032) @ EMRS(2): 0
895 MXC_DCD_ITEM(0x63fd901c, 0x00008032) @ MR2: 0
896 MXC_DCD_ITEM(0x63fd901c, 0x00008032) @ MR3: 0
897 MXC_DCD_ITEM(0x63fd901c, 0x00028031) @ MR1:
898 MXC_DCD_ITEM(0x63fd901c, 0x092080b0) @ MR0: WHY 80b0 instead of 8030? Undocumented bit# 7?
899 MXC_DCD_ITEM(0x63fd901c, 0x04008040)
901 #if BANK_ADDR_BITS > 1
902 #if CYGNUM_HAL_ARM_TX53_SDRAM_TYPE == SDRAM_TYPE_DDR2
903 MXC_DCD_ITEM(0x63fd901c, 0x04008018)
904 MXC_DCD_ITEM(0x63fd901c, 0x00008028)
905 MXC_DCD_ITEM(0x63fd901c, 0x00008028)
907 MXC_DCD_ITEM(0x63fd901c, 0x0a528038) @ MRS: BL: 4, BT: seq, CL: 5, WR: 6
908 MXC_DCD_ITEM(0x63fd901c, 0x03868039) @ EMRS(1): OCD calibration default
909 MXC_DCD_ITEM(0x63fd901c, 0x00068039) @ EMRS(1): OCD calibration exit
910 MXC_DCD_ITEM(0x63fd901c, 0x0000803a) @ EMRS(2): 0
912 MXC_DCD_ITEM(0x63fd9020, 0x00005800)
913 MXC_DCD_ITEM(0x63fd9058, 0x00033332) @ ODT control: 50Ohms, ODT act enable
914 MXC_DCD_ITEM(0x63fd901c, 0x00000000)
916 MXC_DCD_ITEM(0x63fd901c, 0x00448031) @ full drive strength, enable 50ohm ODT
917 MXC_DCD_ITEM(0x63fd901c, 0x04008018)
918 MXC_DCD_ITEM(0x63fd901c, 0x00000000)
920 /* Enable ZQ calibration to tightly control the impedance of the DDR IO pads */
921 MXC_DCD_ITEM(0x63fd9040, 0x04b80003) @ keep ZQ HW control values and enable it
923 MXC_DCD_ITEM(0x53fa8554, 0x00300000)
924 MXC_DCD_ITEM(0x53fa8560, 0x00300000)
925 MXC_DCD_ITEM(0x53fa8594, 0x00300000)
926 MXC_DCD_ITEM(0x53fa8584, 0x00300000)
928 MXC_DCD_ITEM(0x53fa8558, 0x00f00000)
929 MXC_DCD_ITEM(0x53fa8568, 0x00f00000)
930 MXC_DCD_ITEM(0x53fa8590, 0x00f00000)
931 MXC_DCD_ITEM(0x53fa857c, 0x00f00000)
933 MXC_DCD_ITEM(0x53fa8564, 0x00300040)
934 MXC_DCD_ITEM(0x53fa8580, 0x00300040)
935 MXC_DCD_ITEM(0x53fa8570, 0x00300000)
936 MXC_DCD_ITEM(0x53fa8578, 0x00300000)
938 MXC_DCD_ITEM(0x53fa872c, 0x00300000)
939 MXC_DCD_ITEM(0x53fa8728, 0x00300000)
940 MXC_DCD_ITEM(0x53fa871c, 0x00300000)
941 MXC_DCD_ITEM(0x53fa8718, 0x00300000)
943 MXC_DCD_ITEM(0x53fa8574, 0x00300000)
944 MXC_DCD_ITEM(0x53fa8588, 0x00300000)
945 MXC_DCD_ITEM(0x53fa86f0, 0x00300000)
946 MXC_DCD_ITEM(0x53fa8720, 0x00300000)
948 MXC_DCD_ITEM(0x53fa86fc, 0x00000000)
950 MXC_DCD_ITEM(0x53fa86f4, 0x00000000)
951 MXC_DCD_ITEM(0x53fa8714, 0x00000000)
953 MXC_DCD_ITEM(0x53fa8724, 0x04000000)
955 MXC_DCD_ITEM(0x63fd9088, 0x35343535)
956 MXC_DCD_ITEM(0x63fd9090, 0x4d444c44)
957 MXC_DCD_ITEM(0x63fd907c, 0x01370138)
958 MXC_DCD_ITEM(0x63fd9080, 0x013b013c)
960 MXC_DCD_ITEM(0x63fd9018, 0x00011740)
961 MXC_DCD_ITEM(0x63fd9000, 0xc3190000)
962 MXC_DCD_ITEM(0x63fd900c, 0x9f5152e3)
963 MXC_DCD_ITEM(0x63fd9010, 0xb68e8a63)
964 MXC_DCD_ITEM(0x63fd9014, 0x01ff00db)
966 MXC_DCD_ITEM(0x63fd902c, 0x000026d2)
967 MXC_DCD_ITEM(0x63fd9030, 0x009f0e21)
968 MXC_DCD_ITEM(0x63fd9008, 0x12273030)
969 MXC_DCD_ITEM(0x63fd9004, 0x0002002d)
971 MXC_DCD_ITEM(0x63fd901c, 0x00008032)
972 MXC_DCD_ITEM(0x63fd901c, 0x00008033)
973 MXC_DCD_ITEM(0x63fd901c, 0x00028031)
974 MXC_DCD_ITEM(0x63fd901c, 0x092080b0)
975 MXC_DCD_ITEM(0x63fd901c, 0x04008040)
977 #if SDRAM_SIZE > SZ_512M
978 MXC_DCD_ITEM(0x63fd901c, 0x0000803a)
979 MXC_DCD_ITEM(0x63fd901c, 0x0000803b)
980 MXC_DCD_ITEM(0x63fd901c, 0x00028039)
981 MXC_DCD_ITEM(0x63fd901c, 0x09208138)
983 MXC_DCD_ITEM(0x63fd901c, 0x04008048)
985 MXC_DCD_ITEM(0x63fd9020, 0x00005800)
986 MXC_DCD_ITEM(0x63fd9040, 0x04b80003)
987 MXC_DCD_ITEM(0x63fd9058, 0x00022227)
988 MXC_DCD_ITEM(0x63fd901c, 0x00000000)
990 MXC_DCD_ITEM(0x53fa8004, 0x00194005) @ set LDO to 1.3V
994 MXC_DCD_ITEM(0x53fa819c, 0x00000000) @ EIM_DA0
995 MXC_DCD_ITEM(0x53fa81a0, 0x00000000) @ EIM_DA1
996 MXC_DCD_ITEM(0x53fa81a4, 0x00000000) @ EIM_DA2
997 MXC_DCD_ITEM(0x53fa81a8, 0x00000000) @ EIM_DA3
998 MXC_DCD_ITEM(0x53fa81ac, 0x00000000) @ EIM_DA4
999 MXC_DCD_ITEM(0x53fa81b0, 0x00000000) @ EIM_DA5
1000 MXC_DCD_ITEM(0x53fa81b4, 0x00000000) @ EIM_DA6
1001 MXC_DCD_ITEM(0x53fa81b8, 0x00000000) @ EIM_DA7
1002 MXC_DCD_ITEM(0x53fa81dc, 0x00000000) @ WE_B
1003 MXC_DCD_ITEM(0x53fa81e0, 0x00000000) @ RE_B
1004 MXC_DCD_ITEM(0x53fa8228, 0x00000000) @ CLE
1005 MXC_DCD_ITEM(0x53fa822c, 0x00000000) @ ALE
1006 MXC_DCD_ITEM(0x53fa8230, 0x00000000) @ WP_B
1007 MXC_DCD_ITEM(0x53fa8234, 0x00000000) @ RB0
1008 MXC_DCD_ITEM(0x53fa8238, 0x00000000) @ CS0
1010 MXC_DCD_ITEM(0x53fa84ec, 0x000000e4) @ EIM_DA0
1011 MXC_DCD_ITEM(0x53fa84f0, 0x000000e4) @ EIM_DA1
1012 MXC_DCD_ITEM(0x53fa84f4, 0x000000e4) @ EIM_DA2
1013 MXC_DCD_ITEM(0x53fa84f8, 0x000000e4) @ EIM_DA3
1014 MXC_DCD_ITEM(0x53fa84fc, 0x000000e4) @ EIM_DA4
1015 MXC_DCD_ITEM(0x53fa8500, 0x000000e4) @ EIM_DA5
1016 MXC_DCD_ITEM(0x53fa8504, 0x000000e4) @ EIM_DA6
1017 MXC_DCD_ITEM(0x53fa8508, 0x000000e4) @ EIM_DA7
1018 MXC_DCD_ITEM(0x53fa852c, 0x00000004) @ NANDF_WE_B
1019 MXC_DCD_ITEM(0x53fa8530, 0x00000004) @ NANDF_RE_B
1020 MXC_DCD_ITEM(0x53fa85a0, 0x00000004) @ NANDF_CLE_B
1021 MXC_DCD_ITEM(0x53fa85a4, 0x00000004) @ NANDF_ALE_B
1022 MXC_DCD_ITEM(0x53fa85a8, 0x000000e4) @ NANDF_WE_B
1023 MXC_DCD_ITEM(0x53fa85ac, 0x000000e4) @ NANDF_RB0
1024 MXC_DCD_ITEM(0x53fa85b0, 0x00000004) @ NANDF_CS0
1028 AIPS1_PARAM: .word 0x77777777
1029 MXC_REDBOOT_ROM_START: .long SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
1032 CCM_CBCDR_VAL1: .word 0x02888944
1033 CCM_CBCMR_VAL1: .word 0x00015154
1034 CCM_CBCDR_VAL2: .word 0x00888944
1035 CCM_CBCMR_VAL2: .word 0x00016154
1037 CCM_CBCDR_VAL1: .word 0x02888644
1038 CCM_CBCMR_VAL1: .word 0x00015154
1039 CCM_CBCDR_VAL2: .word 0x00888644
1040 CCM_CBCMR_VAL2: .word 0x00016154
1043 W_CSCMR1_VAL: .word 0xa6a2a020
1044 W_CSCDR1_VAL: .word 0x00080b18
1045 W_DP_OP_1000: .word DP_OP_1000
1046 W_DP_MFD_1000: .word DP_MFD_1000
1047 W_DP_MFN_1000: .word DP_MFN_1000
1048 W_DP_OP_800: .word DP_OP_800
1049 W_DP_MFD_800: .word DP_MFD_800
1050 W_DP_MFN_800: .word DP_MFN_800
1051 W_DP_OP_700: .word DP_OP_700
1052 W_DP_MFD_700: .word DP_MFD_700
1053 W_DP_MFN_700: .word DP_MFN_700
1054 W_DP_OP_400: .word DP_OP_400
1055 W_DP_MFD_400: .word DP_MFD_400
1056 W_DP_MFN_400: .word DP_MFN_400
1057 W_DP_OP_532: .word DP_OP_532
1058 W_DP_MFD_532: .word DP_MFD_532
1059 W_DP_MFN_532: .word DP_MFN_532
1060 W_DP_OP_666: .word DP_OP_666
1061 W_DP_MFD_666: .word DP_MFD_666
1062 W_DP_MFN_666: .word DP_MFN_666
1063 W_DP_OP_665: .word DP_OP_665
1064 W_DP_MFD_665: .word DP_MFD_665
1065 W_DP_MFN_665: .word DP_MFN_665
1066 W_DP_OP_216: .word DP_OP_216
1067 W_DP_MFD_216: .word DP_MFD_216
1068 W_DP_MFN_216: .word DP_MFN_216
1069 W_DP_OP_333: .word DP_OP_333
1070 W_DP_MFD_333: .word DP_MFD_333
1071 W_DP_MFN_333: .word DP_MFN_333
1072 W_DP_OP_266: .word DP_OP_266
1073 W_DP_MFD_266: .word DP_MFD_266
1074 W_DP_MFN_266: .word DP_MFN_266
1075 PLATFORM_CLOCK_DIV: .word 0x00000124
1077 /*----------------------------------------------------------------------*/
1078 /* end of hal_platform_setup.h */
1079 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */