4 * Common board functions for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mem.h>
21 #include <asm/arch/mmc_host_def.h>
22 #include <asm/arch/sys_proto.h>
29 #include <asm/errno.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/musb.h>
33 #include <asm/omap_musb.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 static const struct gpio_bank gpio_bank_am33xx[4] = {
38 { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
39 { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
40 { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
41 { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
44 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
46 #ifdef CONFIG_HW_WATCHDOG
47 void hw_watchdog_reset(void)
49 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
50 static int trg __attribute__((section(".data")));
55 if (readl(&wdtimer->wdtwwps) & (1 << 4))
57 writel(trg ? 0x5555 : 0xaaaa, &wdtimer->wdtwspr);
60 if (readl(&wdtimer->wdtwwps) & (1 << 2))
63 writel(-32768 * 10, &wdtimer->wdtwldr);
65 if (readl(&wdtimer->wdtwwps) & (1 << 0))
68 writel(0, &wdtimer->wdtwclr);
74 if (readl(&wdtimer->wdtwwps) & (1 << 4))
76 writel((trg & 1) ? 0xBBBB : 0x4444, &wdtimer->wdtwspr);
80 /* retrigger watchdog */
81 if (readl(&wdtimer->wdtwwps) & (1 << 3))
84 writel(trg, &wdtimer->wdtwtgr);
92 #ifndef CONFIG_SYS_DCACHE_OFF
93 void enable_caches(void)
95 /* Enable D-cache. I-cache is already enabled in start.S */
100 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
101 int cpu_mmc_init(bd_t *bis)
105 ret = omap_mmc_init(0, 0, 0, -1, -1);
109 return omap_mmc_init(1, 0, 0, -1, -1);
113 void setup_clocks_for_console(void)
115 /* Not yet implemented */
119 /* AM33XX has two MUSB controllers which can be host or gadget */
120 #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
121 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
122 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
124 /* USB 2.0 PHY Control */
125 #define CM_PHY_PWRDN (1 << 0)
126 #define CM_PHY_OTG_PWRDN (1 << 1)
127 #define OTGVDET_EN (1 << 19)
128 #define OTGSESSENDEN (1 << 20)
130 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
133 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
134 OTGVDET_EN | OTGSESSENDEN);
136 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
140 static struct musb_hdrc_config musb_config = {
147 #ifdef CONFIG_AM335X_USB0
148 static void am33xx_otg0_set_phy_power(u8 on)
150 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
153 struct omap_musb_board_data otg0_board_data = {
154 .set_phy_power = am33xx_otg0_set_phy_power,
157 static struct musb_hdrc_platform_data otg0_plat = {
158 .mode = CONFIG_AM335X_USB0_MODE,
159 .config = &musb_config,
161 .platform_ops = &musb_dsps_ops,
162 .board_data = &otg0_board_data,
166 #ifdef CONFIG_AM335X_USB1
167 static void am33xx_otg1_set_phy_power(u8 on)
169 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
172 struct omap_musb_board_data otg1_board_data = {
173 .set_phy_power = am33xx_otg1_set_phy_power,
176 static struct musb_hdrc_platform_data otg1_plat = {
177 .mode = CONFIG_AM335X_USB1_MODE,
178 .config = &musb_config,
180 .platform_ops = &musb_dsps_ops,
181 .board_data = &otg1_board_data,
186 int arch_misc_init(void)
188 #ifdef CONFIG_AM335X_USB0
189 musb_register(&otg0_plat, &otg0_board_data,
190 (void *)USB0_OTG_BASE);
192 #ifdef CONFIG_AM335X_USB1
193 musb_register(&otg1_plat, &otg1_board_data,
194 (void *)USB1_OTG_BASE);
199 #ifdef CONFIG_SPL_BUILD
200 void rtc32k_enable(void)
202 struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
205 * Unlock the RTC's registers. For more details please see the
206 * RTC_SS section of the TRM. In order to unlock we need to
207 * write these specific values (keys) in this order.
209 writel(0x83e70b13, &rtc->kick0r);
210 writel(0x95a4f1e0, &rtc->kick1r);
212 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
213 writel((1 << 3) | (1 << 6), &rtc->osc);
216 #define UART_RESET (0x1 << 1)
217 #define UART_CLK_RUNNING_MASK 0x1
218 #define UART_SMART_IDLE_EN (0x1 << 0x3)
220 void uart_soft_reset(void)
222 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
225 regval = readl(&uart_base->uartsyscfg);
226 regval |= UART_RESET;
227 writel(regval, &uart_base->uartsyscfg);
228 while ((readl(&uart_base->uartsyssts) &
229 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
232 /* Disable smart idle */
233 regval = readl(&uart_base->uartsyscfg);
234 regval |= UART_SMART_IDLE_EN;
235 writel(regval, &uart_base->uartsyscfg);