arch/arm/cpu/armv7/at91/sama5d4_devices.c

   1 /*
   2  * Copyright (C) 2014 Atmel
   3  *                    Bo Shen <voice.shen@atmel.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/at91_common.h>
  11 #include <asm/arch/at91_pmc.h>
  12 #include <asm/arch/clk.h>
  13 #include <asm/arch/sama5_matrix.h>
  14 #include <asm/arch/sama5_sfr.h>
  15 #include <asm/arch/sama5d4.h>
  16
  17 char *get_cpu_name()
  18 {
  19         unsigned int extension_id = get_extension_chip_id();
  20
  21         if (cpu_is_sama5d4())
  22                 switch (extension_id) {
  23                 case ARCH_EXID_SAMA5D41:
  24                         return "SAMA5D41";
  25                 case ARCH_EXID_SAMA5D42:
  26                         return "SAMA5D42";
  27                 case ARCH_EXID_SAMA5D43:
  28                         return "SAMA5D43";
  29                 case ARCH_EXID_SAMA5D44:
  30                         return "SAMA5D44";
  31                 default:
  32                         return "Unknown CPU type";
  33                 }
  34         else
  35                 return "Unknown CPU type";
  36 }
  37
  38 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
  39 void at91_udp_hw_init(void)
  40 {
  41         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  42
  43         /* Enable UPLL clock */
  44         writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
  45         /* Enable UDPHS clock */
  46         at91_periph_clk_enable(ATMEL_ID_UDPHS);
  47 }
  48 #endif
  49
  50 #ifdef CONFIG_SPL_BUILD
  51 void matrix_init(void)
  52 {
  53         struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0;
  54         struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
  55         int i;
  56
  57         /* Disable the write protect */
  58         writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
  59         writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
  60
  61         /* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
  62         for (i = 4; i <= 10; i++) {
  63                 writel(0x000f0f0f, &h64mx->ssr[i]);
  64                 writel(0x0000ffff, &h64mx->sassr[i]);
  65                 writel(0x0000000f, &h64mx->srtsr[i]);
  66         }
  67
  68         /* CS3 */
  69         writel(0x00c0c0c0, &h32mx->ssr[3]);
  70         writel(0xff000000, &h32mx->sassr[3]);
  71         writel(0xff000000, &h32mx->srtsr[3]);
  72
  73         /* NFC SRAM */
  74         writel(0x00010101, &h32mx->ssr[4]);
  75         writel(0x00000001, &h32mx->sassr[4]);
  76         writel(0x00000001, &h32mx->srtsr[4]);
  77
  78         /* Enable the write protect */
  79         writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
  80         writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
  81 }
  82
  83 void redirect_int_from_saic_to_aic(void)
  84 {
  85         struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
  86         u32 key32;
  87
  88         if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
  89                 key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
  90                 writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
  91         }
  92 }
  93 #endif