2 * Keystone2: DDR3 initialization
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/ddr3.h>
13 #include <asm/arch/psc_defs.h>
15 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
19 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
20 & 0x00000001) != 0x00000001)
23 __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
25 tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
26 tmp &= ~(phy_cfg->pgcr1_mask);
27 tmp |= phy_cfg->pgcr1_val;
28 __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
30 __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET);
31 __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET);
32 __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET);
33 __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET);
35 tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
36 tmp &= ~(phy_cfg->dcr_mask);
37 tmp |= phy_cfg->dcr_val;
38 __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
40 __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
41 __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
42 __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
43 __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
44 __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
45 __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
46 __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
47 __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
49 __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
50 __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
51 __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
53 __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
54 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
57 __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
58 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
62 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
64 __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
65 __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
66 __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
67 __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
68 __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
69 __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
70 __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
73 void ddr3_reset_ddrphy(void)
77 /* Assert DDR3A PHY reset */
78 tmp = readl(KS2_DDR3APLLCTL1);
79 tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
80 writel(tmp, KS2_DDR3APLLCTL1);
82 /* wait 10us to catch the reset */
85 /* Release DDR3A PHY reset */
86 tmp = readl(KS2_DDR3APLLCTL1);
87 tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
88 __raw_writel(tmp, KS2_DDR3APLLCTL1);
91 #ifdef CONFIG_SOC_K2HK
93 * ddr3_reset_workaround - reset workaround in case if leveling error
94 * detected for PG 1.0 and 1.1 k2hk SoCs
96 void ddr3_err_reset_workaround(void)
103 * Check for PGSR0 error bits of DDR3 PHY.
104 * Check for WLERR, QSGERR, WLAERR,
105 * RDERR, WDERR, REERR, WEERR error to see if they are set or not
107 tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
108 tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
110 if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) {
111 printf("DDR Leveling Error Detected!\n");
112 printf("DDR3A PGSR0 = 0x%x\n", tmp_a);
113 printf("DDR3B PGSR0 = 0x%x\n", tmp_b);
116 * Write Keys to KICK registers to enable writes to registers
117 * in boot config space
119 __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
120 __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
123 * Move DDR3A Module out of reset isolation by setting
126 tmp_a = __raw_readl(KS2_PSC_BASE +
127 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
129 tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0);
130 __raw_writel(tmp_a, KS2_PSC_BASE +
131 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
134 * Move DDR3B Module out of reset isolation by setting
137 tmp_b = __raw_readl(KS2_PSC_BASE +
138 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
139 tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0);
140 __raw_writel(tmp_b, KS2_PSC_BASE +
141 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
144 * Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes
145 * to RSTCTRL and RSTCFG
147 tmp = __raw_readl(KS2_RSTCTRL);
148 tmp &= KS2_RSTCTRL_MASK;
149 tmp |= KS2_RSTCTRL_KEY;
150 __raw_writel(tmp, KS2_RSTCTRL);
153 * Set PLL Controller to drive hard reset on SW trigger by
154 * setting RSTCFG[13] = 0
156 tmp = __raw_readl(KS2_RSTCTRL_RSCFG);
157 tmp &= ~KS2_RSTYPE_PLL_SOFT;
158 __raw_writel(tmp, KS2_RSTCTRL_RSCFG);