3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/armv7.h>
12 #include <asm/pl310.h>
13 #include <asm/errno.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/imx-common/boot_mode.h>
19 #include <asm/imx-common/dma.h>
21 #include <asm/arch/mxc_hdmi.h>
22 #include <asm/arch/crm_regs.h>
23 #include <asm/bootm.h>
41 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
42 return readl(&scu->config) & 3;
47 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
48 u32 reg = readl(&anatop->digprog_sololite);
49 u32 type = ((reg >> 16) & 0xff);
51 if (type != MXC_CPU_MX6SL) {
52 reg = readl(&anatop->digprog);
53 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
54 u32 cfg = readl(&scu->config) & 3;
55 type = ((reg >> 16) & 0xff);
56 if (type == MXC_CPU_MX6DL) {
58 type = MXC_CPU_MX6SOLO;
61 if (type == MXC_CPU_MX6Q) {
67 reg &= 0xff; /* mx6 silicon revision */
68 return (type << 12) | (reg + 0x10);
71 #ifdef CONFIG_REVISION_TAG
72 u32 __weak get_board_rev(void)
74 u32 cpurev = get_cpu_rev();
75 u32 type = ((cpurev >> 12) & 0xff);
76 if (type == MXC_CPU_MX6SOLO)
77 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
79 if (type == MXC_CPU_MX6D)
80 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
88 struct aipstz_regs *aips1, *aips2;
90 struct aipstz_regs *aips3;
93 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
94 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
96 aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
100 * Set all MPROTx to be non-bufferable, trusted for R/W,
101 * not forced to user-mode.
103 writel(0x77777777, &aips1->mprot0);
104 writel(0x77777777, &aips1->mprot1);
105 writel(0x77777777, &aips2->mprot0);
106 writel(0x77777777, &aips2->mprot1);
109 * Set all OPACRx to be non-bufferable, not require
110 * supervisor privilege level for access,allow for
111 * write access and untrusted master access.
113 writel(0x00000000, &aips1->opacr0);
114 writel(0x00000000, &aips1->opacr1);
115 writel(0x00000000, &aips1->opacr2);
116 writel(0x00000000, &aips1->opacr3);
117 writel(0x00000000, &aips1->opacr4);
118 writel(0x00000000, &aips2->opacr0);
119 writel(0x00000000, &aips2->opacr1);
120 writel(0x00000000, &aips2->opacr2);
121 writel(0x00000000, &aips2->opacr3);
122 writel(0x00000000, &aips2->opacr4);
126 * Set all MPROTx to be non-bufferable, trusted for R/W,
127 * not forced to user-mode.
129 writel(0x77777777, &aips3->mprot0);
130 writel(0x77777777, &aips3->mprot1);
133 * Set all OPACRx to be non-bufferable, not require
134 * supervisor privilege level for access,allow for
135 * write access and untrusted master access.
137 writel(0x00000000, &aips3->opacr0);
138 writel(0x00000000, &aips3->opacr1);
139 writel(0x00000000, &aips3->opacr2);
140 writel(0x00000000, &aips3->opacr3);
141 writel(0x00000000, &aips3->opacr4);
145 static void clear_ldo_ramp(void)
147 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
150 /* ROM may modify LDO ramp up time according to fuse setting, so in
151 * order to be in the safe side we neeed to reset these settings to
152 * match the reset value: 0'b00
154 reg = readl(&anatop->ana_misc2);
155 reg &= ~(0x3f << 24);
156 writel(reg, &anatop->ana_misc2);
160 * Set the PMU_REG_CORE register
162 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
163 * Possible values are from 0.725V to 1.450V in steps of
166 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
168 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
169 u32 val, step, old, reg = readl(&anatop->reg_core);
173 val = 0x00; /* Power gated off */
175 val = 0x1F; /* Power FET switched full on. No regulation */
177 val = (mv - 700) / 25;
195 old = (reg & (0x1F << shift)) >> shift;
196 step = abs(val - old);
200 reg = (reg & ~(0x1F << shift)) | (val << shift);
201 writel(reg, &anatop->reg_core);
204 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
212 static void imx_set_wdog_powerdown(bool enable)
214 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
215 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
217 /* Write to the PDE (Power Down Enable) bit */
218 writew(enable, &wdog1->wmcr);
219 writew(enable, &wdog2->wmcr);
222 static void set_ahb_rate(u32 val)
224 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
227 div = get_periph_clk() / val - 1;
228 reg = readl(&mxc_ccm->cbcdr);
230 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
231 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
234 static void clear_mmdc_ch_mask(void)
236 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
238 /* Clear MMDC channel mask */
239 writel(0, &mxc_ccm->ccdr);
242 int arch_cpu_init(void)
246 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
247 clear_mmdc_ch_mask();
250 * When low freq boot is enabled, ROM will not set AHB
251 * freq, so we need to ensure AHB freq is 132MHz in such
254 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
255 set_ahb_rate(132000000);
257 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
259 #ifdef CONFIG_APBH_DMA
267 int board_postclk_init(void)
269 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
274 #ifndef CONFIG_SYS_DCACHE_OFF
275 void enable_caches(void)
277 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
278 enum dcache_option option = DCACHE_WRITETHROUGH;
280 enum dcache_option option = DCACHE_WRITEBACK;
283 /* Avoid random hang when download by usb */
284 invalidate_dcache_all();
286 /* Enable D-cache. I-cache is already enabled in start.S */
289 /* Enable caching on OCRAM and ROM */
290 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
293 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
299 #if defined(CONFIG_FEC_MXC)
300 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
302 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
303 struct fuse_bank *bank = &ocotp->bank[4];
304 struct fuse_bank4_regs *fuse =
305 (struct fuse_bank4_regs *)bank->fuse_regs;
307 u32 value = readl(&fuse->mac_addr_high);
308 mac[0] = (value >> 8);
311 value = readl(&fuse->mac_addr_low);
312 mac[2] = value >> 24 ;
313 mac[3] = value >> 16 ;
314 mac[4] = value >> 8 ;
320 void boot_mode_apply(unsigned cfg_val)
323 struct src *psrc = (struct src *)SRC_BASE_ADDR;
324 writel(cfg_val, &psrc->gpr9);
325 reg = readl(&psrc->gpr10);
330 writel(reg, &psrc->gpr10);
333 * cfg_val will be used for
334 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
335 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
336 * to SBMR1, which will determine the boot device.
338 const struct boot_mode soc_boot_modes[] = {
339 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
340 /* reserved value should start rom usb */
341 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
342 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
343 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
344 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
345 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
346 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
347 /* 4 bit bus width */
348 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
349 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
350 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
351 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
357 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
358 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
361 u32 reg, periph1, periph2;
363 if (is_cpu_type(MXC_CPU_MX6SX))
366 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
367 * to make sure PFD is working right, otherwise, PFDs may
368 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
369 * workaround in ROM code, as bus clock need it
372 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
373 ANATOP_PFD_CLKGATE_MASK(1) |
374 ANATOP_PFD_CLKGATE_MASK(2) |
375 ANATOP_PFD_CLKGATE_MASK(3);
376 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
377 ANATOP_PFD_CLKGATE_MASK(3);
379 reg = readl(&ccm->cbcmr);
380 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
381 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
382 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
383 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
385 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
386 if ((periph2 != 0x2) && (periph1 != 0x2))
387 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
389 if ((periph2 != 0x1) && (periph1 != 0x1) &&
390 (periph2 != 0x3) && (periph1 != 0x3))
391 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
393 writel(mask480, &anatop->pfd_480_set);
394 writel(mask528, &anatop->pfd_528_set);
395 writel(mask480, &anatop->pfd_480_clr);
396 writel(mask528, &anatop->pfd_528_clr);
399 #ifdef CONFIG_IMX_HDMI
400 void imx_enable_hdmi_phy(void)
402 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
404 reg = readb(&hdmi->phy_conf0);
405 reg |= HDMI_PHY_CONF0_PDZ_MASK;
406 writeb(reg, &hdmi->phy_conf0);
408 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
409 writeb(reg, &hdmi->phy_conf0);
411 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
412 writeb(reg, &hdmi->phy_conf0);
413 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
416 void imx_setup_hdmi(void)
418 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
419 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
422 /* Turn on HDMI PHY clock */
423 reg = readl(&mxc_ccm->CCGR2);
424 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
425 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
426 writel(reg, &mxc_ccm->CCGR2);
427 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
428 reg = readl(&mxc_ccm->chsccdr);
429 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
430 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
431 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
432 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
433 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
434 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
435 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
436 writel(reg, &mxc_ccm->chsccdr);
440 #ifndef CONFIG_SYS_L2CACHE_OFF
441 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
442 void v7_outer_cache_enable(void)
444 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
447 #if defined CONFIG_MX6SL
448 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
449 val = readl(&iomux->gpr[11]);
450 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
451 /* L2 cache configured as OCRAM, reset it */
452 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
453 writel(val, &iomux->gpr[11]);
457 /* Must disable the L2 before changing the latency parameters */
458 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
460 writel(0x132, &pl310->pl310_tag_latency_ctrl);
461 writel(0x132, &pl310->pl310_data_latency_ctrl);
463 val = readl(&pl310->pl310_prefetch_ctrl);
465 /* Turn on the L2 I/D prefetch */
469 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
470 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
471 * But according to ARM PL310 errata: 752271
472 * ID: 752271: Double linefill feature can cause data corruption
473 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
474 * Workaround: The only workaround to this erratum is to disable the
475 * double linefill feature. This is the default behavior.
481 writel(val, &pl310->pl310_prefetch_ctrl);
483 val = readl(&pl310->pl310_power_ctrl);
484 val |= L2X0_DYNAMIC_CLK_GATING_EN;
485 val |= L2X0_STNDBY_MODE_EN;
486 writel(val, &pl310->pl310_power_ctrl);
488 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
491 void v7_outer_cache_disable(void)
493 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
495 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
497 #endif /* !CONFIG_SYS_L2CACHE_OFF */