arch/arm/cpu/armv7/omap-common/emif-common.c

   1 /*
   2  * EMIF programming
   3  *
   4  * (C) Copyright 2010
   5  * Texas Instruments, <www.ti.com>
   6  *
   7  * Aneesh V <aneesh@ti.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <asm/emif.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/omap_common.h>
  17 #include <asm/utils.h>
  18 #include <linux/compiler.h>
  19
  20 static int emif1_enabled = -1, emif2_enabled = -1;
  21
  22 void set_lpmode_selfrefresh(u32 base)
  23 {
  24         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  25         u32 reg;
  26
  27         reg = readl(&emif->emif_pwr_mgmt_ctrl);
  28         reg &= ~EMIF_REG_LP_MODE_MASK;
  29         reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
  30         reg &= ~EMIF_REG_SR_TIM_MASK;
  31         writel(reg, &emif->emif_pwr_mgmt_ctrl);
  32
  33         /* dummy read for the new SR_TIM to be loaded */
  34         readl(&emif->emif_pwr_mgmt_ctrl);
  35 }
  36
  37 void force_emif_self_refresh()
  38 {
  39         set_lpmode_selfrefresh(EMIF1_BASE);
  40         set_lpmode_selfrefresh(EMIF2_BASE);
  41 }
  42
  43 inline u32 emif_num(u32 base)
  44 {
  45         if (base == EMIF1_BASE)
  46                 return 1;
  47         else if (base == EMIF2_BASE)
  48                 return 2;
  49         else
  50                 return 0;
  51 }
  52
  53 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
  54 {
  55         u32 mr;
  56         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  57
  58         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  59         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  60         if (omap_revision() == OMAP4430_ES2_0)
  61                 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
  62         else
  63                 mr = readl(&emif->emif_lpddr2_mode_reg_data);
  64         debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
  65               cs, mr_addr, mr);
  66         if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
  67             ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  68             ((mr & 0xff000000) >> 24) == (mr & 0xff))
  69                 return mr & 0xff;
  70         else
  71                 return mr;
  72 }
  73
  74 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
  75 {
  76         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  77
  78         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  79         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  80         writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
  81 }
  82
  83 void emif_reset_phy(u32 base)
  84 {
  85         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  86         u32 iodft;
  87
  88         iodft = readl(&emif->emif_iodft_tlgc);
  89         iodft |= EMIF_REG_RESET_PHY_MASK;
  90         writel(iodft, &emif->emif_iodft_tlgc);
  91 }
  92
  93 static void do_lpddr2_init(u32 base, u32 cs)
  94 {
  95         u32 mr_addr;
  96         const struct lpddr2_mr_regs *mr_regs;
  97
  98         get_lpddr2_mr_regs(&mr_regs);
  99         /* Wait till device auto initialization is complete */
 100         while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
 101                 ;
 102         set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
 103         /*
 104          * tZQINIT = 1 us
 105          * Enough loops assuming a maximum of 2GHz
 106          */
 107
 108         sdelay(2000);
 109
 110         set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
 111         set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
 112
 113         /*
 114          * Enable refresh along with writing MR2
 115          * Encoding of RL in MR2 is (RL - 2)
 116          */
 117         mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
 118         set_mr(base, cs, mr_addr, mr_regs->mr2);
 119
 120         if (mr_regs->mr3 > 0)
 121                 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
 122 }
 123
 124 static void lpddr2_init(u32 base, const struct emif_regs *regs)
 125 {
 126         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 127
 128         /* Not NVM */
 129         clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
 130
 131         /*
 132          * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
 133          * when EMIF_SDRAM_CONFIG register is written
 134          */
 135         setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 136
 137         /*
 138          * Set the SDRAM_CONFIG and PHY_CTRL for the
 139          * un-locked frequency & default RL
 140          */
 141         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 142         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 143
 144         do_ext_phy_settings(base, regs);
 145
 146         do_lpddr2_init(base, CS0);
 147         if (regs->sdram_config & EMIF_REG_EBANK_MASK)
 148                 do_lpddr2_init(base, CS1);
 149
 150         writel(regs->sdram_config, &emif->emif_sdram_config);
 151         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 152
 153         /* Enable refresh now */
 154         clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 155
 156         }
 157
 158 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 159 {
 160 }
 161
 162 void emif_update_timings(u32 base, const struct emif_regs *regs)
 163 {
 164         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 165
 166         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
 167         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
 168         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
 169         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
 170         if (omap_revision() == OMAP4430_ES1_0) {
 171                 /* ES1 bug EMIF should be in force idle during freq_update */
 172                 writel(0, &emif->emif_pwr_mgmt_ctrl);
 173         } else {
 174                 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
 175                 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
 176         }
 177         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
 178         writel(regs->zq_config, &emif->emif_zq_config);
 179         writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 180         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 181
 182         if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
 183                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
 184                         &emif->emif_l3_config);
 185         } else if (omap_revision() >= OMAP4460_ES1_0) {
 186                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
 187                         &emif->emif_l3_config);
 188         } else {
 189                 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
 190                         &emif->emif_l3_config);
 191         }
 192 }
 193
 194 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 195 {
 196         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 197
 198         /* keep sdram in self-refresh */
 199         writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
 200                 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 201         __udelay(130);
 202
 203         /*
 204          * Set invert_clkout (if activated)--DDR_PHYCTRL_1
 205          * Invert clock adds an additional half cycle delay on the
 206          * command interface.  The additional half cycle, is usually
 207          * meant to enable leveling in the situation that DQS is later
 208          * than CK on the board.It also helps provide some additional
 209          * margin for leveling.
 210          */
 211         writel(regs->emif_ddr_phy_ctlr_1,
 212                &emif->emif_ddr_phy_ctrl_1);
 213
 214         writel(regs->emif_ddr_phy_ctlr_1,
 215                &emif->emif_ddr_phy_ctrl_1_shdw);
 216         __udelay(130);
 217
 218         writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
 219                & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 220
 221         /* Launch Full leveling */
 222         writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 223
 224         /* Wait till full leveling is complete */
 225         readl(&emif->emif_rd_wr_lvl_ctl);
 226               __udelay(130);
 227
 228         /* Read data eye leveling no of samples */
 229         config_data_eye_leveling_samples(base);
 230
 231         /*
 232          * Launch 8 incremental WR_LVL- to compensate for
 233          * PHY limitation.
 234          */
 235         writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
 236                &emif->emif_rd_wr_lvl_ctl);
 237
 238         __udelay(130);
 239
 240         /* Launch Incremental leveling */
 241         writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
 242                __udelay(130);
 243 }
 244
 245 static void ddr3_leveling(u32 base, const struct emif_regs *regs)
 246 {
 247         if (is_omap54xx())
 248                 omap5_ddr3_leveling(base, regs);
 249 }
 250
 251 static void ddr3_init(u32 base, const struct emif_regs *regs)
 252 {
 253         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 254
 255         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
 256         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 257         /*
 258          * Set SDRAM_CONFIG and PHY control registers to locked frequency
 259          * and RL =7. As the default values of the Mode Registers are not
 260          * defined, contents of mode Registers must be fully initialized.
 261          * H/W takes care of this initialization
 262          */
 263         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 264
 265         /* Update timing registers */
 266         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
 267         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
 268         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
 269
 270         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 271
 272         /*
 273          * The same sequence should work on OMAP5432 as well. But strange that
 274          * it is not working
 275          */
 276         if (is_dra7xx()) {
 277                 do_ext_phy_settings(base, regs);
 278                 writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
 279                 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 280                 writel(regs->sdram_config_init, &emif->emif_sdram_config);
 281         } else {
 282                 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 283                 writel(regs->sdram_config_init, &emif->emif_sdram_config);
 284                 do_ext_phy_settings(base, regs);
 285         }
 286
 287         /* enable leveling */
 288         writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 289
 290         ddr3_leveling(base, regs);
 291 }
 292
 293 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 294 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
 295
 296 /*
 297  * Organization and refresh requirements for LPDDR2 devices of different
 298  * types and densities. Derived from JESD209-2 section 2.4
 299  */
 300 const struct lpddr2_addressing addressing_table[] = {
 301         /* Banks tREFIx10     rowx32,rowx16      colx32,colx16  density */
 302         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
 303         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
 304         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
 305         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
 306         {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
 307         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
 308         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
 309         {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
 310         {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
 311         {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
 312 };
 313
 314 static const u32 lpddr2_density_2_size_in_mbytes[] = {
 315         8,                      /* 64Mb */
 316         16,                     /* 128Mb */
 317         32,                     /* 256Mb */
 318         64,                     /* 512Mb */
 319         128,                    /* 1Gb   */
 320         256,                    /* 2Gb   */
 321         512,                    /* 4Gb   */
 322         1024,                   /* 8Gb   */
 323         2048,                   /* 16Gb  */
 324         4096                    /* 32Gb  */
 325 };
 326
 327 /*
 328  * Calculate the period of DDR clock from frequency value and set the
 329  * denominator and numerator in global variables for easy access later
 330  */
 331 static void set_ddr_clk_period(u32 freq)
 332 {
 333         /*
 334          * period = 1/freq
 335          * period_in_ns = 10^9/freq
 336          */
 337         *T_num = 1000000000;
 338         *T_den = freq;
 339         cancel_out(T_num, T_den, 200);
 340
 341 }
 342
 343 /*
 344  * Convert time in nano seconds to number of cycles of DDR clock
 345  */
 346 static inline u32 ns_2_cycles(u32 ns)
 347 {
 348         return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
 349 }
 350
 351 /*
 352  * ns_2_cycles with the difference that the time passed is 2 times the actual
 353  * value(to avoid fractions). The cycles returned is for the original value of
 354  * the timing parameter
 355  */
 356 static inline u32 ns_x2_2_cycles(u32 ns)
 357 {
 358         return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
 359 }
 360
 361 /*
 362  * Find addressing table index based on the device's type(S2 or S4) and
 363  * density
 364  */
 365 s8 addressing_table_index(u8 type, u8 density, u8 width)
 366 {
 367         u8 index;
 368         if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
 369                 return -1;
 370
 371         /*
 372          * Look at the way ADDR_TABLE_INDEX* values have been defined
 373          * in emif.h compared to LPDDR2_DENSITY_* values
 374          * The table is layed out in the increasing order of density
 375          * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
 376          * at the end
 377          */
 378         if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
 379                 index = ADDR_TABLE_INDEX1GS2;
 380         else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
 381                 index = ADDR_TABLE_INDEX2GS2;
 382         else
 383                 index = density;
 384
 385         debug("emif: addressing table index %d\n", index);
 386
 387         return index;
 388 }
 389
 390 /*
 391  * Find the the right timing table from the array of timing
 392  * tables of the device using DDR clock frequency
 393  */
 394 static const struct lpddr2_ac_timings *get_timings_table(const struct
 395                         lpddr2_ac_timings const *const *device_timings,
 396                         u32 freq)
 397 {
 398         u32 i, temp, freq_nearest;
 399         const struct lpddr2_ac_timings *timings = 0;
 400
 401         emif_assert(freq <= MAX_LPDDR2_FREQ);
 402         emif_assert(device_timings);
 403
 404         /*
 405          * Start with the maximum allowed frequency - that is always safe
 406          */
 407         freq_nearest = MAX_LPDDR2_FREQ;
 408         /*
 409          * Find the timings table that has the max frequency value:
 410          *   i.  Above or equal to the DDR frequency - safe
 411          *   ii. The lowest that satisfies condition (i) - optimal
 412          */
 413         for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
 414                 temp = device_timings[i]->max_freq;
 415                 if ((temp >= freq) && (temp <= freq_nearest)) {
 416                         freq_nearest = temp;
 417                         timings = device_timings[i];
 418                 }
 419         }
 420         debug("emif: timings table: %d\n", freq_nearest);
 421         return timings;
 422 }
 423
 424 /*
 425  * Finds the value of emif_sdram_config_reg
 426  * All parameters are programmed based on the device on CS0.
 427  * If there is a device on CS1, it will be same as that on CS0 or
 428  * it will be NVM. We don't support NVM yet.
 429  * If cs1_device pointer is NULL it is assumed that there is no device
 430  * on CS1
 431  */
 432 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
 433                                 const struct lpddr2_device_details *cs1_device,
 434                                 const struct lpddr2_addressing *addressing,
 435                                 u8 RL)
 436 {
 437         u32 config_reg = 0;
 438
 439         config_reg |=  (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
 440         config_reg |=  EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
 441                         EMIF_REG_IBANK_POS_SHIFT;
 442
 443         config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
 444
 445         config_reg |= RL << EMIF_REG_CL_SHIFT;
 446
 447         config_reg |= addressing->row_sz[cs0_device->io_width] <<
 448                         EMIF_REG_ROWSIZE_SHIFT;
 449
 450         config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
 451
 452         config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
 453                         EMIF_REG_EBANK_SHIFT;
 454
 455         config_reg |= addressing->col_sz[cs0_device->io_width] <<
 456                         EMIF_REG_PAGESIZE_SHIFT;
 457
 458         return config_reg;
 459 }
 460
 461 static u32 get_sdram_ref_ctrl(u32 freq,
 462                               const struct lpddr2_addressing *addressing)
 463 {
 464         u32 ref_ctrl = 0, val = 0, freq_khz;
 465         freq_khz = freq / 1000;
 466         /*
 467          * refresh rate to be set is 'tREFI * freq in MHz
 468          * division by 10000 to account for khz and x10 in t_REFI_us_x10
 469          */
 470         val = addressing->t_REFI_us_x10 * freq_khz / 10000;
 471         ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
 472
 473         return ref_ctrl;
 474 }
 475
 476 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
 477                                const struct lpddr2_min_tck *min_tck,
 478                                const struct lpddr2_addressing *addressing)
 479 {
 480         u32 tim1 = 0, val = 0;
 481         val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
 482         tim1 |= val << EMIF_REG_T_WTR_SHIFT;
 483
 484         if (addressing->num_banks == BANKS8)
 485                 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
 486                                                         (4 * (*T_num)) - 1;
 487         else
 488                 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
 489
 490         tim1 |= val << EMIF_REG_T_RRD_SHIFT;
 491
 492         val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
 493         tim1 |= val << EMIF_REG_T_RC_SHIFT;
 494
 495         val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
 496         tim1 |= val << EMIF_REG_T_RAS_SHIFT;
 497
 498         val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
 499         tim1 |= val << EMIF_REG_T_WR_SHIFT;
 500
 501         val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
 502         tim1 |= val << EMIF_REG_T_RCD_SHIFT;
 503
 504         val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
 505         tim1 |= val << EMIF_REG_T_RP_SHIFT;
 506
 507         return tim1;
 508 }
 509
 510 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
 511                                const struct lpddr2_min_tck *min_tck)
 512 {
 513         u32 tim2 = 0, val = 0;
 514         val = max(min_tck->tCKE, timings->tCKE) - 1;
 515         tim2 |= val << EMIF_REG_T_CKE_SHIFT;
 516
 517         val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
 518         tim2 |= val << EMIF_REG_T_RTP_SHIFT;
 519
 520         /*
 521          * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
 522          * same value
 523          */
 524         val = ns_2_cycles(timings->tXSR) - 1;
 525         tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
 526         tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
 527
 528         val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
 529         tim2 |= val << EMIF_REG_T_XP_SHIFT;
 530
 531         return tim2;
 532 }
 533
 534 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
 535                                const struct lpddr2_min_tck *min_tck,
 536                                const struct lpddr2_addressing *addressing)
 537 {
 538         u32 tim3 = 0, val = 0;
 539         val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
 540         tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
 541
 542         val = ns_2_cycles(timings->tRFCab) - 1;
 543         tim3 |= val << EMIF_REG_T_RFC_SHIFT;
 544
 545         val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
 546         tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
 547
 548         val = ns_2_cycles(timings->tZQCS) - 1;
 549         tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
 550
 551         val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
 552         tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
 553
 554         return tim3;
 555 }
 556
 557 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
 558                              const struct lpddr2_addressing *addressing,
 559                              u8 volt_ramp)
 560 {
 561         u32 zq = 0, val = 0;
 562         if (volt_ramp)
 563                 val =
 564                     EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
 565                     addressing->t_REFI_us_x10;
 566         else
 567                 val =
 568                     EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
 569                     addressing->t_REFI_us_x10;
 570         zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
 571
 572         zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
 573
 574         zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
 575
 576         zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
 577
 578         /*
 579          * Assuming that two chipselects have a single calibration resistor
 580          * If there are indeed two calibration resistors, then this flag should
 581          * be enabled to take advantage of dual calibration feature.
 582          * This data should ideally come from board files. But considering
 583          * that none of the boards today have calibration resistors per CS,
 584          * it would be an unnecessary overhead.
 585          */
 586         zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
 587
 588         zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
 589
 590         zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
 591
 592         return zq;
 593 }
 594
 595 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
 596                                  const struct lpddr2_addressing *addressing,
 597                                  u8 is_derated)
 598 {
 599         u32 alert = 0, interval;
 600         interval =
 601             TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
 602         if (is_derated)
 603                 interval *= 4;
 604         alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
 605
 606         alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
 607
 608         alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
 609
 610         alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
 611
 612         alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
 613
 614         alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
 615
 616         return alert;
 617 }
 618
 619 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
 620 {
 621         u32 idle = 0, val = 0;
 622         if (volt_ramp)
 623                 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
 624         else
 625                 /*Maximum value in normal conditions - suggested by hw team */
 626                 val = 0x1FF;
 627         idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
 628
 629         idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
 630
 631         return idle;
 632 }
 633
 634 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
 635 {
 636         u32 phy = 0, val = 0;
 637
 638         phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
 639
 640         if (freq <= 100000000)
 641                 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
 642         else if (freq <= 200000000)
 643                 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
 644         else
 645                 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
 646         phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
 647
 648         /* Other fields are constant magic values. Hardcode them together */
 649         phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
 650                 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
 651
 652         return phy;
 653 }
 654
 655 static u32 get_emif_mem_size(u32 base)
 656 {
 657         u32 size_mbytes = 0, temp;
 658         struct emif_device_details dev_details;
 659         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
 660         u32 emif_nr = emif_num(base);
 661
 662         emif_reset_phy(base);
 663         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
 664                                                 &cs0_dev_details);
 665         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
 666                                                 &cs1_dev_details);
 667         emif_reset_phy(base);
 668
 669         if (dev_details.cs0_device_details) {
 670                 temp = dev_details.cs0_device_details->density;
 671                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 672         }
 673
 674         if (dev_details.cs1_device_details) {
 675                 temp = dev_details.cs1_device_details->density;
 676                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 677         }
 678         /* convert to bytes */
 679         return size_mbytes << 20;
 680 }
 681
 682 /* Gets the encoding corresponding to a given DMM section size */
 683 u32 get_dmm_section_size_map(u32 section_size)
 684 {
 685         /*
 686          * Section size mapping:
 687          * 0x0: 16-MiB section
 688          * 0x1: 32-MiB section
 689          * 0x2: 64-MiB section
 690          * 0x3: 128-MiB section
 691          * 0x4: 256-MiB section
 692          * 0x5: 512-MiB section
 693          * 0x6: 1-GiB section
 694          * 0x7: 2-GiB section
 695          */
 696         section_size >>= 24; /* divide by 16 MB */
 697         return log_2_n_round_down(section_size);
 698 }
 699
 700 static void emif_calculate_regs(
 701                 const struct emif_device_details *emif_dev_details,
 702                 u32 freq, struct emif_regs *regs)
 703 {
 704         u32 temp, sys_freq;
 705         const struct lpddr2_addressing *addressing;
 706         const struct lpddr2_ac_timings *timings;
 707         const struct lpddr2_min_tck *min_tck;
 708         const struct lpddr2_device_details *cs0_dev_details =
 709                                         emif_dev_details->cs0_device_details;
 710         const struct lpddr2_device_details *cs1_dev_details =
 711                                         emif_dev_details->cs1_device_details;
 712         const struct lpddr2_device_timings *cs0_dev_timings =
 713                                         emif_dev_details->cs0_device_timings;
 714
 715         emif_assert(emif_dev_details);
 716         emif_assert(regs);
 717         /*
 718          * You can not have a device on CS1 without one on CS0
 719          * So configuring EMIF without a device on CS0 doesn't
 720          * make sense
 721          */
 722         emif_assert(cs0_dev_details);
 723         emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
 724         /*
 725          * If there is a device on CS1 it should be same type as CS0
 726          * (or NVM. But NVM is not supported in this driver yet)
 727          */
 728         emif_assert((cs1_dev_details == NULL) ||
 729                     (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
 730                     (cs0_dev_details->type == cs1_dev_details->type));
 731         emif_assert(freq <= MAX_LPDDR2_FREQ);
 732
 733         set_ddr_clk_period(freq);
 734
 735         /*
 736          * The device on CS0 is used for all timing calculations
 737          * There is only one set of registers for timings per EMIF. So, if the
 738          * second CS(CS1) has a device, it should have the same timings as the
 739          * device on CS0
 740          */
 741         timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
 742         emif_assert(timings);
 743         min_tck = cs0_dev_timings->min_tck;
 744
 745         temp = addressing_table_index(cs0_dev_details->type,
 746                                       cs0_dev_details->density,
 747                                       cs0_dev_details->io_width);
 748
 749         emif_assert((temp >= 0));
 750         addressing = &(addressing_table[temp]);
 751         emif_assert(addressing);
 752
 753         sys_freq = get_sys_clk_freq();
 754
 755         regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
 756                                                         cs1_dev_details,
 757                                                         addressing, RL_BOOT);
 758
 759         regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
 760                                                 cs1_dev_details,
 761                                                 addressing, RL_FINAL);
 762
 763         regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
 764
 765         regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
 766
 767         regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
 768
 769         regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
 770
 771         regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
 772
 773         regs->temp_alert_config =
 774             get_temp_alert_config(cs1_dev_details, addressing, 0);
 775
 776         regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
 777                                             LPDDR2_VOLTAGE_STABLE);
 778
 779         regs->emif_ddr_phy_ctlr_1_init =
 780                         get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
 781
 782         regs->emif_ddr_phy_ctlr_1 =
 783                         get_ddr_phy_ctrl_1(freq, RL_FINAL);
 784
 785         regs->freq = freq;
 786
 787         print_timing_reg(regs->sdram_config_init);
 788         print_timing_reg(regs->sdram_config);
 789         print_timing_reg(regs->ref_ctrl);
 790         print_timing_reg(regs->sdram_tim1);
 791         print_timing_reg(regs->sdram_tim2);
 792         print_timing_reg(regs->sdram_tim3);
 793         print_timing_reg(regs->read_idle_ctrl);
 794         print_timing_reg(regs->temp_alert_config);
 795         print_timing_reg(regs->zq_config);
 796         print_timing_reg(regs->emif_ddr_phy_ctlr_1);
 797         print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
 798 }
 799 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 800
 801 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 802 const char *get_lpddr2_type(u8 type_id)
 803 {
 804         switch (type_id) {
 805         case LPDDR2_TYPE_S4:
 806                 return "LPDDR2-S4";
 807         case LPDDR2_TYPE_S2:
 808                 return "LPDDR2-S2";
 809         default:
 810                 return NULL;
 811         }
 812 }
 813
 814 const char *get_lpddr2_io_width(u8 width_id)
 815 {
 816         switch (width_id) {
 817         case LPDDR2_IO_WIDTH_8:
 818                 return "x8";
 819         case LPDDR2_IO_WIDTH_16:
 820                 return "x16";
 821         case LPDDR2_IO_WIDTH_32:
 822                 return "x32";
 823         default:
 824                 return NULL;
 825         }
 826 }
 827
 828 const char *get_lpddr2_manufacturer(u32 manufacturer)
 829 {
 830         switch (manufacturer) {
 831         case LPDDR2_MANUFACTURER_SAMSUNG:
 832                 return "Samsung";
 833         case LPDDR2_MANUFACTURER_QIMONDA:
 834                 return "Qimonda";
 835         case LPDDR2_MANUFACTURER_ELPIDA:
 836                 return "Elpida";
 837         case LPDDR2_MANUFACTURER_ETRON:
 838                 return "Etron";
 839         case LPDDR2_MANUFACTURER_NANYA:
 840                 return "Nanya";
 841         case LPDDR2_MANUFACTURER_HYNIX:
 842                 return "Hynix";
 843         case LPDDR2_MANUFACTURER_MOSEL:
 844                 return "Mosel";
 845         case LPDDR2_MANUFACTURER_WINBOND:
 846                 return "Winbond";
 847         case LPDDR2_MANUFACTURER_ESMT:
 848                 return "ESMT";
 849         case LPDDR2_MANUFACTURER_SPANSION:
 850                 return "Spansion";
 851         case LPDDR2_MANUFACTURER_SST:
 852                 return "SST";
 853         case LPDDR2_MANUFACTURER_ZMOS:
 854                 return "ZMOS";
 855         case LPDDR2_MANUFACTURER_INTEL:
 856                 return "Intel";
 857         case LPDDR2_MANUFACTURER_NUMONYX:
 858                 return "Numonyx";
 859         case LPDDR2_MANUFACTURER_MICRON:
 860                 return "Micron";
 861         default:
 862                 return NULL;
 863         }
 864 }
 865
 866 static void display_sdram_details(u32 emif_nr, u32 cs,
 867                                   struct lpddr2_device_details *device)
 868 {
 869         const char *mfg_str;
 870         const char *type_str;
 871         char density_str[10];
 872         u32 density;
 873
 874         debug("EMIF%d CS%d\t", emif_nr, cs);
 875
 876         if (!device) {
 877                 debug("None\n");
 878                 return;
 879         }
 880
 881         mfg_str = get_lpddr2_manufacturer(device->manufacturer);
 882         type_str = get_lpddr2_type(device->type);
 883
 884         density = lpddr2_density_2_size_in_mbytes[device->density];
 885         if ((density / 1024 * 1024) == density) {
 886                 density /= 1024;
 887                 sprintf(density_str, "%d GB", density);
 888         } else
 889                 sprintf(density_str, "%d MB", density);
 890         if (mfg_str && type_str)
 891                 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
 892 }
 893
 894 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
 895                                   struct lpddr2_device_details *lpddr2_device)
 896 {
 897         u32 mr = 0, temp;
 898
 899         mr = get_mr(base, cs, LPDDR2_MR0);
 900         if (mr > 0xFF) {
 901                 /* Mode register value bigger than 8 bit */
 902                 return 0;
 903         }
 904
 905         temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
 906         if (temp) {
 907                 /* Not SDRAM */
 908                 return 0;
 909         }
 910         temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
 911
 912         if (temp) {
 913                 /* DNV supported - But DNV is only supported for NVM */
 914                 return 0;
 915         }
 916
 917         mr = get_mr(base, cs, LPDDR2_MR4);
 918         if (mr > 0xFF) {
 919                 /* Mode register value bigger than 8 bit */
 920                 return 0;
 921         }
 922
 923         mr = get_mr(base, cs, LPDDR2_MR5);
 924         if (mr > 0xFF) {
 925                 /* Mode register value bigger than 8 bit */
 926                 return 0;
 927         }
 928
 929         if (!get_lpddr2_manufacturer(mr)) {
 930                 /* Manufacturer not identified */
 931                 return 0;
 932         }
 933         lpddr2_device->manufacturer = mr;
 934
 935         mr = get_mr(base, cs, LPDDR2_MR6);
 936         if (mr >= 0xFF) {
 937                 /* Mode register value bigger than 8 bit */
 938                 return 0;
 939         }
 940
 941         mr = get_mr(base, cs, LPDDR2_MR7);
 942         if (mr >= 0xFF) {
 943                 /* Mode register value bigger than 8 bit */
 944                 return 0;
 945         }
 946
 947         mr = get_mr(base, cs, LPDDR2_MR8);
 948         if (mr >= 0xFF) {
 949                 /* Mode register value bigger than 8 bit */
 950                 return 0;
 951         }
 952
 953         temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
 954         if (!get_lpddr2_type(temp)) {
 955                 /* Not SDRAM */
 956                 return 0;
 957         }
 958         lpddr2_device->type = temp;
 959
 960         temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
 961         if (temp > LPDDR2_DENSITY_32Gb) {
 962                 /* Density not supported */
 963                 return 0;
 964         }
 965         lpddr2_device->density = temp;
 966
 967         temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
 968         if (!get_lpddr2_io_width(temp)) {
 969                 /* IO width unsupported value */
 970                 return 0;
 971         }
 972         lpddr2_device->io_width = temp;
 973
 974         /*
 975          * If all the above tests pass we should
 976          * have a device on this chip-select
 977          */
 978         return 1;
 979 }
 980
 981 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
 982                         struct lpddr2_device_details *lpddr2_dev_details)
 983 {
 984         u32 phy;
 985         u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
 986
 987         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 988
 989         if (!lpddr2_dev_details)
 990                 return NULL;
 991
 992         /* Do the minimum init for mode register accesses */
 993         if (!(running_from_sdram() || warm_reset())) {
 994                 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
 995                 writel(phy, &emif->emif_ddr_phy_ctrl_1);
 996         }
 997
 998         if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
 999                 return NULL;
1000
1001         display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1002
1003         return lpddr2_dev_details;
1004 }
1005 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1006
1007 static void do_sdram_init(u32 base)
1008 {
1009         const struct emif_regs *regs;
1010         u32 in_sdram, emif_nr;
1011
1012         debug(">>do_sdram_init() %x\n", base);
1013
1014         in_sdram = running_from_sdram();
1015         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1016
1017 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1018         emif_get_reg_dump(emif_nr, &regs);
1019         if (!regs) {
1020                 debug("EMIF: reg dump not provided\n");
1021                 return;
1022         }
1023 #else
1024         /*
1025          * The user has not provided the register values. We need to
1026          * calculate it based on the timings and the DDR frequency
1027          */
1028         struct emif_device_details dev_details;
1029         struct emif_regs calculated_regs;
1030
1031         /*
1032          * Get device details:
1033          * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1034          * - Obtained from user otherwise
1035          */
1036         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1037         emif_reset_phy(base);
1038         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1039                                                 &cs0_dev_details);
1040         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1041                                                 &cs1_dev_details);
1042         emif_reset_phy(base);
1043
1044         /* Return if no devices on this EMIF */
1045         if (!dev_details.cs0_device_details &&
1046             !dev_details.cs1_device_details) {
1047                 return;
1048         }
1049
1050         /*
1051          * Get device timings:
1052          * - Default timings specified by JESD209-2 if
1053          *   CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1054          * - Obtained from user otherwise
1055          */
1056         emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1057                                 &dev_details.cs1_device_timings);
1058
1059         /* Calculate the register values */
1060         emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1061         regs = &calculated_regs;
1062 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1063
1064         /*
1065          * Initializing the LPDDR2 device can not happen from SDRAM.
1066          * Changing the timing registers in EMIF can happen(going from one
1067          * OPP to another)
1068          */
1069         if (!(in_sdram || warm_reset())) {
1070                 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
1071                         lpddr2_init(base, regs);
1072                 else
1073                         ddr3_init(base, regs);
1074         }
1075         if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
1076                 set_lpmode_selfrefresh(base);
1077                 emif_reset_phy(base);
1078                 ddr3_leveling(base, regs);
1079         }
1080
1081         /* Write to the shadow registers */
1082         emif_update_timings(base, regs);
1083
1084         debug("<<do_sdram_init() %x\n", base);
1085 }
1086
1087 void emif_post_init_config(u32 base)
1088 {
1089         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1090         u32 omap_rev = omap_revision();
1091
1092         /* reset phy on ES2.0 */
1093         if (omap_rev == OMAP4430_ES2_0)
1094                 emif_reset_phy(base);
1095
1096         /* Put EMIF back in smart idle on ES1.0 */
1097         if (omap_rev == OMAP4430_ES1_0)
1098                 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1099 }
1100
1101 void dmm_init(u32 base)
1102 {
1103         const struct dmm_lisa_map_regs *lisa_map_regs;
1104         u32 i, section, valid;
1105
1106 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1107         emif_get_dmm_regs(&lisa_map_regs);
1108 #else
1109         u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1110         u32 section_cnt, sys_addr;
1111         struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1112
1113         mapped_size = 0;
1114         section_cnt = 3;
1115         sys_addr = CONFIG_SYS_SDRAM_BASE;
1116         emif1_size = get_emif_mem_size(EMIF1_BASE);
1117         emif2_size = get_emif_mem_size(EMIF2_BASE);
1118         debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1119
1120         if (!emif1_size && !emif2_size)
1121                 return;
1122
1123         /* symmetric interleaved section */
1124         if (emif1_size && emif2_size) {
1125                 mapped_size = min(emif1_size, emif2_size);
1126                 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1127                 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1128                 /* only MSB */
1129                 section_map |= (sys_addr >> 24) <<
1130                                 EMIF_SYS_ADDR_SHIFT;
1131                 section_map |= get_dmm_section_size_map(mapped_size * 2)
1132                                 << EMIF_SYS_SIZE_SHIFT;
1133                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1134                 emif1_size -= mapped_size;
1135                 emif2_size -= mapped_size;
1136                 sys_addr += (mapped_size * 2);
1137                 section_cnt--;
1138         }
1139
1140         /*
1141          * Single EMIF section(we can have a maximum of 1 single EMIF
1142          * section- either EMIF1 or EMIF2 or none, but not both)
1143          */
1144         if (emif1_size) {
1145                 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1146                 section_map |= get_dmm_section_size_map(emif1_size)
1147                                 << EMIF_SYS_SIZE_SHIFT;
1148                 /* only MSB */
1149                 section_map |= (mapped_size >> 24) <<
1150                                 EMIF_SDRC_ADDR_SHIFT;
1151                 /* only MSB */
1152                 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1153                 section_cnt--;
1154         }
1155         if (emif2_size) {
1156                 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1157                 section_map |= get_dmm_section_size_map(emif2_size) <<
1158                                 EMIF_SYS_SIZE_SHIFT;
1159                 /* only MSB */
1160                 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1161                 /* only MSB */
1162                 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1163                 section_cnt--;
1164         }
1165
1166         if (section_cnt == 2) {
1167                 /* Only 1 section - either symmetric or single EMIF */
1168                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1169                 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1170                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1171         } else {
1172                 /* 2 sections - 1 symmetric, 1 single EMIF */
1173                 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1174                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1175         }
1176
1177         /* TRAP for invalid TILER mappings in section 0 */
1178         lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1179
1180         if (omap_revision() >= OMAP4460_ES1_0)
1181                 lis_map_regs_calculated.is_ma_present = 1;
1182
1183         lisa_map_regs = &lis_map_regs_calculated;
1184 #endif
1185         struct dmm_lisa_map_regs *hw_lisa_map_regs =
1186             (struct dmm_lisa_map_regs *)base;
1187
1188         writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1189         writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1190         writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1191         writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1192
1193         writel(lisa_map_regs->dmm_lisa_map_3,
1194                 &hw_lisa_map_regs->dmm_lisa_map_3);
1195         writel(lisa_map_regs->dmm_lisa_map_2,
1196                 &hw_lisa_map_regs->dmm_lisa_map_2);
1197         writel(lisa_map_regs->dmm_lisa_map_1,
1198                 &hw_lisa_map_regs->dmm_lisa_map_1);
1199         writel(lisa_map_regs->dmm_lisa_map_0,
1200                 &hw_lisa_map_regs->dmm_lisa_map_0);
1201
1202         if (lisa_map_regs->is_ma_present) {
1203                 hw_lisa_map_regs =
1204                     (struct dmm_lisa_map_regs *)MA_BASE;
1205
1206                 writel(lisa_map_regs->dmm_lisa_map_3,
1207                         &hw_lisa_map_regs->dmm_lisa_map_3);
1208                 writel(lisa_map_regs->dmm_lisa_map_2,
1209                         &hw_lisa_map_regs->dmm_lisa_map_2);
1210                 writel(lisa_map_regs->dmm_lisa_map_1,
1211                         &hw_lisa_map_regs->dmm_lisa_map_1);
1212                 writel(lisa_map_regs->dmm_lisa_map_0,
1213                         &hw_lisa_map_regs->dmm_lisa_map_0);
1214         }
1215
1216         /*
1217          * EMIF should be configured only when
1218          * memory is mapped on it. Using emif1_enabled
1219          * and emif2_enabled variables for this.
1220          */
1221         emif1_enabled = 0;
1222         emif2_enabled = 0;
1223         for (i = 0; i < 4; i++) {
1224                 section = __raw_readl(DMM_BASE + i*4);
1225                 valid = (section & EMIF_SDRC_MAP_MASK) >>
1226                         (EMIF_SDRC_MAP_SHIFT);
1227                 if (valid == 3) {
1228                         emif1_enabled = 1;
1229                         emif2_enabled = 1;
1230                         break;
1231                 }
1232
1233                 if (valid == 1)
1234                         emif1_enabled = 1;
1235
1236                 if (valid == 2)
1237                         emif2_enabled = 1;
1238         }
1239 }
1240
1241 static void do_bug0039_workaround(u32 base)
1242 {
1243         u32 val, i, clkctrl;
1244         struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
1245         const struct read_write_regs *bug_00339_regs;
1246         u32 iterations;
1247         u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
1248         u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
1249
1250         if (is_dra7xx())
1251                 phy_status_base++;
1252
1253         bug_00339_regs = get_bug_regs(&iterations);
1254
1255         /* Put EMIF in to idle */
1256         clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
1257         __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
1258
1259         /* Copy the phy status registers in to phy ctrl shadow registers */
1260         for (i = 0; i < iterations; i++) {
1261                 val = __raw_readl(phy_status_base +
1262                                   bug_00339_regs[i].read_reg - 1);
1263
1264                 __raw_writel(val, phy_ctrl_base +
1265                              ((bug_00339_regs[i].write_reg - 1) << 1));
1266
1267                 __raw_writel(val, phy_ctrl_base +
1268                              (bug_00339_regs[i].write_reg << 1) - 1);
1269         }
1270
1271         /* Disable leveling */
1272         writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
1273
1274         __raw_writel(clkctrl,  (*prcm)->cm_memif_clkstctrl);
1275 }
1276
1277 /*
1278  * SDRAM initialization:
1279  * SDRAM initialization has two parts:
1280  * 1. Configuring the SDRAM device
1281  * 2. Update the AC timings related parameters in the EMIF module
1282  * (1) should be done only once and should not be done while we are
1283  * running from SDRAM.
1284  * (2) can and should be done more than once if OPP changes.
1285  * Particularly, this may be needed when we boot without SPL and
1286  * and using Configuration Header(CH). ROM code supports only at 50% OPP
1287  * at boot (low power boot). So u-boot has to switch to OPP100 and update
1288  * the frequency. So,
1289  * Doing (1) and (2) makes sense - first time initialization
1290  * Doing (2) and not (1) makes sense - OPP change (when using CH)
1291  * Doing (1) and not (2) doen't make sense
1292  * See do_sdram_init() for the details
1293  */
1294 void sdram_init(void)
1295 {
1296         u32 in_sdram, size_prog, size_detect;
1297         u32 sdram_type = emif_sdram_type();
1298
1299         debug(">>sdram_init()\n");
1300
1301         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1302                 return;
1303
1304         in_sdram = running_from_sdram();
1305         debug("in_sdram = %d\n", in_sdram);
1306
1307         if (!in_sdram) {
1308                 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
1309                         bypass_dpll((*prcm)->cm_clkmode_dpll_core);
1310                 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
1311                         writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
1312         }
1313
1314         if (!in_sdram)
1315                 dmm_init(DMM_BASE);
1316
1317         if (emif1_enabled)
1318                 do_sdram_init(EMIF1_BASE);
1319
1320         if (emif2_enabled)
1321                 do_sdram_init(EMIF2_BASE);
1322
1323         if (!(in_sdram || warm_reset())) {
1324                 if (emif1_enabled)
1325                         emif_post_init_config(EMIF1_BASE);
1326                 if (emif2_enabled)
1327                         emif_post_init_config(EMIF2_BASE);
1328         }
1329
1330         /* for the shadow registers to take effect */
1331         if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
1332                 freq_update_core();
1333
1334         /* Do some testing after the init */
1335         if (!in_sdram) {
1336                 size_prog = omap_sdram_size();
1337                 size_prog = log_2_n_round_down(size_prog);
1338                 size_prog = (1 << size_prog);
1339
1340                 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1341                                                 size_prog);
1342                 /* Compare with the size programmed */
1343                 if (size_detect != size_prog) {
1344                         printf("SDRAM: identified size not same as expected"
1345                                 " size identified: %x expected: %x\n",
1346                                 size_detect,
1347                                 size_prog);
1348                 } else
1349                         debug("get_ram_size() successful");
1350         }
1351
1352         if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
1353             (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
1354                 if (emif1_enabled)
1355                         do_bug0039_workaround(EMIF1_BASE);
1356                 if (emif2_enabled)
1357                         do_bug0039_workaround(EMIF2_BASE);
1358         }
1359
1360         debug("<<sdram_init()\n");
1361 }