arch/arm/cpu/armv7/omap-common/hwinit-common.c

   1 /*
   2  *
   3  * Common functions for OMAP4/5 based boards
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author :
   9  *      Aneesh V        <aneesh@ti.com>
  10  *      Steve Sakoman   <steve@sakoman.com>
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14 #include <common.h>
  15 #include <spl.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <linux/sizes.h>
  18 #include <asm/emif.h>
  19 #include <asm/omap_common.h>
  20 #include <linux/compiler.h>
  21 #include <asm/system.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
  26 {
  27         int i;
  28         struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
  29
  30         for (i = 0; i < size; i++, pad++)
  31                 writew(pad->val, base + pad->offset);
  32 }
  33
  34 static void set_mux_conf_regs(void)
  35 {
  36         switch (omap_hw_init_context()) {
  37         case OMAP_INIT_CONTEXT_SPL:
  38                 set_muxconf_regs_essential();
  39                 break;
  40         case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
  41                 break;
  42         case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
  43         case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
  44                 set_muxconf_regs_essential();
  45                 break;
  46         }
  47 }
  48
  49 u32 cortex_rev(void)
  50 {
  51
  52         unsigned int rev;
  53
  54         /* Read Main ID Register (MIDR) */
  55         asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
  56
  57         return rev;
  58 }
  59
  60 static void omap_rev_string(void)
  61 {
  62         u32 omap_rev = omap_revision();
  63         u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
  64         u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
  65         u32 major_rev = (omap_rev & 0x00000F00) >> 8;
  66         u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
  67
  68         if (soc_variant)
  69                 printf("OMAP");
  70         else
  71                 printf("DRA");
  72         printf("%x ES%x.%x\n", omap_variant, major_rev,
  73                minor_rev);
  74 }
  75
  76 #ifdef CONFIG_SPL_BUILD
  77 void spl_display_print(void)
  78 {
  79         omap_rev_string();
  80 }
  81 #endif
  82
  83 void __weak srcomp_enable(void)
  84 {
  85 }
  86
  87 #ifdef CONFIG_ARCH_CPU_INIT
  88 /*
  89  * SOC specific cpu init
  90  */
  91 int arch_cpu_init(void)
  92 {
  93         save_omap_boot_params();
  94         return 0;
  95 }
  96 #endif /* CONFIG_ARCH_CPU_INIT */
  97
  98 /*
  99  * Routine: s_init
 100  * Description: Does early system init of watchdog, muxing,  andclocks
 101  * Watchdog disable is done always. For the rest what gets done
 102  * depends on the boot mode in which this function is executed
 103  *   1. s_init of SPL running from SRAM
 104  *   2. s_init of U-Boot running from FLASH
 105  *   3. s_init of U-Boot loaded to SDRAM by SPL
 106  *   4. s_init of U-Boot loaded to SDRAM by ROM code using the
 107  *      Configuration Header feature
 108  * Please have a look at the respective functions to see what gets
 109  * done in each of these cases
 110  * This function is called with SRAM stack.
 111  */
 112 void s_init(void)
 113 {
 114         /*
 115          * Save the boot parameters passed from romcode.
 116          * We cannot delay the saving further than this,
 117          * to prevent overwrites.
 118          */
 119 #ifdef CONFIG_SPL_BUILD
 120         save_omap_boot_params();
 121 #endif
 122         init_omap_revision();
 123         hw_data_init();
 124
 125 #ifdef CONFIG_SPL_BUILD
 126         if (warm_reset() &&
 127             (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0)))
 128                 force_emif_self_refresh();
 129 #endif
 130         watchdog_init();
 131         set_mux_conf_regs();
 132 #ifdef CONFIG_SPL_BUILD
 133         srcomp_enable();
 134         setup_clocks_for_console();
 135
 136         gd = &gdata;
 137
 138         preloader_console_init();
 139         do_io_settings();
 140 #endif
 141         prcm_init();
 142 #ifdef CONFIG_SPL_BUILD
 143 #ifdef CONFIG_BOARD_EARLY_INIT_F
 144         board_early_init_f();
 145 #endif
 146         /* For regular u-boot sdram_init() is called from dram_init() */
 147         sdram_init();
 148 #endif
 149 }
 150
 151 /*
 152  * Routine: wait_for_command_complete
 153  * Description: Wait for posting to finish on watchdog
 154  */
 155 void wait_for_command_complete(struct watchdog *wd_base)
 156 {
 157         int pending = 1;
 158         do {
 159                 pending = readl(&wd_base->wwps);
 160         } while (pending);
 161 }
 162
 163 /*
 164  * Routine: watchdog_init
 165  * Description: Shut down watch dogs
 166  */
 167 void watchdog_init(void)
 168 {
 169         struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
 170
 171         writel(WD_UNLOCK1, &wd2_base->wspr);
 172         wait_for_command_complete(wd2_base);
 173         writel(WD_UNLOCK2, &wd2_base->wspr);
 174 }
 175
 176
 177 /*
 178  * This function finds the SDRAM size available in the system
 179  * based on DMM section configurations
 180  * This is needed because the size of memory installed may be
 181  * different on different versions of the board
 182  */
 183 u32 omap_sdram_size(void)
 184 {
 185         u32 section, i, valid;
 186         u64 sdram_start = 0, sdram_end = 0, addr,
 187             size, total_size = 0, trap_size = 0, trap_start = 0;
 188
 189         for (i = 0; i < 4; i++) {
 190                 section = __raw_readl(DMM_BASE + i*4);
 191                 valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
 192                         (EMIF_SDRC_ADDRSPC_SHIFT);
 193                 addr = section & EMIF_SYS_ADDR_MASK;
 194
 195                 /* See if the address is valid */
 196                 if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) &&
 197                     (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) {
 198                         size = ((section & EMIF_SYS_SIZE_MASK) >>
 199                                    EMIF_SYS_SIZE_SHIFT);
 200                         size = 1 << size;
 201                         size *= SZ_16M;
 202
 203                         if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
 204                                 if (!sdram_start || (addr < sdram_start))
 205                                         sdram_start = addr;
 206                                 if (!sdram_end || ((addr + size) > sdram_end))
 207                                         sdram_end = addr + size;
 208                         } else {
 209                                 trap_size = size;
 210                                 trap_start = addr;
 211                         }
 212                 }
 213         }
 214
 215         if ((trap_start >= sdram_start) && (trap_start < sdram_end))
 216                 total_size = (sdram_end - sdram_start) - (trap_size);
 217         else
 218                 total_size = sdram_end - sdram_start;
 219
 220         return total_size;
 221 }
 222
 223
 224 /*
 225  * Routine: dram_init
 226  * Description: sets uboots idea of sdram size
 227  */
 228 int dram_init(void)
 229 {
 230         sdram_init();
 231         gd->ram_size = omap_sdram_size();
 232         return 0;
 233 }
 234
 235 /*
 236  * Print board information
 237  */
 238 int checkboard(void)
 239 {
 240         puts(sysinfo.board_string);
 241         return 0;
 242 }
 243
 244 /*
 245  *  get_device_type(): tell if GP/HS/EMU/TST
 246  */
 247 u32 get_device_type(void)
 248 {
 249         return (readl((*ctrl)->control_status) &
 250                                       (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
 251 }
 252
 253 #if defined(CONFIG_DISPLAY_CPUINFO)
 254 /*
 255  * Print CPU information
 256  */
 257 int print_cpuinfo(void)
 258 {
 259         puts("CPU  : ");
 260         omap_rev_string();
 261
 262         return 0;
 263 }
 264 #endif