arch/arm/cpu/armv7/omap3/am35x_musb.c

   1 /*
   2  * This file configures the internal USB PHY in AM35X.
   3  *
   4  * Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com>
   5  *
   6  * Based on omap_phy_internal.c code from Linux by
   7  * Hema HK <hemahk@ti.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/am35x_def.h>
  15
  16 void am35x_musb_reset(void)
  17 {
  18         /* Reset the musb interface */
  19         clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
  20                         0, USBOTGSS_SW_RST);
  21         clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
  22                         USBOTGSS_SW_RST, 0);
  23 }
  24
  25 void am35x_musb_phy_power(u8 on)
  26 {
  27         unsigned long start = get_timer(0);
  28
  29         if (on) {
  30                 /*
  31                  * Start the on-chip PHY and its PLL.
  32                  */
  33                 clrsetbits_le32(&am35x_scm_general_regs->devconf2,
  34                                 CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN,
  35                                 CONF2_PHY_PLLON);
  36
  37                 debug("Waiting for PHY clock good...\n");
  38                 while (!(readl(&am35x_scm_general_regs->devconf2)
  39                                 & CONF2_PHYCLKGD)) {
  40
  41                         if (get_timer(start) > CONFIG_SYS_HZ / 10) {
  42                                 printf("musb PHY clock good timed out\n");
  43                                 break;
  44                         }
  45                 }
  46         } else {
  47                 /*
  48                  * Power down the on-chip PHY.
  49                  */
  50                 clrsetbits_le32(&am35x_scm_general_regs->devconf2,
  51                                 CONF2_PHY_PLLON,
  52                                 CONF2_PHYPWRDN | CONF2_OTGPWRDN);
  53         }
  54 }
  55
  56 void am35x_musb_clear_irq(void)
  57 {
  58         clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
  59                         0, USBOTGSS_INT_CLR);
  60         readl(&am35x_scm_general_regs->lvl_intr_clr);
  61 }