arch/arm/cpu/armv7/omap5/sdram.c

   1 /*
   2  * Timing and Organization details of the ddr device parts used in OMAP5
   3  * EVM
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  * Sricharan R <r.sricharan@ti.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <asm/emif.h>
  15 #include <asm/arch/sys_proto.h>
  16
  17 /*
  18  * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
  19  * EVM. Since the parts used and geometry are identical for
  20  * evm for a given OMAP5 revision, this information is kept
  21  * here instead of being in board directory. However the key functions
  22  * exported are weakly linked so that they can be over-ridden in the board
  23  * directory if there is a OMAP5 board in the future that uses a different
  24  * memory device or geometry.
  25  *
  26  * For any new board with different memory devices over-ride one or more
  27  * of the following functions as per the CONFIG flags you intend to enable:
  28  * - emif_get_reg_dump()
  29  * - emif_get_dmm_regs()
  30  * - emif_get_device_details()
  31  * - emif_get_device_timings()
  32  */
  33
  34 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  35 const struct emif_regs emif_regs_532_mhz_2cs = {
  36         .sdram_config_init              = 0x80800EBA,
  37         .sdram_config                   = 0x808022BA,
  38         .ref_ctrl                       = 0x0000081A,
  39         .sdram_tim1                     = 0x772F6873,
  40         .sdram_tim2                     = 0x304a129a,
  41         .sdram_tim3                     = 0x02f7e45f,
  42         .read_idle_ctrl                 = 0x00050000,
  43         .zq_config                      = 0x000b3215,
  44         .temp_alert_config              = 0x08000a05,
  45         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  46         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  47         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  48         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  49         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  50         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  51         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  52 };
  53
  54 const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
  55         .sdram_config_init              = 0x80800EBA,
  56         .sdram_config                   = 0x808022BA,
  57         .ref_ctrl                       = 0x0000081A,
  58         .sdram_tim1                     = 0x772F6873,
  59         .sdram_tim2                     = 0x304a129a,
  60         .sdram_tim3                     = 0x02f7e45f,
  61         .read_idle_ctrl                 = 0x00050000,
  62         .zq_config                      = 0x100b3215,
  63         .temp_alert_config              = 0x08000a05,
  64         .emif_ddr_phy_ctlr_1_init       = 0x0E30400d,
  65         .emif_ddr_phy_ctlr_1            = 0x0E30400d,
  66         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  67         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  68         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  69         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  70         .emif_ddr_ext_phy_ctrl_5        = 0xC330CC33,
  71 };
  72
  73 const struct emif_regs emif_regs_266_mhz_2cs = {
  74         .sdram_config_init              = 0x80800EBA,
  75         .sdram_config                   = 0x808022BA,
  76         .ref_ctrl                       = 0x0000040D,
  77         .sdram_tim1                     = 0x2A86B419,
  78         .sdram_tim2                     = 0x1025094A,
  79         .sdram_tim3                     = 0x026BA22F,
  80         .read_idle_ctrl                 = 0x00050000,
  81         .zq_config                      = 0x000b3215,
  82         .temp_alert_config              = 0x08000a05,
  83         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  84         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  85         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  86         .emif_ddr_ext_phy_ctrl_2        = 0x0A414829,
  87         .emif_ddr_ext_phy_ctrl_3        = 0x14829052,
  88         .emif_ddr_ext_phy_ctrl_4        = 0x000520A4,
  89         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  90 };
  91
  92 const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
  93         .sdram_config_init              = 0x61851B32,
  94         .sdram_config                   = 0x61851B32,
  95         .sdram_config2                  = 0x0,
  96         .ref_ctrl                       = 0x00001035,
  97         .sdram_tim1                     = 0xCCCF36B3,
  98         .sdram_tim2                     = 0x308F7FDA,
  99         .sdram_tim3                     = 0x027F88A8,
 100         .read_idle_ctrl                 = 0x00050000,
 101         .zq_config                      = 0x0007190B,
 102         .temp_alert_config              = 0x00000000,
 103         .emif_ddr_phy_ctlr_1_init       = 0x0020420A,
 104         .emif_ddr_phy_ctlr_1            = 0x0024420A,
 105         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 106         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 107         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 108         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 109         .emif_ddr_ext_phy_ctrl_5        = 0x04010040,
 110         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 111         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 112         .emif_rd_wr_lvl_ctl             = 0x00000000,
 113         .emif_rd_wr_exec_thresh         = 0x00000305
 114 };
 115
 116 const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
 117         .sdram_config_init              = 0x61851B32,
 118         .sdram_config                   = 0x61851B32,
 119         .sdram_config2                  = 0x0,
 120         .ref_ctrl                       = 0x00001035,
 121         .sdram_tim1                     = 0xCCCF36B3,
 122         .sdram_tim2                     = 0x308F7FDA,
 123         .sdram_tim3                     = 0x027F88A8,
 124         .read_idle_ctrl                 = 0x00050000,
 125         .zq_config                      = 0x1007190B,
 126         .temp_alert_config              = 0x00000000,
 127         .emif_ddr_phy_ctlr_1_init       = 0x0030400A,
 128         .emif_ddr_phy_ctlr_1            = 0x0034400A,
 129         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 130         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 131         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 132         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 133         .emif_ddr_ext_phy_ctrl_5        = 0x4350D435,
 134         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 135         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 136         .emif_rd_wr_lvl_ctl             = 0x00000000,
 137         .emif_rd_wr_exec_thresh         = 0x40000305
 138 };
 139
 140 const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
 141         .sdram_config_init              = 0x61851ab2,
 142         .sdram_config                   = 0x61851ab2,
 143         .sdram_config2                  = 0x08000000,
 144         .ref_ctrl                       = 0x00001035,
 145         .sdram_tim1                     = 0xCCCF36B3,
 146         .sdram_tim2                     = 0x308F7FDA,
 147         .sdram_tim3                     = 0x027F88A8,
 148         .read_idle_ctrl                 = 0x00050000,
 149         .zq_config                      = 0x0007190B,
 150         .temp_alert_config              = 0x00000000,
 151         .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
 152         .emif_ddr_phy_ctlr_1            = 0x0024400A,
 153         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 154         .emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
 155         .emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
 156         .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 157         .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 158         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 159         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 160         .emif_rd_wr_lvl_ctl             = 0x00000000,
 161         .emif_rd_wr_exec_thresh         = 0x00000305
 162 };
 163
 164 const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
 165         .sdram_config_init              = 0x61851B32,
 166         .sdram_config                   = 0x61851B32,
 167         .sdram_config2                  = 0x08000000,
 168         .ref_ctrl                       = 0x00001035,
 169         .sdram_tim1                     = 0xCCCF36B3,
 170         .sdram_tim2                     = 0x308F7FDA,
 171         .sdram_tim3                     = 0x027F88A8,
 172         .read_idle_ctrl                 = 0x00050000,
 173         .zq_config                      = 0x0007190B,
 174         .temp_alert_config              = 0x00000000,
 175         .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
 176         .emif_ddr_phy_ctlr_1            = 0x0024400A,
 177         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 178         .emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
 179         .emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
 180         .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 181         .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 182         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 183         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 184         .emif_rd_wr_lvl_ctl             = 0x00000000,
 185         .emif_rd_wr_exec_thresh         = 0x00000305
 186 };
 187
 188 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
 189         .dmm_lisa_map_0 = 0x0,
 190         .dmm_lisa_map_1 = 0x0,
 191         .dmm_lisa_map_2 = 0x80740300,
 192         .dmm_lisa_map_3 = 0xFF020100,
 193         .is_ma_present  = 0x1
 194 };
 195
 196 /*
 197  * DRA752 EVM board has 1.5 GB of memory
 198  * EMIF1 --> 2Gb * 2 =  512MB
 199  * EMIF2 --> 2Gb * 4 =  1GB
 200  * so mapping 1GB interleaved and 512MB non-interleaved
 201  */
 202 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
 203         .dmm_lisa_map_0 = 0x0,
 204         .dmm_lisa_map_1 = 0x80640300,
 205         .dmm_lisa_map_2 = 0xC0500220,
 206         .dmm_lisa_map_3 = 0xFF020100,
 207         .is_ma_present  = 0x1
 208 };
 209
 210 /*
 211  * DRA752 EVM EMIF1 ONLY CONFIGURATION
 212  */
 213 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
 214         .dmm_lisa_map_0 = 0x0,
 215         .dmm_lisa_map_1 = 0x0,
 216         .dmm_lisa_map_2 = 0x80500100,
 217         .dmm_lisa_map_3 = 0xFF020100,
 218         .is_ma_present  = 0x1
 219 };
 220
 221 /*
 222  * DRA752 EVM EMIF2 ONLY CONFIGURATION
 223  */
 224 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 225         .dmm_lisa_map_0 = 0x0,
 226         .dmm_lisa_map_1 = 0x0,
 227         .dmm_lisa_map_2 = 0x80600200,
 228         .dmm_lisa_map_3 = 0xFF020100,
 229         .is_ma_present  = 0x1
 230 };
 231
 232 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 233 {
 234         switch (omap_revision()) {
 235         case OMAP5430_ES1_0:
 236                 *regs = &emif_regs_532_mhz_2cs;
 237                 break;
 238         case OMAP5432_ES1_0:
 239                 *regs = &emif_regs_ddr3_532_mhz_1cs;
 240                 break;
 241         case OMAP5430_ES2_0:
 242                 *regs = &emif_regs_532_mhz_2cs_es2;
 243                 break;
 244         case OMAP5432_ES2_0:
 245                 *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
 246                 break;
 247         case DRA752_ES1_0:
 248                 switch (emif_nr) {
 249                 case 1:
 250                         *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
 251                         break;
 252                 case 2:
 253                         *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
 254                         break;
 255                 }
 256                 break;
 257         default:
 258                 *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
 259         }
 260 }
 261
 262 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 263         __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 264
 265 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 266                                                 **dmm_lisa_regs)
 267 {
 268         switch (omap_revision()) {
 269         case OMAP5430_ES1_0:
 270         case OMAP5430_ES2_0:
 271         case OMAP5432_ES1_0:
 272         case OMAP5432_ES2_0:
 273                 *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 274                 break;
 275         case DRA752_ES1_0:
 276         default:
 277                 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
 278         }
 279
 280 }
 281
 282 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 283         __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 284 #else
 285
 286 static const struct lpddr2_device_details dev_4G_S4_details = {
 287         .type           = LPDDR2_TYPE_S4,
 288         .density        = LPDDR2_DENSITY_4Gb,
 289         .io_width       = LPDDR2_IO_WIDTH_32,
 290         .manufacturer   = LPDDR2_MANUFACTURER_SAMSUNG
 291 };
 292
 293 static void emif_get_device_details_sdp(u32 emif_nr,
 294                 struct lpddr2_device_details *cs0_device_details,
 295                 struct lpddr2_device_details *cs1_device_details)
 296 {
 297         /* EMIF1 & EMIF2 have identical configuration */
 298         *cs0_device_details = dev_4G_S4_details;
 299         *cs1_device_details = dev_4G_S4_details;
 300 }
 301
 302 void emif_get_device_details(u32 emif_nr,
 303                 struct lpddr2_device_details *cs0_device_details,
 304                 struct lpddr2_device_details *cs1_device_details)
 305         __attribute__((weak, alias("emif_get_device_details_sdp")));
 306
 307 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 308
 309 const u32 ext_phy_ctrl_const_base[] = {
 310         0x01004010,
 311         0x00001004,
 312         0x04010040,
 313         0x01004010,
 314         0x00001004,
 315         0x00000000,
 316         0x00000000,
 317         0x00000000,
 318         0x80080080,
 319         0x00800800,
 320         0x08102040,
 321         0x00000001,
 322         0x540A8150,
 323         0xA81502a0,
 324         0x002A0540,
 325         0x00000000,
 326         0x00000000,
 327         0x00000000,
 328         0x00000077,
 329         0x0
 330 };
 331
 332 const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
 333         0x01004010,
 334         0x00001004,
 335         0x04010040,
 336         0x01004010,
 337         0x00001004,
 338         0x00000000,
 339         0x00000000,
 340         0x00000000,
 341         0x80080080,
 342         0x00800800,
 343         0x08102040,
 344         0x00000002,
 345         0x0,
 346         0x0,
 347         0x0,
 348         0x00000000,
 349         0x00000000,
 350         0x00000000,
 351         0x00000057,
 352         0x0
 353 };
 354
 355 const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 356         0x50D4350D,
 357         0x00000D43,
 358         0x04010040,
 359         0x01004010,
 360         0x00001004,
 361         0x00000000,
 362         0x00000000,
 363         0x00000000,
 364         0x80080080,
 365         0x00800800,
 366         0x08102040,
 367         0x00000002,
 368         0x00000000,
 369         0x00000000,
 370         0x00000000,
 371         0x00000000,
 372         0x00000000,
 373         0x00000000,
 374         0x00000057,
 375         0x0
 376 };
 377
 378 const u32
 379 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
 380         0x00B000B0,
 381         0x00400040,
 382         0x00400040,
 383         0x00400040,
 384         0x00400040,
 385         0x00400040,
 386         0x00800080,
 387         0x00800080,
 388         0x00800080,
 389         0x00800080,
 390         0x00800080,
 391         0x00600060,
 392         0x00600060,
 393         0x00600060,
 394         0x00600060,
 395         0x00600060,
 396         0x00800080,
 397         0x00800080,
 398         0x40010080,
 399         0x08102040,
 400         0x0,
 401         0x0,
 402         0x0,
 403         0x0,
 404         0x0
 405 };
 406
 407 const u32
 408 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
 409         0x00BB00BB,
 410         0x00440044,
 411         0x00440044,
 412         0x00440044,
 413         0x00440044,
 414         0x00440044,
 415         0x007F007F,
 416         0x007F007F,
 417         0x007F007F,
 418         0x007F007F,
 419         0x007F007F,
 420         0x00600060,
 421         0x00600060,
 422         0x00600060,
 423         0x00600060,
 424         0x00600060,
 425         0x0,
 426         0x00600020,
 427         0x40010080,
 428         0x08102040,
 429         0x0,
 430         0x0,
 431         0x0,
 432         0x0,
 433         0x0
 434 };
 435
 436 const struct lpddr2_mr_regs mr_regs = {
 437         .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
 438         .mr2    = 0x6,
 439         .mr3    = 0x1,
 440         .mr10   = MR10_ZQ_ZQINIT,
 441         .mr16   = MR16_REF_FULL_ARRAY
 442 };
 443
 444 static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
 445                                              const u32 **regs,
 446                                              u32 *size)
 447 {
 448         switch (omap_revision()) {
 449         case OMAP5430_ES1_0:
 450         case OMAP5430_ES2_0:
 451                 *regs = ext_phy_ctrl_const_base;
 452                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base);
 453                 break;
 454         case OMAP5432_ES1_0:
 455                 *regs = ddr3_ext_phy_ctrl_const_base_es1;
 456                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
 457                 break;
 458         case OMAP5432_ES2_0:
 459                 *regs = ddr3_ext_phy_ctrl_const_base_es2;
 460                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 461                 break;
 462         case DRA752_ES1_0:
 463                 if (emif_nr == 1) {
 464                         *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
 465                         *size =
 466                         ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
 467                 } else {
 468                         *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
 469                         *size =
 470                         ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
 471                 }
 472                 break;
 473         default:
 474                 *regs = ddr3_ext_phy_ctrl_const_base_es2;
 475                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 476
 477         }
 478 }
 479
 480 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 481 {
 482         *regs = &mr_regs;
 483 }
 484
 485 void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 486 {
 487         u32 *ext_phy_ctrl_base = 0;
 488         u32 *emif_ext_phy_ctrl_base = 0;
 489         u32 emif_nr;
 490         const u32 *ext_phy_ctrl_const_regs;
 491         u32 i = 0;
 492         u32 size;
 493
 494         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 495
 496         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 497
 498         ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
 499         emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
 500
 501         /* Configure external phy control timing registers */
 502         for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
 503                 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
 504                 /* Update shadow registers */
 505                 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
 506         }
 507
 508         /*
 509          * external phy 6-24 registers do not change with
 510          * ddr frequency
 511          */
 512         emif_get_ext_phy_ctrl_const_regs(emif_nr,
 513                                          &ext_phy_ctrl_const_regs, &size);
 514
 515         for (i = 0; i < size; i++) {
 516                 writel(ext_phy_ctrl_const_regs[i],
 517                        emif_ext_phy_ctrl_base++);
 518                 /* Update shadow registers */
 519                 writel(ext_phy_ctrl_const_regs[i],
 520                        emif_ext_phy_ctrl_base++);
 521         }
 522 }
 523
 524 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 525 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
 526         .max_freq       = 532000000,
 527         .RL             = 8,
 528         .tRPab          = 21,
 529         .tRCD           = 18,
 530         .tWR            = 15,
 531         .tRASmin        = 42,
 532         .tRRD           = 10,
 533         .tWTRx2         = 15,
 534         .tXSR           = 140,
 535         .tXPx2          = 15,
 536         .tRFCab         = 130,
 537         .tRTPx2         = 15,
 538         .tCKE           = 3,
 539         .tCKESR         = 15,
 540         .tZQCS          = 90,
 541         .tZQCL          = 360,
 542         .tZQINIT        = 1000,
 543         .tDQSCKMAXx2    = 11,
 544         .tRASmax        = 70,
 545         .tFAW           = 50
 546 };
 547
 548 static const struct lpddr2_min_tck min_tck = {
 549         .tRL            = 3,
 550         .tRP_AB         = 3,
 551         .tRCD           = 3,
 552         .tWR            = 3,
 553         .tRAS_MIN       = 3,
 554         .tRRD           = 2,
 555         .tWTR           = 2,
 556         .tXP            = 2,
 557         .tRTP           = 2,
 558         .tCKE           = 3,
 559         .tCKESR         = 3,
 560         .tFAW           = 8
 561 };
 562
 563 static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
 564         &timings_jedec_532_mhz
 565 };
 566
 567 static const struct lpddr2_device_timings dev_4G_S4_timings = {
 568         .ac_timings     = ac_timings,
 569         .min_tck        = &min_tck,
 570 };
 571
 572 /*
 573  * List of status registers to be controlled back to control registers
 574  * after initial leveling
 575  * readreg, writereg
 576  */
 577 const struct read_write_regs omap5_bug_00339_regs[] = {
 578         { 8,  5 },
 579         { 9,  6 },
 580         { 10, 7 },
 581         { 14, 8 },
 582         { 15, 9 },
 583         { 16, 10 },
 584         { 11, 2 },
 585         { 12, 3 },
 586         { 13, 4 },
 587         { 17, 11 },
 588         { 18, 12 },
 589         { 19, 13 },
 590 };
 591
 592 const struct read_write_regs dra_bug_00339_regs[] = {
 593         { 7,  7 },
 594         { 8,  8 },
 595         { 9,  9 },
 596         { 10, 10 },
 597         { 11, 11 },
 598         { 12, 2 },
 599         { 13, 3 },
 600         { 14, 4 },
 601         { 15, 5 },
 602         { 16, 6 },
 603         { 17, 12 },
 604         { 18, 13 },
 605         { 19, 14 },
 606         { 20, 15 },
 607         { 21, 16 },
 608         { 22, 17 },
 609         { 23, 18 },
 610         { 24, 19 },
 611         { 25, 20 },
 612         { 26, 21}
 613 };
 614
 615 const struct read_write_regs *get_bug_regs(u32 *iterations)
 616 {
 617         const struct read_write_regs *bug_00339_regs_ptr = NULL;
 618
 619         switch (omap_revision()) {
 620         case OMAP5430_ES1_0:
 621         case OMAP5430_ES2_0:
 622         case OMAP5432_ES1_0:
 623         case OMAP5432_ES2_0:
 624                 bug_00339_regs_ptr = omap5_bug_00339_regs;
 625                 *iterations = sizeof(omap5_bug_00339_regs)/
 626                              sizeof(omap5_bug_00339_regs[0]);
 627                 break;
 628         case DRA752_ES1_0:
 629                 bug_00339_regs_ptr = dra_bug_00339_regs;
 630                 *iterations = sizeof(dra_bug_00339_regs)/
 631                              sizeof(dra_bug_00339_regs[0]);
 632                 break;
 633         default:
 634                 printf("\n Error: UnKnown SOC");
 635         }
 636
 637         return bug_00339_regs_ptr;
 638 }
 639
 640 void emif_get_device_timings_sdp(u32 emif_nr,
 641                 const struct lpddr2_device_timings **cs0_device_timings,
 642                 const struct lpddr2_device_timings **cs1_device_timings)
 643 {
 644         /* Identical devices on EMIF1 & EMIF2 */
 645         *cs0_device_timings = &dev_4G_S4_timings;
 646         *cs1_device_timings = &dev_4G_S4_timings;
 647 }
 648
 649 void emif_get_device_timings(u32 emif_nr,
 650                 const struct lpddr2_device_timings **cs0_device_timings,
 651                 const struct lpddr2_device_timings **cs1_device_timings)
 652         __attribute__((weak, alias("emif_get_device_timings_sdp")));
 653
 654 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */