arch/arm/cpu/armv7/omap5/sdram.c

   1 /*
   2  * Timing and Organization details of the ddr device parts used in OMAP5
   3  * EVM
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  * Sricharan R <r.sricharan@ti.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <asm/emif.h>
  15 #include <asm/arch/sys_proto.h>
  16
  17 /*
  18  * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
  19  * EVM. Since the parts used and geometry are identical for
  20  * evm for a given OMAP5 revision, this information is kept
  21  * here instead of being in board directory. However the key functions
  22  * exported are weakly linked so that they can be over-ridden in the board
  23  * directory if there is a OMAP5 board in the future that uses a different
  24  * memory device or geometry.
  25  *
  26  * For any new board with different memory devices over-ride one or more
  27  * of the following functions as per the CONFIG flags you intend to enable:
  28  * - emif_get_reg_dump()
  29  * - emif_get_dmm_regs()
  30  * - emif_get_device_details()
  31  * - emif_get_device_timings()
  32  */
  33
  34 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  35 const struct emif_regs emif_regs_532_mhz_2cs = {
  36         .sdram_config_init              = 0x80800EBA,
  37         .sdram_config                   = 0x808022BA,
  38         .ref_ctrl                       = 0x0000081A,
  39         .sdram_tim1                     = 0x772F6873,
  40         .sdram_tim2                     = 0x304a129a,
  41         .sdram_tim3                     = 0x02f7e45f,
  42         .read_idle_ctrl                 = 0x00050000,
  43         .zq_config                      = 0x000b3215,
  44         .temp_alert_config              = 0x08000a05,
  45         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  46         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  47         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  48         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  49         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  50         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  51         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  52 };
  53
  54 const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
  55         .sdram_config_init              = 0x80800EBA,
  56         .sdram_config                   = 0x808022BA,
  57         .ref_ctrl                       = 0x0000081A,
  58         .sdram_tim1                     = 0x772F6873,
  59         .sdram_tim2                     = 0x304a129a,
  60         .sdram_tim3                     = 0x02f7e45f,
  61         .read_idle_ctrl                 = 0x00050000,
  62         .zq_config                      = 0x100b3215,
  63         .temp_alert_config              = 0x08000a05,
  64         .emif_ddr_phy_ctlr_1_init       = 0x0E30400d,
  65         .emif_ddr_phy_ctlr_1            = 0x0E30400d,
  66         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  67         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  68         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  69         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  70         .emif_ddr_ext_phy_ctrl_5        = 0xC330CC33,
  71 };
  72
  73 const struct emif_regs emif_regs_266_mhz_2cs = {
  74         .sdram_config_init              = 0x80800EBA,
  75         .sdram_config                   = 0x808022BA,
  76         .ref_ctrl                       = 0x0000040D,
  77         .sdram_tim1                     = 0x2A86B419,
  78         .sdram_tim2                     = 0x1025094A,
  79         .sdram_tim3                     = 0x026BA22F,
  80         .read_idle_ctrl                 = 0x00050000,
  81         .zq_config                      = 0x000b3215,
  82         .temp_alert_config              = 0x08000a05,
  83         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  84         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  85         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  86         .emif_ddr_ext_phy_ctrl_2        = 0x0A414829,
  87         .emif_ddr_ext_phy_ctrl_3        = 0x14829052,
  88         .emif_ddr_ext_phy_ctrl_4        = 0x000520A4,
  89         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  90 };
  91
  92 const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
  93         .sdram_config_init              = 0x61851B32,
  94         .sdram_config                   = 0x61851B32,
  95         .sdram_config2                  = 0x0,
  96         .ref_ctrl                       = 0x00001035,
  97         .sdram_tim1                     = 0xCCCF36B3,
  98         .sdram_tim2                     = 0x308F7FDA,
  99         .sdram_tim3                     = 0x027F88A8,
 100         .read_idle_ctrl                 = 0x00050000,
 101         .zq_config                      = 0x0007190B,
 102         .temp_alert_config              = 0x00000000,
 103         .emif_ddr_phy_ctlr_1_init       = 0x0020420A,
 104         .emif_ddr_phy_ctlr_1            = 0x0024420A,
 105         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 106         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 107         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 108         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 109         .emif_ddr_ext_phy_ctrl_5        = 0x04010040,
 110         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 111         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 112         .emif_rd_wr_lvl_ctl             = 0x00000000,
 113         .emif_rd_wr_exec_thresh         = 0x00000305
 114 };
 115
 116 const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
 117         .sdram_config_init              = 0x61851B32,
 118         .sdram_config                   = 0x61851B32,
 119         .sdram_config2                  = 0x0,
 120         .ref_ctrl                       = 0x00001035,
 121         .sdram_tim1                     = 0xCCCF36B3,
 122         .sdram_tim2                     = 0x308F7FDA,
 123         .sdram_tim3                     = 0x027F88A8,
 124         .read_idle_ctrl                 = 0x00050000,
 125         .zq_config                      = 0x1007190B,
 126         .temp_alert_config              = 0x00000000,
 127         .emif_ddr_phy_ctlr_1_init       = 0x0030400A,
 128         .emif_ddr_phy_ctlr_1            = 0x0034400A,
 129         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 130         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 131         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 132         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 133         .emif_ddr_ext_phy_ctrl_5        = 0x4350D435,
 134         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 135         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 136         .emif_rd_wr_lvl_ctl             = 0x00000000,
 137         .emif_rd_wr_exec_thresh         = 0x40000305
 138 };
 139
 140 const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
 141         .sdram_config_init              = 0x61851ab2,
 142         .sdram_config                   = 0x61851ab2,
 143         .sdram_config2                  = 0x08000000,
 144         .ref_ctrl                       = 0x00001035,
 145         .sdram_tim1                     = 0xCCCF36B3,
 146         .sdram_tim2                     = 0x308F7FDA,
 147         .sdram_tim3                     = 0x027F88A8,
 148         .read_idle_ctrl                 = 0x00050000,
 149         .zq_config                      = 0x0007190B,
 150         .temp_alert_config              = 0x00000000,
 151         .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
 152         .emif_ddr_phy_ctlr_1            = 0x0024400A,
 153         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 154         .emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
 155         .emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
 156         .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 157         .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 158         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 159         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 160         .emif_rd_wr_lvl_ctl             = 0x00000000,
 161         .emif_rd_wr_exec_thresh         = 0x00000305
 162 };
 163
 164 const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
 165         .sdram_config_init              = 0x61851B32,
 166         .sdram_config                   = 0x61851B32,
 167         .sdram_config2                  = 0x08000000,
 168         .ref_ctrl                       = 0x00001035,
 169         .sdram_tim1                     = 0xCCCF36B3,
 170         .sdram_tim2                     = 0x308F7FDA,
 171         .sdram_tim3                     = 0x027F88A8,
 172         .read_idle_ctrl                 = 0x00050000,
 173         .zq_config                      = 0x0007190B,
 174         .temp_alert_config              = 0x00000000,
 175         .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
 176         .emif_ddr_phy_ctlr_1            = 0x0024400A,
 177         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 178         .emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
 179         .emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
 180         .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 181         .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 182         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 183         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 184         .emif_rd_wr_lvl_ctl             = 0x00000000,
 185         .emif_rd_wr_exec_thresh         = 0x00000305
 186 };
 187
 188 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
 189         .dmm_lisa_map_0 = 0x0,
 190         .dmm_lisa_map_1 = 0x0,
 191         .dmm_lisa_map_2 = 0x80740300,
 192         .dmm_lisa_map_3 = 0xFF020100,
 193         .is_ma_present  = 0x1
 194 };
 195
 196 /*
 197  * DRA752 EVM board has 1.5 GB of memory
 198  * EMIF1 --> 2Gb * 2 =  512MB
 199  * EMIF2 --> 2Gb * 4 =  1GB
 200  * so mapping 1GB interleaved and 512MB non-interleaved
 201  */
 202 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
 203         .dmm_lisa_map_0 = 0x0,
 204         .dmm_lisa_map_1 = 0x80640300,
 205         .dmm_lisa_map_2 = 0xC0500220,
 206         .dmm_lisa_map_3 = 0xFF020100,
 207         .is_ma_present  = 0x1
 208 };
 209
 210 /*
 211  * DRA752 EVM EMIF1 ONLY CONFIGURATION
 212  */
 213 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
 214         .dmm_lisa_map_0 = 0x0,
 215         .dmm_lisa_map_1 = 0x0,
 216         .dmm_lisa_map_2 = 0x80500100,
 217         .dmm_lisa_map_3 = 0xFF020100,
 218         .is_ma_present  = 0x1
 219 };
 220
 221 /*
 222  * DRA752 EVM EMIF2 ONLY CONFIGURATION
 223  */
 224 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 225         .dmm_lisa_map_0 = 0x0,
 226         .dmm_lisa_map_1 = 0x0,
 227         .dmm_lisa_map_2 = 0x80600200,
 228         .dmm_lisa_map_3 = 0xFF020100,
 229         .is_ma_present  = 0x1
 230 };
 231
 232 /*
 233  * DRA722 EVM EMIF1 CONFIGURATION
 234  */
 235 const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
 236         .dmm_lisa_map_0 = 0x0,
 237         .dmm_lisa_map_1 = 0x0,
 238         .dmm_lisa_map_2 = 0x80600100,
 239         .dmm_lisa_map_3 = 0xFF020100,
 240         .is_ma_present  = 0x1
 241 };
 242
 243 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 244 {
 245         switch (omap_revision()) {
 246         case OMAP5430_ES1_0:
 247                 *regs = &emif_regs_532_mhz_2cs;
 248                 break;
 249         case OMAP5432_ES1_0:
 250                 *regs = &emif_regs_ddr3_532_mhz_1cs;
 251                 break;
 252         case OMAP5430_ES2_0:
 253                 *regs = &emif_regs_532_mhz_2cs_es2;
 254                 break;
 255         case OMAP5432_ES2_0:
 256                 *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
 257                 break;
 258         case DRA752_ES1_0:
 259         case DRA752_ES1_1:
 260                 switch (emif_nr) {
 261                 case 1:
 262                         *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
 263                         break;
 264                 case 2:
 265                         *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
 266                         break;
 267                 }
 268                 break;
 269         case DRA722_ES1_0:
 270         default:
 271                 *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
 272         }
 273 }
 274
 275 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 276         __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 277
 278 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 279                                                 **dmm_lisa_regs)
 280 {
 281         switch (omap_revision()) {
 282         case OMAP5430_ES1_0:
 283         case OMAP5430_ES2_0:
 284         case OMAP5432_ES1_0:
 285         case OMAP5432_ES2_0:
 286                 *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 287                 break;
 288         case DRA752_ES1_0:
 289         case DRA752_ES1_1:
 290                 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
 291                 break;
 292         case DRA722_ES1_0:
 293         default:
 294                 *dmm_lisa_regs = &lisa_map_2G_x_2;
 295         }
 296
 297 }
 298
 299 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 300         __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 301 #else
 302
 303 static const struct lpddr2_device_details dev_4G_S4_details = {
 304         .type           = LPDDR2_TYPE_S4,
 305         .density        = LPDDR2_DENSITY_4Gb,
 306         .io_width       = LPDDR2_IO_WIDTH_32,
 307         .manufacturer   = LPDDR2_MANUFACTURER_SAMSUNG
 308 };
 309
 310 static void emif_get_device_details_sdp(u32 emif_nr,
 311                 struct lpddr2_device_details *cs0_device_details,
 312                 struct lpddr2_device_details *cs1_device_details)
 313 {
 314         /* EMIF1 & EMIF2 have identical configuration */
 315         *cs0_device_details = dev_4G_S4_details;
 316         *cs1_device_details = dev_4G_S4_details;
 317 }
 318
 319 void emif_get_device_details(u32 emif_nr,
 320                 struct lpddr2_device_details *cs0_device_details,
 321                 struct lpddr2_device_details *cs1_device_details)
 322         __attribute__((weak, alias("emif_get_device_details_sdp")));
 323
 324 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 325
 326 const u32 ext_phy_ctrl_const_base[] = {
 327         0x01004010,
 328         0x00001004,
 329         0x04010040,
 330         0x01004010,
 331         0x00001004,
 332         0x00000000,
 333         0x00000000,
 334         0x00000000,
 335         0x80080080,
 336         0x00800800,
 337         0x08102040,
 338         0x00000001,
 339         0x540A8150,
 340         0xA81502a0,
 341         0x002A0540,
 342         0x00000000,
 343         0x00000000,
 344         0x00000000,
 345         0x00000077,
 346         0x0
 347 };
 348
 349 const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
 350         0x01004010,
 351         0x00001004,
 352         0x04010040,
 353         0x01004010,
 354         0x00001004,
 355         0x00000000,
 356         0x00000000,
 357         0x00000000,
 358         0x80080080,
 359         0x00800800,
 360         0x08102040,
 361         0x00000002,
 362         0x0,
 363         0x0,
 364         0x0,
 365         0x00000000,
 366         0x00000000,
 367         0x00000000,
 368         0x00000057,
 369         0x0
 370 };
 371
 372 const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 373         0x50D4350D,
 374         0x00000D43,
 375         0x04010040,
 376         0x01004010,
 377         0x00001004,
 378         0x00000000,
 379         0x00000000,
 380         0x00000000,
 381         0x80080080,
 382         0x00800800,
 383         0x08102040,
 384         0x00000002,
 385         0x00000000,
 386         0x00000000,
 387         0x00000000,
 388         0x00000000,
 389         0x00000000,
 390         0x00000000,
 391         0x00000057,
 392         0x0
 393 };
 394
 395 const u32
 396 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
 397         0x00B000B0,
 398         0x00400040,
 399         0x00400040,
 400         0x00400040,
 401         0x00400040,
 402         0x00400040,
 403         0x00800080,
 404         0x00800080,
 405         0x00800080,
 406         0x00800080,
 407         0x00800080,
 408         0x00600060,
 409         0x00600060,
 410         0x00600060,
 411         0x00600060,
 412         0x00600060,
 413         0x00800080,
 414         0x00800080,
 415         0x40010080,
 416         0x08102040,
 417         0x0,
 418         0x0,
 419         0x0,
 420         0x0,
 421         0x0
 422 };
 423
 424 const u32
 425 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
 426         0x00BB00BB,
 427         0x00440044,
 428         0x00440044,
 429         0x00440044,
 430         0x00440044,
 431         0x00440044,
 432         0x007F007F,
 433         0x007F007F,
 434         0x007F007F,
 435         0x007F007F,
 436         0x007F007F,
 437         0x00600060,
 438         0x00600060,
 439         0x00600060,
 440         0x00600060,
 441         0x00600060,
 442         0x0,
 443         0x00600020,
 444         0x40010080,
 445         0x08102040,
 446         0x0,
 447         0x0,
 448         0x0,
 449         0x0,
 450         0x0
 451 };
 452
 453 const struct lpddr2_mr_regs mr_regs = {
 454         .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
 455         .mr2    = 0x6,
 456         .mr3    = 0x1,
 457         .mr10   = MR10_ZQ_ZQINIT,
 458         .mr16   = MR16_REF_FULL_ARRAY
 459 };
 460
 461 static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
 462                                              const u32 **regs,
 463                                              u32 *size)
 464 {
 465         switch (omap_revision()) {
 466         case OMAP5430_ES1_0:
 467         case OMAP5430_ES2_0:
 468                 *regs = ext_phy_ctrl_const_base;
 469                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base);
 470                 break;
 471         case OMAP5432_ES1_0:
 472                 *regs = ddr3_ext_phy_ctrl_const_base_es1;
 473                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
 474                 break;
 475         case OMAP5432_ES2_0:
 476                 *regs = ddr3_ext_phy_ctrl_const_base_es2;
 477                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 478                 break;
 479         case DRA752_ES1_0:
 480         case DRA752_ES1_1:
 481         case DRA722_ES1_0:
 482                 if (emif_nr == 1) {
 483                         *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
 484                         *size =
 485                         ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
 486                 } else {
 487                         *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
 488                         *size =
 489                         ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
 490                 }
 491                 break;
 492         default:
 493                 *regs = ddr3_ext_phy_ctrl_const_base_es2;
 494                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 495
 496         }
 497 }
 498
 499 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 500 {
 501         *regs = &mr_regs;
 502 }
 503
 504 void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 505 {
 506         u32 *ext_phy_ctrl_base = 0;
 507         u32 *emif_ext_phy_ctrl_base = 0;
 508         u32 emif_nr;
 509         const u32 *ext_phy_ctrl_const_regs;
 510         u32 i = 0;
 511         u32 size;
 512
 513         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 514
 515         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 516
 517         ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
 518         emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
 519
 520         /* Configure external phy control timing registers */
 521         for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
 522                 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
 523                 /* Update shadow registers */
 524                 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
 525         }
 526
 527         /*
 528          * external phy 6-24 registers do not change with
 529          * ddr frequency
 530          */
 531         emif_get_ext_phy_ctrl_const_regs(emif_nr,
 532                                          &ext_phy_ctrl_const_regs, &size);
 533
 534         for (i = 0; i < size; i++) {
 535                 writel(ext_phy_ctrl_const_regs[i],
 536                        emif_ext_phy_ctrl_base++);
 537                 /* Update shadow registers */
 538                 writel(ext_phy_ctrl_const_regs[i],
 539                        emif_ext_phy_ctrl_base++);
 540         }
 541 }
 542
 543 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 544 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
 545         .max_freq       = 532000000,
 546         .RL             = 8,
 547         .tRPab          = 21,
 548         .tRCD           = 18,
 549         .tWR            = 15,
 550         .tRASmin        = 42,
 551         .tRRD           = 10,
 552         .tWTRx2         = 15,
 553         .tXSR           = 140,
 554         .tXPx2          = 15,
 555         .tRFCab         = 130,
 556         .tRTPx2         = 15,
 557         .tCKE           = 3,
 558         .tCKESR         = 15,
 559         .tZQCS          = 90,
 560         .tZQCL          = 360,
 561         .tZQINIT        = 1000,
 562         .tDQSCKMAXx2    = 11,
 563         .tRASmax        = 70,
 564         .tFAW           = 50
 565 };
 566
 567 static const struct lpddr2_min_tck min_tck = {
 568         .tRL            = 3,
 569         .tRP_AB         = 3,
 570         .tRCD           = 3,
 571         .tWR            = 3,
 572         .tRAS_MIN       = 3,
 573         .tRRD           = 2,
 574         .tWTR           = 2,
 575         .tXP            = 2,
 576         .tRTP           = 2,
 577         .tCKE           = 3,
 578         .tCKESR         = 3,
 579         .tFAW           = 8
 580 };
 581
 582 static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
 583         &timings_jedec_532_mhz
 584 };
 585
 586 static const struct lpddr2_device_timings dev_4G_S4_timings = {
 587         .ac_timings     = ac_timings,
 588         .min_tck        = &min_tck,
 589 };
 590
 591 /*
 592  * List of status registers to be controlled back to control registers
 593  * after initial leveling
 594  * readreg, writereg
 595  */
 596 const struct read_write_regs omap5_bug_00339_regs[] = {
 597         { 8,  5 },
 598         { 9,  6 },
 599         { 10, 7 },
 600         { 14, 8 },
 601         { 15, 9 },
 602         { 16, 10 },
 603         { 11, 2 },
 604         { 12, 3 },
 605         { 13, 4 },
 606         { 17, 11 },
 607         { 18, 12 },
 608         { 19, 13 },
 609 };
 610
 611 const struct read_write_regs dra_bug_00339_regs[] = {
 612         { 7,  7 },
 613         { 8,  8 },
 614         { 9,  9 },
 615         { 10, 10 },
 616         { 11, 11 },
 617         { 12, 2 },
 618         { 13, 3 },
 619         { 14, 4 },
 620         { 15, 5 },
 621         { 16, 6 },
 622         { 17, 12 },
 623         { 18, 13 },
 624         { 19, 14 },
 625         { 20, 15 },
 626         { 21, 16 },
 627         { 22, 17 },
 628         { 23, 18 },
 629         { 24, 19 },
 630         { 25, 20 },
 631         { 26, 21}
 632 };
 633
 634 const struct read_write_regs *get_bug_regs(u32 *iterations)
 635 {
 636         const struct read_write_regs *bug_00339_regs_ptr = NULL;
 637
 638         switch (omap_revision()) {
 639         case OMAP5430_ES1_0:
 640         case OMAP5430_ES2_0:
 641         case OMAP5432_ES1_0:
 642         case OMAP5432_ES2_0:
 643                 bug_00339_regs_ptr = omap5_bug_00339_regs;
 644                 *iterations = sizeof(omap5_bug_00339_regs)/
 645                              sizeof(omap5_bug_00339_regs[0]);
 646                 break;
 647         case DRA752_ES1_0:
 648         case DRA752_ES1_1:
 649         case DRA722_ES1_0:
 650                 bug_00339_regs_ptr = dra_bug_00339_regs;
 651                 *iterations = sizeof(dra_bug_00339_regs)/
 652                              sizeof(dra_bug_00339_regs[0]);
 653                 break;
 654         default:
 655                 printf("\n Error: UnKnown SOC");
 656         }
 657
 658         return bug_00339_regs_ptr;
 659 }
 660
 661 void emif_get_device_timings_sdp(u32 emif_nr,
 662                 const struct lpddr2_device_timings **cs0_device_timings,
 663                 const struct lpddr2_device_timings **cs1_device_timings)
 664 {
 665         /* Identical devices on EMIF1 & EMIF2 */
 666         *cs0_device_timings = &dev_4G_S4_timings;
 667         *cs1_device_timings = &dev_4G_S4_timings;
 668 }
 669
 670 void emif_get_device_timings(u32 emif_nr,
 671                 const struct lpddr2_device_timings **cs0_device_timings,
 672                 const struct lpddr2_device_timings **cs1_device_timings)
 673         __attribute__((weak, alias("emif_get_device_timings_sdp")));
 674
 675 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */