arch/arm/cpu/armv7/sunxi/clock_sun4i.c

   1 /*
   2  * sun4i, sun5i and sun7i specific clock code
   3  *
   4  * (C) Copyright 2007-2012
   5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   6  * Tom Cubie <tangliang@allwinnertech.com>
   7  *
   8  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/gpio.h>
  17 #include <asm/arch/sys_proto.h>
  18
  19 #ifdef CONFIG_SPL_BUILD
  20 void clock_init_safe(void)
  21 {
  22         struct sunxi_ccm_reg * const ccm =
  23                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  24
  25         /* Set safe defaults until PMU is configured */
  26         writel(AXI_DIV_1 << AXI_DIV_SHIFT |
  27                AHB_DIV_2 << AHB_DIV_SHIFT |
  28                APB0_DIV_1 << APB0_DIV_SHIFT |
  29                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
  30                &ccm->cpu_ahb_apb0_cfg);
  31         writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
  32         sdelay(200);
  33         writel(AXI_DIV_1 << AXI_DIV_SHIFT |
  34                AHB_DIV_2 << AHB_DIV_SHIFT |
  35                APB0_DIV_1 << APB0_DIV_SHIFT |
  36                CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
  37                &ccm->cpu_ahb_apb0_cfg);
  38 #ifdef CONFIG_SUN7I
  39         setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
  40 #endif
  41         writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
  42 }
  43 #endif
  44
  45 void clock_init_uart(void)
  46 {
  47         struct sunxi_ccm_reg *const ccm =
  48                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  49
  50         /* uart clock source is apb1 */
  51         writel(APB1_CLK_SRC_OSC24M|
  52                APB1_CLK_RATE_N_1|
  53                APB1_CLK_RATE_M(1),
  54                &ccm->apb1_clk_div_cfg);
  55
  56         /* open the clock for uart */
  57         setbits_le32(&ccm->apb1_gate,
  58                 CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1));
  59 }
  60
  61 int clock_twi_onoff(int port, int state)
  62 {
  63         struct sunxi_ccm_reg *const ccm =
  64                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  65
  66         if (port > 2)
  67                 return -1;
  68
  69         /* set the apb clock gate for twi */
  70         if (state)
  71                 setbits_le32(&ccm->apb1_gate,
  72                              CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
  73         else
  74                 clrbits_le32(&ccm->apb1_gate,
  75                              CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
  76
  77         return 0;
  78 }
  79
  80 #ifdef CONFIG_SPL_BUILD
  81 #define PLL1_CFG(N, K, M, P)    ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \
  82                                   0 << CCM_PLL1_CFG_VCO_RST_SHIFT |  \
  83                                   8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \
  84                                   0 << CCM_PLL1_CFG_PLL4_EXCH_SHIFT | \
  85                                  16 << CCM_PLL1_CFG_BIAS_CUR_SHIFT | \
  86                                  (P)<< CCM_PLL1_CFG_DIVP_SHIFT | \
  87                                   2 << CCM_PLL1_CFG_LCK_TMR_SHIFT | \
  88                                  (N)<< CCM_PLL1_CFG_FACTOR_N_SHIFT | \
  89                                  (K)<< CCM_PLL1_CFG_FACTOR_K_SHIFT | \
  90                                   0 << CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT | \
  91                                   0 << CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT | \
  92                                  (M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT)
  93
  94 static struct {
  95         u32 pll1_cfg;
  96         unsigned int freq;
  97 } pll1_para[] = {
  98         /* This array must be ordered by frequency. */
  99         { PLL1_CFG(16, 0, 0, 0), 384000000 },
 100         { PLL1_CFG(16, 1, 0, 0), 768000000 },
 101         { PLL1_CFG(20, 1, 0, 0), 960000000 },
 102         { PLL1_CFG(21, 1, 0, 0), 1008000000},
 103         { PLL1_CFG(22, 1, 0, 0), 1056000000},
 104         { PLL1_CFG(23, 1, 0, 0), 1104000000},
 105         { PLL1_CFG(24, 1, 0, 0), 1152000000},
 106         { PLL1_CFG(25, 1, 0, 0), 1200000000},
 107         { PLL1_CFG(26, 1, 0, 0), 1248000000},
 108         { PLL1_CFG(27, 1, 0, 0), 1296000000},
 109         { PLL1_CFG(28, 1, 0, 0), 1344000000},
 110         { PLL1_CFG(29, 1, 0, 0), 1392000000},
 111         { PLL1_CFG(30, 1, 0, 0), 1440000000},
 112         { PLL1_CFG(31, 1, 0, 0), 1488000000},
 113         /* Final catchall entry */
 114         { PLL1_CFG(31, 1, 0, 0), ~0},
 115 };
 116
 117 void clock_set_pll1(unsigned int hz)
 118 {
 119         int i = 0;
 120         int axi, ahb, apb0;
 121         struct sunxi_ccm_reg * const ccm =
 122                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 123
 124         /* Find target frequency */
 125         while (pll1_para[i].freq < hz)
 126                 i++;
 127
 128         hz = pll1_para[i].freq;
 129
 130         /* Calculate system clock divisors */
 131         axi = DIV_ROUND_UP(hz, 432000000);      /* Max 450MHz */
 132         ahb = DIV_ROUND_UP(hz/axi, 204000000);  /* Max 250MHz */
 133         apb0 = 2;                               /* Max 150MHz */
 134
 135         printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0);
 136
 137         /* Map divisors to register values */
 138         axi = axi - 1;
 139         if (ahb > 4)
 140                 ahb = 3;
 141         else if (ahb > 2)
 142                 ahb = 2;
 143         else if (ahb > 1)
 144                 ahb = 1;
 145         else
 146                 ahb = 0;
 147
 148         apb0 = apb0 - 1;
 149
 150         /* Switch to 24MHz clock while changing PLL1 */
 151         writel(AXI_DIV_1 << AXI_DIV_SHIFT |
 152                AHB_DIV_2 << AHB_DIV_SHIFT |
 153                APB0_DIV_1 << APB0_DIV_SHIFT |
 154                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
 155                &ccm->cpu_ahb_apb0_cfg);
 156         sdelay(20);
 157
 158         /* Configure sys clock divisors */
 159         writel(axi << AXI_DIV_SHIFT |
 160                ahb << AHB_DIV_SHIFT |
 161                apb0 << APB0_DIV_SHIFT |
 162                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
 163                &ccm->cpu_ahb_apb0_cfg);
 164
 165         /* Configure PLL1 at the desired frequency */
 166         writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg);
 167         sdelay(200);
 168
 169         /* Switch CPU to PLL1 */
 170         writel(axi << AXI_DIV_SHIFT |
 171                ahb << AHB_DIV_SHIFT |
 172                apb0 << APB0_DIV_SHIFT |
 173                CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 174                &ccm->cpu_ahb_apb0_cfg);
 175         sdelay(20);
 176 }
 177 #endif
 178
 179 unsigned int clock_get_pll6(void)
 180 {
 181         struct sunxi_ccm_reg *const ccm =
 182                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 183         uint32_t rval = readl(&ccm->pll6_cfg);
 184         int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
 185         int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
 186         return 24000000 * n * k / 2;
 187 }