arch/arm/dts/ls1021a.dtsi

   1 /*
   2  * Freescale ls1021a SOC common device tree source
   3  *
   4  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include "skeleton.dtsi"
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 / {
  13         compatible = "fsl,ls1021a";
  14         interrupt-parent = <&gic>;
  15
  16         aliases {
  17                 serial0 = &lpuart0;
  18                 serial1 = &lpuart1;
  19                 serial2 = &lpuart2;
  20                 serial3 = &lpuart3;
  21                 serial4 = &lpuart4;
  22                 serial5 = &lpuart5;
  23                 sysclk = &sysclk;
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu@f00 {
  31                         compatible = "arm,cortex-a7";
  32                         device_type = "cpu";
  33                         reg = <0xf00>;
  34                         clocks = <&cluster1_clk>;
  35                 };
  36
  37                 cpu@f01 {
  38                         compatible = "arm,cortex-a7";
  39                         device_type = "cpu";
  40                         reg = <0xf01>;
  41                         clocks = <&cluster1_clk>;
  42                 };
  43         };
  44
  45         timer {
  46                 compatible = "arm,armv7-timer";
  47                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  48                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  51         };
  52
  53         pmu {
  54                 compatible = "arm,cortex-a7-pmu";
  55                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  56                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
  57         };
  58
  59         soc {
  60                 compatible = "simple-bus";
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 device_type = "soc";
  64                 interrupt-parent = <&gic>;
  65                 ranges;
  66
  67                 gic: interrupt-controller@1400000 {
  68                         compatible = "arm,cortex-a7-gic";
  69                         #interrupt-cells = <3>;
  70                         interrupt-controller;
  71                         reg = <0x1401000 0x1000>,
  72                               <0x1402000 0x1000>,
  73                               <0x1404000 0x2000>,
  74                               <0x1406000 0x2000>;
  75                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  76
  77                 };
  78
  79                 ifc: ifc@1530000 {
  80                         compatible = "fsl,ifc", "simple-bus";
  81                         reg = <0x1530000 0x10000>;
  82                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  83                 };
  84
  85                 dcfg: dcfg@1ee0000 {
  86                         compatible = "fsl,ls1021a-dcfg", "syscon";
  87                         reg = <0x1ee0000 0x10000>;
  88                         big-endian;
  89                 };
  90
  91                 esdhc: esdhc@1560000 {
  92                         compatible = "fsl,esdhc";
  93                         reg = <0x1560000 0x10000>;
  94                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
  95                         clock-frequency = <0>;
  96                         voltage-ranges = <1800 1800 3300 3300>;
  97                         sdhci,auto-cmd12;
  98                         big-endian;
  99                         bus-width = <4>;
 100                         status = "disabled";
 101                 };
 102
 103                 scfg: scfg@1570000 {
 104                         compatible = "fsl,ls1021a-scfg", "syscon";
 105                         reg = <0x1570000 0x10000>;
 106                         big-endian;
 107                 };
 108
 109                 clockgen: clocking@1ee1000 {
 110                         #address-cells = <1>;
 111                         #size-cells = <1>;
 112                         ranges = <0x0 0x1ee1000 0x10000>;
 113
 114                         sysclk: sysclk {
 115                                 compatible = "fixed-clock";
 116                                 #clock-cells = <0>;
 117                                 clock-output-names = "sysclk";
 118                         };
 119
 120                         cga_pll1: pll@800 {
 121                                 compatible = "fsl,qoriq-core-pll-2.0";
 122                                 #clock-cells = <1>;
 123                                 reg = <0x800 0x10>;
 124                                 clocks = <&sysclk>;
 125                                 clock-output-names = "cga-pll1", "cga-pll1-div2",
 126                                                      "cga-pll1-div4";
 127                         };
 128
 129                         platform_clk: pll@c00 {
 130                                 compatible = "fsl,qoriq-core-pll-2.0";
 131                                 #clock-cells = <1>;
 132                                 reg = <0xc00 0x10>;
 133                                 clocks = <&sysclk>;
 134                                 clock-output-names = "platform-clk", "platform-clk-div2";
 135                         };
 136
 137                         cluster1_clk: clk0c0@0 {
 138                                 compatible = "fsl,qoriq-core-mux-2.0";
 139                                 #clock-cells = <0>;
 140                                 reg = <0x0 0x10>;
 141                                 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
 142                                 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
 143                                 clock-output-names = "cluster1-clk";
 144                         };
 145                 };
 146
 147                 dspi0: dspi@2100000 {
 148                         compatible = "fsl,vf610-dspi";
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                         reg = <0x2100000 0x10000>;
 152                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 153                         clock-names = "dspi";
 154                         clocks = <&platform_clk 1>;
 155                         num-cs = <6>;
 156                         big-endian;
 157                         status = "disabled";
 158                 };
 159
 160                 dspi1: dspi@2110000 {
 161                         compatible = "fsl,vf610-dspi";
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164                         reg = <0x2110000 0x10000>;
 165                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 166                         clock-names = "dspi";
 167                         clocks = <&platform_clk 1>;
 168                         num-cs = <6>;
 169                         big-endian;
 170                         status = "disabled";
 171                 };
 172
 173                 qspi: quadspi@1550000 {
 174                         compatible = "fsl,vf610-qspi";
 175                         #address-cells = <1>;
 176                         #size-cells = <0>;
 177                         reg = <0x1550000 0x10000>,
 178                                 <0x40000000 0x4000000>;
 179                         num-cs = <2>;
 180                         big-endian;
 181                         status = "disabled";
 182                 };
 183
 184                 i2c0: i2c@2180000 {
 185                         compatible = "fsl,vf610-i2c";
 186                         #address-cells = <1>;
 187                         #size-cells = <0>;
 188                         reg = <0x2180000 0x10000>;
 189                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 190                         clock-names = "i2c";
 191                         clocks = <&platform_clk 1>;
 192                         status = "disabled";
 193                 };
 194
 195                 i2c1: i2c@2190000 {
 196                         compatible = "fsl,vf610-i2c";
 197                         #address-cells = <1>;
 198                         #size-cells = <0>;
 199                         reg = <0x2190000 0x10000>;
 200                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 201                         clock-names = "i2c";
 202                         clocks = <&platform_clk 1>;
 203                         status = "disabled";
 204                 };
 205
 206                 i2c2: i2c@21a0000 {
 207                         compatible = "fsl,vf610-i2c";
 208                         #address-cells = <1>;
 209                         #size-cells = <0>;
 210                         reg = <0x21a0000 0x10000>;
 211                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 212                         clock-names = "i2c";
 213                         clocks = <&platform_clk 1>;
 214                         status = "disabled";
 215                 };
 216
 217                 uart0: serial@21c0500 {
 218                         compatible = "fsl,16550-FIFO64", "ns16550a";
 219                         reg = <0x21c0500 0x100>;
 220                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 221                         clock-frequency = <0>;
 222                         fifo-size = <15>;
 223                         status = "disabled";
 224                 };
 225
 226                 uart1: serial@21c0600 {
 227                         compatible = "fsl,16550-FIFO64", "ns16550a";
 228                         reg = <0x21c0600 0x100>;
 229                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 230                         clock-frequency = <0>;
 231                         fifo-size = <15>;
 232                         status = "disabled";
 233                 };
 234
 235                 uart2: serial@21d0500 {
 236                         compatible = "fsl,16550-FIFO64", "ns16550a";
 237                         reg = <0x21d0500 0x100>;
 238                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 239                         clock-frequency = <0>;
 240                         fifo-size = <15>;
 241                         status = "disabled";
 242                 };
 243
 244                 uart3: serial@21d0600 {
 245                         compatible = "fsl,16550-FIFO64", "ns16550a";
 246                         reg = <0x21d0600 0x100>;
 247                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 248                         clock-frequency = <0>;
 249                         fifo-size = <15>;
 250                         status = "disabled";
 251                 };
 252
 253                 lpuart0: serial@2950000 {
 254                         compatible = "fsl,ls1021a-lpuart";
 255                         reg = <0x2950000 0x1000>;
 256                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 257                         clocks = <&sysclk>;
 258                         clock-names = "ipg";
 259                         status = "disabled";
 260                 };
 261
 262                 lpuart1: serial@2960000 {
 263                         compatible = "fsl,ls1021a-lpuart";
 264                         reg = <0x2960000 0x1000>;
 265                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 266                         clocks = <&platform_clk 1>;
 267                         clock-names = "ipg";
 268                         status = "disabled";
 269                 };
 270
 271                 lpuart2: serial@2970000 {
 272                         compatible = "fsl,ls1021a-lpuart";
 273                         reg = <0x2970000 0x1000>;
 274                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 275                         clocks = <&platform_clk 1>;
 276                         clock-names = "ipg";
 277                         status = "disabled";
 278                 };
 279
 280                 lpuart3: serial@2980000 {
 281                         compatible = "fsl,ls1021a-lpuart";
 282                         reg = <0x2980000 0x1000>;
 283                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 284                         clocks = <&platform_clk 1>;
 285                         clock-names = "ipg";
 286                         status = "disabled";
 287                 };
 288
 289                 lpuart4: serial@2990000 {
 290                         compatible = "fsl,ls1021a-lpuart";
 291                         reg = <0x2990000 0x1000>;
 292                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 293                         clocks = <&platform_clk 1>;
 294                         clock-names = "ipg";
 295                         status = "disabled";
 296                 };
 297
 298                 lpuart5: serial@29a0000 {
 299                         compatible = "fsl,ls1021a-lpuart";
 300                         reg = <0x29a0000 0x1000>;
 301                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 302                         clocks = <&platform_clk 1>;
 303                         clock-names = "ipg";
 304                         status = "disabled";
 305                 };
 306
 307                 wdog0: watchdog@2ad0000 {
 308                         compatible = "fsl,imx21-wdt";
 309                         reg = <0x2ad0000 0x10000>;
 310                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 311                         clocks = <&platform_clk 1>;
 312                         clock-names = "wdog-en";
 313                         big-endian;
 314                 };
 315
 316                 sai1: sai@2b50000 {
 317                         compatible = "fsl,vf610-sai";
 318                         reg = <0x2b50000 0x10000>;
 319                         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 320                         clocks = <&platform_clk 1>;
 321                         clock-names = "sai";
 322                         dma-names = "tx", "rx";
 323                         dmas = <&edma0 1 47>,
 324                                <&edma0 1 46>;
 325                         big-endian;
 326                         status = "disabled";
 327                 };
 328
 329                 sai2: sai@2b60000 {
 330                         compatible = "fsl,vf610-sai";
 331                         reg = <0x2b60000 0x10000>;
 332                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 333                         clocks = <&platform_clk 1>;
 334                         clock-names = "sai";
 335                         dma-names = "tx", "rx";
 336                         dmas = <&edma0 1 45>,
 337                                <&edma0 1 44>;
 338                         big-endian;
 339                         status = "disabled";
 340                 };
 341
 342                 edma0: edma@2c00000 {
 343                         #dma-cells = <2>;
 344                         compatible = "fsl,vf610-edma";
 345                         reg = <0x2c00000 0x10000>,
 346                               <0x2c10000 0x10000>,
 347                               <0x2c20000 0x10000>;
 348                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 349                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 350                         interrupt-names = "edma-tx", "edma-err";
 351                         dma-channels = <32>;
 352                         big-endian;
 353                         clock-names = "dmamux0", "dmamux1";
 354                         clocks = <&platform_clk 1>,
 355                                  <&platform_clk 1>;
 356                 };
 357
 358                 mdio0: mdio@2d24000 {
 359                         compatible = "gianfar";
 360                         device_type = "mdio";
 361                         #address-cells = <1>;
 362                         #size-cells = <0>;
 363                         reg = <0x2d24000 0x4000>;
 364                 };
 365
 366                 usb@8600000 {
 367                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 368                         reg = <0x8600000 0x1000>;
 369                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 370                         dr_mode = "host";
 371                         phy_type = "ulpi";
 372                 };
 373
 374                 usb3@3100000 {
 375                         compatible = "snps,dwc3";
 376                         reg = <0x3100000 0x10000>;
 377                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 378                         dr_mode = "host";
 379                 };
 380         };
 381 };